MOS-PUFFERSCHALTUNG

HALBLEITERSCHALTUNG MIT SPEICHER UND PULSTREIBERSCHALTUNG.

Voltage comparitors

A voltage comparitor or level detector comprises a differential amplifier the input terminals of which are formed by the gates of two IGFET's Q1, Q2 which have different threshold voltages due to the use of differently doped semiconductor material for their gate electrodes. This structure provides a stable input offset for the amplifier which is used as a reference. The input voltage and a reference level are applied to the input terminals and the output of the amplifier is determined by the difference between the input p.d. and the input offset. The values of the source currents I1, I2 may be adjusted to provide temperature compensation. In an alternative arrangement the input transistors Q1, Q2 are arranged in a common source configuration with constant current drain supplies. The arrangement may be used as a battery voltage level detector by applying the battery voltage (via a potential divider) to one input and a fixed level (e.g. VDD or VSS) to the other input. Circuits incorporating ...

Circuit for reducing noise sensitivity in logic circuits

A voltage regulator circuit for reducing the noise sensitivity of digital logic circuits by controlling the voltage amplitude range of the clock signal. The circuit includes sensing means connected to the clock input for determining the range of the voltage amplitude of the input clock signal, a regulator circuit connected to the sensing circuit for limiting the voltage swing of the clock signal, and a clock output connected to the regulator circuit for supplying an output clock signal having a predetermined voltage amplitude range.

Level conversion circuit and method

Clamping audio signal paths

INPUT CIRCUITS

... 1524558 Protecting FET circuits HITACHI Ltd 14 Nov 1975 [22 Nov 1974] 47136/75 Heading H3T An IGFET circuit such as an inverter Q1, Q2 having an input transistor Q3 connected to a supply terminal V DD is protected against breakdown due for example to noise on the input by inserting resistors R1, R2 which together with the gate capacitances C, C' of Q1 and Q3 form integrating circuit. A further resistor R3 may be connected between the gate of Q3 and its supply V GG so that any incipient breakdown current in Q3 drops voltage across R3 and is thereby stifled. Clamp diodes may be connected across the resistors R1, R2, R3.

REFERENCE VOLTAGE GENERATOR DEVICE

CLOCK STRETCHER AND LEVEL SHIFTER WITH SMALL COMPONENT COUNT AND LOW POWER CONSUMPTION

A clock stretching circuit (110) mediates between a synchronous bus (112) and a microcontroller (124) which is asleep most of the time to save electrical power. The bus is of a type in which a slow bus device can cause the sender of data to "hold" the data until the slow device is up to speed. The stretching circuit (110) is of small component count and low power consumption, and there is no requirement for a continuous clock. In one embodiment is comprised of a triple analog switch (120, 121, 122) and a very small number of additional components. In another embodiment a dual four-position multiplexer (162, 163) is employed. In still another embodiment, four transistors (210, 212, 213, 215) are used with handful of additional components. A level shifter (220, 221, 222, 223) including an MOSFET and a large-value resistor help to minimize power drain within the bus device. The components can be external to an off- the-shelf microcontroller or can be included in an IC that also contains an ...

Telefonsystem mit Sammelschalteinrichtungen für die Teilnehmerleitungen

REFERENCE TENSION PRODUCER.

REFERENCE TENSION PRODUCER.

REFERENCE TENSION PRODUCER.

Driving circuit

Bidirectional input/output circuit

CIRCUIT A TRANSISTORS A EFFET DE CHAMP UTILISANT UN POTENTIEL DE SUBSTRAT POUR METTRE HORS CIRCUIT DES DISPOSITIFS TRAVAILLANT EN MODE D'APPAUVRISSEMENT

Circuit à transistors à effet de champ. Il utilise trois sources de tension +V, la masse, et une tension dérivée du substrat V SUB négative. Un étage d'entrée connecté entre +V et la masse est composé de T1 et T2 alimenté par des signaux logiques complementaires entre les deux premières tensions. Le couplage capacitif CB permet d'amener le noeud N2 à un potentiel permettant la conduction des transistors T4 et T7 permettant au noeud de sortie de passer du potentiel +V à un potentiel proche de V SUB. Ce potentiel est suffisant pour mettre hors circuit les transistors à effet de champ travaillant en mode d'appauvrissement des étages ultérieurs. Peut être utilisé par exemple dans les mémoires intégrées ou dans les circuits de restauration.

CIRCUIT INVERSEUR D'ENTREE CMOS COMPATIBLE AVEC DES SIGNAUX TTL

L'invention concerne les circuits d'interface TTL-CMOS. Un circuit de décalage de niveau d'entrée CMOS comprend un transistor à canal N de compensation de température 16 dans lequel une résistance R connectée en série avec la région de source est formée par un prolongement d'une région de type P faiblement dopée dans laquelle les régions de source et de drain sont diffusées. On obtient ainsi une variation du courant de drain réalisant une compensation de la température sans exiger une modification importante des processus classiques de fabrication de circuits CMOS. Application à la microélectronique. (CF DESSIN DANS BOPI) ...

BIDIRECTIONAL CONVERTER OF TENSION

CIRCUIT HAS FIELD-EFFECT TRANSISTORS USING a POTENTIAL OF SUBSTRATE TO PUT EXCEPT WORKING CIRCUIT OF the DEVICES IN MODE Of IMPOVERISHMENT

FIELD-EFFECT TRANSISTORS OF THE TYPE HAS ENRICHMENT AND IMPOVERISHMENT, CONNECT IN PARALLEL

STATIC BIPOLAR TO MOS INTERFACE CIRCUIT

ASSEMBLY COMPRISING TWO SWITCHING SYSTEMS

INTEGRATED CIRCUIT

Dispositif de charge pour ligne de bus de communication entre des circuits électroniques à niveaux logiques du type TTL et du type CMOS

Le dispositif 4'' comprend des transistors NMOS M1 et M3 à appauvrissement et un transistor NMOS M2 à enrichissement. Le transistor M1 débite dans la ligne 3 un courant d'intensité définie par l'une ou l'autre de deux lois différentes, sélectionnée par la conduction ou la non-conduction du transistor M2. Celle-ci est déterminée par le niveau logique établi sur la ligne par le circuit TTL 2. Le courant ID S , fourni par le dispositif de charge 4'', relève le niveau de tension de la ligne correspondant à l'état logique " 1 " pour que cet état, établi par le circuit 2, soit compris par le circuit 1. Application à la mise en compatibilité de circuits TTL et CMOS en environnements difficiles générateurs de contraintes de dispersion dans les caractéristiques des circuits intégrés.

LOGIG GATE USING SCHMITT TRIGGER CIRCUIT

... 슈미트 트리거 회로를 이용한 AND 게이트 및 OR 게이트를 개시한다. 슈미트 트리거 회로를 이용한 AND 게이트는 두 개의 입력 신호들을 입력 받아 NAND 논리 연산을 수행하여 제1 출력 신호를 출력하는 NAND 게이트; 및 상기 제1 출력 신호를 인버팅하여 제2 출력 신호를 출력하는 DTMOS 인버터를 포함하고, 상기 제2 출력 신호를 이용하여 상기 NAND 게이트의 문턱전압을 조절할 수 있다. 슈미트 트리거 회로를 이용한 OR 게이트는 두 개의 입력 신호들을 입력 받아 NOR 논리 연산을 수행하여 제1 출력 신호를 출력하는 NOR 게이트; 및 상기 제1 출력 신호를 인버팅하여 제2 출력 신호를 출력하는 DTMOS 인버터를 포함하고, 상기 제2 출력 신호를 이용하여 상기 NOR 게이트의 문턱전압을 조절할 수 있다.

Timing controller for dead - time control

POST DRIVER

A post driver comprises a source follower and a first sub-unit. The source follower comprises an input unit to receive a first voltage from a pad, and an output unit to provide a second voltage. The first sub-unit comprises a first transistor and a second transistor. The first transistor is coupled between the pad and a first power rail, and is configured to operate in a sub-threshold region in response to the second voltage and a first range of the first voltage. The second transistor is coupled in parallel with the first transistor between the pad and the first power rail, and is configured to electrically connect the pad to the first power rail in response to a second range of the first voltage. COPYRIGHT KIPO 2016 (110) Core circuit (120) Level shifter (130) Pre driver (241) Pull-up unit (242) Pull down ...

Interface circuit

The present invention provides an interface circuit including an output buffer, a tracking circuit and a pre-driver, where the output buffer includes at least one P-type transistor and at least one N-type transistor, the at least one P-type transistor is coupled between a supply voltage and a pad, and the at least one N-type transistor is coupled between a ground voltage and the pad. In the operations of the circuit, the tracking circuit is configured to generate a tracking signal according to a voltage level at the pad, and the pre-driver is configured to generate a control signal to control the at least one P-type transistor or the at least one N-type transistor according to the tracking signal.

Semiconductor device

DYNAMIC FEEDBACK-CONTROLLED OUTPUT DRIVER WITH MINIMUM SLEW RATE VARIATION FROM PROCESS, TEMPERATURE AND SUPPLY

In examples, apparatus and methods are provided that mitigate buffer slew rate variations due to variations in output capacitive loading, a fabrication process, a voltage, and/or a temperature (PVT). An exemplary embodiment includes an inverting buffer having an input and an output, as well as an active resistance series-coupled with a capacitor between the input and the output. The resistance of the active resistance varies based on a variation in a fabrication process, a voltage, and/or temperature. The active resistance can be a passgate. In another example, a CMOS inverter's output is coupled to the input of the inverting buffer, and two series-coupled inverting buffers are coupled between the input of the CMOS inverter and the output of the inverting buffer.

HIGH-SPEED GATE DRIVER FOR POWER SWITCHES WITH REDUCED VOLTAGE RINGING

A fast power switch comprises one or more field- effect transistors, such as pull-up and pull-down transistors, that are coupled to a load. Respective driver electronic circuits for each of the field-effect transistors include parallel first and second drivers (X30, X33) with a shared driver output coupled to a gate of the field-effect transistor. The first and second drivers (X30, X33) are operative to switch the shared driver output for the appropriate field-effect transistor in response to a transition (e.g., low-to-high or high-to-low) at a driver input terminal. A control circuit (X35) enables the stronger second driver (X33) in response to a transition at the driver input terminal and subsequently disables the second driver (X33) once a transition threshold at the gate of the field-effect transistor(s) is crossed. The weaker first driver (X30) is sized to damp reactive energy at the load to minimize ringing.

High range positive voltage level shifter using low voltage devices

A voltage level shifter is provided. The voltage level shifter includes an input stage and at least one level shifting stage. The input stage receives an input voltage and a complementary input voltage and receives a first supply voltage and a ground voltage. The input stage outputs one of the first supply voltage and the ground voltage over a first output voltage node and a first complementary output voltage node based on the input voltage and the complementary input voltage. A level shifting stage is coupled to the input stage. The level shifting stage receives the first supply voltage and a second supply voltage and outputs one of the ground voltage, the first supply voltage and the second supply voltage over second and third output voltage nodes and second and third complementary output voltage nodes based on voltages of the first output voltage node and the first complementary output voltage node.

Fast voltage level shifter circuit

A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate.

Decoder structure for a folded logic array

This specification describes a decoder for use in a programmable logic array (PLA) of the type having opposite ends of input lines of the array connected to outputs of different decoders. Instead of using the outputs of two two-bit decoders to drive four input lines, as was previously done, four one-bit decoders are used to drive the four input lines. This arrangement permits the one-bit decoders with minor modifications to be used to perform four one-bit decodes of four input signals, two two-bit decodes on two sets of two input signals on either side of the array and one two-bit decode on two input signals that are on opposite sides of the array.

Output circuit capable of being connected to another circuit having transistors of any conduction type

An integrated circuit having a signal terminal 13 and a reference terminal 14, an output transistor Q4 connected across these terminals with its gate or base connected to the output of exclusive OR gate 12, and an internal circuit 110 with its input port connected to the signal terminal and its output terminal connected to one of the inputs of the OR gate. The other OR-gate input is connected to the reference terminal. By applying the proper reference voltage to the reference terminal, the signal terminal can operate as an I/O terminal with another integrated circuit of the same or of different conductivity type.

Method for interconnecting CMOS chip types

A variable voltage driver circuit produces an output swing off of a single voltage power supply which is logically configurable to allow interconnection of CMOS chips of varying technologies and power supplies. First a voltage requirement for a destination chip is identified to which a driver chip is to be coupled, and the voltage requirement for the driver chip is identified. The variable voltage driver circuit is activated to produce a variable voltage output swing off of a single voltage power supply meeting the voltage requirements of the driver chip. The driver has data input, and level selection inputs and pins which select and enable the driver independent of the output level state that the driver is in. The driver has predriver stage having a data input and a first and a second driver output level input for determining the voltage level at the output, and having control circuits for setting output states at the output stage to a supply level, intermediate voltage level, and a disabled ...

Multi-bootstrap driver circuit

Plural bootstrap capacitors are coupled to an output stage of a MOSFET driver. A conventional bootstrap driver is preceded by one or more additional bootstrap stages. Each one includes a capacitor, a tri state inverter and a delay section. When the output stage is off all capacitors are discharged. To turn the output stage on, all capacitors, including the output gate capacitance, are charged in parallel. Then each capacitor in turn is caused to pump its charge into the gate of the output stage, with the last capacitor pumping the output stage gate voltage to a level well in excess of the applied power supply voltage.

MOS Input circuit with selectable stabilized trip voltage

Disclosed is an integrated buffer circuit having a selectable stabilized trip voltage. The circuit includes an input stage and a reference stage. Each of these stages includes an MOS field effect transistor, a substantially constant resistance device coupling the drain of the input transistor to a bias source, and a device having a resistance that is variable in response to control signals coupling the source of the input transistor to another bias source. The reference stage is biased in the linear region at the selectable trip voltage. A signal generated at the drain of the transistor in the reference stage is connected to all of the variable resistance devices as the control signal. This signal varies the variable resistance in such a way as to compensate for threshold voltage variations in the transistor of the input stage and thus stabilize the selected trip voltage of the input stage.

Universal sink/source I/O module for industrial controller

An I/O module for an industrial controller provides single terminal outputs that may either sink or source current. This capability is provided through the use of dedicated sourcing and sinking transistors connected to the terminal and controlled by lockout logic ensuring activation of only the appropriate transistor in the correct phasing for sinking or sourcing operation modes.

Level shifting circuit and method

A level shifting circuit includes a shift circuit configured to output first and second voltage signals according to level signals, and an input circuit configured to carry out inversion and delay operations on input level signals to obtain first, second, third, and fourth level signals. Rising edge of the first level signal is earlier than falling edge of the second level signal by a first preset time. Falling edge of first level signal is later than rising edge of the second level signal by a second preset time; the third level signal is obtain by delaying the first level signal by a third preset time, and the fourth level signal is obtain by delaying the second level signal by a fourth preset time; the first preset time is longer than the third preset time, and the second preset time is longer than the fourth preset time.

Output circuit, system including output circuit, and method of controlling output circuit

An output circuit includes a first transistor coupled to an external terminal and including a gate terminal that receives a first drive signal. The first transistor drives a potential at the external terminal in accordance with the first drive signal. A first capacitor includes a first end coupled to the gate terminal of the first transistor and a second end coupled to the external terminal. The output circuit also includes a circuit portion coupled to the first transistor. The circuit portion maintains the first transistor in an inactivated state when the gate terminal of the first transistor is in a floating state.

HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR (HVMOS) DEVICE INTEGRATED WITH A HIGH VOLTAGE JUNCTION TERMINATION (HVJT) DEVICE

Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well. 1. An integrated circuit (IC) comprising:a substrate;a first switching device well and a termination device well bordering in the substrate and having a first doping type;a first switching device overlying the first switching device well;a peripheral well in the substrate and having a second doping type opposite the first doping type, wherein the peripheral well has a first sidewall boundary directly contacting the first switching device well continuously in a first closed path and further has a second sidewall boundary directly contacting the termination device well continuously in a second closed path;a dielectric structure sunken into the substrate;a first field plate overlying the second sidewall boundary and on a first sidewall of the dielectric structure; anda spiral structure overlying the first switching device well and the termination device well on the dielectric structure, wherein the dielectric structure extends directly from the first field plate to the spiral structure.2. The IC according to claim 1 , further comprising:a high side well overlying the termination device well in the substrate and having the second ...

Level shifter circuit

A level shifter with reduced propagation delay. A level shifter includes a signal input terminal, a first signal output node, a first transistor, a second transistor, a third transistor, and a first capacitor. The first transistor includes a control terminal coupled to the signal input terminal. The second transistor includes an output terminal coupled to an input terminal of the first transistor. The first capacitor includes a bottom plate coupled to an input terminal of the second transistor. The third transistor includes a control terminal coupled to a top plate of the first capacitor, and an output terminal coupled to the first signal output node.

Apparatuses including scalable drivers and methods

Apparatuses and methods are described that include a plurality of drivers corresponding to a single via. A number of drivers can be selected to operate individually or together to drive a signal through a single via. Additional apparatus and methods are described.

Semiconductor device

A semiconductor device or the like capable of preventing malfunction of a driver circuit is provided. In a driver circuit for driving a power device used for current supply, a transistor including an oxide semiconductor is used as a transistor in a circuit (specifically, for example, a level shift circuit) requiring a high withstand voltage. In addition, a transistor (for example, a silicon transistor or the like) capable of higher operation than a transistor including an oxide semiconductor is preferably used as a transistor in a circuit (specifically, for example, a buffer circuit, a flip-flop circuit, or the like) requiring a lower withstand voltage than the level shift circuit.

Transmitter

A transmitter is provided. the transmitter includes a hybrid feedback circuit and a hybrid driving circuit. The hybrid feedback circuit compares a reference voltage with a feedback voltage in closed-loop, determines whether to perform polarity reversal according to a mode control signal, controls power output according to a comparison result and the mode control signal, and generates a first output signal. The hybrid driving circuit, coupled to the hybrid feedback circuit, receives the first output signal of the hybrid feedback circuit, generates a transmitter output signal according to an input data, and generates a second output signal according to the transmitter output signal. The first output signal and the second output signal are transmitted back to the hybrid feedback circuit.

HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS

SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that configures a driving circuit that drives a long length wiring at a high speed while saving its area in the case of driving a load with a large capacity and a reception circuit that receives the signal from the drive circuit at a high speed. SOLUTION: An inverter 30 is provided in the inside of the driving circuit and an N-channel MOS TR 16 is adopted, which has a higher driving force in comparison with a P-channel MOS TR as a driving TR, so as to drive a long extension wiring having a high load such as a bus at a high speed. Thus, a driving circuit that drives a long length wiring at a high speed while saving its area is realized and a reception circuit that suppresses a through-current while receiving the varying signal from the driving circuit can be realized. COPYRIGHT: (C)2000,JPO ...

DIGITAL LOGIC CIRCUIT

CMOS INPUT LEVEL SHIFTING CIRCUIT

Clamping audio signal paths

Clamping audio signal paths

Voltage clamping circuitry 200 has a first actively controlled PMOS switching device 201 in series with a second actively controlled NMOS switching device 202 between a node of the signal path and the clamp voltage, e.g. ground. Control signals S1, S2 are generated by controller 203. The clamping circuitry is selectively operable in a first state wherein both switching devices are on such that a voltage at the node is substantially the same as the clamp voltage; and also in a second state to electrically disconnect the signal path from the clamp voltage. In a second state the first switching device blocks conduction when the voltage at said node of the signal path is positive and the second switching device blocks conduction when the voltage at said node of the signal path is negative.

ELECTRONIC INTERFACE CIRCUIT

Digital circuit topology offering an improved power delay product

BUS TRANSCEIVER INCLUDING CIRCUIT FOR COMPENSATION OF COMPONENT VARIATION

A bus transceiver having a driver with charging/discharging characteristics that are device-independent and a receiver that provides adequate noise immunity is described. The transceiver uses a reference network to modulate the conductance of a depletion device as a function of device parameter variations in order to maintain a constant response time for the driver and optimize peak current. The receiver uses a modified differential amplifier to provide high gain and hysteresis sufficient for a desired level of noise immunity.

VOLTAGE LEVEL TRANSLATING CIRCUIT

ENHANCEMENT-AND DEPLETION-TYPE FIELD EFFECT TRANSISTORS CONNECTED IN PARALLEL

CLOCK STRETCHER AND LEVEL SHIFTER WITH SMALL COMPONENT COUNT AND LOW POWER CONSUMPTION

A clock stretching circuit (110) mediates between a synchronous bus (112) and a microcontroller (124) which is asleep most of the time to save electrical power. The bus is of a type in which a slow bus device can cause the sender of data to "hold" the data until the slow device is up to speed. The stretching circuit (110) is of small component count and low power consumption, and there is no requirement for a continuous clock. In one embodiment is comprised of a triple analog switch (120, 121, 122) and a very small number of additional components. In another embodiment a dual four-position multiplexer (162, 163) is employed. In still another embodiment, four transistors (210, 212, 213, 215) are used with handful of additional components. A level shifter (220, 221, 222, 223) including an MOSFET and a large-value resistor help to minimize power drain within the bus device. The components can be external to an off- the-shelf microcontroller or can be included in an IC that also contains an ...

CLAMPING CIRCUIT FOR AUDIO SIGNALS

Wake circuit for powered ophthalmic lens

Novel UART interface level converting and multiplexing circuit

DEVICE HAS INTEGRATED CIRCUIT, CARRIED OUT STARTING FROM STANDARD MATRIX A “, CARRYING OUT A MULTIPLICITY OF SWITCHING FUNCTIONS BY MODIFICATION OF THE NETWORK OF CALIBRATION”

REFERENCE VOLTAGE GENERATOR DEVICE

NOT-CIRCUIT Of ENTRY CMOS COMPATIBLE WITH SIGNALS TTL

FET INTERFACE CIRCUIT

OUTPUT DRIVER FOR MIXED SUPPLY VOLTAGE SYSTEM

레벨 변환 디바이스 및 방법

... 레벨 시프터 및 셀렉터를 포함하는 디바이스가 개시된다. 레벨 시프터는 제1 전류 제한기를 포함한다. 레벨 시프터는, 제1 입력 신호에 따라 제1 전류 제한기의 제1 단자에서 제1 출력 신호를 발생하고 제1 전류 제한기의 제2 단자에서 제2 출력 신호를 발생하도록 구성된다. 셀렉터는 제1 입력 신호에 따라 제1 출력 신호와 제2 출력 신호 중의 하나를 선택적으로 전송하도록 구성된다.

LEVEL SHIFTER CIRCUIT

A level shifter circuit comprises a first transistor and a second transistor. The first transistor is connected to a power terminal and an output terminal and transfers a power voltage applied from the power terminal to the output terminal in response to an input signal, transferred from the input terminal to a first gate, and a signal transferred to a second gate. The second transistor is connected to the power terminal and transfers a grounding voltage to the output terminal in response to a gate signal transferred to a gate. Accordingly, the present invention can improve power efficiency in a depletion mode or an increase mode by forming a main transistor in the level shifter circuit as a double gate transistor. COPYRIGHT KIPO 2016 ...

Switching control circuit with voltage sensing function and photo-flash capacitor charger thereof

A switching control circuit is utilized to control a switch to turn on/off. The switch is coupled between a primary winding of a transformer of a photo-flash capacitor charger and ground. The switching control circuit includes a voltage-clamping buffer circuit, a set driving circuit, a reset driving circuit, and a reset-dominated latch. The voltage-clamping buffer circuit is coupled to the primary winding for reducing the switching voltage on the primary winding. The set and the reset driving circuits generate a set signal and a reset signal respectively according to the reduced switching voltage. The reset-dominated latch controls the switch to turn on/off according to the set signal and the reset signal.

Level converting circuit efficiently increasing an amplitude of a small-amplitude signal

A gate of an N-channel MOS transistor driving an output node is driven through a capacitance element in accordance with an input signal. A voltage on a source node of the drive transistor is applied as an output signal to an output node. Consequently, it is possible to perform level conversion of a voltage at a low level of the input signal having a higher voltage than the source node voltage of the drive transistor. It is thus possible to achieve a level converting circuit that can reduce the number of manufacturing steps, and can perform the level conversion of any logical level of the input signal.

Digital interface detecting apparatus

LEVEL SHIFT CIRCUIT

Provided is a high-reliability level shift circuit not prone to faulty operation due to noise. This level shift circuit (1) is provided with: a first and second current control element (12a, 12b) into the control terminals of which a reverse-phase input signal and a same-phase input signal are inputted, respectively; a first and second load circuit (13a, 13b) which are connected at one end to a high side power source terminal (Vb) and at the other end to the first terminals of the first and second current control elements (12a, 12b); a comparator (14) in which a pair of differential input terminals (Np, Nn) connects separately to the first terminals of the first and second current control elements (12a, 12b); a current generating circuit (3) in which first and second current output terminals (Na, Nb) connect to second terminals of the first and second current control elements (12a, 12b) and each of which separately generates a current which flows through the respective first and second ...

COMMUNICATION DEVICE, AND ELECTRONIC DEVICE COMPRISING SAME

A communication device is disclosed. The disclosed communication device comprises: a transmission circuit for generating a transmission signal by using a first field effect transistor (FET) and a signal inputted from a first control circuit, and transmitting the transmission signal to a second control circuit; and a reception circuit for generating a reception signal by using a second field effect transistor (FET) and a signal received from the second control circuit, and outputting the reception signal to the first control circuit. 1. A communication device , comprising:a transmission circuit configured to generate a transmission signal by using a signal input from a first control circuit and a first field effect transistor (FET), and transmit the transmission signal to a second control circuit; anda reception circuit configured to generate a reception signal by using a signal received from the second control circuit and a second field effect transistor (FET), and output the reception signal to the first control circuit.2. The communication device of claim 1 , wherein the transmission circuit is configured to generate claim 1 , based on a voltage level of the first control circuit being lower than a voltage level of the second control circuit claim 1 , the transmission signal by performing a level shift to a signal inputted from the first control circuit claim 1 , andwherein the reception circuit is configured to generate, based on a voltage level of the first control circuit being lower than a voltage level of the second control circuit, the reception signal by performing a level shift to a signal received from the second control circuit.3. The communication device of claim 1 , wherein the reception circuit is configured to have a symmetrical structure with the transmission circuit.4. The communication device of claim 1 , wherein the transmission circuit further comprises:a first resistance configured for one end to be connected to the first control circuit, and ...

Systems and methods to provide charge sharing at a transmit buffer circuit

A circuit includes a data input in communication with a first transistor stack; a first capacitor having a first capacitance and in communication with a power supply via a first transistor of the first transistor stack, wherein the first transistor is configured to charge the first capacitor in response to the data input receiving a signal corresponding to a first binary value; a data output node coupled between the first transistor stack and a transmission line having a second capacitance; and wherein the first capacitor is coupled between the data output node and a second transistor of the first transistor stack, further wherein the second transistor is configured to discharge the first capacitor to the data output node in response to the data input receiving a signal corresponding to a second binary value.

COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) COMPATIBLE RF SWITCH AND HIGH VOLTAGE CONTROL CIRCUIT (HVCC)

A complementary metal-oxide semiconductor (CMOS) compatible radio frequency (RF) switch circuit and high voltage control circuit (HVCC) are disclosed. In a mobile device, an RF switch circuit couples a first RF circuit to a shared antenna through a low resistance path while electrically isolating other RF circuits from the antenna by a high resistance path. Each path in the RF switch circuit includes a series metal-oxide semiconductor (MOS) Field-Effect Transistor (FET) MOSFET switch which provides a low resistance path when fully turned on by a strong positive gate-to-source voltage and a corresponding body bias voltage, and a high resistance path when fully turned off by a strong negative gate-to-source voltage and corresponding body bias voltage. The RF switch circuit paths are controlled by a CMOS compatible HVCC which supplies high and low voltage signals to the gate node and body bias node of each MOSFET in each path. 1. A radio frequency (RF) switch circuit , comprising:a primary node configured to couple to a circuit component; 'a first series switch having a rated voltage, the first series switch configured to couple a first RF node to the primary node in response to a gate node-to-source node voltage and a body bias voltage of the first series switch;', 'a first RF path, comprising 'a second series switch having the rated voltage, the second series switch configured to couple a second RF node to the primary node in response to a gate node-to-source node voltage and a body bias voltage of the second series switch; and', 'a second RF path, comprising supply a reference voltage to a gate node and a body bias node of a first one of the first and second series switches;', 'supply a power supply voltage to the gate node of a second one of the first and second series switches; and', 'supply a medial voltage between the reference voltage and the power supply voltage to the body bias node of the second one of the first and second series switches;', 'wherein a ...

Extended GPIO (eGPIO)

An extended General Purpose Input/Output (eGPIO) scheme is disclosed. In some implementations, an input/output (I/O) boundary scan cell comprises an output path to route output signals from a first voltage domain and signals from a second voltage domain to an I/O pad operating in a pad voltage domain, the output path having a first level shifter to up shift the output signals from the first voltage domain or the second voltage domain to the pad voltage domain; an input path to receive input signals from the I/O pad, the input path having a second level shifter to down shift the input signals from the pad voltage domain to the second voltage domain; and test logic to test signals in the first voltage domain and the second voltage domain.

Cascode SSTL output buffer using source followers

A cascode SSTL output buffer using a source follower circuit includes a biasing circuit arranged to generate a first bias signal. The source follower circuit is responsive to the first bias signal and generates a second bias signal which is then used by a cascode circuit that receives an input signal to the SSTL output buffer to drive an output signal from the SSTL output buffer.

Tracking unity gain for edge rate and timing control

In general, in one aspect, the disclosure describes an apparatus for calibrating signals. The apparatus includes a unity gain detector to traverse a gain curve of an output buffer circuit to determine unity gain voltages associated with unity gain crossover points on an input voltage ramp. The apparatus further includes a pre-boost circuit to apply the unity gain voltages to at least one input/output buffer within the output buffer circuit.

Switch control circuit with voltage sensing function and camera flash capacitor charger thereof

A switch control circuit has a voltage sensing function. The switch control circuit includes a voltage-clamping buffer, a set driver, a reset driver, and an R-dominant SR latch. The voltage-clamping buffer shifts a switch voltage to generate a down-shifted switch voltage. The set driver generates a set signal according to the down-shifted switch voltage. The reset driver generates a reset signal according to the down-shifted switch voltage. The R-dominant SR latch comprises a set end for receiving the set signal, a reset end for receiving the reset signal, an output end for outputting a switch control signal for controlling conductance of a first transistor coupled to a primary winding of a transformer, and an output bar end for outputting an inverted switch control signal.

Level shifter with low voltage loss

A system and method are disclosed for level shifting a DDC bus with a low voltage loss. A pull up circuit includes an NMOS transistor, a PMOS transistor and resistor. An NMOS pull up gate is also included in line with the DDC bus. When powered, the level shifter adjusts the voltage of transmitted signals to match the voltage of a receiving device. The resulting adjusted is slightly lower due to a threshold voltage lost across one or more transistors. Additionally, when unpowered, the level shifter releases the signal transmission line. Unadjusted signals can then be transmitted without consumption of power by the level shifter.

Interface Circuit

An interface circuit includes a phase inverter. An input end of the phase inverter is connected to a signal output end of a first power domain circuit, and an output end of the phase inverter is connected to a signal input end of a second power domain circuit. A power end of the phase inverter is connected to a power supply of the first power domain circuit, and a ground end of the phase inverter is connected to a reference ground of the second power domain circuit. Alternatively, a power end of the phase inverter is connected to a power supply of the second power domain circuit, and a ground end of the phase inverter is connected to a reference ground of the first power domain circuit.

High voltage tolerant input circuit capable of operating at extremely low IO supply voltage

An input circuit including a diode, a resistor, a first transistor, a buffer, a bulk voltage generating unit and an enhancing unit is provided. The input circuit of the present invention uses the bulk voltage generating unit and the enhancing unit for making the internal input voltage to be the same as the external input voltage when the external input voltage is less than or equal to the first supply voltage (for example, the IO supply voltage). Moreover, even if the first supply voltage is extremely low, the input circuit of the present can still operate correctly. Accordingly, the input circuit of the present invention can be operated at extremely low IO supply voltage.

Level shifter circuit, corresponding device and method

A level-shifter circuit operates to shift an input signal referenced to a first set supply voltages to generate an output signal referenced to a second set of supply voltages. The output signal from the level-shifter circuit is latched by a latching circuit. A logic gate has a first input configured to receive the input signal, a second input configured to receive a feedback signal and an output coupled to a input of the level shifting circuit. A feedback circuit has a first input configured to receive the output signal, a second input configured to receive the input signal and an output configured to generate the feedback signal. The feedback circuit operates to sense an uncontrolled switching event of the output signal occurring in the absence of a switching of the input signal and apply, in response thereto, the feedback signal to cancel the uncontrolled switching event.

LEVEL SHIFT CIRCUIT

There is provided a level shift circuit free from malfunction. The level shift circuit converts a signal of a first power supply voltage of a first supply terminal, which is supplied to an input terminal, into a signal of a second power supply voltage of a second supply terminal and outputs the converted signal to an output terminal. The level shift circuit has a control circuit that detects when the first power supply voltage reduces below a predetermined voltage. The voltage of the output terminal of the level shift circuit is fixed to the second power supply voltage or a ground voltage according to a detection signal of the control circuit.

Negative-level shifting circuit and a source driver and a display device using the circuit

A negative-level shifting circuit includes a first level shifter including an input circuit configured to receive a logic signal having a first voltage level and a load circuit configured to generate a first output signal having a second voltage level based on a voltage generated by the input circuit, and a second level shifter configured to receive the first output signal from the first level shifter and generate a second output signal having a third voltage level. The first level shifter further includes a shielding circuit connected between the input circuit and the load circuit and configured to separate an operating voltage region of the input circuit from an operating voltage region of the load circuit such that the input circuit operates in a positive voltage region and the load circuit operates in a negative voltage region.

Output buffer circuit having a level conversion function

СХЕМА АКТИВАЦИИ ДЛЯ ОФТАЛЬМОЛОГИЧЕСКОЙ ЛИНЗЫ С ЭЛЕКТРОПИТАНИЕМ

MONOLITHISCH INTEGRIERBARE MIS- TREIBERSTUFE

Kleinleistungs-Einzelanschluss-Pegelschieber unter Verwendung eines Abschaltsignals aus einem Ausgangsleistungsbereich und ein Verfahren zum Umwandeln eines Datensignals zwischen Leistungsbereichen

INTEGRIERTE FESTKOERPERSCHALTUNG MIT EINER MEHRZAHL VON MOS-BAUELEMENTEN

SCHALTUNGSANORDNUNG FUER LOGISCHE SCHALTKREISE MIT FELDEFFEKTTRANSISTOREN

SCHALTUNGSANORDNUNG FUER LOGISCHE SCHALTKREISE MIT FELDEFFEKTTRANSISTOREN

Cascode level shifter transient protection

A cascode level shifter receives a low voltage input and generates an output in a high voltage range and is divided into low and high supply voltage sections, the combined voltage across which corresponds to the high voltage range. The level shifter comprises a driver switch 200,220 in series with a cascode switch 210,230 at a midpoint node that switches depending on the input and a reference voltage DVDD2. A perturbation circuit transiently varies the reference voltage in response to an input transition thereby turning the cascode switches on faster. The perturbation circuit can comprise an RC circuit having capacitors 240, 270 connecting the reference node to an input and resistors 250,260 that can be PMOS transistors (fig 3,.300,305); clamping transistors (fig 3, 320, 325) and cut-off capacitors (fig 3, 330,335). The reference voltage of a high voltage section cascoded switch (fig 5 400,420) can be perturbed by a pulling it down to ground with a switch such as an NMOS transistor (fig ...

Semiconductor Device, and Display Device and Electronic Device Utilizing the Same

A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased.

DRIVING CIRCUIT WITH ZERO CURRENT SHUTDOWN AND A DRIVING METHOD THEREOF

Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current. 1. A driving circuit comprising:a) a linear regulating circuit configured to receive an input voltage source, and to provide an output voltage based on a first current;c) a first power switch configured to receive said output voltage of said linear regulating circuit and an external enable signal, and to generate an internal enable signal configured to drive a logic circuit; andd) a start-up circuit configured to receive said external enable signal at a gate of a second power switch, wherein when said external enable signal is lower than a threshold voltage that is related to said second power switch, said start-up circuit is configured to disable said first current and said driving circuit, and when said external enable signal is higher than said threshold voltage, said start-up circuit is configured to a generate said first current and enable said driving circuit.2. The driving circuit of claim 1 , further comprising a first current mirror coupled to said input voltage source claim 1 , said linear regulating circuit claim ...

LEVEL SHIFT CIRCUIT AND DRIVE CIRCUIT OF DISPLAY DEVICE

In a level shift circuit, input signals are input into gates of a first and a second MOS transistors whose sources are coupled to a first supply voltage VSS. Gates of a third and a fourth MOS transistors whose sources are coupled to a second supply voltage are coupled to drains of the second and the first MOS transistors. A first voltage generation circuit is coupled between the drains of the first and the third MOS transistors, and a second voltage generation circuit is coupled between the drains of the second and the fourth MOS transistors. The gate of the fifth MOS transistor is coupled to a connection node NDB, and the source of the fifth MOS transistor is coupled to the second supply voltage. 1. A level shift circuit comprising:a first MOS transistor of a first conductivity type, into a gate of which an input signal having an amplitude between a third supply voltage indicating a voltage between a first supply voltage and a second supply voltage and the first supply voltage is input;a second MOS transistor of the first conductivity type, into a gate of which an inverted input signal which is an inverted signal of the input signal, is input, sources of the first and the second MOS transistors being commonly coupled to the first supply voltage;a third MOS transistor of a second conductivity type complementary to the first conductivity type, whose gate is coupled to a drain of the second MOS transistor;a fourth MOS transistor of the second conductivity type, whose gate is coupled to a drain of the first MOS transistor, sources of the third and the fourth MOS transistors being commonly coupled to the second supply voltage;a first voltage generation circuit coupled between the drain of the first MOS transistor and a drain of the third MOS transistor;a second voltage generation circuit coupled between the drain of the second MOS transistor and a drain of the fourth MOS transistor;a fifth MOS transistor of the second conductivity type, whose gate is coupled to a ...

3x input voltage tolerant device and circuit

A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltage at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages.

SWITCHING ARRANGEMENT, INTEGRATED CIRCUIT COMPRISING SAME, METHOD OF CONTROLLING A SWITCHING ARRANGEMENT, AND RELATED COMPUTER PRORAM PRODUCT

There is disclosed a switching arrangement comprising a switch with a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail. Each of the elementary switches can be in either one of a closed state and an open state independently of the others. A controller is adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch. The number of elementary switches in the closed state is variable. The higher is the intensity of the current, the higher the number of elementary switches in the closed state. Thus, the impedance of the switch decreases when the current increases, and vice versa, and the voltage drop across the switch may be kept substantially constant. 1. A switching arrangement , comprising:a switch comprising a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail, each of said elementary switches being in either one of a closed state and an open state independently of the others; and,a controller adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch, wherein the number of elementary switches in the closed state is variable and wherein the higher is the intensity of the current the higher the number of elementary switches in the closed state.2. The switching arrangement of claim 1 , wherein the controller is further adapted to receive claim 1 , from a load supplied by the second supply rail claim 1 , a current value indication representative of the intensity of the current flowing through the switch claim 1 , and to control the closing or opening of the elementary switches responsive to said current value indication.3. The switching arrangement of claim 1 , wherein the controller comprises a current-sense block adapted to ...

ASYMMETRICAL BUS KEEPER

Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first inverter stage having an input node and an output node, an asymmetrical inverter stage having an input node and an output node and a feedback stage with an input node and an output node. The input node of the asymmetrical inverter stage is connected to the output node of the first inverter stage. The input node of the feedback stage connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage connected to the input node of the first inverter stage. The asymmetrical stage provides asymmetrical drive towards one logic level. 2. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a high logic level and the asymmetrical inverter stage comprises a single p-channel transistor wherein a gate of the p-channel transistor is connected to the input node of the asymmetrical inverter stage claim 1 , a source of the p-channel transistor is connected to a positive voltage supply level claim 1 , and a drain of the p-channel transistor is connected to the output node of the asymmetrical inverter stage.3. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a high logic level and the asymmetrical inverter stage comprises a p-channel transistor having a first drive and an n-channel transistor having a second drive claim 1 , the p-channel and n-channel transistors being oriented in an inverter configuration claim 1 , wherein the first drive is at least one order of magnitude larger than the second drive.4. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a low logic level and the asymmetrical ...

SEMICONDUCTOR DEVICE HAVING FLOATING BODY TYPE TRANSISTOR

A semiconductor device includes a first circuit node supplied with a first signal changing between first and second logic levels, a second circuit node supplied with a second signal changing between the first and second logic levels, a third circuit node, a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level, a fourth circuit node supplied with a voltage level being close to or the same as the second logic level, and a second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level. 1. A semiconductor device comprising:a first circuit node supplied with a first signal changing between first and second logic levels;a second circuit node supplied with a second signal changing between the first and second logic levels;a third circuit node;a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level;a fourth circuit node supplied with a voltage level being close to or the same as the second logic level; anda second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level,the first transistor being configured as a floating body type in which a body between a source and a drain is in en electrically floating state.2. The semiconductor device as ...

DIFFERENTIAL OUTPUT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

A differential output circuit has a current source, a voltage source, first paired transistors which, in a first operating mode, switch that current from the current source should be flown to which of paired output terminals, depending on logic levels of differential input signals, and is always turned off in a second operating mode, second paired transistors which, in the second operating mode, switch which of the paired output terminals should be applied with a voltage correlated with a voltage of the voltage source, depending on the logic levels of the differential input signals, and configured to be always turned off in the first operating mode, third paired transistors which, in the second operating mode, pass the current inputted into one of the paired output terminals toward a predetermined reference potential, and is always turned on in the first operating mode, and paired impedances. 1. A differential output circuit comprising:a current source;a voltage source;first paired transistors configured to, in a first operating mode, switch that current from the current source should be flown to which of paired output terminals, depending on logic levels of differential input signals, and configured to be always turned off in a second operating mode;second paired transistors configured to, in the second operating mode, switch which of the paired output terminals should be applied with a voltage correlated with a voltage of the voltage source, depending on the logic levels of the differential input signals, and configured to be always turned off in the first operating mode;third paired transistors configured to, in the second operating mode, pass the current inputted into one of the paired output terminals toward a predetermined reference potential, depending on the logic levels of the differential input signals, and configured to be always turned on in the first operating mode, the third paired transistors being connected to output current paths of the second ...

Signal driver circuit having adjustable output voltage for a high logic level output signal

A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage.

Schmitt receiver systems and methods for high-voltage input signals

Presented systems and methods facilitate efficient switching operations for components operating at different voltage level than a received signal voltage level. In one embodiment, the components of a presented system are operable to perform switching operations for signals with a voltage level swing larger than the power rail of the circuit receiving the signals. In one embodiment a system includes an input component, a transition component, a transition point feedback component and an output component. The input component is operable to receive an input signal. The transition component is operable to transition the input signal. The transition point feedback component is operable to adjust a point at which a transition in the input signal occurs in the transition component. The output component is operable to forward an output signal from the transition point feedback component.

SEMICONDUCTOR DEVICE AND FAULT DETECTING METHOD

An obtained margin is smaller than a margin to be kept for a fault period predicted by life prediction based on a power cycle test, extending a maintenance cycle for replacement and so on. A method of detecting a fault of a semiconductor device including a power device mounted on a metal base and a drive circuit for driving the power device, the method detecting a fault of the semiconductor device beforehand based on an increase in thermal resistance between the metal base and the power device. A state of the power device is measured immediately before and after the power device is driven by the drive circuit. A temperature difference of the power device before and after driving is calculated according to the result of measurement. An increase in thermal resistance between the metal base and the power device is detected based on the temperature difference and an amount of electricity inputted to the power device in the driving period, and a fault of the semiconductor device is detected beforehand according to the increase. 1. A semiconductor device comprising:a power device mounted on a metal base;a drive circuit for driving the power device;a measuring circuit that measures a state of the power device immediately before and after a driving period in which the drive circuit drives the power device; anda control circuit that detects, according to a result of the measurement by the measuring circuit, an increase in thermal resistance between the metal base and the power device based on a temperature difference before and after the driving of the power device and input power to the power device in the driving period.2. The semiconductor device according to claim 1 ,wherein the control circuit causes the drive circuit to perform the driving on a condition that the input power is set at a predetermined value.3. The semiconductor device according to claim 2 ,wherein the drive circuit drives the power device in response to a driving signal with pulse width modulation, the ...

System and Method for a Pre-Driver Circuit

A drive circuit includes an input, a driver, a first buffer, a second buffer, a first capacitance element, and a second capacitance element. The driver includes a first PMOS transistor and a first NMOS transistor coupled in series between a supply terminal and a reference terminal. The first buffer is coupled between the input and a control terminal of the first PMOS transistor. The second buffer is coupled between the input and a control terminal of the first NMOS transistor. The first capacitance element is coupled to the control terminal of the first PMOS transistor through a first semiconductor switch. The second capacitance element is coupled to the control terminal of the first NMOS transistor through a second semiconductor switch. 1. A circuit comprising:a driver having an input terminal and an output terminal;a semiconductor switch having a first terminal and a second terminal, the first terminal of the semiconductor switch coupled to the output terminal of the driver; and the semiconductor switch and the capacitance element comprise a variable capacitance,', the variable capacitance provides a capacitance of substantially zero during a first portion of a data transition in the output terminal of the driver from a first state to a second state, and', 'the variable capacitance provides a non-zero capacitance during a second portion of a data transition in the output terminal of the driver from the first state to the second state., 'the variable capacitance is controlled such that'}], 'a capacitance element coupled between the second terminal of the semiconductor switch and a power supply terminal, wherein'}2. The circuit of claim 1 , wherein the semiconductor switch comprises a transistor and the capacitance element is a capacitor.3. The circuit of claim 1 , wherein the semiconductor switch comprises a p-type transistor and the driver is an inverting driver.4. The circuit of claim 1 , wherein the first state represents a 1 and the second state represents a 0. ...

CONFIGURABLE POWER DOMAIN AND METHOD

Aspects of this disclosure are directed to level-shifting approaches with communications between respective circuits. As may be implemented in accordance with one or more embodiments characterized herein, a voltage level of communications passed between respective circuits are selectively shifted. Where the respective circuits operate under respective power domains that are shifted in voltage range relative to one another, the voltage level of the communications is shifted. This approach may, for example, facilitate power-savings for stacked circuits in which a low-level voltage of one circuit is provided as a high-level voltage for another circuit. When the respective circuits operate under a common power domain, the communications are passed directly between the respective circuits (e.g., bypassing any level-shifting, and facilitating fast communication). 1. An apparatus comprising:a first circuit configured and arranged to operate under a first power domain having a first voltage range;a second circuit configured and arranged to operate under a second power domain having a second voltage range; and detect a voltage range of the first power domain,', 'detect a voltage range of the second power domain, and', convert a voltage level of each communication received from one of the first and second circuits to a voltage level of the other one of the first and second circuits in response to the detected voltage ranges being different, and thereafter providing the communication to the other one of the first and second circuits, and', 'pass each communication directly between the first and second circuits in response to the detected voltage ranges being the same., 'for communications between the first and second circuits,'}], 'a level shifter circuit connected to the first circuit and to the second circuit, the level shifter circuit being configured and arranged to2. The apparatus of claim 1 , wherein the level shifter circuit is configured and arranged to:in a first ...

I/o cell

An I/O cell includes a reference output circuit that has a reference output transistor, connected to an output terminal, and has a reference pre-buffer, the reference pre-buffer driving the reference output transistor according to an input signal of the input terminal; adjustment output circuits that have an adjustment output transistor, connected to the output terminal and connected in parallel with the reference output transistor, and have an adjustment pre-buffer, the adjustment pre-buffer driving the adjustment output transistor according to the input signal; and a gate voltage detection control circuit that monitors all of gate voltages applied to the output transistors included in the reference output circuit and the adjustment output circuit. The gate voltage detection control circuit generates a timing when all of the output transistors are turned OFF when switching the H/L level of the output current to the load according to the change of the input signal.

LEVEL SHIFTING CIRCUIT AND METHOD

A level shifting circuit includes a shift circuit configured to output first and second voltage signals according to level signals, and an input circuit configured to carry out inversion and delay operations on input level signals to obtain first, second, third, and fourth level signals. Rising edge of the first level signal is earlier than falling edge of the second level signal by a first preset time. Falling edge of first level signal is later than rising edge of the second level signal by a second preset time; the third level signal is obtain by delaying the first level signal by a third preset time, and the fourth level signal is obtain by delaying the second level signal by a fourth preset time; the first preset time is longer than the third preset time, and the second preset time is longer than the fourth preset time. 1. A level shifting circuit , comprising an input circuit , and a shifting circuit connected with the input circuit , wherein:the input circuit is configured to perform inversion and delay operations on an input level signal to obtain a first level signal, a second level signal, a third level signal and a fourth level signal;a rising edge of the first level signal occurs a first preset time earlier than a falling edge of the second level signal, and a falling edge of the first level signal occurs a second preset time later than a rising edge of the second level signal; the third level signal is a signal obtained by delaying the first level signal for a third preset time, and the fourth level signal is a signal obtained by delaying the second level signal for a fourth preset time; the first preset time is longer than the third preset time, the second preset time is longer than the fourth preset time; andthe shifting circuit is configured to output a first voltage signal and a second voltage signal based on the level signals, and the first voltage signal and the second voltage signal are inverted with each other.2. The level shifting circuit ...

SIGNAL GENERATOR ADJUSTING A DUTY CYCLE AND SEMICONDUCTOR APPARATUS USING THE SAME

A semiconductor apparatus may include a signal generator, and may operate by receiving two or more external power voltages. The signal generator may include a duty cycle circuit. The duty cycle circuit may include a duty control circuit and a duty cycle adjustment circuit. The duty cycle adjustment circuit may be configured to compensate a duty change of an output signal when a power voltage domain changes. 1. A signal generator comprising:a first buffer configured to amplify an input signal to a level of a first power voltage and generate a first output signal;a second buffer configured to amplify the first output signal to a level of a second power voltage and generate a second output signal;a duty control circuit configured to generate a duty control signal by comparing the levels of the first power voltage and the second power voltage; anda duty cycle adjustment circuit configured to change a voltage level of the first output signal based on the input signal and the duty control signal.2. The signal generator of claim 1 , wherein the first buffer generates the first output signal having a voltage level between the first power voltage and a first ground voltage based on the input signal.3. The signal generator of claim 2 , wherein the second buffer generates the second output signal having a voltage level between the second power voltage and a second ground voltage based on the input signal.4. The signal generator of claim 3 , wherein the first ground voltage has substantially the same level as the second ground voltage.5. The signal generator of claim 1 ,wherein the duty control signal includes a duty up signal and a duty down signal, andwherein the duty control circuit generates the duty up signal when the level of the first power voltage is higher than the level of the second power voltage, and generates the duty down signal when the level of the first power voltage is lower than the level of the second power voltage.6. The signal generator of claim 1 , ...

LEVEL SHIFT CIRCUIT

The present invention provides a level-shift circuit that can suppress the malfunction caused by the noise due to the ON/OFF of a level-shift transistor and the dV/dt noise due to external noise. The present invention provides a level-shift circuit for transmitting a signal from a primary potential side to a secondary potential side, comprising: a first serial circuit a first resistance including serially-connected to a first switching element; a second serial circuit including a second resistance serially-connected to a second switching element; a latch malfunction protection circuit for which the respective output terminals of the first and second serial circuits are connected to an input terminal; a latch circuit for receiving a signal outputted from the latch malfunction protection circuit; and a capacitor connected between drain terminals of the first resistance and the first switching element and between drain terminals of the second resistance and the second switching element. 1. A level-shift circuit for transmitting a signal from a primary potential side to a secondary potential side different from the primary potential side , comprising:a first serial circuit including a first resistance serially-connected to a first switching element, wherein the input of the first switching element is a first input signal for turning ON or OFF the first switching element, and a connecting point of the first resistance and the first switching element acts as an output terminal;a second serial circuit including a second resistance serially-connected to a second switching element, wherein the input of the second switching element is a second input signal for controlling the ON/OFF of the second switching element, a connecting point of the second resistance and the second switching element acts as an output terminal, and the first input signal and the second input signal are not simultaneously turned ON;a latch circuit for changing a status depending on the output of the ...

Cross-Coupled, Narrow Pulse, High Voltage Level Shifting Circuit With Voltage Domain Common Mode Rejection

A system for high voltage level shifting includes a level shifting circuit having a high side circuit that receives a mixed signal having a common mode signal and a differential mode signal, and to attenuate the common mode signal in the mixed signal to generate an adjusted signal. The high side circuit generates a high output signal at a high output node in response to the adjusted signal. The system further includes a high side high voltage power transistor having a gate connected to the high output node of the high side circuit. The high side high voltage power transistor configured to provide a high portion of an output signal on a first output node in response to the high output signal. 1. A system , comprising: 'a high side circuit configured to receive a mixed signal having a common mode signal and a differential mode signal, and to attenuate the common mode signal in the mixed signal to generate an adjusted signal, wherein the high side circuit is further configured to generate a high output signal at a high output node in response to the adjusted signal; and', 'a level shifting circuit includinga high side high voltage power transistor having a gate connected to the high output node of the high side circuit, the high side high voltage power transistor configured to provide a high portion of an output signal on a first output node in response to the high output signal.2. The system of claim 1 , further comprising:a low side circuit configured to generate the differential signal in response to a high input signal; anda low side high voltage power transistor having a gate connected to a low output node of the low side circuit;wherein the low side circuit is further configured to generate a low output signal at the low output node in response to a low input signal; andwherein the low side high voltage power transistor is configured to provide a low portion of an output signal on a second output node in response to the low output signal.3. The system of claim 2 ...

Multifunction Terminals for Alarm Systems

The present invention is directed to circuit that improves alarm systems by adding the flexibility through software to configure an output terminal for typical device functions of Alarm System Devices. With a number of these circuits on a single Circuit Board, installers can use fewer different Circuit Boards. Alarm systems may be constructed from many different components and sensors. These components and sensors may be connected either with wires or wireless networks. This present invention improves the ability to connect components and sensors for a Wired Alarm System. Present Alarm systems have dedicated terminals for each different sensor, keypad or human interface, Contacts for Windows and Doors, Solenoids to remotely unlock Doors. 1. A multifunction terminal for alarm systems comprising: i) measuring an analog signal and a digital signal; and', 'ii) outputting binary numbers at 3.3-volt logic level;, 'a) a first bit capable ofb) a second bit configured to be a terminal with input and output capabilities;c) a third bit configured to enable alarm system analog measurements;d) a fourth bit configured with a 3.3-volt binary output;e) a fifth bit configured with a 3.3-volt binary output and a pulse width modulated output;f) a sixth bit configured to be a terminal for a voltage and current connection;g) a plurality of P-Channel-MOSFETs;h) a plurality of N-Channel-MOSFETs;i) a plurality of resistors;j) an analog measurement mode;k) a test mode to detect a voltage source;l) a data receive mode;m) a data transmit current limited mode;n) a data or high current drive mode; ando) a data drive non-current limited mode.2. The multifunction terminal for alarm systems of claim 1 , wherein the analog measurement mode comprises:a) the first bit being configured to measure analog voltages;b) the fourth bit and the fifth bit being configured to output in a logic low setting; andc) the third bit being configured to be in a logic high setting.3. The multifunction terminal for ...

Level shifting circuit and method for the same

A level shifting circuit includes a transistor output unit that receives a first power supply signal and convert the first power supply signal to a second power supply signal having a different level from the first power supply signal and a current provision unit that provides a current to an output terminal of the transistor output unit when the first power supply signal of the transistor output unit is inputted to shorten a prolonged portion of the second power supply signal. Therefore, the level shifting circuit may provide an additional current to the output terminal of the transistor output unit to shorten a prolonged portion of the output voltage.

Multi-Voltage to Isolated Logic Level Trigger

Various systems may benefit from interfaces for handling multiple types of inputs. For example, a device with a trigger input from an external device may benefit from an isolated logic level trigger that is capable of addressing multiple types and values of voltage. An apparatus can include an input configured to receive an external trigger input signal having a trigger input voltage. The apparatus can also include circuitry configured to automatically adjust the trigger input voltage to a value configured to be compatible with a provided attached system. A working range of the trigger input voltage can exceed a compatible working range of the provided attached system. 1. An apparatus , comprising:an input configured to receive an external trigger input signal having a trigger input voltage; andcircuitry configured to automatically adjust the trigger input voltage to a value configured to be compatible with a provided attached system, wherein the circuitry comprises a current limiting device;wherein a working range of the trigger input voltage exceeds a compatible working range of the provided attached system.2. The apparatus of claim 1 , wherein the circuitry comprises a rectification section claim 1 , wherein the rectification section is configured to adjust claim 1 , for the trigger input voltage claim 1 , at least one of a polarity or a current type.3. The apparatus of claim 2 , wherein the rectification section of the circuitry comprises a full wave bridge rectifier.4. The apparatus of claim 2 , wherein the circuitry comprises an external ground trigger selection section.5. The apparatus of claim 4 , wherein the external ground trigger selection section comprises a switch configured to enable an external ground trigger when selected.6. The apparatus of claim 2 , wherein the circuitry comprises an isolation section configured to isolate the trigger input voltage from the provided attached system.7. The apparatus of claim 6 , wherein the isolation section ...

NAND GATE CIRCUIT, DISPLAY BACK PLATE, DISPLAY DEVICE AND ELECTRONIC DEVICE

The NAND gate circuit includes at least two input transistors, at least two pull-up modules and at least two input control transistors. A first electrode of each input transistor is connected to a second level output end via the pull-up module. The input control transistor is configured to enable a potential of the control end of the pull-up module connected to the first electrode of the input transistor to be the first level when the input signal connected to the gate electrode of the input control transistor is at a second level. The at least two pull-up modules are configured to cut off the connection between the second level output end and the NAND gate output end when all the input signals are at the second level, and enable the connection therebetween when none of the input signals is at the second level. 1. An NAND gate circuit , comprising at least two input transistors , a gate electrode of each input transistor being connected to an input signal , a first electrode of a first input transistor being connected to an NAND gate output end , a second electrode of a last input transistor being connected to a first level , and apart from the last input transistor , a second electrode of each input transistor being connected to a first electrode of a next input transistor , whereinthe NAND gate circuit further comprises at least two pull-up modules and at least two input control transistors,a gate electrode of each input control transistor is connected to the input signal, a first electrode thereof is connected to a control end of the corresponding pull-up module, and a second electrode thereof is connected to the first level,the first electrode of the first input transistor is connected to a second level output end via the pull-up module,the input control transistor is configured to enable a potential of the control end of the pull-up module connected to the first electrode of the input transistor to be the first level when the input signal connected to the gate ...

Driving circuit

A driving circuit includes: a primary driving module configured to receive a first signal and generate a second signal based on the first signal, driving capability of the second signal being greater than that of the first signal; and an auxiliary driving module connected to an output terminal of the primary driving module and configured to receive the first signal and generate an auxiliary driving signal based on the first signal, the auxiliary driving signal being configured to shorten a rise time of the second signal.

HIGH SPEED CIRCUIT WITH DRIVER CIRCUIT

A high-speed circuit with a high-voltage (HV) driver circuit. The high-speed circuit has a driver circuit and a level shifter. The driver circuit includes HV components which are operated in an HV domain. The level shifter includes low-voltage (LV) components which are operated in an LV domain. The level shifter translates signals from the LV domain to the HV domain to generate control signals for the driver circuit. The high-speed circuit may include a protection voltage generator converting a power supply voltage and a power ground voltage to generate a first direct-current bias voltage (VBP) and a second direct-current bias voltage (VBN) to bias the LV components of the level shifter. The LV components of the level shifter include input transistors and protection transistors. Gate voltages of the protection transistors may be tied to VBP or VBN. 1. A high-speed circuit , comprising:a driver circuit, including high-voltage components which are operated in a high-voltage domain; anda level shifter, including low-voltage components which are operated in a low-voltage domain, wherein the level shifter translates signals from the low-voltage domain to the high-voltage domain to generate control signals for the driver circuit.2. The high-speed circuit as claimed in claim 1 , further comprising:a protection voltage generator, converting a power supply voltage and a power ground voltage to generate a first direct-current bias voltage and a second direct-current bias voltage to bias the low-voltage components of the level shifter.3. The high-speed circuit as claimed in claim 2 , wherein:the protection voltage generator is an on-circuit circuit having input terminals coupled to a power supply terminal and a power ground terminal of the high-speed circuit to receive the power supply voltage and the power ground voltage, respectively; anda first voltage difference between the power supply voltage and the first direct-current bias voltage and a second voltage difference ...

SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes first, second, third, and fourth circuits. A first voltage is applied to the first circuit. A second voltage is applied to each of the second, third and fourth circuits. The third circuit is configured to generate a first control signal and a second control signal based on a signal generated by the first circuit and a signal generated by the second circuit. The fourth circuit is configured to output an output signal based on the first control signal and the second control signal. The output signal is brought to a high impedance state when at least one of the first voltage or the second voltage is not applied. 1. A semiconductor device comprising:a first circuit to which a first voltage is applied and which is capable of receiving a first input signal and a second input signal and is capable of generating a first signal based on the first input signal, a second signal based on the second input signal, and a third signal obtained by inverting a logic level of the second signal;a second circuit to which a second voltage different from the first voltage is applied and which is capable of receiving the second input signal and is capable of generating a fourth signal based on the second input signal and a fifth signal obtained by inverting a logic level of the fourth signal;a third circuit to which the second voltage is applied and which is capable of generating a first control signal based on the first signal, the second signal, and the fourth signal, and a second control signal based on the first voltage, the first signal, the third signal, and the fifth signal; anda fourth circuit to which the second voltage is applied and which is capable of outputting an output signal based on the first control signal and the second control signal,wherein the output signal is brought to a high impedance state when at least one of the first voltage or the second voltage is not applied.2. The device according to claim 1 , ...

Semiconductor Device, and Display Device and Electronic Device Utilizing the Same

A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased. 1. (canceled)2. A semiconductor device comprising:a first transistor;a second transistor;a third transistor;a fourth transistor; anda fifth transistor,wherein:one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor;a gate of the first transistor is electrically connected to a first wiring;the one of the source and the drain of the first transistor is electrically connected to a gate of the third transistor;a gate of the first transistor is electrically connected to a second wiring;one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;the other of the source and the drain of the third transistor is electrically connected to a third wiring;the other of the source and the drain of the fourth transistor is electrically connected to a fourth wiring;one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring;the other of the source and the drain of the fifth transistor is electrically connected to a fifth wiring; anda gate of the fifth transistor is electrically connected to a second wiring.3. The semiconductor device according to claim 2 , wherein the first ...

Level shift switch and electronic device with the same

According to one embodiment, in a level shift switch, a first input signal is inputted into a first input-output terminal, a first output signal is outputted from a second input-output terminal, a second input signal is inputted into the second input-output terminal, a second output signal is outputted from the first input-output terminal. The level shift switch includes a transmission circuit, a first MOSFET, a second MOSFET, and a first one-shot pulse generation circuit.

High Speed Level Shifter with Amplitude Servo Loop

A high speed level shifter interfaces a high speed DAC to the digital information that the DAC processes. The level shifter may convert CMOS level digital representations to, for example, CML level digital representations for processing by the DAC. The level shifter conserves the voltage swing in the CMOS level representations (e.g., about 1V). The level shifter also avoids voltage overstress, using a feedback loop to constrain the voltage amplitude, and thereby facilitates the use of fast thin film transistors in its architecture. 1. A circuit comprising:a supply input configured to provide a target high output level;a signal input configured to carry an input signal;a signal output configured to carry an output signal; and an amplitude control circuit connected to the supply input and the signal output;', 'an overvoltage protection circuit in series with the amplitude control circuit; and', 'a switching circuit in series with the overvoltage protection circuit and connected to the signal input., 'level translation circuitry configured to generate the output signal by shifting the input signal between a target low output level and the target high output level, the level translation circuitry comprising2. The circuit of claim 1 , where:the amplitude control circuit comprises an amplitude control transistor.3. The circuit of claim 1 , where:the overvoltage protection circuit comprises a cascode connected transistor in series with the amplitude control circuit and the switching circuit.4. The circuit of claim 1 , where:the amplitude control circuit comprises an amplitude control transistor;the amplitude control transistor comprises a gate; and where:the gate is connected to an amplitude control gate voltage.5. The circuit of claim 4 , further comprising:a feedback loop configured to provide the amplitude control gate voltage.6. The circuit of claim 5 , where the feedback loop comprises:a reference voltage input;a feedback voltage input connected to the signal output; ...

Level shifting apparatus and method of using the same

A level shifting apparatus includes a first capacitor, a first side of the first capacitor configured to receive a first voltage. The level shifting apparatus further includes an edge detector configured to receive the first voltage. The level shifting apparatus further includes an output inverter connected to a second side of the first capacitor, the output inverter configured to output an voltage-level shifted signal of the level shifting apparatus. The level shifting apparatus further includes a latch loop configured to receive feedback the output signal to an input of the output inverter, wherein the edge detector is configured to selectively interrupt feedback of the output signal to the input of the output inverter.

SWITCH BIASING USING ISOLATED NEGATIVE AND POSITIVE BIAS CIRCUITRY

A switch control circuit includes a positive voltage bias node, a voltage-regulated positive supply rail coupled to the positive voltage bias node, a charge pump coupled to a charge pump supply node, and a current source positive supply rail coupled to the charge pump supply node and configured to supply the charge pump. 1. A switch control circuit comprising:a positive voltage bias node;a voltage-regulated positive supply rail coupled to the positive voltage bias node;a charge pump coupled to a charge pump supply node; anda current source positive supply rail coupled to the charge pump supply node and configured to supply the charge pump.2. The switch control circuit of claim 1 , wherein the positive voltage bias node is at least partially isolated from the charge pump supply node.3. The switch control circuit of further comprising over-voltage protection clamp circuitry coupled to the charge pump supply node.4. The switch control circuit of wherein the over-voltage protection clamp circuitry includes a diode and a capacitor in parallel.5. The switch control circuit of wherein the over-voltage protection clamp circuitry includes a comparator circuit.6. The switch control circuit of wherein the over-voltage protection clamp circuitry includes a diode stack.7. The switch control circuit of further comprising level shifter circuitry configured to receive a positive bias voltage from the positive voltage bias node and receive a negative bias voltage from the charge pump.8. The switch control circuit of wherein the level shifter circuitry is further configured to provide a bias output to control one or more transistors of a switch circuit.9. The switch control circuit of further comprising a first transistor having a drain or source coupled to the positive voltage bias node and a second transistor having a drain or source coupled to the charge pump supply node.10. The switch control circuit of further comprising an amplifier having an output coupled to a gate of the ...

LEVEL SHIFTER

A level shifter includes an input stage circuit, a latch circuit and a transient speed-up circuit. The input stage circuit receives an input signal. The latch circuit is coupled to the input stage circuit through a first output terminal and a second output terminal, and determining steady-state levels of the first and the second output terminals according to the input signal. The transient speed-up circuit is coupled to the first and the second output terminals. When the transient speed-up circuit determines the first and the second output terminals are at the same logic level, the transient speed-up circuit accelerates the positive edge transition of the first or the second terminals. 1. A level shifter , comprising:an input stage circuit, receiving a first input signal and a second input signal, wherein the voltage levels of the first input signal and the second input signal are in an input level section, and the first input signal and the second input signal are out-of-phase;a latch circuit, coupled to the input stage circuit through a first output terminal and a second output terminal, the latch circuit and the input stage circuit determining the steady-state levels of the first output terminal and the second output terminal according to the first input signal and the second input signal, wherein the voltage levels of the first output terminal and the second output terminal are in an output level section, which is defined by a voltage on an output reference voltage terminal and a voltage on the ground terminal; and a first OR gate, having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal and the second input terminal of the first OR gate are coupled to the second output terminal and the first output terminal respectively, and the voltage level of an output signal of the first OR gate is in the output level section;', 'a fifth transistor, a control terminal of the fifth transistor coupled to the output ...

Serial communication apparatus

A serial communication apparatus includes a slew rate control circuit, an output circuit, a detection circuit, and a switching circuit. The slew rate control circuit has a predetermined impedance, and supplies a constant current from an output according to an input signal. In the output circuit, first capacitance is charged and discharged by the constant current from the slew rate control circuit. The output circuit outputs a digital signal from an output terminal according to a drive voltage. The noise detection circuit detects noise propagated from the output terminal, and outputs a switching signal according to a detection result. The switching circuit switches an impedance of the slew rate control circuit to a value smaller than the predetermined impedance according to the switching signal.

TRANSISTOR SWITCH WITH BACK-GATE BIASING

Driving a back-gate of a transistor with a follower signal that corresponds to an information signal. At least some of the illustrative embodiments are methods including: passing an information signal from a source terminal to an drain terminal of a main field effect transistor (FET), the information signal has a peak-to-peak voltage; generating a follower signal that corresponds to the information signal, the follower signal electrically isolated from the information signal, and the follower signal has a peak-to-peak voltage lower than the peak-to-peak voltage of the information signal; and applying the follower signal to a back-gate of the main FET. 1. A method , comprising:passing an information signal from a source terminal to a drain terminal of a main field effect transistor (FET), the information signal having a peak-to-peak voltage;generating a follower signal that corresponds to the information signal, the follower signal electrically isolated from the information signal, and the follower signal has a peak-to-peak voltage lower than the peak-to-peak voltage of the information signal; andapplying the follower signal to a back-gate of the main FET.2. The method of claim 1 , further comprising: grounding a gate of the main FET;', 'grounding the back-gate of the main FET; and', 'ceasing the generation of the follower signal., 'detecting that a select signal is not asserted, and responsive to the detecting that the select signal is not asserted3. The method of wherein grounding the back-gate further comprises grounding the back-gate through a first transistor.4. The method of further comprising claim 3 , responsive to the detecting that the select signal is not asserted claim 3 , grounding the gate of the main FET through a second transistor.5. The method of wherein generating the follower signal further comprises:operating a first follower transistor in an active region by driving a gate of the first follower transistor with the information signal; and ...

Semiconductor Device, and Display Device and Electronic Device Utilizing the Same

A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased.

LEVEL SHIFT CIRCUIT AND DRIVE CIRCUIT OF DISPLAY DEVICE

A display driver includes an input node for receiving display data, a level shift circuit configured to convert voltage level of the display data and output a first voltage and a second voltage based on the display data, an output node for outputting the output display data, a first P-channel MOS transistor coupled to the output node, whose gate is configured to input the first voltage, and a first N-channel MOS transistor coupled to the output node, whose gate is configured to input the second voltage, wherein a voltage difference between the second voltage and the first voltage varies based on the display data. 1. A display driver comprising:an input node for receiving display data;a level shift circuit configured to convert a voltage level of the display data and output a first voltage and a second voltage based on the display data;an output node for outputting the output display data;a first P-channel MOS (Metal-Oxide-Semiconductor) transistor coupled to the output node, the first P-channel MOS transistor including a gate that is configured to input the first voltage; anda first N-channel MOS transistor coupled to the output node, the first N-channel MOS transistor including a gate that is configured to input the second voltage,wherein a voltage difference between the second voltage and the first voltage varies based on the display data.2. The display driver according to claim 1 , wherein the level shift circuit further comprises:a first voltage generator configured to generate the voltage difference based on the display data, and output the first voltage and the second voltage.3. The display driver according to claim 2 , wherein the level shift circuit further comprises:a second N-channel MOS transistor including a gate that is configured to input the display data;a third N-channel MOS transistor including a gate that is configured to input an inverted display data which is inverted from the display data;a second P-channel MOS transistor including a gate that ...

Level shifter for power applications

A level shifter causes a switch to open or close by selecting one of two stored logical values to generate a gate-drive voltage to cause a transition in the switch.

Switch Driver Circuit And Associated Methods

A driver circuit for driving a switch includes a high output impedance driver circuit portion having a high impedance output node coupled to the control terminal of the transistor and a low output impedance driver circuit portion having a low impedance output node also coupled to the control terminal of the transistor. The slew rate of the control signal is established by at least one of the high impedance driver circuit portion and the low impedance driver circuit portion. 1. A driver circuit for driving a transistor having a control terminal responsive to a control signal having a slew rate during a slew time interval , comprising:a first driver circuit portion having an first output node coupled to the control terminal of the transistor and having a first output impedance; anda second driver circuit portion having a second output node coupled to the control terminal of the transistor and having a second output impedance, lower than the first output impedance, wherein the slew rate of the control signal is established by at least one of the first driver circuit portion and the second driver circuit portion.2. The driver circuit of wherein the first driver circuit portion has a first input responsive to a feedback signal claim 1 , a second input responsive to a reference signal claim 1 , and generates an output signal at the first output node.3. The driver circuit of wherein the first driver circuit portion comprises a differential amplifier comprising the first input and the second input and a current mirror coupled to an output of the differential amplifier.4. The driver circuit of wherein the differential amplifier comprises an operational transconductance amplifier.5. The driver circuit of wherein the second driver circuit portion comprises a pre-driver circuit coupled to the first driver circuit portion and a transistor having a control terminal and an output terminal claim 1 , wherein the control terminal of the transistor is responsive to the pre-driver ...

LEVEL SHIFTING IN A GAN HALF BRIDGE CIRCUIT

A half bridge GaN circuit is disclosed. The half bridge GaN circuit includes a first power node having a first power voltage, where the first power voltage is referenced to a switch voltage at the switch node. The half bridge GaN circuit also includes a VMID power node having a VMID power voltage, where the VMID power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage. The half bridge GaN circuit also includes a logic circuit, where a negative power terminal of the logic circuit is connected to the VMID node, and where a positive power terminal of the first logic circuit is connected to the first power node, where the logic circuit is configured to generate a logic output voltage, which controls the conductivity of the high side power switch. 1. A GaN half bridge circuit , comprising:a switch node;a low side power switch configured to selectively conduct current from the switch node according to one or more input signals;a high side power switch configured to selectively conduct current to the switch node according to the one or more input signals;a first power node having a first power voltage, wherein the first power voltage is referenced to a switch voltage at the switch node;a VMID power node having a VMID power voltage, wherein the VMID power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage; anda logic circuit, wherein a negative power terminal of the logic circuit is connected to the VMID node, and wherein a positive power terminal of the logic circuit is connected to the first power node, wherein the logic circuit is configured to generate a logic output voltage, which controls a conductivity of the high side power switch.2. The half bridge circuit of claim 1 , further comprising a control level shift circuit comprising a level shift transistor claim 1 , wherein the control level shift circuit is configured to cause the logic circuit to cause the ...

Frontside-to-Backside Intermixing Architecture

Various implementations described herein are related to various devices having a frontside power network with frontside supply rails and a backside power network with backside supply rails. The device may include intermixing architecture with transition vias that couple the frontside power network to the backside power network. The intermixing architecture may transition the frontside supply rails of the frontside power network to the backside supply rails of the backside power network.

LOW VOLTAGE BANDGAP REFERENCE GENERATOR

A reference voltage generator circuit having a feedback circuit connected to an output branch. The circuit has a first branch, having a first current and a first voltage, a second branch, having a second current and a second voltage, and a third branch, having a third current and a third voltage. The circuit has an amplifier that couples the first voltage to the second voltage. The circuit also has a feedback circuit that couples the third voltage to at least one of the first or second voltages. 1. A reference voltage generator circuit , comprising:a first branch having a first transistor, a first impedance in series with the first transistor and a first terminal between the first transistor and the first impedance;a second branch having a second transistor, a second impedance in series with the second transistor and a second terminal between the second transistor and the second impedance;a third branch having a third transistor, a third impedance in series with the third transistor, a fourth transistor coupled between the third transistor and the third impedance and a third terminal coupled between the third transistor and the fourth transistor; a first input coupled to the first terminal;', 'a second input coupled to the second terminal; and', 'a first output coupled to respective control terminals of the first, second and third transistors;, 'a first amplifier having a first input coupled to the third terminal; and', 'a second input coupled to the first terminal or the second terminal; and', 'a second output coupled to a control terminal of the fourth transistor., 'a second amplifier having2. The reference voltage generator circuit of claim 1 , further comprising:a fourth branch, the fourth branch comprising a fifth transistor, a fourth impedance in series with the fifth transistor, and a sixth transistor coupled between the fifth transistor and the fourth impedance,wherein the second output of the second amplifier is coupled to a control terminal of the sixth ...

Memory cell with two anti-fuse elements

A memory cell includes a first anti-fuse element, a second anti-fuse element, and a selection circuit. The first anti-fuse element has a first terminal, a second terminal being floating, and a control terminal coupled to a first anti-fuse control line. The second anti-fuse element has a first terminal coupled to the first terminal of the first anti-fuse element, a second terminal being floating, and a control terminal coupled to a second anti-fuse control line. The selection circuit is coupled to the first terminal of the first anti-fuse element, the first terminal of the second anti-fuse element, and a source line. The selection circuit controls an electrical connection from the source line to the first terminal of the first anti-fuse element and the first terminal of the second anti-fuse element.

DATA INTERFACE, CHIP, AND CHIP SYSTEM

A data interface is disclosed, which includes an electrostatic discharge circuit, and a charge transmitting circuit connected to a binding wire through the electrostatic discharge circuit; the charge transmitting circuit includes a first capacitor, the charge transmitting circuit transfers charges in the first capacitor to a parasitic capacitor of the electrostatic discharge circuit and a parasitic capacitor of the binding wire, to generate a first voltage signal and output the first voltage signal through the binding wire. According to the data interface, charges in a charging capacitor and a parasitic capacitor are redistributed, which could not only reduce a power consumption loss caused by a parasitic capacitor in a communication channel but also effectively reduce time delay. In addition, the use of dual-wire communication is avoided by using single-wire communication, and the manufacturing costs are reduced relative to low-voltage differential signaling (LVDS). 1. A data interface comprising:an electrostatic discharge circuit; anda charge transmitting circuit connected to a binding wire through the electrostatic discharge circuit, wherein the charge transmitting circuit comprises a first capacitor, the charge transmitting circuit transfers charges in the first capacitor to a parasitic capacitor of the electrostatic discharge circuit and a parasitic capacitor of the binding wire, to generate a first voltage signal and output the first voltage signal through the binding wire.2. The data interface according to claim 1 , wherein the charge transmitting circuit further comprises:a first MOS transistor, a second MOS transistor and a third MOS transistor;wherein a source of the first MOS transistor is configured to receive a power supply voltage, a drain of the first MOS transistor is connected to the ground through the first capacitor, a gate of the first MOS transistor is configured to receive a first control signal, the drain of the first MOS transistor is ...

SYMMETRICAL DUAL VOLTAGE LEVEL INPUT-OUTPUT CIRCUITRY

In a described example, an apparatus includes a driver circuit coupled to an output pad, the driver having a p-channel FET coupled between a positive peripheral voltage and the pad, and having a first gate terminal coupled to a first gate control signal, and an n-channel FET coupled between the pad and a ground terminal and having a second gate terminal coupled to a second gate control signal. A predriver circuit is coupled to receive a data signal for output to the pad and further coupled to output the first gate control signal; and the predriver circuit is coupled to output a supply voltage to the first gate control signal in a first mode, and to output a bias voltage less than the supply voltage to the first gate control signal in a second mode; and a bias circuit is coupled for outputting the bias voltage. 1. An apparatus , comprising:a driver circuit coupled to an output pad, the driver having a p-channel FET coupled between a positive peripheral voltage and the pad, and having a first gate terminal coupled to a first gate control signal, and an n-channel FET coupled between the pad and a ground terminal and having a second gate terminal coupled to a second gate control signal;a predriver circuit configured to receive a data signal for output to the pad and further configured to output the first gate control signal and to output the second gate control signal, the predriver circuit configured to output a supply voltage to the first gate control signal in a first mode, and to output a bias voltage less than the supply voltage to the first gate control signal in a second mode, the predriver circuit configured to output the supply voltage to the second gate control signal in both the first and second modes; anda bias circuit for outputting the bias voltage.2. The apparatus of claim 1 , wherein the p-channel FET comprises a p-channel drain extended MOS (DEMOS) transistor.3. The apparatus of claim 2 , wherein the p-channel DEMOS transistor has a source terminal ...

HIGH-VOLTAGE TOLERANT LEVEL SHIFTER USING THIN-OXIDE TRANSISTORS AND A MIDDLE-OF-THE-LINE (MOL) CAPACITOR

A level shifter according to some embodiments is disclosed. In some embodiments, a level shifter includes a middle-of-the-line (MOL) capacitor; and a circuit including at least one thin-film transistor coupled to the MOL capacitor, wherein an input voltage provided to the MOL capacitor is split between the MOL capacitor and the circuit. The MOL capacitor can be formed with a contact strip adjacent to a gate structure. A method of forming a level shifter using thin-oxide technologies includes forming a middle-of-the-line (MOL) capacitor; forming a circuit with one or more thin-film transistors; and coupling the MOL capacitor to the circuit such that an input voltage provided at the MOL capacitor is split between the MOL capacitor and the circuit. 1. A level shifter , comprising:a middle-of-the-line (MOL) capacitor; anda circuit including at least one thin-film transistor coupled to the MOL capacitor,wherein an input voltage provided to the MOL capacitor is split between the MOL capacitor and the circuit.2. The level shifter of claim 1 , wherein the MOL capacitor includesa gate; anda contact formed adjacent the gate.3. The level shifter of claim 2 , wherein the gate and the contact are formed with an advanced process.4. The level shifter of claim 3 , wherein the gate and the contact are formed with a 7 nm process technology.5. The level shifter of claim 2 , wherein the gate is a fin and the contact is a strip formed adjacent the gate.6. The level shifter of claim 5 , wherein the gate and the contact are characterized by a height and a width.7. The level shifter of claim 6 , wherein a capacitance of the MOL capacitor is determined by the height and the width.8. The level shifter of claim 7 , wherein the capacitance of the MOL capacitor is set according to an input voltage slew such that an internal voltage remains below a maximum voltage.9. The level shifter of claim 1 , wherein the circuit includes a latch circuit coupled to an inverter.10. The level shifter of claim ...

Level-Shifter with Defined Power-up State and Increased Density

A level-shifter is provided in which the devices may all be sized approximately the same yet a known startup state is provided at power-up by forming the level-shifter using a one-sided NMOS latch. The one-sided NMOS latch is powered through a pair of head-switch transistors. A pair of pull-down transistors function to flip a binary state for the one-sided NMOS latch. 1. A level-shifter , comprising:an inverter PMOS transistor;an inverter NMOS transistor having a drain coupled to the a drain of the inverter PMOS transistor,a non-inverter PMOS transistor having a drain coupled to a gate for the inverter PMOS transistor and to a gate for the inverter NMOS transistor, wherein the drain of the inverter PMOS transistor is coupled to a gate for the non-inverter PMOS transistor;a first pull-down transistor coupled between a drain of the non-inverter PMOS transistor and ground, wherein a gate for the first pull-down transistor is coupled to a first input signal node carrying an input signal from a first power domain powered by a first power supply voltage; anda first head-switch transistor coupled between a source of the non-inverter PMOS transistor and a power supply node configured to supply a second power supply voltage for a second power domain, the second power supply voltage being greater than the first power supply voltage, wherein a gate for the first head-switch transistor is coupled to the input signal node.2. The level-shifter of claim 1 , further comprising a second pull-down transistor coupled between a drain of the inverter PMOS transistor and ground claim 1 , wherein a gate for the second pull-down transistor is coupled to a complement input signal node carrying a complement of the input signal.3. The level-shifter of claim 2 , further comprising a second head-switch transistor coupled between a source of the inverter PMOS transistor and the power supply node claim 2 , and wherein a gate of the second head-switch transistor is coupled to the complement input ...

LOW CURRENT, WIDE RANGE INPUT COMMON MODE LVDS RECEIVER DEVICES AND METHODS

In various embodiments, the present disclosure provides low-voltage differential signaling (LVDS) receiver circuits, electronic devices, and methods. In one embodiment, a LVDS receiver includes an input differential pair of transistors that receive a differential input signal. The input differential pair includes a first NMOS transistor that receives a first input signal and a second NMOS transistor that receives a second input signal. A third NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the first NMOS transistor, and a fourth NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the second NMOS transistor. A first level shifter is coupled to a gate of the third NMOS transistor, and a second level shifter is coupled to a gate of the fourth NMOS transistor. 1. A low-voltage differential signaling (LVDS) receiver , comprising: a first NMOS transistor configured to receive a first input signal of the differential input signal; and', 'a second NMOS transistor configured to receive a second input signal of the differential input signal;, 'an input differential pair of transistors configured to receive a differential input signal, the input differential pair includinga third NMOS transistor having a source terminal coupled to a source terminal of the first NMOS transistor, the third NMOS transistor having a drain terminal coupled to a drain terminal of the first NMOS transistor;a fourth NMOS transistor having a source terminal coupled to a source terminal of the second NMOS transistor, the fourth NMOS transistor having a drain terminal coupled to a drain terminal of the second NMOS transistor;a first level shifter coupled to a gate of the third NMOS transistor; anda second level shifter coupled to a gate of the fourth NMOS transistor.2. The LVDS receiver of wherein the first level shifter comprises a first PMOS transistor claim 1 , and the second level shifter comprises ...

LEVEL SHIFTER WITH BUILT-IN LOGIC FUNCTION FOR REDUCED DELAY

A method and circuit for implementing a level shifter with built-in-logic function for reduced delay. The circuit including at least one set of inputs from a first power supply domain. The circuit further including at least two cross coupled field effect transistors (FETs) connected to a second power supply domain. The circuit further including a true logic gate connected to the first power supply domain and the at least two cross coupled FETs. The true logic gate being configured to generate a logic function based on the at least one set of inputs. The circuit further including a complementary logic gate connected to the first power supply domain and the at least two cross coupled FETs. The complementary logic gate being configured to generate a complement of the logic function based on the at least one set of inputs. 1. A circuit comprising:at least one set of inputs from a first power supply domain;at least two cross coupled field effect transistors (FETs) connected to a second power supply domain, wherein the at least two cross coupled FETs are pFETs;a true logic gate connected to the first power supply domain and the at least two cross coupled FETs, wherein the true logic gate is comprised of at least one nFET and configured to generate a logic function based on the at least one set of inputs; anda complementary logic gate connected to the first power supply domain and the at least two cross coupled FETs, wherein the complementary logic gate is comprised of at least one nFET and configured to generate a complement of the logic function based on the at least one set of inputs,wherein the pFETs and nFETs are thin-oxide FETs.2. The circuit of claim 1 , wherein:a source of one of the at least two cross coupled FETs is connected to the second power supply domain;a source of another of the at least two cross coupled FETs is connected to the second power supply domain;a drain of the one of the at least two cross coupled FETs is connected to a drain of the true logic ...

Multiple Voltage Input Buffer and Related Method

A device includes a first level shifter, a switch, and a control circuit. The first level shifter is electrically connected to a pad. The switch has an input terminal electrically connected to an input terminal of the first level shifter, and an output terminal electrically connected to an output terminal of the first level shifter. The control circuit is electrically connected to a control terminal of the switch. 1. A device comprising:a first level shifter electrically connected to a pad; an input terminal electrically connected to an input terminal of the first level shifter; and', 'an output terminal electrically connected to an output terminal of the first level shifter; and, 'a switch havinga control circuit electrically connected to a control terminal of the switch.2. The device of claim 1 , wherein the switch is a P-type metal-oxide-semiconductor (PMOS) transistor.3. The device of claim 1 , wherein the control circuit comprises:a second level shifter electrically connected to the pad;an inverter electrically connected to the second level shifter;a third level shifter electrically connected to the inverter and the control terminal of the switch; anda fourth level shifter electrically connected to the second level shifter and the control terminal of the switch.4. The device of claim 3 , wherein the second level shifter comprises: a first electrode electrically connected to the pad; and', 'a second electrode electrically connected to an input terminal of the inverter; and, 'a first transistor having a first electrode electrically connected to the input terminal of the inverter; and', 'a control electrode electrically connected to the first electrode of the first transistor., 'a second transistor having5. The device of claim 4 , wherein the second level shifter further comprises:a resistor having a first terminal electrically connected to the pad, and a second terminal electrically connected to the first electrode of the first transistor.6. The device of claim 4 ...

Driver for a shared bus, in particular a lin bus

A driver for a shared bus, such as a LIN bus, having a supply node (Vbat), a bus node (LIN), a transmit data input node (TX) and a receive data output node (RX), said driver comprising: a pull-up circuitry between the supply node and the bus node, driver circuitry (100) having a control input connected to the transmit data input node, feedback circuitry (200) configured to provide feedback from the shared bus to the control input of the driver circuitry; said feedback circuitry comprising copy circuitry (210) configured to obtain at least one copy signal representative for a signal on the bus node, filter circuitry (220) configured to low-pass filter the at least one copy signal, derivative circuitry (230) configured to obtain at least one derivative signal representative for the speed at which the signal on the bus node varies.

SEMICONDUCTOR DEVICE, DISPLAY MODULE, AND ELECTRONIC DEVICE

To reduce power consumption and perform high-speed switching in boosting a voltage to a desired voltage. A semiconductor device includes a first buffer circuit, a level-shift circuit, and a second buffer circuit. The first buffer circuit includes a tri-state buffer circuit. The tri-state buffer circuit has a function of making each of an output of an input signal and an output of an inverted input signal into a resting state in response to a standby signal. The level-shift circuit includes a current mirror circuit, a differential amplifier circuit, and a switch circuit. The differential amplifier circuit has a function of controlling a current flowing through the current mirror circuit using the input signal and the inverted input signal as differential signals. The switch circuit has a function of making a current flowing through the differential amplifier circuit into a resting state in response to the standby signal. 1. A semiconductor device comprising:a first buffer circuit and a second buffer circuit; anda level-shift circuit between the first buffer circuit and the second buffer circuit,wherein the first buffer circuit comprises a tri-state buffer circuit configured to make each of an output of an input signal and an output of an inverted input signal into a resting state in response to a standby signal, a current mirror circuit;', 'a differential amplifier circuit configured to control a current flowing through the current mirror circuit in response to the input signal and the inverted input signal; and', 'a switch circuit configured to make a current flowing through the differential amplifier circuit into a resting state in response to the standby signal., 'wherein the level-shift circuit comprises2. The semiconductor device according to claim 1 ,wherein each of the differential amplifier circuit and the switch circuit comprise a n-channel transistor, andwherein the current mirror circuit comprises a p-channel transistor.3. The semiconductor device ...

Input/output circuit

An input/output circuit includes a first switch element, a control voltage providing circuit and a floating voltage providing circuit. The first switch element includes a control terminal, a first path terminal, a second path terminal and a base terminal. The first path terminal receive a first voltage, and the second path terminal receives a second voltage. The control voltage providing circuit provides a control voltage to the control terminal of the first switch element. The floating voltage providing circuit provides the larger between the first voltage and the second voltage to the base terminal of the first switch element, so as to prevent a leakage current from being generated between the first voltage source or the second voltage source and the base terminal of the first switch element.

LEVEL SHIFT CIRCUIT AND FINGERPRINT IDENTIFICATION DEVICE

A level shift circuit includes a complementary signal generating unit, a high voltage pulse generating unit, and a shift and latch uni. The high voltage pulse generating unit is connected to the complementary signal generating unit and the shift and latch unit. The complementary signal generating unit is used to receive a target signal at a low voltage domain and output a complementary signal of the target signal and the target signal. The high voltage pulse generating unit is used to generate a high voltage pulse according to the target signal and complementary signa. Tthe shift and latch unit is used to shift the target signal from the low voltage domain to a high voltage domain when a high voltage pulse is generated, and is used to latch and output the target signal at the high voltage domain. 1. A level shift circuit , comprising: a complementary signal generating unit , a high voltage pulse generating unit , and a shift and latch unit , wherein:the complementary signal generating unit is used to receive a target signal at a low voltage domain and output a complementary signal of the target signal and the target signal;the high voltage pulse generating unit comprises a first transistor, a second transistor, a first high voltage transistor, a second high voltage transistor, a first phase inverter, a first delay, a second phase inverter and a second delay; sources of the first transistor and second transistor are grounded, and gates thereof are used to receive the complementary signal and the target signal respectively; the first delay receives the complementary signal through the first phase inverter and the second delay receives the target signal the second phase inverter; sources of the first high voltage transistor and second high voltage transistor are respectively connected to drains of the first transistor and second transistor, gates thereof are respectively connected to the first delay to receive the target signal and the second delay to receive the ...

LEVEL SHIFTER CIRCUIT, CORRESPONDING DEVICE AND METHOD

A level-shifter circuit operates to shift an input signal referenced to a first set supply voltages to generate an output signal referenced to a second set of supply voltages. The output signal from the level-shifter circuit is latched by a latching circuit. A logic gate has a first input configured to receive the input signal, a second input configured to receive a feedback signal and an output coupled to a input of the level shifting circuit. A feedback circuit has a first input configured to receive the output signal, a second input configured to receive the input signal and an output configured to generate the feedback signal. The feedback circuit operates to sense an uncontrolled switching event of the output signal occurring in the absence of a switching of the input signal and apply, in response thereto, the feedback signal to cancel the uncontrolled switching event. 1. A circuit , including:a first circuit powered from a first set of a supply node and a ground, the first circuit including at least one first switching element configured for receiving a switching input signal, i) at least one second switching element coupled to the at least one first switching element in the first circuit section, the at least one second switching element in the second circuit section configured for switching as a result of switching of the at least one first switching element in the first circuit section, and', 'ii) a latch circuit block driven by the at least one second switching element and having at least one latch output, wherein switching of the at least one latch output is controlled by switching of the at least one second switching element in the second circuit section to provide at least one latch output level-shifted replica of the switching input signal applied to the at least one first switching element in the first circuit section, and, 'a second circuit powered from a second set of a supply node and a ground, wherein the second circuit section includesa feedback ...

SIGNAL TRANSMISSION CIRCUIT, SWITCH DRIVING DEVICE, AND POWER MODULE

A filter circuit includes a first rise delay circuit that delays a rising time of a first shifted signal by a predetermined time for output and a first fall delay circuit that delays a falling time of a second shifted signal by a predetermined time for output. The first rise delay circuit is configured so that a second rise delay signal does not follow a change in a first voltage toward a decreasing side and follows a change in the first voltage toward an increasing side. The first fall delay circuit is configured so that a second fall delay signal does not follow a change in the first voltage toward a decreasing side and follows a change in the first voltage toward an increasing side. 1. A signal transmission circuit comprising:a level shifter that is actuated with a first voltage and a second voltage, which is lower than the first voltage, and level-shifts each of a first input signal and a second input signal to output a first shifted signal and a second shifted signal; anda filter circuit that is actuated with the first voltage and the second voltage and performs a filtering process on each of the first shifted signal and the second shifted signal, wherein a first rise delay circuit that delays a rising time of the first shifted signal by a predetermined time for output, and', 'a first fall delay circuit that delays a falling time of the second shifted signal by a predetermined time for output, wherein', 'the first rise delay circuit includes a first rise delay NOT circuit that inverts the first shifted signal for output and a second rise delay NOT circuit that inverts a first rise delay signal of the first rise delay NOT circuit,', 'the first fall delay circuit includes a first fall delay NOT circuit that inverts the second shifted signal for output and a second fall delay NOT circuit that inverts a first fall delay signal of the first fall delay NOT circuit for output,', 'the first rise delay circuit is configured so that a second rise delay signal of the ...

HIGH-VOLTAGE OUTPUT DRIVER FOR A SENSOR DEVICE WITH REVERSE CURRENT BLOCKING

A high-voltage output driver () for a sensor device () with reverse current blocking comprises a supply node (SN) to apply a supply voltage (VHV) and an output node (OP) to provide an output signal (OS) of the high-voltage output driver (). The high-voltage output driver () comprises a driver transistor (MP) being disposed between the supply node (SN) and the output node (OP). The high-voltage output driver () further comprises a bulk control circuit () to apply a bulk control voltage (Vwell) to a bulk node (BMP) of the driver transistor (MP), and a gate control circuit () to apply a gate control voltage (GCV) to thegate node (GMP) of the driver transistor (MP). 1. A high-voltage output driver for a sensor device with reverse current blocking , comprising:a supply node to apply a supply voltage,an output node to provide an output signal of the high-voltage output driver,a driver transistor being disposed between the supply node and the output node,a bulk control circuit to apply a bulk control voltage to a bulk node of the driver transistor,a gate control circuit to apply agate control voltage to the gate node of the driver transistor.2. The high-voltage output driver of claim 1 ,wherein the high-voltage output driver is operated in a first operation mode in which the potential at the output node is lower than the supply voltage, and in a second operation mode in which the potential at the output node is higher than the supply voltage,wherein the bulk control circuit is configured to apply the level of a bulk control voltage to the bulk node of the driver transistor in dependence on operating the high-voltage output driver in the first and second operation mode,wherein the gate control circuit is configured to apply the level of the gate control voltage to the gate node of the high side driver transistor in dependence on operating the high-voltage output driver in the first and second operation mode.3. The high-voltage output driver of claim 1 ,wherein the bulk ...

APPARATUSES AND METHODS FOR LEVEL SHIFTING

Apparatuses and methods for level shifting in a semiconductor device are described. An example apparatus includes: a splitter circuit that operates on a first voltage potential to produce a first signal having a first polarity and a second signal having a second polarity that is substantially opposite to the first polarity; an one-shot pulse circuit that operates on the first voltage potential to produce a first one-shot pulse signal responsive to the first signal and a second one-shot pulse signal responsive to the second signal; and a logic circuit configured to operate on a second voltage potential to produce a third signal responsive to the first and second one-shot pulse signals, the second voltage potential being different from the first voltage potential. 1. A level shifter circuit comprising:a splitter circuit configured to operate on a first voltage potential to provide a first signal having a first polarity and a second signal having a second polarity that is substantially opposite to the first polarity;a one-shot pulse generator circuit configured to operate on the first voltage potential to provide a first one-shot pulse signal responsive to the first signal and a second one-shot pulse signal responsive to the second signal; anda logic circuit configured to operate on a second voltage potential to provide a third signal responsive to the first and second one-shot pulse signals, the second voltage potential being different from the first voltage potential.2. The level shifter circuit of claim 1 , wherein the logic circuit comprises:a pulse generator configured to produce fourth and fifth signals responsive to the first and second one-shot pulse signals; andan XOR gate configured to produce the third signal responsive to the fourth and fifth signals.3. The level shifter circuit of claim 1 , wherein a cycle period of the fourth signal is twice a cycle period of the first signal claim 1 , andwherein a cycle period of the fifth signal is twice a cycle period ...

Half bridge power conversion circuits using gan devices

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Integrated bias supply, reference and bias current circuits for gan devices

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

INTEGRATED LEVEL SHIFTER

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits. 1. A semiconductor device comprising:a level shift transistor having a ratio of output saturation current (Idsat) to output capacitor charge (Qoss) of greater than 1 ampere per nanocoulomb.2. The semiconductor device of wherein the level shift transistor is GaN-based.3. The semiconductor device of wherein the level shift transistor has less than 25 picocoulombs of output charge (Qoss).4. The semiconductor device of wherein the level shift transistor is operated with a pulsed input signal.5. The semiconductor device of wherein a duration of the pulsed input signal is less than 100 nanoseconds.6. The semiconductor device of wherein a channel width of the level shift transistor is less than 100 microns.7. The semiconductor device of wherein a drain structure of the level shift transistor is placed less than 100 microns from a bond pad.8. The semiconductor device of wherein the level shift transistor includes a source ohmic contact area connected to a source terminal claim 1 , and the source terminal is connected to a metal pad that is immediately adjacent to the source terminal and is more than 100 times the source ohmic contact area.9. The semiconductor device of wherein the level shift transistor includes a drain ohmic contact area connected to a drain terminal claim 1 , and the drain terminal is connected to a metal pad that is immediately adjacent to the drain terminal and ...

LEVEL SHIFT AND INVERTER CIRCUITS FOR GAN DEVICES

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits. 1. A level shift circuit comprising: a first input terminal;', 'a first output terminal; and', 'a first inversion circuit coupled between the first input and the first output terminals and configured to receive a first input logic signal at the first input terminal and in response, provide a first inverted output logic signal at the first output terminal, wherein the first input and the first inverted output logic signals can be referenced to different voltage potentials., 'a first GaN-based inverter circuit comprising2. The level shift circuit of wherein the first inversion circuit is configured to be capable of operating with the first inverted output logic signal referenced to a voltage that is more than 20 volts higher than a reference voltage for the first input logic signal.3. The level shift circuit of wherein the first inversion circuit comprises a first GaN-based enhancement-mode transistor having a gate coupled to the first input terminal claim 1 , a drain coupled to the first output terminal claim 1 , and a source coupled to a ground.4. The level shift circuit of wherein the first inversion circuit further comprises a current sink device coupled between the source and the ground.5. The level shift circuit of wherein the first inversion circuit further comprises a pull up device coupled between the drain and a floating power supply.6. The level shift circuit of ...

PULSED LEVEL SHIFT AND INVERTER CIRCUITS FOR GAN DEVICES

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits. 1. A level shift circuit comprising: a first input terminal;', 'a first output terminal;', 'a first GaN-based enhancement-mode transistor having a gate coupled to the first input terminal, a drain coupled to the first output terminal, and a source coupled to a ground; and', 'a first pull up device coupled between the drain of the first GaN-based enhancement-mode transistor and a power supply; and, 'a first inverter circuit comprising a second input terminal;', 'a second output terminal;', 'a second GaN-based enhancement-mode transistor having a gate coupled to the second input terminal, a drain coupled to the second output terminal, and a source coupled to the ground; and', 'a second pull up device coupled between the drain of the second GaN-based enhancement-mode transistor and the power supply,', 'wherein the first pull up device comprises a third GaN-based transistor having a gate voltage which is different from a voltage at the first output terminal, and, 'a second inverter circuit comprisingwherein the first, second, and third transistors are of the same conductivity type.2. The level shift circuit of wherein voltages generated at the first and the second input terminals are referenced to a first voltage that is a ground claim 1 , and voltages generated at the first and the second output terminals are referenced to a second voltage at a different potential than ground. ...

Multi-Channel Clock Distribution Circuit and Electronic Device

A multi-channel clock distribution circuit and an electronic device includes a power source, a first switch, and at least two clock distribution sub-circuits; each clock distribution sub-circuit includes a second switch, a third switch, and a capacitor; a first end of the capacitor is connected to the power source by using the second switch and is connected to the first end of the first switch by using the third switch, a second end of the capacitor is grounded, and the first end of the capacitor is used as an output end of the clock distribution sub-circuits; and connection and disconnection of the first switch is controlled by a first clock signal, connection and disconnection of the second switch is controlled by a second clock signal, and connection and disconnection of the third switch is controlled by a third clock signal.

HIGH-SIDE POWER SWITCH CONTROL CIRCUIT

A circuit for controlling a high-side power switch includes a level shifting circuit configured to receive an input signal for selectively configuring a logic command circuit to be in a set state, for providing a first output signal to the high-side power switch, and in a reset state, for providing a second output signal, different from the first output signal, to the high-side power switch. The circuit also includes a regulation circuit configured to detect an indicative signal indicative of the output signal provided to the high-side power switch and to change sensitivity of the level shifting circuit to the input signal, based on the indicative signal that is detected. 1. A circuit for controlling a high-side power switch comprising:a level shifting circuit configured to receive an input signal for selectively configuring a logic command circuit to be in a set state, for providing a first output signal to the high-side power switch, and in a reset state, for providing a second output signal, different from the first output signal, to the high-side power switch; anda regulation circuit configured to detect an indicative signal, indicative of the output signal provided to the high-side power switch, and to change sensitivity of the level shifting circuit to the input signal based on the indicative signal that is detected.2. The circuit in accordance with claim 1 , wherein the regulation circuit is configured to arrange the level shifting circuit to be in a set-dominant configuration claim 1 , in which the sensitivity of the level shifting circuit to the input signal for configuring the logic command circuit to a reset state is reduced claim 1 , in a period during which the detected indicative signal that is detected indicates a transition from the second output signal to the first output signal.3. The circuit in accordance with claim 1 , wherein the regulation circuit is configured to arrange the level shifting circuit to be in a set-dominant configuration claim 1 ...

POWER SUPPLY VOLTAGE SWITCHING CIRCUIT CAPABLE OF PREVENTING CURRENT LEAKAGE

A power supply voltage switching circuit includes a power selecting module, a level shifting module, and a supply switching module. The power selecting module receives a first supply signal and a second supply signal, and outputs an intermediate supply signal according to the first supply signal and the second supply signal. The level shifting module receives the intermediate supply signal as a power supply, and generates a first shifted signal and a second shifted signal by shifting voltage levels of a first control signal and a second control signal respectively. The supply switching module receives the first supply signal and a third supply signal, and generates an output signal according to the first shifted signal, the second shifted signal, the first control signal, and the second control signal. 1. A power supply voltage switching circuit comprising:a power selecting module configured to receive a first supply signal and a second supply signal, and output an intermediate supply signal according to the first supply signal and the second supply signal;a level shifting module coupled to the power selecting module for receiving the intermediate supply signal as a power supply of the level shifting module, and configured to receive a first control signal and a second control signal, and generate a first shifted signal and a second shifted signal by shifting voltage levels of the first control signal and the second control signal respectively; and a first transistor having a first terminal configured to receive the first supply signal, a second terminal, and a control terminal configured to receive the first control signal;', 'a second transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to an output terminal of the power supply voltage switching circuit, and a control terminal configured to receive the first shifted signal;', 'a third transistor having a first terminal configured to receive a third ...

Glitch preventing input/output circuits

Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter.

SIGNAL PROCESSING DEVICES AND METHODS

A pre-driver circuit is provided. The pre-driver circuit includes a switch circuit, a common-mode voltage control circuit, and a current supply circuit. The switch circuit receives differential input signals, outputs differential output signals, and controls switching between a high level and a low level of the differential output signals and the differential input signals. The common-mode voltage control circuit is coupled to the switch circuit. The common-mode voltage control circuit receives a reference voltage and controls a common-mode voltage of the differential output signals according to the reference voltage. The current supply circuit is coupled to the switch circuit and the common-mode voltage control circuit. The current supply circuit provides a driving current for the switch circuit and the common-mode voltage control circuit. 1. A pre-driver circuit comprising:a switch circuit, receiving differential input signals, outputting differential output signals, and controlling switching between a high level and a low level of the differential output signals and the differential input signals;a common-mode voltage control circuit, coupled to the switch circuit, receiving a reference voltage and controlling a common-mode voltage of the differential output signals according to the reference voltage; anda current supply circuit, coupled to the switch circuit and the common-mode voltage control circuit, providing a driving current for the switch circuit and the common-mode voltage control circuit.2. The pre-driver circuit as claimed in claim 1 ,wherein the switch circuit comprises a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor,wherein gates of the first PMOS transistor and the second PMOS transistor receive the differential input signals respectively, sources of the first PMOS transistor and the second PMOS transistor output the ...

Integrated level translator and latch for fence architecture

The present disclosure relates to integrated level translator and latch circuits and, more particularly, to an integrated level translator and latch circuits for fence architectures in SRAM cells. The integrated level translator and latch for input signals includes a first clock (CLKS) and a second clock (CLKH). The first clock (CLKS) is used as a precharge and evaluation clock with its timing being critical for forward edge and the second clock (CLKH) is a latch clock.

Fast Voltage Level Shifter Circuit

A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate. 117-. (canceled)18. A circuit comprising:a switch configured to produce an output voltage on an output terminal in response to an input voltage applied to an input terminal and in response to a current drawn through the switch;a current mirror circuit having a control input and configured to draw the current through the switch in response to the control input; anda charge storage circuit connected to the input terminal and to the control input of the current mirror circuit, wherein the charge storage circuit is configured to discharge a stored charge into the control input in response to the input voltage.19. The circuit of claim 18 , wherein the charge storage circuit comprises a capacitor connected between the input terminal and the control input of the current mirror circuit.20. The circuit of claim 18 , wherein the charge storage circuit comprises:a first diode;a capacitor connected to a first anode of the first diode, wherein a first cathode of the first diode is connected to the control input of the current mirror circuit; anda second diode, wherein a second cathode of the second diode is connected to the first anode.21. The circuit of claim 18 , further comprising an inverting amplifier claim 18 , wherein the charge storage circuit is connected to the input terminal through the inverting amplifier.22. The circuit of claim 18 , further comprising:a resistor connected between ...

Method and System for Increasing Efficiency and Controlling Slew Rate in DC-DC Converters

One embodiment pertains to a method including transitioning a logic state of at least one enable signal. A first power transistor begins to turn off. A parameter level of the input of the first power transistor is directly sensed. A second power transistor is turned off when the parameter level is less than a threshold level. 1. An apparatus , comprising:a first driver having first and second inputs, and first and second outputs;wherein the first output is configured to be coupled to a first terminal of a first slew resistor having a second terminal coupled to an input of a first power transistor;wherein the second output is configured to be coupled to a third terminal of a second slew resistor having a fourth terminal coupled to the input of the first power transistor;a second driver having third and fourth inputs and third and fourth outputs;wherein the third output is configured to be coupled to a fifth terminal of a third slew resistor also having a sixth terminal coupled to an input of a second power transistor;wherein the fourth output is configured to be coupled to a seventh terminal of a fourth slew resistor also having an eighth terminal coupled to an input of the second power transistor;wherein the first output is coupled to the fourth input;wherein the third output is coupled to the second input;wherein the first input is configured to receive an enable signal;wherein the third input is configured to receive a complementary enable signal;wherein the first output is configured to directly sense a voltage at the input of the first power transistor upon the first power transistor beginning to be turned off; andwherein the third output is configured to directly sense a voltage at the input of the second power transistor upon the second power transistor beginning to be turned off.2. The apparatus of claim 1 , wherein at least one of the first and second power transistors is a MOSFET.3. The apparatus of claim 1 , further comprising programmable dead time ...

INVERSELY PROPORTIONAL VOLTAGE-DELAY BUFFERS FOR BUFFERING DATA ACCORDING TO DATA VOLTAGE LEVELS

Inversely proportional voltage-delay buffers for buffering data according to data voltage levels are disclosed. In one aspect, an inversely proportional voltage-delay buffer is configured to buffer a data signal for an amount of time that is inversely proportional to a voltage level of the data signal. The inversely proportional voltage-delay buffer includes an inversion circuit and pass circuit. The inversion circuit is configured to generate a control signal that is the logic inverse of the data signal. Notably, the control signal transitions at a rate proportional to the voltage level of the data signal. The pass circuit is configured to generate a weak logic state of the data signal when the data signal and the control signal have the same logic state. The pass circuit is configured to generate a strong logic state of the data signal when the data input and the control signal have opposite logic states. 1. An inversely proportional voltage-delay buffer , comprising:a first circuit configured to generate a control signal having an inverted logic state of a data input signal; generate a data output signal having a weaker logic state corresponding to a logic state of the data input signal in response to the data input signal and the control signal both having one of a first logic state or a second logic state that is opposite of the first logic state;', 'generate the data output signal having a stronger logic state corresponding to a logic state of the data input signal in response to the control signal having the first logic state and the data input signal having the second logic state; and', 'generate the data output signal having a stronger logic state corresponding to a logic state of the data input signal in response to the control signal having the second logic state and the data input signal having the first logic state., 'a second circuit configured to2. The inversely proportional voltage-delay buffer of claim 1 , wherein the second circuit comprises: ...

LEVEL SHIFTER, DC-DC CONVERTER, AND LEVEL SHIFT METHOD

A level shifter includes: a first cascode portion, including a first transistor of a first conductivity type and a second transistor of a second conductivity type which are cascode-coupled to each other, configured to transmit a first input signal; a second cascode portion, including a third transistor of the first conductivity type and a fourth transistor of the second conductivity type which are cascode-coupled to each other, configured to transmit a second input signal; a latch portion configured to retain a first output signal and a second output signal obtained by changing, based on a first voltage obtained by boosting a power supply voltage, potential levels of the first input signal and the second input signal; and a potential-difference suppression circuit, coupled in parallel to the first cascode portion, configured to control a potential difference between source and drain of each of the first transistor and the second transistor. 1. A level shifter comprising:a first cascode portion, including a first transistor of a first conductivity type and a second transistor of a second conductivity type which are cascode-coupled to each other, configured to transmit a first input signal;a second cascode portion, including a third transistor of the first conductivity type and a fourth transistor of the second conductivity type which are cascode-coupled to each other, configured to transmit a second input signal which is in a complementary relation with the first input signal;a latch portion configured to retain a first output signal and a second output signal obtained by changing, based on a first voltage obtained by boosting a power supply voltage, potential levels of the first input signal and the second input signal; anda potential-difference suppression circuit, coupled in parallel to the first cascode portion, configured to control a potential difference between a source and a drain of each of the first transistor and the second transistor.2. The level shifter ...

DATA TRANSMISSION CIRCUIT

A data transmission circuit may include a first driving block configured to drive an output terminal for a first time in response to a data driving signal and a level of the output terminal, and a second driving block configured to drive the output terminal for a second time after the first time, in response to the data driving signal. 1. A data transmission circuit comprising:a transmitter configured to control a current leakage amount of an output terminal in response to a result of detecting a level of the output terminal, and thereby offset an increment in the level of the output terminal; anda receiver electrically coupled with the transmitter through a transmission line.2. The data transmission circuit according to claim 1 , wherein the receiver is included in a controller outside a semiconductor apparatus including the transmitter claim 1 , which instructs the semiconductor apparatus to input/output data.3. The data transmission circuit according to claim 1 , wherein the receiver has an input terminal which is terminated to a level of a ground terminal through a termination resistor.4. The data transmission circuit according to claim 1 , wherein the transmitter comprises:a driving block configured to drive the output terminal in response to a data driving signal; anda compensation block configured to control the current leakage amount of the output terminal in response to the data driving signal and the result of detecting the level of the output terminal, and thereby offset the increment in the level of the output terminal.5. The data transmission circuit according to claim 4 , wherein the driving block comprises logic elements which are designed to have different threshold voltages from logic elements of the compensation block.6. The data transmission circuit according to claim 4 ,wherein the driving block and the compensation block comprise first type logic elements and second type logic elements, respectively, andwherein the first type logic elements are ...

LEVEL SHIFTER

A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level. 120-. (canceled)21. A level shifter , comprising:first and second input terminals configured to receive complementary first and second input signals of a low voltage domain;first and second output terminals configured to provide complementary first and second output signals of a high voltage domain;an input circuit coupled between the first and second input terminals and the first and second output terminals, and further coupled with control nodes configured to provide first and second control signals based on the complementary first and second input signals;a tracking circuit coupled with the control nodes, and configured to generate first and second tracking signals based on the first and second control signals; anda cross-latch circuit coupled with the tracking circuit, and configured to provide the complementary first and second output signals of the high voltage domain to the first and second output terminals based on the tracking signals.22. The level shifter of claim 21 , ...

LEVEL SHIFTING AN I/O SIGNAL INTO MULTIPLE VOLTAGE DOMAINS

Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O module converts data signals in a core logic voltage domain to data signals in an external voltage domain. In one embodiment, when transmitting data signals to an external device, the I/O module level shifts the data signals from a core logic voltage domain to a low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to an intermediate voltage domain. The I/O module may further shift the data signals from the intermediate voltage domain to both a low voltage domain and a high voltage domain. Using the data signals from both of these domains, the I/O module outputs the data signals in a voltage domain corresponding to a communication technique used to transmit data to the external device. 1. A method comprising:receiving a data signal in a first voltage domain;level shifting the data signal from the first voltage domain into an intermediate voltage domain, the intermediate voltage domain is between a low voltage domain and a high voltage domain;level shifting the data signal from the intermediate voltage domain to the high voltage domain and the low voltage domain; andgenerating an output data signal in a second voltage domain different from the first voltage domain using a driver circuit, wherein the data signal in the high voltage domain and the data signal in the low voltage domain are inputs to the driver circuit.2. The method of claim 1 , wherein level shifting the data signal from the first voltage domain into the intermediate voltage domain comprises:level shifting the data signal from the first voltage domain to the low voltage domain; andlevel shifting the data signal from the low voltage domain to the intermediate voltage domain.3. The method of claim 1 , wherein level shifting the data signal from the intermediate voltage domain to the high voltage domain ...

Half bridge power conversion circuits using gan devices

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Semiconductor devices and inverter having the same

Disclosed are CMOS device and CMOS inverter. The CMOS device includes a substrate having active lines extending in a first direction and defined by a device isolation layer, the substrate being divided into an NMOS area, a PMOS area and a boundary area interposed between the NMOPS and the PMOS areas and having the device isolation layer without the active line, a gate line extending in a second direction across the active lines and having a first gate structure on the active line in the first area, a second gate structure on the active line in the second and a third gate structure on the device isolation layer in the third area. The electrical resistance and parasitic capacitance of the third gate structure are smaller than those of the NMOS and the PMOS gate structures. Accordingly, better AC and DC performance of the CMOS device can be obtained.

Fast Voltage Level Shifter Circuit

A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (FET) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism. The current changing mechanism includes a current mirror circuit having an output connected between the source and an electrical earth. The output of the current mirror circuit is preferably adapted to change a current flowing between the drain and the source based on an input voltage applied to the gate.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND LEVEL SHIFTER CIRCUIT

A semiconductor integrated circuit device includes: first and second transistors provided between a first power source and an output terminal; a step-down circuit that generates a second power source from the first power source; a power source switch circuit that outputs, as a fourth power source, a higher one of potentials of the second power source and a third power source; and a level shifter circuit that transits between the first power source and a fourth power source. The first transistor has a gate connected to an output of the level shifter circuit; the second transistor has a gate connected to the fourth power source. 1. A semiconductor integrated circuit device that receives a data input signal and outputs an output signal that varies in accordance with the data input signal , the semiconductor integrated circuit device comprising:an output terminal via which the output signal is output;a first transistor of a p type having a source connected to a first power source;a second transistor of a p type having a source connected to a drain of the first transistor and a drain connected to the output terminal;a step-down circuit that generates a second power source from the first power source;a power source switch circuit that outputs, as a fourth power source, a higher one of potentials of the second power source and a third power source, the power source switch circuit including a third transistor connected to the second power source and a fourth transistor connected to the third power source; anda first level shifter circuit that transits between the first power source and the fourth power source,the first transistor having a gate connected to an output of the level shifter circuit, the second transistor having a gate connected to the fourth power source.2. The semiconductor integrated circuit device of claim 1 , further comprisinga fifth transistor of an n type provided between the output terminal and a fifth power source,the fifth transistor having a gate ...

PULSED LEVEL SHIFT AND INVERTER CIRCUITS FOR GAN DEVICES

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed. 1. A level shift circuit , comprising: a first input terminal,', 'an intermediate node,', 'a first GaN-based transistor having a gate coupled to the first input terminal, a drain coupled to the intermediate node, and a source coupled to a first reference voltage, and', 'a first pull up device coupled between the drain of the first GaN-based transistor and a first power supply; and, 'an inverter circuit, comprising a first output terminal,', 'a second GaN-based transistor having a gate coupled to the intermediate node, a drain coupled to a second power supply, and a source coupled to the first output terminal, and', 'a first pull down device coupled between the first output terminal and a second reference voltage., 'a buffer circuit, comprising2. The level shift circuit of claim 1 , wherein the first power supply is a floating power supply.3. The level shift circuit of claim 1 , wherein the voltage of the first reference voltage is substantially fixed.4. The level shift circuit of claim 1 , wherein the voltage of the second reference voltage is configured to change in response to a signal at the first input terminal.5. The level shift circuit of claim 1 , wherein the second power supply is a floating power supply.6. The level shift circuit of claim 1 , wherein the first pull down device comprises a resistor.7. The level shift circuit of claim 1 , wherein the gate of the second GaN-based transistor is coupled to the intermediate node by one or more additional GaN-based transistors.8. The level shift circuit of claim 7 , wherein at least one of the one or more additional GaN-based ...

CONFIGURABLE TERMINATION CIRCUITRY

A resistance of configurable termination circuitry located at an interface between a memory component and a processing device is adjusted. The configurable termination circuitry includes a plurality of transistors, a plurality of switches coupled to the plurality of transistors, and a plurality of resistors coupled to the plurality of switches. The resistance of the configurable termination circuitry is adjusted based on a mode of the configurable termination circuitry. 1. An apparatus , comprising: the configurable termination circuitry includes a plurality of transistors coupled to a plurality of switches;', 'the configurable termination circuitry includes a plurality of resistors coupled to the plurality of switches; and', 'a first resistor of the plurality of resistors is coupled to two switches of the plurality of switches and a second resistor of the plurality of resistors is coupled to two different switches of the plurality of switches; and, 'configurable termination circuitry, whereina processing device to adjust a resistance of the configurable termination circuitry.2. The apparatus of claim 1 , wherein the processing device is to adjust the resistance of the configurable termination circuitry based on a mode of the configurable termination circuitry.3. The apparatus of claim 1 , wherein the processing device is to adjust the resistance of the configurable termination circuitry by turning two of the plurality of switches on and turning two of the plurality of switches off.4. The apparatus of claim 1 , wherein the first resistor and the second resistor are each coupled to at least one transistor of the plurality of transistors and an input/output (I/O) pad.5. The apparatus of claim 1 , wherein the first resistor and the second resistor are coupled to different transistors of the plurality of transistors.6. An apparatus claim 1 , comprising: the configurable termination circuitry is to reduce a plurality of signals to or from circuitry outside of the ...

DRIVER CIRCUIT WITH DEVICE VARIATION COMPENSATION AND OPERATION METHOD THEREOF

A driver circuit with device variation compensation function and an operation method thereof are provided. The driver circuit includes a pull-up switch unit, an isolating switch and a pull-down switch unit. A first terminal of the pull-up switch unit is coupled to a first voltage. A second terminal of the pull-up switch unit is coupled to an output terminal of the driver circuit. A first terminal of the isolating switch is coupled to the second terminal of the pull-up switch unit. A first terminal of the pull-down switch unit is coupled to a second terminal of the isolating switch. A second terminal of the pull-down switch unit is coupled to a second voltage. The pull-down switch unit has a device variation compensation function. 1. A driver circuit , comprising:a pull-up switch unit, having a first terminal coupled to a first voltage, and a second terminal of the pull-up switch unit being coupled to an output terminal of the driver circuit;an isolating switch, having a first terminal coupled to the second terminal of the pull-up switch unit; anda pull-down switch unit, having a first terminal coupled to a second terminal of the isolating switch, and a second terminal of the pull-down switch unit being coupled to a second voltage; wherein when the driver circuit operates in an initialization mode, the isolating switch is turned off, and the pull-down switch unit samples a threshold voltage of the pull-down switch unit to obtain a pull-down threshold voltage value; and when the driver circuit operates in a normal mode, the isolating switch is turned on, and the pull-down switch unit uses the pull-down threshold voltage value to compensate an input voltage of the pull-down switch unit.2. The driver circuit according to claim 1 , wherein the pull-down switch unit comprises:a pull-down switch, having a first terminal coupled to the second terminal of the isolating switch, and a second terminal of the pull-down switch being coupled to the second voltage; anda pull-down ...

Receiver for resonance-coupled signaling

An illustrative integrated circuit configured for galvanically isolated signaling includes a receiver having: a detector module coupled to receive a differential signal from terminals of a transformer secondary, the detector module responsively presenting an impedance that varies based on a magnitude of the differential signal; a biasing module that converts the detector module impedance to a response signal; and a comparator module that compares the response signal to a reference signal to obtain a detection signal indicative of oscillation in the differential signal. A method of receiving a pulse modulated alternating current (AC) signal from a resonantly-coupled signaling path comprises: supplying balanced quiescent currents from a cross-coupled FET pair in a common gate amplifier configuration thereby obtaining an impedance that varies based on an AC signal magnitude; converting the impedance into a response signal; and comparing the response signal to a reference signal to obtain a detection signal representing pulses in the differential AC signal.

Level shifter

The present disclosure provides a level shifter including: a level shifter section that is driven by a first power source voltage, and that, in accordance with switching of an input signal of a voltage lower than the first power source voltage, switches an output signal that has been level-shifted, from the first power source voltage to a voltage lower than the first power source voltage; and a threshold voltage changing circuit that, in accordance with a switching direction of the input signal, changes a threshold voltage of the input signal for switching the output signal.

Semiconductor Device

A semiconductor device or the like capable of preventing malfunction of a driver circuit is provided. In a driver circuit for driving a power device used for current supply, a transistor including an oxide semiconductor is used as a transistor in a circuit (specifically, for example, a level shift circuit) requiring a high withstand voltage. In addition, a transistor (for example, a silicon transistor or the like) capable of higher operation than a transistor including an oxide semiconductor is preferably used as a transistor in a circuit (specifically, for example, a buffer circuit, a flip-flop circuit, or the like) requiring a lower withstand voltage than the level shift circuit. 1. A semiconductor device comprising:a first circuit comprising a first output terminal and a second output terminal;a second circuit comprising a first transistor, a second transistor, a first resistor, and a second resistor; anda third circuit electrically connected to the second circuit,wherein the first output terminal is electrically connected to a gate of the first transistor,wherein the second output terminal is electrically connected to a gate of the second transistor,wherein one of a source and a drain of the first transistor is electrically connected to one terminal of the first resistor,wherein one of a source and a drain of the second transistor is electrically connected to one terminal of the second resistor,wherein a channel of each of the first transistor and the second transistor comprises an oxide semiconductor,wherein the second circuit is configured to convert a first signal into a second signal and output the second signal,wherein the second signal is input to the third circuit, andwherein the second signal has a higher potential than the first signal.2. The semiconductor device according to claim 1 , wherein the channel of each of the first transistor and the second transistor comprises indium and zinc.3. The semiconductor device according to claim 1 , wherein a band ...

OUTPUT DRIVERS AND SEMICONDUCTOR MEMORY DEVICES HAVING THE SAME

An output driver includes a main output driver configured to receive data of an internal supply voltage to generate output data of an output supply voltage, and to receive the data of a ground voltage to generate the output data of the ground voltage, a pre-emphasis controller configured to detect a transition of the data from the ground voltage to the internal supply voltage to generate a first pulse signal, and to receive a pre-emphasis enable signal and the first pulse signal and generate a level-up pre-emphasis enable signal and a first level-up pulse signal of the ground voltage, a pre-emphasis pre-driver configured to generate one or more pre-emphasis pull-up control signals, and a pre-emphasis driver configured to pre-emphasize the output data based on the output data transitioning from the ground voltage to the output supply voltage. 1. An output driver comprising:a main output driver configured to receive data of an internal supply voltage to generate output data of an output supply voltage lower than the internal supply voltage and to receive the data of a ground voltage to generate the output data of the ground voltage;a pre-emphasis controller configured to detect a transition of the data from the ground voltage to the internal supply voltage to generate a first pulse signal that is activated for a predetermined time, and to receive a pre-emphasis enable signal and the first pulse signal and generate a level-up pre-emphasis enable signal and a first level-up pulse signal of the ground voltage;a pre-emphasis pre-driver configured to generate one or more pre-emphasis pull-up control signals of a high supply voltage higher than the internal supply voltage using the level-up pre-emphasis enable signal and the first level-up pulse signal of the ground voltage; anda pre-emphasis driver configured to pre-emphasize the output data in response to the one or more pre-emphasis pull-up control signals of the high supply voltage based on the output data transitioning ...

MEMORY DEVICE

A memory device includes a data receiver, a latch driver, and a voltage level shifter. The data receiver works in a first voltage, receives an enable signal, a reference signal, and an input data signal, and outputs an internal data signal by the first voltage. The latch driver receives a write select signal and the internal data signal, latches the internal data signal by the first voltage, and outputs at least one latch data signal by a second voltage. The voltage level shifter receives the at least one latch data signal by the second voltage and generates at least one output data signal by the at least one latch data signal. The voltage level shifter sets a voltage value of the at least one output data signal by the first voltage. The voltage value of the first voltage is greater than the voltage value of the second voltage. 1. A memory device , comprising:a data receiver, working in a first voltage, configured to receive an enable signal, a reference signal, and an input data signal, outputting an internal data signal by the first voltage;a latch driver, coupled to the data receiver, configured to receive a write select signal and the internal data signal, latching the internal data signal by the first voltage, outputting at least one latch data signal by a second voltage; anda voltage level shifter, coupled to the latch driver, receiving the at least one latch data signal by the second voltage, generating at least one output data signal by the at least one latch data signal, wherein the voltage level shifter sets a voltage value of the at least one output data signal by the first voltage,wherein the voltage value of the first voltage is greater than the voltage value of the second voltage.2. The memory device as claimed in claim 1 , wherein the latch driver further receives a reset signal to perform a reset operation.3. The memory device as claimed in claim 2 , wherein the data receiver comprises:a first transistor, a first terminal of the first transistor ...

DISPLAY PANEL, GATE DRIVER AND CONTROL METHOD

A display panel includes gate lines and a gate driver. The gate driver includes series coupled driving stages, in which an N-th driving stage of the series-coupled driving stages includes a driving unit and an input control unit. The driving unit transmits a first clock signal according to a control voltage level of a control node, so as to output a gate-driving signal. The input control unit transmits the gate-driving signal outputted from an (N−1)-th driving stage to the control nodes, so as to adjust the control voltage level to one of a first voltage level and a second voltage level. A predetermined time interval is present between a rising edge of the first clock signal and a falling edge of the second clock signal. During the predetermined time interval, the control voltage level is pulled to the first voltage level by the input control unit. 1. A display panel , comprising:a plurality of gate lines; and a driving unit configured to selectively transmit a first clock signal according to a control voltage level of a control node to output a first gate-driving signal; and', 'an input control unit configured to selectively transmit a second gate-driving signal outputted from an (N−1)-th stage of the series-coupled driving stages to the control node according to a second clock signal, so as to adjust the control voltage level to one of a first voltage level and a second voltage level, wherein N is a positive integer, and the first voltage level is lower than the second voltage level,, 'a gate driver comprising a plurality of series-coupled driving stages, wherein each of the series-coupled driving stages is electrically coupled to a corresponding gate line of the gate lines, and an N-th stage of the series-coupled driving stages compriseswherein a predetermined time interval is present between a rising edge of the first clock signal and a falling edge of the second clock signal, and the input control unit pulls the control voltage level to the first voltage level ...

PSEUDO-DYNAMIC CIRCUIT FOR MULTI-VOLTAGE TIMING INTERLOCKS

An interlock circuit utilizes a single combinatorial pseudo-dynamic logic gate to take inputs from two voltage domains at the same time without requiring either input to be level shifted. The interlock design allows hold timing to be met across a large voltage range of both supplies in a dual-voltage supply environment while not significantly hurting setup time by having much lower latency than the latency of a level shifter. 1. An apparatus comprising: a keeper circuit having a pull-up portion coupled to the second input signal and configured to maintain an output signal on an output node of the interlock circuit at a first high voltage level associated with the first voltage domain until the first input signal is at the first high voltage level and the second input signal is at a second high voltage level associated with the second voltage domain; and', 'a pull-down circuit coupled to receive the first input signal and the second input signal, wherein the keeper circuit is configured to be weaker than the pull-down circuit, to thereby cause the output node to transition from the first high voltage level to a low voltage level responsive to the second input signal transitioning to the second high voltage level from the low voltage level while the first input signal is at the first high voltage level., 'an interlock circuit coupled to receive a first input signal from a first voltage domain and a second input signal from a second voltage domain, the interlock circuit including,'}2. The apparatus as recited in claim 1 , wherein the pull-up portion of the keeper circuit comprises:first and second transistors serially coupled between the output node of the interlock circuit and a power supply node of the first voltage domain.3. The apparatus as recited in claim 2 ,wherein the first transistor is coupled to receive an inverted version of the output signal as a first transistor gate signal; andwherein the second transistor is coupled to receive the second input signal as ...

INTERNAL VOLTAGE GENERATION CIRCUIT

An internal voltage generation circuit may be provided. The internal voltage generation circuit may include a pulse generation circuit configured to generate a first pulse and a second pulse in response to an external voltage. The internal voltage generation circuit may include a pulse synthesis circuit configured for synthesizing the first pulse and the second pulse to generate a synthesis pulse. 1. An internal voltage generation circuit comprising:a first pulse generation circuit configured for generating a first pulse having a pulse width which is adjusted by a first variation rate in response to an external voltage;a second pulse generation circuit configured for generating a second pulse having a pulse width which is adjusted by a second variation rate in response to the external voltage; anda pulse synthesis circuit configured for synthesizing the first pulse and the second pulse to generate a synthesis pulse for driving an internal voltage.2. The circuit of claim 1 ,wherein the first variation rate is set to a ratio of a variation amount of a pulse width of the first pulse to a variation amount of a level of the external voltage; andwherein the second variation rate is set to a ratio of a variation amount of a pulse width of the second pulse to a variation amount of a level of the external voltage.3. The circuit of claim 1 , wherein the second variation rate is set to be greater than the first variation rate.4. The circuit of claim 1 , wherein a difference between a pulse width of the first pulse and a pulse width of the second pulse increases if a level of the external voltage is lowered.5. The circuit of claim 1 ,wherein the first pulse generation circuit is configured to include a passive element; andwherein the first pulse generation circuit generates a delay signal from an input signal thereof and generates the first pulse from the input signal and the delay signal.6. The circuit of claim 5 , wherein the passive element is configured to include a ...

WAKE CIRCUIT FOR POWERED OPHTHALMIC LENS

A wake circuit is designed to minimize leakage current from a battery or other suitable energy source connected to various electronic components. The wake circuit essentially connects/disconnects or couples/decouples the battery or other power source from the other components when the device is in a storage state or otherwise idle. 1. An electronic system including a wake circuit configured for use in at least one of on or in the body , the electronic system comprising:functional electronics, including a digital controller and additional circuitry;a power supply for supplying power to the functional electronics;a wake logic circuit having a storage state and an active state configured to decouple the power supply from the functional electronics to minimize leakage current from the power supply when in the storage state;a switching element coupled to the power source, the wake logic circuit and the functional electronics; anda sensor coupled to the wake logic circuit, wherein the wake logic circuit is configured to switch from the storage state to the active state when the sensor is activated.2. The electronic system including a wake circuit according to claim 1 , wherein the power supply is a battery.3. The electronic system including a wake circuit according to claim 1 , wherein the switching element comprises a transistor.4. The electronic system including a wake circuit according to claim 1 , wherein the switching element comprises a voltage regulator.5. The electronic system including a wake circuit according to claim 1 , wherein the sensor comprises a photodetector.6. The electronic system including a wake circuit according to claim 5 , wherein the photodetector comprises a photodiode.7. The electronic system including a wake circuit according to claim 1 , wherein the system is incorporated into an ophthalmic device.8. The electronic system including a wake circuit according to claim 7 , wherein the ophthalmic device comprises a contact lens.9. The electronic ...

HALF BRIDGE CIRCUIT WITH BOOTSTRAP CAPACITOR CHARGING CIRCUIT

A half bridge circuit is disclosed. The half bridge circuit includes a low side transistor having a low side transistor gate, where a low side transistor gate voltage at the low side transistor gate is controlled by a low side gate signal. The half bridge circuit also includes a high side transistor having a high side transistor gate, where a high side transistor gate voltage at the high side transistor gate is controlled by a high side gate signal. The half bridge circuit also includes a semiconductor circuit configured to allow current to flow from a ground referenced power supply node to a first floating power supply terminal. The semiconductor circuit includes a first transistor, where a gate voltage is controlled by a gate drive circuit control signal, a source is connected to the ground referenced power supply node, and a drain connected to the first floating power supply terminal. 1a low side GaN-based transistor having a low side transistor gate, wherein a low side transistor gate voltage at the low side transistor gate is controlled by a low side gate signal; anda high side GaN-based transistor having a high side transistor gate, wherein a high side transistor gate voltage at the high side transistor gate is controlled by a high side gate signal.. A half bridge circuit, comprising: This application is a continuation of and claims priority to U.S. patent application Ser. No. 16/447,922, for “HALF BRIDGE CIRCUIT WITH BOOTSTRAP CAPACITOR CHARGING CIRCUIT”, filed on Jun. 20, 2019, which is a continuation of and claims priority to U.S. patent application Ser. No. 15/961,723, for “BOOTSTRAP CAPACITOR CHARGING CIRCUIT FOR GAN DEVICES,” filed on Apr. 24, 2018, which is a continuation of U.S. patent application Ser. No. 14/667,515, for “BOOTSTRAP CAPACITOR CHARGING CIRCUIT FOR GAN DEVICES,” filed Mar. 24, 2015, which claims priority to U.S. provisional patent application Ser. No. 62/051,160, for “HYBRID HALF-BRIDGE DRIVER USING GAN AND SILICON DEVICES,” filed on Sep ...

NEGATIVE-LEVEL SHIFTING CIRCUIT AND A SOURCE DRIVER AND A DISPLAY DEVICE USING THE CIRCUIT

A negative-level shifting circuit includes a first level shifter including an input circuit configured to receive a logic signal having a first voltage level and a load circuit configured to generate a first output signal having a second voltage level based on a voltage generated by the input circuit, and a second level shifter configured to receive the first output signal from the first level shifter and generate a second output signal having a third voltage level. The first level shifter further includes a shielding circuit connected between the input circuit and the load circuit and configured to separate an operating voltage region of the input circuit from an operating voltage region of the load circuit such that the input circuit operates in a positive voltage region and the load circuit operates in a negative voltage region. 1. A negative-level shifting circuit , comprising:a first level shifter including an input circuit configured to receive a logic signal having a first voltage level and a load circuit configured to generate a first output signal having a second voltage level based on a voltage generated by the input circuit; anda second level shifter configured to receive the first output signal from the first level shifter and generate a second output signal having a third voltage level,wherein the first level shifter further comprises a shielding circuit connected between the input circuit and the load circuit and configured to separate an operating voltage region of the input circuit from an operating voltage region of the load circuit such that the input circuit operates in a positive voltage region and the load circuit operates in a negative voltage region.2. The circuit of claim 1 , wherein a negative first-power supply voltage is applied to the first level shifter and the second level shifter.3. The circuit of claim 1 , wherein a negative first-power supply voltage and a positive second-power supply voltage are applied to the first level shifter.4. ...

LEVEL SHIFT CIRCUIT AND DC-DC CONVERTER FOR USING THE SAME

A level shift circuit and a DC-DC buck converter controller for using the same are disclosed. The level shift circuit is capable of detecting a state of a converting circuit, and avoids a current leakage when determining that the converting circuit is operating under a light-load. Therefore, the level shift circuit and the DC-DC converting controller provided by the present invention can reduce power consumption under the light-load and have power-saving advantage. 1. A level shift circuit , comprising:a signal input circuit, coupled between a first level and a second level, configured to receive a first input signal and a second input signal, and levels of the first input signal and the second input signal being switched between the first level and a third level, wherein the signal input circuit generates a first current when the first input signal is at the third level and generates a second current when the second input signal is at the third level;a signal output circuit, coupled between the second level and a fourth level, configured to output a first output signal and a second output signal, and levels of the first output signal and the second output signal being switched between the second level and the fourth level, wherein the first output signal is switched to the second level when the signal input circuit generates the first current, and the second output signal is switched to the second level when the signal input circuit generates the second current; anda state detecting circuit, detecting an operating state of a converting circuit, and accordingly determining whether generating a stop signal for stopping the signal input circuit generating the first current and the second current.2. The level shift circuit according to claim 1 , wherein the signal output circuit comprises an accelerating circuit claim 1 , which cuts off the second current when the first current is generated claim 1 , and cuts off the first current when the second current is generated.3 ...

Analog multiplexer

An analog multiplexer may be used for sampling an input voltage that is capable of having a higher voltage level than an upper supply voltage. The analog multiplexer includes a plurality of input switch circuits and a shorting switch circuit. The plurality of input switch circuits include n-type or p-type laterally diffused field effect transistors (NLDFETs or PLDFETs). At least one of the input switch circuits includes a level shifting switch circuit that is able to sample an input voltage that is greater than the upper supply voltage for the multiplexer. A shorting switch circuit, at an output of the multiplexer, includes a capacitively coupled gate drive circuit and is configured to short a first differential output to a second differential output after the input voltage is sampled.

INTEGRATED CIRCUIT AND CABLE ASSEMBLY INCLUDING THE SAME

An integrated circuit embedded in a plug of a universal serial bus (USB) 3.1 type-C cable assembly is disclosed. The integrated circuit includes a first pin connected to an operation transmission line through which an operation voltage is transmitted, a second pin connected to a configuration channel (CC) line, a first resistor connected to the first pin, a ground line, and a switching circuit configured to connect the first resistor and the ground line using a channel voltage supplied to the second pin when the operation voltage is not applied, and disconnect the first resistor from the ground line based on the operation voltage. 1. A device comprising:a first resistor connected to an operation voltage transmission line, and supplied with a first voltage via the operation voltage transmission line;a first transistor connected to the first resistor; anda negative charge pump coupled to the first transistor,wherein the first transistor is turned on and the first resistor is connected to a ground line when a second voltage is supplied to the first transistor via a configuration channel line,the negative charge pump is configured to supply a negative voltage to the first transistor when the negative charge pump is enabled, thereby reducing power consumption by preventing unnecessary current from flowing through the first resistor,the configuration channel line is distinguished from the operation voltage transmission line even when the first voltage is not supplied to the device, andthe device is universal serial bus (USB) type-C compatible.2. The device of claim 1 , wherein the device is a cable.3. The device of claim 1 , wherein when the negative charge pump is disabled claim 1 , the first transistor is turned on.4. The device of claim 1 , further comprising a switching circuit configured to connect the first resistor and the ground line.5. The device of claim 1 , wherein the negative charge pump is configured to supply the negative voltage to the first transistor ...

Signal transmitting circuit, and semiconductor apparatus and semiconductor system using the same

A signal transmitting circuit includes a first output control circuit, a second output control circuit, a first output driver, and a second output driver. The first output control circuit generates a first main driving signal based on a first control signal and generates a first auxiliary driving signal based on the first control signal and a second control signal. The second output control circuit generates a second main driving signal based on the second control signal and generates a second auxiliary driving signal based on the first control signal and the second control signal. The first output driver drives an output node based on the first main driving signal and the first auxiliary driving signal. The second output driver drives the output node based on the second main driving signal and the second auxiliary driving signal.

INPUT/OUTPUT CIRCUIT

A circuit includes an output node, a set of first transistors, a set of second transistors, and a first and second power node. The first power node is configured to carry a first voltage level, and second power node is configured to carry a second voltage level. Set of first transistors is coupled between the first power node and output node. Set of second transistors is coupled between the second power node and output node. The first control signal generating circuit is coupled to a gate of a first transistor of the set of first transistors and a gate of a first transistor of the set of second transistors. The first control signal generating circuit is configured to generate a set of biasing signals for the gate of the first transistor of the set of first transistors and the gate of the first transistor of the set of second transistors. 1. A circuit , comprising:a first power node configured to carry a first voltage level;a second power node configured to carry a second voltage level;an output node;a set of first transistors coupled between the first power node and the output node;a set of second transistors coupled between the second power node and the output node; anda first control signal generating circuit coupled to a gate terminal of a first transistor of the set of first transistors and a gate terminal of a first transistor of the set of second transistors, the first control signal generating circuit being configured to generate a set of biasing signals for the gate terminal of the first transistor of the set of first transistors and the gate terminal of the first transistor of the set of second transistors.2. The circuit of claim 1 , further comprising: a third voltage level after an input signal is set at a zero reference voltage level, and', 'the first voltage level after the input signal is set at a fourth voltage level; and, 'a second transistor of the set of first transistors having a gate terminal configured to receive a first signal being set ata ...