FOOD SUPPLEMENT RICH IN BIOLOGICAL IONS FOR HIGH-INTENSITY OUTDOOR SPORTS

Abstract The present disclosure relates to the technical field of food supplement application, in particular to a food supplement rich in biological ions for high-intensity outdoor sports and a preparation method thereof. The sports food supplement is prepared by the following raw materials of poly-y-glutamic acid, magnesium sulfate, sodium carbonate, ammonium bicarbonate, potassium magnesium aspartate, potassium chloride, sodium citrate, potassium citrate, calcium hydroxide, zinc sulfate, an antioxidant, a preservative, a Schisandra chinensis extraction liquor and water. The present disclosure promotes the middle-aged men to get recovery faster during exercise and reduces the risk of injury, thus enhancing the high-intensity exercise ability. The concentrated liquor provided herein tastes bitter free, cool and slightly sweet; and has good palatability and good stability; moreover, it is simple in preparation and wide in application range; and thus can be applied to sports beverage and ...

Intelligent controller for straw bioreactor and control method thereof

The invention discloses an intelligent controller, and particularly relates to an intelligent controller for an external straw bioreactor for protective land production and conversion from straws to carbon dioxide gas fertilizer. The intelligent controller for the straw bioreactor structurally comprises an air supply control system, a switch, a liquid discharge control system and a water level sensor, wherein the air supply control system sends working instructions to an air supply motor according to various different switch instruction; the switch sends working instructions to the air supply control system under different working conditions; the liquid discharge control system sends working instructions to a liquid discharge pump according to signals sent by the water level sensor; and the water level sensor transmits working signals to the liquid discharge control system after the water level reaches a set value. The intelligent controller has the characteristics of convenient setting ...

LOW POWER MASTER-SLAVE FLIP-FLOP

A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

Dual flip-flop circuit

A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.

Efficient scan latch systems and methods

Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

SELECTING A NEURAL NETWORK ARCHITECTURE FOR A SUPERVISED MACHINE LEARNING PROBLEM

Systems and methods for selecting a neural network for a machine learning problem are disclosed. A method includes accessing an input matrix. The method includes accessing a machine learning problem space associated with a machine learning problem and multiple untrained candidate neural networks for solving the machine learning problem. The method includes computing, for each untrained candidate neural network, at least one expressivity measure capturing an expressivity of the candidate neural network with respect to the machine learning problem. The method includes computing, for each untrained candidate neural network, at least one trainability measure capturing a trainability of the candidate neural network with respect to the machine learning problem. The method includes selecting, based on the at least one expressivity measure and the at least one trainability measure, at least one candidate neural network for solving the machine learning problem.

Application of ASB17 in preparation of medicine for preventing or treating inflammation caused by salmonella typhimurium plague

The invention belongs to the technical field of biomedicine, and discloses application of ASB17 in preparation of a medicine for preventing or treating inflammation caused by salmonella typhimurium plague, and ASB17 plays a role by inhibiting activation of NLRC4 inflammasomes. The ASB17 plays a role in inhibiting the maturation and secretion of a proinflammatory factor pro-IL-1beta. According to the invention, the function and mechanism of the ASB17 in the infection of the salmonella typhimurium plague are defined, and the ASB17 is found to be capable of inhibiting the inflammatory reaction in the infection process of the salmonella typhimurium plague. An experimental basis is provided for revealing a new function of ASB17, and a theoretical basis is provided for developing a new antiviral or anti-inflammatory target spot. The invention clarifies the mechanism of ASB17 for inhibiting the activation of Salmonella plague mediated NLRC4 inflammasome, and provides a new anti-inflammatory protein ...

Kleinleistungs-Einzelanschluss-Pegelschieber unter Verwendung eines Abschaltsignals aus einem Ausgangsleistungsbereich und ein Verfahren zum Umwandeln eines Datensignals zwischen Leistungsbereichen

Accident lighting system

The invention discloses an accident lighting system. The system comprises an accident lighting distribution box and a PLC cabinet provided with a PLC system. Compared with the prior art, the accident lighting system has the advantages that: the safety precaution is advanced because failure information is stored in the PLC system and a PLC system program gives an alarm. Simultaneously, part of components are arranged in the PLC cabinet, so a control cable is shortened, a plurality of lighting distribution boxes share one accident lighting distribution box, and the resource is saved. Besides, due to a signal lamp and local operation in the accident lighting distribution box, the accident lighting system is more humanistic and more reliable.

Constant temperature purifier of boiler condensed water

The invention provides a constant temperature purifier of boiler condensed water, comprising a tank body, wherein the tank body is divided into an oxidation filter cavity, an oil removal cavity and a deironing cavity from top to bottom. The invention needs little investment without increasing new energy consumption and impurities or generating cleaning mixture and has wide application field.

Method for preparing metoclopramide hydrochloride sustained-release capsule

The invention discloses a method for preparing micropills in a metoclopramide hydrochloride slow release capsule through the coating by a fluidized bed. In the method, the coating of main medicine layers and slow release layers of the micropills is operated by the fluidized bed, and a preferred fluidized coating control scheme is provided. The method greatly improves coating speed and drying efficiency, shortens working period, can reach ideal release rate in a dissolution rate experiment, and is suitable for mass production.

Visual intelligent agricultural planting system

The invention, which relates to the technical field of plant planting, discloses a visual intelligent agricultural planting system comprising an intelligent greenhouse and an intelligent planting system. The intelligent planting system comprises an intelligent control system, a monitoring system, a movable track type planting frame and pollination system, a negative pressure ventilation ground source heat regulation and control temperature and humidity system, a seedling cultivation and plant cultivation system and an intelligent irrigation system. The intelligent greenhouse is composed of a main function module, a coordinator module, a temperature, humidity and brightness monitoring module, a greenhouse roof foreign matter monitoring module, a dangerous area protection module, an anti-theft monitoring module, a water storage tank liquid level height monitoring module, a fire monitoring module, a serial port control module and a sunshade net control module. According to the designed intelligent ...

Surface anomaly detection method and device based on cascade reconstruction-discrimination structure

The invention relates to a surface anomaly detection method and device based on a cascade reconstruction-discrimination structure. The method comprises the following steps: reconstructing an image to be detected to obtain a first reconstructed image; reconstructing the first reconstructed image to obtain a second reconstructed image; splicing the to-be-detected image with the first reconstructed image and the second reconstructed image from channel dimensions to obtain a first abnormal score graph and a second abnormal score graph; and carrying out pixel-by-pixel average processing on the first abnormal score graph and the second abnormal score graph to obtain an indication abnormal detection result of the to-be-detected image. According to the invention, the surface anomaly detection performance is improved.

Low power, single-rail level shifters employing power down signal from output power domain and a method of converting a data signal between power domains

Process variation tolerant sense amplifier flop design

One embodiment of the present invention sets forth a sense amplifier flop design that is tolerant of process variation. Specific staging of signal transitions through the sense amplifier flop circuit eliminate operational phases involving short-circuit currents between n-channel field-effect transistors (N-FETs) and p-channel field effect transistors (P-FETs) in a complementary-symmetry metal-oxide semiconductor process. By eliminating short-circuit currents between N-FETs and P-FETs within the sense amplifier flop, a large variation in conductivity ratio between N-FETs and P-FETs may be tolerated by the sense amplifier flop. This tolerance to conductivity ratio translates to a tolerance for process variation by the sense amplifier flop circuit.

Array von virtuellen Frisch-Gitter-Detektoren mit gemeinsamer Kathode und reduzierter Länge der Schirmelektroden

Storage battery charging system

A storage battery charging system comprise a first rectifying circuit, an inverter circuit connected with the first rectifying circuit, a voltage isolating circuit connected with the inverter circuit, a second rectifying circuit connected with the voltage isolating circuit, an electric quantity detecting circuit connected with the first rectifying circuit and the inverter circuit, and a control circuit connected with the first rectifying circuit, the electric quantity detecting circuit and the inverter circuit. The control circuit is used for generating a rectifying control signal according to the voltage at the input end and the output end of the first rectifying circuit so as to control the rectifying circuit to output corresponding direct currents and is used for generating an inverting control signal so as to control the inverter circuit to generate corresponding alternating currents. The system is low in noise and size, and safety and reliability are increased by controlling the first ...

Thermal pattern assay apparatus

The invention relates to a device to analyze an infrared thermal picture of a person under test. Currently, infrared thermal pictures can not be treated automatically after being inputted into a computer; the pictures that are provided can not fully reflect or predict the functional changes of the organs of the person under test; and the creativity of certain imaging technology leads to external or internal trauma to the patient. The device makes use of the picture of the person under test, inputs the picture into the computer, converts the picture into digital temperature picture, analyzes the converted digital temperature picture through an analyzing program, and compares the analysis result with the data bank of the computer to get the health state of the person under test. The method can detect diseases at early stage before the appearance of the symptoms, provides a plurality of set of data and information through thermal picture scanning, and gives a full estimation to the health ...

ARRAY OF VIRTUAL FRISCH-GRID DETECTORS WITH COMMON CATHODE AND REDUCED LENGTH OF SHIELDING ELECTRODES

A novel radiation detector system is disclosed that solves the electron trapping problem by optimizing shielding of the individual virtual Frisch-grid detectors in an array configuration.

Apparatus and method for preventing current leakage when a low voltage domain is powered down

An apparatus and method are provided for preventing a current leakage or direct current when a low voltage domain is powered down. Included is a voltage transition circuit connected between a low voltage domain and a high voltage domain. Such voltage transition circuit includes a circuit component for preventing a current leakage when the low voltage domain is powered down.

Mitigating external influences on long signal lines

ADSORBENTS FOR USE IN THE SEPARATION OF CARBON MONOXIDE AND/OR UNSATURATED HYDROCARBONS FROM MIXED GASES

Novel adsorbents for use in the separation of carbon monoxide and/or unsaturated hydrocarbons from mixed gases An adsorbent for separating carbon monoxide or unsaturated hydrocarbon from mixed gases is made by heating a solid mixture comprising a copper compound and a support having a high surface area in a suitable atmosphere.

On-bed hot-water circulation bare calandria with two ends clusteringly fixed

The invention relates to an on-bed hot-water circulation bare calandria with two ends clusteringly fixed. The on-bed hot-water circulation bare calandria comprises a hot-water conveying circuitous calandria and is characterized in that the upper end and the lower end of the hot-water conveying circuitous calandria are clusteringly fixed together; the middle parts of the hot-water conveying circuitous calandria are distributed in parallel and at uniform intervals. The on-bed hot-water circulation bare calandria has the characteristics of being simple in processing, few in materials and small in size, occupies small warehouse and workshop space, is easy to store and transport, has good security, and is flexible and convenient for use.

Low heat conduction thermal insulation material and preparation and molding method thereof

The invention relates to a low heat conduction thermal insulation material and a preparation and molding method thereof. The method comprises the following steps: designing a molding die; slitting prepared prepreg cloth and pouring the slit prepreg out of a disc; then winding the slit prepreg cloth poured out of the disc; coating the wound prepreg cloth; curing the coated prepreg cloth; and machining the cured prepreg cloth. The method can be used for preparing the low heat conduction thermal insulation material which has lower heat conduction and better overall performance compared with traditional thermal insulation materials, thus making up the research blank on molding technology of low heat conduction thermal insulation materials. The low heat conduction thermal insulation material is prepared by the method, the density of the thermal insulation material is not greater than 0.85kg/m<3>, and the heat conductivity of the material is not greater than 0.18W/m*K at 200 DEG C.

Hybrid anode for semiconductor radiation detectors

The present invention relates to a novel hybrid anode configuration for a radiation detector that effectively reduces the edge effect of surface defects on the internal electric field in compound semiconductor detectors by focusing the internal electric field of the detector and redirecting drifting carriers away from the side surfaces of the semiconductor toward the collection electrode(s).

Low power, single-rail level shifters employing power down signal from output power domain and a method of converting a data signal between power domains

本文提供一種電壓位準移位器、一種包含電壓位準移位器的裝置、及一種用以轉換輸入及輸出電力域間之電壓的方法。在一具體實施例中，電壓位準移位器包含：(1)一輸入電路，組態以從一輸入電力域接收一資料信號以及從一輸出電力域接收一電力關閉信號；以及(2)一過渡電路，耦合至輸入電路並組態以接收資料信號及電力關閉信號的一反相信號，其中輸入電路及過渡電路兩者係組態以連接至輸出電力域的一供應電壓作為一電源。

Clock gating latch, method of operation thereof and integrated circuit employing the same

A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method are provided. In one embodiment, the clock gating latch includes: (1) a propagation circuit having a single, first switch configured to be driven by an input clock signal, (2) a keeper circuit coupled to the propagation circuit and having a single, first switch configured to be driven by the input clock signal and (3) an AND gate coupled to the propagation circuit and the keeper circuit and having an internal node coupled to a second switch in the propagation circuit and a second switch in the keeper circuit.

EFFICIENT SCAN LATCH SYSTEMS AND METHODS

Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component. 1. A scan flip flop comprising:a master latch in which data input is passed without delay associated with scan input;a slave latch operable to hold a value forwarded from the master latch.2. The scan flip flop of wherein the master latch introduces a delay to a scan input value before passing it on the slave latch.3. The scan flip flop of wherein the slave latch is a circuit comprising:the master latch is operable to select between a scan in value and a recirculation value in the recirculation path;the slave latch is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component; anda control component for controlling an indication of a selection by the scan in propagation component and the data propagation component.4. The scan flip flop of wherein a data input is not subjected to parasitics associated with a selection between a scan input and a recirculation.5. The scan flip flop of wherein a scan input is subjected to parasitics associated with a selection between a recirculation.6. The scan flip flop of wherein the master latch is at least partially controlled with a gated clock signal.7. The scan flip flop of wherein the slave ...

Communication system and communication method based on non-network layer

The invention discloses a communication system and a communication method based on a non-network layer. The system comprises a two-layer switch supporting two-layer forwarding capability, a first internal network machine, a second internal network machine, a first external network machine and a second external network machine, the first intranet machine and the second intranet machine are connected with the two-layer switch through MAC interfaces, the first extranet machine and the second extranet machine are connected through an IP network, the first extranet machine is connected with the first intranet machine through an MAC interface, and the second extranet machine is connected with the second intranet machine through an MAC interface. According to the method, RAW Socket is combined with a user-defined data structure mode for data between the internal network environment hosts and data between the internal and external network environment hosts, protocol forwarding based on a network ...

Low tau synchronizer flip-flop with dual loop feedback approach to improve mean time between failure

A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF).

Method for producing fuel ethanol by sugar grass stalk juice

The invention relates to a method for producing fuel ethanol by sugar grass stalk juice and a device; the stalk pretreatment, juice modulation, immobilization yeast particles and fluidization quick fermentation new processes are adopted to prepare the fuel ethanol; the fermentation process is continuous, the equipment is advanced, the fermentation speed is rapid, the reaction is full, the output is high, and the ethanol yield is high, no three-waste exhaust exists, secondary utilization is carried out totally, a great amount of investment, labor cost and raw material cost are reduced, the economic benefit is improved obviously, and the production cost is greatly reduced.

Application of compound 6-furfuryl amino purine in preparing medicine for treating myocardial tissue oxidizing damage

Method for generating pressure distribution chart of urban water supply pipeline network

The invention relates to a method for generating a pressure distribution chart of an urban water supply pipeline network in the technical field of monitoring. The method comprises the following steps of: firstly, collecting the pressure data of nodes of a pressure measurement point, a water plant, a pumping station and the like from the water supply pipeline network by utilizing an SCADA (Supervisory Control And Data Acquisition) system; secondly, preprocessing the collected node data; thirdly, carrying out restrictive cluster analysis on a sample of the collected pressure data; fourthly, zoning the water supply pipeline network according to a clustering result, selecting a representative pressure node from each zone so as to represent the pressure level of the zone in which the representative pressure node is in; and finally, displaying different colors according to the pressure value of each zone and outputting the pressure distribution chart of the water supply pipeline network. The ...

Track type rotary pollination system for uniformly receiving sunlight and pollinating plants

The invention relates to the field of planting, in particular to a rail type rotary pollination system for uniformly receiving sunlight and pollinating plants, two annular guide rails are positioned at the same height and are parallel to each other; a plurality of guide rail brackets are fixedly arranged below the annular guide rail; a plurality of planting frame grooves are fixedly formed in the planting frame; sliding devices are fixedly arranged at four corners below the planting frame; the sliding device is in sliding fit with the two annular guide rails; the sliding device and the two annular guide rails form an annular sliding module. A plurality of planting frames are arranged on the annular guide rail and form a planting frame vehicle, and the adjacent planting frames are connected through connecting pieces and can be connected in a relatively rotating mode. Rotating shafts of the pulleys are vertical; and the pulleys are fixedly connected with the guide rail bracket through pulley ...

Low power single rail input voltage level shifter

One embodiment of the present invention sets forth a technique for shifting the voltage level of signals from a low voltage domain to a high voltage domain, where VDDH is the supply voltage of the high voltage domain and VDDL is the supply voltage of the low voltage domain. A level shifting circuit uses a single input rather than dual rail inputs and does not produce a direct current flow in order to reduce the power consumption. The voltage level shifting circuit may also be used to shift a clock signal since the delays of the rising and falling edges of the clock signal are matched by using a delay element.

APPARATUS AND METHOD FOR PREVENTING CURRENT LEAKAGE WHEN LOW VOLTAGE DOMAIN IS POWERED DOWN

PROBLEM TO BE SOLVED: To provide an apparatus and method for preventing a current leakage or direct current when a low voltage domain is powered down. SOLUTION: Included is a voltage transition circuit connected between a low voltage domain and a high voltage domain. Such a voltage transition circuit includes a circuit component for preventing a current leakage when the low voltage domain is powered down. COPYRIGHT: (C)2009,JPO&INPIT ...

Refining method of tin-containing lead bullion and lead refining production method

The invention discloses a refining method of tin-containing lead bullion. The refining method of the tin-containing lead bullion comprises the following steps: (1) heating a molten lead raw material to a temperature which can ensure that tin impurities in the molten lead raw material are oxidized; (2) adding sodium hydroxide to the molten lead raw material, and stirring so as to ensure that the tin impurities in the molten lead raw material are rapidly and fully oxidized to form stannic oxide slag; (3) fishing out the stannic oxide slag. The refining method of the tin-containing lead bullion has the advantages that tin in the lead raw material can be removed, the problem that as the electrolytic potential of tin is close to the electrolytic potential of lead, tin is dissolved in a positive pole and separated out in a negative pole in an electrolytic refining production process, is avoided, the current efficiency is improved, and the electric energy is saved. The invention also discloses ...

POWER SAVINGS VIA SELECTION OF SRAM POWER SOURCE

A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.

Synthesis of discodermolide and analogs

Clock gating latch, method of operation thereof and integrated circuit employing same

A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method. In one embodiment, the clock gating latch includes: (1) a propagation circuit having a single, first switch configured to be driven by an input clock signal, (2) a keeper circuit coupled to the propagation circuit and having a single, first switch configured to be driven by the input clock signal and (3) an AND gate coupled to the propagation circuit and the keeper circuit and having an internal node coupled to a second switch in the propagation circuit and a second switch in the keeper circuit.

Method for producing fuel ethanol by sugar grass stalk juice

The invention relates to a method for producing fuel ethanol by sugar grass stalk juice and a device; the stalk pretreatment, juice modulation, immobilization yeast particles and fluidization quick fermentation new processes are adopted to prepare the fuel ethanol; the fermentation process is continuous, the equipment is advanced, the fermentation speed is rapid, the reaction is full, the output is high, and the ethanol yield is high, no three-waste exhaust exists, secondary utilization is carried out totally, a great amount of investment, labor cost and raw material cost are reduced, the economic benefit is improved obviously, and the production cost is greatly reduced.

Low power master-slave flip-flop

A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

Area efficient high performance memory cell

Embodiments for an area efficient high performance memory cell comprising a transistor connected to one of a bit line and a bit line bar are disclosed.

TAKTAUSBLENDAUFFANGREGISTER, VERFAHREN FÜR DESSEN BETRIEB UND INTEGRIERTE SCHALTUNG, IN DER DIESES ANGEWENDET IST

Ein Taktausblendauffangregister, mit: einer Ausbreitungsschaltung und einem einzigen ersten Schalter, der ausgebildet ist, von einem Eingangstaktsignal angesteuert zu werden; einer Erhaltungsschaltung, die mit der Ausbreitungsschaltung verbunden ist und einen einzigen ersten Schalter aufweist, der ausgebildet ist, von dem Eingangstaktsignal angesteuert zu werden; und einem UND-Gatter, das mit der Ausbreitungsschaltung und der Erhaltungsschaltung gekoppelt ist und einen internen Knoten aufweist, der mit einem zweiten Schalter in der Ausbreitungsschaltung und einem zweiten Schalter in der Erhaltungsschaltung verbunden ist, wobei der erste Schalter der Erhaltungsschaltung gemeinsam von dem UND-Gatter und der Erhaltungsschaltung benutzt ist.

Array von virtuellen Frisch-Gitter-Detektoren mit gemeinsamer Kathode und reduzierter Länge der Schirmelektrode

Ein neuartiges Strahlungsdetektorsystem ist offenbart, das das Elektroneneinfangproblem löst, in dem die Schirmung von den individuellen virtuellen Frisch-Gitter-Detektoren in einer Arraykonfiguration optimiert wird.

MIXED THRESHOLD FLIP-FLOP ELEMENT TO MITIGATE HOLD TIME PENALTY DUE TO CLOCK DISTORTION

A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.

PREPARATION METHOD OF COMPOSITE ANTIBACTERIAL POLY-γ-GLUTAMIC ACID/CHITOSAN/NANO-ZnO FIBER

Abstract The present disclosure belongs to the technical field of fiber material preparation and application, and particularly relates to a method for preparing a composite antibacterial poly-y-glutamic acid/chitosan/nano-ZnO fiber. The method is specifically achieved by the following steps of: dripping a poly-y-glutamic acid solution into a chitosan spinning solution to prepare nanoparticles; mixing poly-y-glutamic acid/chitosan with a nano-ZnO suspension, and adding water for dissolving the mixed solution, then adding glycerol, and uniformly mixing the above materials to prepare into a composite spinning solution; and then electrospinning and vacuum drying the composite spinning solution to obtain a product. In the present disclosure, the carboxyl in y-PGA and the amino in CS have a rather high coordination coefficient and a stable structure to increase the loading rate of nano-ZnO; and meanwhile, the addition of nano-ZnO highlights the mechanical property. Moreover, in this present disclosure ...

Intelligent planting system with Internet of Things control function

The invention relates to the field of planting, in particular to an intelligent planting system with an internet-of-things control function, which comprises an intelligent control structure, an intelligent monitoring structure and an intelligent drip irrigation structure, and is characterized in that a front-end sensor in the intelligent control structure monitors soil temperature and humidity, air temperature and humidity, carbon dioxide concentration and illuminance; the data acquisition TRU acquires data of the front-end sensor and transmits the data to the controller, and the controller receives and processes the data and transmits the data to the mobile terminal and the fixed terminal through the communication module and the Internet. The mobile terminal and the fixed terminal carry out remote operation through the Internet, the controller starts corresponding equipment according to the front-end sensor to intelligently carry out drip irrigation, ventilation, auxiliary illumination ...

TAKTAUSBLENDAUFFANGREGISTER, VERFAHREN FÜR DESSEN BETRIEB UND INTEGRIERTE SCHALTUNG, IN DER DIESES ANGEWENDET IST

Ein Taktsausblendauffangregister, ein Verfahren zum gesteuerten Ausblenden eines Taktsignals und eine integrierte Schaltung, in der das Taktsausblendauffangregister oder das Verfahren enthalten sind. In einer Ausführungsform umfasst das Taktsausblendauffangregister: (1) eine Ausbreitungsschaltung mit einem einzelnen ersten Schalter, der ausgebildet ist, von einem Eingangstaktsignal angesteuert zu sein, (2) eine Erhaltungsschaltung, die mit der Ausbreitungsschaltung verbunden ist und einen einzelnen ersten Schalter aufweist, der ausgebildet ist, von dem Eingangstaktsignal angesteuert zu sein, und (3) ein UND-Gatter, das mit der Ausbreitungsschaltung und der Erhaltungsschaltung verbunden ist und einen internen Knoten aufweist, der mit einem zweiten Schalter in der Ausbreitungsschaltung und einem zweiten Schalter in der Erhaltungsschaltung verbunden ist.

Building extraction application based on machine learning in Urban-Suburban-Integration Area

Abstract This is a technology based on computer learning, which realizes the automatic recognition of buildings in semantic segmentation by the means of deep learning.The invention consists of the following steps: Inputing the improved DCNN (with hole convolution and ASPP module) and getting a rough prediction result - expanding to the original size by bilinear interpolation refining the prediction result by fully connected CRF - getting the final output . It does not require manual selection of features and can accurately and quickly identify different shapes and heights of buildings on macroscopic remote sensing images. Conv1 rate=2 rate=4 rate=8 rate=16 Poolt Blockl Block2 Block3 Block4 Block5 Block6 Block Image ",rid, 4 8 16 16 16 16 16 16 figure 3 f~i, j) figure 4 P(C) figure 5 ...

POLY γ-GLUTAMIC ACID/CHITOSAN/CALCIUM CITRATE BIOMATERIAL AND PREPARATION METHOD THEREO

Abstract The present disclosure relates to the field of bone biomaterials, in particular to a poly y-glutamic acid/chitosan/calcium citrate biomaterial and a preparation method thereof. The method includes firstly preparing y-polyglutamic acid/chitosan gel particles by a spray freeze-drying method, loading recombinant human bone morphogenetic protein 2 growth factors, premixing with a solid phase of calcium citrate by a wet method, grinding and freeze-drying, adding a curing liquid according to a proportion, and carrying out injection molding and pressing molding. The poly-y glutamic acid and chitosan used in the present disclosure are colorless, non-toxic, tasteless and easily degradable microbial fermentation extracts, and the carboxyl group of the y-PGA and the amino group of CS have high coordination coefficient and stable structures. According to the present disclosure, the recombinant human bone morphogenetic protein 2 and calcium ions can be slowly released into a human body to help ...

Quantum security hash right confirmation traceability system and method thereof

The system comprises a network receiving module, a judgment module, a first identity auditing module, a second identity auditing module, a quantum hash calculation module, a right confirmation storage module, a tracing module and a network transmission module. The network receiving module is connected with the judgment module, the judgment module is connected with the first identity auditing module, and the first identity auditing module, the quantum hash calculation module, the right confirmation storage module and the network transmission module are connected in sequence; the judgment module is also connected with the traceability module; according to the method, the right of the data to be confirmed can be confirmed, and the safety of right confirmation is improved to the level of quantum safety, so that the uniqueness of file right confirmation can be safely and efficiently guaranteed, and disputes caused by the problem of data ownership are avoided; and the access data can be traced ...

Generic flexible timer design

One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.

Efficient scan latch systems and methods

Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

APPARATUS FOR PREVENTING CURRENT LEAKAGE WHEN A LOW VOLTAGE DOMAIN IS POWERED DOWN AND METHOD THEREOF

PURPOSE: An apparatus and method for preventing current leakage is provided to prevent a current leakage by using a voltage transition circuit. CONSTITUTION: An apparatus and method for preventing current leakage comprises the followings: a low voltage domain(710); a high voltage domain(730); a voltage transition circuit(722) connected between the low voltage domain and the high voltage domain; a circuit component(760) for preventing a current leakage or a direct current when the low voltage domain is powered down; and a processor(700). © KIPO 2009 ...

Kleinleistungs-Einzelanschluss-Pegelschieber unter Verwendung eines Abschaltsignals aus einem Ausgangsleistungsbereich und ein Verfahren zum Umwandeln eines Datensignals zwischen Leistungsbereichen

Hierin werden ein Spannungspegelschieber, eine Vorrichtung mit einem Spannungspegelschieber und ein Verfahren zum Umwandeln von Spannungen zwischen einem Eingangs leistungsbereich und einem Ausgangsleistungsbereich bereitgestellt. In einer Ausführungsform umfasst der Spannungspegelschieber: (1) eine Eingangsschaltung, die ausgebildet ist, ein Datensignal aus einem Eingangsleistungsbereich und ein Leistungsabschaltsignal aus einem Ausgangsleistungsbereich zu empfangen, und (2) eine Übergangsschaltung, die mit der Eingangsschaltung verbunden und ausgebildet ist, das Datensignal und ein invertiertes Signal des Leistungsabschaltsignals zu empfangen, wobei die Eingangsschaltung und die Übergangsschaltung jeweils ausgebildet sind, mit einer Versorgungsspannung des Ausgangsleistungsbereichs als eine Leistungsquelle in Verbindung zu stehen.

Excitation module and excitation system

The invention discloses an excitation module and an excitation system. An auxiliary generator excitation initiating circuit supplies power supply initial excitation, and an auxiliary generator receives the power supply initial excitation and outputs a target value of voltage. An excitation transformer carries out isolation step-down on the target value of voltage and then outputs a first current and a second current, a main generator excitation controller carries out PID closed-loop regulation on a main generator excitation current according to the first current, and an auxiliary generator carries out PID closed-loop regulation on an auxiliary generator excitation current according to the second current. The auxiliary generator can be subjected to excitation pre-initiating through the auxiliary generator excitation initiating circuit, so that the main generator excitation controller is only needed to be subjected to first-level initial excitation and is not needed to be subjected to second-level ...

Method for generating real-time dynamic water supply network pressure distribution pattern

The invention discloses a method for generating a real-time dynamic water supply network pressure distribution pattern in the technical fields of water supply safety and monitoring of pipe network states. The method comprises the steps of: firstly collecting pressure data of all joints of a water supply network regularly through an SCADA (supervisory control and data acquisition) system, connecting the joints into a triangular grid, then adding new joints on the edges of the triangular grid, inquiring the joints traversally after removing the joints outside the profile of a base pattern, and judging whether alarm display is needed. The method for generating the real-time dynamic water supply network pressure distribution pattern, disclosed by the invention, not only can be used for monitoring joints with pressure sensors, but also can be used for obtaining the condition of pressure of the joints without pressure sensors, and can be widely applied in the fields of water supply safety and ...

Frequency conversion foodstuff scattering system for aquatic product feeding

The invention relates to the technical field of aquatic product feeding devices, in particular to an aquatic product feeding frequency conversion foodstuff scattering system which comprises a support, a hopper arranged at the top of the support, an automatic foodstuff conveying pipe belt and a driving mechanism and further comprises a discharging pipe arranged at the bottom of the hopper. A material throwing disc assembly is arranged at the bottom of the bracket and corresponds to the discharging pipe; the material throwing disc assembly is connected with the driving mechanism; the material throwing disc assembly comprises a material throwing disc body and a discharging opening formed in the inner side of the material throwing disc body. The material throwing disc body further comprises a high disc and a low disc. Feed passes through a high disc and a low disc arranged on the feed throwing disc assembly, and when the feed is discharged through a discharge pipe, the throwing range of the ...

Begrenzen von externen Einflüssen auf lange Signalleitungen

Begrenzen von externen Einflüssen auf lange Signalleitungen. Gemäß einer Ausführungsform der vorliegenden Erfindung weist eine Reihe eines Speicherarrays einen ersten und einen zweiten Transistor auf, die zum Hochziehen der Bitleitung der Reihe konfiguriert sind. Die Reihe enthält einen dritten Transistor, der zum wahlweisen Hochziehen der Bitleitung der Reihe als Reaktion auf ein Level der invertierten Bitleitung der Reihe konfiguriert ist, und einen vierten Transistor, der zum wahlweisen Hochziehen der invertierten Bitleitung der Reihe als Reaktion auf ein Level der Bitleitung der Reihe konfiguriert ist. Die Reihe enthält ferner einen fünften und einen sechsten Transistor, die zum Wahlweisen Hochziehen der Bitleitung und der invertierten Bitleitung der Reihe als Reaktion auf das Klemmsignal konfiguriert sind, und einen siebten Transistor, der zum Wahlweisen Koppeln der Bitleitung der Reihe und der invertierten Bitleitung der Reihe als Reaktion auf das Klemmsignal konfiguriert ist.

Connector on-off detection method, system and device

The invention discloses a connector on-off detection method, a connector on-off detection system and a connector on-off detection device. The method comprises the following steps: connecting an outgoing line of a tested connector to a test common interface; connecting the input end of the tested connector to the test male seat; a test level signal is sent to the tested connector through the single-chip microcomputer control unit; receiving the test level signal through a single-chip microcomputer control unit, and judging the on-off condition of the tested connector according to the test level signal; the on-off condition is sent to the LCD display unit through the single-chip microcomputer control unit. According to the invention, the problems of poor reliability and difficult operation of manual measurement are effectively reduced, batch testing is realized, and the product testing efficiency is greatly improved.

Writing stationery

Pin programmable delay unit,timer and integrated circuit

One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.

Modeling method and device of geological lithologic model, storage medium and electronic equipment

The invention provides a modeling method and device of a geological lithology model, a storage medium and electronic equipment. The method comprises the steps that three-dimensional seismic data of a target stratum is obtained and explained, first initial horizon data of a first interface and second initial horizon data of a second interface are obtained, the target stratum at least comprises a bottom layer, a target layer and a top layer which are arranged in sequence, the first interface is an interface between the top layer and the target layer, and the second interface is an interface between the top layer and the target layer; the second interface is an interface between the bottom layer and the target layer; the first initial horizon data and the second initial horizon data are corrected, first target horizon data and second target horizon data are obtained, the first target horizon data correspond to the first initial horizon data, and the second target horizon data correspond to ...

Flipflop-Element mit einem Gemisch von Schwellenwerten, um einen Haltezeitaufschlag aufgrund einer Taktstörung abzuschwächen

Ein Flipflop-Element ist ausgestaltet, um Transistoren einer FinFET-Technologie mit einem Gemisch von Schwellenspannungen aufzuweisen. Der Dateneingangspfad weist FinFET-Transistoren auf, welche mit hohen Spannungsschwellenwerten ausgestaltet sind. Der Takteingangspfad weist Transistoren auf, welche mit normalen Spannungsschwellenwerten ausgestaltet sind. Indem FinFET-Transistoren mit normalen Schwellenwerten in dem Taktsignalpfad vorhanden sind, wird die Millerkapazität des Taktsignalpfads im Vergleich zu FinFET-Transistoren mit einem hohen Spannungsschwellenwert verringert, was zu einer geringeren Anstiegszeit und dementsprechend zu einer kürzeren Haltezeit führt. Indem Bauelemente mit einem hohen Schwellenwert in dem Dateneingangspfad enthalten sind, weist das Flipflop-Element im Betrieb eine hohe Geschwindigkeit und einen niedrigen Stromverbrauch auf. Indem Bauelemente mit einem normalen Schwellenwert in dem Taktsignalpfad enthalten sind, erzielt das Flipflop-Element schnellere Schaltzeiten in dem Taktsignalpfad.

Kleinflächiger Niedrigleistungs-Datenbeibehaltungsflop

Ein Schaltkreis (300) aufweisend:einen Master-Latch (110) aufweisend:einen ersten Inverter (114), der an einen Eingang eines ersten NAND-Gatters (116) gekoppelt ist;ein erstes Pass-Gatter (123) zum selektiven Koppeln eines Ausgangs des ersten NAND-Gatters (116) an einen Eingang des ersten Inverters (114);ein zweites Pass-Gatter (122) zum selektiven Koppeln des einen Eingangs des ersten Inverters (114) an einen Schaltkreiseingang;einen Datenbeibehaltungs-Latch (330) aufweisend:ein zweites NAND-Gatter (131), das an einen Eingang eines zweiten Inverters (133) gekoppelt ist;ein drittes Pass-Gatter (135) zum selektiven Koppeln eines Ausgangs des zweiten Inverters (133) an einen ersten Eingang des zweiten NAND-Gatters (131);ein viertes Pass-Gatter (125) zum selektiven Koppeln eines Ausgangs des ersten Inverters (114) an den ersten Eingang des zweiten NAND-Gatters (131);einen fünften Inverter (338), der an einen Ausgang des vierten Pass-Gatters (125) gekoppelt ist zum Treiben eines sechsten Inverters ...

Haupt-Neben-Flipflop mit geringer Leistung

Eine Flipflop-Schaltung mit: einer getakteten Hochzieh-Komponente (102) mit: einem ersten getakteten Hochzieh-Transistor (234), der mit einer Versorgungsspannung verbunden ist, und einem zweiten getakteten Hochzieh-Transistor (218), der mit der Versorgungsspannung verbunden ist; einer Haupt-Signalspeicherkomponente (110), die ausgebildet ist, einen wahren Pegel einer eingebetteten Logikfunktion eines Dateneingangsbündels an einen Haupt-Wahr-Speicherknoten (112) zu übergeben, und ein Komplement des Pegels der eingebetteten Logikfunktion des Dateneingangsbündels an einen Haupt-Komplementärspeicherknoten (114) zu übergeben, wenn ein Taktsignal (130) auf einem ersten Pegel ist; und einen ersten Wert des Haupt-Wahr-Speicherknotens (112) und einen zweiten Wert des Haupt-Komplementärspeicherknotens (114) konstant zu halten, wenn ein Taktsignal (130) auf einem zweiten Pegel ist; mit: einem komplementären Hochzieh-Logikkegel (202; 602), der ausgebildet ist, den komplementären. Pegel der eingebetteten ...

Furnace door position detection system and single crystal furnace

The invention discloses a furnace door position detection system and a single crystal furnace, and the system comprises a tilt angle sensor which is arranged on a furnace door of the single crystal furnace to collect tilt angle data of the furnace door; the data acquisition device is electrically connected with the tilt angle sensor; and the upper computer is in communication connection with the data acquisition device through a signal line, acquires the inclination angle data and determines the closing state of the furnace door according to the inclination angle data. By automatically detecting the position of the furnace door of the single crystal furnace, whether the inclination error occurs or not is judged, the problem that a single crystal rod cannot be formed due to the error is avoided, and the problems that manual measurement is complex in operation and low in efficiency are solved.

Clock gating latch, method of operation thereof and integrated circuit employing the same

Low power master-slave flip-flop

Array of virtual Frisch-grid detectors with common cathode and reduced length of shielding electrodes

A radiation detector system that solves the electron trapping problem by optimizing shielding of the individual virtual Frisch-grid detectors in an array configuration with a common cathode.

WEARABLE CLOTHING ACCESSORY INCORPORATING AN OPEN COMPUTING PLATFORM

A clothing or garment accessory incorporating a computing platform being configured to provide a user with a wearable open computing platform. The computing platform includes a multiplicity of conductive threads incorporated in the fabric of the clothing or garment accessory used as power wires, communication wires and connection points. A central processing unit control the functions of units connected to the platform. A display unit senses a touch of a user and display executed software applications. A battery unit supplies power to the central processing unit, the display unit, and other hardware units connected to the central processing unit through the power wires. A preconfigured software app running on the central processing unit provides a user interface operable to control and communicate with the connected hardware units.

FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY

An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal. 1. An adder circuit comprising:a first operand input and a second operand input to an XNOR cell;an OAI cell transforming an output of the XNOR cell into a carry out signal; andan XOR cell comprising a NOR gate and an AOI cell configured to transform a third operand input and the output of the XNOR cell into a sum output signal.2. The adder circuit of claim 1 , wherein the XNOR cell comprises a NAND gate coupled to an input of the OAI cell.3. The adder circuit of claim 1 , wherein an output of the NOR gate is coupled to an input of the AOI cell.4. The adder circuit of claim 1 , wherein an output of the NOR gate is coupled to an input of an OAI cell.5. The adder circuit of claim 1 , wherein the third operand input is a complement operand input.6. The adder circuit of claim 1 , wherein the third operand input is an un-complemented operand input.7. The adder circuit of claim 1 , wherein the sum output signal is an un-complemented sum output signal.8. The adder circuit of claim 1 , wherein the sum output signal is a complement sum output signal.9. A compressor circuit comprising:a first full adder;a second full adder; and a first operand input and a second operand input to both of a NAND gate and a first OAI cell;', 'a second OAI cell to transform outputs of the NAND gate and the first OAI cell into a carry out signal; and', 'an output stage comprising an AOI cell to transform outputs of the first OAI cell and a third operand input into a sum output signal., 'each full adder comprising10. The compressor circuit of claim 9 , wherein a sum output of the first full adder is applied to an input stage of the second full adder without an intervening inverter.11. The ...

Lamp light control device capable of tracking and adapting to human eyes

The invention discloses a lamp light control device capable of tracking and adapting to human eyes. The lamp light control device comprises a lamp light control module (3), a mechanical arm module (4) and a base (5), wherein the mechanical arm module (4) is rotationally arranged on the base (5) of a lamp light control device, the lamp light control module (3) is arranged at the end part of the mechanical arm module (4), the lamp light control device also comprises an information identifier (1), an intelligent processing component (2) and a power supply device (6), the information identifier (1) is arranged outside the lamp light control device, and the intelligent processing component (2) and the power supply device (6) are arranged in the base (5). The lamp light control device has the advantages that the bright and dark combination of the lamp light can be controlled for adapting to the requirements of people, the sound control, the light sensing control and the mechanical control are ...

Application of morchella fermented herba epimedii extract in enhancing macrophage activity and antitumor activity

The invention relates to an application of a morchella fermented herba epimedii extract in enhancing macrophage activity and antitumor activity. The preparation method of the morchella esculenta fermented herba epimedii extract comprises the following steps: activating a morchella esculenta strain through a PDA solid culture medium, inoculating the morchella esculenta strain into an herba epimedii culture medium, soaking the morchella esculenta strain in 70% ethanol, concentrating the morchella esculenta strain by a rotary evaporator, and freeze-drying the morchella esculenta strain to obtain the morchella esculenta A broad-spectrum MTT experiment is carried out on cells such as RAW264.7 macrophages and BEAS-2B cells which are cultured in vitro by taking the unfermented herba epimedii extract prepared by the same method as a contrast, and the result shows that the morchella fermented herba epimedii extract can obviously enhance the activity of the RAW264.7 macrophages in vitro and inhibit ...

GENERIC FLEXIBLE TIMER DESIGN CAPABLE OF INTRODUCING COST-DOWN SUBSTITUTES WHEN ERROR IS GENERATED

PURPOSE: A generic flexible timer design is provided to decrease an effort for realizing high quality design and to introduce a cost-down substitute when a plan error is generated. CONSTITUTION: An input signal is transmitted to an input channel. A first control signal is transmitted to a first control input channel in order to control a first transmission gate. A second controlling signal is transmitted to a second control input channel in order to control the second and third transmission gates. The first, second, and third transmission gates are arranged between a first delay element and a second delay element. A pin-programmable delay cell includes a first output channel in which a first output signal is transmitted. © KIPO 2009 ...

Small area low power data retention flop

But compression bending's motion plastic bottle

The utility model provides a but compression bending's motion plastic bottle, the motion plastic bottle includes the tubbiness main part, tubbiness main part upper end is equipped with the bottleneck, the motion plastic bottle still include with the bottle lid of bottleneck spiro union, at the bottom of the tubbiness main part includes integrated into one piece's support bottle, activity body and support the bottleneck, but the activity body includes a plurality of compression bending's fold unit, the compression of plastic bottle can be realized to the fold unit, it is crooked, screw thread through bottleneck and bottle lid closely links to each other, guarantee the seal structure of whole plastic bottle, cooperation fold unit reaches the memory effect, support the bottle end and support the bottleneck and make whole plastic bottle no matter have the splendid attire thing still not have steadily to stand vertically under the condition of splendid attire thing, realize the compression under ...

Phytobacterium plantarum S165 and application thereof in transforming and synthesizing rare notoginsenoside R2 by fermenting notoginsenoside R1

The invention relates to the field of probiotic fermentation, in particular to plant lactobacillus S165 and application thereof in conversion and synthesis of rare notoginsenoside R2 by fermenting notoginsenoside R1, the strain is preserved in China Center for Type Culture Collection on June 2, 2022, and the preservation number is CCTCC NO: M2022783. According to the invention, the notoginsenoside R1 is fermented by utilizing the plant lactobacillus S165, and the notoginsenoside R1 is converted into the rare notoginsenoside 20-(R)-R2 and 20-(S)-R2 under the action of glucosidase produced by the plant lactobacillus S165. The rare notoginsenoside 20-(R)-R2 and 20-(S)-R2 can be efficiently converted and synthesized, the method has the advantages of being safe, efficient, low in cost and the like, and a brand new source mode is provided for biosynthesis of the rare notoginsenoside 20-(R)-R2 and 20-(S)-R2.

Low power single-rail-input voltage level shifter

An apparatus includes a single-rail input connected to a low-voltage domain and a voltage-transition circuit connected to the single-rail input. The voltage-transition circuit is configured to convert a voltage of the low-voltage domain received via the single-rail input to a voltage of the high-voltage domain.

Kleinflächiger Niedrigleistungs-Datenbeibehaltungsflop

Kleinflächige Niedrigleistungs-Datenbeibehaltungsflop. Gemäß einer ersten Ausführungsform der vorliegenden Erfindung weist ein Schaltkreis einen Master-Latch auf, der an einen Datenbeibehaltungs-Latch gekoppelt ist. Der Datenbeibehaltungs-Latch ist zum Arbeiten als ein Slave-Latch zu dem Master-Latch konfiguriert, um einen Master-Slave-Flipflop während normalen Betriebs zu implementieren. Der Datenbeibehaltungs-Latch ist konfiguriert zum Beibehalten eines Ausgangswertes des Master-Slave-Flipflops während eines Niedrigleistungs-Datenbeibehaltungsmodus, wenn der Master-Latch ausgeschaltet ist. Eine einzige Steuereingang ist zum Wählen zwischen dem normalen Betrieb und dem Niedrigleistungs-Datenbeibehaltungsmodus konfiguriert. Der Schaltkreis mag unabhängig von einem dritten Latch sein. Small area, low performance data retention flop. According to a first embodiment of the present invention, a circuit has a master latch that is coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip-flop during normal operation. The data retention latch is configured to maintain an output value of the master-slave flip-flop during a low power data retention mode when the master latch is off. A single control input is configured to choose between normal operation and low performance data retention mode. The circuit may be independent of a third latch.

Controllable load and distributed power supply access network privacy data review method

The invention discloses a privacy data review method for a controllable load and distributed power supply access network, which is characterized in that sensitive words are determined according to the occurrence frequency of related lexical items in privacy data, the accuracy of dividing the sensitive words is improved, and omission and deletion caused by artificially determining the sensitive words are reduced. Through calculation of a coordinate vector between a sensitive word and a context lexical item, the association degree between the specific content of the privacy data information center and the sensitive word is determined, so that whether the sensitive word and the sensitive information are involved in the privacy data information or not is judged. By establishing the association between the content and the sensitive word, the problem existing in the process of only reviewing the sensitive word is avoided, and the processed sensitive word in the privacy information can be accurately ...

SRAM CORE CELL DESIGN WITH WRITE ASSIST

A static random access memory (SRAM) cell is disclosed. The SRAM cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage node when a word line is asserted. The SRAM cell further includes a row header configured to provide current from a power supply when the word line is not asserted, and to not provide current from the power supply when the word line is asserted. The SRAM cell further includes a column header configured to provide current from a power supply when a write column line is not asserted, and to not provide current from the power supply when the write column line is asserted. 1. A static random access memory (SRAM) cell , comprising:a storage unit configured to store a data bit in a storage node;an access unit coupled to the storage unit, to a word line, and to a bit line and configured to transfer current from the bit line to the storage node when the word line is asserted;a row header coupled to the storage unit, to the word line, and to a power supply rail and configured to transfer current from the power supply rail to the storage unit when the word line is not asserted and to transfer substantially no current from the power supply rail to the storage unit when the word line is asserted; anda column header coupled to the storage unit, to a write column line, and to the power supply rail and configured to transfer current from the power supply rail to the storage unit when the write column line is not asserted and to transfer substantially no current from the power supply rail to the storage unit when the write column line is asserted.2. The SRAM cell of claim 1 , wherein the row header further comprises a switching mechanism configured to transfer current from the power supply rail to the storage unit when the word line is not asserted and to not transfer current from the power supply rail ...

Energy-saving vehicle-mounted road surface shot-blasting machine

Photovoltaic type hollow glass

The invention relates to photovoltaic-type glazing glass, wherein glazing glass is constituted by transparent inner and outer layer glass, the outer layer glass is constituted by photovoltaic glue clamping glass, a sealed insulated external member which is extracted by an internal and an external electrodes is mounted between the inner layer glass and the outer layer glass, a convex rib for fixing a normal electrode connector is arranged in a cavity of the sealed insulated external member of the electrode, the normal electrode connector is connected with a cable conductor which is extracted by the internal and the external electrodes, the external side wall of the sealed insulated external member is provided with a seal groove and the convex rib which is fixed with the photovoltaic glue clamping glass, at least one electrode connector is packed and fixed in the sealed insulated external member which is extracted out by the electrodes in the electrode sealed insulated external member, and ...

Self-timed dynamic sense amplifier flop circuit apparatus and method

Apparatuses and methods are provided for a self-timed dynamic sense amplifier flop circuit, wherein a pulse generating circuit may be adapted to generate at least a first logic signal based, at least in part, on a first evaluation node signal, and a discharge path circuit comprising at least a first transistor within a first stack of transistors may be operatively responsive to the first timing signal.

Low power single-rail-input voltage level shifter

An apparatus includes a single-rail input connected to a low-voltage domain and a voltage-transition circuit connected to the single-rail input. The voltage-transition circuit is configured to convert a voltage of the low-voltage domain received via the single-rail input to a voltage of the high-voltage domain.

Radiation detector device for rejecting and excluding incomplete charge collection events

A radiation detector device is provided that is capable of distinguishing between full charge collection (FCC) events and incomplete charge collection (ICC) events based upon a correlation value comparison algorithm that compares correlation values calculated for individually sensed radiation detection events with a calibrated FCC event correlation function. The calibrated FCC event correlation function serves as a reference curve utilized by a correlation value comparison algorithm to determine whether a sensed radiation detection event fits the profile of the FCC event correlation function within the noise tolerances of the radiation detector device. If the radiation detection event is determined to be an ICC event, then the spectrum for the ICC event is rejected and excluded from inclusion in the radiation detector device spectral analyses. The radiation detector device also can calculate a performance factor to determine the efficacy of distinguishing between FCC and ICC events.

Low power flip-flop element with gated clock

A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system.

Integrated device for starting diesel engine and charging battery, as well as diesel locomotive

The invention discloses an integrated device for starting a diesel engine and charging a battery, as well as a diesel locomotive, belongs to the technical field of locomotives, and solves the technical problems that internal components of the conventional diesel locomotive are large in sizes and high in cost. The integrated device comprises a chopper circuit, a converter and a controller; when the diesel engine is started, the controller is adopted to drive the chopper circuit, the output voltage of the battery is boosted to a first intermediate voltage, the controller is further used to drive the converter, and the first intermediate voltage is inverted into the alternating current and is output to a generator, so that the generator is operated in the motor state to start the diesel engine; when the battery is being charged, the diesel engine is used for driving the generator to generate power, the controller is used for driving the converter to rectify the alternating current generated ...

Haupt-Neben-Flipflop mit geringer Leistung

Eine Flipflop-Schaltung kann einen Haupt-Signalspeicher und einen Neben-Signalspeicher aufweisen. Jeder Signalspeicher hat einen transparenten Modus und einen Speichermodus. Der Neben-Signalspeicher ist in dem Speichermodus, wenn der Haupt-Signalspeicher in dem transparenten Modus ist; und umgekehrt. Ein Taktsignal steuert den Modus des Signalspeichers über ein Paar getakteter Hochzieh-Transistoren und ein Paar getakteter Herabzieh-Transistoren, so dass insgesamt vier getakteten Transistoren vorhanden sind. Die getakteten Transistoren können einen gemeinsam von dem Haupt-Signalspeicher und dem Neben-Signalspeicher verwendet werden. Es sind weniger getaktete Transistoren erforderlich, wenn diese gemeinsam benutzt werden, im Bergleich dazu, wenn diese nicht gemeinsam benutzt werden. Getaktete Transistoren können eine parasitäre Kapazität aufweisen und Leistung verbrauchen, wenn sie mit einem variierenden Taktsignal beaufschlagt werden aufgrund der Ladung und der Entladung der parasitären Kapazität. Das Vorsehen von weniger getakteten Transistoren kann daher die von der Flipflop-Schaltung verbrauchte Leistung reduzieren. A flip-flop circuit may include a main latch and a sub-latch. Each latch has a transparent mode and a memory mode. The sub-latch is in the memory mode when the main latch is in the transparent mode; and vice versa. A clock signal controls the mode of the latch via a pair of clocked pull-up transistors and a pair of clocked pull-down transistors, for a total of four clocked transistors. The clocked transistors may be shared by the main latch and the slave latch. Less clocked transistors are needed when shared, in mountain mode when not shared. Clocked transistors may have a parasitic capacitance and consume power when supplied with a varying clock signal due to the charge and discharge of the parasitic capacitance. The provision of less clocked transistors can therefore reduce the power consumed by the flip-flop circuit.

Visual tracking method based on multi-cue fusion

The invention discloses a visual tracking method based on multi-cue fusion, which belongs to the technical field of information. The method comprises the following steps: a) determining a tracking window comprising a target region and a background region in a first frame of a video sequence; b) obtaining a color feature probability distribution graph, a position feature probability distribution graph and a motion continuity feature probability distribution graph of the previous frame from the second frame; c) adding the three probability distribution graphs in a weighed manner to obtain a total probability distribution graph; and d) using a CAMSHIFT algorithm to obtain the coordinates of a central point of the tracking window of the current frame in the total probability distribution graph. The method can be used in human-computer interaction, visual intelligent surveillance, intelligent robot, virtual reality technology, model-based image encoding, content retrieval of streaming media ...

Instruction execution method and device

The invention provides an instruction execution method and device. The execution method comprises the following steps: obtaining an instruction keyword; according to the identified instruction keyword, matching instruction action from instruction configuration data; executing the instruction action. A user instruction is matched to the instruction action which can be executed by a program by using the instruction configuration data, and the user instruction and the corresponding instruction action can be dynamically configured to revise an application program instead of upgrading the application program all the time.

Sewage filtering device

The invention relates to the technical field of sewage filtering, in particular to a sewage filtering device which comprises a filtering device body, a filtering plate, a rolling and scraping type filtering assembly and a filtering layer. The rolling and scraping type filtering assembly comprises a support, two sets of rotating rollers a, two sets of rotating rollers b and a filtering belt, and the filtering belt surrounds the outer sides of the two sets of rotating rollers a and the outer sides of the two sets of rotating rollers b respectively; connecting plates are arranged at the positions, corresponding to the rotating roller a and the rotating roller b, of the side edge of the support, a rolling and scraping type filtering assembly is arranged, the rotating roller a, the rotating roller b and a driving motor are arranged in the rolling and scraping type filtering assembly, and a filtering belt is connected to the outer sides of the rotating roller a and the rotating roller b in a ...

Superoxide dismutase conjugate of galactosed quaternarized chitosan and preparation thereof

The invention provides a superoxide dismutase conjugate of galactosed quaternarized chitosan and preparation thereof. The superoxide dismutase conjugate is formed by combining free amino on a super oxide dlsmutase (SOD) molecule with the galactosed quaternarized chitosan, wherein the modification rate of the free amino which is located on the SOD molecule and is combined with the galactosed quaternarized chitosan is 15.22%-43.13%; and one SOD molecule can be combined with 1-8 galactosed quaternarized chitosan molecules. Compared with the natural SOD, the original function of decomposing a superoxide anion of the SOD can be maintained in the SOD conjugate provided by the invention; the isoelectric point of the SOD can be obviously improved; the SOD conjugate is combined with a galactose receptor on the surface of a cell by virtue of galactose in a conjugate molecule; and the SOD conjugate integrates radical resistance function of the SOD, inflammatory and fibrillation resistance of chitosan ...

METHOD, DEVICE FOR DISPLAYING EMBLEM IN NAVIGATION AND MEDIUM

Embodiments of the present disclosure disclose a method, apparatus and device for displaying an emblem in navigation and a medium, and relates to a field of navigation. The method includes: obtaining current information of a navigation terminal, in which, the current information at least includes a state of a location system, a driving speed and a driving location; and drawing an emblem with the driving speed drawn thereon when the state of the location system indicates an enabled state, and displaying the emblem at the driving location. The method, apparatus and device for displaying the emblem in navigation and the medium provided by the present disclosure may reduce a display area occupied by information and solve the problem that the display area of the driving speed overlays the map elements below it while displaying the same amount of information.

LOW CLOCKING POWER FLIP-FLOP

Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition. 1. A flip-flop electronic circuit comprising:a master latch coupled to a slave latch in a flip-flop configuration; anda clock control circuit for comparing an input to said master latch with an output of said slave latch, and responsive to said comparing, said master latch and said slave latch are configured to retain their respective states when said flip-flop electronic circuit is in a quiescent condition.2. The flip-flop electronic circuit of wherein only devices of said clock control circuit receive said clock signal in said quiescent condition.3. The flip-flop electronic circuit of wherein no more than four devices dissipate active clocking power in said quiescent condition.4. The flip-flop electronic circuit of wherein said clock control circuit implements a logic function wherein a clock signal to said master latch is equal to (said input to said master latch XNOR said output of said slave latch) OR said clock signal.5. The flip-flop electronic circuit of wherein said clock control circuit implements a logic function wherein a clock signal to said slave latch is equal to (said input to said master latch XOR said output of said slave latch) AND said clock signal.6. The flip-flop electronic circuit of wherein said clock control circuit comprises no more than three two-input logic gates.7. The flip-flop electronic circuit of wherein said clock control circuit controls said clock signal only for one flip-flop electronic circuit.8. An electronic circuit ...

Tile type flue gas water-condensing collecting device

The invention relates to a tile type flue gas water-condensing collecting device which is arranged at the bottom of a heat exchanger at the tail of a boiler. The tile type flue gas water-condensing collecting device comprises assembling frames (3), an upper layer tile (1), a lower layer tile (2), hydrophobic grooves (4) and hydrophobic pipes (5). The number of the assembling frames (3) is two, the assembling frames (3) are respectively a left assembling frame (3) and a right assembling frame (3), the upper layer tile (1) and the lower layer tile (2) are arranged between the left assembling frame (3) and the right assembling frame (3) in an upper-layer and a lower-layer mode, two ends of the lower layer tile (2) are open, the number of the hydrophobic grooves (4) is also two, the hydrophobic grooves (4) are respectively a left hydrophobic groove (4) and a right hydrophobic groove (4) and are arranged below the lower layer tile (2), the number of the hydrophobic pipes (5) is also two, and ...

Generic flexible timer design

One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.

DUAL-TRIGGER LOW-ENERGY FLIP-FLOP CIRCUIT

One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock. 1. A dual-trigger low-energy flip-flop circuit , comprising:a trigger sub-circuit that includes a first clock-activated transistor and is configured to arm either a first trigger signal or a second trigger signal when an input signal to the dual-trigger low-energy flip-flop circuit is at a different level than a level of an output signal generated by the dual-trigger low-energy flip-flop circuit; anda latch sub-circuit that includes a second clock-activated transistor and is configured to change the level of the output signal when either the first trigger or the second trigger is armed and a clock signal transitions from a first level to a second level and maintains the level of the output signal when neither the first trigger or the second trigger is armed.2. The dual-trigger low-energy flip-flop circuit of claim 1 , wherein the latch sub-circuit further comprises a third clock-activated transistor that is coupled to a first isolation transistor and a second isolation transistor.3. The dual-trigger low-energy flip-flop circuit of claim 2 , wherein the third clock-activated transistor is enabled for every Nth clock cycle and N is greater than ten.4 ...

ARRAY OF VIRTUAL FRISCH-GRID DETECTORS WITH COMMON CATHODE AND REDUCED LENGTH OF SHIELDING ELECTRODES

A novel radiation detector system is disclosed that solves the electron trapping problem by optimizing shielding of the individual virtual Frisch-grid detectors in an array configuration. 2. A virtual Frisch-grid detector array according to claim 1 , wherein the plurality of virtual Frisch-detectors in the edge module comprise the shielding electrode extending a less than ⅓ length of a semiconductor placed near the anode edge.3. A virtual Frisch-grid detector array according to claim 1 , further comprises a side insulating layer between the side surface of the semiconductor and the shielding electrode producing the virtual Frisch-grid effect.4. A virtual Frisch-grid detector array according to claim 1 , wherein the cathodes of the detectors in the array are connected together.5. A virtual Frisch-grid detector array according to claim 1 , wherein the aspect ratio of the semiconductor is at least about 2.6. A virtual Frisch-grid detector array according to claim 1 , wherein the shielding electrode in the detectors of the internal module extends about ⅓ of the total length of the semiconductor.7. A virtual Frisch-grid detector array according to claim 6 , wherein the shielding electrode is made from conducting metals.8. A virtual Frisch-grid detector array according to claim 7 , wherein the conducting metals is selected from copper (Cu) or aluminum (Al).9. A virtual Frisch-grid detector array according to claim 1 , wherein interaction depth information derived from the cathode signal of the internal module is used to correct the anode's charge loss due to electron trapping of the array.10. A virtual Frisch-grid detector array according to claim 1 , wherein the ratio between the cathode and an anode signals is used to reject the events interacting close to the anode.11. A virtual Frisch-grid detector array according to claim 1 , wherein the semiconductor is selected from the group consisting of Group III-V semiconductors and Group II-VI semiconductors.12. A virtual ...

DUAL-TRIGGER LOW-ENERGY FLIP-FLOP CIRCUIT

One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the dock. 1. A dual-trigger low-energy flip-flop circuit , comprising:a first isolation transistor having a source that is coupled to a clock-activated pull-up transistor and having a gate that is coupled to a complement of a first trigger signal;a second isolation transistor having a source that is coupled to the clock-activated pull-up transistor and having a gate that is coupled to a complement of a second trigger signal, wherein only one of the second trigger signal and the first trigger signal is asserted at a time;a third transistor having a drain that is coupled to a drain of the first isolation transistor and a gate that is coupled to the first trigger signal; anda fourth transistor having a drain that is coupled to a drain of the second isolation transistor and a gate that is coupled to the second trigger signal.2. The dual-trigger low-energy flip-flop circuit of claim 1 , wherein the first trigger signal is a reset trigger that resets an output signal of the dual-trigger lo energy flip-flop circuit claim 1 ,3. The dual-trigger low-energy flip-flop circuit of claim 1 , wherein the second trigger signal is a set trigger that sets an output signal of ...

CLOCK GATING LATCH, METHOD OF OPERATION THEREOF AND INTEGRATED CIRCUIT EMPLOYING THE SAME

A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method. In one embodiment, the clock gating latch includes: (1) a propagation circuit having a single, first switch configured to be driven by an input clock signal, (2) a keeper circuit coupled to the propagation circuit and having a single, first switch configured to be driven by the input clock signal and (3) an AND gate coupled to the propagation circuit and the keeper circuit and having an internal node coupled to a second switch in the propagation circuit and a second switch in the keeper circuit. 1. A clock gating latch , comprising:a propagation circuit having a single, first switch configured to be driven by an input clock signal;a keeper circuit coupled to said propagation circuit and having a single, first switch configured to be driven by said input clock signal; andan AND gate coupled to said propagation circuit and said keeper circuit and having an internal node coupled to a second switch in said propagation circuit and a second switch in said keeper circuit.2. The clock gating latch as recited in wherein said clock gating latch has a first node located between third and fourth switches of said propagation circuit and an inverter of said keeper circuit claim 1 , said node coupled to a first input of said AND gate and between said first and second switches of said keeper circuit.3. The clock gating latch as recited in wherein said AND gate is formed by a combination of a NAND gate and an inverter claim 1 , said internal node located between said NAND gate and said inverter.4. The clock gating latch as recited in wherein a high state of said input clock signal prevents a signal provided via second switch of said propagation circuit from driving an inverter in said keeper circuit and said AND gate.5. The clock gating latch as recited in wherein said first switch of said propagation circuit is a PFET switch and said first switch of ...

LOW POWER, SINGLE-RAIL LEVEL SHIFTERS EMPLOYING POWER DOWN SIGNAL FROM OUTPUT POWER DOMAIN AND A METHOD OF CONVERTING A DATA SIGNAL BETWEEN POWER DOMAINS

Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source. 1. A voltage level shifter , comprising:an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain; anda transition circuit coupled to said input circuit and configured to receive said data signal and an inverted signal of said power down signal, wherein said input circuit and said transition circuit are both configured to connect to a supply voltage of said output power domain as a power source.2. The voltage level shifter as recited in wherein said input circuit includes a switch configured to receive said supply voltage to control operation thereof.3. The voltage level shifter as recited in wherein said voltage level shifter is a bidirectional voltage shifter.4. The voltage level shifter as recited in wherein said switch is positioned to control current flowing through said input circuit.5. The voltage level shifter as recited in wherein said input circuit includes two p-type transistors coupled in series to two n-type transistors claim 1 , wherein a gate of one of said p-type transistors is configured to connect to said power down signal and a gate of one of said n-type transistors is configured to connect to a reference voltage of said input power domain.6. The voltage level shifter as recited in wherein said transition circuit includes two p-type ...

RADIATION DETECTOR

Technologies are described for semiconductor radiation detectors. The semiconductor radiation detectors may comprise a semiconductor material. The semiconductor material may include a first surface and a second surface. The first surface may be opposite from the second surface. The semiconductor material may include at least one metal component. The semiconductor material may be effective to absorb radiation and induce a current pulse in response thereto. The semiconductor radiation detector may comprise an electrode contact. The electrode contact may include a metal doped oxide deposited on the first surface of the semiconductor material. The metal doped oxide may include the metal component element of the semiconductor material. 1. A semiconductor radiation detector , the semiconductor radiation detector comprising:a semiconductor material including a first surface and a second surface, the first surface being opposite from the second surface, the semiconductor material including at least one metal component, the semiconductor material effective to absorb radiation and induce a current pulse in response thereto;an electrode contact that includes a metal doped oxide deposited on the first surface of the semiconductor material, wherein the metal doped oxide includes an oxide of the metal component element of the semiconductor material.2. The semiconductor radiation detector of claim 1 , wherein the oxide includes one of zinc claim 1 , cadmium or zinc plus cadmium.3. The semiconductor radiation detector of claim 1 , wherein the metal doped oxide is doped with one of aluminum claim 1 , indium claim 1 , or silver.4. The semiconductor radiation detector of claim 1 , wherein the metal doped oxide is aluminum-doped zinc oxide (Al:ZnO) or aluminum doped cadmium oxide (Al:CdO).5. The semiconductor radiation detector of claim 1 , wherein the semiconductor material is one of CdZnTe claim 1 , thallium bromide claim 1 , CdMnTe claim 1 , CdTeSe or CdZnTeSe.6. The semiconductor ...

LOW POWER MASTER-SLAVE FLIP-FLOP

A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit. 1. A flip-flop circuit comprising: a first clock gated pull-up transistor, coupled to a supply voltage, and', 'a second clock gated pull-up transistor, coupled to the supply voltage;, 'a clocked pull-up component comprising 'a complement pull-up logic cone configured to generate the complement level of the embedded logic function of the data input bundle, coupled between the first clock gated pull-up transistor and the master complement storage node, and a true pull-up logic cone configured to generate the true level of the embedded logic function of the data input bundle, coupled between the second clock gated pull-up transistor and the master true storage node; and', 'a master latch component configured to propagate a true level of an embedded logic function of a data input bundle to a master true storage node, and a complement of the level of the embedded logic function of the data input bundle to a master complement storage node when a clock signal is at a first level; and to hold a first value of the master true storage node and hold a second value of the master complement storage node constant ...

Production and Distribution of Dilute Species in Semiconducting Materials

Technologies are described effective to implement systems and methods of producing a material. The methods comprise receiving a tertiary semiconductor sample with a dilute species. The sample has two ends. The first end of the sample includes a first concentration of the dilute species lower than a second concentration of the dilute species in the second end of the sample. The method further comprises heating the sample in a chamber. The chamber has a first zone and a second zone. The first zone having a first temperature higher than a second temperature in the second zone. The sample is orientated such that the first end is in the first zone and the second end is in the second zone.

METHOD AND APPARATUS FOR DISPLAYING NAVIGATION ROUTES AND STORAGE MEDIUM

Embodiments of the present disclosure disclose a method and apparatus for displaying navigation routes. The method includes: receiving, from a navigation server, at least two navigation routes from a navigation starting point to a navigation destination; determining a current navigation route from the navigation routes according to selection by a user, and assigning remaining routes as backup navigation routes; and displaying, in a navigation map, the current navigation route in a first mode and displaying the backup navigation routes in a second mode different from the first mode. In the embodiments of the present disclosure, by using the technical solution, the user may clearly and conveniently distinguish the current navigation route from the backup navigation routes, thereby improving the user experience. 1. A method for displaying navigation routes , the method comprising:receiving, from a navigation server, at least two navigation routes from a navigation starting point to a navigation destination;determining a current navigation route from the navigation routes according to selection by a user, and assigning remaining routes as backup navigation routes; anddisplaying, in a navigation map, the current navigation route in a first mode and displaying the backup navigation routes in a second mode different from the first mode,wherein the method is performed by at least one hardware processor.2. The method according to claim 1 , wherein the method further comprises:acquiring estimated arrival time to the navigation destination through the current navigation route and the backup navigation routes respectively;acquiring time difference information between the estimated arrival time through the backup navigation routes and the estimated arrival time through the current navigation route; anddisplaying, in the navigation map, the time difference information at a set display position associated with the backup navigation routes corresponding to the time difference ...

LOW POWER FLIP-FLOP ELEMENT WITH GATED CLOCK

A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system. 1. A circuit element configured to perform a data capture operation , the circuit element comprising: receive a first data signal that has a first logic state,', 'invert the first logic state to generate a first inverted logic state, and', 'receive a first clock signal; and, 'a first latch element configured to invert the first clock signal to generate a first inverted clock signal, and', 'transmit the first inverted clock signal to the first latch element, wherein the first latch element, in response to the first inverted clock signal, inverts the first data signal to generate a first inverted data signal., 'a first logic element coupled to the first latch element and configured to2. The circuit element of wherein the first latch element comprises:a first inverter pair configured to receive the first data signal;a first switching element coupled between the first inverter pair and a supply voltage;a second switching element coupled between the first inverter pair and a grounding path;a second inverter pair coupled to the first inverter pair;a third switching element coupled between the second inverter pair and the supply voltage;a first inverter coupled between the first inverter pair and the second inverter pair; anda fourth switching element coupled between the second inverter pair and ...

Hyperparameter Transfer Via the Theory of Infinite-Width Neural Networks

Systems and method are provided that are directed to tuning a hyperparameter associated with a small neural network model and transferring the hyperparameter to a large neural network model. At least one neural network model may be received along with a request for one or more tuned hyperparameters. Prior to scaling the large neural network, the large neural network is parameterized in accordance with a parameterizing schemed. The large neural network is then scaled and reduced in size such that a hyperparameter tuning process may be performed. A tuned hyperparameter may then be provided to a requestor such that the hyperparameter can be directly input into the large neural network. By tuning a hyper parameter using a small neural network, significant computation cycles and energy may be saved. 1. A method for tuning one or more hyperparameters of a large neural network model , the method comprising:receiving a large neural network model;parameterizing the large neural network model according to a parameterization scheme;reducing a width of at least one layer of the large neural network model resulting in a smaller neural network model;performing a hyperparameter tuning process using the smaller neural network model to identify a tuned hyperparameter; andtransferring the tuned hyperparameter to the large neural network model.2. The method of claim 1 , wherein the hyperparameter tuning process includes performing an exhaustive search to identify an optimized hyperparameter.3. The method of claim 2 , further comprising using the optimized hyperparameter in the large neural network model during a training process.4. The method of claim 1 , wherein reducing the width of the at least one layer of the large neural network model is based at least upon an amount of available computing resources.5. The method of claim 1 , wherein the parameterization includes scaling at least one layer by a function of a width of the layer.6. A method for providing hyperparameters claim 1 , ...

EFFICIENT SCAN LATCH SYSTEMS AND METHODS

Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component. 1. A circuit comprising:a scan in propagation component operable to select between a scan in value and a recirculation value;a data propagation component operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component; anda control component for controlling an indication of a selection by the scan in propagation component and the data propagation component.2. The circuit of wherein the data propagation component is operable to pass input data without a delay associated with the scan in component.3. The circuit of wherein the scan in component and data propagation component are operable to introduce a delay to scan input.4. The circuit of wherein the scan in propagation component is configured in the recirculation path of data propagation component.5. The circuit of wherein the control component includes a gated clock.6. The circuit of wherein the scan in propagation component includes a multiplexer and the data propagation component includes a multiplexer.7. The circuit of wherein the scan in propagation component is included in a keeper.8. A method comprising:receiving a scan enable indication;selecting between a scan input and a ...

Dual flip-flop circuit

A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.

FLIP-FLOP CIRCUIT HAVING A REDUCED HOLD TIME REQUIREMENT FOR A SCAN INPUT

A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal. 1. A scan flip-flop circuit , comprising: receive a scan input signal and a scan enable signal; and', 'when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels; and, 'a scan input sub-circuit configured to receive the complementary scan input signals; and', 'based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a selected input signal., 'a selection sub-circuit that is coupled to the scan input sub-circuit and configured to2. The scan flip-flop circuit of claim 1 , further comprising a storage sub-circuit configured to store the selected input signal and transfer the selected input signal to an output signal when a buffered clock signal transitions between the two different logic levels.3. The scan flip-flop circuit of claim 2 , further comprising a clock driver configured to receive the clock input signal claim 2 , generate an inverted clock signal claim 2 , and generate a buffered clock signal.4. The scan flip-flop circuit of claim 3 , wherein the clock driver is coupled to a second scan flip-flop circuit that is configured to receive the inverted clock signal and the ...

COPPER ION-COMPLEXED POLY GAMMA-GLUTAMIC ACID/CHITOSAN/COTTON BLENDED ANTIBACTERIAL KNITTED FABRIC AND PREPARATION METHOD THEREOF

A copper ion-complexed poly gamma-glutamic acid (γ-PGA)/chitosan (CS)/cotton blended antibacterial knitted fabric and a preparation method includes chitosan that is crosslinked with poly gamma-glutamic acid, then a copper-ammonia complex ion solution is added to prepare a spinning solution. The spinning solution is wet spun and then stretched, washed with water, finished, washed with water, and dried to get copper ion-complexed poly gamma-glutamic acid/chitosan composite fibers. The blended antibacterial knitted fabric is then prepared by using cotton fiber yarns and the composite fibers. There is a very high coordination coefficient between carboxyl groups of gamma-PGA and amino groups of CS, so the structure is stable. Poly-gamma glutamic acid can be used as water-retaining agent and heavy metal ion adsorbent, which can increase the loading rate of copper ions. 1. A copper ion-complexed poly gamma-glutamic acid/chitosan/cotton blended antibacterial knitted fabric , wherein , the knitted fabric is prepared as below: chitosan is crosslinked with poly gamma-glutamic acid , then a copper-ammonia complex ion solution is added to prepare a spinning solution; the spinning solution is wet spun and then stretched , washed with water , finished , washed with water , and dried to get copper ion-complexed poly gamma-glutamic acid/chitosan composite fibers , then the blended antibacterial knitted fabric is prepared by using cotton fiber yarns and the composite fibers.2. A preparation method of the copper ion-complexed poly gamma-glutamic acid/chitosan/cotton blended antibacterial knitted fabric according to claim 1 , wherein claim 1 , the method comprises the following steps:(1) aqueous ammonia is dropwise added into a copper salt solution to generate basic copper sulfate precipitates, aqueous ammonia is continually dropwise added until the precipitates are dissolved completely, to get a copper ammonia complex-ion solution;(2) 20 mg chitosan is dissolved in 20 ml acetic acid ...

SMALL AREA LOW POWER DATA RETENTION FLOP

Small area low power data retention flop. In accordance with a first embodiment of the present invention, a circuit includes a master latch coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip flop during normal operation. The data retention latch is configured to retain an output value of the master-slave flip flop during a low power data retention mode when the master latch is powered down. A single control input is configured to select between the normal operation and the low power data retention mode. The circuit may be independent of a third latch. 17-. (canceled)8. A circuit comprising:a master latch comprising:a first inverter coupled to an input of a first NAND gate;a first pass gate for selectively coupling an output of said first NAND gate to an input of said first inverter;a second pass gate for selectively coupling said an input of said first inverter to a circuit input;a data retention latch comprising:a second NAND gate coupled to an input of a second inverter;a third pass gate for selectively coupling an output of said second inverter to an input of said second NAND gate;a fourth pass gate for selectively coupling an output of said first inverter to said input of said second NAND gate;a control circuit comprising:a third NAND gate accepting as input a latch clock signal and a low power data retention control signal,wherein an output of said third NAND gate is coupled to a control input of said first, second, third and fourth pass gates, andwherein said output of said third NAND gate is inverted and coupled to the opposite control input of said first, second, third and fourth pass gates.9. The circuit of wherein said output of said third NAND gate is coupled to the non-inverted control inputs of said second and third pass gates.10. The circuit of wherein said output of said third NAND gate is coupled to the inverted control inputs of said first and ...

MITIGATING EXTERNAL INFLUENCES ON LONG SIGNAL LINES

Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal. 1. An electronic circuit comprising:a first transistor configured to selectively pull up a bit line of a memory array responsive to a clamp signal; anda second transistor configured to selectively couple said bit line and an inverted bit line of a same cell of said memory array responsive to said clamp signal.2. The electronic circuit of further comprising a third transistor configured to selectively pull up said inverted bit line responsive to said clamp signal.3. The electronic circuit of further comprising:a fourth transistor configured to selectively pull up a second bit line of a memory array responsive to a second clamp signal; anda fifth transistor configured to selectively couple said second bit line and a second inverted bit line of a same second cell of said memory array responsive to said second clamp signal.4. The electronic circuit of further comprising a sixth transistor configured to selectively pull up said second inverted bit line responsive to said second clamp signal.5. The electronic circuit of wherein said first and third transistors are further configured to precharge said bit line and said inverted ...

HIGH-INTENSITY OUTDOOR SPORTS FOOD SUPPLEMENT RICH IN BIOLOGICAL IONS AND PREPARATION METHOD THEREOF

The present disclosure relates to the technical field of food supplement application, in particular to a high-intensity outdoor sports food supplement rich in biological ions and a preparation method thereof. The sports food supplement is prepared using the following components: poly-γ-glutamic acid, magnesium sulfate, sodium carbonate, ammonium bicarbonate, potassium magnesium aspartate, potassium chloride, sodium citrate, potassium citrate, hydroxide calcium, zinc sulfate, antioxidant, preservative, extraction solution, and water. The present disclosure promotes faster recovery of middle-aged men during exercise, reduces the risk of injury, and improves the ability of high-intensity running. The concentrated solution provided by the present disclosure has no bitter taste, a slightly sweet and refreshing taste, good palatability and good stability. The present disclosure is simple in preparation, and has a wide application range, which not only can be applied to sports drinks, but also can be added to sports food. 1Schisandra chinensis. A high-intensity outdoor sports food supplement rich in biological ions , wherein it is prepared using the following components: 10-15 parts of poly-γ-glutamic acid , 6-15 parts of magnesium sulfate , 3-10 parts of sodium carbonate , 4-12 parts of ammonium bicarbonate , 5-20 parts of potassium magnesium aspartate , 2-10 parts of potassium chloride , 5-10 parts of sodium citrate , 3-12 parts of potassium citrate , 10-15 parts of hydroxide calcium , 5-20 parts of zinc sulfate , 1 part of antioxidant , 0.05 part of preservative , 3-5 parts of extraction solution , and 20 parts of water.2. The high-intensity outdoor sports food supplement rich in biological ions according to claim 1 , wherein the potassium magnesium aspartate is an equal mixture of potassium L-aspartate and magnesium L-aspartate; the antioxidant is vitamin C claim 1 , vitamin E claim 1 , citric acid or a combination thereof; the preservative is potassium sorbate or ...

FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY

This disclosure relates to an adder circuit. The adder circuit comprises an operand input and a second operand input to an XNOR cell. The XNOR cell may be configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell may transform the output of the XNOR cell into a carry out signal. 1. An adder circuit comprising:a first operand input and a second operand input to an XNOR cell;the XNOR cell configured to transform the first operand input and the second operand input utilizing a NAND gate and a first OAI cell; anda second OAI cell transforming an output of the XNOR cell into a carry out signal.2. The adder circuit of claim 1 , wherein an output of the NAND gate is coupled to an input of the first OAI cell.3. The adder circuit of claim 1 , wherein the output of the XNOR cell is further coupled to an input terminal of a pass gate.4. The adder circuit of claim 1 , further comprising:a pass gate; anda third operand input coupled to one or more control terminals of the pass gate and to an input terminal of the second OAI cell.5. The adder circuit of claim 3 , wherein the output of the XNOR cell is further coupled to the input terminal of the pass gate.6. The adder circuit of claim 3 , further comprising a tri-state inverter coupled to an output of the pass gate.7. The adder circuit of claim 6 , configured such that the tri-state inverter is controlled by a third operand input and the output of the XNOR cell.8. The adder circuit of claim 1 , wherein an output of the NAND gate is coupled to an input of the second OAI cell.9. The adder circuit of claim 1 , further comprising a third operand input and a third operand complement input.10. The adder circuit of claim 1 , further comprising a third operand input and an inverter to complement the third operand input.11. The adder circuit of claim 1 , further comprising a pass gate and an inverter configured to receive an output of the pass gate.12. A compressor ...

Calibration device and calibration method for display panel brightness uniformity

Disclosed is a calibration device and calibration method for display panel brightness-uniformity. The method includes: storing a first-mode measured brightness-value, K sets of maximum brightness-values of a display region, a set of second-mode brightness-reference-values, and a second ratio of a second-mode measured brightness-value to the first-mode measured brightness-value; calculating a second-mode brightness-value according to the first-mode measured brightness-value and the second ratio; calculating a second-mode target brightness ratio according to a target brightness setting and the second-mode brightness-value; calculating X second-mode target brightness-value(s) according to the set of second-mode brightness-reference-values and the second-mode target brightness ratio; calculating K sets of second-mode colored-component brightness-values according to the K sets of maximum brightness-values; generating X second-mode brightness curve(s) according to the K sets of second-mode colored-component brightness-values; and calculating X second-mode brightness-gain(s) for second-mode calibration according to the X second-mode target brightness-value(s) and the X second-mode brightness curve(s).

RADIATION DETECTOR DEVICE FOR REJECTING AND EXCLUDING INCOMPLETE CHARGE COLLECTION EVENTS

A radiation detector device is provided that is capable of distinguishing between full charge collection (FCC) events and incomplete charge collection (ICC) events based upon a correlation value comparison algorithm that compares correlation values calculated for individually sensed radiation detection events with a calibrated FCC event correlation function. The calibrated FCC event correlation function serves as a reference curve utilized by a correlation value comparison algorithm to determine whether a sensed radiation detection event fits the profile of the FCC event correlation function within the noise tolerances of the radiation detector device. If the radiation detection event is determined to be an ICC event, then the spectrum for the ICC event is rejected and excluded from inclusion in the radiation detector device spectral analyses. The radiation detector device also can calculate a performance factor to determine the efficacy of distinguishing between FCC and ICC events. 1. A radiation detector device , comprising:at least one radiation detector element configured to generate electrical charges in response to radiation interacting with a radiation detector material;at least one anode connected to the at least one radiation detector element and configured to output electrical signals from the radiation detector material corresponding to generated electrical charges;at least one shared cathode connected to one or more of the at least one radiation detector elements and configured to output electrical signals from the radiation detector material corresponding to generated electrical charges;a specialized radiation detector chip (SRDC) connected to the at least one anode and connected to the at least one shared cathode, wherein the SRDC is configured to receive the electrical signals, sense parameters of the received electrical signals, and output the sensed electrical signal parameters;a non-transitory computer readable storage medium storing a full charge ...

LOW TAU SYNCHRONIZER FLIP-FLOP WITH DUAL LOOP FEEDBACK APPROACH TO IMPROVE MEAN TIME BETWEEN FAILURE

A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF). 1. A flip-flop , comprising:a first loop coupled to a flip-flop input and having first and second stable states; anda second loop coupled to said first loop and having said first and second stable states, properties of cross-coupled inverters in said first and second loops creating a metastable state skewed toward said first stable state in said first loop and skewed toward said second stable state in said second loop.2. The flip-flop as recited in further comprising a transmission gate coupled between said first and second loops and said flip-flop input.3. The flip-flop as recited in wherein said first loop is a first master loop and said second loop is a second master loop claim 1 , said flip-flop further comprising:a first slave loop coupled to said first and second master loops and having said first and second stable states; anda second slave loop coupled to said first slave loop and having said first and second stable states, properties of cross-coupled inverters in said first and second slave loops creating a metastable state skewed toward said first stable state in said first slave loop and skewed toward said second stable state in said second slave loop.4. The flip-flop as recited in further comprising a transmission gate coupled between said first and second slave loops and said first and second master loops.5. The flip-flop as ...

Low power master-slave flip-flop

A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

SELECTING A NEURAL NETWORK ARCHITECTURE FOR A SUPERVISED MACHINE LEARNING PROBLEM

Systems and methods for selecting a neural network for a machine learning problem are disclosed. A method includes accessing an input matrix. The method includes accessing a machine learning problem space associated with a machine learning problem and multiple untrained candidate neural networks for solving the machine learning problem. The method includes computing, for each untrained candidate neural network, at least one expressivity measure capturing an expressivity of the candidate neural network with respect to the machine learning problem. The method includes computing, for each untrained candidate neural network, at least one trainability measure capturing a trainability of the candidate neural network with respect to the machine learning problem. The method includes selecting, based on the at least one expressivity measure and the at least one trainability measure, at least one candidate neural network for solving the machine learning problem. The method includes providing an output representing the selected at least one candidate neural network. 1. A system comprising:processing hardware; and accessing a machine learning problem space associated with a machine learning problem and a plurality of untrained candidate neural networks for solving the machine learning problem;', 'computing, for each untrained candidate neural network, at least one expressivity measure capturing an expressivity of the candidate neural network with respect to the machine learning problem;', 'computing, for each untrained candidate neural network, at least one trainability measure capturing a trainability of the candidate neural network with respect to the machine learning problem;', 'selecting, based on the at least one expressivity measure and the at least one trainability measure, at least one candidate neural network for solving the machine learning problem; and', 'providing an output representing the selected at least one candidate neural network., 'a memory storing ...

Radiation detector

Technologies are described for semiconductor radiation detectors. The semiconductor radiation detectors may comprise a semiconductor material. The semiconductor material may include a first surface and a second surface. The first surface may be opposite from the second surface. The semiconductor material may include at least one metal component. The semiconductor material may be effective to absorb radiation and induce a current pulse in response thereto. The semiconductor radiation detector may comprise an electrode contact. The electrode contact may include a metal doped oxide deposited on the first surface of the semiconductor material. The metal doped oxide may include the metal component element of the semiconductor material.

GRAPHENE OXIDE (GO)-BASED COMPOSITE NANOPARTICLE DRUG DELIVERY SYSTEM AND PREPARATION METHOD THEREOF

The present disclosure belongs to the technical field of biomedicine, and in particular relates to a graphene oxide (GO)-based composite nanoparticle drug delivery system for treating cervical cancer and a preparation method thereof. The composite nanoparticle drug delivery system includes an aptamer NH-AS1411 (Aptamer NH2-AS1411, APT), monolayer graphene oxide (GO), chitosan oligosaccharide (CO) and γ-polyglutamic acid (γ-PGA). 1. A graphene oxide-based composite nanoparticle drug delivery system , wherein raw materials for preparing the composite nanoparticle drug delivery system comprise: an aptamer NH-AS1411 , monolayer graphene oxide (GO) , chitosan oligosaccharide (CO) , γ-polyglutamic acid (γ-PGA) , 1-(3-dimethylaminopropyl)-3-ethylcarbodiimide (EDC) , N-hydroxysuccinimide (NETS) , a 2-morpholino ethanesulfonic acid buffer (MES buffer) and a phosphate buffer solution buffer (PBS buffer).2. A method for preparing the graphene oxide-based composite nanoparticle drug delivery system according to claim 1 , comprising:(1) dissolving monolayer GO in ultrapure water and pulverizing under sonication, and then centrifuging a resultant solution after the sonication to remove unexfoliated GO to obtain a GO suspension;(2) adjusting a pH value of the GO suspension to be within a range 5 to 6 with the MES buffer, and adding EDC and NETS in sequence to obtain a mixture; then sealing the mixture after sonication and placing on a shaker for reacting, followed by centrifuging to remove a supernatant to obtained a GO precipitate;(3) dissolving CO in the PBS buffer under sonication to obtain a CO solution; resuspending the GO precipitate with the CO solution, adjusting a pH value of a resultant mixed suspension to be within a range of 7.2 to 7.5 with the PBS buffer, then sealing after sonication and placing on a shaker for reacting; subsequently, centrifuging and washing a resultant reaction solution and then dialyzing to obtain GO-CO;(4) dissolving γ-PGA in ultrapure water to ...

Tear resistant blown polyethylene films

Blown films may be monolayer or multilayer where a layer comprises (or consists of) about 40 wt% to about 90 wt% of a first polyethylene, about 5 wt% to about 30 wt% of a second polyethylene, about 5 wt% to about 30 wt% of a hydrocarbon resin, and 0 wt% to about 15 wt% of an anti-drip additive.

Adsorbents for use in the separation of carbon monoxide and/or unsaturated hydrocarbons from mixed gases

Novel adsorbents for use in the separation of carbon monoxide and/or unsaturated hydrocarbons from mixed gases. An adsorbent for separating carbon monoxide or unsaturated hydrocarbon from mixed gases is made by heating a solid mixture comprising a copper compound and a support having a high surface area in a suitable atmosphere.

Low power master-slave flip-flop

本發明提供一種正反器電路，其可包括一主要閂鎖以及一從屬閂鎖。每個閂鎖皆可具有透通模式和儲存模式。在主要閂鎖處於透通模式下時，從屬閂鎖可在儲存模式下；且反之亦然。時脈信號可經由一對時脈閘控拉升電晶體和一對時脈閘控下拉電晶體(共計四個時脈閘控電晶體)控制每個閂鎖之模式。時脈閘控電晶體可由主要閂鎖和從屬閂鎖共享。相對於不共享，共享時需求的時脈閘控電晶體可較少。時脈閘控電晶體可具有寄生電容，並在經受變化的時脈信號時，由於寄生電容之充電及放電而消耗功率。具有較少的時脈閘控電晶體因而可減少正反器電路所消耗的功率。

Radiation detector device for rejecting and excluding incomplete charge collection events

A radiation detector device is provided that is capable of distinguishing between full charge collection (FCC) events and incomplete charge collection (ICC) events based upon a correlation value comparison algorithm that compares correlation values calculated for individually sensed radiation detection events with a calibrated FCC event correlation function. The calibrated FCC event correlation function serves as a reference curve utilized by a correlation value comparison algorithm to determine whether a sensed radiation detection event fits the profile of the FCC event correlation function within the noise tolerances of the radiation detector device. If the radiation detection event is determined to be an ICC event, then the spectrum for the ICC event is rejected and excluded from inclusion in the radiation detector device spectral analyses. The radiation detector device also can calculate a performance factor to determine the efficacy of distinguishing between FCC and ICC events.

Generic flexible timer design

One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.

Low power master-slave flip-flop

A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

Full adder cell with improved power efficiency

An adder circuit that includes an operand input and a second operand input to an XNOR cell. The XNOR cell is configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell transforms the output of the XNOR cell into a carry out signal.

高效真空浇筑装置

本实用新型公开了一种高效真空浇筑装置包括浇筑罐和混料罐，混料罐底部通过连通管道与浇筑罐顶部相连通，连通管道底端固定有浇筑软管，浇筑软管侧面固定有拨动机构，拨动机构包括固定于浇筑罐内顶部的拨动电机、连接杆以及拨动杆，拨动杆固定于浇筑软管上，拨动杆一侧与连接杆的一端固定连接，连接杆另一端与拨动电机相连接，拨动机构固定于浇筑罐顶部，浇筑罐内设置有导轨、设置于导轨上的导轨车以及移动驱动机构。本实用新型采用上述结构的一种高效真空浇筑装置，导轨车的移动配合浇筑软管的摆动实现两列互感器模具的浇筑，提高了生产效率。

Preparation method for hydrothermal synthesis of fly ash silicate aggregate

The present disclosure provides a preparation method for hydrothermal synthesis of fly ash silicate aggregate including: mixing sodium metasilicate, potassium hydroxide, and inorganic-organic hybrid excitation monomer as raw materials to obtain an inorganic-organic composite activator; preparing a silicate aggregate raw material, mixing measured fly ash, carbide slag, quicklime, and vitrified micro bubble by mass, adding the inorganic-organic composite activator and continue stirring to produce a mixture; forming a ball disc, wetting an expanded perlite that forms a core of the ball by spraying water, adding a prepared mixture, spraying water while adding, standing and curing, performing a maturation and activation treatment in an autoclave, undergoing a silicon calcium reaction for a hydrothermal synthesis to obtain the silicate aggregates. The present disclosure obtains silicate aggregates with high-performance by accelerating an internal activity of fly ash at an early stage and fully activating the activity of fly ash in all process.

Embolic protection device

An embolic protection device includes a frame, an edge filter screen, and a plurality of supporting rods that are arranged at intervals. Each supporting rod includes a first tail end, a second tail end, and at least one head end that faces a distal end. The first tail end and the second tail end are separately connected to two opposite sides of the frame. The first tail end and the second tail end separately form a first line segment and a second line segment with the head end. The first line segment extends in a direction from the first tail end to the head end and gradually moves away from the frame, and the second line segment extends in a direction from the second tail end to the head end and gradually moves away from the frame, such that the plurality of supporting rods support the edge filter screen, which covers the plurality of supporting rods, in a direction facing away from the frame.

Heat exchange fin, heat exchanger, and heat pump system

The present invention relates to a heat exchange fin, with a tube hole formed thereon for a heat exchange tube to be inserted into, and with a corrugated structure arranged near the tube hole, wherein the corrugated structure comprises a wave section arranged along a flow direction of fluid medium, where a distance between two adjacent wave crests or wave troughs of the wave section is one wavelength, and the total length of the wave section is 1-1.5 times the wavelength, wherein, a bridge plate is further arranged at the wave crests and wave troughs of the wave section, respectively, where the bridge plate deflects relative to the wave crests and wave troughs by a preset distance. The present invention also proposes a heat exchanger configured with the heat exchange fins, and a heat pump system configured with the heat exchanger. The heat exchange fins according to the present invention can significantly improve the heat transfer efficiency of the heat exchange fins, thereby greatly enhancing the heat exchange effect.

Heat exchange fin, heat exchanger, and heat pump system

The invention relates to a heat exchange fin, with a tube hole formed thereon for a heat exchange tube to be inserted into. A corrugated structure is arranged near the tube hole. The corrugated structure comprises a wave section arranged along a flow direction of fluid medium. The distance between two adjacent wave crests or wave troughs of the wave section is one wavelength. The total length of the wave section is 1-1.5 times the wavelength. A bridge plate is arranged at the wave crests and wave troughs of the wave section, respectively. The bridge plate deflects relative to the wave crests and wave troughs by a preset distance. The invention also proposes a heat exchanger configured with the heat exchange fins, and a heat pump system configured with the heat exchanger.

血管造影机c臂球管发生器防撞装置

本实用新型提供一种血管造影机C臂球管发生器防撞装置，包括：多个连接箱，其包括上端面和下端面，所述下端面与C臂球管发生器的端面固定连接；橡胶壳体，其为弧形空腔体，所述橡胶壳体的下端面与所述连接箱的上端面连接；弹性部件，其设置在所述连接箱内；充气气囊，其设置在所述橡胶壳体内；气压传感器，其设置在所述充气气囊内；红外线传感器，其设置在所述连接箱的下端面上；控制器，其与所述气压传感器、红外线传感器、报警器和电机连接。本实用新型实现了血管造影机自动检测和判断前进轨迹内有无障碍物，并据此控制血管造影机的运行和停止，从而有效防止将手术操作人员撞伤的人身伤害事故。

Perovskite materials for ionizing radiation detection and related methods

In accordance with the purpose(s) of the present disclosure, as embodied and broadly described herein, the disclosure, in one aspect, relates to compound Bi-poor perovskite crystals, methods for making the same, and ionizing and other electromagnetic radiation detectors constructed using the Bi-poor perovskite crystals. The Bi-poor perovskite crystals can be synthesized using melt-based growth methods and solution-based growth methods and contain no toxic heavy metals such as lead, cadmium, thallium, or mercury. Devices fabricated from the crystals maintain acceptable levels of performance over time. In some aspects, post-growth annealing can be used to improve the properties, including, but not limited to, room temperature resistivity and response to radiation.

Display substrate and display device

A chip-level disc-type acousto-optic standing wave gyroscope

Disclosed is a chip-level disc-type acousto-optic standing wave gyroscope including a substrate and a gyroscope structure placed on an upper surface of the substrate; the substrate is in a shape of a circular disc; the gyroscope structure includes an acoustic wave drive module and an optical detection module, the acoustic wave drive module is arranged in a circular shape taking the center of the circular disc as an origin and extending outward radially, and the optical detection module is arranged in the middle of the acoustic wave drive module and is annular; the acoustic wave drive module includes an annular interdigitated transducer, a metal electrode layer group uniformly sputtered on the annular interdigitated transducer, annularly arranged metallic pillars and an annular reflection grating, respectively placed in sequence from center of the disk radially to periphery of the disk; the optical detection module includes a first grating coupler, an optical waveguide at a light source input end, a first coupler, a second coupler, an optical waveguide at a signal output end and a second grating coupler, which are connected in sequence. According to the technical solution of the disclosure, the sensitivity of gyroscope detection can be improved.

Action state detection method and system for elevator brake

The present invention relates to the field of elevator braking, in particular to an action state detection method and system for an elevator brake, comprising: acquiring matching pairs of brake linings in the same braking state; constructing normal record data sets based on the matching pairs; grouping the normal record data sets based on braking power corresponding to samples in the normal record data sets to determine a median of elevator running speed corresponding to the samples in each group; dividing the operating state levels of the elevator brake according to the size of the median; constructing a data training set; training a constructed network model to obtain a trained network model; acquiring the operating state levels of an elevator to be detected by the trained network model, evaluating the elevator brake according to the operating state levels, and controlling the elevator.

Deep neural network-based method for detecting living cell morphology, and related product

A deep neural network-based method for detecting living cell morphology may include identifying and locating one or more living cells within an acquired image to be detected by using a deep neural network-based target detection model, so as to extract one or more living single cell images. segmenting the image of the one or more living single cells by using a deep neural network-based cell segmentation model, so as to obtain one or more feature part of the one or more living single cells. and analyzing and determining a morphological parameter of the one or more living single cells based on the one or more feature parts. Thus, the activity of the detected cells can be ensured, and a non-destructive, accurate, and rapid detection of living cell morphology can be achieved.

Hyperparameter transfer via the theory of infinite-width neural networks

Systems and method are provided that are directed to tuning a hyperparameter associated with a small neural network model and transferring the hyperparameter to a large neural network model. At least one neural network model may be received along with a request for one or more tuned hyperparameters. Prior to scaling the large neural network, the large neural network is parameterized in accordance with a parameterizing schemed. The large neural network is then scaled and reduced in size such that a hyperparameter tuning process may be performed. A tuned hyperparameter may then be provided to a requestor such that the hyperparameter can be directly input into the large neural network. By tuning a hyper parameter using a small neural network, significant computation cycles and energy may be saved.

Writing panel and manufacturing method therefor, and writing board

A writing panel includes an array substrate, a flexible substrate disposed opposite to the array substrate, a liquid crystal layer disposed between the array substrate and the flexible substrate, and a plurality of spacers each in a shape of a column disposed on a surface of the array substrate proximate to the liquid crystal layer. The array substrate includes a base and a pixel driving circuit layer disposed on the base, and the pixel driving circuit layer includes a plurality of thin film transistors and a plurality of signal lines. An orthographic projection of each spacer on the base is non-overlapping with orthographic projections of the plurality of thin film transistors and the plurality of signal lines on the base.

Apparatus and method for preventing current leakage when a low voltage domain is powered down

Method for preparing modified multi-branched polyether demulsifier

The present invention relates to a method for synthesizing and modifying a multi-branched polyether demulsifier. The method includes: (1) mixing, heating and dissolving 2,2-bis(4-hydroxyphenyl) propane and triethylene tetramine, then performing a thermal insulation reaction in a formaldehyde solution, adding xylene for backflow dehydration, then heating to evaporate the xylene and enabling remaining substances to react to generate an initiator; (2) using potassium hydroxide as a catalyst, putting the initiator into a high-temperature high-pressure reaction kettle, sealing and vacuumizing the reaction kettle, and adding propylene oxide, so as to enable a polyether reaction in the reaction kettle to generate an intermediate product 1; (3) with potassium hydroxide as a catalyst, putting the intermediate product 1 into the high-temperature high-pressure reaction kettle, sealing and vacuumizing the reaction kettle, and introducing ethylene oxide, so as to enable a polyether reaction in the reaction kettle to generate a multi-branched polyether B; and (4) with potassium hydroxide as a catalyst, heating the multi-branched polyether B in a water bath, and slowly and dropwise adding epoxy chloropropane for modification to generate the multi-branched polyether demulsifier. The present invention has the beneficial effects of safety, environmental friendliness, a satisfactory surface tension reduction efficiency and effect, excellent hydrophilcity, wettability and permeability, rapid approach to an oil-water interface, a high dehydration rate, a reduced usage amount, a desirable demulsification effect, a high demulsification rate as well as an improved crude oil production efficiency.

Deep neural network-based method for detecting living cell morphology, and related product

The present disclosure relates to a deep neural network-based method for detecting living cell morphology, and related products. The method includes: identifying and locating one or more living cells within an acquired image to be detected by using a deep neural network-based target detection model, so as to extract one or more living single cell images; segmenting the living single cell image(s) by using a deep neural network-based cell segmentation model, so as to obtain one or more feature part of the living single cell(s); and analyzing and determining a morphological parameter of the living single cell(s) based on the feature part(s). According to the method of the present disclosure, the activity of the detected cells can be ensured, and a non-destructive, accurate, and rapid detection of living cell morphology can be achieved, which is beneficial for the clinical application and research of the detected cells.

Liquid crystal handwriting board, handwriting system, and control method for handwriting system

Provided is a liquid crystal handwriting board. The liquid crystal handwriting board includes: a liquid crystal panel, a photosensitive assembly, and a control assembly; wherein the liquid crystal panel includes a first substrate and a second substrate that are opposite; the photosensitive assembly includes a plurality of photosensitive elements; and the control assembly is electrically connected to the liquid crystal panel and the photosensitive assembly, and is configured to determine position information of a pixel region for erasure by detecting position information of target light irradiated to the liquid crystal panel by the photosensitive assembly and supply a pixel voltage to the plurality of pixel electrodes in the pixel region for erasure, such that a voltage difference is present between the plurality of pixel electrodes in the pixel region for erasure and the common electrode.

Display panel and display apparatus

A display panel and a display apparatus. The display panel has a display area (AA) and a binding area (BOD). The display panel comprises a color film substrate (3) and an array substrate (1), wherein the color film substrate (3) comprises a near-field communication antenna (32), the near-field communication antenna (32) comprises a coil structure (35), and the coil structure (35) is at least partially located in the display area (AA); and the array substrate (1) comprises a first base substrate (101), a channel region (1061) and a non-channel region, wherein an orthographic projection of the coil structure (35) on the first base substrate (101) is located within an orthographic projection of the non-channel region on the first base substrate (101). Electromagnetic interference that is generated toward a thin-film transistor during operation of the near-field communication antenna (32) is reduced, thereby improving the display effect of the display panel.

Complément Alimentaire à Base de Silicium et son Procédé de Préparation

La présente invention appartient au domaine technique de la préparation et de l’application des compléments alimentaires et elle concerne, en particulier, un complément alimentaire à base de silicium et son procédé de préparation. Le complément est constitué des matières premières suivantes : polyacide γ-glutamique, chitosane hydrosoluble, solution aqueuse de silicate, amidon, xylitol, stéarate de magnésium, acide citrique et eau. Le carboxyle du γ-PGA et l’amino du CS utilisés ici possèdent un coefficient de coordination assez élevé et une structure stable, ce qui permet d’améliorer la solubilité des silicates. Avec une douceur adéquate et une bonne sensation en bouche, le complément est une source majeure d’apport en silicium dans les régimes alimentaires. Le complément alimentaire à base de silicium préparé selon l’invention est riche en élément Si, simple à préparer, sûr et inoffensif. En raison de l’ajout de chitosane, le comprimé de complément présente une plus forte affinité pour le corps humain ; et le polyacide γ-glutamique est ajouté pour jouer un rôle synergique avec le silicate dans la croissance des os et des tissus conjonctifs, ce qui aide à résister à l’ostéoporose et réduit le risque d’ostéoporose.

Liquid crystal handwriting board, handwriting device, and method for controlling handwriting device

A liquid crystal handwriting board, comprising: a liquid crystal panel (001) and a driving assembly (002). The liquid crystal panel (001) comprises: a first substrate (100) and a second substrate (200) which are arranged opposite to each other, and a liquid crystal layer (300) located between the first substrate (100) and the second substrate (200). As pixel electrodes (101) in the first substrate (100) of the liquid crystal panel (001) are a plurality of block electrodes, when the liquid crystal handwriting board is in an erasing mode, the driving assembly (002) electrically connected to the liquid crystal panel (001) can apply, on the basis of position information of an area to be erased, a pixel voltage to a block pixel electrode (101) in said area, so that a voltage difference is formed between the pixel electrode (101) in said area and a common electrode (201), and thus liquid crystal molecules located in said area in the liquid crystal layer (300) is rearranged under the action of the voltage difference, achieving erasion of a local area of the liquid crystal handwriting board. Also provided are a handwriting apparatus, and a method for controlling the handwriting apparatus.

Liquid crystal handwriting board, handwriting device, and method for controlling handwriting device

Provided is a liquid crystal handwriting board. The liquid crystal handwriting board includes: a liquid crystal panel, and a drive assembly electrically connected to the liquid crystal panel; wherein the liquid crystal panel includes: a first substrate and a second substrate that are opposite to each other, and a liquid crystal layer disposed between the first substrate and the second substrate; and the drive assembly is configured to apply, based on position information of a region to be erased, a pixel voltage to a pixel electrode in the region to be erased in the case that the liquid crystal handwriting board is in an erasing mode, such that a voltage difference is developed between the pixel electrode in the region to be erased and the common electrode.

Structual member of guided fasterning connection for elevator guide rail

A structural member of guided fastening connection for an elevator guide rail includes a vertical docking plate, wherein a fixing side plate is welded on two sides of the vertical docking plate symmetrically, a fixing hole is provided on a side of the fixing side plates, an upright plugging plate is welded at two ends of the vertical docking plate symmetrically, the upright plugging plates are docked with a first buckling block on a side, the upright plugging plates are docked with a second buckling block on a side away from the first buckling blocks, the fixing side plates are welded with a lateral arc-shaped plate horizontally on a side away from the vertical docking plate, a turnover strut is provided between the lateral arc-shaped plates horizontally, a middle fixing rod is plugged within a top face of the lateral arc-shaped plates.

用于血管造影机的防撞装置

本实用新型公开了一种用于血管造影机的防撞装置，其设置在血管造影机的球管发生器上，其包括：防撞条，其设置在所述球管发生器的外壳上，所述防撞条上镶嵌有距离传感器和警报发生器，当距离传感器检测数值小于预设阈值时，启动警报发生器；以及连接桥，其包括固定至所述球管发生器外壳顶部的横梁和连接至所述横梁两端的两个纵梁，所述纵梁的另一端连接至所述防撞条。本实用新型结构简单，安装方便，能够在C型臂球管发生器端到达极限位置时，发出警报，提醒助手和手术操作者避免造成撞击。

一种用于悬臂式掘进机的新型钻头

本实用新型属于轨道交通工程装备技术领域，具体涉及一种用于悬臂式掘进机的新型钻头。解决了现有悬臂式掘进机截割头在工作中无法有效破碎硬岩、工作效率低、安全风险大的问题。本实用新型的技术方案是：包括截割钻头(3)、壳体(10)和冲击钻头(1)，所述截割钻头(3)与壳体(10)连接，截割钻头(3)中部设置有滑道，所述滑道中设置有冲击器(2)，冲击钻头(1)与冲击器(2)连接，所述壳体(10)内部连接有切割头轴轴套(8)，所述切割头轴轴套(8)与截割钻头(3)连接。本实用新型能够对硬岩进行切割破碎，提高了掘进机的掘进效率，减小掘进机的故障率，不需要额外的人工作业，降低了施工的安全风险。本实用新型适用于含有硬岩的隧道、巷道等的掘进。

Perovskite materials for ionizing radiation detection and related methods

In accordance with the purpose(s) of the present disclosure, as embodied and broadly described herein, the disclosure, in one aspect, relates to compound Bi-poor perovskite crystals, methods for making the same, and ionizing and other electromagnetic radiation detectors constructed using the Bi-poor perovskite crystals. The Bi-poor perovskite crystals can be synthesized using melt-based growth methods and solution-based growth methods and contain no toxic heavy metals such as lead, cadmium, thallium, or mercury. Devices fabricated from the crystals maintain acceptable levels of performance over time. In some aspects, post-growth annealing can be used to improve the properties, including, but not limited to, room temperature resistivity and response to radiation.

Selecting a neural network architecture for a supervised machine learning problem

Systems and methods for selecting a neural network for a machine learning problem are disclosed. A method includes accessing an input matrix. The method includes accessing a machine learning problem space associated with a machine learning problem and multiple untrained candidate neural networks for solving the machine learning problem. The method includes computing, for each untrained candidate neural network, at least one expressivity measure capturing an expressivity of the candidate neural network with respect to the machine learning problem. The method includes computing, for each untrained candidate neural network, at least one trainability measure capturing a trainability of the candidate neural network with respect to the machine learning problem. The method includes selecting, based on the at least one expressivity measure and the at least one trainability measure, at least one candidate neural network for solving the machine learning problem. The method includes providing an output representing the selected at least one candidate neural network.

トルコギキョウ抽出物を含む組成物

【課題】トルコギキョウの抽出物を含む医薬組成物及びスキンケア組成物の提供。【解決手段】トルコギキョウの植物全体、又はトルコギキョウの根、葉を伴う茎、及び／又は花を、Ｃ１−Ｃ６アルコール、水、及びこれらの組み合わせからなる極性溶媒により抽出して調製される抽出物を含有し、１，１−ジフェニル−２−ピクリルヒドラジル（ＤＰＰＨ）フリーラジカルの捕捉、マトリックスメタロプロテアーゼ（ＭＭＰｓ）活性の阻害、及び／又はエラスターゼ活性の阻害に有効である、医薬組成物及びスキンケア組成物。【選択図】なし

pH探针标定清洗和干燥装置

本实用新型公开了一种pH探针标定清洗和干燥装置，包括：支架、盖板、pH探针标定模块、pH探针清洗模块和pH探针干燥模块；所述pH探针标定模块和pH探针干燥模块均设置在所述支架上，所述盖板设置在所述pH探针标定模块和pH探针干燥模块的上方，所述盖板上开设有安装槽，所述pH探针清洗模块设置在所述安装槽内。本实用新型集成pH探针的标定、清洗和干燥功能于一体，并且充分考虑到生物化工等行业中pH探针标定清洗和干燥的实际需求，能实现高通量自动化pH探针的标定、清洗和干燥，符合现代生物化学实验的高通量的大发展方向；本实用新型结构简单，各模块布置紧凑，装置体积小，使用方便，具有很好的推广应用前景。

System for training an artificial neural network

Embodiments of the present disclosure include a system for optimizing an artificial neural network by configuring a model, based on a plurality of training parameters, to execute a training process, monitoring a plurality of statistics produced upon execution of the training process, and adjusting one or more of the training parameters, based on one or more of the statistics, to maintain at least one of the statistics within a predetermined range. In some embodiments, artificial intelligence (AI) processors may execute a training process on a model, the training process having an associated set of training parameters. Execution of the training process may produce a plurality of statistics. Control processor(s) coupled to the AI processor(s) may receive the statistics, and in accordance therewith, adjust one or more of the training parameters to maintain at least one of the statistics within a predetermined range during execution of the training process.

System for training an artificial neural network

Embodiments of the present disclosure include a system for optimizing an artificial neural network by configuring a model, based on a plurality of training parameters, to execute a training process, monitoring a plurality of statistics produced upon execution of the training process, and adjusting one or more of the training parameters, based on one or more of the statistics, to maintain at least one of the statistics within a predetermined range. In some embodiments, artificial intelligence (AI) processors may execute a training process on a model, the training process having an associated set of training parameters. Execution of the training process may produce a plurality of statistics. Control processor(s) coupled to the AI processor(s) may receive the statistics, and in accordance therewith, adjust one or more of the training parameters to maintain at least one of the statistics within a predetermined range during execution of the training process.

Action state detection method and system for elevator brake

The present invention relates to the field of elevator braking, in particular to an action state detection method and system for an elevator brake, comprising: acquiring matching pairs of brake linings in the same braking state; constructing normal record data sets based on the matching pairs; grouping the normal record data sets based on braking power corresponding to samples in the normal record data sets to determine a median of elevator running speed corresponding to the samples in each group; dividing the operating state levels of the elevator brake according to the size of the median; constructing a data training set; training a constructed network model to obtain a trained network model; acquiring the operating state levels of an elevator to be detected by the trained network model, evaluating the elevator brake according to the operating state levels, and controlling the elevator.

Display panel and display panel motherboard

Provided is a display panel. The display panel includes a driver circuit, at least one to-be-detected line, and at least one conductive line in one-to-one correspondence with the at least one to-be-detected line. Any to-be-detected line in the at least one to-be-detected line includes a first sub-line and a second sub-line arranged separating from each other, and another end of the second sub-line is exposed out of an edge of the display panel. The second sub-line is configured to be electrically connected to a detection unit outside the display panel prior to cutting of a display panel motherboard including the display panel.

Structural member of guided fastening connection for elevator guide rail

A structural member of guided fastening connection for an elevator guide rail includes a vertical docking plate, wherein a fixing side plate is welded on two sides of the vertical docking plate symmetrically, a fixing hole is provided on a side of the fixing side plates, an upright plugging plate is welded at two ends of the vertical docking plate symmetrically, the upright plugging plates are docked with a first buckling block on a side, the upright plugging plates are docked with a second buckling block on a side away from the first buckling blocks, the fixing side plates are welded with a lateral arc-shaped plate horizontally on a side away from the vertical docking plate, a turnover strut is provided between the lateral arc-shaped plates horizontally, a middle fixing rod is plugged within a top face of the lateral arc-shaped plates.

Display substrate and display apparatus

There is provided a display substrate having a display region, and a peripheral region surrounding the display region, and including: a base substrate; first conductive structures in the display region and the peripheral region; the first conductive structures each extend in a first direction and are arranged side by side in a second direction; an interlayer insulation layer on a side of the first conductive structures away from the base substrate; second conductive structures on a side of the interlayer insulation layer away from the base substrate; the second conductive structures each extend in the second direction and are arranged side by side in the first direction; the second conductive structures intersect with the first conductive structures, and are electrically connected with the first conductive structures through vias in the interlayer insulation layer; and at least one third conductive structure in the display region. A display apparatus is provided.

Array substrate and method for manufacturing same, and liquid crystal panel

Provided is an array substrate. The array substrate has a display region and a non-display region disposed on a periphery of the display region. The array substrate includes a substrate and a plurality of patterned film layer structures stacked on the substrate. The plurality of the patterned film layer structures are configured to form a plurality of sub-pixels. The plurality of sub-pixels include a plurality of first sub-pixels within the display region and a plurality of virtual sub-pixels within the non-display region. An area of an orthographic projection of a pixel electrode of the virtual sub-pixel on the substrate is greater than an area of an orthographic projection of a pixel electrode of the first sub-pixel on the substrate.

用于血管造影机术中患者约束装置

本实用新型公开了一种用于血管造影机术中患者约束装置，其包括：主支撑件，其可拆卸连接在血管造影机导管床床体底面上，沿所述血管造影机导管床床体的长度方向延伸；束缚带收纳盒，其包括可滑动连接至所述主支撑件两侧的两个盒体，所述两个盒体内均设置有自动收卷装置，所述自动收卷装置上收卷有束缚带；所述束缚带上连接有锁扣组件；所述束缚带自盒体内抽出，利用锁扣组件连接两个盒体的束缚带将患者束缚在血管造影机导管床床体上。本实用新型能够将患者固定在导管床上，并使患者在手术过程中保持稳定体位，提高手术效率。

Financial circuit and web3 tokenomics theory

The present invention provides a new theoretical system for the theorizing of financial engineering in the form of financial circuit. The theoretical system of financial circuit includes: 1. Theoretical definition of basic elements and components in financial circuit; 2. The basic relationship between elements and components by the form of theorems and formulas; 3. Three standard financial circuit theoretical models provided as examples, including Financial Thévenin ' s Theorem, Financial Kirchhoff's Cash Flow Law, and Financial Kirchhoff 's Value Law. The financial circuit theory, based on the definition and the relationships of its basic elements and important components, has disclosed a complete set of financial circuit principles corresponding to the basic principle paradigm of physical circuit. The functional relationship of various elements and components in financial circuit conforms to the basic laws of financial circuit principles according to the laws transferred from the physical circuit paradigm.

Mir-7-5p mimic for inhibiting migration and invasion of breast cancer, screening method and application thereof

The present invention belongs to the technical field of biomedicine, and mainly relates to a miR-7-5p mimic for inhibiting migration and invasion of breast cancer, a screening method and an application thereof. The sequence of the miR-7-5p is shown in SEQ ID NO.1. The present invention has found that the miR-7-5p mimic generates a significant inhibitory effect on breast cancer through targeted inhibition of the molecular mechanism of RYK. In vitro culture system, the miR-7-5p mimic can function to inhibit migration and invasion capabilities of breast cancer. The miR-7-5p mimic can inhibit RYK protein and mRNA levels in breast cancer. In nude mice, the miR-7-5p mimic can also significantly inhibit migration and invasion capabilities of breast cancer. Therefore, the present invention demonstrates that the miR-7-5p mimic can be a small-nucleic-acid drug to significantly inhibit breast cancer metastasis.

洋桔梗萃取物之應用

一種使用洋桔梗萃取物於製造藥劑或護膚產品之用途。該藥劑或護膚產品尤其可用於提供清除1,1-二苯基-2-三硝基苯肼(1,1-diphenyl-2-picrylhydrazyl，DPPH)自由基、抑制基質金屬蛋白酶(matrix metalloproteinases，MMPs)活性、及/或抑制彈性蛋白酶(elastase)活性之效益。

文具組合

PREPARATION METHOD OF MgO/GQD/CHITOSAN OLIGOSACCHARIDE/PVA COMPOSITE ADSORPTIVE MEMBRANE

The present disclosure belongs to the field of sewage treatment, and.specifically relates to a preparation.method.of an.MgO/GQD/chitosan oligosaccharide/PVA.composite adsorptive membraneandaniapplicationthereof.Inthispreparationnethod, a magnesium. chloride solution. is dropwise added into a dispersion of graphene oxide quantum dots and stirred to get a mixed solution of the magnesium chloride solution and the dispersion.of graphene oxide quantum.dots, into which is added a surfactant and reacted, then calcined. to get MgO/GQD nanocomposites; chitosan oligosaccharide is dissolved in an acetic acid solution, into which are added the MgO/GQD nanocompositesandaacrosslinker,stirred,adjustedtheEflL and stirred.magnetically for 0.8—1.5 h; then washed.to neutral and lyophilized to get MgO/GQD/chitosan oligosaccharide nanocomposite powder; the composite powder is dissolved in water together with PVA, the resulting mixed solution is spun toformthecompositeadsorptivemembrane.TheMgO/GQD/chitosan oligosaccharide/PVA.composite adsorptive membrane prepared.in the present disclosure has the advantages of large adsorption capacity, good mechanical strength, recoverability and excellent biological properties.

天仙果萃取物用於防止皮膚老化之用途

Construction and culture method of breast tumor cell transplanted with yeast cell mitochondrion

The present invention relates to a method of constructing and culturing a breast tumour cell transplanted with a yeast cell mitochondrion. The method comprises the following steps: culturing a Saccharomyces cerevisiae cell, obtaining a yeast cell mitochondrion crude extract by multi-step differential centrifugation, obtaining a purified yeast cell mitochondrion from the yeast cell mitochondrion crude extract by sucrose density gradient centrifugation and adding the purified yeast cell mitochondrion into a culture solution of an MDA-MB-231 breast tumour cell, and performing co-incubation culture for 12 hours to obtain MDA-MB-231 cells containing yeast mitochondrion. Preferably the Saccharomyces cerevisiae is cultured to logarithmic growth phase in media comprising 2.5% glucose, 2.5% peptone and 1% yeast extract. Optionally the crude mitochondrion are obtained by pelleting the yeast cells, disrupting the yeast cells with glass beads and vortexing. To obtain pure mitochondria sucrose density gradient centrifugation is performed at 140,000 g for 1 – 1.5 hours at 2˚C. The MDA-MB-231 cells are grown as adherent cells in DMEM until 50 – 80% confluent.

Kleinleistungs-Einzelanschluss-Pegelschieber unter Verwendung eines Abschaltsignals aus einem Ausgangsleistungsbereich und ein Verfahren zum Umwandeln eines Datensignals zwischen Leistungsbereichen

Spannungspegelschieber (130; 400) mit:einer Eingangsschaltung (132; 410), die ausgebildet ist, ein Datensignal (Daten Ein, Daten Ein (n); A_IN) aus einem Eingangsleistungsbereich (110) und ein Leistungsabschaltsignal (PD; B_PD) aus einem Ausgangsleistungsbereich (120) zu empfangen; undeiner Übergangsschaltung (134; 420), die mit der Eingangsschaltung (132; 410) verbunden und ausgebildet ist, das Datensignal (Daten Ein, Daten Ein (n); A_IN) und ein invertiertes Signal des Leistungsabschaltsignals (PD; B_PD) zu empfangen, wobei die Eingangsschaltung (132; 410) und die Übergangsschaltung (134; 420) jeweils ausgebildet sind, mit einer Ausgangsversorgungsspannung (B_VDD) des Ausgangsleistungsbereichs (120) als eine Leistungsquelle in Verbindung zu stehen, wobei die Eingangsschaltung (132; 410) einen ersten Schalter (N4), der ausgebildet ist, die Ausgangsversorgungsspannung (B_VDD) zu empfangen, und einen zweiten Schalter (N1), der ausgebildet ist, eine Eingangsversorgungsspannung (A_VDD) des Eingangsleistungsbereichs (110) zu seiner Funktionssteuerung zu empfangen, umfasst, wobei eine Funktion des ersten Schalters (N4) auf einer Spannungsdifferenz zwischen der Eingangsversorgungsspannung (A_VDD) und der Ausgangsversorgungsspannung (B_VDD) beruht.