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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 35. Отображено 33.
24-01-2013 дата публикации

LATCH CIRCUIT WITH A BRIDGING DEVICE

Номер: US20130021078A1
Автор: Alben Jonah M., Dally William James, Elkin Ilyas
Принадлежит:

One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors. 1. A latch circuit , comprising:a storage sub-circuit configured to propagate an input signal to generate an output signal while a clock signal is high, capture a level of the input signal when the clock signal transitions from high to low and hold the level to generate the output signal while the clock signal is low;a bridging transistor configured to enable a path between the storage sub-circuit and a power supply; anda propagation sub-circuit configured to receive the input signal and propagate the level of the input signal to generate the output signal while the clock signal is high, wherein at least one pull-down transistor activates the propagation sub-circuit when the clock signal is high and deactivates the propagation sub-circuit when the clock signal is low.2. The latch circuit of claim 1 , wherein the propagation sub-circuit comprises:a first input transistor that receives the input signal and is coupled to a first pull-down transistor of the at least one pull-down transistor; anda second input transistor that receives an inverted input signal and is coupled to a second pull-down transistor of the at least one pull-down transistor.3. The latch circuit of claim 1 , wherein the propagation sub-circuit comprises:a first input transistor that receives the input signal and is coupled to a single pull-down transistor of the at least one pull-down transistor;a second input transistor that ...

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Номер записи: 1
24-01-2013 дата публикации

VIA RESISTANCE ANALYSIS SYSTEMS AND METHODS

Номер: US20130021107A1
Автор: Elkin Ilyas, Gupta Puneet, Poppe Wojciech Jakub
Принадлежит: NVIDIA CORPORATION

Component characteristics analysis systems and methods are described. In one embodiment, a ring oscillator comprises: at least one inversion stage operable to cause a signal transition; a target component that has an increased comparative impact or influence on a signal transition propagation in the ring oscillator; and an output component for outputting an indication of the impact the target component has on the signal transition. The target component can include a plurality of vias from one metal layer to another metal layer. The plurality of vias from one metal layer to another metal layer can be configured in a cell. The vias can correspond to a via layer. In one exemplary implementation, the output is coupled to an analysis component. The analysis component can include correlation of the via resistance into a wafer variations and generate a wafer map. The analysis component can include correlation of the via resistance into a wafer. 1. A ring oscillator comprising:at least one inversion stage operable to cause a signal transition; wherein said inverting stage is coupled to another component through a via layer in which a resistance due to characteristics of the via layer coupling has a relatively significant impact on a transition of a signal through a ring path; andan output component for outputting an indication of the impact the via resistance has on the signal transition of the signal through the ring oscillator.2. A ring oscillator of in which the coupling through the via layer includes a first horizontal metal layer component at one level and a second horizontal metal layer component at another level and a vertical component coupling the first horizontal metal layer component at one level and a second horizontal metal layer at another level.3. A ring oscillator of wherein the first horizontal metal layer component claim 2 , the second horizontal metal layer component and the vertical component are configured to form a reduced coupling enclosure area for ...

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Номер записи: 2
31-01-2013 дата публикации

COUPLING RESISTANCE AND CAPACITANCE ANALYSIS SYSTEMS AND METHODS

Номер: US20130027140A1
Автор: Elkin Ilyas, Gupta Puneet, Poppe Wojciech Jakub
Принадлежит: NVIDIA CORPORATION

The described systems and methods can facilitate examination of device parameters including analysis of relatively dominant characteristic impacts on delays. In one embodiment, at least some coupling components (e.g., metal layer wires, traces, lines, etc.) have a relatively dominate impact on delays and the delay is in part a function of both capacitance and resistance of the coupling component. In one embodiment, a system comprises a plurality of dominate characteristic oscillating rings, wherein each respective one of the plurality of dominate characteristic oscillating rings includes a respective dominate characteristic. Additional analysis can be performed correlating the dominate characteristic delay impact results with device fabrication and operation. 1. A system comprising: a coupling resistance relative to a channel resistance; and', 'a coupling capacitance relative to a coupling capacitance of another respective one of the plurality of dominate characteristic oscillating rings; and, 'a plurality of dominate characteristic oscillating rings, wherein each respective one of the plurality of dominate characteristic oscillating rings includes at least one dominate characteristic inversion stage with a respective dominate characteristic based uponan analysis component operable to analyze an indication of the respective dominate characteristic associated with each respective one of the plurality of dominate characteristic oscillating rings.2. A ring oscillator of wherein the dominate characteristic includes:a high channel resistance relative to a coupling resistance of the at least one dominate characteristic inversion stage; anda low coupling capacitance relative to coupling capacitance of another dominate characteristic inversion stage in another one of the plurality of dominate characteristic oscillating rings.3. A ring oscillator of wherein the dominate characteristic includes:a high channel resistance relative to a coupling resistance of the at least one ...

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Номер записи: 3
02-05-2013 дата публикации

SYSTEM AND METHOD FOR EXAMINING ASYMETRIC OPERATIONS

Номер: US20130106438A1
Автор: Elkin Ilyas, Poppe Wojciech Jakub
Принадлежит: NVIDIA CORPORATION

Systems and methods for transition delay measuring are presented. A transition delay measuring method can include oscillating a signal between states and tracking an indication associated with an isolated attribute of the transitions between the states. Oscillations can include asymmetric transitions between the states and the tracked isolated attribute can be a delay in completing transitions between the states in one direction or vice versa. The asymmetric transitions can include transitions between the first state and the second state that are faster than slower transitions between the second state and the first state or vice versa. The tracked indication can be utilized in analysis of the isolated transition delay characteristics. The results can be utilized in analysis of various further features and characteristics (e.g., examination of leakage current related power consumption, timing of asymmetric operation, etc.). The analysis can include examination of fabrication process and operating parameters. 1. A delay measuring system comprising:a first transition stage including a first component under test, the first transition stage operable to cause a first inversion transition;a second transition stage including a second component under test, the second transition stage operable to cause a second inversion transition, wherein an amount of time to complete the first inversion transition is different from an amount of time to complete the second inversion transition; anda transition completion detection component coupled to the first component under test and the second component under test, wherein the transition completion detection component is operable to detect an indication of a delay measurement between initiating the second inversion transition to completing the second inversion transition.2. The delay measuring system of wherein the first component under test claim 1 , the second component under test and the transition completion detection component are ...

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Номер записи: 4
02-05-2013 дата публикации

SYSTEM AND METHOD FOR EXAMINING LEAKAGE IMPACTS

Номер: US20130106524A1
Автор: Elkin Ilyas, Poppe Wojciech Jakub
Принадлежит: NVIDIA CORPORATION

Leakage inversion systems and methods are described. A leakage inverter can be configured to transition a signal, wherein a leakage characteristic impacts a transition of the signal. The leakage inverter can be included in an oscillating ring path that outputs an indication of the impacts the leakage characteristic has on a transition of a signal. A leakage inverter can include a leakage transistor coupled in series between a pull up transistor and a pull down transistor, wherein leakage in the leakage transistor impacts at least one transition of the signal. A pull down transition delay can be asymmetric (e.g., fast/slow, short/long, etc.) with respect to a pull up transition delay. Asymmetry can be associated with an effect of the leakage current on a transition of the signal. Results can be utilized in a variety of different analysis (e.g., analyze manufacturing process compliance and defects, leakage current power consumption, etc.). 1. A ring oscillator comprising:at least one leakage inverter configured to transition a signal, wherein a leakage characteristic impacts a transition of the signal and wherein the at least one leakage inverter is coupled as part of a ring path; andan output that outputs an indication of the impacts the leakage characteristic has on the transition of the signal.2. The ring oscillator of in which an output signal of the at least one leakage inverter has a rising transition delay and a falling transition delay that are asymmetric.3. The ring oscillator of in which an output signal of the at least one leakage inverter has a rising transition delay that is relatively fast and a falling transition delay that is relatively slow.4. The ring oscillator of in which an output signal of the at least one leakage inverter has a rising transition delay that is relatively slow and a falling transition delay that is relatively fast.5. The ring oscillator of in which the at least one leakage inverter includes a leakage component coupled in series ...

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Номер записи: 5
02-05-2013 дата публикации

Determining on-chip voltage and temperature

Номер: US20130110437A1
Автор: Abhishek Singh, Ilyas Elkin, Wojciech Jakub Poppe
Принадлежит: Nvidia Corp

A method, in one embodiment, can include modeling and calibrating two types of sensors that are part of a semiconductor device. In addition, the method can include determining a temperature and voltage based on data received from the two sensors.

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Номер записи: 6
13-03-2014 дата публикации

CLOCK GATING LATCH, METHOD OF OPERATION THEREOF AND INTEGRATED CIRCUIT EMPLOYING THE SAME

Номер: US20140070847A1
Автор: Alben Jonah, Elkin Ilyas, Yang Ge
Принадлежит: NVIDIA CORPORATION

A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method. In one embodiment, the clock gating latch includes: (1) a propagation circuit having a single, first switch configured to be driven by an input clock signal, (2) a keeper circuit coupled to the propagation circuit and having a single, first switch configured to be driven by the input clock signal and (3) an AND gate coupled to the propagation circuit and the keeper circuit and having an internal node coupled to a second switch in the propagation circuit and a second switch in the keeper circuit. 1. A clock gating latch , comprising:a propagation circuit having a single, first switch configured to be driven by an input clock signal;a keeper circuit coupled to said propagation circuit and having a single, first switch configured to be driven by said input clock signal; andan AND gate coupled to said propagation circuit and said keeper circuit and having an internal node coupled to a second switch in said propagation circuit and a second switch in said keeper circuit.2. The clock gating latch as recited in wherein said clock gating latch has a first node located between third and fourth switches of said propagation circuit and an inverter of said keeper circuit claim 1 , said node coupled to a first input of said AND gate and between said first and second switches of said keeper circuit.3. The clock gating latch as recited in wherein said AND gate is formed by a combination of a NAND gate and an inverter claim 1 , said internal node located between said NAND gate and said inverter.4. The clock gating latch as recited in wherein a high state of said input clock signal prevents a signal provided via second switch of said propagation circuit from driving an inverter in said keeper circuit and said AND gate.5. The clock gating latch as recited in wherein said first switch of said propagation circuit is a PFET switch and said first switch of ...

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Номер записи: 7
29-01-2015 дата публикации

LOW POWER MASTER-SLAVE FLIP-FLOP

Номер: US20150028927A1
Автор: Elkin Ilyas, Yang Ge
Принадлежит:

A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit. 1. A flip-flop circuit comprising: a first clock gated pull-up transistor, coupled to a supply voltage, and', 'a second clock gated pull-up transistor, coupled to the supply voltage;, 'a clocked pull-up component comprising 'a complement pull-up logic cone configured to generate the complement level of the embedded logic function of the data input bundle, coupled between the first clock gated pull-up transistor and the master complement storage node, and a true pull-up logic cone configured to generate the true level of the embedded logic function of the data input bundle, coupled between the second clock gated pull-up transistor and the master true storage node; and', 'a master latch component configured to propagate a true level of an embedded logic function of a data input bundle to a master true storage node, and a complement of the level of the embedded logic function of the data input bundle to a master complement storage node when a clock signal is at a first level; and to hold a first value of the master true storage node and hold a second value of the master complement storage node constant ...

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Номер записи: 8
11-02-2016 дата публикации

LOW POWER FLIP-FLOP ELEMENT WITH GATED CLOCK

Номер: US20160043706A1
Автор: Elkin Ilyas, Yang Ge, Yu Jiani, Zhang Xi
Принадлежит:

A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system. 1. A circuit element configured to perform a data capture operation , the circuit element comprising: receive a first data signal that has a first logic state,', 'invert the first logic state to generate a first inverted logic state, and', 'receive a first clock signal; and, 'a first latch element configured to invert the first clock signal to generate a first inverted clock signal, and', 'transmit the first inverted clock signal to the first latch element, wherein the first latch element, in response to the first inverted clock signal, inverts the first data signal to generate a first inverted data signal., 'a first logic element coupled to the first latch element and configured to2. The circuit element of wherein the first latch element comprises:a first inverter pair configured to receive the first data signal;a first switching element coupled between the first inverter pair and a supply voltage;a second switching element coupled between the first inverter pair and a grounding path;a second inverter pair coupled to the first inverter pair;a third switching element coupled between the second inverter pair and the supply voltage;a first inverter coupled between the first inverter pair and the second inverter pair; anda fourth switching element coupled between the second inverter pair and ...

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Номер записи: 9
01-05-2014 дата публикации

EFFICIENT SCAN LATCH SYSTEMS AND METHODS

Номер: US20140122949A1
Автор: Elkin Ilyas, Yang Ge
Принадлежит: NVIDIA CORPORATION

Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component. 1. A circuit comprising:a scan in propagation component operable to select between a scan in value and a recirculation value;a data propagation component operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component; anda control component for controlling an indication of a selection by the scan in propagation component and the data propagation component.2. The circuit of wherein the data propagation component is operable to pass input data without a delay associated with the scan in component.3. The circuit of wherein the scan in component and data propagation component are operable to introduce a delay to scan input.4. The circuit of wherein the scan in propagation component is configured in the recirculation path of data propagation component.5. The circuit of wherein the control component includes a gated clock.6. The circuit of wherein the scan in propagation component includes a multiplexer and the data propagation component includes a multiplexer.7. The circuit of wherein the scan in propagation component is included in a keeper.8. A method comprising:receiving a scan enable indication;selecting between a scan input and a ...

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Номер записи: 10
08-05-2014 дата публикации

LATCH CIRCUIT WITH A BRIDGING DEVICE

Номер: US20140125393A1
Автор: Alben Jonah M., DALLY William J., Elkin Ilyas
Принадлежит: NVIDIA CORPORATION

One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors. 1. A latch circuit , comprising:a storage sub-circuit including two cross-coupled inverters and configured to capture a level of the input signal when the clock signal transitions from a first level to a second level and hold the captured level of the input signal to generate the output signal that equals the captured level of the input signal while the clock signal is at the second level, wherein the inverters each have a supply terminal coupled to ground;a bridging transistor coupled between the supply terminals and configured to allow current to flow from the storage sub-circuit to the ground; anda propagation sub-circuit configured to receive the input signal and propagate the input signal to generate the output signal so that the input signal is passed through to the output signal while the clock signal is at the first level, wherein at least one pull-up transistor activates the propagation sub-circuit when the clock signal is at the first level and deactivates the propagation sub-circuit when the clock signal is at the second level.2. The latch circuit of claim 1 , wherein the propagation sub-circuit comprises:a first input transistor that receives the input signal and is coupled to a first pull-up transistor of the at least one pull-up transistor; anda second input transistor that receives an inverted input signal and is coupled to a second pull-up transistor of the at least one pull- ...

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Номер записи: 11
29-04-2021 дата публикации

Full adder cell with improved power efficiency

Номер: US20210124558A1
Автор: Ge Yang, Ilyas Elkin, Xi Zhang
Принадлежит: Nvidia Corp

An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.

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Номер записи: 12
29-04-2021 дата публикации

Full adder cell with improved power efficiency

Номер: US20210124559A1
Автор: Ge Yang, Ilyas Elkin, Xi Zhang
Принадлежит: Nvidia Corp

This disclosure relates to an adder circuit. The adder circuit comprises an operand input and a second operand input to an XNOR cell. The XNOR cell may be configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell may transform the output of the XNOR cell into a carry out signal.

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Номер записи: 13
17-08-2017 дата публикации

EFFICIENT SCAN LATCH SYSTEMS AND METHODS

Номер: US20170234927A1
Автор: Elkin Ilyas, Yang Ge
Принадлежит:

Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component. 1. A scan flip flop comprising:a master latch in which data input is passed without delay associated with scan input;a slave latch operable to hold a value forwarded from the master latch.2. The scan flip flop of wherein the master latch introduces a delay to a scan input value before passing it on the slave latch.3. The scan flip flop of wherein the slave latch is a circuit comprising:the master latch is operable to select between a scan in value and a recirculation value in the recirculation path;the slave latch is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component; anda control component for controlling an indication of a selection by the scan in propagation component and the data propagation component.4. The scan flip flop of wherein a data input is not subjected to parasitics associated with a selection between a scan input and a recirculation.5. The scan flip flop of wherein a scan input is subjected to parasitics associated with a selection between a recirculation.6. The scan flip flop of wherein the master latch is at least partially controlled with a gated clock signal.7. The scan flip flop of wherein the slave ...

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Номер записи: 14
17-09-2015 дата публикации

Low power master-slave flip-flop

Номер: US20150263708A1
Автор: Ge Yang, Ilyas Elkin
Принадлежит: Nvidia Corp

A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

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Номер записи: 15
01-02-2015 дата публикации

Low power master-slave flip-flop

Номер: TW201505372A
Автор: Ge Yang, Ilyas Elkin
Принадлежит: Nvidia Corp

本發明提供一種正反器電路，其可包括一主要閂鎖以及一從屬閂鎖。每個閂鎖皆可具有透通模式和儲存模式。在主要閂鎖處於透通模式下時，從屬閂鎖可在儲存模式下；且反之亦然。時脈信號可經由一對時脈閘控拉升電晶體和一對時脈閘控下拉電晶體(共計四個時脈閘控電晶體)控制每個閂鎖之模式。時脈閘控電晶體可由主要閂鎖和從屬閂鎖共享。相對於不共享，共享時需求的時脈閘控電晶體可較少。時脈閘控電晶體可具有寄生電容，並在經受變化的時脈信號時，由於寄生電容之充電及放電而消耗功率。具有較少的時脈閘控電晶體因而可減少正反器電路所消耗的功率。

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Номер записи: 16
07-07-2015 дата публикации

Latch circuit with a bridging device

Номер: US9077329B2
Автор: Ilyas Elkin, Jonah M. Alben, William J. Dally
Принадлежит: Nvidia Corp

One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors.

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Номер записи: 17
15-11-2016 дата публикации

Via resistance analysis systems and methods

Номер: US9496853B2
Автор: Ilyas Elkin, Puneet Gupta, Wojciech Jakub Poppe
Принадлежит: Nvidia Corp

Component characteristics analysis systems and methods are described. In one embodiment, a ring oscillator comprises: at least one inversion stage operable to cause a signal transition; a target component that has an increased comparative impact or influence on a signal transition propagation in the ring oscillator; and an output component for outputting an indication of the impact the target component has on the signal transition. The target component can include a plurality of vias from one metal layer to another metal layer, which can be configured in a cell. The vias can correspond to a via layer. In one exemplary implementation, the output is coupled to an analysis component. The analysis component can include correlation of the via resistance into a wafer variations and generate a wafer map and can include correlation of the via resistance into a wafer.

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Номер записи: 18
29-01-2015 дата публикации

Main sub-flip-flop with low power

Номер: DE102013021988A1
Автор: Ge Yang, Ilyas Elkin
Принадлежит: Nvidia Corp

Eine Flipflop-Schaltung kann einen Haupt-Signalspeicher und einen Neben-Signalspeicher aufweisen. Jeder Signalspeicher hat einen transparenten Modus und einen Speichermodus. Der Neben-Signalspeicher ist in dem Speichermodus, wenn der Haupt-Signalspeicher in dem transparenten Modus ist; und umgekehrt. Ein Taktsignal steuert den Modus des Signalspeichers über ein Paar getakteter Hochzieh-Transistoren und ein Paar getakteter Herabzieh-Transistoren, so dass insgesamt vier getakteten Transistoren vorhanden sind. Die getakteten Transistoren können einen gemeinsam von dem Haupt-Signalspeicher und dem Neben-Signalspeicher verwendet werden. Es sind weniger getaktete Transistoren erforderlich, wenn diese gemeinsam benutzt werden, im Bergleich dazu, wenn diese nicht gemeinsam benutzt werden. Getaktete Transistoren können eine parasitäre Kapazität aufweisen und Leistung verbrauchen, wenn sie mit einem variierenden Taktsignal beaufschlagt werden aufgrund der Ladung und der Entladung der parasitären Kapazität. Das Vorsehen von weniger getakteten Transistoren kann daher die von der Flipflop-Schaltung verbrauchte Leistung reduzieren. A flip-flop circuit may include a main latch and a sub-latch. Each latch has a transparent mode and a memory mode. The sub-latch is in the memory mode when the main latch is in the transparent mode; and vice versa. A clock signal controls the mode of the latch via a pair of clocked pull-up transistors and a pair of clocked pull-down transistors, for a total of four clocked transistors. The clocked transistors may be shared by the main latch and the slave latch. Less clocked transistors are needed when shared, in mountain mode when not shared. Clocked transistors may have a parasitic capacitance and consume power when supplied with a varying clock signal due to the charge and discharge of the parasitic capacitance. The provision of less clocked transistors can therefore reduce the power consumed by the flip-flop circuit.

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Номер записи: 19
30-06-2015 дата публикации

Low power master-slave flip-flop

Номер: US9071233B2
Автор: Ge Yang, Ilyas Elkin
Принадлежит: Nvidia Corp

A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

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Номер записи: 20
05-04-2022 дата публикации

Full adder cell with improved power efficiency

Номер: US11294631B2
Автор: Ge Yang, Ilyas Elkin, Xi Zhang
Принадлежит: Nvidia Corp

An adder circuit that includes an operand input and a second operand input to an XNOR cell. The XNOR cell is configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell transforms the output of the XNOR cell into a carry out signal.

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Номер записи: 21
23-02-2021 дата публикации

Low power flip-flop element with gated clock

Номер: US10931266B2
Автор: Ge Yang, Ilyas Elkin, Jiani Yu, Xi Zhang
Принадлежит: Nvidia Corp

A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system.

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Номер записи: 22
14-07-2016 дата публикации

Bestimmen von On-Chip-Spannung und -Temperatur

Номер: DE102012219971B4
Автор: Abhishek Singh, Ilyas Elkin, Wojciech Jakub Poppe
Принадлежит: Nvidia Corp

Verfahren, welches aufweist: Modellieren von zwei Arten von Sensoren, die Teil einer Halbleitervorrichtung sind; und Bestimmen einer Temperatur und Spannung basierend auf Daten, die von den zwei Sensoren empfangen werden, wobei ein erster Sensor der zwei Sensoren einen ersten Ringoszillator mit einer Leckstromkomponente aufweist, wobei ein zweiter Sensor der zwei Sensoren einen zweiten Ringoszillator ohne eine Leckstromkomponente aufweist, wobei das Bestimmen das Verwenden eines kalibrierten ersten Modells, das den ersten Sensor darstellt, und eines kalibrierten zweiten Modells, das den zweiten Sensor darstellt, aufweist, wobei das erste Modell eine Abhängigkeit der Daten des ersten Sensors von der Temperatur und von der Spannung beschreibt, wobei das zweite Modell eine Abhängigkeit der Daten des zweiten Sensors von der Temperatur und von der Spannung beschreibt, wobei das erste Modell und das zweite Modell kreuzgekoppelt sind, wobei das Bestimmen das iterative Lösen der kreuzgekoppelten ersten und zweiten Modelle umfasst.

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Номер записи: 23
04-05-2023 дата публикации

Data path circuit design using reinforcement learning

Номер: US20230139623A1
Автор: Bryan Catanzaro, Ilyas Elkin, Jonathan RAIMAN, Ming Y. Siu, Neel Kant, Rajarshi Roy, Robert Kirby, Saad Godil, Stuart Oberman
Принадлежит: Nvidia Corp

Apparatuses, systems, and techniques for designing a data path circuit such as a parallel prefix circuit with reinforcement learning are described. A method can include receiving a first design state of a data path circuit, inputting the first design state of the data path circuit into a machine learning model, and performing reinforcement learning using the machine learning model to output a final design state of the data path circuit, wherein the final design state of the data path circuit has decreased area, power consumption and/or delay as compared to conventionally designed data path circuits.

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Номер записи: 24
16-05-2024 дата публикации

Low-precision floating-point datapath in a computer processor

Номер: US20240160406A1
Автор: Brent Ralph Boswell, Brucek Kurdo Khailany, Charbel Sakr, Ilyas Elkin, Ming Y Siu, Rangharajan VENKATESAN, Reena Elangovan
Принадлежит: Nvidia Corp

Mechanisms to exploit the inherent resiliency of deep learning inference workloads to improve the energy efficiency of computer processors such as graphics processing units with these workloads. The mechanisms provide energy-accuracy tradeoffs in the computation of deep learning inference calculations via energy-efficient floating point data path micro-architectures with integer accumulation, and enhanced mechanisms for per-vector scaled quantization (VS-Quant) of floating-point arguments.

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Номер записи: 25
17-05-2023 дата публикации

データ経路回路を設計するための装置、システム、及び方法

Номер: JP2023068601A
Автор: Catanzaro Bryan, Elkin Ilyas, Godil Saad, Kant Neel, Kirby Robert, Oberman Stuart, RAIMAN Jonathan, Rajarshi Roy, Siu Michael, エルキン イルヤス, オーベルマン スチュアート, カービィ ロバート, カタンザーロ ブライアン, カント ニール, ゴディル サード, シュウ マイケル, ライマン ジョナサン, ラジョーシ ロイ
Принадлежит: Nvidia Corp

【課題】強化学習を用いて並列プレフィックス回路などのデータ経路回路を設計するための装置、システム、及び技法を提供する。【解決手段】方法は、データ経路回路の第１の設計状態を受信するステップと、データ経路回路の第１の設計状態を機械学習モデルに入力するステップと、データ経路回路の最終設計状態を出力するために機械学習モデルを使用して強化学習を実施するステップであって、データ経路回路の最終設計状態が、従来設計されたデータ経路回路と比較して減少された面積、電力消費及び／又は遅延を有する、ステップとを含むことができる。【選択図】図９Ａ

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Номер записи: 26
16-05-2024 дата публикации

Gleitkomma-datenpfad geringer genauigkeit in einem computerprozessor

Номер: DE102023130107A1
Автор: Brent Ralph Boswell, Brucek Kurdo Khailany, Charbel Sakr, Ilyas Elkin, Ming Y Siu, Rangharajan VENKATESAN, Reena Elangovan
Принадлежит: Nvidia Corp

Mechanismen, um die inhärente Elastizität von Deep-Learning-Inferenz-Arbeitslasten auszunutzen, um die Energieeffizienz von Computerprozessoren zu verbessern, wie beispielsweise Graphikverarbeitungseinheiten mit diesen Arbeitslasten. Die Mechanismen stellen Energie-Genauigkeits-Kompromisse bei der Berechnung von Deep-Learning-Inferenz-Berechnungen über Energieeffiziente Gleitkomma-Datenpfad-Mikroarchitekturen mit Ganzzahlakkumulation und verbesserten Mechanismen für Pro-Vektor skalierter Quantisierung (VS-Quant) von Gleitkomma-Argumenten bereit.

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Номер записи: 27
30-03-2023 дата публикации

Prioritätscodierer-basierte techniken zum berechnen des minimums oder des maximums von mehreren werten

Номер: DE102022124367A1
Автор: Brent Ralph Boswell, Ilyas Elkin, Ming Y. Siu, Stuart F. Oberman
Принадлежит: Nvidia Corp

In verschiedenen Ausführungsformen wird das Maximum oder Minimum einer Mehrzahl von Eingangswerten bestimmt. Für jeden eines Satzes von möglichen Werten wird ein entsprechendes Erfassungsergebnis eingestellt, um anzugeben, ob mindestens einer der Eingangswerte mit dem möglichen Wert übereinstimmt. Die Erfassungsergebnisse werden verwendet, um das Maximum oder Minimum der mehreren Eingangswerten zu ermitteln.

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Номер записи: 28
30-05-2017 дата публикации

Latch and flip-flop circuits with shared clock-enabled supply nodes

Номер: US09667230B1
Автор: Ilyas Elkin, Matthew Rudolph Fojtik, Yanqing Zhang
Принадлежит: Nvidia Corp

A method for operating a latch and a latch circuit are disclosed. The latch circuit comprises a storage sub-circuit, a propagation sub-circuit, and a shared clock-enabled transistor. The storage sub-circuit is configured to capture a level of an input signal when a clock signal transitions from first level to a second level and hold the captured level to generate an output signal while the clock signal is at the second level. The propagation sub-circuit is configured to enable a path through a blocking transistor to the shared clock-enabled supply node to propagate the captured level of the input signal to the storage sub-circuit. The shared clock-enabled transistor is configured to couple the shared clock-enabled supply node to a power supply while the clock signal is at the first level and decouple the shared clock-enabled supply node from the power supply while the clock signal is at the second level.

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Номер записи: 29
20-09-2016 дата публикации

Determining on-chip voltage and temperature

Номер: US09448125B2
Автор: Abhishek Singh, Ilyas Elkin, Wojciech Jakub Poppe
Принадлежит: Nvidia Corp

A method, in one embodiment, can include modeling and calibrating two types of sensors that are part of a semiconductor device. In addition, the method can include determining a temperature and voltage based on data received from the two sensors.

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Номер записи: 30
06-09-2016 дата публикации

Low power master-slave flip-flop

Номер: US09438213B2
Автор: Ge Yang, Ilyas Elkin
Принадлежит: Nvidia Corp

A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

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Номер записи: 31
06-09-2016 дата публикации

Efficient scan latch systems and methods

Номер: US09435861B2
Автор: Ge Yang, Ilyas Elkin
Принадлежит: Nvidia Corp

Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

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Номер записи: 32
23-08-2016 дата публикации

Coupling resistance and capacitance analysis systems and methods

Номер: US09425772B2
Автор: Ilyas Elkin, Puneet Gupta, Wojciech Jakub Poppe
Принадлежит: Nvidia Corp

The described systems and methods can facilitate examination of device parameters including analysis of relatively dominant characteristic impacts on delays. In one embodiment, at least some coupling components (e.g., metal layer wires, traces, lines, etc.) have a relatively dominant impact on delays and the delay is in part a function of both capacitance and resistance of the coupling component. In one embodiment, a system comprises a plurality of dominant characteristic oscillating rings, wherein each respective one of the plurality of dominant characteristic oscillating rings includes a respective dominant characteristic. Additional analysis can be performed correlating the dominant characteristic delay impact results with device fabrication and operation.

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Номер записи: 33