DELAY CIRCUIT

A delay circuit includes a memory addresses of which is designated by a counter incremented in response to each clock signal from an initial value set by an initial value setting circuit to an end value. A digital signal is written into an address as designated and read and converted into an analog signal to be outputted at an output terminal through a buffer amplifier. A delay time is determined by the writing timing and the reading timing of the digital signal. If the delay time is to be varied in the course of a delaying operation, a further initial value is set in the counter. A control signal for returning the counter to the initial value is generated by a first signal generating circuit when the end value is reached and a setting completion signal is generated by a second signal generating circuit when a setting of the further initial value is completed, and in response to both the signals, a muting signal is generated by a muting signal generating circuit, whereby the buffer amplifier mutes the output signal in response to the muting signal to prevent a noise due to random data from occurring at the output terminal.

Digital pulse generator having a programmable pulse width and a pulse repetition interval

A technique for accurately controlling both the pulse repetition interval and pulse width of a pulse signal generator which uses a crystal oscillator to maintain a very accurate time base. Two separate digital counters clock-in the clock pulses. When the desired number of clock pulses are registered by the first counter, a first digital comparator generates a start pulse which resets the first counter and triggers an output flip-flop. The change of state in the flip-flop enables the second counter to begin its count. When the desired number of clock pulses are registered by the second counter, a second digital comparator generates an end pulse which resets the second counter and triggers the flip-flop a second time. The second change of state of the flip-flop disables the second counter until the first comparator generates a new start pulse. The new start pulse toggles the flip-flop and the entire process is repeated continuously to generate at the output of the flip-flop a periodic pulse ...

Input/output circuit with programmable input sensing time

An input/output circuit of an integrated circuit with a programmable input sensing time. The output driver of the input/output circuit is open drain and is designed for use in a wire-OR configuration with other devices. The input/output circuit is coupled to a bonding pad and through the bonding pad to a device pin, and counts a programmable number of clock cycles between a negation of an output drive signal and when the state of the pin is sampled as an input. Since different applications use a wide range of values for external pullup resistors, the input/output circuit allows adjustment of the sample time to fit a particular application.

The driving circuit of the timing adjustment method and the driving circuit of the timing adjusting circuit

DELAY CIRCUIT

The present invention provides a technique for increasing resolution of a delay circuit while reducing the area thereof. The delay circuit comprises: multiple delay units connected in series in a loop shape, and sequentially delaying an input signal of the delay circuit; an input control part selecting the delay unit to receive the input signal of the delay circuit among the multiple delay units; and an output control part controlling to output an output signal of a predetermined delay unit to an output signal of the delay circuit, when the output signal of the predetermined delay unit among the multiple delay units is activated an N number of times (N is an integer greater than or equal to zero). COPYRIGHT KIPO 2017 (121) Pulse generator (122) Decoder (131) Counter (132) Code comparator (133) Delay line ...

PHASE ADJUSTMENT CIRCUIT

【課題】入力される複数の信号の位相を補償し、これら信号の位相の単調増加性を向上する位相調整回路の実現する。 【解決手段】位相調整回路は、第１から第ｎの二位相調整回路（１０）を備えている。各二位相調整回路（１０）は、入力された二つの信号の論理和を演算する第１の論理回路（１０５）、論理積を演算する第２の論理回路（１０７）、第２の論理回路（１０７）と同等の信号遅延量を有し、第１の論理回路（１０５）の出力信号を遅延させる第１の遅延回路（１０８）、及び第１の論理回路（１０５）と同等の信号遅延量を有し、第２の論理回路（１０７）の出力信号を遅延させる第２の遅延回路（１０６）を備えている。ここで、二つの二位相調整回路（１０）の出力信号は、次段の二位相調整回路（１０）の入力信号となる。 【選択図】図１

DELAY CIRCUIT

Delay circuit and delay synchronization loop device

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Delay circuit

A delay circuit includes a memory (4) addresses of which is designated by a counter (6) incremented in response to each clock signal from an initial value set by an initial value setting circuit (7) to an end value. A digital signal is written into an address as designated and read and converted into an analog signal to be outputted at an output terminal through a buffer amplifier (13). A delay time is determined by the writing timing and the reading timing of the digital signal. If the delay time is to be varied in the course of a delaying operation, a further initial value is set in the counter. A control signal for returning the counter to the initial value is generated by a first signal generating circuit (9) when the end value is reached and a setting completion signal is generated by a second signal generating circuit (11) when a setting of the further initial value is completed, and in response to both the signals, a muting signal is generated by a muting signal generating circuit ...

Verzögerungsschaltung.

Delay circuit and delay sysnchronization loop device

Deplay circuit and delay synchronization loop device

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

FREQUENCY SYNTHESIZER AND METHOD CONTROLLING FREQUENCY SYNTHESIZER

A voltage controlled oscillator (VCO) in a frequency synthesizer generates an output signal having a target frequency by being coarse tuned in accordance with a channel code derived through a binary tree search. Thereafter, the output signal of the VCO may be further tuned using a phase lock loop (PLL) circuit. Each stage of the binary tree search includes a comparison step that determines a channel code bit, and another step that confirms that the channel code converges to a final channel code within an established stage range value.

Verzögerungsschaltung und Verzögerungssynchronisationsschleifenvorrich- tung

Eine Verzögerungsschaltung hat eine erste Verzögerungsleitungsschaltung mit einer Anzahl von Stufen von Verzögerungseinheiten (101 bis 110), eine zweite Verzögerungsleitungsschaltung mit einer Anzahl von Stufen von Verzögerungseinheiten (111 bis 121), eine Anzahl von Transferschaltungen (131 bis 141), die bei, zugeordnet zu den jeweiligen Stufen der Verzögerungseinheiten (101 bis 110), der ersten Verzögerungsleitungsschaltung vorgesehen sind, wobei die Transferschaltungen den Transfer der Ausgänge der Verzögerungseinheiten der ersten Verzögerungsleitungsschaltung zu den zugehörigen Stufen der Verzögerungseinheiten der zweiten Verzögerungsleitungsschaltung steuern. Die Verzögerungseinheiten der jeweiligen Stufen der ersten Verzögerungsleitungsschaltung invertieren die eingegebenen Signale. Jede Verzögerungseinheit der Stufe der zweiten Verzögerungsleitungsschaltung hat eine Logikschaltung, die ein Ausgangssignal der Tranferschaltung, die der in Frage stehenden Verzögerungseinheit zugeordnet ...

Event tagging time delay

A time delay circuit for providing a delayed replica of a digital input signal including first and second counters for providing first and second count outputs offset relative to each other by a predetermined value indicative of a predetermined delay, and further including a first-in first-out (FIFO) memory for controllably storing selected values of the digital input signal together with corresponding first count output values. First comparison circuitry compares each digital input with the immediately prior digital input, and controls the FIFO memory to store (a) each digital input which is different from the immediately prior digital input, and (b) the first counter output value associated therewith. The FIFO memory circuit provides an output comprising (1) a digital output that corresponds to the earliest changed digital output which has not yet been utilized in the delayed replica of the digital input signal, and (2) a FIFO count output that corresponds to the first counter output ...

Verzögerungsschaltung und Verzögerungssynchronisations-Schleifenvorrichtung

Verzögerungsschaltung mit: einer ersten Verzögerungsleitungsschaltung mit einer Anzahl von Stufen von Verzögerungseinheiten (101 bis 110); einer zweiten Verzögerungsleitungsschaltung mit einer Anzahl von Stufen von Verzögerungseinheiten (111 bis 121); und einer Anzahl von Transferschaltungen (131 bis 141), die zugeordnet zu den jeweiligen Stufen der Verzögerungseinheiten der ersten Verzögerungsleitungsschaltung vorgesehen sind, wobei die Transferschaltungen jeweils Ausgänge der Stufen der Verzögerungseinheiten der ersten Verzögerungsleitungsschaltung empfangen, um den Transfer der Ausgänge der Verzögerungseinheiten zu den zugeordneten Stufen der Verzögerungseinheiten der zweiten Verzögerungsleitungsschaltung zu steuern; wobei – die Verzögerungseinheit jeder Stufe der ersten Verzögerungsleitungsschaltung ein Signal invertiert, das den Verzögerungseinheiten zugeführt worden ist, und das invertierte Signal ausgibt; – die Verzögerungseinheit jeder Stufe der zweiten Verzögerungsleitungsschaltung eine Logikschaltung aufweist, die ein Ausgangssignal der, der Verzögerungseinheit zugeordneten Transferschaltung und ein Ausgangssignal der vorhergehenden Stufe der zweiten Verzögerungsleitungsschaltung empfängt und das Ergebnis der logischen Operation der eingegebenen Signale an eine folgende Stufe... Delay circuit with: a first delay line circuit having a number of stages of delay units (101 to 110); a second delay line circuit having a number of stages of delay units (111 to 121); and a plurality of transfer circuits (131 to 141) provided associated with the respective stages of the delay units of the first delay line circuit, the transfer circuits receiving respective outputs of the stages of the delay units of the first delay line circuit to transfer the outputs of the delay units to the associated stages of the first delay line circuit To control delay units of the second delay line circuit; in which The delay unit of each stage of the first delay line circuit inverts a ...

Phase adjustment circuit

本发明提供一种相位调整电路，所述相位调整电路具有第1至第n二相位调整电路。各二相位调整电路包括：计算所输入的2个信号的逻辑和的第1逻辑电路；计算逻辑积的第2逻辑电路；第1延迟电路，具有与第2逻辑电路相等的信号延迟量，使第1逻辑电路的输出信号延迟；以及第2延迟电路，具有与第1逻辑电路相等的信号延迟量，使第2逻辑电路的输出信号延迟。这里，2个二相位调整电路的输出信号成为次级的二相位调整电路的输入信号。

DELAY CIRCUIT

PURPOSE: To prevent production of noise when a delay time is changed by generating a setting end signal caused when an initial value setting circuit completes the initial value setting and a muting signal in response to a control signal generated when a counter reaches a final value. CONSTITUTION: An input signal is A-D converted, stored tentatively in a memory 4 and a signal read from the memory 4 is DA-converted to obtain an output and the storage time in the memory 4 is a delay time. In this case, the address of the memory 4 is designated by a counter 6 to control the count of the counter 6, thereby varying the delay and the initial value is set to the counter 6 by using an initial value setting circuit 7. When the setting of the initial value is finished, a setting end signal is generated and when the count reaches the final value, the control signal is generated and a muting signal generating circuit 12 generates a muting signal in response to the setting end signal and the control ...

MEASUREMENT OF THE DURATION OF A PULSE

A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit. 1. A device , comprising:a first circuit providing a Vernier delay line circuit that comprises a first chain of identical stages defining first and second delay lines both coupled to a first input;a second circuit comprising a second chain of identical stages defining third and fourth delay lines, wherein the identical stages of the second chain are identical to the identical stages of the first chain; anda third circuit configured to selectively couple a selected one of an output of the third delay line, an output of the fourth delay line, or a first input of the third circuit to said first input of the first circuit,wherein said first circuit is configured to generate a digital signal representative of a duration of a pulse received by said first input of the first circuit.2. The device of claim 1 , wherein a number of identical stages in the second chain is smaller than a number of identical stages in the first chain.3. The device of claim 1 , wherein the digital signal is a binary word representative of the duration of the pulse.4. The device of claim 1 , further comprising:a fourth circuit connected to the output of the third delay line and configured to deliver to a second input of the third circuit a first pulse having a duration representative of a delay introduced by the third delay line; anda fifth circuit connected to the output of the fourth delay line and configured to deliver to a third input of the third circuit a second pulse having a duration representative of a delay introduced by the fourth delay line; andwherein the ...

Delay circuit and delay synchronization loop device

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

APPARATUS AND METHOD FOR CONTROLLING OUTPUT OF FREQUENCY SYNTHESIZER

The present invention relates to an apparatus and a method for controlling the output of a frequency synthesizer. The frequency synthesizer according to an embodiment of the present invention comprises: an oscillator for generating an oscillation frequency corresponding to a channel code; a frequency determiner for determining the channel code based on the oscillation frequency and a reference value corresponding to a target frequency and correcting the determined channel code when detecting an error; and a phase locker for correcting the phase of the oscillation frequency by detecting a phase difference between the oscillation frequency and the target frequency. The frequency synthesizer of the present invention can reduce frequency synthesis time by detecting and correcting the error. COPYRIGHT KIPO 2016 (410) Oscillator (430) Frequency determiner (433) Binary comparator (434) Channel code determiner (435) Corrector (450) Phase locker ...

Verzögerungsschaltung.

Deplay circuit and delay synchronization loop device

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Delay circuit with muting to prevent noise due to random data at output

A delay circuit includes a memory addresses of which is designated by a counter incremented in response to each clock signal from an initial value set by an initial value setting circuit to an end value. A digital signal is written into an address as designated and read and converted into an analog signal to be outputted at an output terminal through a buffer amplifier. A delay time is determined by the writing timing and the reading timing of the digital signal. If the delay time is to be varied in the course of a delaying operation, a further initial value is set in the counter. A control signal for returning the counter in the initial value is generated by a first signal generating circuit when the end value is reached and a setting completion signal is generated by a second signal generating circuit when a setting of the further initial value is completed, and in response to both the signals, a muting signal is generated by a muting signal generating circuit, whereby the buffer amplifier ...

Delay circuit

A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.

Phase adjustment circuit

A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.

Delay circuit and delay sysnchronization loop device

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Delay circuit and delay synchronization loop device

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

COHERENT SAMPLING TRUE RANDOM NUMBER GENERATION IN FD-SOI TECHNOLOGY

The present description concerns a random number generation circuit (2) of correlated sampling ring oscillator type comprising: two identical ring oscillators (RO1, R02) implemented in CMOS-on-FDSOI technology; a circuit (104) sampling and storing an output (O1) of one of the two oscillators (RO1) at a frequency of the other one of the two oscillators (R02) and delivering a corresponding binary signal (Beat); and a circuit (200) controlling back gates of PMOS and NMOS transistors of at least one delay element of at least one of the two oscillators (RO1, R02) based on a period difference between the two oscillators (RO1, R02).

Phase adjustment circuit

本发明提供一种相位调整电路，所述相位调整电路具有第1至第n二相位调整电路。各二相位调整电路包括：计算所输入的2个信号的逻辑和的第1逻辑电路；计算逻辑积的第2逻辑电路；第1延迟电路，具有与第2逻辑电路相等的信号延迟量，使第1逻辑电路的输出信号延迟；以及第2延迟电路，具有与第1逻辑电路相等的信号延迟量，使第2逻辑电路的输出信号延迟。这里，2个二相位调整电路的输出信号成为次级的二相位调整电路的输入信号。

Delay circuit and delay synchronization loop device

The invention provides a device to accomplish a DLL (delay lock loop; delay synchronization loop) with low jitter and small area. The device comprises a first delay circuit row having a plurality of sections of delay units 101-110, a second delay circuit row having a plurality of sections of delay units 111-121, and a plurality of transmission circuits 131-141 controlling the transmission of the output of each section of the first delay circuit row to the corresponding section of the second delay circuit row based on a control signal each inputted and provided corresponding to each section of the first delay circuit row. Each section of the delay units 101-110 of the first delay circuit row inverts and then outputs the input signal. Each section of the delay units of the second delay circuit row includes a logic circuit that inputs the output of the transmission circuit corresponding to the delay unit and the output of the front section of the delay unit and then outputs an output signal ...

Frequency synthesizer and method controlling frequency synthesizer

A voltage controlled oscillator (VCO) in a frequency synthesizer generates an output signal having a target frequency by being coarse tuned in accordance with a channel code derived through a binary tree search. Thereafter, the output signal of the VCO may be further tuned using a phase lock loop (PLL) circuit. Each stage of the binary tree search includes a comparison step that determines a channel code bit, and another step that confirms that the channel code converges to a final channel code within an established stage range value.

Phase adjustment circuit

本发明提供一种相位调整电路，所述相位调整电路具有第1至第n二相位调整电路。各二相位调整电路包括：计算所输入的2个信号的逻辑和的第1逻辑电路；计算逻辑积的第2逻辑电路；第1延迟电路，具有与第2逻辑电路相等的信号延迟量，使第1逻辑电路的输出信号延迟；以及第2延迟电路，具有与第1逻辑电路相等的信号延迟量，使第2逻辑电路的输出信号延迟。这里，2个二相位调整电路的输出信号成为次级的二相位调整电路的输入信号。

Delay circuit and delay synchronization loop device

Delay circuit

Delay circuit and delay sysnchronization loop device

Timing adjustment method for drive circuit and timing adjustment circuit for drive circuit

A timing adjustment method for a drive circuit, including: a rise detector for a rise start when a voltage-driven semiconductor element is turned off; a timing signal output unit outputting a speed change timing signal after a set delay time has elapsed from the rise start; and a conduction controller for a conduction control terminal of the semiconductor element using the timing signal, comprises: defining an estimated terminal voltage of the conduction control terminal when a rise completion time elapses; increasing a delay time by a predetermined unit time, and changing the drive signal to a turning off level again, when the conduction control terminal doesn't fall below the estimated terminal voltage after the drive signal is changed to a turning off level before the level is inverted; and determining a delay time, when the conduction control terminal falls below the estimated terminal voltage initially, as a set value.

Delay circuit

Delay circuit and delay synchronization loop device

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Electronic circuit and method for clock skew-calibration

The electronic circuit for multiphase clock skew calibration of at least one example embodiment provides a novel low power solution to detect clock skew errors with very high accuracy, of the order of a few femto seconds, and corrects clock skew errors and decreases and/or minimizes high frequency jitter in a data path of the electronic circuit.

Phase adjustment circuit

A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.

Programmable delay circuit

A monolithically integrated delay circuit is provided that comprises a gate coupled for receiving a digital input signal. The output of the gate is capacitively loaded whereby the output signal has a sloping downward transition. A line receiver has a first input coupled to said gate and a second input coupled for receiving an analog signal for comparing the analog signal with the output of the gate and for providing a digital output signal that is delayed with respect to the digital input signal.

Digital pulse generator having a programmable pulse width and a pulse repetition interval

A technique for accurately controlling both the pulse repetition interval and pulse width of a pulse signal generator which uses a crystal oscillator to maintain a very accurate time base. Two separate digital counters clock-in the clock pulses. When the desired number of clock pulses are registered by the first counter, a first digital comparator generates a start pulse which resets the first counter and triggers an output flip-flop. The change of state in the flip-flop enables the second counter to begin its count. When the desired number of clock pulses are registered by the second counter, a second digital comparator generates an end pulse which resets the second counter and triggers the flip-flop a second time. The second change of state of the flip-flop disables the second counter until the first comparator generates a new start pulse. The new start pulse toggles the flip-flop and the entire process is repeated continuously to generate at the output of the flip-flop a periodic pulse ...

DELAY CIRCUIT WITH MUTING TO PREVENT NOISE DUE TO RANDOM DATA AT OUTPUT

Phase adjustment circuit

A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.

Delay circuit and delay sysnchronization loop device

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

TIMING ADJUSTMENT METHOD FOR DRIVE CIRCUIT AND TIMING ADJUSTMENT CIRCUIT FOR DRIVE CIRCUIT

A timing adjustment method for a drive circuit, including: a rise detector for a rise start when a voltage-driven semiconductor element is turned off; a timing signal output unit outputting a speed change timing signal after a set delay time has elapsed from the rise start; and a conduction controller for a conduction control terminal of the semiconductor element using the timing signal, comprises: defining an estimated terminal voltage of the conduction control terminal when a rise completion time elapses; increasing a delay time by a predetermined unit time, and changing the drive signal to a turning off level again, when the conduction control terminal doesn't fall below the estimated terminal voltage after the drive signal is changed to a turning off level before the level is inverted; and determining a delay time, when the conduction control terminal falls below the estimated terminal voltage initially, as a set value.

DELAY CIRCUIT

A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.

DELAY CIRCUIT AND DELAY SYNCHRONIZATION LOOP DEVICE

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Timing adjustment method for drive circuit and timing adjustment circuit for drive circuit

DELAY CIRCUIT AND DELAY LOCK LOOP DEVICE

PROBLEM TO BE SOLVED: To provide a device for realizing low jitter and a small area of a DLL (delay lock loop). SOLUTION: This device is provided with: a first delay circuit series having a plurality of stages of delay units 101 to 110; a second delay circuit series having a plurality of stages of delay units 111 to 121; and a plurality of transfer circuits 131 to 141 provided corresponding to each step of the first delay circuit series and controlling the transfer of an output of each stage of the first delay circuit series to a corresponding stage of the second delay circuit series on the basis of each inputted control signal. The delay units 101 to 110 of each stage of the first delay circuit series inversely output an input signal. Delay units of each stage of the second delay circuit series includes a logic circuit for inputting an output of the transfer circuits corresponding to the delay units and an output of delay units of a preceding stage of the delay units and outputting an ...

Delay circuit and delay synchronization loop device

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Input/output circuit with programmable input sensing time

An input/output circuit of an integrated circuit with a programmable input sensing time. The output driver of the input/output circuit is open drain and is designed for use in a wire-OR configuration with other devices. The input/output circuit is coupled to a bonding pad and through the bonding pad to a device pin, and counts a programmable number of clock cycles between a negation of an output drive signal and when the state of the pin is sampled as an input. Since different applications use a wide range of values for external pullup resistors, the input/output circuit allows adjustment of the sample time to fit a particular application.

Programmable delay circuit

A monolithically integrated delay circuit is provided that comprises a gate coupled for receiving a digital input signal. The output of the gate is capacitively loaded whereby the output signal has a sloping downward transition. A line receiver has a first input coupled to said gate and a second input coupled for receiving an analog signal for comparing the analog signal with the output of the gate and for providing a digital output signal that is delayed with respect to the digital input signal.

Frequancy synthesizer and method for controlling frequency synthesizer

Delay circuit and delay synchronization loop device

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Delay circuit and delay synchronization loop device

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Measurement of the duration of a pulse

A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.

Deplay circuit and delay synchronization loop device

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Event tagging time delay

A time delay circuit for providing a delayed replica of a digital input signal including first and second counters for providing first and second count outputs offset relative to each other by a predetermined value indicative of a predetermined delay, and further including a first-in first-out (FIFO) memory for controllably storing selected values of the digital input signal together with corresponding first count output values. First comparison circuitry compares each digital input with the immediately prior digital input, and controls the FIFO memory to store (a) each digital input which is different from the immediately prior digital input, and (b) the first counter output value associated therewith. The FIFO memory circuit provides an output comprising (1) a digital output that corresponds to the earliest changed digital output which has not yet been utilized in the delayed replica of the digital input signal, and (2) a FIFO count output that corresponds to the first counter output ...

Phase adjustment circuit

A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.

Delay circuit and delay synchronization loop device

A delay circuit includes a delay line circuit string having a plurality of stages of delay units, a first switch on/off controlled based on an input control signal, a second switch connected to an output of the delay unit of the stage number corresponding to the control signal, and turned on at a time point when the transition edge of the rise or fall of the input signal supplied to the delay line circuit and propagated has traversed a number of stages corresponding to the selection control signal, with the second switch causing transition of a common node from one logic value to the other logic value; a signal generating circuit for generating a rising signal or a falling signal, and a control circuit for setting the common node to one logic value by the other transition, that is the falling or rising of the input signal. A series circuit composed of the second switch connected to outputs of the odd-numbered delay units and the first switch associated with the second switch may be connected ...

Phase adjustment circuit

A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.

Delay circuit and delay synchronization loop device

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Phase adjustment circuit

Apparatus and method for controlling output of frequency synthesizer

본 발명은 주파수 합성기(Frequency Synthesizer)의 출력을 제어하기 위한 장치 및 방법에 관한 것으로서, 본 발명의 실시 예에 따른 주파수 합성 장치는 채널 코드에 대응되는 발진 주파수를 발생시키는 발진기(oscillator)와, 상기 발진 주파수 및 목표 주파수에 대응되는 기준 값에 기초하여 상기 채널 코드를 결정하고, 오류 감지 시 상기 결정된 채널 코드를 보정하는 주파수 결정기와, 상기 발진 주파수 및 상기 목표 주파수 간의 위상차를 검출하여 상기 발진 주파수의 위상을 보정하는 위상 고정기를 포함하는 것을 특징으로 한다. The present invention relates to an apparatus and method for controlling an output of a frequency synthesizer, and the frequency synthesizer according to an embodiment of the present invention includes an oscillator that generates an oscillation frequency corresponding to a channel code, and the A frequency determiner that determines the channel code based on an oscillation frequency and a reference value corresponding to the target frequency and corrects the determined channel code when an error is detected, detects a phase difference between the oscillation frequency and the target frequency It characterized in that it comprises a phase locker for correcting the phase.

Delay circuit

지연 회로는, 루프 형태로 직렬로 연결되어 지연 회로의 입력 신호를 순차적으로 지연시키기 위한 다수의 지연 유닛들; 상기 다수의 지연 유닛들 중 상기 지연 회로의 입력 신호를 입력받을 지연 유닛을 선택하기 위한 입력 제어부; 및 상기 다수의 지연 유닛들 중 미리 결정된 지연 유닛의 출력 신호가 N번 활성화되면(N은 0이상의 정수), 상기 미리 결정된 지연 유닛의 출력 신호가 지연 회로의 출력 신호로 출력되도록 제어하는 출력 제어부를 포함할 수 있다.

Generation de nombres vraiment aleatoires a echantillonnage coherent en technologie fd-soi

La présente description concerne un circuit (2) de génération de nombres aléatoires de type à oscillateur en anneau à échantillonnage corrélé comprenant : deux oscillateurs en anneau (RO1, R02) identiques mis en œuvre en technologie CMOS sur FDSOI ; un circuit (104) échantillonnant et mémorisant une sortie (O1) d'un des deux oscillateurs (RO1) à une fréquence de l'autre des deux oscillateurs (RO2) et fournissant un signal binaire (Beat) correspondant ; et un circuit (200) commandant des grilles arrière de transistors PMOS et NMOS d'au moins un élément à retard d'au moins un des deux oscillateurs (RO1, RO2) à partir d'un écart de période entre les deux oscillateurs (RO1, RO2) .

Génération de nombres vraiment aléatoires à échantillonnage cohérent en technologie FD-SOI

Génération de nombres vraiment aléatoires à échantillonnage cohérent en technologie FD-SOI La présente description concerne un circuit (2) de génération de nombres aléatoires de type à oscillateur en anneau à échantillonnage corrélé comprenant : deux oscillateurs en anneau (RO1, R02) identiques mis en œuvre en technologie CMOS sur FDSOI ; un circuit (104) échantillonnant et mémorisant une sortie (O1) d'un des deux oscillateurs (RO1) à une fréquence de l'autre des deux oscillateurs (RO2) et fournissant un signal binaire (Beat) correspondant ; et un circuit (200) configuré commandant des grilles arrière de transistors PMOS et NMOS d'au moins un élément à retard d'au moins un des deux oscillateurs (RO1, RO2) à partir d'un écart de période entre les deux oscillateurs (RO1, RO2). Figure pour l'abrégé : Fig. 2

延迟电路、延迟同步回路装置、半导体存储装置和信号发生装置

本发明提供一种延迟电路，实现DLL的低波动、小面积化。具有：具有多级延迟单元(101～110)的第1延迟电路串；具有多级延迟单元(111～121)的第2延迟电路串；以及，与第1延迟电路串的各级对应而设，根据分别输入的控制信号，对第1延迟单元的输出向第2延迟电路串对应的级的传送进行控制的多个传送电路(131～141)。内含逻辑回路是：第1延迟电路串的各级的延迟单元(101～110)将输入信号反相输出，第2延迟电路串的各级的延迟单元输入与该延迟单元对应的上述传送电路的输出和该延迟单元的前级延迟单元的输出，把输出信号输出到后级。通过对输入的信号的上升沿和下降沿的传输通路独立地进行选择，使占空比可变。

用于时钟偏斜校准的电子电路和方法

公开了用于时钟偏斜校准的电子电路和方法。所述电子电路包括滤波电路，被配置为对由多相时钟驱动的串行器电路系统输出的数据进行滤波，并且生成表示输入到串行器电路系统的多个多相时钟信号之间的偏斜的差分电压，其中，差分电压的极性表示所述多个多相时钟信号之间的偏斜的极性；离散时间积分器电路系统，被配置为对生成的差分电压进行放大；比较器电路系统，被配置为基于差分电压和期望值来确定差分电压的差异度；以及时钟偏斜校正器电路系统，被配置为：基于确定的差异度来修改所述多个多相时钟信号的上升沿和/或下降沿位置，触发串行器电路系统根据修改后的多个多相时钟信号来输出数据，以及减小所述多个多相时钟信号之间的偏斜。