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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 9604. Отображено 200.
10-01-1974 дата публикации

BELEUCHTUNGSVORRICHTUNG MIT UEBER GROSSE BEREICHE AENDERBARER HELLIGKEIT

Номер: DE0002333287A1
Принадлежит:

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08-08-1991 дата публикации

Clock pulse signal generating circuit - has input release circuit in front of flip=flop for control signal flank-dependent operation

Номер: DE0004003501A1
Принадлежит:

The circuit has a flip-flop (6,9) whose clock pulse signal delivering output (10) is coupled to an input of the flip-flop via a capacitor (11), while its output (7) delivering an inverting clock pulse signal is coupled to that input via a resistor (8). The clock pulse signal state changes, when the input signal of the flip-flop has exceeded a preset value. In front of the flip-flop input is fitted a release circuit (1), which releases the flip-flop input when the flank of a supply control clock pulse signal appears, whose frequency exceeds that of the clock pulse signal. Pref. the flip-flop input is released when the flank of the control signal is of rising nature. ADVANTAGE - Generating a clock pulse signal whose frequency corresponds to a frequency part of an existing clock pulse signal.

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13-02-1969 дата публикации

Impulsgenerator mit veraenderbarer Impulsfolgefrequenz

Номер: DE0001289102B
Принадлежит: SIEMENS AG

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21-03-1974 дата публикации

OSZILLATOR FUER HOHE FREQUENZEN MIT INTEGRIERTEN LOGIKBAUSTEINEN

Номер: DE0002245476A1
Принадлежит:

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22-07-1976 дата публикации

OSZILLATOR ZUR ERZEUGUNG EINER RECHTECKFOERMIGEN IMPULSFOLGE, DEREN IMPULSFOLGEFREQUENZ STEUERBAR IST

Номер: DE0002444250B2
Автор:
Принадлежит:

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19-05-1976 дата публикации

GENERATOR FOR CONTROLLING A TRANSDUCER

Номер: GB0001435874A
Автор:
Принадлежит:

... 1435874 Amplitude modulators COMMISSARIAT A L'ENERGIE ATOMIQUE 11 June 1974 [13 June 1973] 25785/74 Heading H3R A generator for controlling a transducer by bursts of sinusoidal oscillations comprises a generator as shown in Fig. 2 for producing wave trains formed by a whole number of half cycles of periodic signals and a low pass filter (not shown) which passes the fundamental frequency of the periodic signals. The generator includes two monostable circuits connected in closed loop to form an astable circuit which is on-off keyed by a pulse 25 to form two displaced pulse trains S 1 , S 2 synchronized in phase which are added in a circuit including inverters 26, 27, transistor 28 and resistors R 1 to derive a composite pulse train at 0 having twice the amplitude. This composite signal is applied to a low-pass filter (Figs. 4, 6, not shown) to derive a sine wave signal suitable for driving a transducer. The free running frequency of the astable circuit can be varied by adjusting the time ...

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16-06-1993 дата публикации

RING OSCILLATOR

Номер: GB0009308944D0
Автор:
Принадлежит:

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18-06-1980 дата публикации

An audible tone generator

Номер: GB0002035653A
Автор: Learn, Richard Larry
Принадлежит:

A circuit for providing a plurality of distinguishable audible signals from an audible tone generator includes at least two gates wherein the output of one of the gates determines the type of audible signal produced by the audible tone generator in response thereto. The circuit further includes a single control terminal for controlling the logical state the output of the one gate and for controlling the type of audible signal produced by the audible tone generator. The absence of an electrical potential at the control terminal when power is applied to the circuit results in a latching of the output of the one gate and the production of a continuous audible signal by the audible tone generator. The presence of an electrical potential at the control terminal when power is applied to the circuit results in a periodic changing of the output of the one gate and the production of an interrupted audible signal by the audible tone generator.

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30-08-2000 дата публикации

Digital phase control circuit for controlling phase error

Номер: GB0002347287A
Принадлежит:

A digital phase control circuit 20 for controlling a phase error between a phase of an output signal of an oscillating circuit and a phase of a reference signal. A pulse cycle of the output signal is changed in response to a control input value S. The digital phase control circuit comprises a phase comparator 21 for judging an advance/delay of a phase of the output signal, and a counter circuit 22 for counting up or down according to a judgement of the phase comparator circuit 21 and for changing a count, when that judgement has been reversed, to approximately a mean value of the counts made during the successive same judgements, this count being used as the control input value S.

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03-05-2000 дата публикации

An oscillator circuit

Номер: GB0000005725D0
Автор:
Принадлежит:

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08-09-1971 дата публикации

RC-PULSE OSCILLATOR

Номер: GB0001245552A
Автор:
Принадлежит:

... 1,245,552. Integrated circuit oscillators. ITT INDUSTRIES Inc. 21 April, 1970 [25 April, 1969], No. 18975/70. Heading H3T. A monolithic integrated oscillator circuit comprises a capacitor C which is charged through a circuit LS and discharged through a circuit ES when a switch S is closed, the switch being controlled by a threshold circuit SWS to close at an upper and open at a lower threshold voltage on the capacitor, the output being taken either from point A as a delta waveform or from the circuit SWS as a rectangular one. The output is amplified by an unspecified circuit AS. The charge and discharge circuits comprise transistors of complementary type and constitute constant current circuits which are adjustable by inputs E LS , E ES to vary the duty factor and frequency of the output. It may be arranged to vary E LS and E ES together in a manner to vary the frequency only. The threshold circuit includes a potentiometer, across one half of which is connected a further resistor controlled ...

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15-09-2004 дата публикации

ELECTRONIC SWITCHING CONFIGURATION

Номер: AT0000274765T
Автор: WOOD JOHN, WOOD, JOHN
Принадлежит:

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27-08-1985 дата публикации

AUTOMOTIVE PULSE GENERATOR

Номер: AU0000545611A3
Автор: BARRY GORDGE STEVEN
Принадлежит:

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24-07-2000 дата публикации

Dual clock signal generating circuit

Номер: AU0002482600A
Принадлежит:

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30-12-1975 дата публикации

MULTIVIBRATOR CIRCUIT

Номер: CA980881A
Автор:
Принадлежит:

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15-06-1976 дата публикации

VARIABLE INTENSITY ILLUMINATOR

Номер: CA0000991258A1
Автор: WESNER CHARLES R
Принадлежит:

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27-07-2000 дата публикации

ELECTRONIC CIRCUITRY

Номер: CA0002355930A1
Автор: WOOD, JOHN
Принадлежит:

Timing signal generation and distribution are combined in operation of a signal path (15) exhibiting endless electromagnetic continuity affording signal phase inversion and having associated regenerative active means (21). Two or more phases of substantially square-wave bipolar signals arise directly in travelling wave transmission-line embodiments compatible with semiconductor fabrication including CMOS. Coordination by attainable frequency synchronism with phase coherence for several such oscillating signal paths has intra-IC inter-IC and printed circuit board impact, as does two-way simultaneous data transfer.

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30-12-1975 дата публикации

MULTIVIBRATOR CIRCUIT

Номер: CA0000980881A1
Принадлежит:

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15-01-1973 дата публикации

Taktversorgungsanlage

Номер: CH0000532870A
Принадлежит: SIEMENS AG, SIEMENS AKTIENGESELLSCHAFT

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15-02-1969 дата публикации

Impulsgenerator

Номер: CH0000468749A
Принадлежит: SIEMENS AG, SIEMENS AKTIENGESELLSCHAFT

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28-02-1978 дата публикации

Номер: CH0000595721A5
Принадлежит: SIEMENS AG ALBIS, SIEMENS-ALBIS AG

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21-09-2005 дата публикации

Switching electronic circuit for random number generation

Номер: CN0001672127A
Автор: LASZLO HARS, HARS LASZLO
Принадлежит:

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13-07-1973 дата публикации

MULTIPLE PHASE CLOCK GENERATOR CIRCUIT WITH CONTROL CIRCUIT

Номер: FR0002138715B1
Автор:
Принадлежит:

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20-10-1978 дата публикации

OSCILLATEUR DELIVRANT DES IMPULSIONS RECTANGULAIRES

Номер: FR0002385261A
Автор:
Принадлежит:

Oscillateur délivrant des impulsions rectangulaires à fréquence de sortie variable, à l'aide d'une bascule de Schmitt commandée par un élément RC. Une source de courant constant délivre le courant IK nécessaires à la charge du condensateur CT . Un circuit image de courant T2 assure en outre l'égalité des courants de charge et de décharge du condensateur.

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08-04-1983 дата публикации

GENERATOR Of BASIC IMPULSES OF TIME

Номер: FR0002281007B1
Автор:
Принадлежит:

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27-02-1976 дата публикации

GENERATOR Of BASIC IMPULSES OF TIME

Номер: FR0002281007A1
Принадлежит:

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23-03-1973 дата публикации

Номер: FR0002148775A5
Автор:
Принадлежит:

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05-04-1974 дата публикации

PULSE GENERATOR CIRCUITS

Номер: FR0002199230A1
Автор:
Принадлежит:

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03-02-2009 дата публикации

Oscillator capable of operating at multi-frequency

Номер: KR0100881180B1
Автор:
Принадлежит:

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01-02-2009 дата публикации

Measurement apparatus for improving performance of standard cell library

Номер: TW0200905228A
Принадлежит:

Disclosed herein is a measurement apparatus for improving performances of standard cells in a standard cell library when verifying performance of the standard cell library through a ring oscillator among various test element groups (TEGs). A built-in circuit is used to measure and verify performance of the standard cell library through a TEG. Therefore, it is possible to effectively improve performances of the standard cells in the standard cell library. Particularly, it is possible to not only remove human errors or internal errors of equipment, but also perform the measurement more readily, rapidly and accurately. Further, it is possible to curtail the use of high-performance equipment or manpower and time required in a measurement process.

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08-07-2004 дата публикации

Multiphase resonant pulse generators

Номер: US20040130362A1
Автор: William Athas
Принадлежит:

A multiphase resonant pulse generator (74 ) has N groups of N-1 switches (44,46,48) which, when activated, form N paths from a power supply (Vdc) to ground or a reference voltage. Here N is a positive integer greater than 2. Each of the paths includes an inductance (38,40,42) and N-1 switches. The signal outputs (X1,X2,X3) from each of the N paths are cross coupled to switches beloning to the other N-1 paths to active or deactivate the groups of switches.

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25-03-1997 дата публикации

Phase locked loop having voltage controlled oscillator utilizing combinational logic

Номер: US0005614868A1
Автор: Nielson; Edward T.
Принадлежит: VLSI Technology, Inc.

A phase locked loop including a VCO having a multi-stage oscillator portion and a combinational logic portion. The multi-stage oscillator portion is configured to oscillate at a VCO clock frequency during a steady state condition under the control of a VCO control signal, and is further operative to develop a plurality of clock phases at the VCO clock frequency, with one of such clock phases used in the determination of the VCO control signal. The combinational logic portion is responsive to at least some of the plurality of clock phases and is operative to combine clock phases to create an output clock having an output clock frequency that is a multiple of the input clock frequency. A method for multiplying an input clock frequency includes the steps of applying an input clock to a delay chain, developing a plurality of phase-shifted clocks by tapping into the delay chain, and combining the plurality of phase-shifted clocks in combinational logic to produce an output clock having a frequency ...

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13-10-1998 дата публикации

Voltage-controlled oscillator

Номер: US0005821823A1
Автор: Bereza; William
Принадлежит: Northern Telecom Limited

A voltage-controlled oscillator (VCO) includes a plurality of differential amplifiers which are ring-connected. Each amplifier includes two FETs, the sources of which are coupled. The coupled sources of each amplifier are connected to series-connected FETs which is part of a current mirror circuit. The series-connected FETs decrease transconductance of (i.e., increase impedance against) fluctuations in a power supply voltage, so that fluctuations in current flowing in the amplifiers are lessened. Thus, power-supply rejection ratio of the VCO increases and fluctuations in the VCO frequency are lessened.

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19-09-1978 дата публикации

MOS IC Oscillation circuit

Номер: US0004115748A1
Принадлежит: Tokyo Shibaura Electric Co., Ltd.

A MOS IC oscillation circuit comprising a circuit including a MOS FET and a resistor connected in series between a power source and ground, a capacitor one end of which is connected to the junction between both said components and the other end is connected to said power source or the ground, and a Schmitt trigger circuit receiving an input signal from the junction and produces an output signal which controls "on-off" operation of the MOS FET.

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03-06-1997 дата публикации

Low voltage high frequency ring oscillator for controling phase-shifted outputs

Номер: US0005635877A1
Принадлежит: SGS-Thomson Microelectronics Ltd.

A oscillator having two synchronized oscillator rings is described. Synchronization is accomplished by circuitry connected between the outputs of two aligned stages in coupled oscillator rings, the circuitry being operable to maintain outputs of the stages 180° apart in phase.

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29-10-1996 дата публикации

Micropower RC oscillator having hysteresis produced by switching current sources to a transistor

Номер: US0005570067A
Автор:
Принадлежит:

An RC oscillator operates at very low current levels and manifests very brief internal component delays. The RC oscillator does not employ a conventional comparator and a conventional hysteresis circuit for changing reference voltages on the comparator. Instead, the RC oscillator includes a plurality of amplifiers. Hysteresis is achieved by changing the threshold voltage of one of the amplifiers. The threshold voltage is changed by switching different current values through the transistor so that the current for activating the amplifier is different from the current for deactivating the amplifier.

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03-11-2009 дата публикации

Resistor-capacitor oscillation circuit capable of adjusting oscillation frequency and method of the same

Номер: US0007612624B2

An RC oscillation circuit and method capable of adjusting an oscillation frequency includes: an RC oscillator including a variable resistor and a variable capacitor, the RC oscillator generating an RC oscillating signal having a frequency determined by a resistance of the variable resistor and a capacitance of the variable capacitor; a counter counting a clock number of a reference oscillating signal corresponding to one period of the RC oscillating signal to generate a first count value, the reference oscillating signal having a preset frequency; and a frequency controller controlling a frequency of the RC oscillating signal by determining the resistance of the variable resistor and the capacitance of the variable capacitor such that a difference between the first count value and a preset second count value is smaller than a preset first critical value.

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26-06-2014 дата публикации

OSCILLATION METHOD AND OSCILLATION CIRCUIT

Номер: US20140176247A1
Принадлежит:

The oscillation method uses an oscillation circuit in which a plurality of MOSFETs are annularly connected. The method comprises the steps of: forming GND of the circuit, which is separated from GND of a driving electric source of the MOSFETs, in a part of a first connection line which connects the MOSFET with the adjacent MOSFET; connecting a probe with a second connection line which connects another MOSFET with the adjacent MOSFET, an odd number of the MOSFETs being connected between the GND and the second connection line; and generating an oscillation waveform between the probe and the GND.

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25-07-2002 дата публикации

High speed voltage-controlled ring oscillator

Номер: US2002097098A1
Автор:
Принадлежит:

A high speed ring voltage-controlled oscillator (VCO) system is provided. The ring VCO system includes a plurality of interpolation stages coupled in a "look-ahead" configuration. Each interpolation stage receives two signal inputs and outputs a single differential voltage representative of a time delay interpolation between the two input signals. In accordance with the invention, each interpolation stage receives a first signal input from the immediately previous stage and a second signal input from the output of a different stage. In this manner, the delay stages in the ring VCO can generate a variable delay by interpolating between inputs with small relative delays without adding additional delay to the total loop delay.

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11-05-2005 дата публикации

Voltage controlled oscillator circuit

Номер: EP0001530293A2
Принадлежит:

A voltage controller oscillator circuit includes first and second chopper comparators (120,121), a capacitor (122), first and second current sources (123,124) and a converter circuit (125) for making the current sources (123,124) to generate a current (I) proportionate to an input voltage (Vin). The voltage controlled oscillator circuit further includes first and second switches (126,127) and an inverter (128) for controlling on/off of the current sources (123,124). A logic circuit (129) latches the output signals of the comparators (120,121), outputs the output voltage (Vout) that serves as an oscillation signal of the voltage controlled oscillator and generates clock signals (φ1,φ2) for switching operation of the chopper comparators (120,121).

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17-04-2008 дата публикации

OSCILLATION CIRCUIT

Номер: JP2008092489A
Автор: NOGUCHI MINEO
Принадлежит:

PROBLEM TO BE SOLVED: To provide an oscillation circuit with small fluctuation in an oscillation frequency caused by a source voltage and an ambient temperature. SOLUTION: An output signal ZA from an NAND 48a is supplied to a first input of an NAND 48b as well as to a second input of the NAND 48b through a delay circuit. An output signal ZB of the NAND 48b is supplied to a first input of the NAND 48a as well as a second input of the NAND 48a through a delay circuit. The delay circuit is provided with: a charging and discharging circuit comprising an NMOS 42 of which conductivity is controlled by the temperature-dependent voltage VN outputted from a temperature-dependent current source 30 and a capacitor 44; and an NMOS 45 which is on/off controlled by a voltage of the capacitor 44. By setting a temperature characteristic of the voltage VN to be countered by that of a threshold voltage of the NMOS 45, the fluctuation in the oscillation frequency by an unstable multi-vibrator is restrained ...

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10-02-1982 дата публикации

FREE-RUNNING MULTIVIBRATOR

Номер: JP0057025718A
Автор: AZEGAMI TADASHI
Принадлежит:

PURPOSE: To ensure an output of the stable frequency of oscillation, by longitudinally connecting an inverter between an input and an output and then installing a series electrostatic capacitor between the 1st and 2nd inverters plus a constant value current limiting circuit between the input and the output of the 2nd inverter. CONSTITUTION: A capacitor C1 is put into the area between the output of an inverter (INV) G1 having a longitudinal connection secured between the input and the output and the input of an INVG2. Furthermore a constant value current limiting circuit CC is connected between the input and the output of the INVG2. The frequency of oscillation of a free-running multivibrator having such constitution is decided by only the capacitor C1, the power supply voltage E and the current of the circuit CC. Accordingly the C1 is selected to decide the frequency of oscillation, by stabilizing the voltage E. Thus the effect to the frequency of oscillation due to the fluctuation of distribution ...

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09-08-1996 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT

Номер: JP0008204450A
Автор: IMURA SATORU
Принадлежит:

PURPOSE: To reduce power consumption at the time of normal operations and to reduce higher harmonic noise radiation in an oscillation circuit incorporated in a semiconductor integrated circuit. CONSTITUTION: This circuit is provided with a constant voltage generation circuit 13 provided with a switching means 132 for switching an operating power supply voltage supplied to the oscillation circuit 11 to a lower voltage by activation control signals for which a period from the oscillation activation to the oscillation stabilization of the oscillation circuit 11 is provided in a pulse width and a level conversion circuit 14 for level converting the output amplitude of the oscillation circuit 11 fluctuating corresponding to the operating power supply voltage supplied by the constant voltage generation circuit 13 into the logical amplitude of a logic circuit part 12. COPYRIGHT: (C)1996,JPO ...

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10-04-2013 дата публикации

СХЕМА ПРЕОБРАЗОВАНИЯ НАПРЯЖЕНИЕ-ЧАСТОТА И УСТРОЙСТВО ИЗМЕРЕНИЯ КРОВЯНОГО ДАВЛЕНИЯ, ОБОРУДОВАННОЕ УПОМЯНУТОЙ СХЕМОЙ

Номер: RU2011139070A
Принадлежит:

... 1. Схема преобразования напряжение-частота, содержащая:схему (34) резистивно-емкостного (RC) генератора, содержащую емкостную составляющую и резистивную составляющую; при этомсхема RC-генератора содержитввод, на который подается входное напряжение,первый резистивный элемент (13, 16), подсоединенный между вводом и первой внутренней точкой (NA) разветвления,первый конденсатор (14), содержащий один электрод, соединенный с первой внутренней точкой разветвления, и другой электрод, соединенный со второй внутренней точкой (NC) разветвления,второй резистивный элемент (12), содержащий один проводящий вывод, соединенный с первой внутренней точкой разветвления параллельно первому конденсатору,первую логическую схему (11A, 11B), соединенную с другим проводящим выводом второго резистивного элемента и подсоединенную между первой внутренней точкой разветвления и второй внутренней точкой разветвления через второй резистивный элемент,вторую логическую схему (11C), соединенную со второй внутренней точкой ...

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28-05-2020 дата публикации

Verfahren zum Abschalten einer Kommunikation und korrespondierende Kommunikationsanordnung

Номер: DE102018220398A1
Принадлежит:

Die Erfindung betrifft ein Verfahren zum Abschalten einer Kommunikation zwischen mindestens zwei Busteilnehmern (3, 3A, 3B), welche über einen Datenbus (DB) miteinander verbunden sind und während der Kommunikation jeweils zusätzlich zu einem Datensignal (TxData, RxData) ein Sendetaktsignal (TxCLK, RxCLK) übertragen, wobei mindestens einer der Busteilnehmer (3A) sein Sendetaktsignal (TxCLK) und sein Datensignal (TxData) basierend auf einem Referenztaktsignal (CLK_Ref) erzeugt, sowie eine korrespondierende Kommunikationsanordnung (1). Hierbei wird im Fehlerfall das Referenztaktsignal (CLK_Ref) abgeschaltet, so dass der mindestens eine betroffene Busteilnehmer (3A) kein Sendetaktsignal (TxCLK) und kein Datensignal (TxData) mehr überträgt und die fehlerhafte Kommunikation abgeschaltet ist.

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18-06-1970 дата публикации

Schaltung zum Erzeugen von zeitlich genau bemessenen Signalen

Номер: DE0001960791A1
Принадлежит:

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20-03-1975 дата публикации

Electronic clock pulse generator - generates at least two clock pulse trains of same frequency but phase shifted

Номер: DE0002345837A1
Принадлежит:

The generator has a low impedance output and a low power consumption. A multivibrator delivering the required frequency and operated at a much lower voltage is connected through a dynamic resistor network with bases of two transistors of opposite conduction types forming a bipolar push-pull stage; supply voltage of this stage corresponds to the required output voltage. Transistor collector resistors are connected to an output delivering the clock pulses, and through a delay line to the control input of an externally controlled, but similarly assembled multivibrator, so that its push-pull stage delivers a further clock pulse train of the same frequency.

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16-06-1977 дата публикации

SCHALTUNGSANORDNUNG FUER EINEN AKUSTISCHEN SIGNALGEBER

Номер: DE0002554219A1
Принадлежит:

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16-04-1992 дата публикации

Номер: DE0004003501C2

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23-04-2020 дата публикации

MULTIPLIZIERENDE VERZÖGERUNGSREGELSCHLEIFE (MDLL) UND VERFAHREN ZUR MITTELWERTBILDUNG VON RINGOSZILLATORSIGNALEN ZUR JITTERKOMPENSATION

Номер: DE112017007834T5
Принадлежит: INTEL CORP, INTEL CORPORATION

Hierin werden generell Aspekte der vorliegenden Offenbarung einer multiplizierenden Verzögerungsschleifenschaltung (MDLL) und von Kommunikationsvorrichtungen beschrieben. Die MDLL-Schaltung kann einen Multiplexer und einen Ringoszillator umfassen. Der Ringoszillator kann eine Kaskade von Verzögerungselementen umfassen. Der Multiplexer kann ein Referenztaktsignal empfangen und kann ein Ringoszillatorausgangssignal aus einem letzten Verzögerungselement der Kaskade von Verzögerungselementen empfangen. Der Multiplexer kann, als ein Ringoszillatoreingangssignal, entweder das Referenztaktsignal oder das Ringoszillatorausgangssignal auswählen. Der Ringoszillator kann eine Jitterschätzung mindestens teilweise basierend auf einem Vergleich zwischen Ausgangssignalen von zwei bestimmten Verzögerungselementen der Kaskade bestimmen. Der Ringoszillator kann Verzögerungsreaktionen der Verzögerungselemente der Kaskade mindestens teilweise basierend auf der Jitterschätzung kompensieren.

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01-06-1977 дата публикации

PULSE GENERATOR CIRCUITS

Номер: GB0001475724A
Автор:
Принадлежит:

... 1475724 FET pulse generators HITACHI Ltd 22 May 1974 [4 June 1973] 22976/74 Heading H3T A pulse generator circuit includes first, second and third inverters I1, I2, I3, Fig. 1, each comprising series connected FET's of the same conductivity type which are connected in cascade to form a closed loop, an output terminal T0 connected to the third inverter, a first capacitor C1 arranged between the input to the second inverter 12 and another part of the circuit and a second capacitor C2 arranged between the input of the third inverter I3 and a reference potential. In the pulse generator shown in Fig. 1 P-channel MOSFET's T1-T6 are used and assuming T2 and T4 are off and T6 is on, capacitor C1 charges until the threshold level of T4 is reached and then T4 conducts. At this time the charge on capacitor C2 starts to discharge through T4 and when the output voltage of T4 at b falls below the threshold level of T6, T6 turns-off. As the output of T6 does not include a large capacitance as in the case ...

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03-05-2000 дата публикации

Clock pulse generator for LCD

Номер: GB0002343309A
Принадлежит:

A clock pulse generator comprises N stages which provide pulse outputs successively on lines Nn,Pp. The clock input CK to each stage 1,2 is gated by a transmission gate M3,M4, M9,M10 under control of the output A,D of the preceding stage to pass a clock pulse to the output Nn,Pp of the stage. When the transmission gate of a stage is enabled by the previous stage and the clock signal is then asserted, the control circuit M5,M6,M11,M12 of the stage is asserted to activate the following stage. The control circuit is subsequently disasserted by the control circuit of the next-but-one stage. Gating of the clock reduces loading of the clock line. A two-phase clock may be used. Overlapping and non-overlapping outputs may be obtained.

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19-09-2001 дата публикации

Electronic circuitry

Номер: GB0002349524B
Автор: WOOD JOHN, JOHN * WOOD
Принадлежит: WOOD JOHN, JOHN * WOOD

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30-03-1988 дата публикации

DATA CLOCK OSCILLATOR HAVING ACCURATE DUTY CYCLE

Номер: GB0008804963D0
Автор:
Принадлежит:

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15-03-1984 дата публикации

STEUERIMPULSGENERATOR ZUR ANSTEUERUNG VON SCHALTTRANSISTOREN

Номер: ATA553281A
Автор:
Принадлежит:

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12-11-1984 дата публикации

STEUERIMPULSGENERATOR FOR THE CONTROL OF SCHALTTRANSISTOREN

Номер: AT0000376333B
Принадлежит:

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15-03-1984 дата публикации

STEUERIMPULSGENERATOR FOR THE CONTROL OF SCHALTTRANSISTOREN

Номер: AT0000553281A
Принадлежит:

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06-08-1987 дата публикации

ASTABLE MULTIVIBRATORS

Номер: AU0000564290B2
Принадлежит:

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21-10-1991 дата публикации

HIGH SPEED LOGIC AND MEMORY FAMILY USING RING SEGMENT BUFFER

Номер: AU0007582391A
Принадлежит:

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23-02-2017 дата публикации

Integrated circuitry for generating a clock signal in an implantable medical device

Номер: AU2013381688B2
Принадлежит: Griffith Hack

Timer circuitry completely formable in an integrated circuit (IC) for generating a clock signal in an implantable medical device is disclosed. The timer circuitry can be formed on the same Application Specific Integrated Circuit typically used in the implant, and requires no external components. The timer circuitry comprises modification to a traditional astable timer circuit. A resistance in the disclosed timer circuit can be trimmed to adjust the frequency of the clock signal produced, thus allowing that frequency to be set to a precise value during manufacturing. Precision components are not needed in the RC circuit, which instead are used to set the rough value of the frequency of the clock signal. A regulator produces a power supply for the timer circuitry from a main power supply (Vcc), producing a clock signal with a frequency that is generally independent of temperature and Vcc fluctuations.

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20-08-1974 дата публикации

PULSE TRAIN SUPPLY SYSTEMS

Номер: CA953372A
Автор:
Принадлежит:

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15-08-1978 дата публикации

WIDE RANGE PULSE GENERATOR

Номер: CA1036677A

WIDE RANGE PULSE GENERATOR A pulse generator for generating pulses over a wide range without changing scales is disclosed. The pulse generator is capable of generating pulses in the range from 0.5 Hz to greater than 2 MHz in one continuous range. The wide range of operation is achieved by a timing capacitor which is charged at a logarithmic rate with respect to a frequency determining voltage input signal. This permits a wide frequency range to be covered with a reasonable range of the voltage input signal.

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22-09-1991 дата публикации

HIGH SPEED LOGIC AND MEMORY FAMILY USING RING SEGMENT BUFFER

Номер: CA0002078778A1
Принадлежит: SIM & MCBURNEY

A logic and memory family using CMOS technology operates at high speeds using a Ring Segment Buffer to couple logic gates to one another in an integrated circuit chip, and to couple memory cells to other circuits to provide shift registers, triggers, clock pulse generators and other memory related circuits. The Ring Segment Buffer comprises one or more serially connected complementary field effect transistor (FET) inverter stages, with the output of a preceding stage being connected to the input of a succeeding stage. The N-channel FET in each inverter stage has a channel width which is less than a predetermined factor (K) times the width of the N-channel of the immediately preceding stage. By maintaining the K channel width relationship, the Ring Segment Buffer can drive large capacitive loads at high speed. The Ring Segment Buffer may also provide a predetermined delay which is a function of channel length and the number of stages. For large capacitive loads, the last stage of the Ring ...

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06-01-1978 дата публикации

VARIABLE INTENSITY ILLUMINATION APPARATUS

Номер: FR0002191397B1
Автор:
Принадлежит:

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20-01-1978 дата публикации

RELAXATION OSCILLATOR

Номер: FR0002232136B1
Автор:
Принадлежит:

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28-10-1977 дата публикации

OSCILLATING CIRCUIT HAS JUST TRANSISTORS MOS, COMPENSATES IN TEMPERATURE

Номер: FR0002346902A1
Принадлежит:

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05-01-1973 дата публикации

MULTIPLE PHASE CLOCK GENERATOR CIRCUIT WITH CONTROL CIRCUIT

Номер: FR0002138715A1
Автор:
Принадлежит:

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21-06-2000 дата публикации

Semiconductor integrated circuit device

Номер: TW0000394942B
Автор:
Принадлежит:

An oscillation circuit provides clock signals and a clock distribution circuit or system of circuits having low skew and low jitter to logic circuits and memory circuits of a microprocessor or the like. Further, a semiconductor integrated circuit device of high speed is provided as a result of the stable clock signal that is generated and distributed. The oscillation circuit is in a semiconductor integrated circuit device having a plurality of oscillators each having an oscillation node, wherein the oscillation nodes of each of the oscillators are connected together by a conductive wiring line that may be a closed loop. The oscillators are synchronized to oscillate at substantially the same frequency. The oscillators are connected to the conductive wiring line at connecting points having substantially the same interval of conductive wiring lengths between the connection points, which leads to synchronizing the oscillators to oscillate with a substantially identical phase. The conductive ...

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08-10-2009 дата публикации

FRACTIONAL AND INTEGER PLL ARCHITECTURES

Номер: WO2009124145A2
Принадлежит:

A digital fractional PLL introduces an accumulated phase offset before the digital VCO using a digital accumulator to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component Δn. By forcing Δn to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a single bit comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock signal and the feedback signal to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.

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08-09-2006 дата публикации

CURRENT CONTROLLED OSCILLATOR

Номер: WO2006092842A1
Принадлежит:

A frequency range can be widened without increasing the power consumption. Current circuits (1a,1b) output charging currents based on a control current. Capacitors (C1,C2), which are associated with the respective current circuits (1a,1b), are supplied with the charging currents. Discharge transistors (M1,M3), which are associated with the respective capacitors (C1,C2), cause the respective capacitors (C1,C2) to discharge. Switching transistors, which are connected between the current circuits (1a,1b) and the capacitors (C1,C2), open/close the paths between the current circuits (1a,1b) and the capacitors (C1,C2) in accordance with the voltages of the capacitors (C1,C2). Signal output transistors (M5,M6), the gates of which are connected between the current circuits (1a,1b) and the switching transistors (M2,M4), output signals to a flip-flop (2) in accordance with the charging currents. The flip-flop (2) alternately drives the discharge transistors (M1,M3) in response to the signals.

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09-12-1999 дата публикации

A TUNABLE DIGITAL OSCILLATOR CIRCUIT AND METHOD FOR PRODUCING CLOCK SIGNALS OF DIFFERENT FREQUENCIES

Номер: WO1999063665A1
Автор: FURMAN, Elliot
Принадлежит:

A tunable digital oscillator circuit comprising a first dual-clock pulse generator (202), a second dual-clock pulse generator (204), a run controller (104), a stop controller (106) and a decoder (108). The first and second dual-clock pulse generators are coupled in a cascaded manner with the output of the first dual-clock pulse generator provided as an input to the second dual-clock pulse generator. Each of the first and second dual-clock pulse generators is preferably tunable, in that, they can output one clock signal from a predetermined number of frequencies. The run controller is preferably coupled to receive a start signal and the output of the second dual-clock pulse generator. The run controller provides the input to begin and maintain the first and second dual-clock pulse generators in the state of generating a clock signal. The stop controller is coupled to receive a clock signal from the first dual-clock pulse generator, and a stop signal. The tunable digital oscillator circuit ...

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10-11-1994 дата публикации

RING OSCILLATOR

Номер: WO1994026025A1
Принадлежит:

An oscillator comprises an odd number of single ended stages (S1, S2, S3), each stage comprising two transistors (T1, T2) connected as a current mirror. The stage provides for low-voltage performance and improved process tolerance characteristics.

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01-05-2008 дата публикации

RESISTOR-CAPACITOR OSCILLATION CIRCUIT CAPABLE OF ADJUSTING OSCILLATION FREQUENCY AND METHOD OF THE SAME

Номер: US2008100391A1
Принадлежит:

There is provided an RC oscillation circuit capable of adjusting an oscillation frequency, and an oscillation method thereof. The RC oscillation circuit including: an RC oscillator including a variable resistor and a variable capacitor, the RC oscillator generating an RC oscillating signal having a frequency determined by a resistance of the variable resistor and a capacitance of the variable capacitor; a counter counting a clock number of a reference oscillating signal corresponding to one period of the RC oscillating signal to generate a first count value, the reference oscillating signal having a preset frequency; and a frequency controller controlling a frequency of the RC oscillating signal by determining the resistance of the variable resistor and the capacitance of the variable capacitor such that a difference between the first count value and a preset second count value is smaller than a preset first critical value.

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27-04-1993 дата публикации

Current controlled oscillator with linear output frequency

Номер: US0005206609A1
Автор: Mijuskovic; Dejan
Принадлежит: Motorola, Inc.

A current controlled ring oscillator use a plurality of serial amplifier stages with the output of the last stage connected to the input of the first stage. The ring oscillator maintains a linear output frequency over the control range by using a control circuit to compensate for variation in gate-source voltage of output clamping transistors. Moreover, switching nonlinearities can be removed by increasing the minimum value and decreasing the maximum value of the output waveform of each amplifier stage so as to compensate for time lost during the transition of the deadzone.

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04-01-1994 дата публикации

Bi-phase decoder phase-lock loop in CMOS

Номер: US0005276716A1
Автор: Wincn; John M.
Принадлежит: Advanced Micro Devices Inc.

A bi-phase decoder for extraction of an embedded clock in a Manchester encoded signal operating at about ten megahertz. A phase-lock loop (PLL) includes a phase frequency detector and an interruptible voltage controlled oscillator (VCO). The PLL has a narrow bandwidth for stability to reduce effects of five megahertz components on clock extraction. The bi-phase decoder has a fast acquisition time to ensure frequency and phase lock during a preamble portion of an input data packet. A clock reference operates the PLL and the VCO at a nominal frequency of the embedded clock. Receipt of a data packet initiates interruption of the VCO operation to switch in the received data. The VCO resumes operation in phase with the received data packet and at about the proper frequency, therefore acquisition is fast. The VCO is designed to resume operation after operation at a particular phase to help in phase alignment.

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06-05-1997 дата публикации

Multiple frequency oscillator

Номер: US0005627498A1
Автор: Meyer; Charles S.
Принадлежит: Nvision, Inc.

An oscillator comprises a first inverter provided with a resonant feedback circuit, a second inverter having its signal input terminal at the same DC level as the signal input terminal of the first inverter, and a current source having a current supply terminal connected to the power supply terminals of the first and second inverters.

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15-04-1997 дата публикации

Voltage supply isolation buffer

Номер: US0005621360A1
Автор: Huang; Samson X.
Принадлежит: Intel Corporation

A CMOS delay cell with feedback circuitry to ensure that the delay cell is operating in saturation mode. A voltage controlled oscillator (VCO) comprising a loop of an odd number of delay cells, where the VCO is operating in a saturation mode. Under normal operation any intermediate node in the VCO will generate an output signal from a delay cell with reduced supply noise. The output signal can be used to generate a PLL clock signal with a lower phase jitter than prior art VCO's operating at low supply potentials.

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10-06-1997 дата публикации

Clock pulse generator

Номер: US0005638014A1
Автор: Kurita; Kozaburo
Принадлежит: Hitachi, Ltd.

A simply structured clock pulse generator operating stably in a wide range of frequencies in response to a timing signal fed from outside a semiconductor integrated circuit. A first frequency signal fed from the external terminal of the semiconductor integrated circuit and a second frequency signal generated within the semiconductor integrated circuit are input to a phase comparator. The output signal of the phase comparator is smoothed by a low-pass filter for conversion to a voltage signal. A compensation circuit uses both a delay signal from a current-controlled delay circuit receiving the first frequency signal and the first frequency signal to generate a current signal corresponding to the frequency of the latter signal. The voltage signal generated by the low-pass filter is converted into a current signal. This current signal is combined with the current signal from the compensation circuit to control the oscillation frequency of a ring oscillator comprising a current-controlled delay ...

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04-08-2005 дата публикации

Oscillation circuit and semiconductor device

Номер: US2005168293A1
Принадлежит:

An oscillation circuit capable of outputting an oscillation signal of constant frequency free from the influence of source voltage, temperature, and nonuniformity and fluctuation in inverter threshold voltage. An inverter inverts a voltage applied to one end of a capacitive element and outputs the inverted voltage to transistors and an inverter. A constant voltage source outputs a constant voltage free from the influence of source voltage and temperature. The transistors connect the other end of the capacitive element to the constant voltage source or ground in accordance with the voltage output from the first-mentioned inverter. A constant current source causes a constant current free from the influence of the source voltage and temperature to flow into or out of the one end of the capacitive element in accordance with the voltage from the second-mentioned inverter connected to the first-mentioned inverter. Consequently, the voltage at the one end of the capacitive element varies with ...

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07-08-2001 дата публикации

Voltage-controlled oscillator including current control element

Номер: US0006271730B1

An odd number of inverter circuits are connected with each other so as to form a ring. A first current-control element is provided between an oscillation signal line which is used for connecting adjacent inverter circuits and a power-source-potential point, a current flowing through the first current-control element varying by a first control signal. A second current-control element is provided between the oscillation signal line and a ground point, a current flowing through the second current-control element varying by a second control signal.

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25-08-1981 дата публикации

Gated oscillator

Номер: US0004286233A
Автор:
Принадлежит:

A gated oscillator implemented with cascade-connected inverting logic circuits and resistor-capacitor timing elements generates oscillations so long as an inhibiting signal is not applied to one of the logic circuits. Means are provided to maintain potentials on the timing elements during application of inhibiting signal, which potentials are equivalent to steady-state operating potentials at the inception of a state transition. When the inhibiting signal is discontinued allowing oscillations to be generated, the initial pulse period is equal to the steady-state pulse period.

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14-04-1998 дата публикации

High-speed voltage controlled oscillator having a level shifter for providing rail-to-rail output

Номер: US0005739726A
Автор:
Принадлежит:

A voltage controlled oscillator circuit with a high power supply rejection ratio incorporates a clamping transistor with respect to each output terminal which limits the signal swing of the output terminal. The limited voltage swing allows relatively large movements in the power supply and ground voltages without causing significant changes in the frequency of the output signals. Such an oscillator circuit may be incorporated into an integrated circuit characterized by noisy power supply and ground conductors. Additionally, multiple delayed versions of the output frequency may be created using a level shifter circuit and a buffer circuit. The oscillator circuit is relatively quick to react to changes in the controlling voltage, adjusting the oscillation frequency in a relatively short time interval.

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22-01-1991 дата публикации

Lockproof low level oscillator using digital components

Номер: US4987389A
Автор:
Принадлежит:

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19-11-2019 дата публикации

Techniques for detecting and correcting errors on a ring oscillator

Номер: US0010483951B2
Принадлежит: Altera Corporation, ALTERA CORP

A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.

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13-12-1996 дата публикации

RING OSCILLATOR

Номер: JP0008330912A
Автор: NAKAJIMA TERUYA
Принадлежит:

PURPOSE: To shorten the delay time of continuous delayed signals and also to increase the number of delayed signals without changing the oscillation frequency and the number of stages of an inverter contained in one loop of a rind oscillator and with the same control current/oscillation frequency characteristic kept as it is by connecting together the unit inverter circuits in an odd number of stages. CONSTITUTION: The serial circuits of P and N channel transistors are connected in parallel to each other, and a constant current source that is controlled by a current control circuit 9 is connected to the P and N channel sides of these parallel circuits respectively. Thus a unit inverter circuit 22 is obtained in such a constitution where two inverters use the constant current sources 2 and 3 in common to each other. Then such circuits 22 are connected together in a ring shape and continuously at (n) staves (n: an odd number). As a result, the delay time of every inverter stage is shortened ...

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17-07-1982 дата публикации

OSCILLATION CIRCUIT

Номер: JP0057115017A
Автор: NAKANISHI TADAAKI
Принадлежит:

PURPOSE: To achieve stable oscillation with a hysteresis width determined by a forward voltage of a diode, by connecting a charge/discharge circuit to the input of inversion gate consisting of an MOSFET via a pair of diodes of antiparallel connection. CONSTITUTION: When an input terminal (a) of an inversion gate 12 is at L level, an output terminal (c) is at H level, and an output terminal (d) of an inversion gate B is at L level, then a capacitor C1 is charged via a resistor R1. When a potential at connecting point (a) between the resistor R1 and the capacitor C1 becomes a potential being the sum between a threshold value of the inversion gate 12 and a forward voltage of a diode D1, the gate 12 is inverted, the connecting point (c) is at L level and the connecting point (d) is at H level. When the capacitor C1 is discharged via the resistor R1 and the potential at the connecting point (a) becomes a threshold voltage of the gate 12 subtracted from the forward voltage of the diode D2, the ...

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07-10-1997 дата публикации

PHASE LOCKED LOOP HAVING VOLTAGE-CONTROLLED OSCILLATOR UTILIZING COMBINATIONAL LOGIC

Номер: JP0009266444A
Автор: NIELSON EDWARD T
Принадлежит:

PROBLEM TO BE SOLVED: To generate an output clock which has its frequency multiplied by operating at nearly the same frequency with an input clock. SOLUTION: The phase locked loop 46 is equipped with a comparator 50, a VCO controller (loop filter) 52, and a voltage-controlled oscillator(VCO) 54 having a multistage oscillator part and a combinational logic part. The comparator 50 inputs the input clock 58 and a VCO clock 62 and compares their clock frequencies with each other to generate a comparator output signal 60. The VCO oscillator 52 inputs the comparator output signal 60 and generates a VCO control signal 64 which controls the frequency of oscillation of the multistage oscillator part of the VCO 54. COPYRIGHT: (C)1997,JPO ...

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24-01-2018 дата публикации

УСТРОЙСТВО ФОРМИРОВАНИЯ УПРАВЛЯЮЩИХ НАПРЯЖЕНИЙ ДЛЯ ГЕНЕРАТОРА, УПРАВЛЯЕМОГО НАПРЯЖЕНИЕМ

Номер: RU2642405C1

Изобретение относится к интегральной электронной технике и может быть использовано в составе боков синтезаторов сетки частот, а именно при реализации генератора, управляемого напряжением (ГУН). Технический результат заключается в повышения стабильности частоты выходного сигнала ГУН к действию помех по цепям напряжения питания. Устройство формирования управляющих напряжений для управления частотой выходного сигнала ГУН содержит элемент, корректирующий в зависимости от изменений напряжения питания значение тока, используемого при формировании управляющих напряжений. Элемент, осуществляющий коррекцию, включен последовательно с основным токозадающим элементом, что обеспечивает близкое к постоянному значению относительное изменение тока в широком диапазоне. 11 ил.

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30-09-1999 дата публикации

Circuit for timing and pulse width modulation of a primary side clocked current supply

Номер: DE0019805847A1
Принадлежит:

The circuit has an optocoupler or a transistor connected to the output of the oscillator and driven by the secondary voltage. The oscillator is a standard CMOS IC with three inverters connected in series and an RC component. The resistor component of the RC member (R1) is connected to the output of the third inverter. The capacitor (C1) is connected to the output of the second inverter. The optocoupler or transistor is connected to the output of the third inverter.

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24-04-1980 дата публикации

Номер: DE0002822509B2

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20-03-1996 дата публикации

Controllable oscillator for a matrix display

Номер: GB0002293289A
Принадлежит:

A controllable oscillator for a matrix display comprises a non-inverting MOS buffer 1, a feedback capacitor 5, MOS switches 3, 4 and controllable charging and discharging current sources 11 and 12 which permit adjustment of the duty ratio and the frequency. Resistors may be used instead of current sources (figures 3 and 8). A matrix display memory is disclosed (figures 9 and 10) in which equivalent circuits that simulate access delay times of the display memory and the character generator memory are used to obviate the need for higher frequency clocks. The memories may have a precharge phase in each clock cycle. The display may be an LCD. ...

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19-07-2000 дата публикации

Clock generator producing clock signal quickly adjusted to target frequency

Номер: GB0000013224D0
Автор:
Принадлежит:

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05-01-2012 дата публикации

Low-power dual-edge-triggered storage cell with scan test support and clock gating circuit therefor

Номер: US20120001669A1
Автор: Jakob Salling
Принадлежит: Oticon AS

A storage cell having a pulse generator and a storage element is proposed. The storage element input is connected to receive a data input signal. The storage element output is connected to provide a data output signal. The storage element is operable in one of a data retention state and a data transfer state in response to a storage control signal received from the pulse generator. The pulse generator is connected to receive a clock signal with rising and falling clock signal edges and is adapted to provide control pulses in the storage control signal. Each control pulse has a leading edge and a trailing edge. The control pulses have a polarity suited to invoke the data transfer state on their leading edges. The novel feature is that the pulse generator is adapted to initiate a rising-edge control pulse when receiving a rising clock signal edge and to initiate a falling-edge control pulse when receiving a falling clock signal edge. In this way, a dual-edge-triggered flip-flop may be made using only combinatorial logic circuitry and one level- or single-edge-triggered storage element. The storage cell has low power consumption, facilitates scan testing and can be used by existing design tools and test equipment.

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25-10-2018 дата публикации

Двухканальный ШИМ с двойным регулирующим воздействием на наклон пилообразного напряжения

Номер: RU0000184381U1

Полезная модель относится к области электроники и может быть применена при разработке вторичных источников питания (ВИП). Предложенная схема двухканального широтно-импульсного модулятора с двойным регулирующим воздействием на наклон пилообразного напряжения отличается от прототипа меньшим числом логических элементов (вентилей), более высокой надежностью и меньшей потребляемой мощностью. Все эти положительные качества были достигнуты за счет введения в состав схемы широтно-импульсного модулятора R-S триггера на двух элементах 2ИЛИ-НЕ, счетного триггера выполненного на Д триггере, срабатывающим по фронту нарастания входного сигнала (фронт 01), электронного ключа и двух канальных вентилей 3ИЛИ-НЕ, соединенных новыми межэлементными связями. Введенные элементы и межэлементные связи позволили реализовать цифровую часть схемы широтно-импульсного модулятора на однотипных элементах ИЛИ-НЕ, сократить число элементов (вентилей, транзисторов) и тем самым повысить надежность и снизить потребляемую мощность. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 184 381 U1 (51) МПК H03K 3/033 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H03K 3/033 (2006.01); H03K 3/02 (2006.01); H03K 4/50 (2006.01); H03K 4/56 (2006.01); H03K 4/90 (2006.01); H03K 7/08 (2006.01) (21)(22) Заявка: 2017123025, 29.06.2017 29.06.2017 Дата регистрации: Приоритет(ы): (22) Дата подачи заявки: 29.06.2017 (56) Список документов, цитированных в отчете о поиске: RU 2613522 C1, 16.03.2017. RU (45) Опубликовано: 25.10.2018 Бюл. № 30 (54) Двухканальный ШИМ с двойным регулирующим воздействием на наклон пилообразного напряжения (57) Реферат: Полезная модель относится к области широтно-импульсного модулятора R-S триггера электроники и может быть применена при на двух элементах 2ИЛИ-НЕ, счетного триггера разработке вторичных источников питания выполненного на Д триггере, срабатывающим (ВИП). по фронту нарастания входного сигнала (фронт Предложенная схема ...

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12-01-2012 дата публикации

Hybrid data transmission circuit

Номер: US20120008713A1
Принадлежит: Panasonic Corp

A data transmitter having a parallel-to-serial conversion function is supplied with a clock by a PLL circuit unit. In the PLL circuit unit, a first multiphase clock supplied to a first parallel-to-serial conversion circuit is generated and output by a multiphase VCO circuit, while a second multiphase clock supplied to a second parallel-to-serial conversion circuit is generated and output by a multiphase clock generator. The multiphase clock generator generates the second multiphase clock based on the clock output from the multiphase VCO circuit.

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09-02-2012 дата публикации

Method for power reduction and a device having power reduction capabilities

Номер: US20120032720A1
Автор: Sergey Sofer
Принадлежит: FREESCALE SEMICONDUCTOR INC

A device that includes a dual edge triggered flip-flop that has state retention capabilities, the dual edge triggered flip-flop includes: a retention latch that includes a first inverter, a second inverter and a first transfer gate; wherein the first and second inverters receive power during a power gating period; a second latch that includes a third inverter, a fourth inverter and a second transfer gate; wherein the third and fourth inverters are powered down during a power gating period; a third transfer gate that is coupled between input nodes of the retention latch and the second latch; wherein the third transfer gate is opened during the power gating period; wherein the first transfer gate is controlled by a control signal and the second transfer gate is controlled by an inverted control signal; wherein the retention latch stores, at the end of the power gating period a retention value; wherein the retention value is selected, in response to a value of the control signal when the power gating period starts, out of a first initial value stored at the retention latch at the beginning of the power gating period and a second initial value stored at the second latch at the beginning of the power gating period.

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09-02-2012 дата публикации

Semiconductor integrated device

Номер: US20120032730A1
Автор: Jun Koyama
Принадлежит: Semiconductor Energy Laboratory Co Ltd

To reduce power consumption of a semiconductor integrated circuit and to reduce delay of the operation in the semiconductor integrated circuit, a plurality of sequential circuits included in a storage circuit each include a transistor whose channel formation region is formed with an oxide semiconductor, and a capacitor whose one electrode is electrically connected to a node that is brought into a floating state when the transistor is turned off. By using an oxide semiconductor for the channel formation region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized. Thus, by turning off the transistor in a period during which power supply voltage is not supplied to the storage circuit, the potential in that period of the node to which one electrode of the capacitor is electrically connected can be kept constant or almost constant. Consequently, the above objects can be achieved.

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16-02-2012 дата публикации

Ring based impedance control of an output driver

Номер: US20120038427A1
Принадлежит: Stoiber Steven T, Stuart Siu

In one embodiment, there is a method that can include utilizing a ring oscillator module to determine a process corner of an integrated circuit as fabricated that includes the ring oscillator module. The impedance of an output driver of the integrated circuit can be altered based on the process corner of the integrated circuit as fabricated.

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01-03-2012 дата публикации

Securing a Storage Element for a Binary Datum, Control Register and Chip Card

Номер: US20120054863A1
Принадлежит: Oberthur Technologies SA

Securing a storage element for a binary datum, control register and chip card. This element ( 60 ) for storing a binary datum (D) inputs a signal representative of said binary datum, said storage to be carried out when an enable signal (ENA) is at a first predetermined level, supplies an output signal (Q) the state whereof represents the datum stored in said storage element ( 10 ), and detects an attack aimed at said enable signal (ENA) or at a signal internal to said storage element.

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22-03-2012 дата публикации

Master-slave flip-flop with timing error correction

Номер: US20120068749A1
Принадлежит: FREESCALE SEMICONDUCTOR INC

A digital logic circuit includes a logic element for providing a data signal, a clock for providing a clock signal and a master-slave flip-flop. The master-slave flip-flop includes a master latch for storing data on a master latch input at a first active edge of the clock signal and a slave latch for storing data on an output of the master latch at a second active edge of the clock signal following the first active edge. A timing error detector asserts an error signal in response to a change in the data signal during a detection period following the first active edge of the clock signal. A timing correction module selectively increases a propagation delay of the data signal from the logic element to the master latch input in response to the error signal.

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22-03-2012 дата публикации

Switching circuits, latches and methods

Номер: US20120068750A1
Автор: John Mccoy
Принадлежит: Micron Technology Inc

Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second binary level. One such switching circuit may have a metastable state that is closer to a first voltage corresponding to the first binary level than it is to a second voltage corresponding to the second binary level. In other embodiments, the metastable state may be dynamically adjustable so that it is at one voltage before the circuit switches and at a different voltage after the circuit switches. As a result, the switching circuit may respond relatively quickly to the input signal transitioning from the first binary level to the second binary level.

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17-05-2012 дата публикации

Latch circuit, flip-flop having the same and data latching method

Номер: US20120119783A1
Автор: Gunok JUNG, Minsu Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A latch circuit includes a first tri-state inverter configured to invert an input voltage in response to a pulse and to output the inverted voltage to a first node, a second tri-state inverter connected between the first node and a second node and to invert a voltage of the second node in response to an inverted pulse being an inverted version of the pulse, and a variable inversion unit connected between the first node and the second node. The variable inversion unit adjusts a logical threshold value according to a logical value corresponding to a voltage of the first node and inverts a voltage of the first node based upon the adjusted logical threshold value, the logical threshold value indicating a voltage for discriminating the logical value.

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28-06-2012 дата публикации

Oscillator device and methods thereof

Номер: US20120161884A1
Автор: Visvesh S. Sathe
Принадлежит: Advanced Micro Devices Inc

A signal generator provides a plurality of oscillating signals, whereby each oscillating signal has a different peak voltage and has a predictable and consistent phase relationship with the other oscillating signals. The signal generator includes a plurality of stacked oscillators arranged between two reference voltages, such that each oscillator in the stack generates an oscillating signal having a different peak voltage. Each oscillator stage in a designated oscillator includes a transistor that is connected to a transistor of a corresponding stage in another oscillator. This arrangement of the oscillators provides for charge transfer between the corresponding stages to provide for similar voltage swings in each oscillating signal, as well as to provide for predictable phase relationship between the oscillating signals.

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19-07-2012 дата публикации

Semiconductor integrated circuit and power-supply voltage adaptive control system

Номер: US20120182047A1
Принадлежит: Renesas Electronics Corp

A semiconductor integrated circuit has: N input terminals; N output terminals; a plurality of flip-flops including N flip-flops and R redundant flip-flops; a selector section configured to select N selected flip-flops from the plurality of flip-flops depending on reconfiguration information and to switch data flow such that data input to the N input terminals are respectively output to the N output terminals by the N selected flip-flops; and an error detection section. At a test mode, the N flip-flops form a scan chain and a scan data is input to the scan chain. The error detection section detects an error flip-flop included in the N flip-flops based on scan input/output data respectively input/output to/from the N flip-flops at the test mode and further generates the reconfiguration information such that the detected error flip-flop is excluded from the N selected flip-flops.

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19-07-2012 дата публикации

Monitoring negative bias temperature instability (nbti) and/or positive bias temperature instability (pbti)

Номер: US20120182079A1
Автор: Jae-Joon Kim, Rahul M. Rao
Принадлежит: International Business Machines Corp

A ring oscillator circuit for measurement of negative bias temperature instability effect and/or positive bias temperature instability effect includes a ring oscillator having first and second rails, and an odd number (at least 3) of repeating circuit structures. Each of the repeating circuit structures in turn includes an input terminal and an output terminal; a first p-type transistor having a gate, a first drain-source terminal coupled to the first rail, and a second drain source terminal selectively coupled to the output terminal; a first n-type transistor having a gate, a first drain-source terminal coupled to the second rail, and a second drain source terminal selectively coupled to the output terminal; and repeating-circuit-structure control circuitry. The ring oscillator circuit also includes a voltage supply and control block.

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27-09-2012 дата публикации

Methods and devices for detecting single-event transients

Номер: US20120242373A1
Принадлежит: UNIVERSITY OF SASKATCHEWAN

Methods and devices for detecting single-event transients in combinational logic circuits and other circuits. A sensing circuit detects a voltage or current deviation at a bulk contact node of a transistor. Output of the sensing circuit is amplified and used to flip a latch. Output of the latch may be evaluated and used in possible error correction measures.

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29-11-2012 дата публикации

Clock generation circuit, display device drive circuit, and control method of clock generation circuit

Номер: US20120299505A1
Автор: Katsuhisa Ohashi
Принадлежит: Renesas Electronics Corp

A clock generation circuit that can reliably recover from a state in which generation of a clock is stopped even during a power-on process and a normal operation. The clock generation circuit includes a clock extraction circuit that extracts an extracted clock from an embedded signal on which a clock and data are superimposed, and a stop detection circuit that detects a stop of the extracted clock on the basis of the embedded signal and the extracted clock and outputs a reset signal that resets the clock extraction circuit to an initial state.

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17-01-2013 дата публикации

Differential ring oscillator-type voltage control oscillator

Номер: US20130015894A1
Автор: Kunihiko Kouyama
Принадлежит: Individual

A voltage control oscillator according to the present invention includes: a voltage-current converter circuit that converts an inputted voltage to a current according to the value of the voltage; a current mirror circuit; a ring oscillator including differential inverters connected in multiple stages; an inverting amplifier; and a buffer. The ring oscillator outputs, from each of the differential inverters, a signal amplitude-limited by a “current converted by the voltage-current converter circuit and the current mirror circuit” and a “voltage applied from the inverting amplifier” and the ring oscillator outputs an oscillatory frequency in response to the output signal.

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31-01-2013 дата публикации

Fractional and integer pll architectures

Номер: US20130027102A1
Принадлежит: Qualcomm Inc

A digital fractional PLL introduces an accumulated phase offset before the digital VCO to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component Δn. By forcing Δn to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock and feedback signals to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.

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07-02-2013 дата публикации

Circuits and methods for latch-tracking pulse generation

Номер: US20130033292A1
Автор: Fadi Adel Hamdan
Принадлежит: Qualcomm Inc

Circuits and methods for latch-tracking pulse generation across process, voltage and temperature (PVT) variations are disclosed in one embodiment, the method includes receiving a clock input at a pulse generation circuit and generating a pulse at the pulse generation circuit in response to the clock input. The method further includes distributing the pulse to a mimic latch, which writes a mimic storage node through a mimic storage circuit of the mimic latch in response to the pulse. The method further includes terminating generation of the pulse at the pulse generation circuit in response to a transition of the mimic storage node. The method may include receiving a clock enable input at a pulse control circuit coupled to the pulse generation circuit and either suppressing or allowing generation of a pulse in response to a value of the clock enable input.

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21-02-2013 дата публикации

Integrated Circuit With an Adaptable Contact Pad Reconfiguring Architecture

Номер: US20130043939A1
Принадлежит: Broadcom Corp

An apparatus and method are disclosed for providing test mode contact pad reconfigurations that expose individual internal functional modules or block groups in an integrated circuit for testing and for monitoring. A plurality of switches between each functional module switches between passing internal signals among the blocks and passing in/out signals external to the block when one or more contact pads are strapped to input a pre-determined value. Another set of switches between the functional modules and input/output contact pads switch between functional inputs to and from the functional modules and monitored signals or input/output test signals according to the selected mode of operation.

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28-02-2013 дата публикации

Soft Error Robust Low Power Latch Device Layout Techniques

Номер: US20130049835A1
Принадлежит: Cisco Technology Inc

A latch device and related layout techniques are provided to reduce soft error rates caused by radiation or other exposure to ionized/charged particles. The latch device comprises a pair of cross-coupled inverters forming a storage cell. A pair of clock pass transistors is coupled to the pair of cross-coupled inverters. The pair of clock pass transistors is configured to receive as input a clock signal. On both true and complement sides of the latch device, a channel-connected region is formed between one of the pair of cross-coupled inverters and one of the pair of clock pass transistors. Each channel-connected region is configured to have a reduced Linear Energy Transfer (LET) cross-section. The reduced LET cross-section results in a reduced soft error rate.

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07-03-2013 дата публикации

Low current single chip oscillator timing circuit

Номер: US20130057353A1
Автор: Dan Raphaeli
Принадлежит: Individual

A low current single chip oscillator timing circuit which includes a dual mode capacitor circuit having a larger capacitance mode and a smaller capacitance mode having a fixed ratio. The timing circuit also includes an oscillator circuit that uses the dual mode capacitor circuit as a part of its time base wherein the large capacitance mode is operated with low power consumption and as needed includes a circuit that generates a reference pulse, wherein the short pulse and the reference pulse are compared and the result is used for correction to the oscillator frequency to create a feedback loop.

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11-04-2013 дата публикации

Low consumption flip-flop circuit with data retention and method thereof

Номер: US20130088272A1

The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

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02-05-2013 дата публикации

Nonvolatile latch circuit, nonvolatile flip-flop circuit, and nonvolatile signal processing device

Номер: US20130107606A1
Автор: Yoshikazu Katoh
Принадлежит: Panasonic Corp

A nonvolatile latch circuit according to the present invention wherein the outputs of an inverter circuit and other inverter circuit which are cross-coupled are connected to each other via a series circuit in which a transistor, a variable resistance element, and other transistor are connected in this order; a store operation and a restore operation for a latch state are controlled by application of a voltage to control terminals of the transistor and the other transistor; and both end potentials of the variable resistance element are summed, an amount of the sum is amplified and inverted, and the inverted amount is returned to an input of the inverter circuit or the other inverter circuit, thereby restoring a logic state in which a forming process of the variable resistance element can be performed.

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13-06-2013 дата публикации

Oscillator with frequency determined by relative magnitudes of current sources

Номер: US20130147564A1
Автор: Tien-Yen Wang
Принадлежит: Individual

An oscillator circuit includes a circuit loop and multiple current sources. The circuit loop includes an output having the oscillating signal. The multiple current sources are turned on independently of a phase of the oscillating signal. The current sources control magnitudes of both charging current and discharging current at nodes of the circuit loop, including the output. Relative magnitudes of different current sources determine a frequency of the oscillating signal.

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20-06-2013 дата публикации

SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE

Номер: US20130154706A1
Автор: ISOZAKI Tomoaki
Принадлежит: RENESAS ELECTRONICS CORPORATION

A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal. The entire chip area is reduced, as compared with the case where plural semiconductor chips, operated at different operating voltages, are interconnected and used as such in a semiconductor device provided with an input/output buffer operating at a voltage different from the respective operating voltages resulting in an increased chip area. 1. A semiconductor chip comprising:an output circuit including a first transistor and a second transistor, being interconnected in series and turned on or off complementarily, said output circuit outputting a signal to a first external terminal; anda first power supply voltage supply source, andan internal circuit outputting a signal to said output circuit;a third transistor connected in series with said first transistor and having a gate terminal connected to a second external terminal which is connected to a power supply of an external circuit, wherein said third transistor is connected between said first supply voltage and said first transistor;said third transistor having one terminal connected to said first power supply voltage source; a first internal circuit unit which outputs to a gate ...

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27-06-2013 дата публикации

Configuration Context Switcher with a Latch

Номер: US20130162291A1
Принадлежит: Tabula Inc

Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.

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27-06-2013 дата публикации

Oscillator with highly-adjustable bang-bang control

Номер: US20130162357A1
Принадлежит: Advanced Micro Devices Inc

A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.

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11-07-2013 дата публикации

REFERENCE VOLTAGE GENERATION CIRCUIT, OSCILLATION CIRCUIT INCLUDING THE SAME AND METHOD FOR CALIBRATING OSCILLATION FREQUENCY OF OSCILLATION CIRCUIT

Номер: US20130176082A1
Автор: Ishikawa Kiyoshi
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

A reference voltage generation circuit has: a first PN junction element; a second PN junction element having a higher forward direction voltage than the first PN junction element; a first differential amplifier inputting an anode of the first PN junction element and a first connection node between a first and a second resistor disposed in series between a first output of the first differential amplifier and a first potential, and generating a first output voltage at the first output; and a second differential amplifier inputting an anode of the second PN junction element and a second connection node between a fourth and a third resistor disposed in series between a second output of the second differential amplifier and the first output of the first differential amplifier, and generating a reference voltage at the second output. A resistance ratio between the third and the fourth resistors is variable. 1. A reference voltage generation circuit comprising:a first PN junction element having a first forward direction voltage;a second PN junction element having a different current density from the first PN junction element and having a second forward direction voltage higher than the first forward direction voltage;a first differential amplifier having a first input configured to be connected to an anode of the first PN junction element and a second input configured to be connected to a first connection node between a first and a second resistor disposed in series between a first output of the first differential amplifier and a first potential, and configured to generate a first output voltage at the first output; anda second differential amplifier having a first input configured to be is connected to an anode of the second PN junction element and a second input configured to be connected to a second connection node between a fourth and a third resistor disposed in series between a second output of the second differential amplifier and the first output of the first ...

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15-08-2013 дата публикации

ELECTRONIC CIRCUITRY

Номер: US20130207734A1
Автор: Wood John
Принадлежит: ANALOG DEVICES, INC.

Electronic circuitry comprising operational circuits of active switching type requiring timing signals, and conductive means for distributing said timing signals to the operational circuits, wherein the timing signal distribution means includes a signal path that has different phases of a drive signal are supplied via active means at different positions about the signal path where that path exhibits endless electro-magnetic continuity without signal phase inversion or has interconnections with another signal path having different substantially unidirectional signal flow where there is no endless electromagnetic continuity between those signal paths and generally has non-linear associated circuit means where the signal path is of a transmission line nature. 1. An apparatus comprising:a differential transmission line in a closed loop, the differential transmission line including a first conductive trace, a second conductive trace, and an odd number of one or more cross-overs, wherein each of the one or more cross-overs is configured to reverse the polarity of a wave propagating through the differential transmission line; anda plurality of regenerative devices electrically connected along a path of the differential transmission line, wherein the plurality of regenerative devices are configured to provide energy to the wave to compensate for losses associated with the differential transmission line.2. The apparatus of claim 1 , wherein each of the plurality of regenerative devices comprises a first inverter and a second inverter claim 1 , wherein the first inverter includes an input electrically connected to the first conductive trace and an output electrically connected to the second conductive trace claim 1 , and wherein the second inverter includes an input electrically connected to the second conductive trace and an output electrically connected to the first conductive trace.3. The apparatus of claim 1 , wherein the plurality of regenerative devices comprises at ...

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22-08-2013 дата публикации

MINIMAL POWER LATCH FOR SINGLE-SLOPE ADCs

Номер: US20130214760A1
Автор: Hancock Bruce R.
Принадлежит: California Institute of Technology

A latch circuit that uses two interoperating latches. The latch circuit has the beneficial feature that it switches only a single time during a measurement that uses a stair step or ramp function as an input signal in an analog to digital converter. This feature minimizes the amount of power that is consumed in the latch and also minimizes the amount of high frequency noise that is generated by the latch. An application using a plurality of such latch circuits in a parallel decoding ADC for use in an image sensor is given as an example. 1. A minimal power latch circuit , comprising:{'b': 1', '0, 'a first latch and a second latch, said first latch having an input at which to receive a comparator signal C, an input at which to receive a code value signal D, and an input at which to receive a signal Q from said second latch, and having an output at which to provide an output signal Q; and'}{'b': 0', '1, 'said second latch having an input at which to receive said comparator signal C, an input at which to receive said code value signal D, and an input at which to receive said signal Q from said first latch, and having an output at which to provide said output signal Q;'}{'o': [{'@ostyle': 'single', 'b': '0', 'Q′'}, {'@ostyle': 'single', 'b': '0', 'Q'}, {'@ostyle': 'single', 'C'}, {'@ostyle': 'single', 'b': '0', 'Q'}], 'b': 1', '1', '1, 'said first latch and said second latch constructed to operate according to a pair of equations in which a first latch equation is given by =( \ue8a0D)+ +Q and a second latch equation is given by Q′=(Q+D)\ue8a0C\ue8a0 ;'}said comparator signal C representing a comparison as a function of time of a signal to be measured and a monotonically varying reference signal;said code value signal D representing a time increment measured from a start of said monotonically varying reference signal; and{'b': 0', '1, 'a selected one of said signal Q and said signal Q encoded with information indicative of said code value signal D at a time when no more ...

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29-08-2013 дата публикации

Oscillator based on a 6T SRAM for measuring the Bias Temperature Instability

Номер: US20130222071A1
Принадлежит: National Chiao Tung University NCTU

The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.

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29-08-2013 дата публикации

LEVEL SHIFTER, OSCILLATOR CIRCUIT USING THE SAME AND METHOD

Номер: US20130222072A1
Автор: van den Boom Jeroen
Принадлежит: NXP B.V.

A level shifter for a set of at least three phase-shifted signals is disclosed. The level shifter comprises an odd plural number of inverters arranged in a ring. A supply terminal of each inverter is coupled to a supply rail via a respective switching device, which is controlled by the phase-shifted signals. 1. A level shifter for a set of at least three phase-shifted signals , the level shifter comprising:a ring oscillator structure with an odd plural number of inverters arranged in a ring with an output of each inverter coupled to an input of the next inverter in the ring, anda control circuit comprising an identical input for receiving each of the set of at least three phase-shifted signals and being adapted to constrain the switching frequency of the ring oscillator structure to the frequency of oscillation of the set of at least three phase-shifted signals.2. A level shifter according to claim 1 , wherein the control circuit comprises a respective switching device coupled between a supply terminal of each inverter and a supply rail claim 1 , each switching device being controlled by a respective one of the set of phase-shifted signals.3. A level shifter according to claim 1 , wherein each switching device is connected between a lower voltage terminal of the respective inverter and a low supply voltage rail claim 1 , and wherein the positive supply terminal of each inverter is coupled to a high supply rail.4. A level shifter according to claim 3 , wherein the low and high supply rails are coupled to supply terminals of an integrated circuit in which the level shifter is integrated.5. A level shifter according to claim 1 , wherein each of the switching devices is identical.6. A level shifter according to claim 1 , wherein each of the switching devices is a transistor.7. A level shifter according to claim 1 , further comprising an additional inverter with its input coupled to the output of one of the inverters arranged in the ring and its output coupled to an ...

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12-09-2013 дата публикации

Nonvolatile Latch Circuit And Logic Circuit, And Semiconductor Device Using The Same

Номер: US20130234757A1
Автор: Jun Koyama, Kiyoshi Kato
Принадлежит: Semiconductor Energy Laboratory Co Ltd

To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion configured to hold data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, a capacitor electrically connected to a source electrode or a drain electrode of the transistor is included.

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12-09-2013 дата публикации

PHYSICAL UNCLONABLE FUNCTION

Номер: US20130234771A1
Принадлежит: INTRINSIC ID B.V.

A physical unclonable function is provided comprising a plurality of bus-keepers each bus-keeper of the plurality of bus-keepers being configured to settle into one of at least two different stable states upon power-up, the particular stable state into which a particular bus-keeper of the plurality of bus-keepers settles being dependent at least in part upon the at least partially random physical characteristics of the particular bus-keeper, and a reading circuit for reading the plurality of stable states into which the plurality of bus-keepers settled after a power-up, the plurality of bus-keepers being read-only. 117.-. (canceled)18. A physical unclonable function comprisinga plurality of cross-coupled loops of two invertors, each cross-coupled loop of the plurality of cross-coupled loops being configured to settle into one of at least two different stable states upon power-up, the particular stable state into which a particular cross-coupled loop of the plurality of cross-coupled loops settles being dependent at least in part upon the at least partially random physical characteristics of the particular cross-coupled loop,a reading circuit for reading the plurality of stable states into which the plurality of cross-coupled loops settled after a power-up, the physical unclonable function being configured for the plurality of cross-coupled loops to be read-only, anda switchable power domain, the plurality of cross-coupled loops being comprised in the power domain and at least a part of the physical unclonable function being outside the power domain, the power domain being configured for selectively connecting and disconnecting the plurality of cross-coupled loops from the power supply while the at least a part of the physical unclonable function is connected to the power supply.19. A physical unclonable function as in claim 18 , wherein the plurality of cross-coupled loops of two invertors are a plurality of bus-keepers.20. A physical unclonable function as in claim ...

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10-10-2013 дата публикации

Flip-Flop Circuits

Номер: US20130265092A1
Автор: JUNG GUNOK, LEE HOIJIN
Принадлежит:

A flip-flop circuit includes an input portion that receives a first external input signal through a first external input terminal, a storage portion that stores a signal transmitted from the input portion, and an output portion that outputs the signal stored in the storage portion through an external output terminal as a logic operation result with respect to a second external input signal received through a second external input terminal of the input portion. The output portion includes a logic gate directly connected to the external output terminal and an input terminal of the logic gate receives the signal stored in the storage portion. 1an input portion configured to output an output signal with respect to an external input signal in response to a pulse signal;a latch circuit configured to store one bit data information with respect to the output signal;an output portion configured to perform a NOR operation with respect to one bit data stored in the latch circuit and another external input signal; anda pulse generator configured to receive a clock signal and to output the pulse signal having a pulse width smaller than the clock signal.. A flip-flop circuit, comprising: This application is a Continuation Application of U.S. patent application Ser. No. 12/963,174, filed on Dec. 8, 2010 and claims under 35 U.S.C. §119 priority to and the benefit of Korean Patent Application No. 10-2009-0123440, filed on Dec. 11, 2009, the entire content of each of which is incorporated by reference herein.The present disclosure relates to semiconductor integrated circuits (ICs), and more particularly, to flip-flop circuits used therein.Through the development of ICs, various electronic devices including computers have the characteristics of high reliability, high speed, low power and miniaturization. As such electronic devices become more and more highly integrated, the complexity of circuits increases. For example, a very large scale IC (VLSI) can integrate more than one hundred ...

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17-10-2013 дата публикации

Self-biased oscillator

Номер: US20130271227A1
Автор: Taner Sumesaglam
Принадлежит: Intel Corp

Described herein is a self-biased oscillator. The self-biased oscillator comprises a first differentiator with adjustable resistance or capacitance, the first differentiator having an output node and an input node; and a second differentiator with adjustable resistance or capacitance, the second differentiator having an input node coupled to the output node of the first differentiator, and having an output node coupled to the input node of the first differentiator.

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31-10-2013 дата публикации

Oscillator, oscillating method, image sensor, and imaging apparatus

Номер: US20130284887A1
Принадлежит: Sony Corp

An oscillator includes: inverters that are connected in a loop shape and of which the number is an odd number greater than or equal to three; and a delay section that delays change in a voltage which is input to one inverter of the odd number of inverters. The one inverter is a schmitt trigger inverter. The schmitt trigger inverter includes a current source, and a resistor in which current supplied by the current source flows. A hysteresis width of the schmitt trigger inverter depends on the current which flows in the resistor.

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07-11-2013 дата публикации

SIGNAL TRANSFER CIRCUIT

Номер: US20130293265A1
Автор: NOH Young-Kyu
Принадлежит:

A signal transfer circuit includes a signal transfer unit configured to transfer an input signal applied to an input node to an output node in response to a control signal and a driving unit configured to drive an output signal of the output node to a level of the input signal in response to the control signal. 14-. (canceled)5. A signal transfer circuit comprising:a signal transfer unit configured to transfer an input signal applied to an input node to an output node in response to a control signal; anda driving unit configured to drive an output signal of the output node to a level of the input signal in response to the control signal,wherein the driving unit comprises:a pull-down driving section configured to pull down the output node when the input signal is at a logic low level in a period in which the control signal is activated.67-. (canceled)8. The signal transfer circuit of claim 5 , wherein the pull-down driving section comprises:a pull-down signal generation part configured to activate a pull-down signal when the input signal is at the logic low level in the period in which the control signal is activated; anda pull-down part configured to pull down the output node in a period in which the pull-down signal is activated.9. A flip-flop circuit comprising:a first pass gate configured to transfer an input signal applied to an input node to a first internal node in response to a control signal;a driving unit configured to drive a first signal of the first internal node to a level of the input signal in response to the control signal; anda signal output unit configured to store the first signal of the first internal node and invert the first signal of the first internal node to output an inverted signal to an output node in response to the control signal.10. The flip-flop circuit of claim 9 , wherein:the first pass gate is configured to transfer the input signal to the first internal node when the control signal is activated;the driving unit is configured to ...

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23-01-2014 дата публикации

TEMPERATURE-INSENSITIVE RING OSCILLATORS AND INVERTER CIRCUITS

Номер: US20140022023A1
Автор: HUANG Hsien-Sheng
Принадлежит:

A ring oscillator includes a plurality of stages of delay cells coupled in serial. At least one delay cell includes a first inverter. The first inverter includes an input node receiving an input signal, a first transistor coupled to a first supply voltage and the input node, a second transistor coupled to a second supply voltage and the input node, an output node coupled to the first transistor and the second transistor and outputting an output signal, and at least one resistive device coupled to the capacitor, the first transistor, and the second transistor. 1. A ring oscillator , comprising: an input node, receiving an input signal;', 'a first transistor, coupled to a first supply voltage and the input node;', 'a second transistor, coupled to a second supply voltage and the input node;', 'an output node, coupled to the first transistor and the second transistor and outputting an output signal; and', 'at least one resistive device, coupled to the capacitor, the first transistor, and the second transistor., 'a plurality of stages of delay cells coupled in serial, wherein at least one delay cell comprises a first inverter, and wherein the first inverter comprises2. The ring oscillator as claimed in claim 1 , wherein the first inverter further comprises a capacitor coupled between the output node and a third supply voltage.3. The ring oscillator as claimed in claim 1 , wherein the resistive device is disposed on a charge path from the first supply voltage to the capacitor or a discharge path from the capacitor to the second supply voltage.4. The ring oscillator as claimed in claim 1 , wherein the resistive device comprises at least a first resistor coupled between the output node and the first supply voltage and a second resistor coupled between the output node and the second supply voltage.5. The ring oscillator as claimed in claim 1 , wherein the resistive device comprises at least a resistor coupled between the output node and a connection node6. The ring ...

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30-01-2014 дата публикации

Low Supply Voltage Logic Circuit

Номер: US20140028346A1
Автор: Robert Kappel
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A low supply voltage logic circuit includes a first current source operable to generate a first current dependent on a first control signal and to generate a first leakage current. A second current source is operable to generate a second current dependent on a second control signal and to generate a second leakage current. A third current source has a third current path between the output terminal and the first supply voltage terminal and is operable to generate a third current through the third current path to compensate for the second leakage current. A fourth current source has a fourth current path between the output terminal and the second supply voltage terminal and is operable to generate a fourth current through the fourth current path to compensate for the first leakage current.

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30-01-2014 дата публикации

INPUT CIRCUIT

Номер: US20140028362A1
Принадлежит: Panasonic Corporation

A combination circuit generates first and second internal signals according to first and second input signals, respectively. A first master latch circuit selectively captures and holds a scan-in signal and the first internal signal, and generates a first output signal and a first intermediate signal based on the signals thus captured and held. A first slave latch circuit selectively captures and holds the first intermediate signal and the second internal signal, and generates a second output signal and a scan-out signal based on the signals thus captured and held. This arrangement reduces a circuit scale and power consumption of the input circuited provided in a semiconductor integrated circuit to which a scan path test method is applied. 1. An input circuit comprising:a combination circuit that generates first and second internal signals according to first and second input signals, respectively;a first master latch circuit that selectively captures and holds a scan-in signal and the first internal signal generated by the combination circuit, and generates a first output signal and a first intermediate signal based on the signals thus captured and held; anda first slave latch circuit that selectively captures and holds the first intermediate signal generated by the first master latch circuit and the second internal signal generated by the combination circuit, and generates a second output signal and a scan-out signal based on the signals thus captured and held.2. The input circuit according to claim 1 , further comprising:a second master latch circuit; anda second slave latch circuit,wherein the combination circuit further generates third and fourth internal signals according to the first and second input signals, respectively,the second master latch circuit receives the scan-out signal generated by the first slave latch circuit as a scan-in signal, selectively captures and holds the scan-in signal and the third internal signal generated by the combination circuit, ...

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13-02-2014 дата публикации

Integrated circuit having a multiplying injection-locked oscillator

Номер: US20140043105A1
Принадлежит: RAMBUS INC

Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

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20-02-2014 дата публикации

RING OSCILLATOR TIMER CIRCUIT

Номер: US20140049328A1
Принадлежит:

A ring oscillator timer circuit can include a plurality of electrical components arranged in a cascaded combination of delay stages connected in a closed loop chain. The timer circuit can begin oscillation a programmable number of gate delays after receiving a start signal. In some examples, the number of gate delays can be programmed to fractional values. In further examples, the ring oscillator timer circuit can include a counter having an input electrically coupled to an output of a reset component. 1. A phase-startable ring oscillator having an output at which is produced an oscillator signal , comprising:a first input receiving a start control signal to control the onset of oscillation from a static state; anda second input receiving control data that control the generation of a predetermined signal level at the output during the static state, and select an initial gate delay of the oscillator signal from a predetermined set of selectable initial gate delays;wherein, in response to the start signal, the oscillator continues to generate the predetermined signal level at the output for the selected gate delay time, and begins oscillation thereafter.2. The phase-startable ring oscillator of claim 1 , further comprising at least one inverting stage.3. The phase-startable ring oscillator of claim 2 , further comprising an odd number of inverting stages.4. The phase-startable ring oscillator of claim 1 , further comprising a plurality of NAND gates.5. The phase-startable ring oscillator of claim 1 , further comprising a plurality of NOR gates.6. The phase-startable ring oscillator of claim 1 , further comprising a first plurality of multiplexers.7. The phase-startable ring oscillator of claim 6 , further comprising a second plurality of multiplexers coupled with the first plurality of multiplexers.8. The phase-startable ring oscillator of claim 7 , wherein the second plurality of multiplexers are fractional multiplexers and the gate delay time has a fractional value. ...

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27-02-2014 дата публикации

Differential ring oscillation circuit, device, and oscillation control method

Номер: US20140055204A1
Принадлежит: Sony Corp

There is provided a differential ring oscillation circuit including a differential ring oscillation unit in which delay circuits, to which signals of 2 phases are input, and which delay and output the input signals of 2 phases, are connected at even stages in a ring form, first and second common-mode level detection units that detect that the input signals of 2 phases of one delay circuit at an even stage of the differential ring oscillation unit and the input signals of 2 phases of one delay circuit at an odd stage of the differential ring oscillation unit are at same predetermined levels, respectively, and first and second switches that set, to specific potentials, one of the output signals of 2 phases of the delay circuit delaying the input signals of 2 phases, when the first and second common-mode level detection units detect the same predetermined levels, respectively.

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06-03-2014 дата публикации

TEST SOLUTION FOR RING OSCILLATORS

Номер: US20140062606A1
Принадлежит:

A method and apparatus is disclosed herein for testing of multiple ring oscillators. In one embodiment, the apparatus comprises at least one ring oscillator structure having a ring oscillator having an inverter chain with an odd number of inverters connected back-to-back and operable to produce an oscillatory output, and a test structure coupled to provide either an observability chain input or a test input to the ring oscillator and to receive the oscillatory output as a feedback from the ring oscillator. 1. An apparatus comprising: a ring oscillator having an inverter chain with an odd number of inverters connected back-to-back and operable to produce an oscillatory output, and', 'a test structure coupled to provide either an observability chain input or a test input to the ring oscillator and to receive the oscillatory output as a feedback from the ring oscillator., 'at least one ring oscillator structure having'}2. The apparatus defined in wherein the test structure is operable to reconfigure the ring oscillator into a testable structure to allow one or more of a structural stuck-at test and a functional test of the ring oscillator.3. The apparatus defined in wherein the test structure is operable to validate whether the ring oscillator can produce an intended oscillating frequency within a specified jitter limit.4. The apparatus defined in wherein the at least one ring oscillator structure comprises a group of ring oscillator structures connected in a serial chain claim 1 , wherein a test output of a last of the ring oscillator test structures in the serial chain is fed back for use with the test input to a first ring oscillator structure in the chain.5. The apparatus defined in further comprising a gate to conditionally activate a feedback path to feed back the test output based on a feedback enable signal.6. The apparatus defined in further comprising an XOR gate to XOR the test output fed back from the last of the test structures with the test input.7. The ...

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13-03-2014 дата публикации

High Frequency Oscillator

Номер: US20140070893A1
Принадлежит: STMICROELECTRONICS SA

A frequency oscillator includes a ring oscillator having N inverters coupled in series, where N is an odd integer equal to three or more. A first filter is coupled between an output node of a first of the inverters and an output line of the frequency oscillator. A second filter is coupled between an output node of a second of the inverters and the output line of the frequency oscillator. 1. A frequency oscillator comprising:a ring oscillator having N inverters coupled in series, where N is an odd integer equal to three or more;a first filter coupled between an output node of a first of the inverters and an output line of the frequency oscillator; anda second filter coupled between an output node of a second of the inverters and the output line of the frequency oscillator.2. The frequency oscillator of claim 1 , wherein the first and second filters have cut-off frequencies selected based on the frequency of the Nth harmonic present at the outputs of the inverters.3. The frequency oscillator of claim 1 , wherein the first and second filters each have a lower cut-off frequency falling between the (N−2)th and the Nth harmonic present at the outputs of the inverters and a higher cut-off frequency falling between the Nth and (N+2)th harmonic present at the outputs of the inverters.4. The frequency oscillator of claim 1 , wherein the frequency oscillator further comprises a second ring oscillator formed of N inverters coupled in series claim 1 , wherein at least one line connecting a pair of inverters of the first ring oscillator is positioned to be electro-magnetically coupled to at least one line connecting a pair of inverters of the second ring oscillator.5. The frequency oscillator of claim 1 , wherein N is equal to 5 or 7.6. The frequency oscillator of claim 1 , wherein the first filter comprises a first inductor and the second filter comprises a second inductor.7. The frequency oscillator of claim 1 , wherein an output of at least one of the N inverters is coupled to ...

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20-03-2014 дата публикации

MASTER-SLAVE FLIP-FLOP CIRCUIT

Номер: US20140077855A1
Автор: SASAGAWA Ryuhei
Принадлежит:

A master-slave flip-flop circuit includes: a master circuit to receive input data in a first state of a reference clock and hold the input data in a second state of the reference clock to output intermediary data; and a slave circuit to receive the intermediary data in the second state and hold the intermediary data in the first state to output data, wherein the master circuit includes: a feedback two-input NOR gate to receive an output of the master circuit and a first clock; an input three-input NOR gate to receive the input data, a second clock, and a third clock; and a synthesis two-input NOR gate to receive an output of the input three-input NOR gate and an output of the feedback two-input NOR gate. 1. A master-slave flip-flop circuit comprising:a master circuit configured to receive input data in a first state of a reference clock and hold the input data in a second state of the reference clock to output intermediary data; anda slave circuit configured to receive the intermediary data in the second state of the reference clock and hold the intermediary data in the first state of the reference clock to output data,wherein the master circuit includes:a feedback two-input NOR gate configured to receive an output of the master circuit and a first clock obtained by delaying the reference clock by a first delay amount that is less than a second delay amount and then inverted;an input three-input NOR gate configured to receive the input data, a second clock obtained by delaying the reference clock by the second delay amount, and a third clock obtained by delaying the reference clock by a third delay amount that is greater than the second delay amount; anda synthesis two-input NOR gate configured to receive an output of the input three-input NOR gate and an output of the feedback two-input NOR gate.2. The master-slave flip-flop circuit according to claim 1 , wherein the input three-input NOR gate includes:a first PMOS transistor and a second PMOS transistor coupled in ...

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20-03-2014 дата публикации

Integrated circuit device and method for self-heating an integrated circuit device

Номер: US20140077856A1
Принадлежит: FREESCALE SEMICONDUCTOR INC

An integrated circuit device comprises a first clock signal source, arranged to provide at least one first clock signal; a second clock signal source, arranged to provide at least one second clock signal different from the at least one first clock signal; and a plurality of sequential logic cells, at least one of the plurality connected to receive, in a first mode, the at least one first clock signal or at least one clock signal derived from the at least one first clock signal, and to receive, in a second mode, the at least one second clock signal or at least one clock signal derived from the at least one second clock signal; wherein in the second mode the at least one second clock signal is adapted to the at least one of the plurality of sequential logic cells to generate in at least a portion of the integrated circuit device a current consumption when the at least one first clock signal is not a toggling signal.

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10-04-2014 дата публикации

Ring oscillator testing with power sensing resistor

Номер: US20140097858A1
Принадлежит: International Business Machines Corp

A test circuit for a ring oscillator comprising a plurality of inverting stages includes a power supply, the power supply configured to provide a voltage to the plurality of inverting stages of the ring oscillator at a power output; and a power sensing resistor located between the power output of the power supply and direct current (DC) bias inputs of the inverting stages of the ring oscillator, wherein a signal from the power sensing resistor is configured to be monitored to determine a characteristic of the ring oscillator.

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02-01-2020 дата публикации

FUNCTIONAL SAFETY POWER SUPPLY FRAMEWORK FOR REAL-TIME AUTOMOTIVE SYSTEMS

Номер: US20200001887A1
Принадлежит: Intel Corporation

A voltage monitoring framework is proposed to predict, report, and correct actions for performance impacting voltage droop due to power supplies in a system-on-a-chip. Both the amplitude and duration of the voltage droop are monitored. By predicting serious voltage droops early, power supplies cross check against each other to avoid catastrophic error, thus ensuring that integrated circuits making up the system-on-a-chip will maintain functional reliability. 1. A system-on-a-chip (SoC) to receive a reference voltage from a first external voltage supply and an input voltage from a second external voltage supply , the SoC comprising:a first voltage droop monitoring circuit to monitor the input voltage, the first voltage droop monitoring circuit to receive a second voltage as its reference voltage;a plurality of intellectual property (IP) units operable via the input voltage;a second voltage droop monitoring circuit to monitor the second voltage, the second voltage droop monitoring circuit comprising the input voltage as its reference voltage; anda power correction unit to adjust power to one or more of the plurality of IP units in response to an input voltage droop of the input voltage being predicted by the first voltage droop monitoring circuit.2. The SoC of claim 1 , further comprising a third voltage droop monitoring circuit to monitor a third voltage droop of a third voltage claim 1 , the third voltage droop comprising the input voltage as its reference voltage claim 1 , wherein the third voltage is to be generated inside the SoC.3. The SoC of claim 2 , further comprising sampling logic to measure a time duration of the input voltage droop claim 2 , the sampling logic comprising a plurality of flip-flops claim 2 , wherein an indication is sent to a safety engine in response to the input voltage droop.4. The SoC of claim 3 , wherein the safety engine is external to the SoC.5. The SoC of claim 4 , wherein the safety engine configures a system comprising the SoC ...

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06-01-2022 дата публикации

PREVENTING GLITCH PROPAGATION

Номер: US20220004864A1
Автор: Dally William James
Принадлежит:

When a signal glitches, logic receiving the signal may change in response, thereby charging and/or discharging nodes within the logic and dissipating power. Providing a glitch-free signal may reduce the number of times the nodes are charged and/or discharged, thereby reducing the power dissipation. A technique for eliminating glitches in a signal is to insert a storage element that samples the signal after it is done changing to produce a glitch-free output signal. The storage element is enabled by a “ready” signal having a delay that matches the delay of circuitry generating the signal. The technique prevents the output signal from changing until the final value of the signal is achieved. The output signal changes only once, typically reducing the number of times nodes in the logic receiving the signal are charged and/or discharged so that power dissipation is also reduced. 1. A circuit , comprising:a delay circuit configured to generate a ready signal that is negated at a first transition of a clock signal and asserted after a first delay relative to the first transition, wherein the first delay is at least as long as a second delay; and receive an input signal generated by combinational logic, wherein a change in a first signal received at an input of the combinational logic causes a corresponding change in the input signal at an output of the combinational logic after the second delay following the first transition of a clock signal; and', 'sample the input signal while the ready signal is asserted to transfer a level of the input signal to an output signal of the sampling circuit, wherein the input signal is unchanged from the second delay until the input signal is sampled., 'a sampling circuit configured to2. The circuit of claim 1 , wherein the sampling circuit is further configured to hold the output signal at a constant level from the first transition of the clock signal until the input signal is sampled.3. The circuit of claim 1 , wherein the sampling ...

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01-01-2015 дата публикации

SEMICONDUCTOR DEVICE SUPPRESSING BTI DETERIORATION

Номер: US20150003177A1
Автор: Fujishiro Keisuke
Принадлежит:

Disclosed herein is a device includes a command generation circuit that activates first and second command signals, an internal circuit that includes a plurality of transistors that are brought into a first operation state when at least one of the first and second command signals is activated, and an output gate circuit that receives a first signal output from the internal circuit, the output gate circuit being configured to pass the first signal when the second command signal is deactivated and to block the first signal when the second command signal is activated. 1. A semiconductor device comprising:a command generation circuit that activates first and second command signals;an internal circuit that includes a plurality of transistors that are brought into a first operation state when at least one of the first and second command signals is activated; andan output gate circuit that receives a first signal output from the internal circuit, the output gate circuit being configured to pass the first signal when the second command signal is deactivated and to block the first signal when the second command signal is activated.2. The semiconductor device as claimed in claim 1 , wherein the internal circuit is configured such that the plurality of transistors are brought into a second operation state different from the first operation state when both the first and second command signals are deactivated.3. The semiconductor device as claimed in claim 1 , further comprising a second control circuit claim 1 , whereinthe internal circuit and the output gate circuit constitute a first control circuit,the first control circuit is configured to perform a first control by outputting the first signal from the output gate circuit when the first command signal is activated, and not to perform the first control when the second command signal is activated, andthe second control circuit is configured to perform a second control different from the first control when the second command ...

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07-01-2016 дата публикации

SCAN CHAIN CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME

Номер: US20160003901A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A scan chain circuit includes first through N-th flip-flops connected in series to sequentially transfer data in response to a control signal, where N is an integer greater than 1. In the first through N-th flip-flops, the data are transferred in a first direction from the first flip-flop to the N-th flip-flop. The control signal is applied to the first through N-th flip-flops in a second direction opposite to the first direction from the N-th flip-flop to the first flip-flop. 1. A scan chain circuit comprising:first through N-th flip-flops connected in series to sequentially transfer data in response to a control signal, where N is an integer greater than 1,wherein, in the first through N-th flip-flops, the data are transferred in a first direction from the first flip-flop to the N-th flip-flop, andwherein the control signal is applied to the first through N-th flip-flops in a second direction opposite to the first direction from the N-th flip-flop to the first flip-flop.2. The scan chain circuit of claim 1 , wherein the control signal applied to an (M−1)-th flip-flop of the first through N-th flip-flops is delayed with respect to the control signal applied to an M-th flip-flop of the first through N-th flip-flops claim 1 , where M is an integer greater than 1 and less than or equal to N.3. The scan chain circuit of claim 2 , further comprising:a delay circuit configured to delay the control signal applied to the (M−1)-th flip-flop such that the control signal applied to the (M−1)-th flip-flop is delayed with respect to the control signal applied to the M-th flip-flop.4. The scan chain circuit of claim 1 , wherein the control signal is a clock signal claim 1 , andwherein a clock propagation direction of the scan chain circuit is the second direction opposite to the first direction in which the data are transferred.5. The scan chain circuit of claim 1 , further comprising:an input inverter configured to invert the control signal; andfirst through N-th inverters ...

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05-01-2017 дата публикации

Method and circuit for adjusting the frequency of a clock signal

Номер: US20170003708A1
Принадлежит: Inside Secure SA

In a general aspect, a method for adjusting an oscillator clock frequency can include applying a first control value to a first oscillator, applying a second control value, different from the first control value, to a second oscillator, measuring a frequency of each of the first and second oscillators, determining, by interpolation, a corrected frequency measurement of the second oscillator depending on a frequency deviation measured between the first and second oscillators when subjected to a third control value, on the third control value, and on the control value applied to the second oscillator, determining by interpolation a new first control value depending on the measured frequency of the first oscillator, on the corrected frequency, on the first and second control values, and on a desired frequency, and applying the new first control value to the first oscillator.

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02-01-2020 дата публикации

Electronic System, Sensing Circuit and Sensing Method

Номер: US20200003807A1
Принадлежит:

The present invention provides a sensing circuit, for sensing a working status of a real-time clock (RTC) module, comprising a comparator module, coupled to the real-time clock module, for receiving an initial voltage of the real-time clock module, and comparing the initial voltage with a threshold voltage, to generate a comparison result; and a storage module, coupled to the comparator module, for storing the comparison result and delivering the comparison result to a host circuit; wherein the host circuit determines whether the working status of the real-time clock module is normal or abnormal according to the comparison result. 1. A sensing circuit , for sensing a working status of a real-time clock (RTC) module , comprising:a comparator module, coupled to the real-time clock module, for receiving an initial voltage of the real-time clock module, and comparing the initial voltage with a threshold voltage, to generate a comparison result; anda storage module, coupled to the comparator module, for storing the comparison result and delivering the comparison result to a host circuit;wherein the host circuit determines whether the working status of the real-time clock module is normal or abnormal according to the comparison result.2. The sensing circuit of claim 1 , further comprising a low dropout regulator (LDO) claim 1 , coupled to the comparator module claim 1 , for providing the threshold voltage.3. The sensing circuit of claim 1 , wherein when the comparison result indicates that the initial voltage is greater than or equal to the threshold voltage claim 1 , the host circuit determines the working status of the real-time clock module to be normal; and when the comparison result indicates that the initial voltage is smaller than the threshold voltage claim 1 , the host circuit determines the working status of the real-time clock module to be abnormal.4. The sensing circuit of claim 1 , wherein the storage module is a D flip-flop claim 1 , and the comparison ...

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07-01-2021 дата публикации

Measurement apparatus

Номер: US20210003460A1
Принадлежит: Pragmatic Printing Ltd

Measurement apparatus, for generating a first output signal indicative of a measurand, comprises: a first oscillator circuit and a second oscillator circuit, each oscillator circuit being arranged to generate a respective oscillating output signal and comprising at least a respective first component having a property determining a respective output frequency of the respective oscillating output signal; a sensor for sensing said measurand, the sensor comprising said first component of the first oscillator circuit, said property of said first component of the first oscillator circuit being dependent upon said measurand; and circuitry arranged to receive said oscillating output signals and generate said first output signal, said first output signal being indicative of a number of cycles of one of the first and second oscillating output signals in a time period determined by a period of the other of said first and second oscillating output signals.

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07-01-2021 дата публикации

POWER GLITCH SIGNAL DETECTION CIRCUIT AND SECURITY CHIP

Номер: US20210003639A1
Автор: XUE Jianfeng, Yang Jiang
Принадлежит:

A power glitch signal detection circuit, a security chip and an electronic apparatus are disclosed. The power glitch signal detection circuit comprises: a latch and a signal output module, wherein a first input of the latch is connected to a power supply voltage, a first output of the latch is connected to a ground voltage, a second input of the latch is connected to a third output of the latch, a third input of the latch is connected to a second output of the latch, and the second output or the third output is connected to the signal output module. The power glitch signal detection circuit could detect a power glitch on the power supply voltage or the ground voltage, and the power glitch signal detection circuit has the advantages of low power consumption, small area, high speed, high sensitivity and strong portability. 1. A power glitch signal detection circuit , comprising:a latch and a signal output module,wherein a first input of the latch is connected to a power supply voltage, a first output of the latch is connected to a ground voltage, a second input of the latch is connected to a third output of the latch, a third input of the latch is connected to a second output of the latch, and the second output or the third output is connected to the signal output module;wherein when there is no power glitch signal on the power supply voltage and no power glitch signal on the ground voltage, the latch is configured to maintain a voltage value of the second input at a first voltage and maintain a voltage value of the third input at a second voltage, wherein the first voltage is greater or less than the second voltage;wherein the signal output module is configured to generate and output a target signal according to change of a voltage value of the third input, and the target signal is used to indicate whether there is a power glitch signal on the power supply voltage or the ground voltage.2. The power glitch signal detection circuit according to claim 1 , wherein when ...

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07-01-2021 дата публикации

POWER MANAGEMENT CIRCUIT AND METHOD FOR INTEGRATED CIRCUIT HAVING MULTIPLE POWER DOMAINS

Номер: US20210004030A1
Принадлежит:

A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit. 1. A power management circuit for an integrated circuit , the power management circuit comprising:an inverter circuit, having an inverter input terminal and an inverter output terminal, the inverter circuit being configured to receive a first control signal from the inverter input terminal and generate a second control signal at the inverter output terminal, the first control signal carrying power status information of a first supply voltage supplied to the integrated circuit; anda latch circuit, having a latch supply terminal, a first latch input terminal and a second latch input terminal, the latch supply terminal being coupled to a second supply voltage supplied to the integrated circuit, the second supply voltage becoming ready before the first supply voltage, the first latch input terminal being coupled to the inverter output terminal to receive the second control signal, the second latch input terminal being coupled to the inverter input terminal to receive the first control signal, the latch circuit being configured to generate a third ...

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07-01-2021 дата публикации

Phase synchronized lo generation

Номер: US20210004042A1
Принадлежит: MediaTek Inc

Aspects of the disclosure provide methods and apparatuses for generating an internal reset signal that is synchronous to a clock signal. In some embodiments, an apparatus includes a clock switch circuit and a plurality of serially coupled D flip-flops (DFFs). The clock switch circuit receiving the clock signal can output the clock signal in an on state and block the clock signal in an off state. The plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal. If an external reset signal is enabled, the plurality of serially coupled DFFs can enable the internal reset signal. If the external reset signal is disabled, after a predefined number of clock signal cycles, the plurality of serially coupled DFFs can disable the internal reset signal.

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03-01-2019 дата публикации

CLOCK GENERATOR

Номер: US20190004562A1
Принадлежит:

A clock generation circuit includes a delay chain configured to generate an N-number of clock signals at a frequency multiple that is M-times the frequency of a reference clock signal. To generate the clock signals at the frequency multiple, a multiplexer selectively inputs, to the delay chain, a delayed reference clock signal and a last clock signal generated by a last delay cell of the delay chain. In addition, a delay control generator circuit periodically compares the phases of the delayed reference clock signal and the last clock signal to set the delay of the delay chain. The clock generation circuit generates the N-number of clock signals at the frequency multiple in response to receipt of the reference clock signal, and continues to generate the clock signals at the frequency multiple when the reference clock signal is no longer being received. 1. A clock generation circuit comprising: alternatingly receive a delayed reference clock signal and a last clock signal output from the delay chain according to pulses of a select signal; and', 'generate a clock signal at a frequency multiple of a frequency of the delayed reference clock signal in response to alternating receipt of the delayed reference clock signal and the last clock signal., 'a delay chain configured to2. The clock generation circuit of claim 1 , wherein the delay chain comprises a first delay chain comprising an N-number of delay cells claim 1 , wherein the clock generation circuit further comprises:a second delay chain comprising an (N/2+1)-number of delay cells, wherein the second delay chain is configured to receive a reference clock signal and generate the delayed reference clock signal in response to receipt of the reference clock signal.3. The clock generation circuit of claim 1 , further comprising:a multiplexer configured to alternatingly output the delayed reference clock signal and the last clock signal output from the delay chain to a first delay cell of the delay chain according to the ...

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05-01-2017 дата публикации

ALL-OPTICAL PROTERETIC PHOTONIC INTEGRATED DEVICE

Номер: US20170005644A1

An apparatus and a method for a design and a simulation of an all-optical proteretic bi-stable device. The proteresis is a reversed hysteresis with an interesting characteristic which increases the oscillation frequency of a feed-back system with a relaxation dynamics by reducing the feed-back delay. The calculation of the bi-stable device parameters, a simulation of the theoretical device, and a simulation of the all-optical device are given. Applications of the proteretic device in ultra-high speed oscillations are also disclosed. 1. A Bi-Stable device comprising:an input of an inverting bi-stable device having a hysteretic threshold function, said input coupled to an output of a bi-stable device having a hysteretic threshold function.2. The Bi-Stable device as recited in claim 1 , where switching occurs before a threshold is reached in both an increasing and a decreasing direction of the input.3. The Bi-Stable device as recited in claim 2 , where the inverting bi-stable device having the hysteric function and the bi-stable device to which it is coupled are both bi-stable electronic semiconductor devices.4. The Bi-Stable device as recited in claim 2 , where the inverting bi-stable device having the hysteric function and the bi-stable device to which it is coupled are both bi-stable optical devices.5. The Bi-Stable device as recited in claim 2 , included as a switching device for an oscillator to thereby increase an oscillation rate of the oscillator without increasing an integration intrinsic speed of the oscillator.6. The Bi-Stable device as recited in claim 2 , included as a switching device for a delta-sigma modulator to thereby increase a modulation rate for the delta-sigma modulator.7. The Bi-Stable device as recited in claim 2 , included as a switching device for a stable dynamical system to thereby increase a relaxation rate without increasing an intrinsic rate.8. The Bi-Stable device as recited in claim 2 , included as a switching device for an artificial ...

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05-01-2017 дата публикации

EFFICIENT HIGH VOLTAGE SQUARE WAVE GENERATOR

Номер: US20170005646A1
Автор: Hargreaves Kirk
Принадлежит: SYNAPTICS INCORPORATED

This disclosure generally provides a system, active input device, and method for generating an amplified square wave signal based on an input signal. The method comprises generating a pulse signal based on the input signal, and driving a switching signal based on the pulse signal to control a first switch. A pulse width of the pulse signal is adaptively controlled using a control signal generated based on the amplified square wave signal. An output terminal of the first switch is coupled with a second switch, and the switching signal controls current entering into the second switch. The method further comprises driving the input signal to control a third switch coupled with the second switch. The amplified square wave signal is generated at the second output terminal based on the switching signal and on the input signal. 1. A system for generating an amplified square wave signal based on an input signal , the system comprising:a variable-width pulse generator configured to generate, based on the input signal, a pulse signal having a pulse width;a feedback module configured to generate a control signal based on the amplified square wave signal, the pulse width of the pulse signal based on the control signal;a first switch having a first control terminal and a first output terminal;a second switch having a second control terminal and a second output terminal, the second output terminal coupled with the first control terminal of the first switch, wherein the second switch is configured to receive at the second control terminal a first switching signal based on the pulse signal; anda third switch having a third control terminal and a third output terminal, the third output terminal coupled with the first output terminal of the first switch, wherein the third switch is configured to receive a second switching signal at the third control terminal,wherein in response to the first and second switching signals provided to the second and third switches, the amplified square ...

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05-01-2017 дата публикации

LOGIC CIRCUIT, PROCESSING UNIT, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE

Номер: US20170005658A1
Принадлежит:

A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor. 1. (canceled)2. A semiconductor device comprising:a first transistor, a second transistor, a third transistor, a capacitor, a selection circuit and a memory circuit,wherein a signal is input to one of a source and a drain of the first transistor,wherein the other of the source and the drain of the first transistor is electrically connected to a first input terminal of the selection circuit,wherein an output terminal of the selection circuit is electrically connected to an input terminal of the memory circuit,wherein one of a source and a drain of the second transistor is electrically connected to the output terminal of the memory circuit,wherein the other of the source and the drain of the second transistor is electrically connected to one terminal of the capacitor and one of a source and a drain of the third transistor,wherein the other of the source and the drain of the third transistor is electrically connected to the first input terminal of the selection circuit, andwherein the second transistor and the third transistor each comprise an oxide semiconductor layer in a channel formation region.3. The semiconductor device according to claim 2 ,wherein the first transistor comprises an oxide semiconductor layer in a channel formation region.4. ...

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04-01-2018 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR DEVICE

Номер: US20180005687A1
Автор: Kawabe Yukihito
Принадлежит: FUJITSU LIMITED

A semiconductor device includes an oscillator that oscillates to generate a clock, a circuit that operates based on the clock generated by the oscillator, a temperature detector that detects the temperature of the circuit, a power detector that acquires, as a monitored power value, power consumed by the circuit, and a frequency controller that controls, when the temperature detected by the temperature detector exceeds a temperature threshold, the frequency of the clock of the oscillator so that the monitored power value matches target power that causes the temperature of the circuit to converge to a temperature higher than the temperature threshold. 1. A semiconductor device comprising:an oscillator that oscillates to generate a clock;a circuit that operates based on the clock generated by the oscillator;a temperature detector that detects the temperature of the circuit;a power detector that acquires, as a monitored power value, power consumed by the circuit; anda frequency controller that controls, when the temperature detected by the temperature detector exceeds a temperature threshold, the frequency of the clock of the oscillator so that the monitored power value matches target power that causes the temperature of the circuit to converge to a temperature higher than the temperature threshold.2. The semiconductor device according to claim 1 ,wherein the frequency controller includesa power estimator that estimates, based on the monitored power value, a base power value corresponding to the temperature of the circuit when the temperature detected by the temperature detector matches the temperature threshold, anda frequency determiner that determines the frequency of the clock so that the target power is equal to or higher than the base power value and equal to or lower than the monitored power value acquired when the temperature detected by the temperature detector exceeds the temperature threshold.3. The semiconductor device according to claim 2 ,wherein the ...

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07-01-2016 дата публикации

QUADRATURE OUTPUT RING OSCILLATOR AND METHOD THEREOF

Номер: US20160006420A1
Автор: Lin Chia-Liang (Leon)
Принадлежит:

Various circuits are described, which sustain an oscillation using a combination of four primary inverters, four feedforward inverters, and four coupling resistors for outputting a quadrature output signal while avoiding contention between a primary inverter and a feedforward inverter. In one configuration, a circuit includes four primary inverters configured in a ring topology, four coupling resistors uniformly interposed in the ring among the four primary inverters, and four feedforward inverters forming four sub-feedback loops, respectively, each sub-feedback loop comprising two primary inverters, one coupling resistor, and one feedforward inverter. In a further embodiment, the circuit further comprises a voltage-to-current converter is for receiving a control voltage and outputting a supply current to the four primary inverters and the four feedforward inverters. A corresponding method is also provided. 1. A circuit comprising:four primary inverters configured in a ring topology;four coupling resistors uniformly disposed in the ring among the four primary inverters, wherein a coupling resistor is interposed between each successive primary inverter; andfour feedforward inverters forming four sub-feedback loops, respectively, each comprising two primary inverters, one coupling resistor, and one feedforward inverter, wherein each end of each of the four coupling resistors shares a connection with one of the four primary inverters and one of the four feedforward inverters.2. The circuit of further comprising a voltage-to-current converter receiving a control voltage and outputting a supply current to the four primary inverters and the four feedforward inverters.3. A method comprising:cascading four primary inverters in a ring topology;evenly inserting four coupling resistors among the four primary inverters in the ring; andinserting four feedforward inverters to the ring to form four three-inverter sub-feedback loops, each comprising two primary inverters, one ...

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07-01-2016 дата публикации

Frequency synthesiser circuit

Номер: US20160006421A1
Принадлежит: NXP BV

The invention relates to frequency synthesiser circuits, and in particular to frequency synthesiser circuits characterised by a small channel spacing. Embodiments disclosed include a frequency synthesiser circuit ( 100 ) for a radio receiver, the circuit comprising: a digitally controlled oscillator ( 118 ) configured to generate an output signal ( 128 ) with an output frequency on application of an oscillator enable signal ( 126 ); a delay module ( 160; 210 ) configured to delay an input reference signal ( 142 ) to generate a delayed reference signal ( 144; 244 ); and a duty cycle module ( 150 ) configured to modulate the oscillator enable signal based on a period of an input reference signal ( 142 ) and the delay of the delayed reference signal ( 144 ), such that a ratio between the output frequency and the frequency of the input reference signal ( 142 ) is a non-integer.

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02-01-2020 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Номер: US20200006384A1
Принадлежит:

A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided. 14-. (canceled)5. A semiconductor integrated circuit device formed on one chip comprising:a first functional block connected to a first power supply line and a second power supply line;a second functional block connected to the first power supply line and a third power supply line and communicating with the first functional block;a third functional block connected to the first power supply line and a fourth power supply line and communicating with the first functional block;a first power switch shutting down the first functional block from power supply via the second power supply line;a second power switch shutting down the second functional block from power supply via the third power supply line; anda third power switch shutting down the third functional block from power supply via the fourth power supply line,wherein the first functional block is shut down by the first power switch when the second and the third functional blocks are shut down.6. A semiconductor integrated circuit device according to claim 5 ,wherein the first functional block is laid out inside each of the second and third functional blocks.7. A semiconductor integrated circuit device according to claim 6 ,wherein the first power switch to shut down the first functional block in the second functional block and the first power switch to shut down the first functional block in the third functional block are provided independently.8. A ...

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07-01-2021 дата публикации

ACTIVE CLAMP CAPACITOR BALANCING

Номер: US20210006236A1
Принадлежит:

In some examples, a circuit includes an input circuit, an output circuit, an auxiliary circuit, and a balancing circuit. The input circuit comprises a primary capacitor coupled to primary windings of a transformer. The output circuit comprises a secondary capacitor coupled to secondary windings of the transformer, wherein the secondary windings are coupled to the primary windings. The auxiliary circuit comprises auxiliary windings coupled to the primary windings. The balancing circuit is coupled to the output circuit, the auxiliary circuit, and the input circuit. The balancing circuit is configured to balance a voltage across the primary capacitor with a voltage across the secondary capacitor. 1. A circuit , comprising:an input circuit comprising a primary capacitor coupled to primary windings of a transformer;an output circuit comprising a secondary capacitor coupled to secondary windings of the transformer, wherein the secondary windings are electromagnetically coupled to the primary windings;an auxiliary circuit comprising auxiliary windings electromagnetically coupled to the primary windings; anda balancing circuit coupled between the output circuit, the auxiliary circuit, and the input circuit, the balancing circuit configured to balance a voltage across the primary capacitor with a voltage across the secondary capacitor.2. The circuit of claim 1 , wherein the input circuit comprises:the primary capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to a first terminal of the primary windings and is configured to receive an input voltage;a first transistor coupled between the second terminal of the primary capacitor and a second terminal of the primary windings;a resistor;a second transistor coupled between the second terminal of the primary windings and a ground node through the resistor;a second capacitor; anda diode having an anode and a cathode, the anode coupled to the auxiliary circuit and the cathode coupled to the ...

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07-01-2021 дата публикации

IMMEDIATE FAIL DETECT CLOCK DOMAIN CROSSING SYNCHRONIZER

Номер: US20210006237A1
Автор: Goyal Avneep Kumar
Принадлежит:

A synchronizer circuit includes a first synchronizer having a first input for receiving a signal associated with a first clock signal, a second input for receiving a second clock signal, and an output for providing a synchronizer circuit output signal; a second synchronizer having a first input for receiving the signal associated with the first clock signal, a second input for receiving the second clock signal, and an output; a detection stage having a first input coupled to the output of the first synchronizer and to the output of the second synchronizer, a second input for receiving the second clock signal, and an output; and a fault output stage having a first input coupled to the detection stage, a second input for receiving the second clock signal, and an output for providing a fault output signal. 1. A synchronizer circuit comprising:a first synchronizer having a first input for receiving a signal associated with a first clock signal, a second input for receiving a second clock signal, and an output for providing a synchronizer circuit output signal;a second synchronizer having a first input for receiving the signal associated with the first clock signal, a second input for receiving the second clock signal, and an output;a detection stage having a first input coupled to the output of the first synchronizer and to the output of the second synchronizer, a second input for receiving the second clock signal, and an output; anda fault output stage having a first input coupled to the detection stage, a second input for receiving the second clock signal, and an output for providing a fault output signal.2. The synchronizer circuit of claim 1 , further comprising a flip-flop having an input for receiving the first clock signal claim 1 , and an output coupled to the first input of the first synchronizer and to the first input of the second synchronizer.3. The synchronizer circuit of claim 2 , wherein the first input of the first synchronizer and the first input of the ...

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02-01-2020 дата публикации

SPECTRALLY EFFICIENT DIGITAL LOGIC

Номер: US20200007113A1
Автор: Murphy Robert J.
Принадлежит:

Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for combinatorial or sequential logic elements and circuits. A SEDL circuit includes a multiplier circuit configured to receive a clock signal and provide a product of the input signal and a clock signal, an integrator circuit to integrate the product signal over a first portion of a clock period to determine the logic state of the input signal, a limit circuit configured to apply limits to a state result provided to the integrator circuit, and a pulse generator configured to receive the logic state from the limit circuit and provide and output signal having a Gaussian-shaped output pulse that represents that logic value corresponding to the logic value of the input signal. 1. In a circuit , a method to assess a state of an incoming bit , the method comprising:receiving an input signal;receiving a clock signal;obtaining a product signal from the product of the input and clock signals;integrating the product signal over a first portion of a clock period of the clock signal to determine a logic state of the input signal, the first portion of the clock period being less than the clock period of the clock signal;providing the determined logic state to a pulse generator; andproviding an output signal having a spectrally-efficient-shape at an output of the pulse generator, wherein the spectrally-efficient-shaped output signal represents a logic value corresponding to the logic value of the input signal.2. The method of claim 1 , wherein the first portion of the clock period of the clock signal over which the product signal is integrated is a first-half of the clock period of the clock signal and the output signal is output by the pulse generator over a second-half of the clock period of the clock signal.3. ...

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02-01-2020 дата публикации

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Номер: US20200007114A1
Принадлежит:

A semiconductor device that can perform product-sum operation with low power is provided. The semiconductor device includes a switching circuit. The switching circuit includes first to fourth terminals. The switching circuit has a function of selecting one of the third terminal and the fourth terminal as electrical connection destination of the first terminal, and selecting the other of the third terminal and the fourth terminal as electrical connection destination of the second terminal, on the basis of first data. The switching circuit includes a first transistor and a second transistor each having a back gate. The switching circuit has a function of determining a signal-transmission speed between the first terminal and one of the third terminal and the fourth terminal and a signal-transmission speed between the second terminal and the other of the third terminal and the fourth terminal on the basis of potentials of the back gates. The potentials are determined by second data. When signals are input to the first terminal and the second terminal, a time lag between the signals output from the third terminal and the fourth terminal is determined by the first data and the second data. 1. A semiconductor device comprising a first circuit , the first circuit comprising: a first transistor comprising a first gate and a second gate;', 'a second transistor comprising a third gate and a fourth gate; and', 'a first inverter circuit; and, 'a switching circuit comprisinga second inverter circuit, a third inverter circuit, and a fourth inverter circuit,wherein the first gate of the first transistor is electrically connected to an input terminal of the first inverter circuit,wherein the third gate of the second transistor is electrically connected to an output terminal of the first inverter circuit,wherein one of a source and a drain of the first transistor is electrically connected to an output terminal of the second inverter circuit,wherein one of a source and a drain of the ...

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02-01-2020 дата публикации

PULSE MODULATION CIRCUIT WITH HIGH-FREQUENCY-LIMITING FUNCTION

Номер: US20200007117A1
Автор: TANG Fang
Принадлежит: CHONGQING PAIXINRUWEI TECH CO., LTD.

A pulse modulation circuit with a high-frequency-limiting function, including a comparator, an RS trigger, a switching triode, a NAND gate, a NOR gate, and a charging capacitor. A capacitor charging time is controlled by adjusting a bias current IB a bias current IB a reference voltage V and a reference voltage V or adjusting values of capacitors C and C In this way, a highest output frequency of a pulse generator is limited, so as to reduce hardware system overheads. 1. A pulse modulation circuit with a high-frequency-limiting function , comprising: a first level output unit , a second level output unit , a first voltage comparator , an RS trigger , a NAND gate , and a NOR gate , whereinan output terminal of the first level output unit is connected to an input terminal of the RS trigger and an input terminal of the NOR gate, and an input terminal of the first level output unit is connected to an output terminal of the RS trigger;an output terminal of the second level output unit is connected to an input terminal of the NAND gate, and an input terminal of the second level output unit is connected to an other output terminal of the RS trigger and a voltage pulse frequency output terminal; and an other input terminal of the NAND gate is connected to an output terminal of the first voltage comparator, and an output terminal of the NAND gate is connected to an other input terminal of the NOR gate; andtwo input terminals of the first voltage comparator are connected to a first periodic input signal and a first reference signal, respectively.2. The pulse modulation circuit with the high-frequency-limiting function according to claim 1 , wherein the first level output unit comprises a first switching triode claim 1 , a first charging capacitor claim 1 , and a second voltage comparator;a gate electrode of the first switching triode is connected to an output terminal of the RS trigger, a drain electrode of the first switching triode is grounded, a source electrode of the ...

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02-01-2020 дата публикации

SOFT ERROR-RESILIENT LATCH

Номер: US20200007129A1
Принадлежит:

A latch is provided. The latch includes a plurality of storage nodes including a plurality of data storage nodes configured to store a data bit having one of two states and a plurality of complementary data storage nodes configured to store a complement of the data bit. The latch includes a plurality of supply voltage multi-dependency stages respectively corresponding to the plurality of storage nodes. Each supply voltage multi-dependency stage has an output coupled to a storage node and at least two control inputs respectively coupled to at least two other storage nodes of the plurality of storage nodes. The supply voltage multi-dependency stage is configured to cause a state of the data bit stored in the storage node to change from a first state to a second state in response a change in both states of two data bits respectively stored in the at least two other storage nodes. 1. A circuit , comprising: [ a plurality of data storage nodes each configured to store a data bit having one of two states including a first state and a second state; and', 'a plurality of complementary data storage nodes each configured to store a complement of the data bit; and, 'a plurality of storage nodes including, 'a plurality of first voltage multi-dependency stages respectively corresponding to the plurality of storage nodes, each first voltage multi-dependency stage having an output coupled to a respective storage node of the plurality of storage nodes and at least two control inputs respectively coupled to at least two other storage nodes of the plurality of storage nodes, the first voltage multi-dependency stage configured to cause the state of the data bit stored in the storage node to change from the second state to the first state in response to a change in both states of two data bits respectively stored in the at least two other storage nodes., 'a first latch including2. The circuit of claim 1 , wherein the first latch includes:a plurality of second voltage multi-dependency ...

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08-01-2015 дата публикации

DIGITAL CONTROLLED OSCILLATOR AND FREQUENCY VARIABLE OSCILLATOR

Номер: US20150008986A1
Автор: TERAZAWA Tomohito
Принадлежит:

A digital controlled oscillator includes: a delay circuit which includes m elements transmitting a pulse signal with delay; a timing signal generator generating a timing signal corresponding to timing-selection data from passing signals, based on the timing-selection data specifying any of timings which are obtained by dividing a circulation period of the pulse signal by m×n; and an output signal generator which sets the timing-selection data based on control data specifying a period of an output pulse signal and the timing-selection data, and generates the output pulse signal based on the timing-selection data by using the timing signal. The timing signal generator generates the timings obtained by dividing the circulation period by m×n by using pulse edge shift circuits which generate n shift signals whose timings differ by a unit delay from one input signal, the unit delay being 1/n of delay time in the element. 1. A digital controlled oscillator , comprising:a ring delay circuit which includes delay elements connected in ring shape, the number of the delay elements being m (m is an integer of 2 or more), and which transmits a pulse signal with delay;a timing signal generation section which generates a timing signal corresponding to timing selection data from passing signals outputted from the delay elements, in accordance with the timing selection data specifying any of timings which are obtained by dividing a circulation period of the pulse signal in the ring delay circuit by m×n (n is an integer of 2 or more); andan output signal generation section which sets the timing selection data based on control data specifying a period of an output pulse signal and the timing selection data every time when the output pulse signal is outputted, and generates the output pulse signal in accordance with the timing selection data by using the timing signal outputted from the timing signal generation section, whereinthe timing signal generation section generates the timings ...

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20-01-2022 дата публикации

METHOD, SYSTEM AND APPARATUS FOR CONSTANT, HIGH SWITCHING FREQUENCY AND NARROW DUTY RATIO PWM CONTROL OF DC-DC CONVERTERS AND ACCURATE PFM CONTROL AT LIGHT LOAD

Номер: US20220021305A1
Автор: Dearborn Scott, Ou Jiong
Принадлежит: MICROCHIP TECHNOLOGY INCORPORATED

DC-DC power converter control comprises current starved delay lines for phase shifting control signals that set and reset a RS flip-flop to provide controllable PWM pulse widths from narrow to wide at a clock frequency. Precise pulse width control and a guaranteed minimum pulse width for pulse frequency modulation (PFM) control the DC-DC power converter during low power demand is also provided. PFM control maintains the same pulse width while decreasing the number of pulses per second when the output voltage exceeds an upper value and increases the number of pulses per second when the output voltage is less than a lower value. Voltage-to-current converters provide control currents to the current starved delay lines that provide the control signals to the SET and RESET inputs of the RS flip-flop. A D-flip-flop may further be used to improved circuit operation when generating high duty cycle (>50 percent) pulse widths. 1. A method for controlling a DC-DC converter with a constant frequency pulse width modulation (PWM) controller , said method comprising the steps of:delaying a clock signal by a fixed time with a first delay line, wherein the first delay line provides a first delayed clock signal;delaying the clock signal by a variable time with a second delay line having adjustable time delay, wherein the second delay line provides a second delayed clock signal, and the delay of the second delayed clock signal is greater than the delay of the first delayed clock signal;providing a power switch controller for coupling to and controlling a power switch of a DC-DC converter, wherein the power switch controller has a first input coupled to the first delayed clock signal and a second input coupled to the second delayed clock signal; andproviding an error amplifier having a first input coupled to an output voltage of the DC-DC converter, a second input couple to a reference voltage, and an output for controlling the time delay of the second delayed clock signal from the ...

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12-01-2017 дата публикации

CLOCK SIGNAL GENERATION DEVICE AND MEMORY DEVICE INCLUDING THE SAME

Номер: US20170011806A1
Принадлежит:

A clock signal generation device includes a variable voltage providing circuit, a fixed voltage providing circuit and a clock signal generating circuit. The variable voltage providing circuit provides a variable reference voltage based on a selection signal, a reference voltage and a temperature coefficient. The variable reference voltage is varied according to temperature. The fixed voltage providing circuit provides a fixed reference voltage that is determined according to the selection signal. The fixed reference voltage is a constant voltage. The clock signal generating circuit provides a clock signal based on the fixed reference voltage and the variable reference voltage. The performance of the clock signal generation device may be increased by providing the clock signal based on the variable reference voltage that is varied according to the temperature and based on the fixed reference voltage. 1. A clock signal generation device comprising:a variable voltage providing circuit configured to provide a variable reference voltage based on a selection signal, a reference voltage and a temperature coefficient, the variable reference voltage being varied according to temperature;a fixed voltage providing circuit configured to provide a fixed reference voltage that is determined according to the selection signal, the fixed reference voltage being a constant voltage; anda clock signal generating circuit configured to provide a clock signal based on the fixed reference voltage and the variable reference voltage.2. The clock signal generation device of claim 1 , wherein the variable voltage providing circuit comprises:a voltage provider configured to provide a temperature-variable voltage and a temperature-fixed voltage, the temperature-variable voltage being varied according to the temperature, and the temperature-fixed voltage being fixed according to the temperature; anda voltage regulator configured to provide the variable reference voltage based on the temperature- ...

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12-01-2017 дата публикации

DOUBLE SAMPLING STATE RETENTION FLIP-FLOP

Номер: US20170012611A1
Принадлежит: NXP B.V.

Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling. 1. A flip-flop circuit , the flip-flop circuit comprising:a master latch;a slave latch connected to the master latch;a dual-function circuit connected to the master latch and the slave latch and configured to perform state retention and double sampling;a control circuit configured to generate a plurality of control signals for the flip-flop circuit based on a clock signal and a delayed version of the clock signal; andan error logic circuit configured to generate an error signal based on signals from the master latch, the dual-function circuit, and the control circuit.2. The flip-flop circuit of claim 1 , wherein the dual-function circuit comprises:a balloon latch connected to the slave latch and configured to perform state retention; anda shadow latch connected to the master latch and configured to perform double sampling.3. The flip-flop circuit of claim 2 , wherein the balloon latch comprises a first pair of inverters and a first switch configured to be controlled by a first pair of complementary signals.4. The flip-flop circuit of claim 3 , wherein the shadow latch comprises a second pair of inverters and a second switch configured to be controlled by a second pair of complementary signals.5. The flip-flop circuit of claim 2 , further comprising a plurality of switch circuits connected to an input terminal of the flip-flop circuit claim 2 , to the master latch claim 2 , to the slave latch claim 2 , to the balloon latch claim 2 , and to the shadow latch.6. (canceled)7. (canceled)8. The flip-flop circuit of claim 1 , wherein the dual-function circuit comprises a shared latch configured to perform state retention and double sampling ...

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15-01-2015 дата публикации

SPARE CELL STRATEGY USING FLIP-FLOP CELLS

Номер: US20150015317A1
Автор: Goh Beng-Heng
Принадлежит:

Configurable flip-flop cells for use in scan chain configurations include one or more multiplexers, a flip-flop, and one or more logic gates. The logic gates are configurable, through modification of different metallization or semiconductor layers, to operate as spare gates or to disable flip-flop cell outputs based selection signal switching between scan shift and capture mode. When disabling flip-flop cell outputs, the logic gates are configured to receive both a test signal and a data input signal and select one of the two to pass to the flip-flop based on the selection signal. When used as spare gates, the logic gates receive external inputs and provide spare gate outputs to circuitry on an integrated circuit that is external to the flip-flop cells. 1. An integrated circuit , comprising: a first multiplexer configured to receive a first data input, a first test input, and a selection signal and provide a first multiplexed output,', 'a first flip-flop configured to generate a first internal data signal based on the first multiplexed output and a clock signal, and', 'a first logic gate configured to generate a first flip-flop cell output in response to the first internal data signal and the selection signal, wherein said first flip-flop cell output is set to a fixed logic value if the selection signal is set to a first logic state and is permitted to change state in response to the first internal data signal if the selection signal is set to a second logic state; and, 'a first replicate flip-flop cell comprising a second multiplexer configured to receive a second data input, a second test input, and the selection signal and provide a second multiplexed output,', 'a second flip-flop configured to generate a second internal data signal based on the second multiplexed output and the clock signal, and', 'a spare logic gate configured to receive one or more inputs from circuitry external to the second replicate flip-flop cell and generate a spare gate output in ...

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11-01-2018 дата публикации

INTEGRATED CIRCUIT COMPRISING CIRCUITRY TO DETERMINE SETTINGS FOR AN INJECTION-LOCKED OSCILLATOR

Номер: US20180013438A1
Принадлежит: RAMBUS INC.

Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more 119-. (canceled)20. An integrated circuit (IC) , comprising:a first injection-locked oscillator (ILO) to generate a set of oscillating signals having different phases, wherein the first ILO has a natural oscillation frequency, and wherein the first ILO generates the set of oscillating signals based on a reference clock signal having a reference clock frequency;a time-to-digital (TDC) converter to generate a sequence of two or more codes based on the reference clock signal and the set of oscillating signals; anda control circuit to determine settings for the first ILO based on the sequence of two or more codes, wherein the settings correspond to the natural oscillation frequency being substantially equal to the reference clock frequency or an integral multiple of the reference clock frequency.21. The IC of claim 20 , wherein the settings for the ILO correspond to a delay setting for each delay element in the ILO.22. The IC of claim 20 , comprising a second ILO to generate an output clock signal based on the reference clock signal claim 20 , wherein the settings for the first ILO are provided to the second ILO.23. The IC of claim 22 , comprising ...

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10-01-2019 дата публикации

CIRCUIT FOR PROTECTING A POWER SWITCH

Номер: US20190013804A1
Принадлежит: STMICROELECTRONICS (ROUSSET) SAS

A protection circuit for a transistor switch coupled to a power supply rail operates to modulate a control voltage at a control terminal of the transistor switch. A first circuit detects an overload across the terminals of the switch with respect to a threshold to generate a signal which modulates the control voltage. A second circuit operates to adjust a value of the threshold in response to sensed variations in a supply voltage at the power supply rail. 1. A circuit for protecting a transistor switch coupled to a power supply rail , comprising:a first circuit configured to detect an overload across terminals of the transistor switch with respect to a first threshold; anda second circuit configured to adjust a value of the first threshold according to variations in a supply voltage at the power supply rail from a nominal voltage.2. The circuit according to claim 1 , wherein the second circuit comprises:a comparator configured to compare information representative of the supply voltage with at least a first level; anda first validation circuit configured to validate a result of the comparison made by the comparator over at least a first duration of time for a modulation of the value of the first threshold.3. The circuit according to claim 2 , wherein said first duration of time is longer than a duration of a transient variation in the supply voltage from the nominal voltage.4. The circuit according to claim 2 , wherein the second circuit further includes a second validation circuit configured to validate the result of the comparison over a second duration of time.5. The circuit according to claim 1 , wherein the nominal voltage is a nominal battery voltage.6. The circuit according to claim 1 , wherein the supply voltage is a DC battery voltage.7. A control circuit claim 1 , comprising:a transistor switch configured to control a load; and a first circuit configured to detect an overload across terminals of the transistor switch with respect to a first threshold; and ...

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14-01-2021 дата публикации

BUFFER CIRCUIT BETWEEN DIFFERENT VOLTAGE DOMAINS

Номер: US20210013873A1

A circuit includes a first inverter and a second inverter. The first inverter is coupled to an input terminal. The input terminal receives an input signal varying in a first voltage domain. The second inverter is coupled between the first inverter and an output terminal. The second inverter generating an output signal varying in a second voltage domain. The first inverter includes a first PMOS transistor and a first NMOS transistor. The first PMOS transistor is biased by a first input tracking signal generated from the input signal. The first input tracking signal varies in a third voltage domain. The first NMOS transistor is biased by a second input tracking signal generated from the input signal. The second input tracking signal varies in the second voltage domain. 1. A circuit , comprising:a first inverter, coupled to an input terminal, the input terminal receiving an input signal varying in a first voltage domain from a negative supply level to a first positive supply level; anda second inverter, coupled between the first inverter and an output terminal, the second inverter generating an output signal varying in a second voltage domain from the negative supply level to a second positive supply level, a first PMOS transistor biased by a first input tracking signal generated from the input signal, the first input tracking signal varies in a third voltage domain from a reference level to the first positive supply level, the reference level is higher than the negative supply level; and', 'a first NMOS transistor biased by a second input tracking signal generated from the input signal, the second input tracking signal varies in the second voltage domain., 'wherein the first inverter comprising2. The circuit of claim 1 , wherein a first voltage difference window of the first voltage domain is larger than a second voltage difference window of the second voltage domain claim 1 , and the first voltage difference window is larger than a third voltage difference window of ...

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14-01-2021 дата публикации

LOGIC FABRIC BASED ON MICROSECTOR INFRASTRUCTURE

Номер: US20210013885A1
Принадлежит:

Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. An n-bit data register (e.g., a 1-bit data register) and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described. 1. An integrated circuit , comprising:a plurality of microsectors arranged in a row and column grid, wherein the plurality of microsectors comprises a first microsesctor communicatively coupled to a first row controller; anda controller configured transmit a command and data from a second row controller to the first row controller, down a column of rows, wherein the first row controller is configured to perform an operation in response to the command using the data.2. The integrated circuit of claim 1 , wherein the plurality of microsectors comprises a second microsector disposed at a different position within the row and column grid than the first microsector claim 1 , wherein the row controller is configured to program the first microsector at least partially in parallel with the second microsector.3. The integrated circuit of claim 1 , wherein the plurality of microsectors comprises a second microsector disposed at a different row within the row and column grid than the first microsector claim 1 , and wherein the row controller is configured to program the second microsector at least partially in parallel with the first microsector.4. The integrated circuit of claim 1 , comprising a third row controller disposed below the first row controller claim 1 , wherein the third row controller and the first row controller are coupled to a shared data path claim 1 , and wherein the first ...

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14-01-2021 дата публикации

FREQUENCY SYNTHESIS DEVICE WITH FEEDBACK LOOP

Номер: US20210013890A1
Автор: LACHARTRE David
Принадлежит:

A frequency synthesis device includes a servo circuit for controlling an output frequency to an input reference frequency. The circuit includes a first phase accumulator clocked by the reference frequency, a phase comparison block, a loop filter and an oscillator. It further includes a feedback loop connecting the output to the comparison block, having a second phase accumulator clocked by the output frequency. The comparison block includes T phase comparators with logic gates receiving respectively T first logic signals from the servo circuit on T first inputs and T second logic signals from the feedback loop on T second inputs, the T first and second signals having logic levels that continuously depend on values provided by the first and second accumulators according to at least one multi-phase correspondence matrix. 1. A feedback-loop frequency synthesis device comprising:an input intended to receive an electrical signal oscillating at a reference frequency;an output intended to supply an electrical signal oscillating at an output frequency;a servo circuit for the control of the output frequency by the reference frequency, connecting the input to the output of the device and comprising a first phase accumulator clocked at a frequency linked to the reference frequency, a phase comparison block, a loop filter and a frequency controlled oscillator providing the electrical signal oscillating at the output frequency, the phase comparison block being linked to the loop filter for controlling said frequency controlled oscillator; anda feedback loop connecting the output to the phase comparison block, comprising a second phase accumulator clocked at a frequency linked to the output frequency, the first and second phase accumulators being adapted to provide the same number T of possible phase accumulation discrete values;wherein the servo circuit is configured to provide, to the phase comparison block T first distinct logic signals the logic levels of which depend ...

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09-01-2020 дата публикации

RC OSCILLATOR WATCHDOG CIRCUIT

Номер: US20200014372A1
Принадлежит: STMICROELECTRONICS INTERNATIONAL N.V.

An RC oscillator generates a periodic trigger signal, and a clock generator generates clock edges in response. A stuck-at-fault detection circuit detects a stuck-at-logic state of the periodic trigger signal and causes the RC oscillator to reset and causes a change in logic state of the periodic trigger signal. 1. A circuit , comprising: a first comparison circuit,', 'a second comparison circuit,', 'a logic circuit receiving output from the first and second comparison circuits as input, and generating a logic output signal, and', 'a clock generation circuit generating a clock signal as a function of the logic output signal; and, 'an RC oscillator comprising a capacitive node,', 'charge circuitry configured to selectively charge the capacitive node based upon the logic output signal,', 'discharge circuitry configured to selectively discharge the capacitive node based upon the logic output signal, and', 'triggering circuitry configured to assert a reset signal when the charge on the capacitive node indicates a fault with the RC oscillator., 'an oscillator fault detection circuit comprising2. The circuit of claim 1 , wherein the discharge circuitry fails to discharge the capacitive node to a lower threshold when the logic output signal transitions in a pattern indicating proper operation of the RC oscillator; and wherein the charge on the capacitive node being above the lower threshold indicates proper operation of the RC oscillator.3. The circuit of claim 1 , wherein the discharge circuitry begins to discharges the capacitive node to below a lower threshold when the logic output signal fails to transition in a pattern indicating proper operation of the RC oscillator; and wherein the charge on the capacitive node being below the lower threshold indicates a fault with the RC oscillator.4. The circuit of claim 1 , wherein the charge circuitry maintains the capacitive node above a lower threshold when the logic output signal transitions in a pattern indicating proper ...

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09-01-2020 дата публикации

SIGNAL TRANSFER DEVICE

Номер: US20200014375A1
Автор: ARIMURA Masahiko
Принадлежит: ROHM CO., LTD.

A pulse generation circuit has: an edge detector detecting a pulse edge in an input signal to generate edge detection signals; a clock generator generating a clock signal according to the edge detection signals; a frequency divider dividing the frequency of the clock signal to generate a frequency-divided clock signal; an input pad for receiving a test mode switch signal from a tester; and an output pad for outputting the frequency-divided clock signal to the tester. The edge detector can generate the edge detection signals by detecting a pulse edge not in the input signal but in the clock signal or in the inverted clock signal obtained by inverting the logic level of the clock signal when the test mode switch signal is being fed in. The signal delay time in the edge detector is adjustable according to the period of the frequency-divided clock signal as measured by the tester. 1. A pulse generation circuit comprising:an edge detector block configured to detect a pulse edge in an input signal to generate a first edge detection signal and a second edge detection signal;a clock generator block configured to generate a clock signal according to the first and second edge detection signals;a frequency divider block configured to divide a frequency of the clock signal to generate a frequency-divided clock signal;a test input pad configured to receive a test mode switch signal from a tester; anda test output pad configured to output the frequency-divided clock signal to the tester,whereinthe edge detector block is configured to have a function of generating the first and second edge detection signals by detecting a pulse edge not in the input signal but in the clock signal or in an inverted clock signal obtained by inverting a logic level of the clock signal when the test mode switch signal is being fed in, anda signal delay time in the edge detector block is adjustable according to a period of the frequency-divided clock signal as measured by the tester.2. The pulse ...

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09-01-2020 дата публикации

METHOD AND APPARATUS FOR NOISE INJECTION FOR PUF GENERATOR CHARACTERIZATION

Номер: US20200014547A1
Принадлежит:

Disclosed is a physical unclonable function generator circuit and method. In one embodiment, physical unclonable function (PUF) generator includes: a PUF cell array that comprises a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two access transistors, at least one enable transistor, and at least two storage nodes, wherein the at least two storage nodes are pre-configured with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state; a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to determine second logical states by turning on the at least one enable transistor and turning off the at least two access transistors of each of the plurality of bit cells, and based on the second logical states of the plurality of bit cells, to generate a PUF output; and a noise injector coupled to the PUF control circuit and the PUF cell array, wherein the noise injector is configured to create stressed operation conditions to evaluate stability of the plurality of bit cells. 1. A physical unclonable function (PUF) generator comprising:a PUF cell array that comprises a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two access transistors, at least one enable transistor, and at least two storage nodes, wherein the at least two storage nodes are pre-configured with substantially the same voltages allowing each of the plurality of bit cells having a first metastable logical state;a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to determine second logical states by turning on the at least one enable transistor and turning off the at least two access transistors of each of the plurality of bit cells, and based on the second logical states of the plurality of bit cells, to generate a ...

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03-02-2022 дата публикации

REGISTER CIRCUIT WITH DETECTION OF DATA EVENTS, AND METHOD FOR DETECTING DATA EVENTS IN A REGISTER CIRCUIT

Номер: US20220034964A1
Принадлежит: MINIMA PROCESSOR OY

A monitor circuit () for monitoring changes in an input digital value of a register circuit comprises a data input () configured to receive a copy of the input digital value of said register circuit, and one or more triggering signal inputs () configured to receive one or more triggering signals. One or more triggering edges thereof define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit. The monitor circuit comprises a data event (DE) output (), so that said monitor circuit is configured to produce a DE signal at said DE output () in response to a digital value at said data input () changing within a time window defined by said one or more triggering signals. 121-. (canceled)22. A monitor circuit for monitoring changes in an input digital value of a register circuit , the monitor circuit comprising:a data input configured to receive a copy of the in-put digital value of said register circuit, andone or more triggering signal inputs configured to receive one or more triggering signals, one or more triggering edges of which define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit, anda data event output, referred to below as DE output;wherein said monitor circuit is configured to produce a data event signal, referred to below as DE signal, at said DE output in response to a digital value at said data input changing within a time window defined by said one or more triggering signals.23. A monitor circuit according to claim 22 , comprising a timing event observation output claim 22 , referred to below as TEO output claim 22 , so that said monitor circuit is configured to produce a timing event observation signal claim 22 , referred to below as TEO signal claim 22 , at said TEO out-put in response to a digital value at said data input changing later than said ...

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19-01-2017 дата публикации

MULTI-BIT FLIP-FLOPS AND SCAN CHAIN CIRCUITS

Номер: US20170016955A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A multi-bit flip-flop includes a plurality of multi-bit flip-flop blocks that share a clock signal. Each of the multi-bit flip-flop blocks includes a single inverter and a plurality of flip-flops. The single inverter generates an inverted clock signal by inverting the clock signal. Each of the flip-flops includes a master latch part and a slave latch part and operates the master latch part and the slave latch part based on the clock signal and the inverted clock signal. Here, the flip-flops are triggered at rising edges of the clock signal. Thus, the multi-bit flip-flop operating as a master-slave flip-flop may minimize (or, reduce) power consumption occurring in a clock path through which the clock signal is transmitted. 120-. (canceled)21. A device comprising: a plurality of flip-flops, each of the plurality of flip-flops including a master latch and a slave latch, and', each of the plurality of flip-flops operates using the clock signal and the inverted clock signal,', 'each master latch included in the plurality of multi-bit flip-flop blocks directly receives the clock signal, and', 'each slave latch included in the plurality of multi-bit flip-flop blocks directly receives the clock signal., 'a single inverter configured to receive a clock signal and to generate an inverted clock signal, wherein'}], 'a plurality of multi-bit flip-flop blocks, each of the plurality of multi-bit flip-flop block including,'}22. The device of claim 21 , whereineach master latch included in the plurality of multi-bit flip-flop blocks directly receives the inverted clock signal, andeach slave latch included in the plurality of multi-bit flip-flop blocks directly receives the inverted clock signal.23. The device of claim 21 , whereineach master latch included in the plurality of multi-bit flip-flop blocks directly receives the clock signal that does not pass through the single inverter, andeach slave latch included in the plurality of multi-bit flip-flop blocks directly receives the ...

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18-01-2018 дата публикации

CHARGE PUMP APPARATUS

Номер: US20180019005A1
Автор: Shao Chi-Yi
Принадлежит: eMemory Technology Inc.

A charge pump apparatus is provided. A two-phase clock signal and a four-phase clock signal for respectively driving a two-phase charge pump circuit and a four-phase charge pump circuit are generated according to delay signals of coupling nodes between delay circuits of a ring oscillator circuit. 1. A charge pump apparatus , comprising:a first two-phase charge pump circuit and a first four-phase charge pump circuit coupled in series, wherein the first four-phase charge pump circuit coupled to an output terminal of the first two-phase charge pump circuit; and [ 'a plurality of delay circuits connected in series as a delay circuit chain, wherein an output terminal of the delay circuit chain is coupled to an input terminal of the delay circuit chain, and the input terminal of the delay circuit chain receives an input clock signal; and', 'a ring oscillator circuit, comprising, 'a logic circuit, coupled to the ring oscillator circuit, the first two-phase charge pump circuit and the first four-phase charge pump circuit, wherein the logic circuit generates a first two-phase clock signal for driving the first two-phase charge pump circuit and a first four-phase clock signal for driving the first four-phase charge pump circuit according to a plurality of delay signals of coupling a plurality of nodes between the delay circuits., 'a driving circuit, coupled to the first two-phase charge pump circuit and the first four-phase charge pump circuit, the driving circuit comprising2. The charge pump apparatus as claimed in claim 1 , wherein the delay circuit chain comprises a first delay circuit claim 1 , a second delay circuit and a third delay circuit connected in series claim 1 , the first delay circuit delays the input clock signal claim 1 , the second delay circuit delays an output signal of the first delay circuit claim 1 , the third delay circuit delays an output signal of the second delay circuit claim 1 , and the logic circuit generates the first two-phase clock signal ...

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19-01-2017 дата публикации

METHOD FOR DRIVING SEMICONDUCTOR DEVICE

Номер: US20170019117A1
Принадлежит:

A novel PLL is provided. An oscillator circuit includes first to n-th inverters, and first and second circuits. A first terminal of each of the first and second circuits is electrically connected to an output terminal of the i-th inverter. A second terminal of each of the first and second circuits is electrically connected to an input terminal of the (i+1)-th inverter. The first circuit has functions of storing first data, switching between electrically disconnecting the first terminal and the second terminal from each other and setting a resistance between the first terminal and the second terminal to a value based on the first data. The second circuit has functions of storing second data, switching between electrically disconnecting the first terminal and the second terminal from each other and setting a resistance between the first terminal and the second terminal to a value based on the second data. 1. A semiconductor device comprising:an oscillator circuit, the oscillator circuit comprising first to n-th inverters (n is an odd number greater than or equal to 3), a first circuit, and a second circuit;a frequency divider having an input electrically connected to an output of the oscillator circuit;a phase comparator having an input electrically connected to an output of the frequency divider;a loop filter having an input electrically connected to an output of the phase comparator, and an output electrically connected to an input of the oscillator circuit,wherein a first terminal of the first circuit is electrically connected to an output terminal of the i-th inverter (i is a number from 1 to (n−1)),wherein a second terminal of the first circuit is electrically connected to an input terminal of the (i+1)-th inverter,wherein a first terminal of the second circuit is electrically connected to the output terminal of the i-th inverter,wherein a second terminal of the second circuit is electrically connected to the input terminal of the (i+1)-th inverter,wherein the ...

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16-01-2020 дата публикации

VOLTAGE SENSING CIRCUIT

Номер: US20200018782A1
Принадлежит:

Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a Zener diode, a first current source, a first n-type field effect transistor (FET), a first inverter circuit, and a second current source. The Zener diode has a cathode coupled to a first node and an anode coupled to a second node. The first current source has a first terminal coupled to the second node and a second terminal coupled to a ground terminal. The first n-type FET has a gate terminal coupled to the second node, a source terminal coupled to the ground terminal, and a drain terminal coupled to a third node. The first inverter circuit has an input coupled to the third node and an output coupled to a fourth node. The second current source has a first terminal coupled to a fifth node and a second terminal coupled to the third node. 1. A circuit , comprising:a Zener diode having a cathode coupled to a first node and an anode coupled to a second node;a first current source having a first terminal coupled to the second node and a second terminal coupled to a ground terminal;a first n-type field effect transistor (FET) having a gate terminal coupled to the second node, a source terminal coupled to the ground terminal, and a drain terminal coupled to a third node;a first inverter circuit having an input coupled to the third node and an output coupled to a fourth node; anda second current source having a first terminal coupled to a fifth node and a second terminal coupled to the third node.2. The circuit of claim 1 , further comprising:a second inverter circuit having an input coupled to a sixth node and an output, where the sixth node is configured to receive a first control signal;a first pulse generator having an input coupled to the output of the second inverter circuit and an output;a second n-type FET having a gate terminal coupled to the output of the first pulse generator, a source terminal coupled to the ground terminal, and a drain terminal coupled to a seventh node ...

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17-01-2019 дата публикации

FINGERPRINT IDENTIFICATION SYSTEM

Номер: US20190019001A1
Принадлежит:

A fingerprint identification system includes: a fingerprint sensing circuit having a power supply terminal and a floating ground terminal, used for generating a first signal; and a signal generation circuit having a first output terminal and a second output terminal, wherein the first output terminal is coupled to the power supply terminal, and the second output terminal is coupled to the floating ground terminal, the signal generation circuit is used for generating a floating power signal to the power supply terminal according to the first signal, and for generating a floating ground signal to the floating ground terminal according to the first signal, wherein the floating power signal has a floating power amplitude, and the floating ground signal has a floating ground amplitude; and wherein the signal generation circuit has a breakdown voltage, and both the floating power amplitude and the floating ground amplitude are greater than the breakdown voltage. 1. A fingerprint identification system , comprising:a fingerprint sensing circuit, having a power supply terminal and a floating ground terminal, the fingerprint sensing circuit being used for generating a fingerprint signal and a first signal, wherein the fingerprint identification system identifies a fingerprint according to the fingerprint signal; anda signal generation circuit, having a first output terminal and a second output terminal, wherein the first output terminal is coupled to the power supply terminal, and the second output terminal is coupled to the floating ground terminal, and the signal generation circuit is used for generating a floating power signal to the power supply terminal according to the first signal, and for generating a floating ground signal to the floating ground terminal according to the first signal, wherein the floating power signal has a floating power amplitude, and the floating ground signal has a floating ground amplitude;wherein the signal generation circuit has a breakdown ...

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03-02-2022 дата публикации

Semiconductor device

Номер: US20220038054A1
Автор: Toshifumi Uemura
Принадлежит: Renesas Electronics Corp

A semiconductor device 1 includes: a first oscillator 11_RC1 configured to operate at a detected voltage, the first oscillator having first temperature dependency; a second oscillator 11_RC4 configured to operate at the detected voltage, the second oscillator having second temperature dependency; a count unit configured to count an output of the first oscillator and an output of the second oscillator, the output of the first oscillator and the output of the second oscillator being supplied to the count unit; an arithmetic unit configured to calculate a count value CNT (T1) of the first oscillator and a count value CNT (T4) of the second oscillator, the count values of the first and second oscillators being counted by the count unit; and a determining unit configured to compare an output of the arithmetic unit with a threshold value to output a detected result signal corresponding to a result of the comparison.

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03-02-2022 дата публикации

Multi-phase signal control circuit and method

Номер: US20220038082A1
Принадлежит: Huawei Technologies Co Ltd

A multi-phase signal control circuit includes: a comparator, configured to compare a triangular wave signal with a feedback control signal to output a first pulse width modulation signal, where the feedback control signal is a signal fed back by the power stage circuit; a phase switch circuit, configured to receive a phase switch signal and the first pulse width modulation signal to generate a first phase signal and a second phase signal, where the first phase signal and the second phase signal are used to control the power stage circuit to generate an output voltage signal.

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18-01-2018 дата публикации

Device And Method For Energy Harvesting Using A Self-Oscillating Power-On-Reset Start-Up Circuit With Auto-Disabling Function

Номер: US20180019661A1
Принадлежит:

Device and method for energy harvesting using a self-oscillating power-on reset start-up circuit. The device for energy harvesting comprises a start-up circuit for generating self-oscillation and initial boosting of an input voltage from an energy source during a start-up phase; a main boost circuit for boosting the input voltage during a steady state phase; a clock generator circuit for generating clock signals which control voltage boosting of the main boost circuit during the steady state phase; and a switching circuit coupled to the start-up circuit, the main boost circuit and the clock generator circuit for switching powering of the clock generator circuit between the start-up circuit and the main boost circuit such that the clock generator circuit is powered by only one of the start-up circuit and the main boost circuit at any point in time. 1. A device for energy harvesting , comprising:a start-up circuit for generating self-oscillation and initial boosting of an input voltage from an energy source during a start-up phase;a main boost circuit for boosting the input voltage during a steady state phase;a clock generator circuit for generating clock signals which control voltage boosting of the main boost circuit during the steady state phase; anda switching circuit coupled to the start-up circuit, the main boost circuit and the clock generator circuit for switching powering of the clock generator circuit between the start-up circuit and the main boost circuit such that the clock generator circuit is powered by only one of the start-up circuit and the main boost circuit at any point in time.2. The device in accordance with claim 1 , wherein the start-up circuit comprises:a power-on reset circuit for generating a sequence of pulses to control the self-oscillation of the start-up circuit;an auxiliary voltage boost circuit, coupled to the power-on reset circuit and an input of the start-up circuit, for boosting the input voltage of the start-up circuit;an inverter ...

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18-01-2018 дата публикации

INTEGRATED CIRCUIT COMPRISING FRACTIONAL CLOCK MULTIPLICATION CIRCUITRY

Номер: US20180019706A1
Принадлежит:

Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO. 120-. (canceled)21. An integrated circuit , comprising:a master clock generator comprising a ring oscillator, wherein the master clock generator outputs a first clock signal, and wherein an adjustment is made to a loop delay of the ring oscillator to maintain a substantially constant frequency multiplication ratio between the first clock signal and a reference clock signal; anda set of fractional clock multipliers, wherein each fractional clock multiplier comprises an injection-locked oscillator (ILO), wherein an adjustment is made to a loop delay of each ILO based on the adjustment that is made to the loop delay of the ring oscillator, and wherein each ILO generates a second clock signal based on the first clock signal.22. The integrated circuit of claim 21 , wherein the integrated circuit is a processor claim 21 , and wherein the second clock signal is provided to one of: an arithmetic logic unit claim 21 , a floating point unit claim 21 , or a memory load/store unit.23. The integrated circuit of claim 21 , wherein each fractional clock multiplier comprises:circuitry to generate an injection signal based on the first clock signal;circuitry to periodically select a different injection location in the ILO; andcircuitry to inject the injection signal into the selected injection location in the ILO.24. The integrated circuit of claim 23 , wherein the circuitry to periodically select the different injection location comprises:a plurality of gates, wherein an output of each gate is coupled to an injection location in the ILO; andcircuitry to ...

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18-01-2018 дата публикации

MULTI-LEVEL CLOCK GATE CONTROLS TO ADDRESS SCAN MODE POWER DROOP AND VOLTAGE BUMP REQUIREMENT

Номер: US20180019733A1
Принадлежит:

Embodiments described herein provide a method and apparatus for multi-level clock gate control for testing electronic devices. The method begins when the number of clock gate controls from root level to the last leaf level are identified and then ranked from the root to last leaf level. A number of test enable commands for testing at least one block of an electronic device are determined. These commands selectively connect and disconnect the test enable commands based on the ranked clock gate levels. The apparatus includes a chain of at least two uncompressed flip-flops with additional flip-flops added to provide multi-level clock gate control during testing. An OR gate in communication with each added flip-flop provides the logic functions to selectively connect and disconnect the test enable command A decompressor and a compressor is in communication with the chain of at flip-flops and the OR gates. 1. A method of multi-level clock gate control for testing electronic devices , comprising:identifying a number of clock gate levels from root level to last leaf level;ranking the clock gate levels from the root level to the last leaf level;determining a number of test enable commands for at least one test block of an electronic device;selectively connecting and disconnecting the test enable commands based on the ranked clock gate levels; andtesting the at least one test block of the electronic device.2. The method of claim 1 , wherein the number of test enable commands is based on a maximum number of flip-flops in a clock domain.3. The method of claim 1 , wherein the test enable commands are shared across multiple clock domains.4. The method of claim 1 , further comprising: tracing clock gates for connection and disconnection of the test enable commands based on the ranking of clock gate levels.5. The method of claim 4 , wherein a test enable command is set to a logic high to disconnect the test enable command for at least one test block.6. The method of claim 4 , ...

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18-01-2018 дата публикации

APPARATUS FOR DESIGN FOR TESTABILITY OF MULTIPORT REGISTER ARRAYS

Номер: US20180019734A1
Принадлежит:

In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port. 1. A register array comprising: a first set of master latches;', 'a first set of slave latches coupled to the first set of master latches; and', 'a first address port configured to select a subset of the first set of slave latches to function with the first set of master latches;, 'a first flip-flop latch array including a second set of master latches;', 'a second set of slave latches coupled to the second set of master latches; and', 'a second address port configured to select a subset of the second set of slave latches to function with the second set of master latches, the second address port being different than the first address port; and', 'an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array, the address counter shared by the first flip-flop latch array and the second flip-flop latch array and configurable to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port., 'a second flip-flop latch array ...

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18-01-2018 дата публикации

PASSIVE PHASED INJECTION LOCKED CIRCUIT

Номер: US20180019757A1
Принадлежит: Circuit Seed, LLC

The present invention relates to passive phased injection locked circuit and ring-based voltage controlled oscillators. passive phased injection locked circuit comprises first and second transmission lines, each has a plurality of discrete elements, that are operative to deley the phase of AC signal. Between the first and second transmission lines, a capacitor network is formed to advance the phases of the AC signal in concert along the transmission lines. For the ring-based voltage controlled oscillators, each of the first and second transmission lines has an odd number of discrete elements. 1. A passive phased injection locked circuit comprising: 1) an input and an output; and', '2) said discrete elements connected electrically in series between said input and said output, each of said discrete elements being operative to delay the phase of AC signal applied to said input;, 'i. each of said first and second transmission lines comprising'}, 'a. first and second transmission lines, said first transmission line comprises a plurality of discrete elements, and said second transmission line comprises a corresponding number of discrete elements to the first transmission line;'}b. a plurality of capacitors, each of said capacitors being connected between an output of one of the elements in said first or second transmission line to the input of the next higher corresponding one of the elements in the other transmission line to form a network between said first and second transmission lines, said network being operative to advance the phases of said applied AC signal in concert along said transmission line.2. A circuit as in wherein said discrete elements comprise an odd number of inverter elements in each of said lines.3. A circuit as in wherein said discrete elements are lumped LC delay elements.4. A circuit as in wherein said discrete elements are inverting circuits5. A voltage controlled oscillator comprising first and second ring oscillators claim 1 , said first ring ...

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17-01-2019 дата публикации

APPARATUSES AND METHODS FOR PROVIDING AN INDICATOR OF OPERATIONAL READINESS OF VARIOUS CIRCUITS OF A SEMICONDUCTOR DEVICE FOLLOWING POWER UP

Номер: US20190019543A1
Автор: Ma Yantao
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods for providing an indicator of operational readiness of various circuits of a semiconductor device following power up are described in the present disclosure. An example apparatus includes a first circuit configured to receive a supply voltage and further configured to provide an active first signal responsive to the supply voltage exceeding a threshold voltage. The example apparatus further includes a second circuit coupled to the first circuit and activated by the active first signal, the second circuit configured to provide an active second signal when a third circuit is ready for operation. 1. An apparatus , comprising:an oscillator circuit configured to receive an activation signal and provide an oscillating signal based on the received activation signal;a timing circuit coupled to the oscillator circuit and configured to provide an oscillating data signal based at least in part on the oscillating signal; anda flip flop circuit coupled to the timing circuit and configured to latch a logic level of the oscillating data signal and provide an output signal to the oscillator circuit having a logic level based at least in part on the latched logic level.2. The apparatus of claim 1 , wherein the flip flop circuit is a model circuit configured to model other flip flop circuits.3. The apparatus of claim 1 , wherein at least one other flip flop circuit is enabled based on the output signal of the flip flop circuit.4. The apparatus of claim 1 , further comprising:a plurality of other flip flop circuits configured to be enabled,wherein the flip flop circuit is a model circuit, andwherein operation of the plurality of other flip flop circuits is responsive to operation of the model circuit.5. The apparatus of claim 4 , wherein the plurality of other flip flop circuits are configured to be enabled for operation responsive to a change in the logic level of the output signal of the model circuit.6. The apparatus of claim 1 , further comprising:a ...

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