СПОСОБ И СХЕМА УПРАВЛЕНИЯ СИСТЕМОЙ ФАЗОВОЙ АВТОПОДСТРОЙКИ ЧАСТОТЫ С ЦИФРОВОЙ ОБРАБОТКОЙ ДЛЯ СЕТЕВОЙСИНХРОНИЗАЦИИ

Изобретение раскрывает управляющий алгоритм системы фазовой автоподстройки частоты с цифровой обработкой (ЦФАПЧ) для сетевой синхронизации для обеспечения технического результата, заключающегося в предотвращении фазового скачка, вырабатываемого во время изменения рабочего режима. Этот алгоритм предусматривает в случае, если и один и другой опорные тактовые сигналы аномальны, преобразование быстрого или нормального режима в режим удержания, без изменения заранее заданной опорной величины девиации фазы, при восстановлении нормального отслеживания тактового сигнала в режиме удержания, в качестве опорной величины девиации фазы используют значение, полученное путем вычитания среднего значения данных девиации фазы в режиме удержания из среднего значения данных девиации фазы для заранее заданного промежутка времени после преобразования из режима удержания в быстрый режим. 2 с. и 5 з.п. ф-лы, 7 ил.

ЦИФРОВОЙ ИЗМЕРИТЕЛЬ СДВИГА ФАЗ ГАРМОНИЧЕСКИХ СИГНАЛОВ

Изобретение относится к областям радиотехники и измерительной техники и может быть использовано в устройствах измерения сдвига фаз между двумя гармоническими колебаниями в измерительной и радиотехнической аппаратуре управления и передачи информации. Технический результат - обеспечение измерения сдвига фаз между двумя входными гармоническими сигналами, которое производится во всем возможном диапазоне его изменения, с высокой точностью и максимальной скоростью формирования искомого результата. Цифровой измеритель сдвига фаз содержит аналого-цифровой преобразователь, регистр сдвига многоразрядных кодов на четыре отсчета, первый и второй каналы квадратурной обработки (ККО), каждый ККО содержит каскадно соединенные вычитатель и nблоков накопления отсчетов (БНО), каждый БНО состоит из регистра сдвига многоразрядных кодов и сумматора, нормирующее устройство, цифровой формирователь арктангенса, регистр результата, формирователь тактовых импульсов и распределитель тактовых импульсов. 2 з.п. ф-лы ...

СИНТЕЗАТОР ЧАСТОТ

Изобретение относится к радиоэлектронике, в частности к синтезаторам частот на основе петли фазовой автоподстройки частоты (ФАПЧ). Технический результат заключается в снижении уровня фазовых шумов и побочных дискретных составляющих в спектре выходного сигнала, что в свою очередь повышает качество выходного сигнала, при сохранении высокого разрешения по частоте и широкой полосы перестройки. Синтезатор частот содержит соединенные последовательно умножитель частоты входного сигнала, делитель с фиксированным коэффициентом деления, первую микросхему прямого цифрового синтеза, фазочастотный детектор, первый фильтр низких частот, генератор, управляемый напряжением, контур отрицательной обратной связи, включающий в себя соединенные последовательно смеситель, один из входов которого соединен с выходом генератора, управляемого напряжением, а второй вход соединен с выходом умножителя частоты входного сигнала, второй фильтр низких частот и вторую микросхему прямого цифрового синтеза, выход которой ...

DIGITAL ANALOG WANDLUNG ZUM STEUERN EINES OSZILLATORS IN EINEM PHASENREGELKREIS

Synchronisierungsschaltung mit einem schnellen digitalen Schlupffrequenzzähler

Frequenz-Phasenwandler mit gleichförmiger Abtastung für volldigitale Phasenregelschleifen

Die vorliegende Offenbarung betrifft Systeme und Verfahren zur Frequenz-Phasenwandlung unter Verwendung gleichförmiger Abtastung, wobei eine gleichförmige bzw. konstante Taktperiode benutzt wird.

System und Verfahren zur Beseitigung des Verstärkungsfehlers eines Phasendetektors bei der Taktrückgewinnung verursacht durch eine datenabhängig variierende Anzahl von Flankenwechseln

PLL-Schaltung und Frequenzteilungsverfahren zum Reduzieren von Störrauschen

Eine Phasenverriegelte Schleifen-(PLL)-Schaltung, die eine Bruchteilung durchgeführt, umfasst eine Phasenkomparatorschaltung, eine Phasendifferenzsignalmodulationsschaltung und eine Oszillatorschaltung. Die Phasenkomparatorschaltung vergleicht Phasen von zwei Signalen und gibt erst und zweite Phasendifferenzsignale aus. Die Phasendifferenzsignalmodulationsschaltung moduliert die zweiten Phasendifferenzsignale in dritte Phasendifferenzsignale und die Oszillatorschaltung oszilliert, basierend auf den ersten und dritten Signalen.

Systemtaktsynchronisation unter Verwendung eines Phasenregelkreises

Es wird eine Vorrichtung zur Synchronisierung der Systemtakte von drahtlosen Geräten in einem digitalen Kommunikationssystem präsentiert. Es wird ein digitaler Phasenregelkreis verwendet. Der Phasenregelkreis kann einen Zähler beinhalten, der durch einen lokalen Gerätesystemtakt inkrementiert und von einer Rahmensynchronisationsmarkierung zwischengespeichert wird, die von einem entfernt gelegenen Gerät empfangen wird, wobei der Zählerausgang ein Vorwärtssteuersignal beinhaltet. Der Phasenregelkreis kann alternativ einen Zähler beinhalten, der den Pegel von Daten widerspiegelt, die in Empfangs- und/oder Sende-FIFO-Puffern gespeichert sind. Das Schleifenausgangssignal steuert die Frequenz des Systemtaktoszillators.

Vorrichtung mit digital gesteuertem Oszillator

Verfahren zum Steuern eines digital gesteuerten Oszillators (DCO), umfassend:Erzeugen eines Oszillatorsteuersignals (DATA; DATAF) mit einer ersten Rate,Einspeisen des Oszillatorsteuersignals (DATA; DATAF) in einen digital gesteuerten Oszillator (DCO) mit einer zweiten Rate,Betreiben einer Zählereinheit (CU) mit einer Schwingungsrate des digital gesteuerten Oszillators (DCO), die auf dem Oszillatorsteuersignal (DATA; DATAF) beruht,Bestimmen von Zählerwerten der Zählereinheit (CU) mit der ersten Rate, undEinstellen der zweiten Rate entsprechend den Zählerwerten der Zählereinheit (CU).

System und Verfahren für einen spannungsgesteuerten Oszillator

Gemäß einer Ausführungsform umfasst ein spannungsgesteuerter Oszillator (VCO) einen VCO-Kern, der eine Vielzahl von Transistoren und eine Varaktorschaltung aufweist, die ein mit Emitteranschlüssen des VCO-Kerns gekoppeltes erstes Ende und ein mit einem Abstimmanschluss gekoppeltes zweites Ende aufweist. Die Varaktorschaltung umfasst eine Kapazität, die mit steigender am Abstimmanschluss angelegter Spannung in Bezug auf die Emitteranschlüsse des VCO-Kerns steigt.

Rectangular clock pulse generator - includes cct for phase synchronisation and comparison with control pulse train

The rectangular clock pulse generator frequency is compared with an external control clock pulse train and the positive or negative phase difference is used for the frequency control in the correct sense. A criterion for phase shift at the beginning or end of the compared pulses or observed over a certain period, is digitally stored by switches reacting to this criterion during a pulse period, or during the above longer period when the criterion repeatedly occurs. The switch is connected to the generator frequency control input. In order to determine the phase shift criterion, instants of both pulse beginning and end are determined for the digital storage process.

PLL-Schaltung mit reduzierter Einschwingzeit

PHASENREGELSCHLEIFE

Digitaler Phasendetektor

Gemäß einem Beispiel wird ein digitaler Phasendetektor zur Verwendung mit einem Phasenregelkreis offenbart. Der digitale Phasendetektor ist so konfiguriert, dass er in einer Niederfrequenzumgebung funktioniert und Rausch und Transienten in einem Signal filtert, während er außerdem gegenüber verworfenen Phasenimpulsen tolerant ist. In einigen Ausführungsformen ist der digitale Phasendetektor so konfiguriert, dass er bis zu zwei REFCLK-Flanken in Bezug auf ein FBCLK-Signal misst und eine Flanke als nacheilend klassifiziert, wenn die Flanke in der ersten Hälfte von REFCLK auftritt, und eine Flanke als voreilend klassifiziert, wenn die Flanke in der zweiten Hälfte von REFCLK auftritt. Wenn beiden Flanken voreilend oder beide nacheilend sind, wird die kleinere der beiden als die Phase verwendet. Wenn eine voreilend ist und eine nacheilend ist, wird die Differenz als die Phase verwendet.

VERFAHREN UND VORRICHTUNG ZUR BESTIMMUNG DER FREQUENZ EINER SIGNALKOMPONENTE IN EINEM ZUSAMMENGESETZTEN SIGNAL

Verfahren und Einrichtung zur Neutaktung eines asynchronen Takts

Digitale Phasenregelschleife

Unterdrückung von niederfrequentem Rauschen von einem Phasendetektor in einer Phasensteuerschleife

Die offenbarte Erfindung schafft eine Struktur und ein Verfahren zum Verbessern der Leistungsfähigkeit einer Phasenregelschleife durch Unterdrücken von niederfrequentem Rauschen, das durch einen Phasendetektor erzeugt wird. Dies wird erreicht durch Aufwärtswandlung der In-Band-Frequenzkomponenten in der Phasendifferenz zwischen Referenzsignal und Rückkopplungssignal zu einem höheren Frequenzbereich, wo eine Rauschleistungsfähigkeit eines Phasendetektors verbessert ist. Die aufwärts gewandelte Phasendifferenz wird an einen Phasendetektor geliefert, der konfiguriert ist, um basierend auf dieser Phasendifferenz ein Fehlersignal zu bestimmen. Das Fehlersignal wird an einen Abwärtswandler ausgegeben, der konfiguriert ist, um das Fehlersignal abwärts zu wandeln (z. B. zurück zu dem ursprünglichen Frequenzbereich), wodurch eigentlich das niederfrequente Rauschen des Fehlersignals (erzeugt durch den Phasendetektor) aufwärts gewandelt wird, bevor dasselbe an ein Filter geliefert wird, das konfiguriert ...

PHASENVERGLEICHSSCHALTUNG ZUR ERZEUGUNG EINER REGELSPANNUNG ZUR SYNCHRONISIERUNG EINES OSZILLATORS

Phase detector and phase locked loop

Frequency and phase acquisition of a clock and data recovery circuit without an external reference clock

Phase- locked loop

CLOCK GENERATOR FOR DIGITAL DEMODULATORS

Clock recovery circuits

In the case of sending the sampled clock of transmission coded data together with the coded data and regenerating a clock synchronized with this sampled clock on the receiver side, the drawing-in or locking is speeded up on the received side for the clock information items SCRn sent at unequal intervals. In the case of generating a control voltage of the vco 5 in accordance with the received SCRn and the SCCn by the counter 6, a CPU 11 calculates the amount of frequency deviation per unit time and generates a control voltage in accordance with this amount of deviation. Thereby, even if SCRn are received at unequal intervals, a rapid follow-up control of the PLL loop including the vco becomes possible. A separator 1 separates the received signal into system clock reference information SCR 106 and coded data 105. The CPU applies an initial value to a counter 6 counting oscillations from vco 6. The counter output SCCn is applied to a flipflop 7 and a latched output is applied to the CPU 11 ...

Clock recovery PLL

Phase Detector and Phase Locked Loop

A phase detector is provided, suitable for use in a phase locked loop (PLL) in a frequency synthesizer. The phase detector comprises a phase-frequency detector (2) providing output pulses (UP, DN), whose widths represent the relative frequencies and phases of input signals (FREF, Fvco). The output pulses are supplied to a pulse width to current converter (15, 16), which continuously supplies a direct output current to the output (VCO control) of the phase detector. The direct output current is a continuous monotonic function of the pulse width of the pulses (UP, DN) from the phase-frequency detector (2). The converter (15, 16) may include integrators for integrating the UP and DN pulses and transconductance amplifier circuits for supply the continuous output current (fig.7). The continuously-variable, continuous output current removes the frequency modulation effect of a varying VCO control voltage. Frequency spurs resulting from such modulation are thereby substantially eliminated.

IMPROVEMENTS IN OR RELATING TO STANDBY POWER SUPPLY SYSTEMS

... 1,214,646. Converting; stand-by power supplies. PLESSEY CO. Ltd. 4 Oct., 1968 [13 Oct., 1967], No. 46728/67. Headings H2F and H2H. [Also in Division H3] In an emergency stand-by power supply system, Fig. 6, an inverter 26 is locked in phase quadrature with the mains input whereby it supplies no power to load 31 under normal conditions and takes over with no break in the event of a power failure. Thyristors 32 prevent power being fed back to the mains input. The inverter may have its frequency controlled by a unijunction transistor relaxation oscillator, Fig. 3 (not shown), the feedback signal adjusting the " aiming " potential of a CR circuit. In the phase locking system, Fig. 2, the inverter 4 is phase controlled by comparing its output with a reference signal to produce an error signal dependent on the phase difference, and combining the error signal with a control signal to produce a phase correction signal which controls the generator such that it is phase locked to the reference signal ...

TIMING RECOVERY CIRCUITS

PHASE-LOCKED LOOP WITH SAMPLED-DATA LOOP FILTER

A phase-locked loop (PLL) circuit, manufacturable using standard integrated circuit technology, includes a sampled-data phase detector, a sampled-data loop filter for filtering the output of the phase detetector, a voltage controlled oscillator driven by the output of the loop filter, and a frequency divider in the feedback loop. A clock circuit generates reference signals needed by the other circuit components. The sampled-data phase detector, under the control of two clocks of differing frequencies, derives a phase error signal through the use of discrete-time analog integration of its input signal. When the PLL is in lock, this phase detector outputs valid phase error signal at discrete time intervals. The gain of the phase detector is proportional to a ratio of capacitor values, a ratio of frequencies, and a reference voltage, all of which can be made substantially independent of variations in temperature and semiconductor processing. A separate frequency acquisition circuit is used ...

Digital phase control circuit for controlling phase error

A digital phase control circuit 20 for controlling a phase error between a phase of an output signal of an oscillating circuit and a phase of a reference signal. A pulse cycle of the output signal is changed in response to a control input value S. The digital phase control circuit comprises a phase comparator 21 for judging an advance/delay of a phase of the output signal, and a counter circuit 22 for counting up or down according to a judgement of the phase comparator circuit 21 and for changing a count, when that judgement has been reversed, to approximately a mean value of the counts made during the successive same judgements, this count being used as the control input value S.

Phase locked loops

In the disclosed digital PLL, a phase/frequency detector 101 receives a reference signal CKref and a feedback signal SFB, and produces adjustment signals U and D respectively indicating a requirement to increase or decrease the frequency of numerically-controlled oscillator 204. The U and D signals are pulse signals modulated between two levels. First and second time-to-digital converters 201-1 and 201-2 respectively receive the U and D pulses and produce respective digital output signals indicative of the duration of the pulses. Each time-to-digital converter comprises a controlled oscillator (fig.4:401) and a counter (fig.4:403). Each controlled oscillator (fig.4:401) operates at a either a first frequency or a second frequency, in accordance with the level of its adjustment signal. Each counter (fig.4:403) produces a count value of the number oscillations of the controlled oscillator in each of a succession of count periods defined by a count clock signal. The TDC digital output signals ...

Integrated data clock extractor

Improvements in or relating to phase locked loops

FREQUENCY AND PHASE SYNCHRONISING ARRANGEMENTS

Phase locked loop circuit

Device including/understanding an oscillator being stabilized automatically on the frequency of an impulse control signal.

PHASE-LOCKED LOOP

PROCEDURE AND DEVICE FOR THE AVOIDANCE OF FLUCTUATIONS OF A DIGITALLY PRODUCED EXPENDITURE CLOCK

DIGITAL PHASE DETECTOR FOR A PHASE-LOCKED LOOP

HIGHLY SOLUBLE PHASE AND FREQUENCY DETECTORS

PROCEDURE AND DEVICE FOR THE FAIL SAFE ONE RESYNCHRONISATION WITH MINIMUM LATENCY

Phase detector

Clock recovery method for bursty communications

Digital phase comparator

VERSATILE PHASE-LOCKED LOOP PHASE DETECTOR

PHASE LOCKED LOOP

PHASE TOLERANT BIT SYNCHRONIZER FOR DIGITAL SIGNALS

PHASE TOLERANT BIT SYNCHRONIZER FOR DIGITAL SIGNALS A bit synchronizer for digital data signals capable of tracking phase errors of up to ? 180.degree. without loss of lock. An input data signal is squared and then applied to a pair of D-type flip-flops. The flip-flops are alternately driven by a clock signal generated by a voltage controlled oscillator in a phase-locked loop. me flip-flops cause the input data to be shifted 0.degree. and 180.degree., respectively, with reference to the clock signal. The flip-flops are crosscoupled to a pair of exclusive-OR gates, in a manner such that as the phase error between the input signal and the clock signal increases or decreases, the pulse width out of one gate varies proportionately while the output of the other gate is a pulse which is always one-half the clock signal period. The phase relationship of the pulses out of the gates switch 180.degree. as the phase error traverses the 0.degree. point. me outputs of the gates are summed to provide ...

DATA TRACKING CLOCK RECOVERY SYSTEM USING DIGITALLY CONTROLLED OSCILLATOR

A clock recovery system according to the present disclosure includes a VCO responsive to a voltage signal for generating a clock signal. A phase detector includes a register and a PROM, the register counting the clock signal to derive the output clock signal. The PROM is responsive to input data and the count in the register to detect and store information concerning relative phase relationships. A counter contains a count from which the control voltage for the VCO is derived. The PROM is operable to alter the count in the counter, thereby performing frequency adjustments, and to alter the count in the register to perform phase adjustments. Also, a converter, operable by the phase detector, may also derive a voltage signal for damping purposes.

CIRCUIT TO MINIMIZE LOCAL CLOCK FREQUENCY DISTURBANCES WHEN PHASE LOCKING TO A REFERENCE CLOCK CIRCUIT

PLL CIRCUIT AND PHASE CONTROL METHOD OF PLL CIRCUIT

A PLL circuit having a phase build-out function and a phase control method of the PLL circuit, in which a phase build-out detector monitors the input phase of a PLL device and detects a transient wander component and a cycle wander component at the same time. When only the transient wander component is automatically detected, a phase build-out actuator resets a phase detector, a digital amp-1 and a digital filter to restructure an output phase as before an input phase change. As to the cycle wander component detected at the same time, no phase restructuring is carried out.

METHOD AND APPARATUS FOR A PHASE-LOCKED LOOP CIRCUIT WITH HOLDOVER MODE

A phase-locked loop circuit with holdover. mode is formed utilizing a primary and secondary phase-locked loop circuits. Each loop circuit comprises a phase detector, loop filter, VCXO and frequency divider. The secondary loop is configured such that its output is very stable. The primary loop is phase-locked on a received reference clock signal and the second loop is phase locked on the output of the primary loop. The scaled output of the secondary loop being parallel to the reference clock signal. If the incoming reference signal is interrupted or lost the circuit is switched to a holdover mode where the input of the primary loop is switched to the stable scaled output of the secondary loop. In holdover mode, the output, of the primary loop is phase-locked to the stable output of the secondary loop. When the reference clock signal is reestablished, the input of the primary loop is switched back to the reference clock signal.

Einrichtung, insbesondere für Fernsehempfänger, zur Erzeugung zweier Steuerspannungen, welche vom gegenseitigen Phasenverhältnis zweier der Einrichtung zugeführten Spannungen annähernd gleicher Frequenz in verschiedener Weise abhängig sind

DIGITAL PHASE/CFREQUENCY COMPARISON CIRCUIT FOR A PHASE BLOCKING CIRCUIT.

DEVICE FOR THE PHASE SYNCHRONIZATION OF A PASSAGE STATION IN A DIGITAL MESSAGE SWITCHING NETWORK

Clock recovery circuit with a phase-locked loop to recover a clock pulse string from an input pulse string

The clock recovery circuit has a phase-locked loop (7) to whose comparison circuit (43) an input pulse train (i) is applied and which is controlled by a clock pulse train (CPW). The phase comparison circuit generates intermediate pulse trains which comprise different parts of the input pulse trains and which are connected to filter circuits (53-58) which generate output pulse trains (i+, i-) which are proportional to the pulse density of the input pulse train (i). These input pulses are applied to a differential amplifier at whose output a voltage signal appears which is equal to the logarithm of the ratio of the output pulses and is therefore independent of the pulse density of the input pulse trains. A clock recovery circuit of this type can be used for 34 Mbit/s, PCM transmission systems according to CCITT Recommendations. ...

Reducing phase noise in phase control loop involves controlling loop filter with process controller that uses outputs of controllable filter and of controllable oscillator

The method involves controlling a loop filter (CLF) with a process controller that uses the outputs of the controllable filter and of a controllable oscillator (DCO) to determine correction values for the phase control loop and to perform automatic correction of the phase error. An Independent claim is also included for a phase control loop, esp. for clock regeneration circuits.

Phase-locked-loop circuit

A phase-locked loop circuit (24) comprises a phase error detector (26) for receiving a multi-phase reference signal (40) and a synchronized phase signal (38) of the phase-locked-loop circuit, and for performing a rotational transformation to convert the multi-phase reference signal into two-phase quantities (32, 34) at a synchronous rotation d-q reference frame. A monotonic transfer module (27) receives the two-phase quantities, and generates a monotonic phase error signal (36) which is monotonic when a phase difference between the multi-phase reference signal and the synchronized phase signal ranges from -180 degrees to 180 degrees. A regulator (28) receives the monotonic phase error signal, and generates a synchronized rotation frequency (39). An integrator (30) receives the synchronized rotation frequency, and generates the synchronized phase signal.

Phase locked loop

Phase synchronous circulation circuit and data regenerator

Universal input data sampling circuit and method thereof

COLOR SYNCHRONIZATION CONTROL CIRCUIT WITH GENERATION OF COLOR KILLER SIGNAL

METHOD FOR MANAGING THE OPERATION OF A PHASE-LOCKED LOOP, AND CORRESPONDING INTEGRATED CIRCUIT

SYSTEM HAS BLOCKING OF LOOP

Freq. locking cct. for measuring signal distortion - locks oscillator, output counted during input signal presence to input signal

THE PHASE/FREQUENCY ANALOG SENSOR AND ITS USE IN A PHASE LOCKED LOOP.

N FREQUENCY/PHASE DETECTOR (IP)-

DEVICE OF DISCRIMINATION OF the PHASE AND the VARIATION OF PHASE Of a SIGNAL

METHOD AND CIRCUIT FOR ADJUSTING THE FREQUENCY OF A CLOCK SIGNAL

Analog frequency/phase detector and its use in a phase-locked loop

Un détecteur fréquence/phase entre un signal de référence V0 à la fréquence F0 et un signal V1 à fréquence variable F1 consiste essentiellement en un discriminateur de fréquence, connu par ailleurs, dans lequel le signal de sortie du circuit de déphasage en fonction de la fréquence (3) centré sur la fréquence F0 est appliqué, non pas directement à un circuit démodulateur (4) mais par l'intermédiaire d'un circuit sommateur (6) qui reçoit par ailleurs le signal de référence V0. L'invention est applicable notamment aux boucles d'asservissement ou de verrouillage en phase mises en ùoeuvre dans les radars et les synthétiseurs de fréquence.

클록 데이터 복원 회로용 위상 검출기

... 위상 검출기는 클록 지연 회로, 데이터 지연 회로, 제어 회로, D 플립-플롭, 및 논리 회로를 포함한다. 클록 지연 회로는 지연 클록 신호를 생성하기 위하여 클록 신호를 지연시킨다. 데이터 지연 회로는 지연 데이터 신호를 생성하기 위하여 데이터 신호를 지연시킨다. 제어 회로는 클록 신호 및 지연 클록 신호에 따라서 클록 지연 회로의 지연 시간 및 데이터 지연 회로의 지연 시간을 조정한다. D 플립-플롭은 데이터 신호 및 클록 신호에 따라서 레지스터 신호를 생성한다. 논리 회로는 CDR(Clock Data Recovery; 클록 데이터 복원)의 충전 펌프를 제어하기 위하여 데이터 신호, 지연 데이터 신호, 및 레지스터 신호에 따라서 업 제어 신호 및 다운 제어 신호를 생성한다.

Digital phase detector for phase locked loop

CIRCUIT FOR DETECTING PHASE

CLOCK GENERATING CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME

메인 클록의 높은 정밀 발진기

... 클록 발진기는: 고속 클록 신호를 발생시키고 디지털 트리밍 기능부를 포함하는 고속 발진기; 클록 입력부에서 상기 고속 클록 신호를 수신하는 카운터; 로우 드리프트(low drift)를 갖고 상기 카운터를 제어하는 타임 베이스 - 상기 카운터는 기준 값과 카운터 값 간의 차이 값을 발생시킴; 및 상기 차이 값을 수신하고 상기 고속 발진기에 트리밍 데이터를 제공하는 디지털 적분기를 포함한다.

CLOCK GENERATOR WITH MINIMIZED LONG TERM JITTER, CAPABLE OF USING THE PHASE OF A CLOCK SIGNAL OUTPUTTED FOR INCREASING DYNAMIC RANGE

PURPOSE: A clock generator with minimized long term jitter is provided to minimize the influence of jitter by using a digital phase locked loop circuit and a charge pump phase locked loop circuit in a cascade method. CONSTITUTION: A control apparatus(110) generates a division factor and a first internal clock signal in response to a reference clock signal and a multiplication factor. A digital phase-locked loop circuit(120) generates a second internal clock signal in response to the reference clock signal, the division factor, and the first internal clock signal. COPYRIGHT KIPO 2011 ...

IMPROVED DELAY LOCKED LOOP AND CLOCK DELAY COMPENSATION METHOD WITH VARIOUS DELAY TIME ACCORDING TO THE NOISE PATTERN

PURPOSE: A delay locked loop is provided to reduce the jitter characteristics by having a pitch out block for monitoring noise data, detecting a noise pattern and storing the noise pattern. CONSTITUTION: A delay locked loop comprises a clock buffer(801), a divider(802), a phase comparator(803), a delay controller(804), a delay line(805), a dummy delay line(806), a replica model(807), an output buffer(809) and a pitch out block(810). Wherein the pitch out block comprises a pattern detector(811) for detecting noise pattern and storing the pattern; a pre delay controller(812) for controlling the delay time according to the output of the pattern detector(811); pre delay lines(813, 814) for delaying an inner clock(rclk, fclk) according to the delay time from the pre delay controller(812). © KIPO 2005 ...

Detetor de fase digital

PROCESSO DE COLOCAR UM OSCILADOR EM FASE COM UM SINAL DE ENTRADA E APARELHO PARA REALIZACAO DO PROCESSO

Oscillating device generating signals based on base signals

The purpose of this invention is to stabilize the phase difference of an oscillating signal relative to a base signal in a PLL circuit; in addition the phase difference and a loop frequency area can be changed. An oscillating device is provided, which has a filter circuit, that possesses a condenser and outputs a control signal based on the charge amount stored in the condenser; an oscillator, which outputs an oscillating signal of a frequency based on the control signal; a phase comparator, which detects the phase difference between the oscillating signal and the base signal by comparing the oscillating signal and the base signal of a pre-determined frequency; a switch circuit, based on tlie phase difference, controls whether the condenser is cliarged by a fixed charging current or the condenser is discharged by a fixed discliarging current; and a current-stabilizing circuit, which determines respectively the charging current and the discharging current based on the pre-determined base ...

Phase-locked loop circuit and clock generator including the same

A phase-locked loop (PLL) circuit may include a voltage-controlled oscillator, a sub-sampling PLL circuit, and a fractional frequency division control circuit. The fractional frequency division control circuit may include a voltage-controlled delay line that routes a feedback signal to generate delay information, a replica voltage-controlled delay line to which the delay information is applied and configured to route a reference clock signal to generate a plurality of delay reference clock signals each delayed by up to a different respective delay time, and a digital-to-time converter (DTC) configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.

PHASE COMPARATOR AND CLOCK DATA REGENERATION CIRCUIT USING THE SAME

An identifying means generates a regenerative signal by identifying an input signal with the timing of a clock signal and outputs the regenerative signal with an adjustable phase. An error pulse generating means generates an error pulse signal having a pulse width corresponding to phase difference between the input signal and the regenerative signal output from the identifying means. A reference pulse generating means generates a reference pulse signal corresponding to the error pulse signal generated by the error pulse generating means and having a constant pulse width. A differential signal generating means generates a phase comparison signal indicating the results of phase comparison by taking difference between the error pulse signal and the reference pulse signal. A phase adjusting means adjusts the phase with which the identifying means outputs the regenerative signal.

DIGITAL PHASE-LOCKED LOOP OPERATING BASED ON FRACTIONAL INPUT AND OUTPUT PHASES

In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference between an oscillator signal from an oscillator and a reference signal, e.g., using a time-to-digital converter (TDC). The DPLL determines a phase error based on the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator based on the phase error. In another aspect, a DPLL includes a synthesized accumulator that determines a coarse output phase by keeping tracking of the number of oscillator signal cycles based on the reference signal.

DIGITAL FREQUENCY SYNTHESIZER

A digital frequency synthesizer includes a digital-to-analog (1), a low pass filter (2), and a controllable oscillator (3), where the oscillator output is the synthesizer output. K number of RS flip-flops (101-108) produce error signals which are coupled to the DAC. The S inputs of the flip-flops come from a phase-splitter (8) which is driven by the more-significant bits unit of an accumulator (5) which is clocked by a reference frequency. The R inputs of the same flip-flops get input pulses from a pulse distributor (9) which is driven by the synthesizer output. The frequency resolution can be increased by adding a less-significant bits accumulator (15), coupled to the more-significant bits unit.

Spur and quantization noise cancellation for PLLS with non-linear phase detection

A fractional-N phase-locked loop (PLL) has a time-to-voltage converter with second order non linearity. The time-to voltage-converter provides an analog error signal indicating a phase difference between the reference clock signal with a period error and a feedback signal supplied by a fractional-N feedback divider. The spur results in quantization noise associated with the fractional-N feedback divider being frequency translated. To address the frequency translated noise, a spur cancellation circuit receives a residue signal indicative of the quantization noise and a spur signal indicative of the spur. The non-linearity of the time-to-voltage converter is mimicked digitally through terms of a polynomial generated to cancel the noise. The generated polynomial is coupled to a delta sigma modulator that controls a digital to analog converter that adds/subtracts a voltage value to/from the error signal to thereby cancel the quantization noise including the frequency translated quantization ...

Locking state detector and DLL circuit having the same

A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to distinguish a first phase difference range, and a second phase difference distinction signal to distinguish a second phase difference range wider than the first phase difference range, and a locking state setting unit configured to generate a locking state signal in response to the first phase difference distinction signal and the second phase difference distinction signal.

Detection arrangement, counter unit, phase locked loop, detection method and method for generating an oscillator signal

A detection arrangement includes a counter unit which receives a first clock signal and a reference clock signal. The counter unit derives a first data word as a function of a time deviation between clock edges of the first clock signal and the reference clock signal. The detection arrangement further includes a signal processing unit to determine a phase deviation word as a function of the first data word and a second data word, the second data word based on the duration of a clock period of the reference clock signal.

Phase-locked loop circuit and radio communication apparatus using the same

A communication apparatus includes a phase-locked loop circuit which receives a first signal having a frequency and converts it into an output signal having a transmission frequency and includes a current output type phase comparator which converts a phase difference between the first signal and a second signal into a current signal, a low pass filter which filters the current signal of the current output type phase comparator to produce an output signal a voltage controlled oscillator which produces an output signal having a transmission frequency corresponding to the output signal of the low pass filter the output signal of the voltage controlled oscillator constituting the output signal of the phase-locked loop circuit, a frequency converter which frequency-converts the output signal of the voltage controlled oscillator to produce the second signal, and a current source which supplies a current to an input of the low pass filter.

Clock signal generating apparatus

An apparatus for generating a clock signal phase-locked to a sync signal of a video signal. The apparatus comprises an error detector for detecting a phase error between the sync signal of the digitized video signal and a comparison signal produced internally; a clock signal generator whose oscillation frequency is variably controlled in response to the output of the error detector; a counter for counting the output of the clock signal generator; and a circuit for producing the comparison signal in response to the count value of the counter. The phase error is detected by integrating the level data of the digitized video signal, and the output of the error detector is replaced with a fixed value when the comparison signal has a predetermined phase. The apparatus is capable of preventing occurrence of a great phase error even at a head switching time or during the vertical blanking interval, so that mislock is preventable and a pull-in action can be executed fast.

Phase-locked loop clock pulse extraction circuit

A circuit for extracting a clock pulse waveform from an input pulse waveform comprising a phase-locked loop including a phase comparator having a first input to which the input pulse waveform is supplied, a second input and an output which is coupled in cascade at least with a voltage controlled oscillator whose output is coupled to the second input of the phase comparator. The clock pulse waveform is provided at the output of the oscillator. The phase comparator includes gating circuits controlled by the clock waveform and the input waveform to produce first and second intermediate pulse waveforms each having pulses constituted by different portions of the pulses of the input waveform and proportional to the pulse density of the input waveform, filter circuits connected directly to the gate circuits responsive to the first and second intermediate waveforms to produce first and second output waveforms which are equal to the mean amplitude values of the first and second intermediate waveforms ...

Digital carrier synthesis by counting cycles for synchronization to a reference signal that is asynchronous with respect to a digital sampling clock

A periodic multi-bit digital signal is synthesized having a frequency that is specified by the frequency of a periodic reference signal that is asynchronous with respect to a sampling clock of the periodic digital signal. In a digital video system, for example, a digital color subcarrier is synthesized and synchronized to a reference frequency of a crystal oscillator that is asynchronous with respect to a digital system clock for the digital video system. The periodic digital signal is generated by an adjustable digital oscillator clocked by the sampling clock. The frequency or phase of the periodic digital signal is compared to the frequency or phase of the periodic reference signal to produce an adjustment value for adjusting the periodic digital signal to synchronize the periodic digital signal with the periodic reference signal. The digital oscillator, for example, generates the periodic digital signal at the sampling rate by periodically incrementing an accumulator with the adjustment ...

Clock distribution network using feedback for skew compensation and jitter filtering

A clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering.

Analog frequency locked loop with digital oversampling feedback control and filter

A filter using analog to digital conversion, digital filtering and oversampling noise reshaping is disclosed. Application of such a filter to a frequency locked oscillator is disclosed. Application of such a filter to an oscillator having a capability to synchronize with an external stimulus is disclosed.

Frequency detector of phase locked loop

A frequency detector in a phase locked loop which generates a clock signal for reproducing a signal from a optical disc. 3 T information corresponding to an upper limit of the frequency of the Eight-to-Fourteen Modulation signal is compared with the oscillation clock of the VCO divided by three to reduce the oscillation frequency of the VCO. Additionally, 11 T information corresponding to a lower limit of the frequency of the Eight-to-Fourteen Modulation signal is compared with the oscillation clock of the VCO divided by eleven to increase the oscillation frequency of the VCO thereby providing a VCO which oscillates at a frequency corresponding to the frequency of the Eight-to-Fourteen Modulation signal.

Phase-locked loop for signals having rectangular waveforms

PCT No. PCT/NL95/00422 Sec. 371 Date Aug. 15, 1996 Sec. 102(e) Date Aug. 15, 1996 PCT Filed Dec. 15, 1995 PCT Pub. No. WO96/19043 PCT Pub. Date Jun. 20, 1996Phase-locked loop (for signals having rectangular waveforms, comprising, in series, a phase detector, a control signal generator circuit having a loop filter, a controlled oscillator and an auxiliary circuit. The detector recieves a reference signal having a reference frequency from a reference source as first input signal. The detector recieves second and third input signals from the auxiliary circuit. The reference signal and the second input signal are compared by a first logic combination function to deliver a second combination signal. The second and third input signals are compared by a second logic combination function to deliver a second combination signal. The second and third input signals are such that, in the locked state of the loop, the frequency of the second input signal is equal to the reference fequency and the frequency ...

Low frequency loop-back in a high speed optical transceiver

The invention relates to methods and apparatus that provide a low frequency data loop-back in a transceiver to advantageously provide built-in test capability with low overhead. The low frequency loop-back advantageously allows testing of a receiver and a transmitter of the transceiver through a high frequency serial interface while reducing the need to interface to a low frequency interface of the transceiver with expensive and specialized test equipment. One embodiment of the low frequency data loop-back includes a transceiver configured to select between a reference clock signal for normal use of the transceiver and a clock signal generated from serial data for test use in response to an activation of a loop-back test command. In one embodiment, a multiplexer selects between the reference clock signal and the generated clock signal.

Phase-locked-loop circuit and bit detection arrangement comprising such a phase-locked-loop circuit

Гибридный синтезатор частот с автокомпенсацией фазовых помех

Полезная модель относится к области радиоэлектроники. Технический результат заключается в снижении уровня паразитных спектральных составляющих, уровня фазового шума и шумовой полосы синтезируемого сигнала формирователя. Технический результат достигается за счёт гибридного синтезатора частот с автокомпенсацией фазовых помех, содержащего: опорный генератор; цифровой вычислительный синтезатор; выходной фильтр цифрового вычислительного синтезатора; петлю фазовой автоподстройки частоты, содержащую: фазовый детектор, фильтр нижних частот и генератор, управляемый напряжением; делитель частоты; автокомпенсатор фазовых искажений, состоящий из опорного тракта, содержащего дифференцирующую цепь, Т-триггер; информационного тракта, содержащего дифференцирующую цепь, двухполупериодный выпрямитель, Т-триггер; усилитель; сумматор; управляемый фазовращатель. 1 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 194 942 U1 (51) МПК H03L 7/085 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H03L 7/085 (2019.08) (21)(22) Заявка: 2019132827, 15.10.2019 (24) Дата начала отсчета срока действия патента: Дата регистрации: 30.12.2019 (45) Опубликовано: 30.12.2019 Бюл. № 1 Адрес для переписки: 600000, г. Владимир, ул. Горького, 87, ВлГУ, патентная группа (73) Патентообладатель(и): Федеральное государственное бюджетное образовательное учреждение высшего образования "Владимирский Государственный Университет имени Александра Григорьевича и Николая Григорьевича Столетовых" (ВлГУ) (RU) U 1 1 9 4 9 4 2 R U (54) Гибридный синтезатор частот с автокомпенсацией фазовых помех (57) Реферат: Полезная модель относится к области фазовой автоподстройки частоты, содержащую: радиоэлектроники. Технический результат фазовый детектор, фильтр нижних частот и заключается в снижении уровня паразитных генератор, управляемый напряжением; делитель спектральных составляющих, уровня фазового частоты; автокомпенсатор фазовых искажений, шума и шумовой полосы ...

Pll circuit, method for operating pll circuit and system

A PLL circuit includes: a first counter to accumulate a frequency command word in response to a reference clock signal and to generate a first counted value; a second counter to count an output clock signal and generate a second counted value; a time measuring circuit to measure an interval between a transition edge of the reference clock signal and a transition edge of the output clock signal to output a third counted value; a phase difference normalizing circuit to multiply the third counted value by a normalizing coefficient to generate a first phase difference; an operating circuit to subtract a value obtained by subtracting the first phase difference from the second counted value from the first counted value to generate a phase difference signal; and an oscillator to change a frequency of the output clock signal based on the phase difference signal.

Frequency synthesizer

There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency.

Device having digitally controlled oscillator

A device includes a digital-to-time converter and an interpolator having a data input and a data output coupled to the digital-to-time converter. The interpolator may be configured to receive a converter control signal at the data input and to provide an interpolated converter control signal at the data output. An interpolation rate of the interpolator may depend on the converter control signal.

Digital phase lock loop

An apparatus may comprise a time-to-digital circuit architecture. Other embodiments are described and claimed.

Fractional digital pll with analog phase error compensator

Disclosed is a fractional digital phase locked loop with an analog phase error compensator. The digital phase locked loop with an analog phase error compensator can reduce excessive power consumption and power noise and transient current noise while increasing phase error detection resolution by performing fractional phase error detection and compensation through the analog phase error compensator.

Variable modulus modulator for fractional-n frequency synthesizers

A variable modulus sigma delta (ΣΔ) modulator for a fractional-N frequency synthesizer in accordance with the present invention may include an integer division unit; a pulse-width modulation (PWM) generator, a ΣΔ noise-shaping unit, a first input FRAC for receiving a first programmable integer, and a second input MOD for receiving a second input, wherein the integer division unit is configured to perform a translation from the first input and the second input into a first output FRAC′ and a second output R, the PWM generator is configured to receive the second input MOD and the second output R, and generate a modulated pulse signal, and the ΣΔ noise-shaping unit is configured to receive the first output and the modulated pulse signal, and generate a sequence whose average equals approximately the first input over the second input.

Digital phase locked loop system and method

A phase locked loop control system includes a digital controlled oscillator (DCO) that is controlled by logic cells in response to comparison of the oscillator output with a reference clock related signal. Delay cell number adjustment, delay cell load adjustment and cycle control are operative to digitally control the DCO frequency to obtain wide frequency range and limited jitter.

Dll phase detection using advanced phase equalization

A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an Onlx mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal is used to terminate the ForceSL and Onlx modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during Onlx exit, and resulting in faster DLL locking time.

ACCUMULATOR-TYPE FRACTIONAL N-PLL SYNTHESIZER AND CONTROL METHOD THEREOF

There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer (), a pulse signal proportional to a fractional phase error occurring between a reference signal and an output signal of a fractional divider () for feeding back an output of a VCO () of an output stage to a preceding stage is generated using an error signal from an accumulator (). Through the use of the pulse signal, pulse widths of a UP signal and a DN signal output from a phase detector () are controlled so as to reduce a fractional phase error occurring between the UP signal and the DN signal. Thus, the fractional spurious caused by periodically switching the frequency division number of the fractional divider () is suppressed. 1. An accumulator-type fractional N-PLL synthesizer comprising:a VCO;a fractional frequency divider, disposed in a feedback path of an output signal of the VCO, for generating a frequency divider output signal of a fractional frequency division number;an accumulator for supplying an overflow signal for periodically switching a frequency division number of the fractional frequency division number, to the fractional frequency divider; anda phase detector for detecting a phase difference between the frequency divider output signal and a predetermined reference signal to generate a control input signal to the VCO based on the detected phase difference,wherein the accumulator generates an error signal having fractional phase error information, andwherein the phase detector corrects the phase difference between the frequency divider output signal and the reference signal, using the error signal.2. The accumulator-type fractional N-PLL synthesizer according to claim 1 , wherein the phase detector generates the phase difference as a UP signal and a DN signal claim 1 ...

Method for Suppression of Spurs from a Free Running Oscillator in Frequency Division Duplex (FDD) and Time Division Duplex (TDD) Wireless Systems

Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include minimizing the mixing gain between the oscillation signal and a power signal provided to the PLL. The oscillation signal and the power signal may be mixed in a phase frequency detector (PFD) included in the PLL. The minimizing of the mixing gain for the PFD also minimizes the degrading effect that the spurs have on the overall performance of the communications device. The mixing gain may be minimized by minimizing the impedance provided at nodes included in the PFD where the oscillation signal and the power signal mix. The mixing gain may also be minimized by maximizing the power supply rejection ratio for the PFD.

CONFIGURABLE DIGITAL-ANALOG PHASE LOCKED LOOP

A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop. 1. A phase locked loop (PLL) device comprising:a phase detector;an analog loop filter comprising a plurality of filter elements;a voltage controlled oscillator (VCO);a time to digital converter (TDC);a digital loop filter;a digital to analog converter (DAC); anda switching mechanism responsive to a first control signal value to configure the PLL device into an analog loop comprising the phase detector, analog loop filter, and VCO and responsive to a second control signal value to configure the PLL device into a hybrid digital-analog loop comprising the phase detector, TDC, DAC, and VCO and further configured to connect the plurality of filter elements to form an integrator between the DAC and the VCO.2. The PLL device of claim 1 , wherein the DAC comprises a current source output stage connected to the integrator when the PLL device is configured in the hybrid digital-analog loop.3. The PLL device of claim 1 , wherein the switching element is configured to connect the plurality of filter elements to form the analog loop filter when the PLL device is configured in the analog loop.4. The PLL device of claim 3 , wherein the switching element is configured to connect the plurality of filter elements to form the analog loop filter having a response comprising a first pole at an origin claim 3 , a zero at a first frequency and a second pole a second frequency greater than the first frequency.5. The PLL device of claim 3 , further comprising a charge pump connected ...

Frequency Synthesizer

The present invention discloses a frequency synthesizer. The frequency synthesizer includes a delay unit, for receiving a reference signal and delaying the reference signal according to a delay parameter, so as to generate a delay reference signal; a phase-locked loop, for generating an output signal according to the delay reference signal and a feedback frequency dividing signal; a control unit, for generating the delay parameter and a frequency dividing parameter according to a target magnification factor; and a frequency divider, for dividing the frequency of the output signal according to the frequency dividing parameter. 1. A frequency synthesizer , comprising:a delay unit, for receiving a reference signal and delaying the reference signal according to a delay parameter, so as to generate a delay reference signal;a phase-locked loop, for generating an output signal according to the delay reference signal and a feedback frequency dividing signal;a control unit, for generating the delay parameter and a frequency dividing parameter according to a target magnification factor; anda frequency divider, for dividing the frequency of the output signal according to the frequency dividing parameter.2. The frequency synthesizer of claim 1 , wherein the phase-locked loop comprises:a phase frequency detector, for receiving the delay reference signal and the feedback frequency dividing signal, and accordingly generating a phase error signal;a charge pump, for generating a control voltage signal according to the phase error signal;a loop filter, for filtering the control voltage signal, so as to generate a filtering signal; anda voltage-controlled oscillator, for generating the output signal according to the filtering signal.3. The frequency synthesizer of claim 1 , wherein the delay parameter is a delay phase and the frequency dividing parameter is a frequency dividing ratio.4. The frequency synthesizer of claim 1 , wherein the control unit generates the delay parameter and ...

DELAY CONTROL CIRCUIT AND CLOCK GENERATION CIRCUIT INCLUDING THE SAME

A clock generation circuit includes a delay line, which delays an input clock and generates a delayed clock, a delay modeling unit, which delays the delayed clock by a modeled delay value and generates a feedback clock, a phase detection unit, which compares phases of the input clock and the feedback clock and generates a phase detection signal, a filter unit, which receives the phase detection signal and generates phase information, generates an update signal when a difference between the numbers of phase detection signals with a first and a second level generated is greater than or equal to a threshold value, and generates the update signal after a lapse of a predetermined time when the difference is less than the threshold value, and a delay line control unit, which sets a delay value of the delay line in response to the update signal and the phase information. 1. A clock generation circuit comprising:a delay line configured to delay an input clock and generate a delayed clock;a delay modeling unit configured to delay the delayed clock by a modeled delay value and generate a feedback clock;a phase detection unit configured to compare phases of the input clock and the feedback clock and generate a phase detection signal;a filter unit configured to receive the phase detection signal and generate phase information, generate an update signal when a difference between the number of phase detection signals with a first level generated and the number of phase detection signals with a second level generated is greater than or equal to a threshold value, and generate the update signal after a lapse of a predetermined time when the difference is less than the threshold value; anda delay line control unit configured to set a delay value of the delay line in response to the update signal and the phase information.2. The clock generation circuit according to claim 1 , wherein the filter unit comprises:a filter configured to generate a filter update signal and the phase ...

FRACTIONAL PLL CIRCUIT

A fractional PLL circuit includes: a phase comparator for detecting a phase difference, and which outputs a controlled voltage; a voltage-controlled oscillator for generating and outputting an output clock signal; a phase-selection circuit for selecting any one of a predetermined number of phases into which one period of a clock of the output clock signal is equally divided, generating a phase-shift clock signal having a rising edge in the selected phase, and outputting the phase-shift clock signal to the phase comparator; and a phase controller for determining a phase of the rising edge of the phase-shift clock signal selected by the phase-selection circuit such that a period of the phase-shift clock signal is a length that is changed by a predetermined phase-shift amount from a period of the output clock signal, and controlling the phase-selection circuit so as to select the determined phase. 1. A fractional PLL circuit comprising:a phase comparator that detects a phase difference between an input clock signal that is a reference and a feedback signal, and outputs a controlled voltage in accordance with the phase difference;a voltage-controlled oscillator that generates and outputs an output clock signal that has a frequency based on the controlled voltage;a phase-selection circuit that selects any one of a predetermined number of phases into which one period of a clock of the output clock signal is equally divided, generates a phase-shift clock signal that has a rising edge in the selected phase, and outputs the phase-shift clock signal as the feedback signal to the phase comparator; anda phase controller that determines a phase of the rising edge of the phase-shift clock signal selected by the phase-selection circuit such that a period of the phase-shift clock signal is a length that is changed by a predetermined phase-shift amount from a period of the output clock signal, and controls the phase-selection circuit so as to select the determined phase.2. The ...

SIGNAL PROCESSING APPARATUS AND METHOD, RECEIVING APPARATUS AND METHOD, AND, TRANSMITTING APPARATUS AND METHOD

There is provided a signal processing apparatus including an oscillating unit having a division ratio of an integer that performs oscillation at a predetermined oscillation frequency, a frequency transforming unit that transforms a frequency of a signal of a processing target using a signal of the oscillation frequency obtained by the oscillation of the oscillating unit, and a correcting unit that corrects an error of the frequency of the signal of the processing target transformed by the frequency transforming unit based on an error of the oscillation frequency. 1. A signal processing apparatus , comprising:an oscillating unit having a division ratio of an integer that performs oscillation at a predetermined oscillation frequency;a frequency transforming unit that transforms a frequency of a signal of a processing target using a signal of the oscillation frequency obtained by the oscillation of the oscillating unit; anda correcting unit that corrects an error of the frequency of the signal of the processing target transformed by the frequency transforming unit based on an error of the oscillation frequency.2. The signal processing apparatus according to claim 1 ,wherein the correcting unit corrects the error of the frequency of the signal of the processing target that has been subjected to a frequency transform by the frequency transforming unit.3. The signal processing apparatus according to claim 2 , further comprisinga channel selecting unit that selects a channel of the signal of the processing target that has been subjected to the frequency transform by the frequency transforming unit,wherein the correcting unit corrects the error of the frequency of the signal of the processing target of the channel selected by the channel selecting unit.4. The signal processing apparatus according to claim 1 ,wherein the correcting unit corrects the error of the frequency of the signal of the processing target that is not subjected to a frequency transform by the frequency ...

Frequency Tuning Based on Characterization of an Oscillator

Aspects of a method and system for frequency tuning based on characterization of an oscillator are provided. In this regard, a frequency of an oscillator in an integrated circuit may be controlled based on a first digital control word, a frequency of a tuned circuit may be controlled based on a second digital control word, and the second control word may be determined utilizing a mapping between the first control word and the second control word. The frequency of the oscillator and the tuned circuit may be controlled by adjusting a capacitance of the oscillator and tuned circuit, respectively. The mapping may be based on a relationship between the oscillator and the tuned circuit, such as logical and/or mathematical relationship between the capacitance of the oscillator and the capacitance of the tuned circuit and/or the relationship between the frequency of the oscillator and the frequency of the tuned circuit.

DETERMINATION SUPPORT APPARATUS, DETERMINING APPARATUS, MEMORY CONTROLLER, SYSTEM, AND DETERMINATION METHOD

A determination support apparatus includes a detecting unit that detects a phase difference between a first clock signal and a second clock signal that is identical in frequency to the first clock signal; a control unit that controls delay of at least one among the first clock signal and the second clock signal such that the detected phase difference becomes less than a given amount; and an acquiring unit that acquires values of a given clock signal among the first clock signal and the second clock signal, among which at least one has been subject to delay control by the control unit, wherein the acquiring unit acquires the values of the given clock signal at a timing that is based on a clock signal that is other than the given clock signal and among the first clock signal and the second clock signal. 1. A determination support apparatus comprisinga detecting unit that detects a phase difference between a first clock signal and a second clock signal that is identical in frequency to the first clock signal;a control unit that controls delay of at least any one among the first clock signal and the second clock signal such that the detected phase difference becomes less than a given amount; andan acquiring unit that acquires values of a given clock signal among the first clock signal and the second clock signal, among which at least one has been subject to delay control by the control unit, wherein the acquiring unit acquires the values of the given clock signal at a timing that is based on a clock signal that is other than the given clock signal and among the first clock signal and the second clock signal, among which at least one has been subject to delay control.2. The determination support apparatus according to claim 1 , further comprisinga delaying unit that delays the given clock signal by a second given amount, whereinthe acquiring unit acquires at a timing that is based on the clock signal other the given clock signal, the values of the given clock signal ...

Phase frequency detector

Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

Method and circuit for adjusting the frequency of a clock signal

In a general aspect, a method for adjusting an oscillator clock frequency can include applying a first control value to a first oscillator, applying a second control value, different from the first control value, to a second oscillator, measuring a frequency of each of the first and second oscillators, determining, by interpolation, a corrected frequency measurement of the second oscillator depending on a frequency deviation measured between the first and second oscillators when subjected to a third control value, on the third control value, and on the control value applied to the second oscillator, determining by interpolation a new first control value depending on the measured frequency of the first oscillator, on the corrected frequency, on the first and second control values, and on a desired frequency, and applying the new first control value to the first oscillator.

REFERENCE MONITORS WITH DYNAMICALLY CONTROLLED LATENCY

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation. 1. An integrated circuit (IC) with reference monitoring , the IC comprising:a clock measurement circuit configured to generate a plurality of digital measurements of a reference clock signal based on timing of a system clock signal; anda reference monitor configured to generate a monitor output signal indicating whether the reference clock signal is within a tolerance of one or more tolerance parameters, wherein the reference monitor comprises a statistical processing circuit configured to process the plurality of digital measurements to generate an estimate of measurement uncertainty, and to control a latency of the reference monitor in generating the monitor output signal based on the estimate of measurement uncertainty.2. The IC of claim 1 , wherein the statistical processing circuit is configured to compute a variance of the plurality of digital measurements over a time window.3. The IC of claim 2 , wherein the one or more tolerance parameters comprises a nominal period and a period offset limit claim 2 , wherein the statistical processing circuit is further configured to control the latency based on ...

System and Method for a Voltage Controlled Oscillator

In accordance with an embodiment, a voltage controlled oscillator (VCO) includes a VCO core having a plurality of transistors and a varactor circuit that has a first end coupled to emitter terminals of the VCO core and a second end coupled to a tuning terminal. The varactor circuit includes a capacitance that increases with increasing voltage applied to the tuning terminal with respect to the emitter terminals of the VCO core.

Device and method to calibrate frequency

A frequency calibration device includes an input signal generator configured to generate an input signal based on an oscillation signal and an external signal, an envelope detector configured to detect an envelope signal corresponding to the input signal, and a frequency tuner configured to tune an oscillation frequency of the oscillation signal based on an envelope frequency corresponding to the envelope signal.

DELAY LOCKED LOOP

A delay locked loop includes a main delay circuit including a plurality of unit delay lines that generate a plurality of internal clocks by delaying an input clock, delay amounts of the plurality of unit delay lines being adjusted in response to code signals; a sub-delay circuit including a plurality of sub-delay lines that generate a plurality of phase clocks by respectively delaying the input clock and the plurality of internal clocks; a phase detector configured to compare phases of the plurality of phase clocks and provide a phase detection signal according to a result of the comparison; and a digital circuit configured to update the code signals corresponding to the plurality of unit delay lines one by one at a time when the phase detection signal is provided to the digital circuit. 1. A delay locked loop comprising:a main delay circuit including a plurality of unit delay lines that generate a plurality of internal clocks by delaying an input clock, delay amounts of the plurality of unit delay lines being adjusted in response to code signals;a sub-delay circuit including a plurality of sub-delay lines that generate a plurality of phase clocks by respectively delaying the input clock and the plurality of internal clocks;a phase detector configured to compare phases of the plurality of phase clocks and provide a phase detection signal according to a result of the comparison; anda digital circuit configured to update the code signals corresponding to the plurality of unit delay lines one by one at a time when the phase detection signal is provided to the digital circuit,wherein the digital circuit comprises:a counter configured to store a count value and change the count value when the phase detection signal is received; anda code controller configured to receive the count value and update a code signal corresponding to the count value among the code signals.2. The delay locked loop of claim 1 , wherein the digital circuit stores information regarding a code ...

DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME

A delay locked loop circuit including: a clock signal input buffer to buffer an input clock signal and generate a reference clock signal; a delay unit to delay the reference clock signal in response to a coarse and fine delay code and generate an internal clock signal; a clock signal delay replica unit to delay the internal clock signal and generate a feedback clock signal; a coarse delay control unit to receive the reference and feedback clock signals, detect a time period between a transition time point of the reference clock signal and a transition time point of the feedback clock signal occurring before the transition time point of the reference clock signal, and generate a coarse delay code; and a fine delay control unit to compare a phase of the reference clock signal and a phase of the feedback clock signal, and generate a fine delay code. 1. A delay locked loop circuit , comprising:a clock signal input buffer configured to buffer an input dock signal and generate a reference clock signal;a delay unit configured to delay the reference clock signal in response to a coarse delay code and a fine delay code and generate an internal clock signal;a dock signal delay replica unit configured to delay the internal clock signal by a delay time of the dock signal input buffer and generate a feedback clock signal;a coarse delay control unit configured to receive the reference clock signal and the feedback clock signal, detect a time period between a transition time point of the reference clock signal and a transition time point of the feedback clock signal, and generate the coarse delay code, wherein the transition time point of the feedback clock signal occurs before the transition time point of the reference clock signal; anda fine delay control unit configured to compare a phase of the reference clock signal and a phase of the feedback clock signal, and generate the fine delay code.2. The delay locked :loop circuit of claim 1 , further comprising:a clock signal delay ...

Clock recovery system and method for near field communication with active load modulation

A system includes a tank circuit, a synchronization circuit, a transmitter, and a control circuit. The tank circuit is configured to receive a first signal transmitted from a near field communication reader. The synchronization circuit is configured to synchronize a clock to the first signal. The transmitter is configured to transmit data using the clock from the tank circuit to the near field communication reader using active load modulation. The control circuit is configured to disable the synchronization circuit during a modulation period of the active load modulation and to reduce energy remaining in the tank circuit at an end of the modulation period.

Clock Duty Cycle Calibration and Frequency Multiplier Circuit

Provided is a clock duty cycle calibration and frequency multiplier circuit used in a square wave frequency multiplier, comprising: a multiplexing module (), which performs a phase-inversion operation on a clock signal according to a control signal; a calibration module () which adjusts the duty cycle according to a control signal, and outputs a clock signal with a 50% duty cycle; a delay module (), which performs a delay operation on the clock signal according to a control signal; a detection module (), which compares the clock signal and outputs a feedback signal; a control module (), which outputs a control signal according to the feedback signal; a frequency multiplication module (), which performs a frequency multiplication operation on the clock signal. Therefore, high-precision clock signal frequency multiplication is implemented with relatively low circuit complexity and low cost. 1. A clock duty cycle calibration and frequency multiplier circuit , comprising:{'b': 2', '1, 'a multiplexing module, configured to output a second clock signal (CK) after inverting an input first clock signal (CKin) based on a first control signal (V);'}{'b': 2', '2', '3, 'a calibration module, configured to adjust a duty cycle of the second clock signal (CK) based on a second control signal (V), and finally output a third clock signal (CK) with a 50% duty cycle;'}{'b': 4', '3', '3, 'a delay module, configured to output a fourth clock signal (CK) after performing a delay operation on the third clock signal (CK) based on a third control signal (V);'}{'b': 3', '4, 'a detection module, configured to compare the third clock signal (CK) and the fourth clock signal (CK) that are input thereto, and output a feedback signal (Va) based on a comparison result;'}{'b': 1', '2', '3, 'a control module, configured to output the first control signal (V), the second control signal (V), and the third control signal (V) based on the input feedback signal (Va); and'}{'b': '3', 'a frequency ...

APPARATUS AND METHODS FOR SYSTEM CLOCK COMPENSATION

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation. 1. An integrated circuit (IC) with system clock compensation , the IC comprising:a system clock generation circuit configured to generate a system clock signal based on a system reference signal;one or more circuit blocks having timing controlled by the system clock signal; anda system clock compensation circuit configured to generate one or more compensation signals operable to compensate the one or more circuit blocks for an error of the system clock signal.2. The IC of claim 1 , wherein the system clock compensation circuit comprises an error model configured to generate an estimate of the error of the system clock signal based on one or more operating conditions.3. The IC of claim 2 , wherein the error model is configured to receive a temperature signal indicating a temperature condition.4. The IC of claim 2 , wherein the error model is configured to receive a supply voltage signal indicating a supply voltage condition.5. The IC of claim 2 , wherein the IC is configured to receive one or more coefficients of the error model over an interface.6. The IC of claim 2 , wherein the system clock compensation ...

Digital phase detector

According to one example, a digital phase detector is disclosed for use with a phase lock loop. The digital phase detector is configured to operate in a low-frequency environment and to filter noise and transients in a signal, while also being tolerant of dropped phase pulses. In some embodiments, the digital phase detector is configured to measure up to two REFCLK edges with respect to a FBCLK signal, and if an edge occurs in the first half of REFCLK, classify the edge as lagging, and if an edge occurs in the second half of REFCLK, classify the edge as leading. If both edges are leading or both are lagging, the smaller of the two is used as the phase. If one is leading and one is lagging, the difference is used as the phase.

PHASE DETECTOR, PHASE-FREQUENCY DETECTOR, AND DIGITAL PHASE LOCKED LOOP

A phase detector includes a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal, a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal, and an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to a control signal. 1. A phase detector comprising:a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal;a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal; andan initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to a control signal.2. The phase detector according to claim 1 , wherein the latch circuit comprises a first input terminal and a second input terminal claim 1 , andwherein the initial voltage control circuit comprises a first is voltage control subcircuit which controls the first input terminal and a second voltage control subcircuit which controls the second input terminal.3. The phase detector according to claim 2 , wherein the first voltage control subcircuit and the second voltage control subcircuit divide a power supply voltage in response to the control signal claim 2 , and control initial voltages of the first input terminal and the second input terminal claim 2 , respectively.4. The phase detector according to claim 2 , wherein the phase comparing circuit first discharges one of the first input terminal and the second input terminal according to the phase difference between the first clock signal and the second clock signal.5. The phase detector according to claim 1 , further comprising:an offset controller configured to output the control signal based on an offset control signal and the second clock signal.6. The phase ...

DUAL-DOMAIN SUB-SAMPLING PHASE-LOCKED LOOP

A sub-sampling phase-locked loop includes a first phase output unit sub-sampling an output clock of a digitally-controlled oscillator and outputting a sign bit corresponding to a voltage-domain phase and a second phase output unit outputting a gain bit corresponding to a time-domain phase based on a pulse width set according to the output clock and a threshold time set according to the reference clock. 1. A sub-sampling phase-locked loop comprising:a first phase output unit sub-sampling an output clock of a digitally-controlled oscillator and outputting a sign bit corresponding to a voltage-domain phase; anda second phase output unit outputting a gain bit corresponding to a time-domain phase based on a pulse width set according to the output clock and a threshold time set according to a reference clock; anda digital loop filter calculating a digital loop filter value based on the sign bit and the gain bit,wherein a value obtained by multiplying the sign bit by the gain bit corresponds to an input value of the digital loop filter value to control a phase of the output clock.2. (canceled)3. The sub-sampling phase-locked loop of claim 1 , wherein the first phase output unit comprises:a sample-and-holder sampling a first differential input voltage from the output clock in response to the reference clock;a signal sampler sampling a latch input signal from the first differential input voltage in response to the reference clock; andan SR latch outputting the sign bit in response to the latch input signal.4. The sub-sampling phase-locked loop of claim 3 , wherein the signal sampler comprises:a first comparator comparing the first differential input voltage in response to the reference clock and outputting a pair of first comparison signals based on the compared result; anda pair of inverters inverting the pair of first comparison signals.5. The sub-sampling phase-locked loop of claim 3 , wherein the second phase output unit comprises:a threshold time controller outputting a ...

Integrated circuit with adaptability to a process-voltage-temperature (pvt) variation

An integrated circuit including: an oscillator configured to generate an oscillating voltage with a predetermined oscillation frequency in an oscillation period; a voltage regulator configured to generate an output voltage for driving the oscillator and provide the output voltage to the oscillator; and a current injection circuit configured to provide an oscillation current to the oscillator, in response to an oscillation enable signal in the oscillation period.

Methods related to frequency synthesis control

Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.

TIME-TO-DIGITAL CONVERTER IN PHASE-LOCKED LOOP

A time-to-digital converter includes a delay unit into which a first signal is input and a sampling unit into which a second signal is input. The delay unit includes a first delay chain, a second delay chain, and a third delay chain that are connected in series in sequence. The delay unit delays the first signal. The first delay chain includes at least one first delayer. The second delay chain includes at least three second delayers. The third delay chain includes a third delayer. The delay duration of the first delayer and the delay duration of the third delayer are greater than delay duration of the second delayer. The sampling unit samples output signals of first delayers in the first delay chain, second delayers in the second delay chain, and third delayers in the third delay chain at a preset time point of the second signal. 1. A time-to-digital converter , comprising:a delay circuit into which a first signal is input; anda sampling circuit into which a second signal is input;wherein the delay circuit and the sampling circuit are part of a phase-locked loop circuit;wherein the delay circuit comprises a first delay chain, a second delay chain, and a third delay chain that are connected in series in sequence, and is operable to delay the first signal for a circuit delay duration, wherein the first delay chain comprises a first delayer, the second delay chain comprises three second delayers, the third delay chain comprises a third delayer, and a first delay duration from the first delayer and a third delay duration from the third delayer are greater than a second delay duration from the three second delayers; andwherein the sampling circuit is operable to perform a sampling on an output signal of each of the first delayer in the first delay chain, the three second delayers in the second delay chain, and the third delayer in the third delay chain at a preset time point of the second signal, and to output a signal of each sampling.2. The time-to-digital converter ...

Multi-mode radio frequency circuitry

Circuitry includes a first RF power amplifier, a second RF power amplifier, a third RF power amplifier, a first bias signal generator, and a second bias signal generator. The first RF power amplifier and the second RF power amplifier are each configured to amplify RF signals for transmission in a first carrier network. The third RF power amplifier is configured to amplify RF signals for transmission in a second carrier network. In a first mode, the first bias signal generator provides a bias signal to the first RF power amplifier and the second bias signal generator provides a bias signal to the second RF power amplifier. In a second mode, the first bias signal generator and the second bias signal generator each provide a portion of a bias signal to the third RF power amplifier.

CLOCK RECOVERY DEVICE AND SOURCE DRIVER FOR RECOVERING EMBEDDED CLOCK FROM INTERFACE SIGNAL

In generating a mask signal to be used when a clock signal embedded in an interface signal is recovered, when a mask rising signal for generating the mask signal is located in a data signal interval and a data signal indicates a high level, the mask signal may be generated in accordance with a falling edge of the data signal other than the mask rising signal. 1. A clock recovery device comprising:a mask signal generation unit configured to form a rising edge of a mask signal in accordance with a mask rising signal when an interface signal indicates a first level at a time point when a signal level of the mask rising signal transits, and to form the rising edge of the mask signal in accordance with a section where the interface signal transits from a second level to the first level when the interface signal indicates the second level different from the first level at the time point when the signal level of the mask rising signal transits;a clock extraction unit configured to generate an extraction clock from the interface signal with a clock signal embedded therein in a time interval in which the mask signal is activated; anda time-delay control unit configured to generate a plurality of data clock signals and the mask rising signal in a next period by time-delaying the extraction clock.2. The clock recovery device of claim 1 , wherein one period of the interface signal is divided into a plurality of unit times claim 1 , each including divided information claim 1 , and a phase of the mask rising signal is ahead of a phase of the extraction clock by K unit times claim 1 , wherein K is a positive number and a multiple of 0.5.3. The clock recovery device of claim 1 , wherein the interface signal includes a dummy signal interval and a clock signal interval claim 1 , and the interface signal indicates the first level in the dummy signal interval and indicates the second level in the clock signal interval.4. The clock recovery device of claim 3 , wherein a phase of the ...

MEMORY DEVICE AND DIVIDED CLOCK CORRECTION METHOD THEREOF

A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data. 1. A memory device comprising:an internal clock generator that is configured to generate a plurality of internal clock signals by dividing a received clock signal, where each of the internal clock signals has a respective phase that is different from the phases of the other internal clock signals;a serializer that is configured to use the internal clock signals to serialize training data;a data output buffer that is configured to output the serialized training data; anda clock controller that is configured to correct a clock dividing start time point of the received clock signal based on a control signal provided by a host,wherein a value of the control signal is based on a time that the serialized training data was received at the host.2. The memory device of claim 1 , wherein a data output buffer that is configured to output the serialized training data through a dedicated EDC pad is distinguished from a data pad through which write data is output.3. The memory device of claim 1 , wherein the control signal comprises a mode register set code.4. The memory device of claim 1 , further comprising a register that stores the training data prior to serialization of the training data.5. The memory device of claim 4 , wherein the training data is provided to the memory device from the host.6. The memory ...

ALL-DIGITAL PHASE-LOCKED LOOP

The present disclosure discloses an all-digital phase-locked loop. The all-digital phase-locked loop may include a time-to-digital conversion circuit configured to convert phase differences between a reference signal and a feedback signal into respective digital values and to output a first data signal and a second data signal corresponding to the respective digital values, a digital loop filter configured to select one of the first data signal and the second data signal as valid data and output a control signal by operating the valid data and a first register signal, a digitally controlled oscillator configured to generate an oscillation signal and control a frequency of the oscillation signal in response to the control signal, and a divider configured to divide the oscillation signal and output the feedback signal to the time-to-digital conversion circuit. 1. An all-digital phase-locked loop comprising:a time-to-digital conversion circuit configured to convert a phase difference between a reference signal and a feedback signal into digital value, and output a first data signal and a second data signal corresponding to the digital value;a digital loop filter configured to select one of the first data signal and the second data signal as valid data and output a control signal by operating the valid data and a first register signal;a digitally controlled oscillator configured to generate an oscillation signal and control a frequency of the oscillation signal in response to the control signal; anda divider configured to divide the oscillation signal and output the feedback signal to the time-to-digital conversion circuit.2. The all-digital phase-locked loop of claim 1 , wherein the time-to-digital conversion circuitoutputs the first data signal as a first digital value when the reference signal has an earlier phase than the feedback signal, andoutputs the second data signal as a second digital value when the reference signal has a later phase than the feedback signal. ...

RADAR TARGET DETECTION SYSTEM FOR AUTONOMOUS VEHICLES WITH ULTRA-LOW PHASE NOISE FREQUENCY SYNTHESIZER

An object detection system for autonomous vehicle, comprising a radar unit and at least one ultra-low phase noise frequency synthesizer, is provided. The radar unit configured for detecting the presence and characteristics of one or more objects in various directions. The radar unit may include a transmitter for transmitting at least one radio signal; and a receiver for receiving the at least one radio signal returned from the one or more objects. The ultra-low phase noise frequency synthesizer may utilize Clocking device, Sampling Reference PLL, at least one fixed frequency divider, DDS and main PLL to reduce phase noise from the returned radio signal. This proposed system overcomes deficiencies of current generation state of the art Radar Systems by providing much lower level of phase noise which would result in improved performance of the radar system in terms of target detection, characterization etc. Further, a method for autonomous vehicle is also disclosed. 1. An autonomous vehicle system , comprising: a). at least one transmitter for transmitting at least one radio signal to the at least one object;', 'b). at least one receiver for receiving the at least one radio signal returned from the at least one object;', (i) at least one clocking device configured to generate at least one clock signal of at least one clock frequency;', (a) at least one sampling phase detector configured to receive the at least one clock signal and a single reference frequency to generate at least one first analog control voltage; and', '(b) at least one reference Voltage Controlled Oscillator (VCO) configured to receive the at least one first analog control voltage or at least one second analog control voltage to generate the single reference frequency, wherein at least one digital control voltage controls one of the at least one first analog control voltage or the at least one second analog control voltage received by the at least one reference VCO;, '(ii) at least one sampling Phase ...

Method and Radio Network Node for Compensation for Local Oscillator Pulling or Pushing

Disclosed is a method and a radio network node for compensating for local oscillator pulling or pushing. The method comprises determining, in a digital domain, a correction phase for the local oscillator to offset a phase error caused by the local oscillator pulling or pushing. The method also comprises correcting a phase of the baseband signal in the digital domain using the correction phase to compensate for the local oscillator pulling or pushing With the proposed method and radio network node, the phase error caused by the local oscillator pulling or pushing could be diminished due to phase correction in the digital domain. 115-. (canceled)16. A method implemented by a radio network node for compensating for local oscillator pulling or pushing , the method comprising:determining, in a digital domain, a correction phase for the local oscillator to offset a phase error caused by the local oscillator pulling or pushing; andcorrecting a phase of the baseband signal in the digital domain, using the correction phase, to compensate for the local oscillator pulling or pushing.17. The method of claim 16 , wherein the determining the correction phase is implemented by an adaptive phase correction algorithm and the method further comprises iteratively performing the following steps until the phase error is minimized:receiving transmitter observing receiver signal fed back from a transmitting chain;determining the correction phase corresponding to the phase error based on a comparison between the baseband signal and the transmitter observing receiver signal; andcorrecting the phase of a subsequent baseband signal using the correction phase.18. The method of claim 17 , wherein the adaptive phase correction algorithm is a least mean square algorithm in which different step sizes are set according to different power levels of the baseband signals.19. The method of claim 16 , wherein the determining the correction phase is implemented by a look-up table in which a plurality of ...

METHOD OF ESTABLISHING AN OSCILLATOR CLOCK SIGNAL

A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate. 1. Method of establishing an output clock signal on a basis of an input timing reference , said method comprising:attenuating jitter of said input timing reference to produce a control signal,providing at least one intermediate clock signal on a basis of said control signal, at least one of said intermediate clock signals being justified to a local clock and being spectrum controlled, andproviding said output clock signal on a basis of said at least one intermediate clock signal by attenuating jitter of said at least one intermediate clock signal.2. Method of establishing an output clock signal according to claim 1 , whereby said at least one intermediate clock signal is an anisochronous signal.3. Method of establishing an output clock signal according to claim 1 , whereby at least a part of the jitter of said at least one intermediate clock signal comprises justification jitter originating from said justification to said local clock.4. Method of establishing an output clock signal according to claim 1 , whereby said justification and spectrum ...

Analog function generator with digital instrumentation methods for output signal

The present invention relates to a function generator made of one apparatus which stabilizes the amplitude of an oscillating triangle signal while canceling offset in the preferred embodiment. A second apparatus is provided which manipulates the stable triangle wave to generate signals of different shapes. The signal shape can be chosen using toggle switches, before setting the amplitude and offset level by an operator. The frequency can be manipulated by editing the original triangle oscillator circuit. A third apparatus measures the amplitudes, offset and pulse width using original software techniques based on specific conditioning circuits, which are coupled to a microcontroller. The microcontroller also measures the frequency of a square wave using hysteresis with two overlapping frequency measurement libraries. 1. A function generator based on triangle wave input from an oscillator with an adjustable oscillation frequency , the function generator comprising:An first apparatus for stabilizing a triangle wave by means positive and negative peak detection, by computing peak-to-peak amplitude and offset, and comparing these computed values to reference voltages, where the output of the comparators being amplified and integrated, and then fed-back to the input until offset and amplitude are stable and equal to fixed reference values.A second apparatus which converts the stable triangle wave output of the first apparatus into signals of different function but with the same amplitude, and offset. The signals being amplified or attenuated after conversion to make sure signal characteristics are identical. The signal shapes being switched from one to the other using toggle switches.A method to manipulate the chosen function by coupling the signal to a potentiometer, an amplifier, and a summing circuit to change the offset and peak-to-peak amplitude.A method of choosing the gain of the amplifier and summing circuit based on the overall gain, voltage ranges and saturation ...

SYNCHRONIZING CIRCUIT AND CLOCK DATA RECOVERY CIRCUIT INCLUDING THE SAME

A synchronizing circuit that is capable of generating a reproduced clock signal synchronized with a reference clock signal without causing a false lock and a clock data recovery circuit including the same are provided. To generate a clock signal synchronized with a reference clock signal associated with a data transition point that appears every predetermined period in an input data signal, the following false-lock avoidance processing is performed. That is, precharging of a first line is started when a phase control voltage applied to the first line by a charge pump falls below a lower-limit reference voltage, and the precharging of the first line is continued until the phase control voltage exceeds an upper-limit reference voltage. 1. A synchronizing circuit for generating a reproduced clock signal synchronized with a reference clock signal , the synchronizing circuit comprising:a charge pump for generating a phase control voltage having a voltage value associated with a phase difference between the reference clock signal and the reproduced clock signal and for delivering the resulting voltage to a first line;a phase control circuit for providing phase control to the reproduced clock signal depending on the phase control voltage; anda false-lock avoidance circuit for starting to precharge the first line when the phase control voltage falls below a lower-limit reference voltage and for continuing the operation of precharging the first line until the phase control voltage exceeds an upper-limit reference voltage.2. The synchronizing circuit according to claim 1 , wherein the false-lock avoidance circuit comprises:a first comparator for comparing magnitudes between the phase control voltage and the lower-limit reference voltage and generating a lower-limit-under signal when the phase control voltage is less than the lower-limit reference voltage;a second comparator for comparing magnitudes between the phase control voltage and the upper-limit reference voltage and ...

PHASE MEASUREMENT

The present disclosure relates to phase measurement circuitry operable based on a first clock signal having an intended clock frequency F and a second clock signal having an intended clock frequency F, the circuitry comprising: a delay line configured to receive the first clock signal, the delay line comprising a plurality of delay units each configured to cause a propagation delay, and the plurality of delay units connected in series along the length of the delay line and defining a series of positions therebetween through which signal edges of the first clock signal propagate over time; an edge detector configured to sample the delay line at successive sample times based on the second clock signal and to record at each sample time the position of a given signal edge of the first clock signal along the delay line; and a phase angle determiner configured to determine a phase angle per delay unit based on successive recorded said positions. 112. Phase measurement circuitry operable based on a first clock signal having an intended clock frequency F and a second clock signal having an intended clock frequency F , the circuitry comprising:a delay line configured to receive the first clock signal, the delay line comprising a plurality of delay units each configured to cause a propagation delay, and the plurality of delay units connected in series along the length of the delay line and defining a series of positions therebetween through which signal edges of the first clock signal propagate over time;an edge detector configured to sample the delay line at successive sample times based on the second clock signal and to record at each sample time the position of a given signal edge of the first clock signal along the delay line; anda phase angle determiner configured to determine a phase angle per delay unit based on successive recorded said positions.2. The circuitry according to claim 1 , wherein:the given signal edge is a rising edge, and optionally is the first rising ...

Loop parameter sensor using repetitive phase errors

A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.

TIME-TO-DIGITAL CONVERTER STOP TIME CONTROL

In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages. 1. A method , comprising:clocking a first clocked stage and a second clocked stage using a test clock signal;propagating a reference clock signal serially through the first and second clocked stages;selecting a STOP signal from among the outputs of the first and second clocked stages;providing the reference clock signal to a timer as a START signal;providing the STOP signal to the timer; andcalculating a difference between when the timer receives the START signal and when the timer receives the STOP signal using the timer; anddetermining a phase delay based on the difference.2. The method of claim 1 , wherein the clocking begins at a time corresponding to an edge of the reference clock source signal preceding a leading transition of the reference clock signal claim 1 , and the clocking ends at a time corresponding to a next transition of the reference clock signal.3. The method of claim 1 , further comprising is used to generating the test clock signal using the reference clock signal.4. The method of claim 1 , wherein the timer is a ring oscillator claim 1 ,5. The method of claim 5 , further ...

Resonator Device, Electronic Apparatus, And Vehicle

A resonator device includes a first resonator that generates a reference clock signal, a second resonator that generates a first clock signal having a frequency adjusted based on the reference clock signal, and a circuit device that includes a temperature sensor for performing temperature compensation on an oscillation frequency of the first resonator. The temperature sensor is disposed on the circuit device such that the first resonator overlaps the temperature sensor in a plan view. 1. A resonator device comprising:a first resonator configured to generate a reference clock signal;a second resonator configured to generate a first clock signal, the first clock signal having a frequency adjusted based on the reference clock signal; and a substrate; and', 'a temperature sensor configured to perform temperature compensation of an oscillation frequency of the first resonator,, 'a circuit device that includeswherein the first resonator is disposed on the circuit device so as to overlap the temperature sensor in a plan view.2. The resonator device according to claim 1 ,wherein the first resonator is supported on the circuit device by a first support, andthe second resonator is supported on the circuit device by a second support.3. The resonator device according to claim 2 ,wherein the first support electrically connects a terminal electrode of the first resonator and a first terminal of the circuit device, andthe second support electrically connects a terminal electrode of the second resonator and a second terminal of the circuit device.4. The resonator device according to claim 2 ,wherein the first support and the second support are conductive bumps.5. The resonator device according to claim 1 ,wherein a combined area of the first resonator and the second resonator is smaller than an area of the circuit device in the plan view.6. The resonator device according to claim 1 , further comprising:a third resonator configured to generate a second clock signal, the second clock ...

INTEGRATED CIRCUIT, METHOD, AND ELECTRONIC DEVICE FOR REDUCING EMI OF SIGNAL

An integrated circuit according to an embodiment of the disclosure may include a plurality of function blocks, a spread spectrum clock (SSC) generator that generates a spread spectrum clock based on a frequency modulation rate value, a clock distribution circuit that distributes the generated spread spectrum clock into the plurality of function blocks, a memory that stores predetermined frequency modulation rate values respectively corresponding to the plurality of function blocks, and a control circuit, and the control circuit may be configured to generate the spread spectrum clock based on a smaller frequency modulation rate value among a first frequency modulation rate value and a second frequency modulation rate value respectively corresponding to a first function block and a second function block, which are operating, from among the plurality of function blocks. Moreover, various embodiment found through the present disclosure are possible. 1. An integrated circuit comprising:a plurality of function blocks;a spread spectrum clock (SSC) generator configured to generate a spread spectrum clock based on a frequency modulation rate value;a clock distribution circuit configured to distribute the generated spread spectrum clock into the plurality of function blocks;a memory configured to store predetermined frequency modulation rate values respectively corresponding to the plurality of function blocks; anda control circuit, wherein the control circuit is configured to:generate the spread spectrum clock based on a smaller frequency modulation rate value among a first frequency modulation rate value and a second frequency modulation rate value respectively corresponding to a first function block and a second function block, which are operating, from among the plurality of function blocks.2. The integrated circuit of claim 1 , wherein the SSC generator includes a phase locked loop (PLL) generating a clock and a modulator modulating a frequency of the clock that the PLL ...

Clock data recovery circuit

Systems and methods for stabilizing clock data recovery (CDR) by filtering the abrupt phase shift associated with data pattern transition in the input signal. The CDR circuit includes a data pattern detector coupled to a data pattern filter. The data pattern detector is capable of detecting the data patterns of the input signal. Accordingly, the data pattern filter can selectively generate a filter indication indicating to freeze or suppress the CDR phase caused by data pattern transition. The filter indication can be incorporated to a phase error signal, a gain function, and/or the control voltage driving the VCO.

DIGITAL PHASE LOCKED LOOP

A phase locked loop circuit () includes a controllable oscillator () for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit () for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit () for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator () is driven by the outputs of the first and second phase detections circuits.

Charge Pump with Matched Currents

A charge pump provides matched charging and discharging currents. One transistor is connected to an input of a charge pump core while two transistors are connected to the other input of the charge pump core, with each of the transistors mirroring a reference transistor through different mirroring pathways so that current through the transistor of the first input is equal to the sum of currents through the two transistors of the second input. 1. A charge pump stage comprising:a charging and discharging charge pump core;a first transistor connected to a first input of the charging and discharging charge pump core;a second transistor connected to a second input of the charging and discharging charge pump core;a third transistor connected to the second input of the charging and discharging charge pump core; anda current mirroring circuit that controls the first transistor, the second transistor, and the third transistor according to a reference current to provide currents having substantially equal magnitude at the first input of the charge pump core and at the second input of the charge pump core.2. The charge pump stage of wherein the first transistor is a PMOS transistor claim 1 , the second transistor is an NMOS transistor claim 1 , and the third transistor is an NMOS transistor.3. The charge pump stage of wherein the first transistor is an NMOS transistor claim 1 , the second transistor is a PMOS transistor claim 1 , and the third transistor is a PMOS transistor.4. The charge pump stage of wherein the second transistor and the third transistor are connected in parallel between the second input and a common terminal claim 2 , and wherein gates of the first and second transistors are coupled to a reference transistor via different pathways so that currents in the second and third transistors mirror the reference current in the reference transistor.5. The charge pump stage of wherein the reference transistor is an NMOS transistor and at least one of the different ...

REFERENCE-FREQUENCY-INSENSITIVE PHASE LOCKED LOOP

A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. The phase locked loop may enable usage of both rising and falling edges of the crystal clock signal, based on the generated reference clock signal. The phase locked loop may perform an operation of the phase locked loop based on the enabling. The phase locked loop may perform a phase comparison function, based on both rising and falling edges of the crystal clock signal. By utilizing a sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of a charge pump in the phase locked loop, disturbance which is associated with duty cycle errors of the crystal clock signal. 1. A method , comprising: enabling, by the phase locked loop, usage of both rising and falling edges of a crystal clock signal generated by a crystal in the phase locked loop for an operation of the phase locked loop; and', 'performing the operation of the phase locked loop based on the enabling., 'in a phase locked loop2. The method according to claim 1 , comprising:generating a reference clock signal whose frequency is twice a frequency of the crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal; andenabling the usage of both rising and falling edges of the crystal clock signal based on the generated reference clock signal.3. The method according to claim 2 , comprising generating the reference clock signal utilizing a frequency doubler in the phase looked loop.4. The method according to claim 2 , comprising performing a phase comparison function claim 2 , based on both rising and falling edges of the crystal clock signal claim 2 , in the operation of the phase locked loop.5. The method according to claim 4 , comprising utilizing a sampled loop filter (SLPF) in the phase locked loop ...

FREQUENCY SYNTHESIZER

A frequency synthesizer includes: an oscillating section that generates a first signal; a frequency ratio measuring section that measures a frequency ratio of the first signal and a second signal by using the first signal and the second signal; a comparing section that compares the frequency ratio, which is measured by the frequency measuring section, with a target value of a frequency ratio; and a filter that is disposed on a preceding stage of the comparing section. A frequency of the first signal of the oscillating section is adjusted on the basis of a comparison result of the comparing section. 1. A frequency synthesizer comprising:an oscillating section that generates a first signal;a frequency ratio measuring section that measures a frequency ratio of the first signal and a second signal, which is different from the first signal, by using the first signal and the second signal;a comparing section that compares the frequency ratio, which is measured by the frequency ratio measuring section, with a target value of a frequency ratio; anda filter that is disposed on a succeeding stage of the frequency ratio measuring section,wherein a frequency of the first signal of the oscillating section is adjusted based on a comparison result of the comparing section, andthe frequency ratio measuring section has a frequency delta sigma modulation section that is configured to perform frequency delta sigma modulation on one of the first signal and the second signal based on the other of the first signal and the second signal.2. The frequency synthesizer according to claim 1 , further comprising:a control amount calculation section that is configured to calculate a control amount of the oscillating section based on the comparison result of the comparing section, a first circuit section that is configured to output a predetermined value times the comparison result of the comparing section;', 'a second circuit section that includes a plurality of circuits each of which is ...

Method And System For A Sampled Loop Filter In A Phase Locked Loop (PLL)

Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch. 1. A system , comprising: a phase frequency detector;', 'a sampled loop filter comprising a plurality of capacitors and at least one switch;', 'a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter; and', 'a frequency divider,', 'wherein the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero., 'a phase locked loop (PLL) for generating at least one clock signal, said PLL comprising2. The system of claim 1 , wherein said frequency divider is a fractional-N divider.3. The system of claim 1 , wherein a second switch in said sampled loop filter has switching times that are non-overlapping with switching times of said at least one switch.4. The system of claim 3 , comprising capacitors coupled to ground from each terminal of said second switch.5. The system of claim 1 , comprising capacitors coupled to ground from each terminal of said at least one switch.6. The system of claim 1 , wherein said sampled loop filter provides a filtered output ...

PHASE LOCKED LOOP CIRCUIT, INTEGRATED CIRCUIT, COMMUNICATION UNIT AND METHOD THEREFOR

A phase locked loop circuit includes a voltage controlled oscillator, VCO, configured to receive an oscillator tuning voltage; a phase detector configured to receive an input signal and a reference signal and generate a phase difference pulse signal that is varied in accordance with the oscillator tuning voltage; a loop filter having an input and an output; and a level shifter circuit coupled to an output of the phase detector and the loop filter input and configured to apply a level shift to the phase difference pulse signal such that the level shift is configured to compensate VCO gain and the loop filter averages the phase difference pulse signal to output an averaged signal to the VCO. 1. A phase locked loop , PLL , circuit comprising:a voltage controlled oscillator, VCO, configured to receive an oscillator tuning voltage;a phase detector configured to receive an input signal and a reference signal and generate a phase difference pulse signal that is varied in accordance with the oscillator tuning voltage;a loop filter having an input and an output; anda level shifter circuit coupled to an output of the phase detector and the loop filter input and configured to apply a level shift to the phase difference pulse signal such that the level shift is configured to compensate VCO gain and the loop filter averages the phase difference pulse signal to output an averaged signal to the VCO.2. The phase locked loop circuit of claim 1 , further comprising a logic inverter coupled to an output of the phase detector and an input of the level shifter circuit and configured to pre-compensate for a pulse inversion caused by the level shifter circuit claim 1 , wherein the level shifter circuit is configured to convert in a non-linear manner a change in a duty cycle of the phase difference pulse signal into the averaged signal to the VCO.3. The phase locked loop circuit of claim 1 , wherein the level shifter circuit is configured to generate a variable phase detector gain that ...

Phase lock loop with dynamic lock ranges

A phase look loop (PLL) device has a dynamic lock range that is based on a temperature measured during a calibration process. The PLL device includes a calibration circuit configured to receive a temperature reading corresponding to a junction temperature of the PLL device during the calibration process. Based on this temperature reading, the calibration circuit initiates a preset procedure that presets a control voltage of a voltage control oscillator in the PLL device. The preset procedure implements a calibration function defined by a slope with a numerator component and a denominator component. The numerator component corresponds to a range of the control voltage, whereas the denominator component corresponds to a range of ambient temperatures within which the PLL device operates.

DIGITAL MULTIPHASE HYSTERETIC POINT-OF-LOAD DC/DC CONVERTER

An autozeroed comparator controls a frequency fof the input voltage inputted to a DC/DC converter. A digital frequency synchronization circuit is connected to the autozeroed comparator so as to form a phase locked loop, wherein the DES circuit controls the hysteretic window of the autozeroed comparator so as to lock fto a clock reference frequency. A plurality of slave phase circuits may be connected to the master phase circuit including the DFS circuit and the autozeroed comparator. Duty cycle calibration circuits adjust a duty cycle signal applied to each of the slave phase circuits, in response to average current measured in the slave phase circuits, so that each slave phase circuit is synchronized with the master phase circuit. A 6 A 90.5% peak efficiency 4-phase hysteretic quasi-current-mode buck converter is provided with constant frequency and maximum ±1.5% current mismatch between the slave phases and the master phase. 1. A DC/DC converter , comprising: a bang bang phase frequency detector (PFD);', 'a PI compensator connected to the PFD, and', 'a Digital to Analog Converter connected to the PI compensator; and, 'a digital frequency synchronization circuit, includingan autozeroed comparator having a hysteretic window controlled by output current from the DAC in response a feedback frequency received from the autozeroed comparator, the autozeroed comparator detecting a continuous current mode (CCM)/discontinuous current mode (DCM) boundary during operation of the DC-DC converter;wherein:{'sub': 'sw', 'the autozeroed comparator controls the frequency f, of the input voltage inputted to the DC/DC converter in response to feedback comprising detection of the CCMIDCM boundary at an output of DC/DC converter; and'} the PFD compares the feedback frequency to a clock reference frequency CLK_ref and outputs a digital signal in response thereto,', 'the PI compensator increments the digital signal if the feedback frequency is greater than the CLK_ref or decrements the ...

Frequency modulation circuit, fm-cw radar, and high-speed modulation radar

A frequency modulation circuit [[110-1]] includes a VCO [[5]], a DIV [[19]], a MIX [[20]], a single-phase differential converter [[18]], and a signal processing circuit [[6]]. The signal processing circuit [[6]] performs differential arithmetic processing of an intermediate frequency signal with a program of a microcomputer according to a quadrature demodulation scheme and, thereafter, measures a frequency from phase information, performs n-th order polynomial (n is an integer equal to or larger than 2) approximation on time-frequency data of an IF signal output by a chirp modulation control voltage after inverse function correction, and performs modulation correction for correcting a time error.

CONNECTION INTERFACE CIRCUIT, MEMORY STORAGE DEVICE AND SIGNAL GENERATION METHOD

A connection interface circuit, a memory storage device and a signal generation method are disclosed. The connection interface circuit is configured to connect a memory controller to a volatile memory module. The connection interface circuit includes a phase locking circuit, a wire module and a signal interface. The signal interface is coupled between the wire module and the memory controller. The phase locking circuit is configured to receive a first clock signal from the memory controller. The phase locking circuit is further configured to generate a second clock signal according to the first clock signal and a delay feature of the wire module. The wire module is configured to provide a third clock signal to the signal interface according to the second clock signal. 1. A connection interface circuit for coupling a memory controller to a volatile memory module , the connection interface circuit comprising:a phase locking circuit, coupled to the memory controller;a wire module, coupled to the phase locking circuit; anda signal interface, coupled between the wire module and the memory controller,wherein the phase locking circuit is configured to receive a first clock signal from the memory controller,the phase locking circuit is further configured to generate a second clock signal according to the first clock signal and a delay feature of the wire module, andthe wire module is configured to provide a third clock signal to the signal interface according to the second clock signal.2. The connection interface circuit according to claim 1 , wherein the phase locking circuit is further configured to lock a phase difference between the first clock signal and the second clock signal at a target phase difference claim 1 , and the target phase difference is affected by the delay feature of the wire module.3. The connection interface circuit according to claim 2 , wherein the wire module is further configured to delay the second clock signal to generate the third clock signal ...

FREQUENCY COMPENSATOR, ELECTRONIC DEVICE AND FREQUENCY COMPENSATION METHOD

A frequency compensator, an electronic device, and a frequency compensation method are disclosed. The frequency compensator includes a control circuit and a frequency compensation circuit. The control circuit is configured to generate a frequency control word according to an initial frequency and an target frequency. The frequency compensation circuit is configured to receive an input signal of an initial frequency, and to generate and output an output signal of a compensated frequency according to the frequency control word and the input signal of the initial frequency. 1. A frequency compensator , comprising:a control circuit configured to generate a frequency control word according to an initial frequency and a target frequency; and receive an input signal of the initial frequency; and', 'generate and output an output signal of a compensated frequency according to the frequency control word and the input signal of the initial frequency., 'a frequency compensation circuit is configured to2. The frequency compensator of claim 1 , wherein the control circuit comprises:an input sub-circuit configured to obtain the initial frequency, the target frequency, and a frequency multiplication parameter;a calculation sub-circuit configured to generate the frequency control word according to the initial frequency, the target frequency, and the frequency multiplication parameter; andan output sub-circuit configured to output the frequency control word to the frequency compensation circuit.3. The frequency compensator of claim 2 , wherein the frequency control word is:{'br': None, 'i': F', 'K·N·C·f', 'f, 'sub': c', 'T, '=()/,'}{'sub': c', 'T, 'wherein F represents the frequency control word, N represents the frequency multiplication parameter, frepresents the initial frequency, frepresents the target frequency, K represents a positive integer greater than 1, and C is a constant.'}4. A frequency compensator of claim 3 , wherein C=1/K claim 3 , and the frequency control word is F ...

ELECTRONIC CIRCUIT AND CONTROL METHOD

An electronic circuit, includes: a first oscillator configured to generate a reference signal; a plurality of phase synchronization circuits, each including a second oscillator configured to generate an output signal having a frequency corresponding to an input, and a phase comparator configured to input, to the second oscillator, a signal corresponding to a phase difference between the output signal generated by the second oscillator and the reference signal generated by the first oscillator; and a controller configured to control relative phases of the reference signals input to the phase synchronization circuits from the first oscillator, based on the signals input to the corresponding second oscillators from the phase comparators in the phase synchronization circuits. 1. An electronic circuit , comprising:a first oscillator configured to generate a reference signal; a second oscillator configured to generate an output signal having a frequency corresponding to an input, and', 'a phase comparator configured to input, to the second oscillator, a signal corresponding to a phase difference between the output signal generated by the second oscillator and the reference signal generated by the first oscillator; and, 'a plurality of phase synchronization circuits, each including'}a controller configured to control relative phases of the reference signals input to the phase synchronization circuits from the first oscillator, based on the signals input to the corresponding second oscillators from the phase comparators in the phase synchronization circuits.2. The electronic circuit according to claim 1 ,wherein the controller controls at least one of phases of the reference signals, input to the phase synchronization circuits from the first oscillator, so that a phase difference between the signals input to the second oscillators is reduced.3. The electronic circuit according to claim 1 ,wherein, with respect to the phase synchronization circuits, the controller controls ...

SELF-CALIBRATING DESKEW FIXTURE

A deskew fixture includes first and second deskew probe points for contacting first and second probes, respectively, during deskew calibration, a signal generating circuit for generating a calibration signal provided to the first and second deskew probe points, and a feedback loop for automatically self-calibrating the deskew fixture. The feedback loop includes first and second analog to digital converters (ADCs) for digitizing the calibration signal at the first and second deskew probe points while contacting the first and second probes, respectively, to provide first and second digitized calibration signals, and a processing unit programmed to determine inherent skew of the deskew fixture between the first and second skew probe points using the first and second digitized calibration signals, and to provide the determined inherent skew to a test instrument for use in the deskew calibration of the first and second probes. 1. A deskew fixture for improving accuracy of a deskew calibration of a first probe and a second probe , performed by a test instrument , to be used in measuring electrical parameters of a device under test (DUT) , the deskew fixture comprising:a first deskew probe point configured to receive a first calibration signal while contacting the first probe;a second deskew probe point configured to receive a second calibration signal while contacting the second probe; and a first analog to digital converter (ADC) configured to digitize the first calibration signal at the first deskew probe point to provide a first digitized calibration signal;', 'a second ADC configured to digitize the second calibration signal at the second deskew probe point to provide a second digitized calibration signal; and', 'a processing unit programmed to determine inherent skew of the deskew fixture between the first and second skew probe points using the first and second digitized calibration signals, and to adjust timing of at least one of the first calibration signal or the ...

DELAY ESTIMATION DEVICE AND DELAY ESTIMATION METHOD

The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code. 1. A delay estimation device , comprising:a pulse generator, receiving a reference clock signal, outputting a first clock signal and a second clock signal in response to the reference clock signal;a digitally controlled delay line (DCDL), coupled with the pulse generator, wherein the DCDL receives the first clock signal from the pulse generator and generates a plurality of first phase signals based on the first clock signal;a time-to-digital converter (TDC), coupled with the pulse generator and the DCDL and generating a first timing code based on the first phase signals and the second clock signal; anda control circuit, coupled with the TDC, estimating a specific delay between the first clock signal and the second clock signal based on the first timing code.2. The delay estimation device according to claim 1 , wherein the pulse generator comprises:a first D flip-flop (DFF), having a data input terminal, a clock input terminal, and an output terminal, wherein the clock input terminal of the first DFF receives the first clock signal, the data input terminal of the first DFF receives a predetermined data ...

SEMICONDUCTOR APPARATUS AND DATA PROCESSING SYSTEM INCLUDING THE SEMICONDUCTOR APPARATUS

A semiconductor apparatus receives a first clock signal and a second clock signal. The semiconductor apparatus configured to perform a training operation internally, the training operation being an operation of internally correcting a phase difference between the first clock signal and the second clock signal by dividing the first clock signal to generate multi-phase signals, detecting phase difference between the second clock signal and the multi-phase signals, and adjusting phases of the multi-phase signals according to a result of the detecting of the phase difference. 1. A semiconductor apparatus configured to receive a first clock signal and a second clock signal provided externally from the semiconductor apparatus ,wherein the semiconductor apparatus is configured to perform a training operation by itself, the training operation being an operation of internally correcting a phase difference between the first clock signal and the second clock signal by dividing the first clock signal to generate multi-phase signals, detecting phase difference between the second clock signal and the multi-phase signals, and adjusting phases of the multi-phase signals according to a result of the detecting of the phase difference.2. The semiconductor apparatus of claim 1 , wherein the semiconductor apparatus includes:a dividing circuit configured to divide the first clock signal to generate the multi-phase signals;a phase detecting circuitry configured to detect the phases of the multi-phase signals with reference to the second clock signal to generate a plurality of phase detection signals;a phase control circuit configured to generate a phase control signal according to the plurality of phase detection signals; anda phase adjusting circuit configured to adjust the phases of the multi-phase signals according to the phase control signal to generate phase adjustment signals.3. The semiconductor apparatus of claim 1 , wherein the semiconductor apparatus is configured to adjust the ...

Clock Generator

A clock generator including a phase frequency detector configured to compare a phase and a frequency of a reference clock signal with a phase and a frequency of a first output clock signal and generate a detection signal based on a difference in the phases and frequencies of the clock signals; a loop filter configured to generate a first control voltage signal based on the detection signal; a first voltage controlled oscillator configured to generate and output a first output clock signal based on the first control voltage signal, a modulation filter configured to generate a modulation voltage signal based on the reference clock signal and generate a second control voltage signal by combining the modulation voltage signal and the first control voltage signal, and a second voltage controlled oscillator configured to generate and output a second output clock signal based on the second control voltage signal is provided. 1. A clock generator , comprising:a phase frequency detector configured to compare a phase and a frequency of a reference clock signal with a phase and a frequency of a first output clock signal and generate a detection signal based on a difference in the phases and frequencies of the clock signals;a loop filter configured to generate a first control voltage signal based on the detection signal;a first voltage controlled oscillator configured to generate and output a first output clock signal based on the first control voltage signal;a modulation filter configured to generate a modulation voltage signal based on the reference clock signal and generate a second control voltage signal by combining the modulation voltage signal and the first control voltage signal; anda second voltage controlled oscillator configured to generate and output a second output clock signal based on the second control voltage signal.2. The clock generator of claim 1 , wherein the first output clock signal is a non-spread spectrum clock signal claim 1 , and the second output ...

PLL CIRCUIT, METHOD, AND ELECTRONIC APPARATUS

A PLL circuit includes a frequency divider dividing an oscillation signal to generate a divided signal having a cycle of T/M (M: an integer greater than one); a phase comparator generating M reference signals by sequentially delaying a reference signal having a cycle of T one after another by a predetermined delay time and generating an Exclusive OR calculation result of the M reference signals and the divided signal; a loop filter generating a voltage signal based on the Exclusive OR calculation result input thereto; a voltage-controlled oscillator generating the oscillation signal by oscillating at a frequency in accordance with the voltage signal; and a control circuit adjusting the predetermined delay time to be equal to T/2M based on an Exclusive OR calculation result of at least two of the M reference signals. 1. A PLL circuit comprising:a frequency divider configured to divide an oscillation signal to generate a divided signal having a cycle of T/M (M: an integer greater than one);a phase comparator configured to generate M reference signals by sequentially delaying a reference signal having a cycle of T one after another by a predetermined delay time and generate an Exclusive OR calculation result of the M reference signals and the divided signal;a loop filter configured to generate a voltage signal based on the Exclusive OR calculation result input thereto;a voltage-controlled oscillator configured to generate the oscillation signal by oscillating at a frequency in accordance with the voltage signal; anda control circuit configured to adjust the predetermined delay time to be equal to T/2M based on an Exclusive OR calculation result of at least two of the M reference signals.2. The PLL circuit according to claim 1 , 'M two-input Exclusive OR circuits connected in series, and', 'wherein the phase comparator includes'}wherein, among the M two-input Exclusive OR circuits, a first-stage two-input Exclusive OR circuit calculates an Exclusive OR calculation ...

NOISE REDUCTION AND SPUR AND DISTORTION CANCELLATION TECHNIQUES

A wireless communication device can include an antenna configured to sense a radio frequency (RF) signal. The wireless communication device can include signal estimation circuitry configured to generate estimates of amplitude and frequency for unmodulated spurs within the RF signal. The wireless communication device can further include multi-tone generator circuitry coupled to the signal estimation circuitry and configured to generate a composite spur cancellation signal based on the estimates of amplitude and frequency for unmodulated spurs within the RF signal. The wireless communication device can further include adder circuitry configured to subtract the spur cancellation signal from the RF signal to generate a spur cancelled signal. 1. A wireless communication device , comprising:an antenna configured to detect a radio frequency (RF) signal;signal estimation circuitry configured to receive the RF signal and generate estimates of amplitude and frequency for unmodulated spurs within the RF signal;multi-tone generator circuitry coupled to the signal estimation circuitry and configured to generate a composite spur cancellation signal based on the estimates of amplitude and frequency for unmodulated spurs within the RF signal; andadder circuitry configured to subtract the composite spur cancellation signal from the RF signal to generate a spur cancelled signal.2. The wireless communication device of claim 1 , wherein the multi-tone generator circuitry includes processing circuitry configured to calculate the composite spur cancellation signal over a period claim 1 , the period based on a period of a fundamental spur signal within the RF signal.3. The wireless communication device of claim 2 , wherein the processing circuitry is configured to store parameters of the composite spur cancellation signal in a look-up table.4. The wireless communication device of claim 2 , wherein the frequencies of each of the unmodulated spurs are integer multiples of the frequency of ...

PHASE LOCKED LOOP CIRCUIT, PHASE LOCKED LOOP MODULE, AND PHASE LOCKED LOOP METHOD

Provided is a phase locked loop circuit that includes: a phase comparison section configured to compare a phase of a first clock signal and a phase of a second clock signal; a loop filter configured to generate a control voltage based on a comparison result by the phase comparison section; and a clock signal generation section configured to generate a clock signal having a frequency corresponding to the control voltage, and output the clock signal as the second clock signal. The loop filter includes a first resistor inserted between a first node on a signal path and a second node, a first capacitor inserted between the second node and a first DC power supply, a first switch inserted between the second node and a third node on the signal path, and a second capacitor inserted between the third node and a second DC power supply. 1. A phase locked loop circuit , comprising:a phase comparison section configured to compare a phase of a first clock signal and a phase of a second clock signal;a loop filter configured to generate a control voltage based on a comparison result by the phase comparison section; anda clock signal generation section configured to generate a clock signal having a frequency corresponding to the control voltage, and output the clock signal as the second clock signal,wherein the loop filter includesa first resistor inserted between a first node on a signal path and a second node,a first capacitor inserted between the second node and a first DC power supply,a first switch inserted between the second node and a third node on the signal path, anda second capacitor inserted between the third node and a second DC power supply.2. The phase locked loop circuit according to claim 1 , wherein the third node is connected to the first node.3. The phase locked loop circuit according to claim 2 , wherein the control voltage is a voltage at the first node.4. The phase locked loop circuit according to claim 2 , wherein the loop filter further includesa second ...

MULTI-OUTPUT PHASE DETECTOR

Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference. 1. A system , comprising:a digitally-controlled oscillator (DCO), arranged to produce an output signal having a frequency proportional to a value of a digital control word;a feedback divider arranged to provide a modified clock signal based on the output signal;a multi-output phase detector arranged to sense a phase difference between a reference clock signal and the modified clock signal and to output a multi-bit representation of the phase difference; anda digital loop filter arranged to form the digital control word based on the multi-bit representation.2. The system of claim 1 , wherein the multi-output phase detector is arranged to detect whether and to what extent a phase of the reference clock signal leads or lags a phase of the modified clock signal.3. The system of claim 1 , wherein the multi-bit representation comprises a binary word of predetermined length and includes information about a polarity of the phase difference and a magnitude of the phase difference.4. A method claim 1 , comprising:receiving a clock signal;receiving a reference clock signal;sensing a phase difference between the reference clock signal and the clock signal;determining a sign and a magnitude of the phase difference;outputting a multi-bit binary representation of the phase difference.5. The method of claim 4 , further comprising determining whether and to what extent the reference clock signal leads or lags the clock signal.6. The method of claim 4 , further comprising comparing the phase difference to a delay value of one or more delay components claim 4 , the one or more delay components representing a predetermined phase-mismatch range.7. The method of claim 6 , further comprising outputting the ...

SEMICONDUCTOR DEVICE AND TEST METHOD OF THE SAME

A semiconductor device having a function of detecting abnormality of a frequency of a clock includes a PLL circuit configured to generate a clock signal of the semiconductor device, a delay circuit in which an amount of delay of an output signal with respect to an input signal is equal to an amount of delay at a critical path of the semiconductor device, a first selection circuit configured to select an input to the delay circuit between a first input that is derived from the clock signal and a second input, which is the output signal of the delay circuit, a frequency dividing circuit configured to divide a frequency of the output signal of the delay circuit, and a second selection circuit configured to select as an input to the PLL circuit one of a reference signal and an output of the frequency dividing circuit. 1. A semiconductor device having a function of detecting abnormality of a frequency , comprising:a PLL circuit configured to generate a clock signal of the semiconductor device;a delay circuit in which an amount of delay of an output signal with respect to an input signal is equal to an amount of delay at a critical path of the semiconductor device;a first selection circuit configured to select an input to the delay circuit between a first input that is derived from the clock signal and a second input, which is the output signal of the delay circuit;a frequency dividing circuit configured to divide a frequency of the output signal of the delay circuit; anda second selection circuit configured to select as an input to the PLL circuit one of a reference signal and an output of the frequency dividing circuit.2. The device according to claim 1 ,wherein the delay circuit includes a first delay circuit having an amount of delay that is equal to the amount of delay at the critical path.3. The device according to claim 2 ,wherein the delay circuit includes a second delay circuit having an amount of delay that is equal to a variation range of the amount of delay at ...

DIGITAL PHASE LOCKED LOOP FREQUENCY ESTIMATION

A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a controlled oscillator signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase. 1. A Digital Phase Locked Loop (DPLL) , comprising:a Time-to-Digital Converter (TDC) configured to generate quantized phase values of a controlled oscillator signal; anda frequency estimation circuit configured to receive the quantized phase values, determine a wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.2. The DPLL of claim 1 , wherein the frequency estimation circuit comprises:a phase determination circuit configured to determine an accumulation of the quantized phase values having the wraparound phase.3. The DPLL of claim 1 , wherein the frequency estimation circuit comprises:a wraparound phase determination circuit configured to determine the wraparound phase of the quantized phase values.4. The DPLL of claim 3 , wherein the wraparound phase determination circuit comprises a decision circuit configured to determine the wraparound phase by comparing a difference between a current quantized phase value and a previous quantized phase value with an expected frequency.6. The DPLL of claim 5 , wherein the frequency estimation circuit comprises:an estimated frequency determination circuit configured to determine the estimated frequency by removing the wraparound phase from the quantized phase values.7. The DPLL of claim 5 , wherein a value of the period used in the wraparound phase determination is an estimate of the period of the controlled oscillator signal.8. The DPLL of claim 1 , wherein the estimated frequency is represented as follows:{'br': None, 'i': f', 'b', '*y', '=b', '*{tilde over (y)}', ...

SEMICONDUCTOR CIRCUIT

A semiconductor circuit includes a plurality of transmitting circuits, each of which receives a corresponding one of synchronized first clock signals input thereto and includes a first circuit outputting a third clock signal which is generated by dividing the frequency of an unsynchronized second clock signal and is synchronized with the first clock signal, a phase comparator comparing phases of the first clock signal and the third clock signal, and a reset signal generator setting, if a phase shift is detected by the phase comparator, the first signal at a first logic level for a predetermined period. The first circuit enters a reset state during a period in which the first signal is at the first logic level, and, when the first signal changes from the first logic level to a second logic level, is released from a reset state and generates the third clock signal synchronized with the first clock signal. 1. A semiconductor circuit comprising:a plurality of transmitting circuits, each transmitting circuit configured to receive a synchronized first clock signal, a frequency division circuit configured to output a third clock signal which is generated by dividing a frequency of an unsynchronized second clock signal and is synchronized with the first clock signal,', 'a phase comparator configured to compare phases of the first clock signal and the third clock signal to detect a phase shift therebetween, and', 'a reset signal generator configured to set, when the phase shift is detected by the phase comparator, a first signal at a first logic level for a predetermined period, and, 'wherein each of the plurality of transmitting circuits includes'}wherein the frequency division circuit is configured to enter a reset state during a period when the first signal is at the first logic level, andwherein when the first signal changes from the first logic level to a second logic level, the frequency division circuit is released from the reset state and generates the third clock ...

Dpll with adjustable delay in integer operation mode

Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.

Pll frequency synthesizer with multi-curve vco implementing closed loop curve searching using charge pump current modulation

A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a phase and frequency detector driving a charge pump and a digital control circuit configured to perform a closed loop curve search operation to select one of the operating curves in the multi-curve VCO and to perform a curve tracking operation using the selected operating curve, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit increases the charge pump current above a nominal current value during the closed loop curve search operation and set the charge pump current to the nominal current during the curve tracking operation.

FREQUENCY REGULATOR AND FREQUENCY REGULATING METHOD THEREOF, AND ELECTRONIC DEVICE

A frequency regulator and a frequency regulating method thereof, and an electronic device are disclosed. The frequency regulator includes: a signal processing circuit configured to generate a frequency control word according to a frequency regulating coefficient and an input frequency; and a frequency regulating circuit configured to receive the frequency control word and to generate and output an output signal having a target frequency according to the frequency control word. The frequency regulating coefficient is an arbitrary positive real number and is expressed as M.m, M is an integer portion of the frequency regulating coefficient and is a natural number, and m is a decimal portion of the frequency regulating coefficient. 1. A frequency regulator , comprising:a signal processing circuit, configured to generate a frequency control word according to a frequency regulating coefficient and an input frequency;a frequency regulating circuit, configured to receive the frequency control word and to generate and output an output signal having a target frequency according to the frequency control word,wherein the frequency regulating coefficient is an arbitrary positive real number and is expressed as M.m, M is an integer portion of the frequency regulating coefficient and is a natural number, and m is a decimal portion of the frequency regulating coefficient.2. The frequency regulator according to claim 1 , wherein the signal processing circuit comprises:an input sub-circuit, configured to obtain an input signal having the input frequency and the frequency regulating coefficient;a frequency detecting sub-circuit, configured to count the input signal within a preset period to obtain a count value of the input signal, and to determine the input frequency based on the count value; anda processing sub-circuit, configured to generate the frequency control word according to the input frequency and the frequency regulating coefficient.3. The frequency regulator according to ...

TIME-TO-DIGITAL CONVERTER STOP TIME CONTROL

In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages. 1. A method comprising:propagating, by a synchronizing block, a reference clock signal through a first clocked stage and a second clocked stage for a time using a test clock signal, the first clocked stage having a first output and the second clocked stage having a second output;selecting, by a multiplexer, as a stop signal, one of at least a signal from the first output, and a signal from the second output;receiving, by a timer, the reference clock signal and the stop signal; anddetermining, by a phase determination block, a phase delay between the reference clock signal and the test clock signal based on the reference clock signal and the stop signal.2. The method of claim 1 ,wherein the reference clock signal is generated using a higher-frequency reference clock source signal.3. The method of claim 1 , wherein the reference clock signal is used to generate the test clock signal.4. The method of claim 1 , wherein the timer is a ring oscillator claim 1 , the method further comprising propagating a signal through the ring oscillator beginning when the timer receives the reference clock signal and ...

Fractional n-pll circuit, oscillator, electronic device, and moving object

In order to appropriately set an operation range of a voltage controlled oscillator without excessively increasing a frequency at which delta-sigma modulation is performed, a fractional N-PLL circuit includes: a voltage controlled oscillator that is configured to set plural output frequency ranges; a frequency selection circuit that selects one output frequency range; a division circuit; and a division setting circuit that sets a division ratio of the division circuit. The division setting circuit performs, while the frequency selection circuit is searching for the plural output frequency ranges of the voltage controlled oscillator, the delta-sigma modulation at a frequency lower than a frequency after the frequency selection circuit terminates the search.

PREDICTION BASED DIGITAL CONTROL FOR FRACTIONAL-N PLLS

Methods and systems for phase correction include determining a phase error direction and generating a prediction for the phase error based on a sigma-delta error. It is determined whether the prediction agrees with the determined phase error direction. If the prediction does not agree, a phase correction is adjusted in accordance with the predicted phase error. 1. A fractional-N digital phase-locked loop (PLL) , comprising:a prediction module, configured to generate a predicted phase error based on a sigma-delta error and to output a phase error correction if the predicted phase error disagrees with an early/late signal based on a reference signal and a feedback signal;an integer divider, configured to divide by an integer value N a frequency of a phase-corrected multiple of the reference signal that is based on the output of the prediction module; anda sigma-delta module, configured to change the integer value N in accordance with a non-integer divide ratio.2. The PLL of claim 1 , wherein the prediction module comprises an integrator configured to integrate an instantaneous frequency error.3. The PLL of claim 2 , wherein the instantaneous frequency error is calculated as a difference between the integer value N for a given cycle and the divide ratio.4. The PLL of claim 2 , wherein the integrator is lossy claim 2 , such that DC components of an integrator output are removed.5. The PLL of claim 2 , wherein the prediction module is further configured to compare a sign of an integrator output with the early/late signal to determine agreement.6. The PLL of claim 5 , wherein the prediction module is further configured to output the integrator output if there is no agreement and to output zero if there is agreement.7. The PLL of claim 6 , wherein the phase-corrected multiple of the reference signal has a phase correction that is changed by an amount that is proportional to the output of the integrator.8. The PLL of claim 1 , further comprising a digital loop filter that ...

Reference-frequency-insensitive phase locked loop

A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. A sampled loop filter (SLPF) in the phase locked loop may capture charge from a charge pump (CHP) in the phase locked loop and the charge is captured at a frequency corresponding to the frequency of the reference clock signal. Opening a switch of the SLPF may hold the captured charge during a phase comparison and closing the switch may release the captured charge. The switch is controlled utilizing a control signal. By utilizing the SLPF in the phase locked loop, the phase locked loop may eliminate, at an output of the CHP, disturbance which is associated with duty cycle errors of the crystal clock signal.

APPARATUS AND METHODS FOR SYNCHRONIZING PHASE-LOCKED LOOPS

Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal. 1. An apparatus comprising:a first phase-locked loop (PLL) configured to receive a reference clock signal and to generate an output clock signal, wherein the first PLL comprises a programmable divider configured to receive a division signal, wherein a ratio of a frequency of the output clock signal to a frequency of the reference clock signal changes in relation to the division signal; an interpolator configured to generate an interpolated signal based on a fraction numerator signal and based on a modulus signal, wherein the first control circuit is configured to generate the division signal based on the interpolated signal;', 'a reset phase adjustment calculator configured to generate a phase adjustment signal and to receive an initialization signal, wherein the reset phase adjustment calculator comprises a counter configured to count a number of periods of the reference clock signal, wherein the counter is configured to be reset by the initialization signal, and wherein the phase adjustment signal is based on a count of the counter; and', 'a synchronization circuit configured to synchronize the first PLL in ...

SIGNAL PROCESSING APPARATUS AND ASSOCIATED METHOD

A signal processing apparatus includes: a signal conversion circuit, for performing a signal conversion operation on a reception signal to generate a first output signal according to a first clock signal, and performing the signal conversion operation on the reception signal according to a second clock signal to generate a second output signal; an amplitude adjustment circuit, coupled to the signal conversion circuit, for calculating an amplitude value of the reception signal according to the first output signal, and accordingly adjusting an amplitude of the reception signal; and a phase adjustment circuit, for adjusting a phase of the second clock signal according to the second output signal. 1. A signal processing apparatus , comprising:a signal conversion circuit, for performing a signal conversion operation on a reception signal according to a first clock signal to generate a first output signal;an amplitude adjustment circuit, coupled to the signal conversion circuit, for calculating an amplitude value of the reception signal according to the first output signal, and accordingly adjusting an amplitude of the reception signal and thereafter, the signal conversion circuit performs the signal conversion operation on the amplitude-adjusted reception signal according to a second clock signal to generate a second output signal; anda phase adjustment circuit, for adjusting a phase of the second clock signal according to the second output signal.2. The signal processing apparatus according to claim 1 , wherein the reception signal comprises a carrier signal claim 1 , and a frequency of the first clock signal is substantially a frequency four times of that of the carrier signal.3. The signal processing apparatus according to claim 1 , wherein the reception signal comprises a carrier signal claim 1 , and a frequency of the second clock signal is substantially equal to that of the carrier signal.4. The signal processing apparatus according to claim 1 , wherein the ...

LOCKED LOOP CIRCUIT WITH REFERENCE SIGNAL PROVIDED BY UN-TRIMMED OSCILLATOR

A circuit includes a frequency detector generating a comparison signal as a function of a comparison between a reference signal and a feedback signal. An oscillator generates an output signal as a function of the comparison signal. A frequency divider, in operation, divides the output signal by a division value to produce the feedback signal as having a frequency that is a multiple of a frequency of the reference signal. A frequency counter circuit measures the frequency of the reference signal and generates a count signal based thereupon. A control circuit adjusts the division value used by the frequency divider, in operation, based upon the count signal. 1. A circuit , comprising:a frequency detector configured to generate a comparison signal as a function of a comparison between a reference signal and a feedback signal;an oscillator configured to generate an output signal as a function of the comparison signal;a frequency divider configured to divide the output signal by a division value to generate the feedback signal as being a divided frequency version of the input having a frequency that is a multiple of a frequency of the reference signal;a frequency counter circuit configured to measure the frequency of the reference signal and to generate a count signal based thereupon; anda control circuit configured to adjust the division value used by the frequency divider, in operation, based upon the count signal.2. The circuit of claim 1 , wherein the frequency counter circuit is configured to determine the frequency of the reference signal by comparing the reference signal to a calibration signal.3. The circuit of claim 2 , wherein the frequency counter circuit compares the reference signal to the calibration signal by counting a number of pulses in the reference signal over a time window measured in clock cycles of the calibration signal.4. The circuit of claim 3 , wherein the time window is equal to a number of clock cycles of the calibration signal equal to 100 ...

APPARATUS AND METHODS FOR SYSTEM CLOCK COMPENSATION

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation. 1. An integrated circuit (IC) with system clock compensation , the IC comprising:a system clock generation circuit configured to generate a system clock signal based on a system reference signal; anda clock difference calculator configured to generate an error signal indicating a timing error between the system clock signal and a stable reference signal, wherein the clock difference calculator includes a closed loop difference calculation circuit configured to generate the error signal based on comparing the system clock signal and the stable reference signal with feedback, and an open loop estimator circuit configured to generate an open loop estimate of a frequency difference between the system clock signal and the stable reference signal, wherein the open loop estimator circuit is further configured to provide the open loop estimate to the closed loop difference calculation circuit so as to reduce a convergence time of the error signal.2. The IC of claim 1 , wherein the closed loop difference calculation circuit further includes a stable source selection circuit configured to select the stable reference ...

PHASE-LOCKED LOOP CIRCUIT

A phase-locked loop circuit includes: a division ratio control circuit controlling a division ratio of an output signal of a variable frequency divider on the basis of an addition signal of a negative feedback signal and a division ratio setting signal indicating the division ratio, in synchronization with a divided signal output from the variable frequency divider; a first phase detection circuit calculating a first phase detection signal indicating a phase of an output signal of a signal output circuit; a second phase detection circuit calculating a second phase detection signal indicating a phase of the output signal of a case where it is assumed that the division ratio control circuit controls the division ratio of the output signal of the variable frequency divider in synchronization with the reference signal; and a shift circuit generating a negative feedback signal from a difference between the first phase detection signal and the second phase detection signal, and outputting an addition signal of the generated negative feedback signal and the division ratio setting signal to the division ratio control circuit. 1. A phase-locked loop circuit comprising:a phase comparator detecting a phase difference between a reference signal and a divided signal;a signal output circuit outputting an output signal having a frequency corresponding to the phase difference detected by the phase comparator;a variable frequency divider generating the divided signal by dividing the output signal of the signal output circuit and outputting the divided signal of the output signal to the phase comparator;a division ratio control circuit controlling a division ratio of the divided signal to be output by the variable frequency divider on a basis of an addition signal in which a negative feedback signal is added to a division ratio setting signal indicating a division ratio, in synchronization with the divided signal output from the variable frequency divider;a first phase detection ...

NETWORK TAP WITH CLOCK ADAPTATION

A network tap includes a first network connector, a second network connector, a third network connector for connecting to a monitoring device, a phase locked loop, and circuitry. The circuitry is configured to extract a clock signal from a first signal on an output of one of the first and second network connectors, provide the clock signal to the phase locked loop, receive a reference clock signal derived from the recovered clock signal from the phase locked loop and clock a second signal on the input of the other one of the first and second network connectors using the received reference clock signal if a link has been established between a first network device and the first network connector and a link has been established between a second network device and the second network connector. 1. A network tap , comprising:a first network connector for connecting to a first network device;a second network connector for connecting to a second network device;a third network connector for connecting to a monitoring device;a phase locked loop;wherein an output of said first network connector is connected to an input of said second network connector, an output of said second network connector is connected to an input of said first network connector, an output of at least one of said first network connector and said second network connector is connected to a input of said third network connector, an output of said circuitry is connected to an input of said phase locked loop and an output of said phase locked loop is connected to an input of said circuitry; extract a clock signal from a first signal on an output of one of said first network connector and said second network connector;', 'provide said clock signal to said phase locked loop;', 'receive a reference clock signal derived from the recovered clock signal from said phase locked loop; and', 'clock a second signal on said input of the other one of said first network connector and said second network connector using said ...

Multi-channel delay locked loop

A multi-channel delay locked loop includes a global delay locked loop and a plurality of local delay locked loops. The global delay locked loop is configured to lock an input clock signal and output a global delay control signal corresponding to a delay amount of the input clock signal during a locking operation. Each of the plurality of local delay locked loops is configured to output a channel clock signal by locking the input clock signal, and initialize the delay amount of the input clock signal according to the global delay control signal.

PHASE TRACKER FOR A PHASE LOCKED LOOP

A phase locked loop includes a feedforward path receiving a reference signal having a reference frequency and outputting an output signal having an output frequency that is a function of the reference signal and a feedback signal. The phase locked loop further includes a feedback path having a divider circuit associated therewith that is configured to receive the output signal and generate the feedback signal having a reduced frequency based on a divide value of the divider circuit. The feedback signal is supplied to the feedforward path. The phase locked loop also includes a modulator circuit configured to receive modulation data and provide a divider control signal to the divider circuit to control the divide value thereof, and a phase tracker circuit configured to determine an amount of phase drift from an initial phase value of the output signal due to an interruption in a locked state of the phase locked loop. 1. A phase locked loop , comprising:a phase locked loop circuit configured to output an output signal based on a reference frequency and a current channel word; anda phase tracking circuit configured to determine a phase drift amount of the output signal based on a previous channel word and the current channel word of the phase locked loop circuit.2. The phase locked loop of claim 1 ,wherein the phase tracking circuit comprises an accumulator circuit that accumulates a difference between an input sequence and the previous channel word,wherein the input sequence includes the current channel word and modulation data, andwherein the accumulated difference represents the phase drift amount.3. The phase locked loop circuit of claim 1 , wherein the phase tracking circuit comprises:a first calculation circuit configured to calculate a frequency control word based on the current channel word and modulation data;a second calculation circuit configured to determine a difference between the frequency control word and the previous channel word, wherein the difference ...

INJECTION LOCKED OSCILLATOR

An injection locked frequency divider includes a ring oscillator, an input terminal, an output terminal and a control voltage terminal. The ring oscillator has a three-stage cascade connection of a first amplification circuit including an N-channel MOS type transistor and P-channel MOS type transistors, a second amplification circuit configured in the same manner as the first amplification circuit and a third amplification circuit configured likewise. A high frequency signal is input to a gate terminal of each P-channel MOS type transistor. A predetermined DC control voltage is supplied to a gate terminal of each P-channel MOS type transistor. 1. An injection locked oscillator comprising:a ring oscillator including a cascade connection of (2n+1) stages (n is an integer of 1 or more) of amplification circuits each having an N-channel MOS type transistor, a first P-channel MOS type transistor and a second P-channel MOS type transistor,wherein a high frequency signal is input to a gate terminal of the first P-channel MOS type transistor in each of the (2n+1) amplification circuits; andwherein a predetermined DC control voltage is supplied to a gate terminal of the second P-channel MOS type transistor in each of the (2n+1) amplification circuits.2. The injection locked oscillator according to claim 1 , further comprising:switches which are provided for the amplification circuits respectively so that the predetermined DC control voltage to be input to the gate terminal of the second P-channel MOS type transistor in each of the amplification circuits is switched to the high frequency signal and the high frequency signal is supplied thereto in accordance with the amplitude of the high frequency signal.3. An injection locked oscillator comprising:a ring oscillator including a cascade connection of (2n+1) stages (n is an integer of 1 or more) of amplification circuits each having an N-channel MOS type transistor and a P-channel MOS type transistor;a first N-channel MOS type ...

PHASE COMPARISON DEVICE AND DLL CIRCUIT

A phase detection range is enabled to be expanded to an arbitrary number of times of a cycle of a reference clock, and in the case of application to a DLL circuit, an operation cycle is enabled to be freely selected. A phase comparison device includes a divider that generates a division clock obtained by receiving a reference clock and dividing it by two; an inverter that inverts a phase of the division clock to generate a division inverted clock; a DFF circuit that synchronizes the division inverted clock with a delay clock to generate a synchronized clock; a DFF circuit that synchronizes the clock with the feedback clock to generate a final synchronized clock; and a phase comparator that receives the division clock and the final synchronized clock to compare phases of the division clock and the final synchronized clock. 17-. (canceled)8. A phase comparison device , which compares a phase of a first clock with a phase of a second clock having the same frequency as the first clock and delayed from the first clock just by a delay amount D1 , the phase comparison device comprising:a divider that generates a division clock obtained by receiving said first clock and dividing the first clock by N, N being a positive integer not smaller than two;an inverter that inverts a phase of said division clock to generate a division inverted clock;a first synchronizing section to synchronize said division inverted clock sequentially with delay clocks in the number of m, m being a positive integer not smaller than N−1, to generate a synchronized clock, the delay clocks having the same frequencies as said first clock and whose delay amounts from said first clock increase by 2π each at the maximum within a range smaller than said delay amount D1 when one cycle of said first clock is regarded as 2π;a second synchronizing section to synchronize said synchronized clock with said second clock to generate a final synchronized clock; anda phase comparator that receives said division clock ...

CIRCUIT DEVICE, OSCILLATOR, ELECTRONIC APPARATUS, AND VEHICLE

A circuit device includes first and second output signal lines from which first and second output signals constituting differential output signals are output, and first to n-th output drivers coupled to the first and second output signal lines. In a first mode, i number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on first and second input signals constituting differential input signals. In a second mode, j number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on the first and second input signals. 1. A circuit device comprising:a first output signal line from which a first output signal constituting differential output signals is output;a second output signal line from which a second output signal constituting the differential output signals is output; andfirst to n-th output drivers for differential input and differential output that are coupled to the first output signal line and the second output signal line, n being an integer of 2 or more, whereinin a first mode, i number of output drivers of the first to n-th output drivers drive the first output signal line and the second output signal line based on a first input signal and a second input signal constituting differential input signals, i being an integer of 1≤i≤n, andin a second mode, j number of output drivers of the first to n-th output drivers drive the first output signal line and the second output signal line based on the first input signal and the second input signal, j being an integer of 1≤j≤n and j≠i.2. The circuit device according to claim 1 , whereinthe first to n-th output drivers includeoutput drivers of a first group including drive current sources that apply drive currents each having a current value Is, andoutput drivers of a second group including drive current sources that apply drive currents each having a current value a×Is, a being an integer of 2 or more.3. The ...

Precision High Frequency Phase Adders

An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit. 1. An electronic circuit comprising:a differential multiplier circuit with a first differential input, a second differential input, and a differential output; anda folded cascode amplifier having a differential input connected to the differential output of the differential multiplier circuit.2. The electronic circuit of claim 1 , wherein the folded cascode amplifier includes a current source section for generating bias currents and wherein the differential multiplier circuit and the folded cascode amplifier are electrically connected together such that the bias currents that are generated by the current source section are shared by both the folded cascode amplifier and the differential multiplier circuit.3. The electronic circuit of claim 2 , wherein the differential multiplier circuit comprises a triode interface circuit including a transistor that during operation is biased to operate in a triode region.4. The electronic circuit of claim 3 , wherein the transistor is an MOS transistor.5. The electronic circuit of claim 2 , wherein the differential multiplier circuit comprises two triode interface circuits electrically connected together claim 2 , and wherein each of the two triode ...

HIGH-RESOLUTION AND AGILE FREQUENCY MEASUREMENT

An apparatus for generating a frequency estimate of an output signal includes a reference signal generator configured to generate a reference clock signal. The apparatus includes frequency estimation circuitry configured to generate a cycle count based frequency estimation of the output signal based on the reference clock signal and a clock cycle count of the output signal. The frequency estimation circuitry further generates a fractional frequency estimation of the output signal based on the reference clock signal and a plurality of time-to-digital conversion phase samples of the output signal. The frequency estimation circuitry further generates the frequency estimate of the output signal using the cycle count based frequency estimation within a range and a frequency error determined from the fractional frequency estimation. The plurality of time-to-digital conversion phase samples and the cycle count based frequency estimation use a same number of reference clock cycles of the reference clock signal. 1. An apparatus to generate a frequency estimate of an output signal , the apparatus comprising:a reference signal generator configured to generate a reference clock signal; and{'claim-text': ['generate a cycle count based frequency estimation of the output signal based on the reference clock signal and a clock cycle count of the output signal;', 'generate a fractional frequency estimation of the output signal based on the reference clock signal and a plurality of time-to-digital conversion phase samples of the output signal; and', 'generate the frequency estimate of the output signal using the cycle count based frequency estimation within a range and a frequency error determined from the fractional frequency estimation,', 'wherein the plurality of time-to-digital conversion phase samples and the cycle count based frequency estimation use a same number of reference clock cycles of the reference clock signal.'], '#text': 'frequency estimation circuitry configured to ...

MEMORY DEVICE AND DIVIDED CLOCK CORRECTION METHOD THEREOF

A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data. 1. A memory device comprising:an internal clock generator that is configured to generate a plurality of internal clock signals by dividing a received clock signal, where each of the internal clock signals has a respective phase that is different from the phases of the other internal clock signals;a deserializer that is configured to use the internal clock signals to deserialize received serial test data;a data comparator that is configured to compare reference data with pieces of internal data that correspond to the deserialized serial test data; anda clock controller that is configured to correct a clock dividing start time point of the received clock signal based on a result of the comparison of the reference data with the pieces of internal data.23-. (canceled)4. The memory device of claim 1 , wherein the deserializer comprises a plurality of samplers that respectively receive the plurality of internal clock signals claim 1 , andwherein the plurality of samplers are configured to sample the serial test data based on the respective received internal clock signals to deserialize the serial test data.5. The memory device of claim 1 , wherein the received clock signal is a data strobe signal.6. The memory device of claim 1 , wherein the received clock signal is a data-dedicated clock signal.7. The ...

Time-to-digital system and associated frequency synthesizer

A time-to-digital system and associated frequency synthesizer are provided. The time-to-digital system receives a reference clock and a variable clock. The time-to-digital system includes a supplement circuit and a time-to-digital converter (TDC). The supplement circuit generates a delayed reference clock signal and at least one pulse of a variable clock ahead of a transition of the delayed reference clock signal. The delayed reference clock signal is generated according to a delay control signal and the reference clock signal. The delay control signal is determined in response to transitions of the variable clock, and frequency of the variable clock is significantly higher than frequency of the reference clock signal. Being coupled to the supplement circuit, the TDC receives the delayed reference clock signal and the at least one pulse of the variable clock and accordingly produces a TDC signal.

SYSTEM FREQUENCY DETECTOR

A system frequency detector includes an orthogonal coordinate signal generator generating an orthogonal two-phase voltage signal from a three-phase voltage signal of three-phase alternating current power of a power system by converting the three-phase voltage signal into a two-phase voltage signal orthogonal to the three-phase voltage signal, converting the two-phase voltage signal into a voltage signal of a rotating coordinate system, calculating a moving average of the voltage signal of the rotating coordinate system, and performing an inverse transformation of the voltage signal of the rotating coordinate system after calculating the moving average; and a frequency calculator including an angular frequency calculator calculating an angular frequency of the power system based on the two-phase voltage signal, and an arithmetic unit calculating a system frequency of the power system from the angular frequency, the frequency calculator further including a low-pass filter provided in series with the arithmetic unit.

REMOVING DETERMINISTIC PHASE ERRORS FROM FRACTIONAL-N PLLS

Methods and devices for phase adjustment include a phase detector that is configured to compare a reference clock and a feedback clock and to generate two output signals. A difference in time between pulse widths of the two output signals corresponds to a phase difference between the reference clock and the feedback clock. A programmable delay line is configured to delay an earlier output signal in accordance with a predicted deterministic phase error. An oscillator is configured to generate a feedback signal in accordance with the delayed output signal. A divider is configured to divide a frequency of the oscillator output by an integer N. The integer N is varied to achieve an average fractional divide ratio and the predicted deterministic phase error is based on the average divide ratio and an instantaneous divide ratio. 1. A phase-locked loop , comprising:a phase detector, configured to generate two output signals, wherein a difference in time between pulse widths of the two output signals corresponds to a phase difference between a reference clock and a feedback clock;a programmable delay line, configured to delay an earlier output signal in accordance with a predicted deterministic phase error;an oscillator configured to generate a feedback signal in accordance with the delayed output signal; anda divider configured to divide a frequency of the oscillator output by an integer N, wherein the integer N is varied to achieve an average fractional divide ratio.2. The phase-locked loop of claim 1 , wherein the predicted deterministic phase error is based on a difference between the average divide ratio and an instantaneous divide ratio.3. The phase-locked loop of claim 1 , wherein the programmable delay line comprises a fixed delay module and a programmable delay module claim 1 , wherein a signal input to the programmable delay module is selected as the signal having a greater delay.4. The phase-locked loop of claim 3 , wherein the fixed delay module has a fixed ...

INTEGRATED CIRCUIT DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

An integrated circuit device includes: a first oscillation circuit that oscillates a first resonator to generate a first clock signal with a first clock frequency; a second oscillation circuit that oscillates a second oscillation element to generate a second clock signal with a second clock frequency that is different from the first clock frequency; and a time-to-digital conversion circuit that converts a time into a digital value using the first and second clock signals. 1. An integrated circuit device comprising:a first oscillation circuit configured to oscillate a first resonator to generate a first clock signal with a first clock frequency;a second oscillation circuit configured to oscillate a second oscillation element to generate a second clock signal with a second clock frequency that is different from the first clock frequency; anda time-to-digital conversion circuit configured to convert a time into a digital value using the first and second clock signals.2. The integrated circuit device according to claim 1 , further comprising:a controller configured to control at least one of the first and second oscillation circuits.3. The integrated circuit device according to claim 2 ,wherein the controller is configured to control at least one of an oscillation frequency and a phase of an oscillation signal of at least the one oscillation circuit.4. The integrated circuit device according to claim 2 ,wherein the controller is configured to control at least the one oscillation circuit so that the first and second clock signals have a given frequency relation or a given phase relation.5. The integrated circuit device according to claim 4 ,{'b': '1', 'wherein the first clock frequency is f,'}{'b': '2', 'the second clock frequency is f, and'}{'b': 1', '2, 'the controller is configured to control at least the one oscillation circuit so that N/f=M/f,'}wherein N and M are mutually different integers equal to or greater than 2.6. The integrated circuit device according to ...

CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE CLOCK GENERATION CIRCUIT

A delay circuit including a first output clock generation circuit and a second output clock generation circuit. The first output clock generation circuit generates a first output clock signal by mixing phases of a first clock signal and a second clock signal based on an (n+1)-th generated delay control signal. The second output clock generation circuit generates a second output clock signal by mixing the phases of the first and second clock signals based on both an n-th generated delay control signal and the (n+1)-th generated delay control signal.

Semiconductor device including a clock adjustment circuit

Disclosed herein is a semiconductor device that includes a first circuit comprising a plurality of first logic elements coupled in cascade and configured, in response to first and second clock signals and a control signal, to produce control information that indicates a first number of the first logic elements through which the control signal has been propagated during a period defined by a first change in logic level of the first clock signal and by a second change in logic level of the second clock signal, the first and second changes occurring adjacently to each other in same directions as each other, and a second circuit comprising a delay circuit configured to receive the first clock signal and the control information and to produce a third clock signal by delaying the first clock signal by an amount responsive to the control information.

FREQUENCY MEASURING AND CONTROL APPARATUS WITH INTEGRATED PARALLEL SYNCHRONIZED OSCILLATORS

A frequency measuring and control apparatus includes a plurality of synchronized oscillators integrated in parallel into one programmable logic device. 1. An electronic frequency measuring and control apparatus , comprising a phase locked loop and a plurality of oscillators disposed in parallel on a single programmable logic device configured to apply a plurality of channel-specific synchronization factors to a digital phase difference signal upstream of phase accumulators.2. The apparatus of claim 1 , further comprising:an oscillating element;an oscillation sensor to sense oscillation of the oscillating element and generate an analog oscillation signal corresponding to the sensed oscillation of the oscillating element; andan analog-to-digital converter in communication with the oscillation sensor to convert the analog oscillation signal to a digital oscillation signal;wherein the phase locked loop compares the digital oscillation signal from the analog-to-digital converter with a digital reference oscillation signal and generate a digital phase difference signal, and wherein the plurality of oscillators is in downstream communication with the phase locked loop to receive the digital phase difference signal, wherein the oscillators include a plurality of phase accumulators to generate a plurality of digital phase signals for a corresponding plurality of channels and a plurality of phase-to-amplitude converters downstream of the phase accumulators to convert the plurality of digital phase signals into a plurality of digital amplitude signals for the corresponding plurality of channels.3. The apparatus of claim 2 , wherein the programmable logic device is also configured to apply a plurality of channel-specific frequency offsets to the digital phase difference signal upstream of the phase accumulators and downstream of the application of the plurality of synchronization factors.4. The apparatus of claim 2 , wherein the programmable logic device is also configured to ...