СПОСОБ И СИСТЕМА ПРЕОБРАЗОВАНИЯ ДАННЫХ

Группа изобретений относится к оптронным системам передачи сигналов и может быть использована для управления передачей сигналов через оптронную среду передачи. Техническим результатом является предотвращение одновременного осуществления связи двух устройств через оптронную среду. Устройство содержит оптрон и контроллер, соединенный с оптроном и сконфигурированный с возможностью приема попытки передачи от первого устройства, определения, передает ли уже второе устройство через оптрон, определения, находится ли прием попытки передачи вне периода мертвой зоны после возникновения включения питания, и передачи от первого устройства через оптрон, если второе устройство не осуществляет передачу и если период мертвой зоны уже истек. 2 н. и 8 з.п. ф-лы, 11 ил.

Двухканальный аналого-цифровой преобразователь

Изобретение относится к измерительной электронной технике и может использоваться для преобразования нескольких аналоговых сигналов в цифровые. Предложенный двухканальный аналого-цифровой преобразователь содержит ключ, одноканальный аналого-цифровой преобразователь, мультиплексор с двумя регистрами на своих выходах, а также формирователь импульсов коммутации, выход которого соединен с управляющим входом ключа и мультиплексора, при этом входами этого двухканального аналого-цифрового преобразователя являются входы каналов ключа, его выходами являются выходы регистров, выход одноканального аналого-цифрового преобразователя соединен с входом мультиплексора. В указанный преобразователь введен формирователь коротких импульсов и дополнительный ключ, включенный между выходом первого ключа и входом одноканального аналого-цифрового преобразователя, при этом второй вход дополнительного ключа закорочен, а управляющий вход этого дополнительного ключа соединен с выходом формирователя коротких импульсов ...

СПОСОБ И СИСТЕМА ПРЕОБРАЗОВАНИЯ ДАННЫХ

... 1. Оптронная система (900) передачи для управления передачей сигналов через оптронную среду передачи, при этом оптронная система (900) передачи содержит:оптрон (115); иконтроллер (920), соединенный с оптроном (115) и сконфигурированный с возможностью приема попытки передачи от первого устройства (905), определения, передает ли уже второе устройство (907) через оптрон (115), определения, находится ли прием попытки передачи вне периода мертвой зоны после возникновения включения питания, и передачи от первого устройства (905) через оптрон (115), если второе устройство (907) не осуществляет передачу, и если период мертвой зоны уже истек.2. Оптронная система (900) передачи по п.1, в которой контроллер (920) дополнительно сконфигурирован с возможностью задержки передачи первым устройством (905) через оптрон (115), пока второе устройство (907) не завершит передачу, если второе устройство (907) уже осуществляет передачу.3. Оптронная система (900) передачи по п.1, в которой контроллер (920) дополнительно ...

Analogue to digital converter

PARALLEL ANALOG-DIGITAL CONVERTER, WITH ERROR CORRECTION CIRCUIT

FLOATING-GATE REFERENCE CIRCUIT

Systems and methods are discussed for using a floating-gate MOSFET (520) as a programmable reference circuit. One example of the programmable reference circuit is a programmable voltage reference source (705), while a second example of a programmable reference circuit is a programmable reference current source (805). The programmable voltage reference source (705) and/or the reference current source (805) may be incorporated into several types of circuits, such as comparator circuits, current-mirror circuits (900), and converter circuits. Comparator circuits and currentmirror circuits are often incorporated into circuits such as converter circuits. Converter circuits include analog–to-digital converters (700, 175) and digital-toanalog converters (800, 100).

Repetitive cell matching technique for integrated circuits

An integrated-circuit A-to-D converter having repetitive cells which are designed to be matched, but which are subject to uncontrolled mismatches adversely affecting performance. In the disclosed embodiment, the cells all include resistors (of equal ohmic value) carrying currents (designed to be of equal value) producing corresponding output signals. To avoid the effects of cell mismatch on the output signals, a network of equal-valued resistors is added to the circuit, with each network resistor connected between corresponding ends of adjacent pairs of the cell resistors.

Voltage level detection circuit and voltage level detection method

In the circuit for detecting the voltage level of an analog signal, a conversion circuit converts an analog signal to digital signals by comparing the voltage level of the analog signal with a plurality of reference potentials. A filter circuit matches timings of at least either rising edges or falling edges of the digital signals with each other. This prevents malfunction in the voltage level detection.

MULTI-ZONE DATA CONVERTERS

Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

Sensing circuit and display apparatus having the same

A sensing circuit includes a first input selecting circuit connected to a first sensing line and a second sensing line, a first path setting circuit that sets a path of a first sensing signal received from the first sensing line or a path of a second sensing signal received from the second sensing line, a second path setting circuit that sets a path of a sensing reference voltage, a first switch matrix connected to the first path setting circuit and the second path setting circuit, a first mode setting circuit connected to a first output terminal of the first switch matrix, a first common sensing amplifier connected to the first mode setting circuit, a second mode setting circuit connected to a second output terminal of the first switch matrix, and a second common sensing amplifier connected to the second mode setting circuit.

COMPARATOR OFFSET CALIBRATION FOR A/D CONVERTERS

Способ аналого-цифрового преобразования и устройство для его осуществления

Изобретение относится к области электронно-вычислительной техники. Технический результат заключается в повышении быстродействия аналого-цифрового преобразования при существенном увеличении разрядности АЦП. Технический результат достигается за счет двухтактного аналого-цифрового преобразования входного сигнала, при этом на первом такте происходит преобразование входного сигнала в 2-х битный сигнал, по которому выбирается соответствующий АЦП с разрядностью n для второго такта преобразования, при этом все АЦП должны быть построены на основе метода одновременного считывания, суммарная разрядность АЦП составит N=4n+2, при этом время преобразования будет равно 2 тактовым интервалам, АЦП, имеющего разрядность 2 бита, дешифратора и 4 параллельных АЦП с разрядностью n, на первом такте первый АЦП определяет интервал амплитуд входного сигнала, а дешифратор – последовательность включения остальных 4-х АЦП на втором такте преобразования в зависимости от амплитуды входного сигнала. 2 н.п. ф-лы, 1 ил.

Analogdigitalwandler und Kodierer dazu

Mixed-signal circuitry and integrated circuit devices

Digital to analog converter

In a digital to analog converter control circuitry is interposed between digital circuitry and analog circuitry. The control circuitry has a plurality of individual clocked circuits (L1-Ln), each receiving one or more first digital signals (T1-Tn) and also receiving a clock signal (CLK). Each clocked circuit derives from the received first digital signal(s) at least one second digital signal (TCK1-TCKn) and applies that derived second digital signal to an analog-circuitry input at a time determined by the received clock signal. The control circuitry has a plurality of block buffer Circuits (B1-Bn) connected in common for receiving a basic timing signal (BCLK). Each clock buffer circuit derives from the basic timing signal a clock signal (CLK1-CLKn) for application to one or more corresponding ones of the clocked circuits (L1-Ln).

Mixed-signal circuitry and integrated circuit devices

MODIFIED, REPETITIVE CELL COMPARISON TECHNOLOGY FOR INTEGRATED CIRCUITS

Method and apparatus for offset cancellation in a wireless receiver

Method and apparatus for a frequency synthesizer having a compensated sigma delta modulator output signal

IDDQ-testing of bias generator circuit

A bias generator is tested in an IDDQ-scheme by applying each respective one of the bias voltages to a respective PFET that is individually gated by a respective NFET. This permits measuring the quiescent currents. Any deviation in the bias voltages is translated into a deviation of the quiescent current.

COMPARATOR OFFSET CALIBRATION FOR A/D CONVERTERS

An A/D converter includes at least one comparator array (COMP1-COMP7) for flash A/D conversion of an analog signal. Means (CCU, SW1-SW7) pro-vide, for each comparator in the array, a common reference signal to both comparator input terminals. Means (CCU, DAC1-DAC7) force each compara-tor in the array into the same logical output state. Finally, means (CCU, DAC1-DAC7) adjust the comparator trip-point for each comparator by a ramp signal until the logical output state is inverted.

LOW VOLTAGE FULLY DIFFERENTIAL ANALOG-TO-DIGITAL CONVERTER

The present invention is to provide a low voltage fully differential analog-to-digital converter. The converter consists of an input stage including a plurality of pre-amplifier differential input cells for producing pre-amplified signals, a successive processing stage for receiving pre-amplified signals from the input stages, and a decoder for output converted signals according to the signals from the successive processing stage. Each differential input cell includes first and second differential pre-amplifiers, a bias impedance, and an averaging impedance branch. The first and second differential pre-amplifiers include two transistors, respectively, and differentially amplify a set of input signals. One terminal of the bias impedance is connected to a high supplied voltage while the other terminal of the bias impedance is connected to the first and second output terminals through respective pieces of load bearing impedance in order to adjust output voltages of first and second output ...

Coding circuit

A coding circuit forming a 1-from-N code from an X-from-N code includes partial circuits in which each position of the X-from-N code forms an input value of a partial circuit. Each partial circuit is formed of three emitter-coupled transistor pairs, a current source connected to reference potential, level shift circuits, signal outputs and a symmetrical signal input. Each partial circuit is connected to the partial circuit with the next higher position of the X-from-N code as an input value and to the partial circuit with the next lower position of the X-from-N code as an input value.

Semiconductor circuit using feedback to latch multilevel data

PCT No. PCT/JP94/02258 Sec. 371 Date Jun. 28, 1996 Sec. 102(e) Date Jun. 28, 1996 PCT Filed Dec. 27, 1994 PCT Pub. No. WO95/18488 PCT Pub. Date Jul. 6, 1995A simple semiconductor circuit by which analog data or multilevel data can be fetched and stored. The circuit receives a first signal and converts the first signal into a second signal composed of multilevel. The second signal is fed back to the circuit. The circuit is constituted of a first circuit which converts the first signal into a signal group composed of multiple quantized signals and second circuit which converts the signal group into the second signal. In addition, the first or/and second circuits are constituted of one or more neuron MOS transistors.

Analog to digital converter

Mixed-signal circuitry and integrated circuit devices

A/D CONVERTER AND TESTING METHOD FOR THE CONVERTER

PURPOSE: To accurately test an A/D converter without being affected by noise by an inexpensive tester. CONSTITUTION: Resistors R1 to Rn connected in series are connected between a power source terminal 11 supplying high potential and a power source terminal 12 supplying low potential. The potential of each connecting point of the resistors R1 to R2 and an input signal Vin are inputted to voltage comparators C1 to Cn-1. An encoder 14 converts an analog signal into a digital based on the outputs of the voltage comparators C1 to Cn-1. A testing terminal 21 is connected to at least one of the respective connecting points of the resistors R1 to Rn. At the time of the test, a prescribed potential is impressed to the testing terminal 21. COPYRIGHT: (C)1995,JPO ...

A/D CONVERTER, SYSTEM AND COMPARATOR

PROBLEM TO BE SOLVED: To provide an A/D converter which can be operated in a high frequency and reduces power consumption in low operation frequencies. SOLUTION: The A/D converter is provided with a plurality of comparators for sampling an analog input potential during a first period and comparing the analog input potential with a reference potential during a second period respectively, an encoder for encoding the compared results by the comparators, and a control signal supply unit for generating a control signal specifying the first and second periods so that the length of the first period can be different from the length of the second period, and supplying the control signal to the plurality of comparators. COPYRIGHT: (C)2003,JPO ...

METHOD AND APPARATUS FOR ANALOG TO DIGITAL CONVERSION USING TIME-VARYING REFERENCE SIGNAL

PROBLEM TO BE SOLVED: To provide a method and apparatus for analog to digital conversion suitable to an automatic test device. SOLUTION: The method which converts an analog signal S(t) into a digital representation comprises a 1st step for generating N time-varying reference signals, where N is an integer equal to or greater than one, 2nd and 3rd steps for comparing an amplitude s(t) of the analog signal S(t) to an amplitude r(t) of each of reference signals R(t) to determine whether the analog signal amplitude s(t) is greater than, equal to, or less than the reference signal amplitudes r(t), and 4th and 5th steps for producing a timestamp each time the analog signal and the reference signal amplitudes s(t) and r(t) are equal, where the timestamp is a record of an amplitude equal-value event and the digital representation is a timestamp group. COPYRIGHT: (C)2003,JPO ...

A/D Wandler-Vorspannungsstromschaltkreis

Analog/digital Wandler

Referenzwertschaltung für die Vergleicher in einem Analog-Digital-Wandler

Integrierte Schaltung zur Erzeugung eines Reset-Signals

ANALOGUE-TO-DIGITAL CONVERTERS

COMPARATOR OFFSETKALLIBRATION FOR A/D CONVERTERS

CODIERSCHALTUNG.

INTEGRATED CIRCUIT FOR THE PRODUCTION OF A RESET OF SIGNAL

TWO BIT A /D TRANSDUCER WITH VERSATZLÍSCHUNG, IMPROVING COMMON MODE UNDER PRINTING AND SCHWELLENSENSITIVITAT

Sampling input stage with multiple channels

DIFFERENTIAL ANALOG-TO-DIGITAL CONVERTER WITH PERIODIC SWITCHING PATHS

L'invention concerne les convertisseurs analogique-numérique, et plus spécialement les convertisseurs de haute résolution et haute linéarité fonctionnant en mode différentiel. Le convertisseur possède un étage d'entrée différentiel recevant un signal d'entrée (Vinp, Vinn) à convertir et ayant deux sorties (S, S'). La chaîne de conversion comprend ensuite un étage suiveur-bloqueur (THA) et une chaîne de conversion (QUA, ENC) avec un circuit de codage (ENC) fournissant un code numérique correspondant au niveau de signal d'entrée. Le traitement de signal est entièrement différentiel. Selon l'invention, pour éviter un échauffement non symétrique des deux voies de traitement, on prévoit un circuit de commutation (SW) apte à commander une interversion périodique des niveaux des deux sorties différentielles de l'étage d'entrée, et un moyen de correction du code numérique, apte à modifier le code numérique en fonction de l'état d'interversion des sorties différentielles pour fournir un code numérique ...

Folding A/D converter

In a folding A/D converter, a comparison part CPM provides a plurality of comparison signals Sc1 . . . Sc9 in response to an input signal Si. The transients in the comparison signals Sc1 . . . Sc9 are mutually shifted and substantially overlap. Because of the overlap, only a relatively small input signal variation is needed to pass all the transients. A limiting part LIM effectively selects portions of the transients. A combining part CBM effectively multiplexes these selected portions into a folding signal Sf. The selection by the limiting part LIM prevents distortion of the folding signal Sf, despite the overlap.

Thermometer-to-adjacent bindary encoder

An encoder circuit converts a thermometer code into an equivalent adjacent binary code wherein only a single bit is changed to minimally increment or decrement the value of the binary code. The encoder logic is grouped so that the state of any single bit of the thermometer code can affect the state of one and only one bit of the binary code whereby when any least significant thermometer code bit is at an invalid logic level, the invalid level is propagated through the encoder circuit to only a single, least significant binary code bit, without the introduction of any logical errors. The invalid binary code bit is then stabilized to a valid level by one or more latches.

DATA TRANSLATION SYSTEM AND METHOD

A data translation system (100) for performing a non-linear data translation on a digitized AC signal is provided. The non-linear data translation system (100) includes an input for receiving the digitized AC signal, an output for outputting a non-linearly translated signal, and a processing system (104) coupled to the input and to the output. The processing system (104) is configured to receive the digitized AC signal, non-linearly translate the digitized AC signal using a predetermined transfer function to create the non-linearly translated signal, and transfer the non-linearly translated signal to the output.

BIT ERROR RATE TIMER FOR A DYNAMIC LATCH

A converter system, including a first converter that digitizes the a first portion of an input signal, the first converter including a comparator, a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator, a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer, and a combiner having inputs to generate a digital code from the digitized first and second portions.

COMPARATOR TRACKING CONTROL SCHEME WITH DYNAMIC WINDOW LENGTH

A comparator tracking scheme for an analog-to-digital converter (ADC) may implement a dynamic window size by varying, over time, a number of comparators powered up to convert an analog input signal to a digital output signal. A comparator-tracking scheme may be implemented, for example, in a controller coupled to a plurality of comparators in an ADC. For example, the controller may determine a window size for the ADC and determine a window position for the ADC. The controller may then activate comparators of the ADC within a window centered at the window position and having a width of the window size. The controller may determine a window size by analyzing an output of a filter. When the filter output indicates a rapidly changing analog input signal, the controller may dynamically increase a window size of the ADC, which may increase a number of comparators powered on.

Glitchless clock multiplexer controlled by an asynchronous select signal

A glitchless clock multiplexer controlled by an asynchronous select signal for use in GPS receivers is disclosed. A device in accordance with the present invention comprises a device for producing a clock signal, the clock signal being selected from a plurality of asynchronous frequency sources. A device in accordance with the present invention comprises a first frequency source, a second frequency source, a select signal, wherein the select signal is asynchronous with the first frequency source, and a multiplexer, which receives the first frequency source and the second frequency source, wherein the multiplexer selects as an output of the multiplexer one of the first frequency source and the second frequency source based on a value of the select signal, such that when the multiplexer switches between the first frequency source and the second frequency source, and between the second frequency source and the first frequency source, the transition is performed when the output of the multiplexer ...

СПОСОБ И СИСТЕМА ПРЕОБРАЗОВАНИЯ ДАННЫХ

Изобретение относится к области преобразования данных и может быть использовано для выполнения нелинейного преобразования данных над оцифрованным сигналом переменного тока. Техническим результатом является улучшение эффективности передачи сигнала. Система (100) нелинейного преобразования данных включает в себя вход для приема оцифрованного сигнала АС, выход для вывода нелинейно преобразованного сигнала и систему (104) обработки, соединенную с входом и с выходом. Система (104) обработки сконфигурирована с возможностью приема оцифрованного сигнала АС, нелинейного преобразования оцифрованного сигнала АС с использованием предварительно определенной передаточной функции, чтобы создать нелинейно преобразованный сигнал, причем предварительно определенная передаточная функция создает нелинейно преобразованный сигнал относительно предварительно определенной точки, и передачи нелинейно преобразованного сигнала на выход. 2 н. и 12 з.п. ф-лы, 11 ил.

Schaltung mit gemischten Signalen und Geräte integrierter Schaltungen

Delta sigma modulators with comparator offset noise conversion

Quantizers of delta sigma modulators include comparators to quantize a quantizer input signal. Each comparator compares a respective reference signal to the quantizer input signal. A logic processing module determines a quantizer output signal based upon the comparison. During subsequent periods of time, a comparator offset converter alters "reference signal-to-comparator input terminal" associations to reroute respective reference signals from one arrangement of comparator input terminals of at least two (2) of the comparators to a different arrangement of comparator input terminals. The comparator offset converter can randomly alter the reference signal-to-comparator input terminal associations. The comparator offset converter can maintain a 1 : 1 reference signal-to-comparator input terminal relationship. By maintaining the 1 : 1 ratio of reference signal-to-comparator input terminal and randomizing the reference signal-to-comparator input terminal associations, the comparator offset ...

Analogue to digital converter

CAPACITIVE PARALLEL ANALOGUE-DIGITAL CONVERTER

CROSS-COUPLED FOLDED CIRCUIT AND ANALOGDIGITALLY TRANSDUCER WITH SUCH FOLDED CIRCUIT

ADVANCED DIGITAL ANTENNA MODULE

Method and apparatus for comparator tree structure for fast acquisition of offsets induced in a wireless receiver

DATA TRANSLATION SYSTEM AND METHOD

A data translation system (100) for performing a non-linear data translation on a digitized AC signal is provided. The non-linear data translation system (100) includes an input for receiving the digitized AC signal, an output for outputting a non-linearly translated signal, and a processing system (104) coupled to the input and to the output. The processing system (104) is configured to receive the digitized AC signal, non-linearly translate the digitized AC signal using a predetermined transfer function to create the non-linearly translated signal, and transfer the non-linearly translated signal to the output.

The temperature measuring device, the integrated circuit and the temperature measuring method

다중 채널을 구비한 샘플링 입력 스테이지

... 아날로그 입력 스테이지는 m개의 차동 입력 채널을 구비하며, 여기서, m>1이다. 아날로그 입력 스테이지는 m개의 차동 입력 채널 중 하나를 선택하여 출력 신호를 제공하도록 구성된다. 아날로그 입력 스테이지는 n개의 동일한 선택 유닛들을 포함하며, 선택 유닛들의 각각은 m개의 차동 채널 입력부들 및 하나의 차동 출력부를 구비하고, n은 적어도 2m-1이다. 각 선택 유닛은 각자의 차동 멀티플렉서 유닛들을 통해 차동 입력 채널들 중 어느 것에도 결합하도록 동작 가능하고, 멀티플렉서 유닛들은 차동 입력 채널들 중 하나를 선택하고 그리고 선택된 차동 채널 입력부를 버터플라이 스위치를 통해 선택 유닛의 차동 출력부와 결합하도록 구동된다. n개의 선택 유닛들의 차동 출력 신호들이 결합하고, 이로써 선택된 채널 이외의 채널들의 원하지 않는 누화가 소거에 의해 제거된다.

ANALOG/DIGITAL CONVERTER

PURPOSE: An analog/digital converter is provided to improve efficiency of a device by reducing accumulation of the off-set voltage and to control the bit number of data output in series and the direction of output and to reduce consumption of power by reducing time to minimum, on which an analog circuit is operated. CONSTITUTION: An analog/digital converter includes a control block(40), a parallel analog/digital converter(50) and a parallel-serial converting logic control block(60). The control block(40) inputs the reference strobe signal(REF_STB), the reference clock signal(REF_CLK) and the bit number control signals(CONT_1, CONT_2) and generates the first and second internal clock signals(CLK_A, CLK_B) and the output direction control signal(CONT_3). The parallel analog/digital converter(50) converts the analog signal input with being synchronized to the first internal clock signal(CLK_A) into the parallel digital data. The parallel-serial converting logic control block(60) converts the ...

ANALOG/DIGITAL CONVERTING CIRCUIT AND CURRENT SUPPLY CIRCUIT

PURPOSE: An A/D(Analog/Digital) converting circuit and a current supply circuit are provided to reduce power consumption. CONSTITUTION: An A/D converting circuit comprises a comparator unit(210). The comparator unit includes a comparator control circuit portion(211) and chopper version comparators(1-7). The chopper version comparators are in an active state or in a dormant state according to the first and second set signals(CONT1A,CONT1B-CONT7A,CONT7B). The comparator control circuit portion logically proceeds the outputs(OUT1-OUT7) of the chopper version comparators in the last conversion. The first and second set signals are formed by the comparator control circuit portion. © KIPO 2004 ...

MULTI-BIT SAMPLING AND QUANTIZING CIRCUIT

Provided are, among other things, systems, apparatuses methods and techniques for performing multi-bit quantization. One such apparatus includes an input signal line; a first comparator having a first input coupled to the input signal line, a second input coupled to a first reference signal, and an output; a rectifier having an input coupled to the input signal line and also having an output; and a second comparator having a first input coupled to the output of the rectifier, a second input coupled to a second reference signal, and an output, with the first comparator and the second comparator being clocked so as to produce sequences of quantized samples at substantially the same times.

Sampling input stage with multiple channels

An analog input stage has m differential input channels, wherein m>1. The analog input stage is configured to select one of the m differential input channels and provide an output signal. The analog input stage has n identical selection units each having m differential channel inputs and one differential output, wherein n is at least 2m1. Each selection unit is operable to be coupled to any of the differential input channels through respective differential multiplexer units, wherein the multiplexor units are driven to select one of the differential input channels and couple the selected differential channel input through a butterfly switch unit with the differential output of the selection unit. The differential output signals of the n selection units are combined whereby unwanted crosstalk from channels other than a selected channel are removed by cancellation.

Flash-successive approximation analog-to-digital converter

This invention relates to a flash-successive approximation analog-to-digital converter combining the low speed, high resolution successive approximation method of conversion with the high speed, low resolution flash method of conversion, which provides the advantages of higher conversion speed with no increased conversion error.

АНАЛОГО-ЦИФРОВОЙ ПРЕОБРАЗОВАТЕЛЬ СТОЛБЦОВ, СПОСОБ АНАЛОГО-ЦИФРОВОГО ПРЕОБРАЗОВАНИЯ СТОЛБЦОВ, ТВЕРДОТЕЛЬНЫЙ ЭЛЕМЕНТ ПОЛУЧЕНИЯ ИЗОБРАЖЕНИЙ И СИСТЕМА КАМЕРЫ

... 1. Твердотельное устройство формирования изображения, содержащее:секцию обработки столбцов, содержащую секцию защелки битов низкого уровня,при этом секция защелки битов низкого уровня выполнена с возможностью приема выходного сигнала компаратора от компаратора и выходного сигнала счета от счетчика и фиксации значения счета.2. Твердотельное устройство формирования изображения по п.1, в которомсчетчик выполнен с возможностью вывода выходного сигнала счета, так чтобы выходной сигнал счета перемещался только на один бит.3. Твердотельное устройство формирования изображения по п.2, в которомсчетчик является счетчиком кода Грея.4. Твердотельное устройство формирования изображения по п.3, в которомсекция защелки битов низкого уровня содержит множество схем защелки битов низкого уровня.5. Твердотельное устройство формирования изображения по п.4, в которомсекция обработки столбцов дополнительно содержит секцию счета битов высокого уровня,при этом секция счета битов высокого уровня выполнена с возможностью ...

СПОСОБ И СИСТЕМА ПРЕОБРАЗОВАНИЯ ДАННЫХ

... 1. Система (100) преобразования данных для выполнения нелинейного преобразования данных над оцифрованным сигналом переменного тока (AC), причем система (100) преобразования содержит: ! вход для приема оцифрованного сигнала AC; ! выход для выведения нелинейно преобразованного сигнала; и ! систему (104) обработки, соединенную с входом и с выходом и сконфигурированную с возможностью приема оцифрованного сигнала AC, нелинейного преобразования оцифрованного сигнала AC с использованием предварительно определенной передаточной функции, чтобы создать нелинейно преобразованный сигнал, и передачи нелинейно преобразованного сигнала на выход. ! 2. Система (100) преобразования данных по п.1, в которой предварительно определенная передаточная функция создает нелинейно преобразованный сигнал относительно предварительно определенной опорной точки. ! 3. Система (100) преобразования данных по п.1, в которой предварительно определенная передаточная функция сконфигурирована с возможностью альтернативно осуществлять ...

Analog-Digital-Signal-Umwandlungsverfahren- und Vorrichtung

Ein Verfahren und eine Vorrichtung wandeln ein analoges Signal in eine Quantität N von digitalen Signaldarstellungen um. Das Verfahren weist den Schritt des Vergleichens eines Amplitudenwerts im analogen Signal mit einer Quantität N von Referenzamplitudenwerten auf, um zu bestimmen, ob der analoge Wert größer als oder kleiner als der Referenzwert ist, wenn N eine Ganzzahl >= 1 ist. Das Verfahren weit ferner den Schritt des Produzierens eines logischen Pegels in einem digitalen Signal entsprechend der Bestimmung im Schritt des Vergleichens auf. Das Verfahren wandelt im wesentlichen das analoge Signal in eine Zeitdarstellung um und wandelt dann die Zeitdarstellung in eine digitale Darstellung um. Die Vorrichtung weist eine Quantität N von Komparatoren auf, die jeweils verbunden sind, um das analoge Signal zu empfangen, separat, um einen anderen der N Referenzwerte zu empfangen und um das digitale Signal zu produzieren. Das analoge Signal wird aus der digitalen Darstellung rekonstruiert.

Quantisierer

Quantisierer mit:einem Signal-zu-Phase-Wandler, der dazu ausgebildet ist, ein Phasensignal entsprechend einem Eingangssignal zu erzeugen;einem Phasendifferenz-Digitalisierungsblock, der dazu ausgebildet ist, ein differenzierten Abtastungen des Phasensignals entsprechendes Quantisierungsausgangssignal zu erzeugen, wobeidas von dem Signal-zu-Phase-Wandler erzeugte Phasensignal sinusförmig ist,der Signal-zu-Phase-Wandler dazu ausgebildet ist, eine Vielzahl von Phasensignalen entsprechend dem Eingangssignal zu erzeugen, und wobei der Phasendifferenz-Digitalisierungsblock dazu ausgebildet ist, eine Vielzahl von differenzierten Abtastungen des Phasensignals entsprechende Quantisierungsausgangssignale zu erzeugen, undder Signal-zu-Phase-Wandler zwei steuerbare Oszillatoren jeweils mit einem nicht-differenziellen Phasenausgang aufweist.

MEMBRANE DIGITAL ANALOG SWITCHES

A membrane digital analog switch includes an input button surface adapted to receive an input pressure from a user, and a digital switch positioned below the input button surface to generate a digital switch activation signal when the received pressure on the input button surface is greater than or equal to a specified digital pressure threshold. The membrane digital analog switch also includes an analog switch adapted to generate an analog switch activation signal when the received pressure on the input button surface is greater than or equal to a specified analog pressure threshold. The specified analog pressure threshold is greater than the specified digital pressure threshold, the digital switch activation signal is a binary digital signal, and the analog switch activation signal is variable and corresponds to an analog sensed value of the received pressure on the input button surface.

DIFFERENTIAL ANALOG-TO-DIGITAL CONVERTER WITH PERIODIC SWITCHING PATHWAYS

PARALLEL ANALOG-TO-DIGITAL CONVERTER, HAS CIRCUIT OF CORRECTION Of ERROR

Advanced digital antenna module

An Advanced Digital Antenna Module (ADAM) for receiving and exciting electromagnetic signals. The ADAM ASIC integrates a complete receiver/exciter function on a monolithic SiGe device, enabling direct digital-to-RF (Radio Frequency) and RF-to-digital transformations. The invention includes an improved analog-to-digital converter (ADC) (10) with a novel active offset method for comparators. The novel ADC architecture (10) includes a first circuit (12, 14) for receiving an input signal; a second circuit (18) for setting a predetermined number of thresholds using a predetermined number of preamplifiers (60) with weighted unit current sources (66) in each of the preamplifier outputs; and a third circuit (20) for comparing the input to the thresholds. In the preferred embodiment, the ADC (10) includes trimmable current sources (66). The ADC (10) of the present invention also includes an improved comparator circuit (62). The novel comparator (62) includes split load resistors, pairs R25 (active ...

Systems and methods for comparator calibration

The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.

Method for increasing rate at which a comparator in a metastable condition transitions to a steady state

A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.

ANALOG TO DIGITAL CONVERTER WITH AMPLIFIER

FLOATING-GATE REFERENCE CIRCUIT

Быстродействующий параллельный АЦП

Изобретение относится к радиоэлектронике, предназначено для аналого-цифрового преобразования аналоговых сигналов, и может быть использовано в системах радиолокации и связи. Технический результат заключается в повышении быстродействия преобразования аналогового сигнала. Параллельный АЦП содержит высокоскоростной ключ, последовательно соединенные счетчик, выполненный с коэффициентом счета четыре, и дешифратор; первый, второй, третий, четвертый АЦП, причем выходы дешифратора подключены к тактовым входам АЦП, при этом входной сигнал одновременно подается на входы всех АЦП. 1 ил.

СПОСОБ АНАЛОГО-ЦИФРОВОГО ПРЕОБРАЗОВАНИЯ НАПРЯЖЕНИЯ

Изобретение относится к аналого-цифровому преобразованию напряжения. Технический результат - минимизация потерь информации о форме преобразуемого напряжения в процессе параллельного аналого-цифрового преобразования напряжения. Для этого предложен способ аналого-цифрового преобразования напряжения, заключающийся в том, что формируют уровни опорного напряжения в диапазоне изменения преобразуемого напряжения; нумеруют их; формируют импульсы напряжения с известной опорной частотой; сравнивают преобразуемое напряжение со всеми уровнями опорного напряжения; регистрируют и нумеруют каждый момент равенства преобразуемого напряжения уровню опорного напряжения; считают количество импульсов опорной частоты от момента равенства преобразуемого напряжения уровню опорного напряжения момента равенства преобразуемого напряжения уровню опорного напряжения; значения кода результата преобразования формируют из номера момента равенства преобразуемого напряжения уровню опорного напряжения с момента начала интервала ...

Verfahren und Vorrichtung zur Analog-Digitalumwandlung unter Verwendung eines zeitvariierenden Referenzsignals

Verfahren (100) zum Umwandeln eines analogen Signals (S) in eine digitale Darstellung, wobei das Verfahren (100) folgende Schritte aufweist: Erzeugen (110) einer Quantität N von zeitvariierenden Referenzsignalen, deren Amplitudenwerte eine vorbekannte Funktion der Zeit sind, wenn N eine Ganzzahl größer als 1 ist; Vergleichen (120; 120') einer Amplitude des Analogsignals mit einer Amplitude von jedem Referenzsignal, um zu bestimmen, ob die Analogsignalamplitude größer als, kleiner als oder gleich jeder Referenzsignalamplitude ist; und Erzeugen (130, 130') eines Zeitstempels, wenn die Analogsignalamplitude gleich der Amplitude von jedem Referenzsignal ist, wobei jeder Zeitstempel der Zeit des Auftretens eines Amplitudengleichheitsereignisses entspricht, und wobei die digitale Darstellung ein Satz von Zeitstempeln ist.

ANALOGUE-TO-DIGITAL CONVERTERS

Analog-to-digital conversion in receiver system

MULTI-STATE LOGIC ENGINE

An analog to digital converter provides a device for characterizing, in digital terms, a first quantity having a magnitude which varies as a function of a second quantity. An output signal is generated having more than two values, the output signal indicating the magnitude of the first quantity in comparison to a reference level and the change in the magnitude of the first quantity as a function of the second quantity.

GRAY COUNTER AND ANALOG-TO - DIGITAL CONVERTER USING SUCH A COUNTER

동적 윈도우 길이를 갖는 비교기 추적 제어 방식

... 아날로그-투-디지털 변환기(ADC)에 대한 비교기 추적 방식은 아날로그 입력 신호를 디지털 출력 신호로 변환하기 위하여 전력 업된 비교기들의 수를 시간에 걸쳐 가변시킴으로써 동적 윈도우 사이즈를 구현할 수 있다. 비교기 추적 방식은 예컨대 ADC의 복수의 비교기들에 커플링된 제어기로 구현될 수 있다. 예컨대, 제어기는 ADC에 대한 윈도우 사이즈를 결정할 수 있고 ADC에 대한 윈도우 포지션을 결정할 수 있다. 그 다음, 제어기는 윈도우 포지션에 중심을 두고 윈도우 사이즈의 폭을 가진 윈도우 내의 ADC의 비교기들을 활성화할 수 있다. 제어기는 필터의 출력을 분석함으로써 윈도우 사이즈를 결정할 수 있다. 필터 출력이 빠르게 변화하는 아날로그 입력 신호를 표시할 때, 제어기는 ADC의 윈도우 사이즈를 동적으로 증가시킬 수 있고, 이는 전력 온되는 비교기들의 수를 증가시킬 수 있다.

열 병렬 싱글-슬로프 아날로그-디지털 변환기를 위한 다이나믹 바이어싱을 갖는 캐스코드 비교기

... 본 발명은 각각의 제 1 및 제 2 입력 트랜지스터를 통해 제 1 입력 신호 및 제 2 입력 신호를 수신하는 것을 포함할 수 있다. 캐스코드 바이어스 발생기에 의해 발생되는 바이어싱 신호는 제 1 입력 신호를 트랙킹하며, 바이어싱 신호는 제 1 입력 신호에 대해 고정된 오프셋을 갖는다. 바이어싱 신호는 제 1 및 제 2 입력 트랜지스터 각각에 캐스코드될 수 있는 제 1 및 제 2 캐스코드 트랜지스터에 인가될 수 있다.

FLASH ANALOG-DIGITAL CONVERTER

PURPOSE: A flash A/D converter is provided to achieve a high converting speed and to generate a digital signal with a high resolution. CONSTITUTION: A converter comprises a reference voltage generating unit(100) for receiving first and second voltages(Vref_top,Vref_bot,Vref_topb,Vref_botb) from an external source and generating reference voltages(Vref,Vrefb) for first and second groups; a switch control signal generating unit(200) for receiving a clock from an external source and generating a latch activation signal(QL) and switch control signals(Q1,Q2,Q1P,Q2P) for first to third groups; an amplification unit(300) having a plurality of amplifiers and which generates, in response to the latch activation signal and switch control signals of the first to third groups, a plurality of amplification signals where a voltage difference between the reference voltages of the first and second groups and the first and second input signals applied from an external source is amplified; and a latch unit ...

METHOD AND APPARATUS FOR PEAK TRACKING A BASEBAND SIGNAL

Ce procédé consiste à poursuivre les crêtes maximales et les crêtes minimales d'un signal, puis à calculer le point médian entre ces crêtes maximales et minimales, et à effectuer le seuillage du signal par rapport à ce point médian. L'invention concerne également un dispositif comprenant une unité de poursuite de crêtes, destinée à poursuivre les crêtes maximales d'un signal, ainsi qu'une unité de poursuite de crêtes, destinée à poursuivre les crêtes minimales d'un signal. Cet appareil comprend en outre une unité de calcul d'un point médian, laquelle reçoit les crêtes maximales et minimales poursuivies, afin de déterminer le point médian entre ces crêtes et minimales. Cet appareil comprend encore un comparateur qui reçoit le signal et le point médian.

Analogue to digital converter

Measures are provided for performing direct radio-frequency to digital conversion. A radio-frequency input signal is compared with a plurality of reference voltages to generate a plurality of comparison signals, each comparison signal corresponding to one of the plurality of reference voltages. One or more of the plurality of generated comparison signals are first filtered to generate a first filtered signal. One or more of the plurality of generated comparison signals are second filtered to generate a second filtered signal. A digital output signal is generated at least on the basis of the first filtered signal and the second filtered signal.

Parallel analog-digital converter with error-correction circuit

The disclosure pertains to parallel analog-digital converters, the first comparator stage of which give a so-called thermometer scale, formed by a sequence of logic "ones" and logic "zeros". According to the disclosure, a corrector stage is added on in series with the comparator stage. If a comparator of the first stage accidentally gives a logic value opposite that given by the two neighboring comparators, the corrector stages forces the accidentally erroneous value to assume the same value as that the values given by the two neighboring comparators, if and only if these values are equal. The disclosed device can be applied to signal processing ADCs.

Polar analog-to-digital converter

A polar analog-to-digital converter ADC that can be advantageously used to extract phase and/or frequency information from a pair of input signals. The polar ADC includes first and second scaling elements, a number of comparators, and a decoder. The first scaling element receives and scales a first signal to provide a set of one or more scaled first signals. The second scaling element receives and scales a second signal to provide a set of one or more scaled second signals. Each of the comparators receives and compares a respective pair of scaled first and second signals and provides a comparison output. The decoder receives the comparison outputs from the comparators and generates output data, which can be indicative of the phase and/or frequency of the first and second signals.

Flash analog-to-digital converter comparator reference arrangement

A circuit reduces the total number of resistors needed to provide the reference voltages to the plurality of comparators in a flash analog-to-digital converter. In such a circuit, a first string of unit resistances having a first plurality of taps is coupled to a second string of unit resistances having first and second ends and a second plurality of taps between the ends. A first active device has an input coupled to a first tap of the first string of unit resistances and an output coupled to the first end of the second string of unit resistances. A second active device has an input coupled to a second tap of the first string of unit resistances and an output coupled to the second end of the second string of unit resistances.

Multiplying digital to analog converter (MDAC) with error compensation and method of operation

The present disclosure provides methods and circuits for compensating reference shifting error. A compensation reference voltage is applied to an error compensation circuit, which is coupled to a multiplying circuit. A compensation parasitic capacitance is induced in the error compensation circuit. The compensation parasitic capacitance is configured to negate a parasitic capacitance induced in the multiplying circuit.

Delay based comparator

A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.

Bit error rate timer for a dynamic latch

A converter system, including a first converter that digitizes the a first portion of an input signal, the first converter including a comparator, a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator, a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer, and a combiner having inputs to generate a digital code from the digitized first and second portions.

A/D converter bias current circuit

Mixed-signal circuitry and integrated circuit devices

Mixed-signal circuitry and integrated circuit devices

Testing an analogue to digital converter

An analogue to digital converter has an analogue signal input in, a reference voltage divider ROA-RTB and a plurality of comparators C0-C7. Each comparator has a first input connected to the analogue signal input in and a reference input connected to receive a respective predetermined reference voltage from the reference voltage divider. In addition, test mode circuitry is provided for feeding a sequence of test voltages VT from the voltage divider to the first inputs of the comparators in a test mode. A decoder is connected to the outputs of the comparators for generating a binary output signal out representative of an input analogue signal.

ERROR LIMITING ANALOG TO DIGITAL CONVERTER

Convertisseur analogique-numérique parallèle, à circuit de correction d'erreur

L'invention se rapporte aux convertisseurs analogiques-numériques CAN, parallèles, dont le premier étage 3 comparateur fournit une échelle dite thermométrique 6, constituée d'une suite de 1 logiques puis de 0 logiques. L'invention consiste à ajouter, en série avec l'étage comparateur 3, un étage correcteur 5 : si un comparateur 1 du premier étage 3 fournit accidentellement une valeur logique B opposée à celles A, C fournies par les deux comparateurs voisins i+1, i-1, l'étage correcteur 5 force la valeur accidentellement erronée B à prendre la même valeur que celles A, C fournies par les deux comparateurs voisins, si et seulement si celles-ci A, C sont égales. Application aux CAN pour traitement du signal.

Translator of coded impulses

GRAY AND COUNTER-TO-ANALOG CONVERTER USING SUCH A COUNTER

Compteur de Gray à N bit, avec N entier supérieur à 1, comprenant un enchaînement de N cellules logiques (CL0 - CLN-1) connectées en cascade, caractérisé en ce que chaque dite cellule logique comprend un port d'entrée pour une succession d'impulsions d'horloge (CK0 - CKN-1), un circuit de génération d'un bit de comptage Gray (bg0 - bgN-1) ayant un port de sortie dudit bit de comptage Gray et un circuit de génération d'un signal d'horloge ayant un port de sortie d'horloge (PSH) relié au port d'entrée de la cellule logique suivante. Convertisseur analogique-numérique de type à rampe utilisant un tel compteur de Gray.

Analog to digital converter

An analog to digital converter for converting an initial analog signal into a digital signal comprising at least one electronic module with an input, a first output, and a second output, which module generates from an analog input signal: a first output signal, which first output signal in terms of multiples of a predetermined amount of current or voltage, such as 1 uA or 1 mV, is substantially equal to the integer quotient of division of the input signal by a number or comprises a plurality of signals which if combined are substantially equal to the integer quotient of division of the input signal in terms of multiples of a predetermined amount of current or voltage, and a second output signal which in terms of multiples of a predetermined amount of current or voltage, such as 1 uA or 1 mV, is substantially equal to the remainder of the division, the analog to digital converter also comprising a further analog to digital converter for converting the second output signal into a digital signal, wherein the further analog to digital converter is connected the at least one module and the module is configured so that in use when the analog input signal connects through the input the first output signal connects through the first output, and the second output signal connects through the second output into the further analog to digital converter.

Adc calibration

An analog-to-digital converter (ADC) including a plurality of comparators connected to the ADC. The ADC further includes a first pair of terminals and a second pair of terminals connected to each of the plurality of comparators. The ADC further includes a first pair of switches coupled to each of the first pair of terminals and a second pair of switches coupled to each of the second pair of terminals, where the first and second pair of switches are configured to alternate a corresponding comparator between normal operation and a calibration configuration. Comparators other than the corresponding comparator are configured for normal operation if the corresponding comparator is configured to be calibrated.

Ad converter

To provide a highly accurate and small AD converter. The AD converter converts an analog voltage Vin into a digital code DC of N-bit, and includes memory blocks MB 1 to MB (2 N −1). Each memory block MB (2 n −1) includes (2 n −1) memory cells 1 for an MRAM. After stored data of the memory cell 1 is reset to “0”, an analog current Iin proportional to the analog voltage Vin is shunted to the (2 n −1) bit lines BL of the each memory block MB (2 n −1). Stored data of the memory cells 1 of the memory blocks MB 1 to MB (2 N −1) is read to generate the digital code DC. Accordingly, a ladder resistance is unnecessary.

Biological analog-to-digital and digital-to-analog converters

Described herein are novel biological converter switches that utilize modular components, such as genetic toggle switches and single invertase memory modules (SIMMs), for converting analog inputs to digital outputs, and digital inputs to analog outputs, in cells and cellular systems. Flexibility in these biological converter switches is provided by combining individual modular components, i.e., SIMMs and genetic toggle switches, together. These biological converter switches can be combined in a variety of network topologies to create circuits that act, for example, as switchboards, and regulate the production of an output product(s) based on the combination and nature of input signals received.

SIGNAL INTERPOLATION DEVICE AND PARALLEL A/D CONVERTING DEVICE

There is provided a signal interpolation device, including: a first amplifier to generate a first signal representing a difference between an input signal and a first reference voltage; a second amplifier to generate a second signal representing a difference between the input signal and a second reference voltage; a first output amplifier to amplify the first signal to generate a first output signal; a second output amplifier to amplify the second signal to generate a second output signal; a third output amplifier to amplify a sum of a first interpolation signal and the first signal to generate a third output signal, the first interpolation signal representing a voltage generated by dividing a difference between the first reference voltage and the second reference voltage by “2̂n”; and a fourth output amplifier to amplify a difference between the second signal and the first interpolation signal to generate a fourth output signal. 1. A signal interpolation device , comprising:a first amplifier to generate a first signal representing a difference between an input signal and a first reference voltage;a second amplifier to generate a second signal representing a difference between the input signal and a second reference voltage;a first output amplifier to amplify the first signal to generate a first output signal;a second output amplifier to amplify the second signal to generate a second output signal;a third output amplifier to amplify a sum of a first interpolation signal and the first signal to generate a third output signal, the first interpolation signal representing a voltage generated by dividing a difference between the first reference voltage and the second reference voltage by “2̂n” (“n” is an integer of at least two); anda fourth output amplifier to amplify a difference between the second signal and the first interpolation signal to generate a fourth output signal.2. The device according to claim 1 , further comprisinga fifth output amplifier to amplify a sum ...

Mixed mode analog to digital converter and method of operating the same

An analog to digital converter in accordance with the inventive concept may include a reference voltage generation circuit outputting first and second reference voltages; a decompression part decompressing amplitude of an analog input signal and the first and second reference voltages; a flash ADC converting the decompressed analog input signal into a first digital signal with reference to the decompressed first and second reference voltages; and a successive approximation ADC converting the analog input signal into a second digital signal according to a successive approximation operation with reference to the first digital signal and the first and second reference voltages.

Ad converting circuit, photoelectric converting apparatus, image pickup system, and driving method for ad converting circuit

An apparatus for acquiring an i-bit digital code by a first stage AD conversion and a j-bit digital code by a second stage AD conversion includes a comparing unit which compares a reference signal and an analog signal in the first stage AD conversion; and an amplifying unit for outputting an amplified residual signal acquired by amplifying a difference between the analog signal and an analog signal corresponding to the i-bit digital code. The comparing unit compares the amplified residual signal and the reference signal in the second stage AD conversion.

BACKGROUND ESTIMATION OF COMPARATOR OFFSET OF AN ANALOG-TO-DIGITAL CONVERTER

A pipeline analog-to-digital converter (ADC) converts an analog input signal over several stages, where a stage generates a residue for the subsequent stage to digitize. The residue is generated by coarsely quantizing the analog input signal to generate a digital code, which is used to reconstruct the analog input signal, and the residue is the difference between the analog input signal and the reconstructed version of the analog input signal. The coarse quantization can have errors which are attributed to comparator offsets and bandwidth mismatch. To estimate the comparator offsets while being insensitive to bandwidth mismatch, peak and trough detectors are used to track maximum and minimum values of the residue or the output of the ADC over time, and an expected value estimating the comparator offset can be computed based on the maximum and minimum values. The expected value advantageously “averages” out the bandwidth mismatch contribution to the offset. 1. A method for estimating comparator offset of a sub-analog-to-digital converter (sub-ADC) of an analog to digital converter (ADC) , the method comprising:determining data samples of (1) a residue signal generated based on a difference between an input signal to the sub-ADC and a reconstructed version of the input signal or (2) an input signal to the sub-ADC, wherein data samples corresponds to two neighboring codes which are associated with a comparison made by a comparator of the sub-ADC;tracking, over time, state information of the neighboring codes based on the data samples; anddetermining an expected value, which estimates an offset of the comparator, based on the state information.2. The method of claim 1 , further comprising:calibrating or correcting for the offset based on the expected value.3. The method of claim 1 , wherein the sub-ADC is a flash ADC or quantizer of any stage of a pipeline analog-to-digital converter.4. The method of claim 1 , wherein:the state information comprises (1) maximum values ...

SEMICONDUCTOR INTEGRATED CIRCUIT

A feedback loop, which feedbacks information of an output voltage or a load current, is provided. The feedback loop has a first mode, which digitalizes and feedbacks the information of the current voltage or the load current, and a second mode, which feedbacks the information as an analog value. 1. A semiconductor integrated circuit which feedbacks information of at least one of an output voltage and a load current and controls the output voltage comprising:a first mode which digitalizes and feedbacks the information of at least one of the output voltage and the load current;and a second mode which feedbacks the information of at least one of the output voltage and the load current as an analog value.2. The semiconductor integrated circuit according to claim 1 , wherein a feedback loop feedbacking the information of the output voltage is provided in the semiconductor integrated circuit claim 1 , and the feedback loop includes an AD converter which digitalizes the information of the output voltage claim 1 , anddigitalization by the AD converter is performed in the first mode, and an operation of the AD converter is stopped in the second mode.3. The semiconductor integrated circuit according to claim 2 , wherein the AD converter is a successive approximation register AD converter.4. The semiconductor integrated circuit according to claim 2 , wherein the AD converter is a parallel type AD converter.5. The semiconductor integrated circuit according to claim 4 , wherein the AD converter includes a plurality of comparison circuits which compares a predetermined reference voltage and a feedback voltage of the output voltage and is connected in parallel claim 4 , and at least one of the comparison circuits includes:first and second MOS transistors which compare the reference voltage and the feedback voltage and constitute a differential pair; anda third MOS transistor which supplies a current to the first and second transistors,wherein conduction of the third MOS transistor ...

Analog-digital converter

AD conversion is performed by using a combination of a parallel AD converter that includes a plurality of comparators to compare an input potential of an analog input signal sampled by a track and hold circuit and reference potentials different from one another and determines a value of a predetermined number of bits on the higher-order side of a digital signal and a single-slope AD converter that reduces the input potential of the analog input signal sampled by the track and hold circuit at a constant speed, converts a time taken until the reduced input potential becomes equal to a reference potential corresponding to the value determined by the parallel AD converter to a digital value, and determines a remaining value on the lower-order side of the digital signal, and thereby the number of bits of the single-slope AD converter can be reduced and high-speed AD conversion is enabled with a small area and low power consumption.

Decision Feedback Equalizer

A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE, then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

DSP RECEIVER WITH HIGH SPEED LOW BER ADC

Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC. 1. A device comprising: [ 'a first comparator generating the first bit, where the first comparator is configured to receive an analog signal at a first time; and', 'a first path determining a first bit in the plurality of bits, the first path comprising, a rectifier, where the rectifier is configured to receive the analog signal at a second time after the first time; and', 'a plurality of comparators coupled to an output of the rectifier, the plurality of comparators generating the second bit., 'a second path determining a second bit in the plurality of bits, the second path comprising], 'a multi-path, rectifying analog-to-digital converter (ADC) converting an analog signal into a plurality of bits, the ADC comprising2. The device of claim 1 , the second path further comprising:a signal hold circuit operating in parallel with the first comparator in the first path, wherein the rectifier is coupled to an output of the signal hold circuit.3. The device of claim 2 , wherein the hold circuit comprises one of a delay circuit claim 2 , a sample-and-hold (SH) circuit and a track-and-hold (TH) circuit.4. The device of claim 3 , wherein the SH circuit comprises a multi-stage SH circuit and the TH circuit comprises a multi-stage TH circuit and wherein an input to the second path is coupled between stages in the multi-stage SH circuit or TH circuit.5. The device of claim 1 , wherein the ...

IMAGE SENSOR AND METHOD OF CONTROLLING THE SAME

Provided is an image sensor including a sensor array including a plurality of pixels arranged in rows and columns. The image sensor may include a ramp signal generator which may generate a ramp signal. The intensity of the ramp signal may increase or decrease in response to a ramp enable signal. The image sensor may include an analog-digital converter electrically connected to one of the columns of the pixels. The analog-digital converter may be configured to compare an output signal from the one of the columns of the pixels with the ramp signal, thereby generating time information. The analog-digital converter may be configured to convert the time information to digital information in response to a counter enable signal. An activation of the counter enable signal may be delayed by a predetermined time delay, compared with that of the ramp enable signal.

INBUILT THRESHOLD COMPARATOR

A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal. 1. A comparator comprising:a first input stage coupled to a first signal input and a first reference input, the first input stage coupled between a first node and a second node;wherein the first input stage comprises:a first transistor coupled between the first node and the second node, the gate of the first transistor being coupled to the first signal input; anda first plurality of capacitors coupled to the first node and a first plurality of switches, the first plurality of switches coupled to the first reference input wherein the first plurality of switches is controlled by a processor;a second input stage coupled to a second signal input and a second reference input, the second input stage coupled between a third node and the second node;wherein the second input stage comprises:a second transistor coupled between the third node and the second node, the gate of the second transistor being coupled to the second signal input; anda second plurality of capacitors coupled to the third node and a second plurality of switches, the second plurality of switches coupled to the second reference input wherein the second plurality of switches is ...

SUCCESSIVE APPROXIMATION A/D CONVERTER

The successive approximation A/D converter includes: switch groups to each of which is connected to the other end of each corresponding capacitor of capacitors to to selectively switch a capacitor to be applied to a successive comparison in response to a switch group control signal Ct a comparator for making a successive comparison of a comparison voltage VSN based on a holding voltage on each corresponding capacitor, selected through the switch groups from among the capacitors, with a predetermined reference voltage VC in synchronization with a timing control signal CLK to obtain a judgment output according to the comparison result; and a voltage application part for applying a predetermined voltage to the comparison voltage based on a form-of-voltage application control signal Ct for a predetermined period when a predetermined time has elapsed after the successive comparison. 1. A successive approximation A/D converter comprising:a capacitor array having a plurality of capacitors;a plurality of switch groups connected to the capacitor array;a comparator connected to the capacitor array to make a successive comparison in response to a timing control signal to obtain a judging output signal; anda first controller for generating a control signal to control the plurality of switch groups according to the judging output signal from the comparator,wherein when the comparator cannot obtain the judging output signal at a time of comparison timing by the timing control signal, the judging output signal is obtained after a lapse of a predetermined time after the time of the comparison timing.2. The successive approximation A/D converter according to claim 1 , wherein a successive comparison of a holding voltage on each corresponding capacitor of the plurality of capacitors in the capacitor array with a predetermined reference voltage is made to obtain a digital output signal corresponding to an input analog signal.3. The successive approximation A/D converter according to ...

Flash analog to digital converter

A flash analog to digital converter includes a voltage generator circuit, an encoder circuit, and first and second double differential amplifier circuits. The voltage generator circuit generates reference voltages according to first and second voltages. The encoder circuit generates a digital signal corresponding to an input signal according to first signals. The first double differential amplifier circuit compares the input signal with a first reference voltage in the reference voltages, to generate a corresponding one of the first signals. The second double differential amplifier circuit compares the input signal with a second reference voltage in the reference voltages, to generate a corresponding one of the first signals. A difference between the first voltage and the first reference voltage is less than that between the first voltage and the second reference voltage, and the first and the second double differential amplifier circuits have different circuit architectures.

RADIO FREQUENCY FLASH ADC CIRCUITS

A system and method for sampling an RF signal are described. The system comprises a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors. 120-. (canceled)21. A system comprising:a plurality of preamplifiers, wherein a first input of each of the plurality of preamplifiers is operably coupled to a radio frequency (RF) input, and wherein a second input of each of the plurality of preamplifiers is operably coupled to a reference level of a plurality of reference levels; anda sampling circuit operably coupled to an output of each of the plurality of preamplifiers, wherein the sampling circuit is operable to produce a plurality of digital outputs.22. The system of claim 21 , wherein the system comprises a converter operable to convert the plurality of digital outputs to a binary output.23. The system of claim 21 , wherein the system comprises a series of resistors between a first reference input and a second reference input claim 21 , each reference level of the plurality of reference levels being produced along the series of resistors.24. The system of claim 23 , wherein the system comprises a first switch for selecting the first reference input and a second switch for selecting the second reference input.25. The system of claim 21 , wherein the sampling circuit comprises a plurality of comparators claim 21 , wherein the output of each of the plurality of preamplifiers is operably coupled to an input of a comparator of the plurality of comparators.26. The system of ...

BAYESIAN NETWORK IN MEMORY

Apparatuses and methods can be related to implementing a Bayesian neural network in a memory. A Bayesian neural network can be implemented utilizing a resistive memory array. The memory array can comprise programmable memory cells that can be programed and used to store weights of the Bayesian neural network and perform operations consistent with the Bayesian neural network.

COMPARATOR AND A/D CONVERTER

A comparator includes: a differential amplifier of which operational state is switched in response to a clock-signal, and which outputs a first intermediate-output corresponding to a first input-signal and a second intermediate-output corresponding to a second input-signal; a differential latch circuit of which operational state is switched in response to the clock-signal, and a state of which is changed depending on the first intermediate-output and the second intermediate-output; a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output; and a second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output. 1. A comparator , comprising:a differential amplifier of which operational state is switched in response to a clock signal, and which outputs a first intermediate output corresponding to a first input signal and a second intermediate output corresponding to a second input signal;a differential latch circuit of which operational state is switched in response to the clock signal, and a state of which is changed depending on the first intermediate output and the second intermediate output;a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate output and a change of a state of the second intermediate output; anda second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate output and a change of a state of the second intermediate output.2. The comparator according to claim 1 , wherein: a latch circuit which includes a first line including a first PMOS transistor and a first NMOS ...

Memory device and operation method thereof

A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results, wherein in performing bitwise multiplication, the memory cells generate a plurality of memory cell currents; a digital accumulating circuit for performing a digital accumulating on the multiplication results; an analog accumulating circuit for performing an analog accumulating on the memory cell currents to generate a first MAC operation result; and a decision unit for deciding whether to perform the analog accumulating; the digital accumulating or a hybrid accumulating, wherein in performing the hybrid accumulating, whether the digital accumulating circuit is triggered is based on the first MAC operation result.

SENSING CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME

A sensing circuit includes a first input selecting circuit connected to a first sensing line and a second sensing line, a first path setting circuit that sets a path of a first sensing signal received from the first sensing line or a path of a second sensing signal received from the second sensing line, a second path setting circuit that sets a path of a sensing reference voltage, a first switch matrix connected to the first path setting circuit and the second path setting circuit, a first mode setting circuit connected to a first output terminal of the first switch matrix, a first common sensing amplifier connected to the first mode setting circuit, a second mode setting circuit connected to a second output terminal of the first switch matrix, and a second common sensing amplifier connected to the second mode setting circuit. 1. A sensing circuit , comprising:a first input selecting circuit connected to a first sensing line and a second sensing line;a first path setting circuit configured to set a path of a first sensing signal received from the first sensing line or a path of a second sensing signal received from the second sensing line;a second path setting circuit configured to set a path of a first sensing reference voltage;a first switch matrix connected to the first path setting circuit and the second path setting circuit;a first mode setting circuit connected to a first output terminal of the first switch matrix;a first common sensing amplifier connected to the first mode setting circuit;a second mode setting circuit connected to a second output terminal of the first switch matrix; anda second common sensing amplifier connected to the second mode setting circuit.2. The sensing circuit of claim 1 , further comprising:an analog-to-digital converter connected to an output terminal of the first common sensing amplifier and an output terminal of the second common sensing amplifier.3. The sensing circuit of claim 2 , wherein the first mode setting circuit ...

Semiconductor device and error correcting method

A semiconductor device includes a comparison circuit that compares an input analog voltage with a plurality of reference voltages, which are arranged in an ascending order in voltage level, to thereby obtain a plurality of comparison signals arranged in an order corresponding to the order of the reference voltage, a first correction circuit that corrects each of the comparison signals using another one of the comparison signals adjacent to the each comparison signal at a first side thereof, to thereby output a plurality of first correction signals arranged in an order corresponding to the order of the comparison signals, and a second correction circuit that corrects each of the first correction signals using another one of first correction signals adjacent to the each first correction signal at a second side thereof, to thereby output a plurality of second correction signals. The second side is different from the first side.

MULTI-STAGE ANALOG TO DIGITAL CONVERTER

A multi-stage analog-to-digital converter (ADC) suitable for low power applications, such as glucose monitoring, may be required to digitize a slow-moving signal. As such, a multi-stage ADC must be versatile. Accordingly, the multi-stage ADC can be configured to operate at different bandwidths and resolutions through the use of ADC stages that can be enabled or disabled in an exchange between resolution and speed. Each ADC stage digitizes an input signal (e.g., a voltage or a current) using an analog comparison to access a lookup table for a digital signal that represents the input signal at a particular accuracy. Unlike other multi-stage approaches, the digitization is asynchronous (i.e., requires no clock) and can provide simplicity, speed, and low-power operation to the multi-stage ADC. 1. A multi-stage analog-to-digital converter (ADC) for generating a digital word representing an analog sample of a signal , the multi-stage ADC comprising: 'access a lookup-table, based on an input signal received by the ADC stage and a reference level received by the ADC stage, and output a digital word segment corresponding to a level of the input signal relative to the reference level; and', 'an ADC stage included in a sequence of ADC stages, the ADC stage configured to 'combine digital word segments from the sequence of ADC stages to generate the digital word representing the analog sample of the signal.', 'a synchronizing and recording circuit configured to2. The multi-stage ADC for generating a digital word representing an analog sample of a signal according to claim 1 , wherein the ADC stage includes: compare the input signal received by the ADC stage to reference ranges set by the reference level received by the ADC stage, and', 'generate, based on the comparison, a plurality of signals, each of the plurality of signals representing the input signal compared to one of the reference ranges., 'a front-end computing portion configured to3. The multi-stage ADC for generating ...

DIFFERENTIAL CLAMP CIRCUITS WITH CURRENT RECIRCULATION

Differential clamp circuits configured to recirculate the current in one clamp, either low-side clamp or high-side clamp, from one output of a differential signal to the other output of the differential signal are disclosed. Differential clamp circuits described herein may be particularly suitable for providing programmable clamps at differential outputs of an ADC driver and may be particularly beneficial to implement clamps that are symmetrical around an ADC's input common-mode voltage. Some differential clamp circuit described herein may advantageously present a smaller capacitive load at each output, thus reducing bandwidth degradation of the output stage. Furthermore, differential clamp circuits described herein may operate with only one control voltage, making it easier to limit the output excursions symmetrically around the default common-mode voltage. 1. A system configured to clamp a differential signal that is output by an electronic component , the system comprising: a clamp transistor, coupled to a control signal that sets one of a minimum voltage value or a maximum voltage value for the output coupled to the portion, and', 'a current mirror, having an input transistor and an output transistor, wherein:', 'a first terminal of the clamp transistor of the first portion is coupled to the output coupled to the first portion,', 'a second terminal of the clamp transistor of the first portion is coupled to the input transistor of the current mirror of the first portion, and', 'the output transistor of the current mirror of the first portion is coupled to the output coupled to the second portion., 'a clamp circuit, comprising a first portion and a second portion, each of the first and second portions coupled to a respective output of the differential signal and comprising2. The system according to claim 1 , wherein:the current mirror is a first current mirror,each of the first and second portions of the clamp circuit further includes a second current mirror, ...

Analog-to-digital converter for a capacitive adiabatic logic circuit

An analog-to-digital converter for an adiabatic logic circuit, including at least one variable-capacitance cell, the cell including first and second main terminals and at least one control terminal insulated from its first and second main terminals and capable of receiving a control voltage to vary the capacitance between its first and second main terminals between a low value and a high value, wherein: the cell has its first main terminal coupled to a node of application of a variable periodic converter power supply voltage; the cell has its second main terminal coupled to a node for supplying a binary output signal of the converter; and the cell receives on its first control terminal an analog input voltage of the converter.

RADIO FREQUENCY FLASH ADC CIRCUITS

A system and method for sampling an RF signal are described. The system comprises a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors. 120-. (canceled)21. A system , the system comprising:a plurality of capacitors, a first port of each of the plurality of capacitors being operably coupled to a radio frequency (RF) input;a plurality of resistors, a first port of each of the plurality of resistors being operably coupled to a reference level of a plurality of reference levels, a second port of each of the plurality of resistors being operably coupled to a second port of each of the plurality of capacitors; anda sampling circuit operably coupled to the second port of each of the plurality of resistors, wherein the sampling circuit is operable to produce a plurality of digital outputs.22. The system of claim 21 , wherein the system comprises a converter operable to convert the plurality of digital outputs to a binary output.23. The system of claim 21 , wherein the system comprises a series of resistors between a first reference input and a second reference input claim 21 , each reference level of the plurality of reference levels being produced along the series of resistors.24. The system of claim 23 , wherein the system comprises a first switch for selecting the first reference input and a second switch for selecting the second reference input.25. The system of claim 21 , wherein the sampling circuit comprises a plurality of comparators claim 21 , the second port ...

CASCODED COMPARATOR WITH DYNAMIC BIASING FOR COLUMN PARALLEL SINGLE SLOPE ADCS

Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively. 1. Circuitry for processing signals , the circuitry comprising:a first PMOS transistor with a source terminal coupled to a positive voltage supply;a drain terminal of the first PMOS transistor coupled to a source terminal of each of a second PMOS transistor and a third PMOS transistor;a fourth PMOS transistor with a source terminal coupled to the drain terminal of the second PMOS transistor;a fifth PMOS transistor with a source terminal coupled to the drain terminal of the third PMOS transistor;a first NMOS transistor with a drain terminal coupled to a drain terminal of the fourth PMOS transistor, to a gate terminal of the first NMOS transistor, to a drain terminal of a second NMOS transistor, and to a gate terminal of a third NMOS transistor;a fourth NMOS transistor with a drain terminal coupled to a drain terminal of the fifth PMOS transistor, to a gate terminal of the fourth NMOS transistor, and to a drain terminal of the third NMOS transistor, and to a gate terminal of the second NMOS transistor;a source terminal of each of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor coupled to ground; anda cascode bias generator with an output terminal coupled to a gate terminal of the fourth PMOS transistor, to a gate terminal of the fifth PMOS transistor.2. The circuitry according to claim 1 , wherein:a biasing signal is applied to a gate terminal of the first PMOS transistor;a first input ramp signal is applied to a gate terminal of the ...

ADC CALIBRATION

An analog-to-digital converter (ADC) includes a plurality of comparators connected to the ADC. The ADC further includes a plurality of switches, wherein switches connected to a corresponding comparator of the plurality of comparators are configured to alternate the corresponding comparator between normal operation and a calibration configuration. The ADC further includes at least one comparator of the plurality of comparators other than the corresponding comparator is configured for normal operation if the corresponding comparator is configured for calibration. 1. An analog-to-digital converter (ADC) comprising:a plurality of comparators connected to the ADC;a plurality of switches, wherein switches connected to a corresponding comparator of the plurality of comparators are configured to alternate the corresponding comparator between normal operation and a calibration configuration, andat least one comparator of the plurality of comparators other than the corresponding comparator is configured for normal operation if the corresponding comparator is configured for calibration.2. The ADC of claim 1 , wherein the plurality of comparators comprises a first comparator and a second comparator claim 1 , the plurality of switches comprises a first switch configured to selectively connect a reference voltage to the first comparator claim 1 , and the plurality of switches comprises a second switch configured to selectively connect a calibration signal to the first comparator.3. The ADC of claim 2 , wherein the first switch is further configured to selectively connect the reference voltage to the second comparator.4. The ADC of claim 1 , further comprising an encoder configured to receive a thermometer code from each comparator of the plurality of comparators.5. The ADC of claim 4 , wherein the encoder is configured to transform the thermometer code from each comparator of the plurality of comparators into binary code.6. The ADC of claim 4 , further comprising a decimator ...

Digital-to-Analog Converter Transfer Function Modification

The present disclosure relates to a digital-to-analog converter (DAC) which includes a resistor string and a transfer function modification circuit. The transfer function modification circuit may be a calibration circuit for calibrating the DAC, The calibration circuit may include a plurality of current sources, which may be current DACs. Each of the current DACS inject current into, or drain current from, a respective node of the resistor string, in order to correct for voltage errors. The injected currents may be positive or negative, depending on the voltage error. The current DACs are controlled by trim codes, which are set dependent on the measured or simulated voltage errors for a given resistor string.

NON-LINEARITY CORRECTION

A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit. 1. A non-linearity correction circuit , comprising: a data capture circuit;', 'a non-linearity term generation circuit coupled to the data capture circuit;', 'a time-to-frequency conversion circuit coupled to the data capture circuit and the non-linearity term generation circuit;', 'a bin identification circuit coupled to the time-to-frequency conversion circuit;', 'a residual non-linearity conversion circuit coupled to the bin identification circuit; and', 'a non-linearity coefficient generation circuit coupled to the bin identification circuit and the residual non-linearity conversion circuit., 'a non-linearity coefficient estimation circuit comprising2. The non-linearity correction circuit of claim 1 , further comprising a non-linearity corrector circuit coupled to the non-linearity coefficient estimation circuit claim 1 , and configured to generate non-linearity corrected data based on non-linearity correction coefficients generated by the non-linearity coefficient generation circuit.3. The non-linearity correction circuit of claim 2 , wherein the data capture ...

ANALOG-TO-DIGITAL CONVERTER AND IMAGE SENSOR HAVING THE SAME

An analog-to-digital converter configured to convert an analog signal into a digital signal includes a first converter configured to receive an input signal of an analog type, compare the input signal with a plurality of reference signals, select one of the plurality of reference signals based on the comparison, and output an upper bit that is a portion of the digital signal based on the selected reference signal, a second converter configured to perform an oversampling operation n times based on a residue signal indicating a difference between an upper analog signal corresponding to the upper bit value and the input signal and output an intermediate bit value of the digital signal corresponding to the first to n-th oversampling signals generated respectively during the oversampling operations performed n times, and a third converter configured to output a lower bit value of the digital signal corresponding to the n-th oversampling signal. 1. An analog-to-digital converter configured to convert an analog signal into a digital signal , the analog-to-digital converter comprising:a first converter configured to operate in a first mode to receive a first input signal of an analog type, compare the first input signal with a plurality of reference signals, select one out of the plurality of reference signals based on the comparison, and output at least one upper bit value that is at least a portion of the digital signal based on the selected reference signal;a second converter configured to operate in a second mode to perform an oversampling operation n times based on a residue signal, where n is an integer, the residue signal indicating a difference between an upper analog signal corresponding to the at least one upper bit value and the first input signal, and output an intermediate bit value of the digital signal corresponding to first to n-th oversampling signals generated respectively during the oversampling operations performed n times; anda third converter ...

ANALOG-TO-DIGITAL CONVERSION CIRCUIT, IMAGING APPARATUS AND IMAGING SYSTEM

An analog-to-digital conversion circuit includes: a plurality of comparators comparing an analog signal with a reference signal; a counter generating a count signal having a plurality of bits in Gray code; a plurality of first signal wirings each transmitting one of bits of the count signal from the counter to the plurality of memories each having a plurality of bit memories; and a plurality of second signal wirings, each connecting between the bit memories of the plurality of memories. Each of the second signal wirings is connected to one of the plurality of first signal wirings, and the first signal wirings and/or the second signal wirings include a signal wiring transmitting a signal of least significant bit in the count signal arranged between the plurality of other signal wirings each transmitting a signal of a bit different from the least significant bit in the count signal. 1. An analog-to-digital conversion circuit comprising:a plurality of comparators, each configured to output a comparing result signal indicating a result of comparing an analog signal with a reference signal having a signal level changing with elapse of time;a plurality of memories, each arranged correspondingly to one of the plurality of comparators;a counter configured to generate a count signal having a plurality of bits in Gray code by counting a clock signal; anda plurality of first signal wirings, each configured to transmit one of the plurality of bits of the count signal from the counter to the plurality of memories, whereineach of the plurality of memories holds the count signal according to a signal level change of the comparing result signal of corresponding one of the plurality of comparators, to convert the analog signal to a digital signal, and whereineach of the plurality of memories has a plurality of bit memories, each storing one bit of the plurality of bits,the analog-to-digital conversion circuit further comprises a plurality of second signal wirings, each connecting ...

COMPARATOR CIRCUITS WITH LOCAL RAMP BUFFERING FOR A COLUMN-PARALLEL SINGLE-SLOPE ADC

A comparator circuit suitable for use in a column-parallel single-slope analog-to-digital converter comprises a comparator, an input voltage sampling switch, a sampling capacitor arranged to store a voltage which varies with an input voltage when the sampling switch is closed, and a local ramp buffer arranged to buffer a global voltage ramp applied at an input. The comparator circuit is arranged such that its output toggles when the buffered global voltage ramp exceeds the stored voltage. Both DC- and AC-coupled comparator embodiments are disclosed. 1. A comparator circuit suitable for use in a column-parallel single-slope analog-to-digital converter , said comparator circuit comprising:an input node;a comparator;an input voltage sampling switch coupled to said input node;a sampling capacitor arranged to store a voltage which varies with an input voltage applied to said input node when said sampling switch is closed; anda local ramp buffer having an associated input and arranged to buffer a global voltage ramp applied directly to said local ramp buffer's input;said comparator circuit arranged such that the output of said comparator toggles when said buffered global voltage ramp exceeds said stored voltage.2. The comparator circuit of claim 1 , wherein said stored voltage is applied at a first input terminal of said comparator and said buffered global voltage ramp is applied at said comparator's second input terminal.3. The comparator circuit of claim 2 , wherein said sampling capacitor is connected between said comparator's first input terminal and a circuit common point and said sampling switch is connected between said input voltage and said comparator's first input terminal.4. The comparator circuit of claim 3 , said comparator circuit arranged to receive timing signals which operate said sampling switch such that said voltage is stored on said sampling capacitor before said global voltage ramp starts to ramp.5. A comparator circuit suitable for use in a column- ...

D/A CONVERSION CIRCUIT, QUANTIZATION CIRCUIT, AND A/D CONVERSION CIRCUIT

A D/A conversion circuit includes: an output terminal connected to an operational amplifier connected to a quantization circuit; a DAC capacitor; a selection switch switching among reference, first and second voltages to apply to the DAC capacitor as an analog potential; a ground switch connecting the DAC capacitor to a ground; and an output switch connecting the DAC capacitor to the output terminal. In a first period, the selection switch selects one of the reference, first and second voltages according to a quantization result value from the quantization circuit, and connects the one to the DAC capacitor, and the ground switch turns on to charge the DAC capacitor. In a second period, the selection switch selects another one of the first and second voltages, and connects the another one to the DAC capacitor, and the output switch turns on to output the analog potential to the output terminal. 1. A D/A conversion circuit having an output terminal connected to an input terminal of an operational amplifier that is connected to a quantization circuit , the D/A conversion circuit comprising:a DAC capacitor;a selection switch that selectively switches among a reference potential, a first voltage higher than the reference potential, and a second voltage lower than the reference potential to apply to an input side of the DAC capacitor as an analog potential;a ground switch that connects an output side of the DAC capacitor to an analog ground potential; andan output switch that connects the output side of the DAC capacitor to the output terminal, wherein:in a first period, the selection switch selects one of the reference potential, the first voltage and the second voltage according to one of four levels output from the quantization circuit as a quantization result value, and connects the one of the reference potential, the first voltage and the second voltage to the input side of the DAC capacitor, and the ground switch turns on to charge the DAC capacitor; andin a second ...

Receiver with Adjustable Reference Voltages

A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators. 1. A receiver comprising: a first reference generator to generate a first set of N reference voltages from a first set of M reference voltages where M is greater than N, the first reference generator adjusting voltage levels of the first set of N reference voltages based on one or more first control signals, the first reference generator comprising a plurality of switches coupled between voltage lines for the first set of M reference voltages and voltage lines for the first set of N reference voltages, the switches to selectively connect a subset of the voltage lines for the first set of M reference voltages to the voltage lines for the first set of N reference voltages based on the one or more first control signals; and', 'a first plurality of comparators to compare a first input signal to the first set of N reference voltages; and, 'a first analog to digital converter comprisingcalibration circuitry to generate the one or more first control signals for adjusting the voltage levels of the first N reference voltages based on outputs of the first plurality of comparators.2. (canceled)3. (canceled)4. The receiver of claim 1 , wherein the first reference generator comprises:a resistor string to generate the set of M reference voltages at a plurality of taps of the resistor string; anda current regulation circuit ...

Current amplifier circuit, integrator, and ad converter

In one embodiment, a current amplifier circuit includes a first transistor, a first resistor, a second transistor, a second resistor, a first passive element, and a control circuit. The first transistor has a first terminal, a second terminal, and a control terminal. The first resistor has one end connected to the first terminal of the first transistor. The second transistor has a first terminal, a second terminal, and a control terminal. The second resistor has one end connected to the first terminal of the second transistor. The first passive element is connected between the first terminals of the first transistor and the second transistor. The control circuit controls at least one of voltage at the control terminals of the first transistor and the second transistor such that the voltage at the other end of the first resistor becomes equal to the voltage at the other end of the second resistor.

METHOD AND DEVICE FOR SYNCHRONIZATION OF LARGE-SCALE SYSTEMS WITH MULTIPLE TIME INTERLEAVING SUB-SYSTEMS

A multi-instance time-interleaving (TI) system and method of operation therefor. The system includes a plurality of TI devices, each with a plurality of clock generation units (CGUs) coupled to an interleaver network. Within each TI device, the plurality of CGUs provides a plurality of clock signals needed by the interleaver network. A phase detector device is coupled to the plurality of TI devices and configured to determine any phase differences between the clock signals of a designated reference TI device and the corresponding clock signals of each other TI device. To determine the phase differences, the phase detector can use a logic comparator configuration, a time-to-digital converter (TDC) configuration, or an auto-correlation configuration. The phases of the clock signals of each other TI device can be aligned to the reference TI device using internal phase control, retimers, delay cells, finite state machines, or the like. 1. A phase detector device for a time-interleaving (TI) system , the phase detector device comprising:inputs configured to receive respective pluralities of clock signals from a plurality of TI devices, each of the respective pluralities of clock signals being generated by a respective one of the plurality of TI devices in accordance with a clock source; anda circuit configured to determine at least one of time and phase misalignment between outputs of the plurality of TI devices bycomparing a plurality of clock signals generated by a selected one of the plurality of TI devices to the pluralities of clock signals generated by each other TI device of the plurality of TI devices, anddetermining at least one of time and phase differences between the plurality of clock signals generated by the selected one of the plurality of TI devices and the pluralities of clock signals generated by the each other TI devices of the plurality of TI devices.2. The phase detector device of claim 1 , the circuit comprising a logic device configured to compare ...

DIGITAL-TO-ANALOG CONVERSION CIRCUIT, DIGITAL-TO-ANALOG CONVERSION METHOD, AND DISPLAY APPARATUS

Digital-to-analog conversion circuit, digital-to-analog conversion method, display apparatus are disclosed. Digital-to-analog conversion circuit may comprise: voltage dividing sub-circuit comprising M voltage dividing signal terminals; decoding sub-circuit comprising M input and output terminals, M input terminals electrically coupled to first to Mvoltage dividing signal terminals of voltage dividing sub-circuit respectively, decoding sub-circuit configured to receive digital signal and select one of M input terminals to be electrically connected with output terminal according to digital signal; amplification sub-circuit comprising input and output terminals, input terminal of amplification sub-circuit electrically coupled to output terminal of decoding sub-circuit, amplification sub-circuit configured to amplify signal at its input terminal, output analog gray-scale voltage at output terminal, voltage dividing signal at voltage dividing signal terminal is less than or equal to ½ of maximum load voltage at output terminal of digital-to-analog conversion circuit, amplification sub-circuit has amplification coefficient N greater than or equal to 2. 1. A digital-to-analog conversion circuit , comprising:a voltage dividing sub-circuit comprising M voltage dividing signal terminals, wherein M is a natural number greater than 2;{'sup': 'th', 'a decoding sub-circuit comprising M input terminals and an output terminal, wherein the M input terminals are electrically coupled to the first to Mvoltage dividing signal terminals of the voltage dividing sub-circuit respectively, and the decoding sub-circuit is configured to receive a digital signal and select one of the M input terminals to be electrically connected with the output terminal according to the digital signal; and'}an amplification sub-circuit comprising an input terminal and an output terminal, wherein the input terminal of the amplification sub-circuit is electrically coupled to the output terminal of the decoding ...

A/D CONVERTER

An A/D converter includes: a sampler that includes a sampling capacitor and samples an input signal; a D/A converter that selectively outputs an analog voltage; an integrator that integrates an input from the sampler and an input from the D/A converter; Multiple switches that include a first switch independently connecting the sampler to the integrator, a second switch independently connecting the D/A converter to the integrator, a third switch, and, a fourth switch, a quantizer that quantizes an output of the integrator; a control circuit that outputs a digital value based on an output of the quantizer, and a reference potential generation circuit that provides a second reference potential to an integrator side of the sampler through the third switch and provides a first reference potential to the integrator side of the D/A converter through the fourth switch. 1. An A/D converter comprising:a sampler that includes a sampling capacitor and is configured to sample an input signal;a D/A converter configured to selectively output an analog voltage in accordance with a control signal;an integrator configured to integrate an input from the sampler and an input from the D/A converter;{'sup': '.', 'a plurality of switches that includes a first switch independently connecting the sampler to the integrator, a second switch independently connecting the D/A convertor to the integrator, a third switch, and, a fourth switch;'}a quantizer configured to quantize an output of the integrator;a control circuit configured to output a digital value based on an output of the quantizer; anda reference potential generation circuit configured to provide a second reference potential to an integrator side of the sampler through the third switch and provide a first reference potential to the integrator side of the D/A converter through the fourth switch.2. The A/D converter according to claim 1 , wherein:the plurality of switches further include a fifth switch; andthe reference potential ...

GRAY COUNTER AND ANALOGUE-DIGITAL CONVERTER USING SUCH A COUNTER

An N-bit Gray counter, with N an integer greater than 1, comprises a string of N logic cells connected in cascade, wherein each logic cell comprises an input port for a succession of clock pulses, a circuit for generating a Gray count bit having an output port for the Gray count bit and a circuit for generating a clock signal having a clock output port linked to the input port of the following logic cell. An analogue-digital converter of ramp type using such a Gray counter is also provided. 1. An N-bit Gray counter , with N an integer greater than 1 , comprising a string of N logic cells connected in cascade , wherein each said logic cell comprises an input port for a succession of clock pulses and a generating circuit for generating a Gray count bit having an output port for the said Gray count bit , wherein each said logic cell , except at most the last logic cell , of the string also comprises a circuit for generating a clock signal having a clock output port linked to the input port of the following logic cell , and wherein:each said circuit for generating a clock signal is adapted for authorizing the passage to the clock output port of one clock pulse out of two present at the input port and for prohibiting the passage of the following clock pulse;the generating circuit for generating a Gray count bit for each said logic cell, with the exception of the last logic cell of the string, is adapted for inverting the value of the count bit present at its output port each time that the circuit for generating a clock signal of the corresponding logic cell prohibits the passage of a said clock pulse, and for maintaining the value unchanged in the converse case; andthe generating circuit for generating a Gray count bit for the last logic cell of the string is adapted for inverting the value of the count bit present at its output port each time that a clock pulse is present at the input port of the last logic cell.2. The Gray counter according to claim 1 , wherein the ...

METHOD AND DEVICE FOR ANALOG/DIGITAL CONVERSION OF AN ANALOG SIGNAL

A method includes a first analog/digital conversion of an analog signal over m bits, with m less than n, associated with a first full-scale value, and a second analog/digital conversion of the analog signal over m bits associated with a second full-scale value 2times bigger than the first. The two analog/digital conversions are carried out simultaneously and respectively delivering a first intermediate digital word of m bits and a second intermediate digital word of m bits. The method also includes a digital post-processing carried out after the two analog/digital conversions and generating an n-bit digital word starting from at least one of the two intermediate digital words extended to n bits and from at least one threshold digital indication representative of at least one threshold lower than or equal to the first full-scale value. 111-. (canceled)12. A method for analog/digital conversion , the method comprising:performing a first analog/digital conversion of an analog signal over m bits, with m less than n, associated with a first full-scale value, to generate a first intermediate digital word of m bits;{'sup': 'n-m', 'simultaneously performing a second analog/digital conversion of the analog signal over m bits associated with a second full-scale value higher than the first full-scale value by a gain ratio having a value equal or substantially equal to 2, to generate a second intermediate digital word of m bits; and'}generating an n-bit digital word starting from at least one of the first and second intermediate digital words extended to n bits and from at least one threshold digital indication representative of at least one threshold lower than or equal to the first full-scale value.13. The method according to claim 12 , wherein the first analog/digital conversion being carried out in a first ramp-type converter and comprises generating a first voltage ramp delivered to an input of the first ramp-type converter by a first capacitive connection.14. The method ...

FLASH ADC WITH INTERPOLATORS

An ADC is provided. The ADC includes a plurality of pre-amplifiers, dynamic comparators coupled to the pre-amplifiers, interpolators and an encoder. Each pre-amplifier provides a pair of differential outputs according to a pair of differential analog signals and a first reference voltage and a second reference voltage different from the first reference voltage. Each dynamic comparator provides a first comparing signal and a second comparing signal according to the pair of differential outputs of the corresponding pre-amplifier. Each interpolator provides an interpolating signal according to the first and second comparing signals of two of the dynamic comparators. The encoder provides a digital output according to the interpolating signals. The first and second comparing signals are the same in a reset phase, and the first and second comparing signals are complementary according to the pair of differential outputs of the corresponding pre-amplifier in an evaluation phase. 1. An analog-to-digital converter , comprising:a plurality of pre-amplifiers, each receiving a pair of differential analog signals, a first reference voltage corresponding to one of the differential analog signals and a second reference voltage corresponding to another of the differential analog signals, and amplifying difference between the pair of differential analog signals and the first and second reference voltages to provide a pair of differential outputs, wherein the first reference voltage is different from the second reference voltage;a plurality of dynamic comparators coupled to the pre-amplifiers, each providing a first comparing signal and a second comparing signal according to the pair of differential outputs of the corresponding pre-amplifier;a plurality of interpolators, each providing an interpolating signal according to the first and second comparing signals of two of the dynamic comparators; andan encoder, providing a digital output according to the interpolating signals,wherein ...

ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERSION METHOD

According to an embodiment, an analog-to-digital (AD) converter includes a first AD conversion unit, a selector and a second AD conversion unit. The first AD conversion unit performs AD conversion of an analog signal in a first period to generate an upper-bit digital signal. The selector selects not less than one reference voltage based on the upper-bit digital signal to obtain a selected reference voltage group in a voltage range narrower than a full scale. The second AD conversion unit performs AD conversion of the analog signal by using the selected reference voltage group. The first period starts before settling of the analog signal up to an accuracy corresponding to a total resolution of the first AD conversion unit and the second AD conversion unit. 1. An analog-to-digital converter comprising:a first analog-to-digital conversion unit configured to perform analog-to-digital conversion of an analog signal in a first period to generate an upper-bit digital signal;a selector configured to select not less than one reference voltage based on the upper-bit digital signal to obtain a selected reference voltage group in a voltage range narrower than a full scale; anda second analog-to-digital conversion unit configured to perform analog-to-digital conversion of the analog signal by using the selected reference voltage group to generate a lower-bit digital signal,wherein the first period starts before settling of the analog signal up to an accuracy corresponding to a total resolution of the first analog-to-digital conversion unit and the second analog-to-digital conversion unit.2. The converter according to claim 1 , wherein the selector selects a plurality of reference voltages based on the upper-bit digital signal to obtain the selected reference voltage group.3. The converter according to claim 2 , wherein the selector selects a second reference voltage lower than a first reference voltage corresponding to the upper-bit digital signal by a (a is an integer) steps ...

Semiconductor device

The present disclosure provides a semiconductor device including: a resistance section that includes a first terminal and a second terminal disposed in contact with an outer periphery, and a serial resistance section in which plural resistance elements are connected in series, wherein one end of the serial resistance section is connected to the first terminal, and another end of the serial resistance section is connected to the second terminal; and a current adjustment section that includes a current source that supplies current to the serial resistance section, and disposed adjacent to the resistance section such that a distance between the first terminal and the current adjustment section along the outer periphery of the resistance section and a distance between the second terminal and the current adjustment section along the outer periphery of the resistance section are equal.

ANALOG-TO-DIGITAL CONVERTER

Improvement of conversion precision in an analog-to-digital converter is realized. Therefore, a voltage of a correction signal and a voltage obtained by attenuating the voltage with a fixed attenuation rate by an attenuation circuit are generated and each voltage is input to an analog-to-digital conversion unit . A correction unit receives a digital output from the analog-to-digital conversion unit , searches a correction coefficient Wof each bit of the analog-to-digital conversion unit , based on an adaptive control algorithm, and corrects the digital output from the analog-to-digital conversion unit using the searched correction coefficient W. 1. An analog-to-digital converter , comprising:an attenuation circuit to which a plurality of first analog voltages having different voltage values are sequentially input and which attenuates the plurality of first analog voltages with a predetermined attenuation rate and sequentially outputs a plurality of second analog voltages;a first selection circuit to which the first and second analog voltages of a plurality of sets including sets of the first analog voltages and the second analog voltages obtained by attenuating the first analog voltages are sequentially input and which selects each analog voltage of the first and second analog voltages of the plurality of sets at different timing and outputs each analog voltage;an analog-to-digital conversion unit which converts the first and second analog voltages of the plurality of sets output from the first selection circuit into first and second digital signals of a plurality of sets; anda correction unit which searches M (M is an integer of 1 or more) correction coefficients multiplied with M bits of the first and second digital signals of the plurality of sets, based on the first and second digital signals of the plurality of sets.2. The analog-to-digital converter according to claim 1 , whereinthe attenuation circuit includes a resistive voltage division circuit or a ...

SAR ANALOG-TO-DIGITAL CONVERTING APPARATUS AND OPERATING METHOD THEREOF AND CMOS IMAGE SENSOR INCLUDING THE SAME

A Successive Approximation Register (SAR) analog-to-digital converting apparatus includes a reference voltage supply unit suitable for supplying different reference voltages depending on bits of a pixel output signal to be converted, an N bit SAR analog-to-digital conversion unit suitable for sequentially converting upper N−1 bits and lower N bits of the pixel output signal by selectively using the reference voltages supplied from the reference voltage supply unit, where N is a natural number, and an error correction unit suitable for calculating an error correction value based on a difference between conversion results of the lower N bits, and outputting a 2N−2 bit analog-to-digital conversion result by combining converted upper N−1 bits and converted lower N bits and correcting an error of the reference voltages using the error correction value in the combining. 1. A Successive Approximation Register (SAR) analog-to-digital converting apparatus , comprising:a reference voltage supply unit suitable for supplying different reference voltages depending on bits of a pixel output signal to be converted;an N bit SAR analog-to-digital conversion unit suitable for sequentially converting upper N−1 bits and lower N bits of the pixel output signal by selectively using the reference voltages supplied from the reference voltage supply unit, where N is a natural number; andan error correction unit suitable for calculating an error correction value based on a difference between conversion results of the lower N bits, and outputting a 2N−2 bit analog-to-digital conversion result by combining converted upper N−1 bits and converted lower N bits and correcting an error of the reference voltages using the error correction value in the combining.2. The SAR analog-to-digital converting apparatus of claim 1 , wherein the reference voltage supply unit includes:a reference voltage generator suitable for outputting the different reference voltages depending on the bits of the pixel output ...

ANALOG TO DIGITAL CONVERTER WITH HIGH PRECISION OFFSET CALIBRATED INTEGRATING COMPARATORS

An analog-to-digital converter includes a plurality of slave sampler multiplexers responsive to outputs of a master sampler that receives analog signals and whose output ports connect to integrating threshold comparators having capacitive digital-to-analog conversion offset adjustments for forming an analog-to-thermometer code conversion. A calibration state machine receives outputs of each of the integrating threshold comparators to control the capacitive digital-to-analog conversion offset adjustment of every integrating threshold comparator and to control a calibration digital-to analog converter. A thermometer code to binary code logic decoder receives outputs of each of the integrating threshold comparators and outputs digital samples. 1. An analog-to-digital converter comprising:a plurality of integrating threshold comparators for forming analog-to-thermometer code conversions;a thermometer code to binary code logic decoder configured to receive and combine outputs of each of the integrating threshold comparators and output digital samples, anda coarse resistance ladder comprising a first resistance ladder of the coarse resistance ladder configured to provide a positive reference voltage to each of the integrating threshold comparators and a second resistance configured to provide a negative reference voltage to each of the integrating threshold comparators.wherein capacitive digital-to-analog conversion offset adjustment of the integrating threshold comparators is controlled by a calibration state machine, andwherein each integrating threshold comparator is configured to receive a pair of differential input data signals and a pair of differential input reference signals.2. The analog-to-digital converter of claim 1 , wherein the coarse resistive ladder is configured to establish a baseline comparator threshold for each of the integrating threshold comparators.3. The analog-to-digital converter of claim 2 , wherein when in slave hold mode claim 2 , the ...

GAIN CALIBRATION DEVICE AND METHOD FOR RESIDUE AMPILIFIER OF PIPELINE ANALOG TO DIGITAL CONVERTER

A gain calibration device for an ADC residue amplifier includes a DAC and a flash ADC. The DAC is configured to convert the digital signal to an analog signal, and the DAC includes a calibration module used in the gain calibration of the ADC residual amplifier. The flash ADC is configured to generate a digital signal, the flash ADC includes a plurality of comparators, the total number of the plurality of comparators is equal to the number of output bits of the flash ADC, and the comparators are configured to be unevenly distributed in an input range. 1. A gain calibration device for an analog to digital converter (ADC) residual amplifier , the gain calibration device comprising:a digital to analog converter (DAC) configured to convert a digital signal to an analog signal, wherein the DAC includes a calibration module used in a gain calibration of the ADC residue amplifier; anda flash analog to digital converter (ADC) configured to generate the digital signal and including a plurality of comparators,wherein a number of the plurality of comparators is equal to a number of output bits of the flash ADC, and wherein the plurality of comparators are uneven comparators providing a plurality of threshold voltages that are unevenly distributed in a input range.2. The gain calibration device according to claim 1 , wherein the flash ADC is configured to generate the digital signal by digitally converting a sampling signal of an input signal.3. The gain calibration device according to claim 2 , further including a part of a stage of a pipeline analog-digital converter (ADC) claim 2 , wherein the pipeline ADC includes the ADC residue amplifier configured to amplify a residue signal.4. The gain calibration device according to claim 3 , wherein the residue signal is generated by subtracting the analog signal from the sampling signal of the input signal.5. The gain calibration device according to claim 2 , wherein the input range includes a zero point voltage of the input signal.6. ...

Systems and Methods for Testing Analog to Digital (A/D) Converter with Built-In Diagnostic Circuit with User Supplied Variable Input Voltage

A method for testing an A/D converter with a built-in diagnostic circuit with a user supplied variable input voltage includes generating a charge by a binary-weighted capacitor array responsive to an external voltage and a user specified code. The method further includes applying the charge to a first input of a voltage comparator and applying a bias voltage to a second input of the voltage comparator, and generating, by the voltage comparator, a comparison voltage responsive to the applied charge and the bias voltage. The method also includes applying the comparison voltage to an input of a successive approximation register and generating, by the successive approximation register, an approximate digital code responsive to the comparison voltage. The method also includes determining if at least one bit of the approximate digital code fails to toggle independent of adjacent bits. 1. A method of testing an analog to digital (A/D) converter with a built-in diagnostic circuit , the method comprising:generating a charge by a binary-weighted capacitor array responsive to an external voltage and a user specified code;applying the charge to a first input of a voltage comparator and applying a bias voltage to a second input of the voltage comparator, and generating, by the voltage comparator, a comparison voltage responsive to the applied charge and the bias voltage;applying the comparison voltage to an input of a successive approximation register and generating, by the successive approximation register, an approximate digital code responsive to the comparison voltage; anddetermining if at least one bit of the approximate digital code fails to toggle independent of adjacent bits.2. The method of claim 1 , further comprising:varying the user specified code; anddetermining if at least one bit of the approximate digital code fails to toggle independent of adjacent bits responsive to the varying the user specified code, wherein a fault bit is detected if at least one bit fails ...

Analog-to-digital converter (adc) with improved power disturbance reduction

Disclosed herein is an analog-to-digital converter (ADC) for converting an input analog voltage to an output digital code, the ADC comprising a first node of the input analog voltage: nodes of a plurality of reference voltages; a plurality of comparators, inputs of each comparator being coupled to the first node and a node of a corresponding reference voltage of the plurality of reference voltages; a logic circuit block for receiving outputs of the plurality of comparators and generating the output digital code; and a voltage stabilizer, terminals of the voltage stabilizer being coupled with the first node and a node of a first reference voltage among the plurality of reference voltages.

Image pickup device, image pickup system, driving method for image pickup device, and driving method for image pickup system

In an image pickup device, in a period for which a signal value of the comparison result signal is changed in a certain AD converter among a plurality of AD converters, the signal value of the comparison result signal changes a plurality of times in another AD converter.

MULTI-ZONE DATA CONVERTERS

Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone. 120-. (canceled)21. A multi-zone analog-to-digital converter , comprisingan analog input configured to receive an analog input signal;a digital output configured to output a generated digital output signal representative of the analog input signal; anda plurality of comparators comprising a first one or more comparators associated with a first voltage range of the analog input signal and a second one or more comparators associated with a second voltage range of the analog input signal;wherein each comparator of the plurality of comparators is configured to perform a comparison of the received analog input signal to a respective reference voltage from a plurality of reference voltages signal; andwherein the first one or more comparators provide greater resolution for the generated digital output signal than the second one or more comparators.22. The multi-zone analog-to-digital converter of claim 21 , wherein:the plurality of comparators further comprise a third one or more comparators associated with a third voltage range of the analog input signal; andthe first one or more comparators provide greater resolution for the generated digital output signal than the third one or more comparators.23. The multi-zone analog-to-digital converter of claim 22 , wherein:the second voltage range corresponds to a low voltage range of the analog input signal;the third voltage range corresponds to a high voltage range of the analog input signal; andthe first voltage range corresponds to a central voltage range ...

MULTI-ZONE DATA CONVERTERS

Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone. 1. A method , comprising:receiving a first input signal with a data converter having a plurality of operating zones;in response to determining that the first input signal corresponds to a first operating zone of the plurality of operating zones, converting the first input signal to a first output signal per a first circuit of the data converter;receiving a second input signal with the data converter; andin response to determining that the second input signal corresponds to a second operating zone of the plurality of operating zones, converting the second input signal to a second output signal per a second circuit of the data converter that is designed to have better operating characteristics than those of the first circuit.2. The method of claim 1 , wherein:said receiving the second input signal comprises receiving a digital input code from the second input signal; andsaid converting to the second output signal comprises generating an analog output value for the second output signal that is dependent upon the received digital input code.3. The method of claim 1 , wherein:said receiving the second input signal comprises receiving an analog input value from the second input signal; andsaid converting to the second output signal comprises generating a digital output code for the second output signal that is dependent upon the received analog input value.4. The method of claim 1 , wherein the second operating zone corresponds to a central operating zone of the plurality of operating zones.5. The ...

Asynchronous to synchronous sampling using akima algorithm

A method, comprising: selecting three Two-Tuples before and three after a selected synchronous ADC conversion point; calculating the coefficients of a third order polynomial based on the value of the previous time asynchronous sample, the time difference between the asynchronous samples surrounding the selected sample, and the five linear slopes of the line segments between the three points before and the points after the selected synchronous sample point, including the slope of the selected point; evaluating the third order polynomial at the synchronous time instant; generating the synchronous ADC value based on this calculation; and using the ADC value as the desired voltage level of the synchronous sample, wherein the synchronous ADC value is generated based on this calculation.

EQUALIZATION CIRCUIT, A METHOD OF OPERATING AN EQUALIZATION CIRCUIT AND A SYSTEM COMPRISING AN EQUALIZATION CIRCUIT AND AN ADC

The present application relates to an EQ circuit, a method of operating it and a system comprising the EQ circuit and an ADC. The EQ circuit has a configurable load section, which is provided for selectively exposing one of a plurality of distinct loads to a reference source connected to a reference voltage signal input of the equalization circuit, and a logic section, which is arranged to accept a state signal from the ADC and to selectively connect one distinct load out of the plurality of distinct loads in response to the state signal. The state signal is indicative of an actual operation state of the ADC. 1. An equalization circuit , comprising:a configurable load section comprising a plurality of distinct effective loads, each effective load configured to be selectively connected to a reference voltage signal input of a reference source,a logic section arranged to accept a state signal from an analog-to-digital converter (ADC) connected to the reference source and to selectively connect one effective load out of the plurality of distinct effective loads in response to the state signal,wherein the state signal is indicative of an actual operation state of the ADC.2. The equalization circuit according to claim 1 ,wherein a total load, which is experienced by the reference source and which comprises the one effective load of the equalization circuit and a load of the ADC, is equal to or greater than a predefined minimum load at least during at least one of a conversion phase and a sampling phase of the ADC.3. The equalization circuit according to claim 1 ,wherein the one effective load is selected based on a function of the actual operation state of the ADC.4. The equalization circuit according to claim 1 ,wherein the plurality of distinct effective loads comprises a plurality of distinct effective capacitive loads.5. The equalization circuit according to claim 1 ,wherein the ADC is a charge redistribution successive approximation register ADC (CR SAR ADC) ...

DELTA-SIGMA MODULATOR, DELTA-SIGMA MODULATION TYPE A/D CONVERTER AND INCREMENTAL DELTA-SIGMA MODULATION TYPE A/D CONVERTER

A ΔΣ modulator includes an input circuit having a sampling capacitor, an integration circuit, a quantizer and a D/A converter having a DAC capacitor. The input circuit takes in an analog input voltage in the sampling capacitor in a sampling period, and transfers a charge to the integration circuit in a holding period. The D/A converter takes in an analog potential, to which selection switches are connected in the sampling period based on a digital output of the quantizer, in the DAC capacitor, and subtracts a charge from the integration circuit in the holding period. At this time, since the input circuit and the D/A converter are set so that the holding periods do not overlap with each other, an error caused by the lowering of a feedback factor is suppressed. 1. A ΔΣ modulator comprising:an input circuit configured to store a charge corresponding to an analog input voltage in a sampling capacitor in a sampling period thereof and transfer the charge of the sampling capacitor in a holding period thereof;a D/A converter configured to store a charge, which corresponds to one of a plurality of analog potentials, in a DAC capacitor in a sampling period thereof in accordance with a quantization result;an integration circuit configured to integrate the charge stored in the input circuit and the charge stored in the D/A converter;a quantizer configured to quantize an output of the integration circuit; anda control circuit configured to control the sampling periods and the holding periods of the input circuit and the D/A converter based on the quantization result of the quantizer and transfer the charge of the DAC capacitor in a holding period thereof,wherein the control circuit is configured to control the holding period of the input circuit and the holding period of the D/A converter not to overlap with each other.2. The ΔΣ modulator according to claim 1 , wherein:the control circuit is configured to control a sampling operation and a subsequent holding operation of the D/A ...

ELECTRIC SIGNAL CONVERSION

In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction. 123-. (canceled)24. An electrical signal converter , comprising:an input for receiving a first species of signal;at least four discrete converter elements for converting the first species of signal into a second species of signal, wherein the converter elements are arranged in an array;a switch for mapping the input to the converter elements; and on a first cycle, use a first converter element at a first position to convert the input; and', 'on a second cycle, use a second converter element at a second position to convert the input, wherein the second position is no more than two positions away from the first position., 'logic configured to cause the switch to25. The electrical signal converter of claim 24 , wherein the converter elements are digital-to-analog converter elements.26. The electrical signal converter of claim 25 , comprising a plurality of inputs claim 25 , and wherein the plurality of inputs form a thermometer code.27. The electrical signal converter of claim 24 , wherein the converter elements are analog-to-digital converters.28. The electrical signal converter of claim 27 , wherein the second species of signal comprises a thermometer code.29. The electrical signal converter of claim 24 , wherein the logic is configured to select the second position according to a pseudorandom input.30. The electrical signal converter of claim 24 , wherein the logic is configured to select the second position according to a pseudorandom input plus a constant. ...

Measurement Circuit

A measurement circuit for providing the maximum and/or minimum voltage of a time-variant electrical input signal is presented. The measurement circuit contains a voltage reference unit to provide voltage reference signals and a comparator unit comprising multiple comparators. Each comparator receiving the electrical input signal at a first comparator input and a different voltage reference signal from the voltage reference unit at its second comparator input. The comparator unit provides comparator output signals based on said electrical input signal and said voltage reference signals. A logic unit receives the comparator output signals and provides a voltage output signal indicative of the maximum and/or minimum voltage of the electrical input signal based on the comparator output signals. The logic unit provides adaptation information to the voltage reference entity. The is adaptation information is dependent on the comparator output signals. The voltage reference unit adapts the voltage reference signals based on the adaption information.

SEMICONDUCTOR INTEGRATED CIRCUIT AND RECEIVER DEVICE

A semiconductor integrated circuit according to an embodiment includes an A/D converter, first and second equalizer circuits, and first and second controllers. The first equalizer circuit includes a first tap. The first and second equalizer circuits receive a signal based on a digital signal, and output first and second signals, respectively. The first controller adjusts a phase of a clock signal based on the first signal. The second controller an operation of adjusting a control parameter including a tap coefficient. In the operation, the second controller adjusts a tap coefficient of each of taps of the second equalizer circuit, and adjusts a tap coefficient of the first tap based on an adjustment result of each tap coefficient of the second equalizer circuit. 1. A semiconductor integrated circuit comprising:an A/D converter configured to convert an analog signal into a digital signal based on a clock signal;a first equalizer circuit includes a plurality of taps including a first tap that is one tap after a center tap, the first equalizer circuit receiving a signal based on the digital signal and outputting a first signal;a first data comparator circuit configured to determine data based on the first signal and output the determined data as first data;a second equalizer circuit includes a plurality of taps, the second equalizer circuit receiving a signal based on the digital signal and outputting a second signal;a second data comparator circuit configured to determine data based on the second signal and output the determined data to an outside;a first control circuit configured to adjust a phase of the clock signal based on the first signal and the first data, and input the adjusted clock signal to the A/D converter; anda second control circuit configured to control each of the first equalizer circuit and the second equalizer circuit, and execute an operation of adjusting a control parameter including a tap coefficient, whereinin the operation, the second control ...

Analog-digital converter

A parallel-type AD converter includes: a plurality of comparators that receive comparison reference potentials different from one another and compare the comparison reference potentials and received analog input signals; an encoder that encodes outputs of the plurality of comparators to output digital signals; and a resistor ladder circuit that resistance-divides a reference voltage to generate the comparison reference potentials and supplies the comparison reference potentials to the comparators through output nodes each positioned between resistors, and is designed to supply a correction current corresponding to noise currents that the comparators generate to the output nodes of the comparison reference potentials in the resistor ladder circuit, and thereby the noise currents that the comparators generate are offset by the correction current, a bias current in the resistor ladder circuit can be decreased, and accuracy deterioration in AD conversion can be suppressed.

Quantizer

In one embodiment the quantizer includes a signal-to-phase converter configured to generate a phase signal according to an input signal and a phase difference digitization block configured to generate a quantization output according to differentiated samples of the phase signal, where the phase signal generated by the signal-to-phase converter has a sinusoidal shape. 1. A quantizer comprising:a signal-to-phase converter configured to generate a phase signal according to an input signal; anda phase difference digitization block configured to generate a quantization output according to differentiated samples of the phase signal, where the phase signal generated by the signal-to-phase converter has a sinusoidal shape.2. The quantizer of claim 1 , wherein the signal-to-phase converter is configured to generate a multiplicity of phase signals according to the input signal claim 1 , and wherein the phase difference digitization block is configured to generate a multiplicity of quantization outputs according to differentiated samples of the phase signals.3. The quantizer of claim 2 , wherein the signal-to-phase converter comprises one controllable oscillator with a differential phase output.4. The quantizer of claim 2 , wherein the signal-to-phase converter comprises two controllable oscillators each with a non-differential phase output.5. The quantizer of claim 2 , wherein the signal-to-phase converter comprises at least one controllable oscillator with a differential circuit structure.6. The quantizer of claim 1 , wherein the phase difference digitization block comprises:a sampler configured to sample the phase signal and generate a quantized phase signal; anda phase differentiator coupled to the sampler and configured to generate the quantization output by differentiating the quantized phase signal(s).7. The quantizer of claim 1 , wherein the signal-to-phase converter is a voltage or current controlled sinus oscillator.8. The quantizer of claim 1 , wherein the signal-to ...

Pinstrap detection circuit

In at least some examples, an integrated circuit includes an input pin and an analog-to-digital converter (ADC) comprising an input terminal coupled to the input pin and an output terminal. The integrated circuit further includes a logic circuit comprising an input terminal coupled to the output terminal of the ADC, a first output terminal, and a second output terminal. The integrated circuit further includes a resistance circuit. In an example, the resistance circuit includes a resistor coupled between the input pin and a first node, a first switch coupled between the first node and a reference voltage pin, and a second switch coupled between the first node and a ground pin.

METHOD AND APPARATUS FOR CONVERTING AN ANALOG SIGNAL TO A DIGITAL SIGNAL BASED ON REFERENCE VOLTAGES PROVIDED BY REFERENCE LADDERS

A circuit including first and second reference ladders, a selection circuit, first and second analog to digital converters (ADCs), and a summer. The first reference ladder is configured to provide first reference voltages via first taps. The selection circuit is configured to select one of the first reference voltages. The second reference ladder is configured to, based on the selected one of the first reference voltages, provide second reference voltages via second taps. The first ADC is configured to convert the first version of the analog input signal to a first digital signal. The second ADC is configured to, based on the second reference voltages, convert the second version of the analog input signal to a second digital signal. The summer is configured to generate a digital output signal based on the first and second digital signals. 1. A circuit comprising:a first reference ladder configured to provide a plurality of first reference voltages via a plurality of first taps;a selection circuit connected to the plurality of first taps, wherein the selection circuit is configured to select one of the plurality of first reference voltages;a second reference ladder configured to, based on the selected one of the plurality of first reference voltages, provide a plurality of second reference voltages via a plurality of second taps;a first analog to digital converter configured to (i) receive a first version of an analog input signal, and (ii) convert the first version of the analog input signal to a first digital signal;a second analog to digital converter connected to the plurality of second taps, wherein the second analog to digital converter is configured to (i) receive a second version of the analog input signal, and (ii) based on the plurality of second reference voltages, convert the second version of the analog input signal to a second digital signal; anda summer configured to generate a digital output signal based on (i) the first digital signal, and (ii) the ...

Analog-to-digital converters

An analog-to-digital converter ADC may be provided. The ADC may include a current driving circuit. The current driving circuit may include an additive current driving circuit and a subtractive current driving circuit configured for adjusting a voltage level of a node. The ADC may include a comparison circuit including a plurality of comparators. Each of the plurality of comparators may be configured to compare a voltage level of the node with a reference voltage.

FREQUENCY-DOMAIN ADC FLASH CALIBRATION

A flash analog-to-digital converter (ADC) includes comparators that convert an analog input signal to a digital output signal. Offsets of these comparators introduce noise and can hurt the performance of the ADC. Thus, these comparators are calibrated using calibration codes. Conventional calibration methods determine these calibration codes by removing the ADC from an input signal. Otherwise, it is difficult to distinguish the noise from the signal in the calibration measurement. In contrast, an embodiment can determine the calibration codes while the ADC converts the input signal to a digital signal. Such an embodiment can be achieved by a frequency-domain technique. In an embodiment employing a frequency-domain power meter, an input signal can be removed from the power measurement. This removal enables accurate measurement of in-band noise without having the measurement be corrupted by input signal power. 1. A calibration system to calibrate an offset of a comparator of an analog-to-digital (ADC) converter , comprising:the analog-to-digital converter (ADC), which includes a plurality of comparators that convert an analog input to digital data, the plurality of comparators including the comparator;a frequency filter to filter the digital data to produce a filtered signal; andcalibration logic configured to adjust the offset the comparator based on the filtered signal.2. The calibration system of claim 1 , wherein the calibration logic is configured to determine a calibration code for the comparator to minimize a power of the digital data.3. The calibration system of claim 2 , wherein the comparator converts the analog input to digital data based on the calibration code.4. The calibration system of claim 1 , further comprising:a frequency summer that sums the filtered signal to produce a power signal, wherein the calibration logic adjusts the offset of the comparator based on the power signal.5. The calibration system of claim 1 , wherein the filter is implemented ...

System and Method for Analog to Digital Conversion

Parallel analog to digital converted (ADC) architectures that can be used to replace single path ADC architectures. The parallel ADC architecture can comprise N branches and one ADC per branch. These ADCs can be identical. However each branch can have a different path adjustments applied to the ADC. The path adjustments can be biases and/or gains and each ADC receives a different combination of biases and/or gain to generate multiple adjusted input signals. These are then combined to generate a quantised output signal. Using these parallel architectures a range of weighting and offset combining schemes can be employed to achieve improvements in signal to noise ratio and to reduce the impact of clipping as compared to a single path ADC architecture. 1. A method for generating one or more quantised output signals from an analog input signal , the method comprising:splitting the analog input signal into a plurality of signal paths and applying a path adjustment to each signal path to generate a plurality of adjusted input signals, wherein the path adjustment comprises one or both of a path gain and a bias;quantising each of the plurality of adjusted input signals to generate a plurality of quantised signals; andgenerating one or more quantised output signals based on the plurality of quantised signals, wherein the step of generating one or more quantised output signals comprises applying a weight and/or offset to each quantised signal and a function of weighted and/or offset quantised signals generates the quantised output signal.2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. The method as claimed in claim 1 , wherein a weight of zero is applied to the quantised signal if the magnitude of the respective adjusted input signal is greater than a magnitude threshold.7. (canceled)8. The method as claimed in claim 6 , wherein if the magnitude of each of the plurality of adjusted input signals is greater than the respective magnitude threshold claim 6 , then the ...

Analog-to-digital converter

An analog-to-digital converter that converts an inputted analog signal into a digital value is disclosed that may include unit circuits that each generate reference voltages comprising regular potential intervals by a series resistor circuit connected between a high potential side reference voltage and a low potential side reference voltage and convert the reference voltages into a digital value by comparing the reference voltages with the inputted analog signal, and an adder that adds the digital values converted by the unit circuits. Each unit circuit may include coupling switches that couple the series resistor circuit with the series resistor circuit of another one of the unit circuits and connect the series resistor circuits between the high potential side reference voltage and the low potential side reference voltage and a sharing switch that shares the inputted analog signal with the other unit circuit that is coupled with the series resistor circuit.

ANALOG-DIGITAL CONVERSION CIRCUIT, SENSOR APPARATUS, CELLULAR PHONE, AND DIGITAL CAMERA

An analog-digital conversion circuit (ADC) includes: a capacitor (C); a charge and discharge control section () that puts, into the capacitor (C), an electric charge corresponding to an input current of a first period and that causes an electric charge corresponding to an input current of a second period to be discharged from the capacitor (C); and a digital conversion section () that converts an amount of electric charge of the capacitor (C) into a digital signal. 1. An analog-digital conversion circuit comprising:a first capacitor;a digital conversion section that converts an amount of electric charge stored in the first capacitor into a digital signal; anda charge and discharge control section that controls charge and discharge of the first capacitor,the charge and discharge control section putting, into the first capacitor, an electric charge corresponding to an electric current inputted to the analog-digital conversion circuit during a first period,the charge and discharge control section causing an electric charge corresponding to an electric current inputted to the analog-digital conversion circuit during a second period that follows the first period to be discharged from the first capacitor,the charge and discharge control section performs more than once a charge and discharge cycle including (i) charging the first capacitor during the first period and (ii) discharging the first capacitor during the second period,during an analog-digital conversion period that comes after the end of the charge and discharge control carried out by the charge and discharge control section, the digital conversion section converting an amount of electric charge stored in the first capacitor at the end of the charge and discharge control into a digital signal.2. (canceled)3. The analog-digital conversion circuit as set forth in claim 1 , wherein:the digital conversion section includes(i) a second capacitor having a capacitance that is lower than the capacitance of the first ...

REDUCTION OF INPUT DEPENDENT CAPACITOR DAC SWITCHING CURRENT IN FLASH-SAR ANALOG-TO-DIGITAL CONVERTERS

Circuits and methods for reducing input dependent capacitor DAC switching current in flash-successive approximation register (SAR) analog-to-digital converters (ADCs) are disclosed. An ADC includes an M-bit flash ADC and N-bit SAR ADC. In flash conversion phase, flash ADC outputs digital signal including most significant M-bits of N-bits of digital output code for a sampled analog signal. SAR ADC includes capacitor DAC and digital engine. The capacitor DAC includes first and second set of capacitors, where first ends of the first and second set of capacitors are coupled to common terminal. The digital engine provides the N-bits of digital output code in SAR conversion phase based on the digital signal and a voltage (Vcom) at the common terminal. During flash conversion phase, second ends of the first set of capacitors are connected to Vref and Vgnd respectively so as to generate a voltage level corresponding to the digital signal as Vcom. 1. An analog-to-digital converter (ADC) for converting an analog input signal into N-bits of digital output code , the ADC comprising:an M-bit flash ADC configured to receive a sampled analog signal and to output a digital signal comprising most significant M-bits of the N-bits of digital output code in a flash conversion phase, the sampled analog signal being a stored signal of the analog input signal, M and N being integers; and a capacitor digital-to-analog converter (DAC) comprising a first set of capacitors and a second set of capacitors, each of the first set of capacitors and the second set of capacitors being weighted capacitors such that the capacitors of the first set of capacitors all have respectively different capacitance values and the capacitors of the second set of capacitors all have respectively different capacitance values, first ends of each capacitor of the first set of capacitors and the second set of capacitors coupled to a common terminal; and', in the flash conversion phase, generate the most significant M- ...

PATTERN BASED ESTIMATION OF ERRORS IN ADC

The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal. 1. An analog to digital converter (ADC) comprising:a flash ADC configured to generate a flash output in response to an input signal;an error correction block configured to generate a known pattern; anda residual ADC configured to generate a residual code in response to the input signal, the known pattern and an analog PRBS (pseudo random binary sequence) signal.2. The ADC of further comprising:a selector block coupled to the flash ADC and the error correction block, and configured to generate a plurality of selected signals in response to the flash output and the known pattern;a digital to analog converter (DAC) coupled to the selector block, and configured to generate a coarse analog signal in response to the plurality of selected signals; anda residue amplifier coupled to the DAC, and configured to generate a residual analog signal in response to the coarse analog signal, the input signal and the analog PRBS signal, wherein the residual ADC is coupled to the residue amplifier.3. The ADC of further comprising:a secondary multiplexer coupled to the error correction block and configured to generate a digital PRBS signal in response to the known ...

Ultrasonic Flow Meter with Improved ADC Arrangement

Transit-time based ultrasonic flow meter with analog-to-digital conversion for measuring ultrasonic signals, wherein accuracy of measurements is improved by making several measurements with different input offset, reference voltage, frame offset or sample rate in an analog-to-digital conversion stage. 1. A transit-time ultrasonic flow meter comprising at least two ultrasonic transducers , an analog-to-digital converter arrangement for sampling ultrasound measurement signals from the ultrasonic transducers and a processing unit for calculating a transit-time based flow representation from the sampled measurement signals; an analog-to-digital converter comprising an analog input and a sample output; and', 'a first non-linearity robustness provider arranged to provide a first non-linearity robustness provision;, 'wherein the analog-to-digital converter arrangement compriseswherein the analog-to-digital converter arrangement is arranged to receive at least four ultrasound measurement signals from the ultrasonic transducers and provide the ultrasound measurement signals to the analog input;wherein the first non-linearity robustness provider is arranged to provide an individual first non-linearity robustness provision for at least two of said ultrasound measurement signals, each individual first non-linearity robustness provision being different; andwherein the analog-to-digital converter is arranged to establish for each of the at least four ultrasound measurement signals a sampled measurement frame with at least 10 samples on the basis of the respective ultrasound measurement signal and the first non-linearity robustness provision and provide the sampled measurement frame at the sample output coupled to said processing unit; an input level offset provider, respectively an input level offset value provided to the analog input of the analog-to-digital converter,', 'a reference voltage provider, respectively a reference voltage provided to a reference voltage input of the ...

LOW-NOISE LOW-DISTORTION SIGNAL ACQUISITION CIRCUIT AND METHOD WITH REDUCED AREA UTILIZATION

A sample and hold amplifier includes an input node for receiving an input current signal, a non-linear sampling capacitor circuit having an input coupled to the input node, an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal, and a linear capacitor coupled between the negative input and the output of the operational amplifier. The non-linear sampling capacitor includes a non-linear capacitor coupled between an intermediate node and ground, a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal. 118-. (canceled)19. A sample and hold amplifier comprising:an operational amplifier having a negative input, a positive input coupled to ground, and an output;a non-linear capacitor having a first terminal, and a second terminal coupled to the negative input of the operational amplifier;a linear capacitor having a first terminal, and a second terminal coupled to the negative input of the operational amplifier;a first switch coupled between the first terminal of the non-linear capacitor and the output of the operational amplifier;a second switch coupled between the first terminal of the non-linear capacitor and ground;a third switch coupled between an input node and the negative input of the operational amplifier;a fourth switch coupled between a first terminal of the linear capacitor and ground; anda fifth switch coupled between a first terminal of the linear capacitor and the output of the operational amplifier.20. The sample and hold amplifier according to wherein the first switch is configured to switch according to a first phase signal.21. The sample and hold amplifier according to wherein the third and fourth switches ...

APPARATUS AND METHOD FOR CONVERSION BETWEEN ANALOG AND DIGITAL DOMAINS WITH A TIME STAMP

An apparatus and method are disclosed with some embodiments including an analog and time to digital converter (ATDC) including a receiver, the receiver for receiving an analog channel input for conversion to a digital data, the digital data having at least one bit, and a defined absolute reference time stamp, the defined absolute reference time stamp representing an absolute reference time associated with conversion of the analog channel input to the digital data and an analog-to-digital converter, the converter converting the analog channel input to the digital data. 1. A method for converting an analog channel input to a digital data , comprising:receiving the analog channel input for conversion to the digital data, the digital data having at least one bit, and a defined absolute reference time stamp; andconverting the analog channel input to the digital data, wherein the defined absolute reference time stamp represents an absolute reference time associated with the converting the analog channel input to the digital data.2. The method for converting an analog channel input to a digital data of claim 1 , wherein a comparator receives the analog channel input for converting the analog channel input to the digital data.3. The method for converting an analog channel input to a digital data of claim 2 , wherein the comparator produces a comparator output received by a clock input of a positive edge-detecting flip flop and a clock input of a negative edge-detecting flip flop.4. The method for converting an analog channel input to a digital data of claim 3 , wherein a first series of flip-flops receive output from positive edge-detecting flip flop and a second series of flip-flops receive output from the negative edge-detecting flip flop.5. The method for converting an analog channel input to a digital data of claim 4 , wherein the first series of flip-flops includes at least 8 D-type flip flops and the second series of flip-flops includes at least 8 D-type flip flops.6. ...

MULTI-ZONE DATA CONVERTERS

Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone. 1. A multi-zone digital-to-analog converter , comprisinga digital input configured to receive a digital input signal;an analog output configured to output an analog output signal representative of the digital input signal;a first plurality of current sources associated with a first voltage range of the analog output signal;a second plurality of current sources associated with a second voltage range of the analog output signal; anda plurality of switches that selectively couple the first plurality of current sources and the second plurality of current sources to the analog output in order to provide the analog output with the analog output signal representative of the digital input signal;wherein the first plurality of current sources provide the first voltage range with one or more performance characteristics;wherein the second plurality of current sources provide the second voltage range with a corresponding one or more performance characteristics; andwherein the one or more first performance characteristics provided by the first plurality of current sources are higher than the corresponding one or more second performance characteristics provided by the second plurality of current sources.2. The multi-zone digital-to-analog converter of claim 1 , further comprising a decoder configured to selectively close the plurality of switches based on the digital input signal.3. The multi-zone digital-to-analog converter of claim 1 , wherein the first voltage range is below the second voltage range.4. The ...

SWITCHED CAPACITOR CIRCUITS HAVING LEVEL-SHIFTING BUFFER AMPLIFIERS, AND ASSOCIATED METHODS

Switched capacitor circuits and charge transfer methods comprising a sampling phase and a transfer phase. Circuits and methods are implemented via a plurality of switches, a set of at least two capacitors, at least one buffer amplifier, and an operational amplifier. In one example, during the sampling phase at least one input voltage is sampled, and during the transfer phase at least a first reference voltage provided by the at least one buffer amplifier is subtracted from the at least one input voltage using the operational amplifier. The same set of at least two capacitors may be used in both the sampling phase and the transfer phase. 2. The circuit of claim 1 , wherein at least one of respective absolute values and respective polarities of the first input voltage and the second input voltage are different.3. The circuit of claim 1 , wherein the first input voltage and the second input voltage have a substantially same absolute value and a same polarity.4. The circuit of claim 1 , wherein the second input voltage is one of a common mode voltage and ground.5. The circuit of claim 1 , wherein the sum voltage is based on a multiple n of at least the first input voltage claim 1 , and the multiple n is based on a ratio of a first capacitance value Cof the at least one input capacitor and a second capacitance value Cof the integration capacitor.6. The circuit of claim 1 , wherein:the at least one buffer amplifier includes a first buffer amplifier and a second buffer amplifier;the first buffer amplifier provides a first offset voltage on which the first reference voltage is based;the second buffer amplifier provides a second offset voltage on which a second reference voltage is based; andduring the transfer phase, the plurality of switches are configured to couple the at least one input capacitor, the integration capacitor, and one of the first buffer amplifier and the second buffer amplifier to the operational amplifier to subtract a corresponding one of the first ...

AD Converter

An analog to digital converter is provided and includes column processing units that convert analog signal to digital signal. One or more counters count time of analog to digital conversion and one or more comparators compares the voltage of reference signal and analog signal from neuromorphic device. One or more generators generates the reference signal for the comparator. 1. An analog to digital converter which converts analog signal output from a neuromorphic device comprising:a counter counting timing for analog to digital conversion;a comparator which compares the voltage of reference signal with the analog signal output from the neuromorphic device and output the comparison result to the counter;a generator which generates the reference signal for the comparator.2. The analog to digital converter according to claim 1 , wherein the reference signal is generated by using one or more look up tables which one or more control signals for generating the reference signal are inputted into and digital to analog converters.3. The analog to digital converter according to claim 1 , wherein the reference signals are related to inverse activation functions which include at least one of horizontal flipped waveform and vertical flipped functions.4. The analog to digital converter according to claim 1 , wherein the comparator compares the analog signal with a median value of a plurality of signals included in the reference signal claim 1 , and compares the analog signal with one of a plurality of signals included in the reference signal.5. The analog to digital converter according to claim 1 , wherein the comparator comprises a plurality of comparators claim 1 , and the generator comprises a plurality of generators claim 1 , the plurality of generator generate a plurality of reference signals for the plurality of comparators claim 1 , the plurality of reference signals are different from each other.6. The analog to digital converter according to claim 1 , further comprises a ...

REFERENCE VOLTAGE CONTROL CIRCUIT FOR A TWO-STEP FLASH ANALOG-TO-DIGITAL CONVERTER

A circuit, which is usable in a flash analog-to-digital converter, includes a first switch configured to provide a first reference voltage to a first reference node responsive to a first control signal and a second switch configured to provide the first reference voltage to a second reference node responsive to a second control signal. A third switch is coupled to the first switch and is configured to provide a second reference voltage to the first reference node responsive to a clock signal. Further, a fourth switch is coupled to the second switch and configured to provide the second reference voltage to the second reference node responsive to the clock signal. 1. A flash analog-to-digital converter (ADC) , comprising:a zero crossing comparator configured to compare an input analog voltage to a zero reference voltage;a flash converter comprising a plurality of comparators, wherein each of the plurality of comparators receives a comparator reference voltage and wherein each of the plurality of comparators is configured to compare the input analog voltage to each of the plurality of comparators reference voltages respectively; anda reference voltage control circuit configured to:responsive to an output signal from the zero crossing comparator, selectively switch a first reference voltage and a second reference voltage to a first reference node and a second reference node of the flash converter; andswitch the second reference voltage to the first reference node and to the second reference node after receipt by the flash converter of an edge of a clock to cause the flash converter to begin using voltages on the first and second reference nodes and the input analog voltage to generate a flash converter output;wherein the comparator reference voltage for each comparator in the plurality of comparators is generated based on voltages on the first and second reference nodes.2. The flash ADC of claim 1 , wherein the second reference voltage is smaller than the first ...

HYBRID SECOND-ORDER NOISE COUPLING TECHNIQUE FOR CONTINUOUS-TIME DELTA-SIGMA MODULATORS

A delta-sigma modulator. The delta-sigma modulator includes a loop filter (LF) and a digital-to-analog converter (DAC) connected to an input of the LF. The delta-sigma modulator also includes an asynchronous successive-approximation register (ASAR) quantizer (QTZ) connected to the DAC. The delta-sigma modulator also includes a second order noise coupling circuit (NC) connected to the ASAR and the DAC. 1. A delta-sigma modulator comprising:a loop filter (LF);a digital-to-analog converter (DAC) connected to an input of the loop filter;an asynchronous successive-approximation register (ASAR) quantizer (QTZ) connected to the DAC; anda second order noise coupling circuit (NC) connected to the ASAR and the DAC.2. The delta-sigma modulator of claim 1 , wherein the ASAR further comprises:an excess loop delay (ELD) compensator built within the ASAR QTZ connected to the NC.3. The delta-sigma modulator of claim 2 , wherein the ELD comprises a second loop filter at an end of the ASAR claim 2 , the second loop filter configured to buffer and inject a quantization error from the NC back into the second loop filter.4. The delta-sigma modulator of claim 3 , wherein the NC comprises a mixed mode discrete time-continuous time second order noise coupler (DT-CT) connected to the ASAR.5. The delta-sigma modulator of claim 4 , wherein the DT-CT implements a noise transfer function of (1−Z)NTF claim 4 , wherein NTFis a fourth order noise transfer function of the loop filter.6. The delta-sigma modulator of claim 5 , wherein the noise coupling structure is realized by a cascade of a discrete time (DT) part and a continuous time (CT) part.7. The delta-sigma modulator of claim 6 , wherein the DT part is implemented by switching two pairs of reference-attenuation capacitors of the DAC.8. The delta-sigma modulator of claim 7 , wherein the CT part is implemented by routing a residue voltage of the two pairs of the reference attenuation capacitors to a summing node of a last integrator of the ...

ANALOG SYSTEM AND ASSOCIATED METHODS THEREOF

Methods and systems 10 are provided for circuits. One method is for increasing device threshold voltage distribution of a plurality of devices of a circuit. The method includes adjusting a device threshold voltage of the plurality of devices by different amounts; and selecting a subset of the plurality of devices with adjusted device threshold voltage by a device selection module for performing a function associated with the circuit. In one aspect, a system for device threshold voltage adjustment is provided. The system includes a sensor module for sensing one or more of temperature and voltage values of a die having a plurality of devices for a circuit; and a threshold temperature and voltage compensation module for receiving an input value from the sensor module to compensate variation in a device threshold voltage caused by changes of one or more of temperature and voltage of the die. 1. A system for analog to digital conversion , comprising:a plurality of flash compare modules, each flash compare module having an inverter based comparator for outputting a set of unordered output signals based on an analog input signal;one or more device selection modules that receive the unordered output signals and generate ordered signals representing the analog input; andan error correction module receiving the ordered signals from the one or more device selection modules for detecting a plurality of transitions in the ordered signals to generate a digital output, and adjusting the digital output to correct any errors.2. The system of claim 1 , wherein the error correction module examines the ordered signals to detect any error in thermometer encoding of the ordered signals.3. The system of claim 1 , wherein the error correction module includes an AND-OR gate for detecting and correcting an error condition in the ordered signals.4. The system of claim 1 , wherein the use of the error correction module improves manufacturing yield for manufacturing the system.5. The system of ...

TOP PLATE SAMPLING ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING A DYNAMIC COMPARATOR WITH A PREAMPLIFIER AND A CLAMP CIRCUIT

A system includes analog-to-digital converter (ADC) logic, wherein the ADC logic includes a stage with a dynamic comparator circuit. The ADC logic also includes a residue stage. The dynamic comparator circuit includes a preamplifier and a common mode clamp circuit for the preamplifier. 12-. (canceled)3. A system , comprising:a sampling circuit having inputs and outputs; a stage with a dynamic comparator circuit wherein the dynamic comparator circuit comprises:', 'a preamplifier; and', 'a common mode clamp circuit coupled to the preamplifier;, 'an analog-to-digital converter (ADC) logic having inputs and outputs, wherein the inputs of the ADC logic are coupled to the outputs of the sampling circuit, wherein the ADC logic comprisesa residue stage having inputs wherein the inputs of the residue stage are coupled to the outputs of the ADC logic.4. A system , comprising: a stage with a dynamic comparator circuit wherein the dynamic comparator circuit comprises:', 'a preamplifier; and', 'a common mode clamp circuit coupled to the preamplifier;, 'analog-to-digital converter (ADC) logic having outputs, wherein the ADC logic comprisesa residue stage having inputs wherein the inputs of the residue stage are coupled to the outputs of the ADC logic,wherein the dynamic comparator circuit is a differential comparator circuit, and the preamplifier is a differential preamplifier.5. The system of claim 3 , wherein the preamplifier comprises a pair of transistors claim 3 , each transistor having a control terminal claim 3 , a first current terminal claim 3 , and a second current terminal claim 3 , wherein each respective control terminal is coupled to a control signal node claim 3 , wherein each respective first current terminal is coupled to a supply voltage node claim 3 , and wherein each respective second current terminal is coupled to a respective differential output node.6. The system of claim 5 , wherein the pair of transistors comprises a first pair of transistors claim 5 , ...

PROTECTION FOR ANALOG TO DIGITAL CONVERTERS

Systems and methods for protecting an analog-to-digital converter (ADC) are provided. The provided systems and methods utilize comparators in a circuit of a stage of the ADC to compare a reference signal to an input signal and output one or more maximum signals when the input signal exceeds the reference signal. A decoder in the stage of the ADC may output a reset signal to another circuit in the stage of the ADC when a predetermined number of the maximum signals are received. When the other circuit receives the reset signal, the ADC may enter a protection mode to protect the ADC by ensuring that the excessive input signal is not propagated to subsequent stages. 1. A pipeline analog-to-digital converter , comprising: a first circuit receiving the input voltage and producing an output of the digital signal and one or more maximum signal when the input voltage exceeds a reference voltage;', 'a decoder coupled to the first circuit, the decoder configured to output a reset signal when a predetermined number of maximum signals are received; and', 'a second circuit coupled to the decoder and the first circuit, the second circuit receiving the input voltage, the digital signal, and the reset signal when output, and configured to output the residue voltage,, 'at least one stage receiving an input voltage and producing outputs of a residue voltage and a digital signal, the at least one stage comprisingwherein the second circuit is configured to not output the residue voltage when the reset signal is output and received.2. The pipeline analog-to-digital converter of claim 1 , wherein the first circuit comprises a flash analog-to-digital converter circuit.3. The pipeline analog-to-digital converter of claim 2 , wherein the flash analog-to-digital converter circuit comprises:a first sample and hold circuit configured to receive the input voltage; andan analog-to-digital converter circuit configured to receive an output from the first sample and hold circuit and produce the ...

Digitally trimmable integrated resistors including resistive memory elements

Embodiments include a resistor, coupled on a signal path, that includes one or more resistive memory elements, such as one or more magnetic tunnel junctions (MTJs). The resistance of the resistive memory elements may be digitally trimmable to adjust a resistance of the resistor on the signal path. The resistor may be incorporated into an analog or mixed signal circuit to pass an analog signal on the signal path. Other embodiments may be described and claimed.

ANALOG-TO-DIGITAL CONVERTER WITH HYSTERESIS

A circuit includes an analog-to-digital converter (ADC) and a hysteresis circuit. The ADC is configured to generate a series of digital codes. The hysteresis circuit is configured to: (a) determine that a first digital code of the series of digital codes represents a change in a same direction as previous digital codes and store the first digital code in the register; and (b) determine that a second digital code of the series of digital codes represents a change in direction from previous digital codes, determine that the second digital code is less than a hysteresis value different than a preceding digital code, and not store the second digital code in the register. 1. A circuit , comprising:an analog-to-digital converter (ADC) having an ADC output;a direction detection circuit having a direction detection circuit input and a first direction detection circuit output, the first direction detection circuit input coupled to the ADC output;an adder having first and second adder inputs and an adder output, the first adder input coupled to the first direction detection circuit output, and the second adder input coupled to a hysteresis storage element;a first latch having a first latch input and a first latch output, the first latch input coupled to the adder output; anda first comparator having first and second comparator inputs, the first comparator input coupled to the ADC output, and the second comparator input coupled to the first latch output.2. The circuit of claim 1 , further comprising:a multiplexer coupled to the first comparator; anda register coupled to the multiplexer.3. The circuit of claim 1 , wherein the first latch has a first clock input claim 1 , and the circuit further comprises:a positive edge detect circuit having a positive edge detect input and a positive edge detect output;a first logic gate having a first logic gate input and a first logic gate output, the first logic gate input is coupled to the positive edge detect output, and the first logic ...

SIGNAL CONVERSION CIRCUIT AND FINGERPRINT IDENTIFICATION SYSTEM

The present disclosure provides a signal conversion circuit and fingerprint identification system. The signal conversion circuit is configured to generate a first digital signal according to a first analog signal, and includes a comparator and counter. The comparator includes a first input terminal configured to receive the first analog signal, a second input terminal connected to a reference voltage generator and configured to receive a reference voltage, and an output terminal configured to output a second digital signal. The counter is connected to the output terminal, and is configured to generate a first digital signal. The signal conversion circuit according to the present disclosure has the advantages of simple circuit structure, small circuit area, low cost and low power consumption. 1. A signal conversion circuit , comprising: a first input terminal, configured to receive a first analog signal;', 'a second input terminal connected to a reference voltage generator, and configured to receive a reference voltage; and, 'a comparator, comprisingan output terminal, configured to output a second digital signal; anda counter connected to the output terminal, and configured to generate a first digital signal.2. The signal conversion circuit according to claim 1 , wherein when the first analog signal is greater than the reference voltage claim 1 , the second digital signal has a first potential claim 1 , or when the first analog signal is less than the reference voltage claim 1 , the second digital signal has a second potential.3. The signal conversion circuit according to claim 1 , wherein the signal conversion circuit is used in a fingerprint identification system claim 1 , wherein the fingerprint identification system comprises a pixel array circuit claim 1 , and the first input terminal is connected to the pixel array circuit.4. The signal conversion circuit according to claim 3 , wherein the pixel array circuit is configured to receive a contact of a finger ...

A/D CONVERSION DEVICE

A first mode in which to output analog electricity quantities of objects one by one independently to an A/D converter, a second mode in which to output none of the analog electricity quantities of the objects, a third mode in which to output none of the analog electricity quantities of the objects and cause the output to the A/D converter to be resistor, and a fourth mode in which to output to the A/D converter a plurality of the analog electricity quantities of the objects at the same time, are caused to be generated, thus acquiring the A/D conversion values of the objects individually when in the first mode, and detecting an anomaly of the A/D converter itself or a device connected to the A/D converter when in the second mode to the fourth mode. 1. An A/D conversion device ,comprising:an A/D converter which converts analog electricity quantities of objects to be detected to digital quantities; switching circuits which connect a plurality of the analog electricity quantities to the A/D converter; and a control section which controls the switching circuits independently of each other, the A/D conversion device being characterized in thatthe control section causes to be generateda first mode in which to output the analog electricity quantities of the objects one by one independently to the A/D converter, a second mode in which to output none of the analog electricity quantities of the objects, a third mode in which to output none of the analog electricity quantities of the objects and cause the output to the A/D converter to be pulled down by a resistor, and a fourth mode in which to output to the A/D converter a plurality of the analog electricity quantities of the objects at the same time,thus acquiring the A/D conversion values of the objects individually when in the first mode, and detecting an anomaly of the A/D converter itself or a device connected to the A/D converter when in the second mode to the fourth mode.2. The A/D conversion device according to claim 1 ...

OPTICAL ANALOG TO DIGITAL CONVERTER AND METHOD

An optical analog to digital converter including a light source, a driver, an array of single photon avalanche diodes, and control circuitry. The light source emits photons. The driver receives an analog input signal and to drive the light source on the basis of the analog input signal. The array of single photon avalanche diodes detects the photons provided by the light source. The control circuity is coupled to the array of single photon avalanche diodes and activates the array of single photon avalanche diodes for a predetermined time interval such that the array of single photon avalanche diodes detects the photons provided by the light source during the predetermined time interval. The control circuity further determines the number of single photon avalanche diodes of the array of single photon avalanche diodes which detected a photon during the predetermined time interval. 1. An optical analog to digital converter , comprising:a light source configured to emit photons;a driver configured to receive an analog input signal and to drive the light source on the basis of the analog input signal;an array of single photon avalanche diodes configured to detect the photons provided by the light source; and activate the array of single photon avalanche diodes for a predetermined time interval such that the array of single photon avalanche diodes detects the photons provided by the light source during the predetermined time interval; and', 'determine the number of single photon avalanche diodes of the array of single photon avalanche diodes which detected a photon during the predetermined time interval., 'control circuitry coupled to the array of single photon avalanche diodes and configured to'}2. The optical analog to digital converter of claim 1 , wherein the control circuitry is further configured to output a digital signal on the basis of the determined number of single photon avalanche diodes of the array of single photon avalanche diodes which detected a photon ...

DUAL COMPARATOR-BASED ERROR CORRECTION SCHEME FOR ANALOG-TO-DIGITAL CONVERTERS

An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC. 1. A method comprising:sampling a first output voltage of a first comparator and a second output voltage of a second comparator during a same binary algorithmic iteration of an analog-to-digital converter (ADC);identifying a first polarity of the first output voltage and a second polarity of the second output voltage; andif the first polarity is equivalent to the second polarity, inserting at least one redundant capacitor for a next binary algorithmic iteration of the ADC.2. The method of claim 1 , further comprising:if the first polarity is not equivalent to the second polarity, performing the next binary algorithmic iteration of the ADC without the at least one redundant capacitor.3. The method of claim 1 , wherein the ADC comprises a successive approximation register (SAR) ADC.4. The method of claim 1 , wherein at least one of the first and second comparators includes an offset.5. The method of claim 1 , wherein at least one of the first and second comparators is biased.6. The method of claim 1 , wherein:each binary algorithmic iteration of the ADC comprises generating first and second voltages;the first voltage is coupled to a positive terminal of the first comparator and a negative terminal of the second comparator; andthe second input voltage is coupled to a negative terminal of the first comparator and a positive ...

Distributed Gain Stage for High Speed High Resolution Pipeline Analog to Digital Converters

In an embodiment, multiple MDAC stages are coupled in parallel to form an MDAC having the desired gain and capacitor size. Each stage may include capacitors and an OTA that are much smaller than the corresponding capacitors and OTA would be for a large single stage. Interconnect for each stage may be shorter than the single stage case, and thus the parasitic resistance and capacitance may be lower. Power consumption may be reduced, and performance of the amplifier may be increased, due to the reduced parasitic resistance and capacitance. The area occupied by the circuitry may be lower as well. Process variation within a given stage may be lower. The process variation between stages may induce noise in the output, but the parallel connection of the stages may serve to reduce the noise, in some embodiments.

SEMICONDUCTOR DEVICE AND ELECTRONIC CONTROL DEVICE

To suppress detection accuracy of a measurement resistance from decreasing by an on-resistance of a selector switch. The selector switch is provided between a first node coupled to a first voltage through a reference resistance and multiple second nodes coupled to the second voltage through measurement resistances, and selects the second node to be coupled to the first node with the selector switch. A correction circuit generates a voltage obtained by adding the second voltage to a voltage between the second node and the first node as a correction voltage. A double integral ADC finds a first integral time elapsed when a difference voltage of the correction voltage to a voltage of the first node is integrated to the first voltage and a second integral time elapsed when the difference voltage of the first voltage to the voltage of the first node is integrated to the correction voltage. 1. An analog-to-digital conversion circuit configured to output a digital value of an input voltage by comparing the input voltage with a reference voltage , the analog-to-digital conversion circuit comprising:an internal terminal configured to receive the input voltage;a reference terminal configured to receive the reference voltage; andan integrator circuit configured to integrate a voltage difference between the input voltage and the reference voltage,wherein the reference voltage is variable.2. An analog-to-digital conversion circuit according to claim 1 , further comprising a correction circuit configured to supply the reference voltage to the reference terminal based on a voltage difference between the internal terminal and a measurement terminal.3. An analog-to-digital conversion circuit according to claim 2 , further comprising a selector switch coupled with the internal terminal and the measurement terminal.4. An analog-to-digital conversion circuit according to claim 3 ,wherein the measurement terminal is configured to couple with a measurement resistor.5. An electronic device ...

MISMATCH PROFILE

A system can include a signal image correlator receives a discrete frequency domain representation of a signal tone in an interleaved analog-to-digital (IADC) signal and an image of the signal tone in the discrete frequency domain representation of the IADC signal and determines a correlation between the signal tone and the image of the signal tone, a power of the signal tone and a power of the image of the signal tone. The system can also include a frequency domain estimator that determines an instantaneous frequency domain mismatch profile estimate based on the correlation between the signal tone and the image of the signal tone. The system can further include an averaging filter that averages the instantaneous frequency domain mismatch profile estimate over time to provide a frequency domain mismatch profile estimate. 1. A system comprising:a signal image correlator receives a discrete frequency domain representation of a signal tone in an interleaved analog-to-digital (IADC) signal and an image of the signal tone in the discrete frequency domain representation of the IADC signal and determines a correlation between the signal tone and the image of the signal tone, a power of the signal tone and a power of the image of the signal tone;a frequency domain estimator determines an instantaneous frequency domain mismatch profile estimate based on the correlation between the signal tone and the image of the signal tone;an averaging filter averages the instantaneous frequency domain mismatch profile estimate over time to provide a frequency domain mismatch profile estimate; anda time domain converter converts the frequency domain mismatch profile estimate into the time domain.2. The system of claim 1 , further comprising:an interleaved analog-to-digital converter (ADC) comprising component ADCs, the interleaved ADC outputs the IADC signal, wherein the IADC signal comprises spurious signals generated from mismatches in the component ADCs.3. The system of claim 1 , ...

VARIABLE RESOLUTION DIGITAL EQUALIZATION

A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing. 1. (canceled)2. An integrated circuit , comprising:an interface to be coupled to receive a signal that is conveyed via a signal channel, the signal channel to attenuate the signal by an attenuation amount as the signal is conveyed by the signal channel;an adjustable resolution analog-to-digital converter (ADC) to receive the signal via the interface; and,digital control circuitry to receive a digital indicator of the attenuation amount and to, based at least in part on the digital indicator, determine a resolution of the ADC.3. The integrated circuit of claim 2 , wherein the ADC corresponds to a successive approximation type ADC.4. The integrated circuit of claim 3 , wherein the digital control circuitry determines the resolution of the ADC by controlling the number of successive approximation iterations the ADC uses to convert the received signal to a digital number.5. The integrated circuit of claim 2 , wherein the digital control circuitry determines the resolution of the ADC by adjusting the number of comparisons the ADC uses to convert the ...

BIOLOGICAL ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS

Described herein are novel biological converter switches that utilize modular components, such as genetic toggle switches and single invertase memory modules (SIMMs), for converting analog inputs to digital outputs, and digital inputs to analog outputs, in cells and cellular systems. Flexibility in these biological converter switches is provided by combining individual modular components, i.e., SIMMs and genetic toggle switches, together. These biological converter switches can be combined in a variety of network topologies to create circuits that act, for example, as switchboards, and regulate the production of an output product(s) based on the combination and nature of input signals received. 1. A digital-to-analog biological converter switch , the digital-to-analog biological converter switch comprising at least two single invertase memory modules (SIMM) , wherein each SIMM comprises at least one module comprising an inducible promoter sequence (iP) , a forward recombinase recognition site sequence (RRS) , an inverted promoter sequence (P) , a recombinase gene sequence (RC) , a reverse recombinase recognition site sequence (RRS) , an inverted second inducible promoter sequence (iP) , and an output product sequence (OP) , (iP-RRS-P-RC-RRS-iP-OP); wherein the recombinase gene sequence of each SIMM encodes a recombinase that recognizes the RRSand RRSof that SIMM; and wherein n≧2.2. The digital-to-analog biological converter switch of claim 1 , wherein the inverted promoter sequence (P) of each SIMM has a different promoter strength.3. The digital-to-analog biological converter switch of claim 1 , wherein the recombinases encoded by each SIMM is different.4. The digital-to-analog biological converter switch of claim 1 , wherein the inverted second inducible promoter sequence of each SIMM is induced by the same inducing agent.5. The digital-to-analog biological converter switch of claim 1 , wherein the output product is a reporter protein claim 1 , a transcriptional ...

AD CONVERTER AND RECEIVING APPARATUS

It is intended to provide an AD converter capable of increasing its conversion accuracy. An AD converter is equipped with a clock generator which generates a first clock using a second clock and a comparator which includes a comparison circuit for comparing an input signal with a prescribed value in a first period of the first clock and a precharging circuit for precharging, in a second period of the first clock, an internal voltage to a prescribed value for the next comparison operation. The clock generator includes a replica circuit of the precharging circuit of the comparator. In the replica circuit of the precharging circuit, a precharging period from the start to the end of precharging is set as the second period of the first clock. 1. An AD converter comprising:a clock generator that generates a first clock using a second clock; and a comparison circuit that compares an input signal with a prescribed value in a first period of the first clock; and', 'a precharging circuit that precharges, in a second period of the first clock, an internal voltage to a prescribed value for a next comparison operation,, 'a comparator comprisingwherein the clock generator comprises a replica circuit of the precharging circuit of the comparator, and in the replica circuit of the precharging circuit a precharging period from the start to the end of precharging is set as the second period of the first clock.2. The AD converter according to claim 1 , wherein the clock generator generates the first clock on the basis of a delay time in an internal block of the replica circuit of the precharging circuit.3. The AD converter according to claim 1 , wherein the comparator comprises plural stages of internal blocks and a latch circuit; an input transistor which is included in a first-stage internal block of the plural stages of internal blocks and receives the input signal; and', 'a second-stage internal block which is one of the plural stages of internal blocks, is connected to the latch ...

Electric signal conversion

In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.

POLAR ANALOG-TO-DIGITAL CONVERTER AND DOWN CONVERTER FOR BANDPASS SIGNALS

Methods and systems for generating a digital representation of the amplitude and phase of a bandpass signal are disclosed. The methods comprise filtering the bandpass signal with a bandpass filter, generating the real and imaginary parts of the complex analytic signal with a quadrature hybrid, determining the amplitude of the complex analytic signal by adding an even power-law transform of the real and imaginary parts of the complex analytic signal, and determining the phase of the complex analytic signal by comparing the real and imaginary parts of the complex analytic signal to zero and comparing an even power-law transform of the real and imaginary parts of the complex analytic signal to each other. Analog to digital converters and methods of converting complex analytic signals to digital signals are also disclosed. 1. A method of determining an amplitude and phase of a bandpass signal , comprising the steps of:generating real and imaginary parts of an analytic representation of said bandpass signal through a quadrature hybrid, wherein the real and imaginary parts of an analytic representation of said bandpass signal is an analytic signal;determining an amplitude of the analytic signal by adding an even power-law transform of the real and imaginary parts of the analytic signal; anddetermining a phase of the analytic signal by comparing the real and imaginary parts of the analytic signal to zero and comparing the even power-law transform of an absolute value of the real and imaginary parts of the analytic signal to each other.2. The method of claim 1 , wherein an amplitude generator circuit extracts the signal amplitude or a power-law thereof.3. The method of claim 2 , wherein the amplitude generator is comprised of a lowpass filter to attenuate generated harmonics and a power-law inverter.4. The method of claim 3 , further comprising converting the amplitude of the analytic signal into binary signals with a linear quantizer.5. The method of claim 2 , wherein the ...

TEMPERATURE MEASUREMENT DEVICE, INTEGRATED CIRCUIT, AND TEMPERATURE MEASUREMENT METHOD

In a first sensing state in which a first current flows in a forward direction with respect to a pn junction of a first semiconductor element and a second current of a different magnitude from the first current flows in a forward direction with respect to a pn junction of a second semiconductor element, a difference between a forward direction voltage of the pn junction of the first semiconductor element and a forward direction voltage of the pn junction of the second semiconductor element is converted into a digital value by a computer and acquired as a first digital value. In a second sensing state in which the second current flows in the forward direction in the pn junction of the first semiconductor element and the first current flows in the forward direction in the pn junction of the second semiconductor element, a difference between the forward direction voltage of the pn junction of the first semiconductor element and the forward direction voltage of the pn junction of the second semiconductor element is converted into a digital value by the computer and acquired as a second digital value. A temperature measurement value is computed based on an average value of the first digital value and the second digital value by the computer. 1. A temperature measurement device comprising:a first semiconductor element and a second semiconductor element that include respective pn junctions;a first current output circuit configured to output a first current and a second current of a different magnitude from the first current in accordance with a control voltage supplied to a current control terminal;a first connection switching circuit configured to switch connections of the first semiconductor element and the second semiconductor element with the first current output circuit so as to give either state of a first sensing state in which the first current flows in a forward direction with respect to the pn junction of the first semiconductor element and the second current ...

Analog-to-digital conversion

An analog-to-digital conversion apparatus 10 comprises a plurality of analog-to-digital converters 30 and a ramp generator 20 . Each of the analog-to-digital converters 30 comprises an analog signal input for receiving an analog signal level and a ramp signal input. A control stage is arranged to compare the ramp signal with the analog signal level and, based on the comparison, to enable a counter provided at the analog-to-digital converter or to latch a digital value received from a counter. The control stage comprises a comparator in the form of a first differential amplifier with a first branch connected to the input for receiving the ramp signal, a second branch connected to the analog signal input and an output, and a biasing current source for biasing the first differential amplifier. A feedback circuit controls the biasing current source. The feedback circuit comprises a second differential amplifier OP 1 with a first input connected to a node 46 on the first branch and a second input connected to a reference voltage VB such that the node on the first branch is maintained at a substantially constant voltage.

SYSTEM AND METHOD FOR RIPPLE-FREE AC POWER DETERMINATION

A power metering circuit includes a current input path for receiving an analog current input at a first analog to digital converter; a voltage input path for receiving an analog voltage input at a second analog to digital converter; a multiplier configured to multiply an output of the current input path and the voltage input path; a notch filter configured to receive an output of the multiplier, the notch filter having a stop band based on a line frequency; and a control circuit for setting a sampling frequency of the first analog to digital converter and the second analog to digital converter to a multiple of the line frequency. 1. A power metering circuit , comprising:a current input path for receiving an analog current input at a first analog to digital converter;a voltage input path for receiving an analog voltage input at a second analog to digital converter;a multiplier configured to multiply an output of the current input path and the voltage input path;a notch filter configured to receive an output of the multiplier, the notch filter having a stop band based on a line frequency; anda control circuit for setting a sampling frequency of the first analog to digital converter and the second analog to digital converter to a multiple of the line frequency.2. A power metering circuit in accordance with claim 1 , wherein the control circuit includes a phase locked loop configured to receive one of the analog current input and the analog voltage input.3. A power metering circuit in accordance with claim 1 , wherein the control circuit comprises a frequency detector and a programmable oscillator configured to receive an output of the frequency detector.4. A power metering circuit in accordance with claim 1 , the current input path and the voltage input path each including a highpass filter.5. A power metering circuit in accordance with claim 4 , wherein the voltage input path includes a selectable phase shifter.6. A power metering circuit in accordance with claim 1 , ...

ANALOG TO DIGITAL CONVERTER

An A/D converter includes multiple bin comparators that compare an analog voltage to corresponding bin threshold voltages to provide output signals for providing corresponding comparison results. Some of the comparators includes enable inputs that selectively enable the output signal of the bin comparator to provide the corresponding comparison result based on a corresponding comparison result from at least one other bin comparator. The A/D convertor includes an encoder that utilizes the output signals to provide encoded bit values of the digital output. The A/D converter includes a bin selection circuit that utilizes the output signals to select a voltage level based on the output signals and provides the selected voltage level to a next stage of the A/D convertor. The next stage uses the selected voltage level and the analog voltage to provide at least one lessor bit of the digital output. 1. An analog-to-digital converter (A/DC) configured to receive an analog voltage and provide a digital output which corresponds to a digital representation of the analog voltage , the A/DC comprising: 'an enable input configured to selectively enable the output signal of the bin comparator to provide the corresponding comparison result based on a corresponding comparison result from at least one other bin comparator of the N bin comparators;', 'N bin comparators, wherein N is an integer greater than one, wherein each bin comparator of the N bin comparators is coupled to receive the analog voltage and a corresponding bin threshold voltage and configured to provide an output signal for providing a corresponding comparison result between the analog voltage and the corresponding bin threshold voltage such that the N bin comparators provide N output signals, and wherein each bin comparator of N−1 bin comparators of the N bin comparators includesan encoder circuit coupled to receive the N output signals from the N bin comparators and configured to encode the N output signals to form ...