DIGITAL-ANALOG-WANDLER.

CONVERTISSEUR NUMERIQUE-ANALOGIQUE PERFECTIONNE

Convertisseur numérique-analogique destiné à convertir en signaux analogiques des signaux numériques constitués de bits de signe, de bits de pas et de bits de segment, notamment de signaux codés par compression de données conformément à la loi A, ledit convertisseur comprenant un générateur de signe 4, destiné à recevoir le bit de signe dudit signal numérique, un générateur de pas 7, connecté à la sortie du générateur de signe et destiné à recevoir les bits de pas dudit signal numérique et un générateur de segments 8 connecté au générateur de pas et destiné à recevoir les bits de segment dudit signal de référence, caractérisé en ce que le générateur de segments 8 est connecté au générateur de signe 4 uniquement par l'intermédiaire du générateur de pas 7. (CF DESSIN DANS BOPI) ...

METHOD AND APPARATUS FOR USE IN SWITCHED CAPACITOR SYSTEMS

Systems and methods receive a digital signal and generate an analog signal indicative thereof. In one embodiment, a system includes a DAC that receives a multi-bit digital signal, generates at least two analog signals each indicative of the multi-bit digital signal, and filters two or more of the at least two analog signals. In another embodiment, a system includes a DAC that receives digital input signals at an input data rate and outputs analog signals indicative of the digital signals to a signal conditioning stage at an output data rate different than the input data rate.

Compact R segment D/A converter

A digital-to-analog converter includes a group of resistors serially connected between a power source potential supply terminal and a reference potential supply terminal. First group switches are connected between a first circuit point and given serial connection nodes of the resistor group, and between the first circuit point and the reference potential supply terminal. Each of these switches is controlled so as to be selectively turned on according to the result obtained from decoding upper bits of a digital signal. Further, second group switches are connected between a second circuit point and other serial connection nodes of the resistor group, and between the second circuit point and the reference potential supply terminal. Each of these switches is controlled so as to be selectively turned on according to the result obtained from decoding lower bits of the digital signal. First and second capacitors are connected between an output terminal and the first circuit points, and between ...

Digital to analog converter for sigma delta modulator

A second order sigma delta modulator (10) includes a digital to analog converter (26) that provides feedback for system modulation. The digital to analog converter (26) employs a dynamic element matching circuit (72) which randomly selects among main capacitors (Cj) to reduce the effect of capacitor value mismatching. The digital to analog converter (26) also employs a self calibration circuit (80) to trim the values of the main capacitors (Cj) to obtain better capacitor matching. During self calibration, a clock signal (frand) driving a pseudo random number generator (74) of the dynamic element matching circuit (72) is reduced to assist in minimizing variance in a digital output signal for accurate calibration of the main capacitors (Cj). Upon completion of calibration, the clock signal (frand) is returned to a frequency coinciding with the modulator clock rate.

Digital-to-analog converter with binary coded inputs to produce a plurality of outputs in the form of thermometer code

Binary bits of least binary significance are converted to a corresponding analog output. Binary bits of increased binary significance are converted to a first plurality of thermometer outputs. A plurality of switching assemblies, each preferably recursive and preferably formed from a plurality of switches (e.g. transistors), process individual pairs of successive ones of such thermometer outputs. Each stage respectively produces first or second outputs or the analog output for first, second and third relationships between the thermometer outputs in such pair. The analog output has a variable value between the first and second outputs depending upon the value of the least significant binary bits. When the binary value is represented only by the binary bits of least and increased binary significance, the first, second and analog outputs are combined to produce an analog output representative of such binary bits. When the binary value additionally includes binary bits of even greater binary significance, an additional decoder decodes such binary bits to produce a second plurality of thermometer outputs. Second pluralities of switching assemblies, each plurality preferably having a construction corresponding to that of the first plurality, receive individual pairs of the thermometer outputs in the second plurality and produce the first or second outputs or an individual one of the outputs in the first plurality. These thermometer outputs are combined to produce an analog output representative of all of the binary bits. The second pluralities of switching assemblies comprise a number corresponding to the number of thermometer outputs in the second plurality.

Device and method for low non-linearity analog-to-digital converter

An apparatus and method for converting an analog signal to a digital signal. The apparatus includes a plurality of capacitors. The plurality of capacitors includes at least a first capacitor, a second capacitor and a third capacitor. The first capacitor is associated with a first capacitance, a second capacitor is associated with a second capacitance, and a third capacitor is associated with a third capacitance. The first capacitance is substantially equal to the second capacitance, and the second capacitance is substantially equal to the third capacitance. Additionally, the apparatus includes a plurality of resistors. The plurality of resistors includes at least a first resistor and a second resistor. Moreover, the apparatus includes an operational amplifier.

Digital/analog converter

Digital/analog converter for converting a binary coded data word into an analog output signal, having a capacitor cell Iratrix (9) comprising capacitor cells (13ij) which are arranged in matrix form in columns and rows and are driven by thermometer-coded control signals via control lines; a first coding device (6) for recoding the n more significant data bits of the data word D to be converted into a thermometer-coded column control signal which has a width of 2n bits and is applied to the capacitor cell matrix (9) via column control lines (8), a second coding device (11) for recoding the m less significant data bits of the data word D to be converted' into a thermometer-coded row control signal which has a width of 2 bits and is applied to the capacitor cell matrix (9) via row control lines (12), each capacitor cell (13ij) of the capacitor cell matrix (9) in each cast having an associated local decoding circuit (1911) which drives switches (34, 35, 36, 37) in a manner dependent on the ...

VARIABLE CONDENSER

CAPACITIVE DIGITAL TO ANALOG AND ANALOG TO DIGITAL CONVERTERS

A digital-to-analog converter (DAC) comprises a capacitive DAC that comprises N first capacitances that are connected in parallel and that have first ends and second ends, wherein N is an integer greater than one, and N first switches that selectively connect a selected one of the second ends of the N first capacitances to a common node and non-selected ones of the second ends of the N first capacitances to one of a voltage potential and a reference potential. Capacitance values of the N first capacitances are substantially equal. A second DAC communicates with the common node.

Digital/analog converting apparatus and digital/analog converter thereof

A digital/analog converting apparatus and digital/analog converter are provided. The digital/analog converter includes an operational amplifier, a first filter, a first switch, a second filter, a number of conversion units and a second switch. The operational amplifier has an output terminal, an inverse-phase input terminal and a non-inverse-phase input terminal coupled to a reference voltage. The first filter is coupled between the output terminal and the inverse-phase input terminal. The second filter is coupled between the output terminal via the first switch and the inverse-phase input terminal. Each of the conversion units includes a capacitor. The second switch is coupled between the inverse-phase input terminal and the conversion units, and the conversion units are connected in parallel between the second switch and the output terminal.

PIPELINED A/D CONVERTER

PROBLEM TO BE SOLVED: To provide a pipelined A/D converter capable of achieving low power consumption while preventing a reduction in feedback factor of an amplifier. SOLUTION: The pipelined A/D converter converts an analog signal to a digital signal, including a plurality of stages connected in cascade connection and an error correction circuit which generates the digital signal, based on sub digital signals respectively outputted from the stages. When a sub digital signal of N bits is outputted in at least one of the stages in the pipelined A/D converter, the stage gain of a transfer function is 2N-K-1, the number of returns is 2N-2 and an integer K satisfies a relation of 1≤K≤N. COPYRIGHT: (C)2010,JPO&INPIT ...

Bipolarer elementenmittelnder Digital-Analog-Wandler

Gerät zur Umwandlung digitaler Werte in analoge Werte.

IMPROVED DIGITAL-ANALOG CONVERTER

Digital to Analog Converter and method thereof

평판 표시 장치의 소스드라이버의 디지털/아날로그 변환장치 및 그 방법이 개시된다. 디지털/아날로그 변환 장치는 아날로그 계조전압 생성부, 디코더부 및 보간 전압 생성부를 포함한다. 디코더부는 제1 디코더와 제2 디코더를 포함한다. 보간전압 생성부는 샘플-홀드 스킴을 이용하여 보간전압을 생성한다. Disclosed are a digital / analog converter for a source driver of a flat panel display device and a method thereof. The digital / analog converter includes an analog gray voltage generator, a decoder, and an interpolation voltage generator. The decoder unit includes a first decoder and a second decoder. The interpolation voltage generator generates an interpolation voltage using a sample-hold scheme.

Digital to analog converter for sigma delta modulator

A second order sigma delta modulator (10) includes a digital to analog converter (26) that provides feedback for system modulation. The digital to analog converter (26) employs a dynamic element matching circuit (72) which randomly selects among main capacitors (Cj) to reduce the effect of capacitor value mismatching. The digital to analog converter (26) also employs a self calibration circuit (80) to trim the values of the main capacitors (Cj) to obtain better capacitor matching. During self calibration, a clock signal (frand) driving a pseudo random number generator (74) of the dynamic element matching circuit (72) is reduced to assist in minimizing variance in a digital output signal for accurate calibration of the main capacitors (Cj). Upon completion of calibration, the clock signal (frand) is returned to a frequency coinciding with the modulator clock rate.

Multiplying digital-to-analog converters and methods that selectively connect unit and feedback capacitors to reference voltages and feedback voltages

Multiplying Digital-to-Analog Converters (MDAC) multiply an analog input signal at an analog input terminal and a digital input signal at a digital input terminal to produce an analog output signal at an output terminal. The MDACs include unit capacitors and a feedback capacitor. The unit capacitors are connected to the analog input terminal during a first time interval and the unit capacitors are selectively connected to a first reference voltage, a second reference voltage or the output terminal during a second time interval in response to the digital input signal at the digital input terminal. The feedback capacitor is connected to the second reference voltage during the first time interval and to the output terminal during the second time interval.

Tri-level dynamic element matcher allowing reduced reference loading and DAC element reduction

ANALOGUE-DIGITAL CONVERTER AND USE PROCEDURE FOR IT

APPARATUS FOR CONVERTING BETWEEN DIGITAL AND ANALOG VALUES

METHOD AND APPARATUS FOR USE IN SWITCHED CAPACITOR SYSTEMS

Systems and methods receive a digital signal and generate an analog signal indicative thereof. In one embodiment, a system includes a DAC that receives a multi-bit digital signal, generates at least two analog signals each indicative of the multi-bit digital signal, and filters two or more of the at least two analog signals. In another embodiment, a system includes a DAC that receives digital input signals at an input data rate and outputs analog signals indicative of the digital signals to a signal conditioning stage at an output data rate different than the input data rate.

D-A CONVERSION CIRCUIT AND ΔΣ AD MODULATOR EMPLOYING IT

PROBLEM TO BE SOLVED: To provide a D-A converter of a simple arrangement in which nonlinearity can be noise-shaped. SOLUTION: The D-A conversion circuit comprises switches S0-S4 performing the charge, discharge, grounding and polarity reversal of each capacitor in a segment switched capacitor type D-A converter 20, and a controller 10 for controlling the switches S0-S4 to perform the secondary noise shaping of the nonlinearity of the D-A conversion circuit for a low-pass ΔΣ AD modulator by using "+2" operation for obtaining an output voltage equal to +2 times of a reference output voltage by performing charge and discharge twice for each capacitor in a clock period, "+1" operation for obtaining an output voltage equal to 1 time of the reference output voltage by performing charge and discharge once for each capacitor in a clock period, "0" operation for obtaining an output voltage of ground potential without performing charge and discharge, and "-1" operation for obtaining an output voltage ...

Ladungsumverteilungs-Digital-Analog-Wandler

Ladungsumverteilungs-Digital-Analog-Wandler (DAC), aufweisend:einen chipinternen Reservoirkondensator, der eine erste Platte und eine zweite Platte aufweist;ein Array von DAC-Kondensatoren, die jeweils eine erste und eine zweite Platte aufweisen; undein Array von Schaltern, gesteuert von einem DAC-Eingangswort, zum Verbinden einer zweiten Platte eines jeweiligen DAC-Kondensators mit der ersten oder der zweiten Platte des chipinternen Reservoirkondensators;einen ersten Schalter, der die erste Platte des chipinternen Reservoirkondensators mit einem externen Anschluss für eine erste externe Referenzspannung verbindet; undeinen zweiten Schalter, der die zweite Platte des chipinternen Reservoirkondensators mit einer zweiten Externer-Anschluss-Referenzspannung verbindet. A charge redistribution digital-to-analog converter (DAC), comprising: an on-chip reservoir capacitor having a first plate and a second plate; an array of DAC capacitors each having a first and a second plate; and an array of switches, controlled by a DAC input word, for connecting a second plate of a respective DAC capacitor to the first or second plate of the on-chip reservoir capacitor; a first switch connecting the first plate of the on-chip reservoir capacitor to an external terminal for one connects first external reference voltage; and a second switch that connects the second plate of the on-chip reservoir capacitor to a second external terminal reference voltage.

Device and method for low non linearity A-D converter

A device for converting analog signal to digital signal and method thereof, which contains plurality of capacitors having at least one first capacitor related with first capacitance, one second capacitor related with second capacitance and a third capacitor related with third capacitance, wherein the first, second and third capacitance are basically equal to each other, said device also contains plurality of resistors consisting of at least first resistor, second resistor and a operation amplifier.

TWO-STAGE DAC ACHITECTURE FOR LCD SOURCE DRIVER UTILIZING ONE-BIT PIPE DAC

A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Capacitive digital to analog and analog to digital converters

A digital to analog converter (DAC) comprises X capacitive DACs that are connected together in series, wherein X is an integer greater than one. Each of the X capacitive DACs comprise M switches wherein M is an integer greater than one; a signal input; a signal output; and M capacitances that communicate with the M switches, respectively, and that have first and second ends and substantially equal capacitance values. The M switches selectively connect the first ends of the M capacitances to the signal output. The M switches connect the second end of a selected one of the M capacitances to the signal input. A first DAC has a signal output that communicates with the signal input of one of the X capacitive DACs.

A ramp generator for an analogue to digital converter

A ramp generator for an analog-to-digital converter comprises an array of capacitors each controlled by a switch responsive to one or more control signals and operable to connect/disconnect one or more of the capacitors relative to the array and a current source operable to charge at least one of the capacitors. Operating the ramp generator comprises resetting the ramp generator, enabling a current generator to charge at least one capacitor in the switched capacitor array, and controlling the state of one or more switches, wherein the switches are operable to connect and disconnect one or more of the capacitors relative to the array. The output of the ramp generator having a plurality of programmable breakpoints. The analogue to digital converter may also comprise means to produce a falling ramp signal and a rising ramp signal.

CHARGE REDISTRIBUTION DIGITAL-TO-ANALOG CONVERTER

Embodiments of the present disclosure may provide a charge redistribution DAC with an on-chip reservoir capacitor to provide charges to the DAC in lieu of traditional external reference voltages. The DAC may include the on-chip reservoir capacitor having a first plate and a second plate, an array of DAC capacitors to generate a DAC output, and an array of switches controlled by a DAC input word to couple the DAC capacitors to the reservoir capacitor. The charge redistribution DAC may further comprise a first switch connecting the first plate to an external terminal for a first external reference voltage, and a second switch connecting the second plate to an external terminal for a second external reference voltage. One embodiment may provide an ADC that includes the charge redistribution DAC.

Capacitive digital to analog and analog to digital converters

A digital to analog converter (DAC) comprises X capacitive DACs that are connected together in series, wherein X is an integer greater than one. Each of the X capacitive DACs comprise M switches wherein M is an integer greater than one; a signal input; a signal output; and M capacitances that communicate with the M switches, respectively, and that have first and second ends and substantially equal capacitance values. The M switches selectively connect the first ends of the M capacitances to the signal output. The M switches connect the second end of a selected one of the M capacitances to the signal input. A first DAC has a signal output that communicates with the signal input of one of the X capacitive DACs.

VARIABLER KONDENSATOR

VERFAHREN UND GERÄT ZUR ANWENDUNG IN SYSTEMEN MIT GESCHALTETEN KAPAZITÄTEN

KONDENSATORARRAY-D/A-WANDLER MIT EINEM TEMPERATURMESSGERÄT-DECODER SOWIE KONDENSATORRAY

Improved digital/analog converter

Digital to analog converter cell for signed operation

一種通訊系統，接收輸入信號及產生轉換的輸出信號。控制信號選擇性地啟動胞元陣列中的一或多個來源胞元。選擇的來源胞元在用於胞元陣列的胞元輸出端產生第一電荷封包及第二電荷封包以產生轉換的輸出信號。第一電荷封包及第二電荷封包係在相同時脈週期期間產生。

Hybrid digital-to-analog converter and method thereof

Hybrid digital-to-analog converter and method thereof are provided. The hybrid digital-to-analog converter (DAC) includes a data processor, at least one first type DAC, at least one second type DAC, and an output circuit. The data processor processes an input digital signal to output at least one of first and second digital signals which are related to a higher bit portion and a lower bit portion of the input digital signal, respectively. If the data processor outputs the first digital signal to the first type DAC, the first type DAC converts the first digital signal. The at least one second type DAC receives and converts the second digital signal outputted from the data processor. The output circuit receives at least one output signal of the first and the second type DACs to output an output analog signal.

DAC ARCHITECTURE FOR LCD SOURCE DRIVER

A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a two-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Highspeed, high spurious-free dynamic range pipelined analog to digital converter

A method for shuffling capacitors, for application in a stage of a pipelined analog-to-digital converter that samples an input voltage at each of a sequence of sample times and provides a sequence of digital outputs representing the magnitude of the sampled input voltage. The stage includes an amplifier and a plurality of capacitors which may be connected between the input voltage and an AC ground at a first time and which may be connected between the output of the amplifier and an input of the amplifier, or which may be connected between the input of the amplifier and one of a plurality of reference voltage sources at a second time. The method includes the following steps. A plurality of coded input values are provided, each such coded value corresponding to the connection of one of the capacitors between the input of the amplifier and either the at least one voltage sources or the output of the amplifier. A predetermined sequence of control codes is provided. The coded input values are ...

VARIABLER KONDENSATOR

CONVERTING A/D NONLINEARITIES TO RANDOM NOISE

For removing the effects of mismatched components in an A/D converter the capacitors of the A/D converter are dynamically rearranged so that physical mismatch is averaged out. An array of equally-sized capacitors C1-C8 is coupled to a switching network. A successive approximation scheme is implemented in which the input signal is coupled through SAR switches to the capacitor array. Each switch is coupled to 2 capacitors where N is the switch number. For example, in an 8-bit scheme, there are 3 switches with switch 1 coupled to one capacitor, switch 2 coupled to two capacitors, and switch 3 coupled to four capacitors. A scramble control code controls the switching array so that the capacitors are coupled to different SAR switches at different times. In this manner, the effects of any variations in the capacitance ratios is averaged out and converted to noise which can be filtered out of the signal. …… ...

Programmable integrating ramp generator and method of operating the same

Digital-to-analog converter with high-speed output

FAST HIGH-RESOLUTION ANALOG-TO-DIGITAL CONVERTER

D-1866 A FAST HIGH-RESOLUTION ANALOG-TO-DIGITAL CONVERTER An unknown analog signal is compared in amplitude with the signal from a digital-to-analog (D-A) converter. The converter, preferably monotonic, may be at least partially formed from a plurality of switches connected in a recursive array to define recursive sub-sets. An adjustable-gain amplifier produces a difference signal having an amplitude indicating the amplitude comparison. A flash converter converts the difference signal to binary signals. These binary signals are modified and fed back to the D-A converter to obtain from this converter an output signal having an amplitude approximating the amplitude of the unknown analog signal. A plurality of successive approximations of the analog signal may be provided in this manner. In at least one (1) of these approximations, the gain of the amplifier may be increased to increase the sensitivity of the approximation by increasing the gain of the difference signal. In such approximation ...

Capacitive digiital to analog and analog to digital converters and method for generating a residue voltage in the converters

Circuit, system and method for performing dynamic element matching using bi-directional rotation within a data converter

A circuit, system, and method are provided for imparting improved randomness into the selection of components or elements of a data converter, such as a D/A converter. The elements are intended to be of equal value, however, regardless of whether they are or not. A circuit is used to randomly select subsets of elements according to a bi-directional selection technique in order to effectively rending the elements or components of equal value. Associated with each component is a switch, and a subset of the plurality of components are correspondingly switched in successive order progressing in a first direction and, subsequently, in successive order progressing in a second direction opposite the first direction. Connecting components in a first direction from left-to-right follows by selecting components in a second direction from right-to-left, and then again selecting components in the first direction from left-to-right, and so forth. A pointer will note the starting element of odd values ...

Semiconductor integrated circuit

One input terminals of switches respectively coupled to capacitors of a capacitance array type D/A converter configured as a main DAC are coupled to a first external terminal of an IC. On the other hand, a current switching type D/A converter of a resistance string type D/A converter configured as a sub DAC that causes a DC current to flow therethrough is coupled to a second external terminal of the IC.

METHOD AND APPARATUS FOR USE IN SWITCHED CAPACITOR SYSTEMS

Systems, methods, apparatus, and handset employing digital to analog conversion, analog to digital conversion and/or switched capacitor techniques.

A CAPACITOR ARRAY ARRANGMENT FOR IMPROVING CAPACITOR ARRAY MATCHING

A capacitor array layout technique for improving capacitor array matching. A capacitor array is laid out in a geometrical configuration wherein the geometrical configuration has a centerpoint. The geometrical configuration is divided into a plurality of first sections wherein each of the plurality of first sections have a corresponding second section diagonally located from and at an approximately equal distance from the centerpoint as said first section. Each of the second sections house a capacitor set of a predetermined value wherein each of the plurality of first sections house a capacitor set of an equal value as the corresponding second section.

Digital/Analog-Wandler

Programmable integrating ramp generator and method of operating the same

Variable capacitor

PCT No. PCT/GB97/01100 Sec. 371 Date Oct. 9, 1998 Sec. 102(e) Date Oct. 9, 1998 PCT Filed Apr. 22, 1997 PCT Pub. No. WO97/40506 PCT Pub. Date Oct. 30, 1997A variable capacitor includes a first electrode (2), a second electrode (3) and, located between the first and second electrodes, an array of gas discharge tubes (7). The capacitor includes means for producing an electrical discharge in the tubes, thereby affecting the capacitance of the capacitor.

APPARATUS FOR CONVERTING BETWEEN DIGITAL AND ANALOG VALUES

APPARATUS FOR CONVERTING BETWEEN DIGITAL AND ANALOG VALUES A first matrix relationship is defined by a plurality of switches operative in first and second states in accordance with the logic levels of binary signals introduced to the switches. The switches in the matrix relationship receive binary signals of relatively high binary significance. An activating line is connected to the matrix relationship to activate storage members, such as capacitors, connected to the matrix relationship. The number of storage members energized by the activating line at each instant is related to the value coded by the logic levels of the binary signals introduced to the matrix relationship. For increasing binary values, the storage members previously energized in the plurality by the activating line continue to be energized and additional storage members in the plurality are energized. An interpolating line is also provided in the first matrix relationship. The interpolating line receives a voltage related ...

MULTI-BIT DAC WITH DYNAMIC ELEMENT MATCHING

A sigma-Delta converter, comprising means for receiving an input digital signal; a digital loop filter and quantizer having an input and an output; a summer having a first input connected to the means for receiving, a second input connected to the output of the digital loop filter and quantizer, and an output connected to the input of the digital loop filter and quantizer for subtracting from the input digital signal an output digital signal from the digital loop filter and quantizer, and in response generating a difference signal for application to the input of the digital loop filter and quantizer; and digital-to-analog converter having a plurality of unit elements with minor mismatching therebetween, for receiving and converting to analog the output digital signal from the digital loop filter and quantizer, and in response generating an output analog signal, where the digital-to-analog converter comprises means for cyclically selecting successive difference permutations of the unit elements ...

Correction of a value of a passive component

Correction d'une valeur d'un composant passif La présente description concerne un circuit intégré comprenant un premier composant passif (Comp) de type capacitif, résistif ou inductif comportant : une pluralité de deuxièmes et troisièmes composants passifs (Compu) dudit type ayant chacun une même première valeur théorique Compu_t, les deuxièmes composants étant connectés entre eux de sorte que leurs valeurs s'ajoutent, et chaque troisième composant étant associé à un premier interrupteur (208) dont l'état détermine si la valeur du troisième composant s'ajoute aux valeurs des deuxièmes composants ; et une pluralité de quatrièmes composants passifs (Compcorr) dudit type chacun associé à un deuxième interrupteur (214) dont l'état détermine si la valeur du quatrième composant s'ajoute aux valeurs des deuxièmes composants, au moins un (Compcorr) des quatrièmes composants (Compcorr) passifs ayant une deuxième valeur théorique égale à (1-P).Compu_t ou à (1+P).Compu_t, avec P positif strictement inférieur à 1/2. Figure pour l'abrégé : Fig. 2

Capacitive digital to analog and analog to digital converters

A digital-to-analog converter (DAC) comprises a capacitive DAC that comprises N first capacitances that are connected in parallel and that have first ends and second ends, wherein N is an integer greater than one, and N first switches that selectively connect a selected one of the second ends of the N first capacitances to a common node and non-selected ones of the second ends of the N first capacitances to one of a voltage potential and a reference potential. Capacitance values of the N first capacitances are substantially equal. A second DAC communicates with the common node.

LOW-POWER COLUMN PARALLEL CYCLIC ANALOG-TO-DIGITAL CONVERTER

A low-power column parallel cyclic analog-to-digital converter and an imaging device using the same. The analog-to-digital converter comprises one stage and is optimized to reduce power, noise and capacitor settling time. The one stage analog-to-digital converter comprises a multiplying circuit for performing a multiplication operation during conversion phases and a sub-analog-to-digital converter connected to receive analog output signals from the multiplying circuit. The sub-analog-to-digital converter converts, during the conversion phases, the analog output signals into portions of an N-bit digital code. The multiplying circuit switches configurations between conversion phases and uses the portions of the digital code during the conversion phases to generate new analog output signals for subseQuent conversion by the sub-analog-to-digital converter.

Tri-level dynamic element matcher allowing reduced reference loading and DAC element reduction

Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been disclosed. Reduced reference loading has been achieved when the tri-level DEM scheme is applied to switched capacitor implementations in particular. Furthermore a differential switched-capacitor DAC implementation, which enables use of the DEM technique is disclosed. The invention allows reduced circuit complexity required to implement a N-bit DAC when constructed using 3-level unit elements.

D/A converter

VERFAHREN UND GERÄT ZUR ANWENDUNG IN SYSTEMEN MIT GESCHALTETEN KAPAZITÄTEN

D/A CONVERTING DEVICE

PURPOSE: To provide a D/A covering device capable of improving accuracy in the output voltage of an analog signal. CONSTITUTION: When data D7-D0 of 8 bits are inputted to a decoder 4, a pair of switches to be connected to both terminals of a prescribed resistor R0 is selected out of respective switches S0A-S255A and S0B-S225B in respective switch groups 3A and 3B of a voltage selector circuit 3 by a control signal from the decoder 4, and the other respective switches are turned off. Then, voltages at both the terminals of the resistor R0 in a voltage generating circuit 2, to which a pair of turned-on switched is connected, and inputted to a differential amplifier 5 and the average voltage of voltages at both terminals of the resistor R0 to connect these turned-on switches is outputted from an output terminal 6 as an analog signal. © KIPO & JPO 2003 ...

TRI-LEVEL DYNAMIC ELEMENT MATCHER ALLOWING REDUCED REFERENCE LOADING AND DAC ELEMENT REDUCTION

Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been disclosed. Reduced reference loading has been achieved when the tri-level DEM scheme is applied to switched capacitor implementations in particular. Furthermore a differential switched-capacitor DAC implementation, which enables use of the DEM technique is disclosed. The invention allows reduced circuit complexity required to implement a N-bit DAC when constructed using 3-level unit elements.

Apparatus for converting digital values into analog values

D/A-Wandler.

A=D converter with several capacitors - has two switches, each coupled to one capacitor group, and switch matrix coupled to switches and capacitors

The converter comprises a number of capacitors, each with an approximately specified capacity. A first group of capacitors is coupled to a switch, with a second such group coupled to a second switch, with the second groups smaller then the first one. To the capacitors and the two switches is coupled a switching matrix for selective connections of the capacitors to the switches. The connection is such that each capacitor in the two groups behave in relation to the group size and the total number of capacitors. Pref. the switching matrix is controllable by a code, provided by a digital counter, e.g. by a pseudo-random digital generator.

Hochauflösender schneller Analog/Digitalwandler.

Variable capacitor using gas discharge

A variable capacitor includes a first electrode 2, a second electrode 3 and, located between the first and second electrodes, gas discharge means such as an array of gas discharge tubes 7. The capacitor includes means for producing an electrical discharge in selected tubes, thereby affecting the capacitance of the capacitor. Corrugated interleaved electrodes and the round or hexagonal cross section tubes are mounted on a pcb for use as a digital-to-analogue converter or to drive an electrostatic loudspeaker diaphragm.

Capacitive digital to analog and analog to digital converters

A CAPACITOR ARRAY ARRANGMENT FOR IMPROVING CAPACITOR ARRAY MATCHING

A capacitor array layout technique for improving capacitor array matching. A capacitor array is laid out in a geometrical configuration wherein the geometrical configuration has a centerpoint. The geometrical configuration is divided into a plurality of first sections wherein each of the plurality of first sections have a corresponding second section diagonally located from and at an approximately equal distance from the centerpoint as said first section. Each of the second sections house a capacitor set of a predetermined value wherein each of the plurality of first sections house a capacitor set of an equal value as the corresponding second section.

DIGITAL-TO-ANALOG CONVERTER WITH HIGH-SPEED OUTPUT

A digital-to-analog converter (DAC) includes separate converter segments (100; 200, 300) for converting the most significant bits (MSB's) and next-most-significant bits (NSB's) of a digital input word. The MSB's are converted in a thermometer-encoded capacitive DAC (CDAC 110), in which the MSB's are decoded and used to control the state of CDAC switches, which connect any of a plurality of CADC reference voltages, through respective unit capacitors, to the DAC output. The NSB's are converted in a preferably binary encoded resistive DAC (RDAC) (200, 300), in which two separate sets ("A" and "B") of RDAC switches selectively connect a plurality of RDAC reference voltages to respective A and B RDAC output buses. Control circuitry (802, 821, 822) is included to decode and apply the MSB's as state control signals to the CDAC switches on each clock cycle. The NSB's are also decoded and applied as control signals, but on alternate clock cycles, to the A and B RDAC switch sets. Bus selection circuitry ...

DIFFERENTIAL PIPELINED ANALOG TO DIGITAL CONVERTER WITH SUCCESSIVE APPROXIMATION REGISTER SUBCONVERTER STAGES USING THERMOMETER CODING

Pipelined analog to digital conversion systems are provided having cascaded multi-bit successive approximation register subconverter stages using thermometer coding. Capacitor arrays are provided in the subconverter stages, where switching logic selectively couples the capacitors to operate in sample, conversion, and residue amplification modes for generating multi-bit subconverter digital outputs and analog subconverter residue outputs, wherein the capacitors are switched according to a thermometer code to reduce differential converter non-linearity.

SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER, METHOD OF CONTROLLING SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER, SOLID-STATE IMAGING DEVICE, AND IMAGING APPARATUS

A successive approximation type A/D converter includes: a reference signal generating section generating a reference signal; a comparator comparing an analog signal input thereto with the reference signal and converting the analog signal into a digital signal; and a control section controlling the reference signal to perform oversampling by executing an A/D conversion process on the analog signal at the comparator plural times such that the analog signal is A/D-converted into a digital value of N bits at the first A/D conversion process and such that the second and subsequent A/D conversion processes are performed starting with a lower bit of the (N−n)-th or lower order with upper n bits of the N-bit digital value obtained at the first A/D conversion process fixed.

Variable capacitor

METHOD AND APPARATUS FOR CONVERTING A/D NONLINEARITIES TO RANDOM NOISE

MULTI-BIT DAC WITH DYNAMIC ELEMENT MATCHING

Capacitive digital to analog and analog to digital converters

A digital-to-analog converter (DAC) comprises a capacitive DAC that comprises N first capacitances that are connected in parallel and that have first ends and second ends, wherein N is an integer greater than one, and N first switches that selectively connect a selected one of the second ends of the N first capacitances to a common node and non-selected ones of the second ends of the N first capacitances to one of a voltage potential and a reference potential. Capacitance values of the N first capacitances are substantially equal. A second DAC communicates with the common node.

Methods and apparatus for calibrating a regulated charge sharing analog-to-digital converter (ADC)

A method of operation in an analog-to-digital converter (ADC) includes performing a calibration operation. The calibration operation includes sampling an input analog reference voltage. A sequence of charge sharing transfers is then performed with a charge sharing regulator to transfer an actual amount of charge between a charge source and a charge load based on the input analog reference voltage. The transferred actual amount of charge is compared to a reference charge value corresponding to the reference voltage. A control input to the charge sharing regulator is adjusted to correspondingly adjust charge sharing of a subsequent amount of charge based on the comparing.

D/A converter for binary coded data word into analog output signal

The D/A converter comprises a capacitor matrix (9) of capacitor cells in columns and lines energises by thermometer coded control signals via control lines. A first coder (6) transcodes the N higher data bits of the data word into 2n bit wide thermometer coded column control signal applied to capacitor matrix via column control lines.A second coder (11) processes the lower data bits into 2m bit wide line control signal for application to the capacitor matrix. Each capacitor cell contains a local decoder circuit for energizing switches for cell capacitors, dependent on thermometer coded line and column control signals.

METHOD AND APPARATUS FOR CONVERTING A/D NONLINEARITIES TO RANDOM NOISE

Mixed analog to digital converter (ADC) with binary weighted capacitor sampling array and sub sampling charge distributing array

混合模数转换器(ADC)有二进制加权电容器阵列和次级电压电容器阵列，它们通过耦合电容器被耦合在一起。次级电压电容器阵列使用一个最小电容器尺寸，其与二进制加权电容器阵列的最小电容器尺寸匹配。耦合电容器的尺寸是最小尺寸的2倍，将对电荷共享导线上的电压效应减半。在次级电压电容器阵列里的第二耦合电容器又各自将电压效应减半，因此次级电压电容器阵列里的第一、第二和第三次级电压电容器产生1/2，1/4和1/8的电压摆幅。只有二进制加权电容器阵列里的MSB电容器采样模拟输入电压。在转换期间，逐次逼近寄存器(SAR)的MSB被用于二进制加权电容器，而LSB被用于次级电压电容器。通过仅仅施加LSB到次级电压电容器阵列，可以降低总电容。

Fast high-resolution analog-to-digital converter

An unknown analog signal is compared in amplitude with the signal from a digital-to-analog (D-A) converter. The converter, preferably monotonic, may be at least partially formed from a plurality of switches connected in a recursive array to define sub-sets having a recurrent relationship. An adjustable-gain amplifier produces a difference signal having an amplitude indicating the amplitude comparison. A flash converter converts the difference signal to binary signals. These binary signals are modified and fed back to the D-A converter to obtain from this converter an output signal having an amplitude approximating the amplitude of the unknown analog signal. A plurality of successive approximations of the analog signal may be provided in this manner. In at least one (1) of these approximations, the gain of the amplifier may be increased to increase the sensitivity of the approximation by increasing the gain of the difference signal. In such approximation(s), before the binary signals from ...

CAPACITOR-ARRAY D/A CONVERTER INCLUDING A THERMOMETER DECODER AND A CAPACITOR ARRAY

Method for selecting capacitors

A method for selecting capacitors in a charge redistribution digital-to-analog converter. m capacitors are arranged in the charge redistribution digital-to-analog converter. First, a signal is input to the charge redistribution digital-to-analog converter to identify n output units of the charge redistribution digital-to-analog converter. Then, the initial capacitor at the initial address and the following n−2 capacitors at the following n−2 addresses are continuously selected and if the following n−2 capacitors comprise the blank capacitor, the next capacitor is selected instead of the blank capacitor and a new blank capacitor is identified. Next, the initial address is changed to the address of the capacitor next to the last selected capacitor. Finally, the n−1 selected capacitors are output for the output units of the charge redistribution digital-to-analog converter. The n and m are positive integers and m>n>=1.

Digital/analog converter

Digital/analog converter for converting a binary coded data word into an analog output signal, having a capacitor cell Matrix (9) comprising capacitor cells (13ij) which are arranged in matrix form in columns and rows and are driven by thermometer-coded control signals via control lines; a first coding device (6) for recoding the n more significant data bits of the data word D to be converted into a thermometer-coded column control signal which has a width of 2n bits and is applied to the capacitor cell matrix (9) via column control lines (8), a second coding device (11) for recoding the m less significant data bits of the data word D to be converted into a thermometer-coded row control signal which has a width of 2m bits and is applied to the capacitor cell matrix (9) via row control lines (12), each capacitor cell (13ij) of the capacitor cell matrix (9) in each cast having an associated local decoding circuit (19ij) which drives switches (34, 35, 36, 37) in a manner dependent on the thermometer-coded ...

Capacitor-array D/A converter including a thermometer decoder and a capacitor array

In a capacitor-array D/A converter which includes a thermometer decoder (103) for thermometer-decoding a decoder input signal having first through m-th (m is an integer not less than two) input bits to produce an output signal having first through n-th (n=2m-1) output bits, where m is an integer not less than two and where n is equal to (2m -1), first through n-th switches (SU1 to SU31) corresponding to the first through the n-th output bits of the thermometer decoder, and a capacitor array (104) including first through n-th capacitors (8C1 through 8C31) corresponding to the first through the n-th switches, the first through the n-th capacitors are arranged in a main area of the capacitor array and in a row direction of the capacitor array consecutively from the center outward to the left and the right to be symmetrical. Each of the first through the n-th switches are supplied with a corresponding bit of the first through the n-th output bits from the thermometer decoder. The corresponding ...

Incremental preloading in an analog-to-digital converter

Capacitive digital to analog and analog to digital converters

A pipelined analog-to-digital converter (ADC) comprises a first stage that receives an input voltage signal and that comprises an analog-to-digital converter (ADC). The ADC includes an amplifier having an input and an output. N capacitances are connected in parallel and include first ends that selectively communicate with the input and second ends. N switches selectively connect the second ends of the N capacitances to the voltage input during a first phase, one of the second ends of the N capacitances to the output of the amplifier during a second phase, and others of the second ends of the N capacitances to one of a voltage reference and a reference potential during the second phase. A second stage communicates with the output the amplifier.

A fast high resolution analog to digital converter

DIGITAL-TO-ANALOG CONVERTER AND METHOD THEREOF

A digitally controlled analog circuit comprises a finite state machine configured for receiving a digital input word and generating at least two digital codes in a manner determined by a state of the finite state machine. The digital codes are decoded into respective sets of binary data. The sets of binary data control respective switched-circuit arrays to generate an analog output corresponding to the digital input word. To establish a monotonic function between the digital input word and the analog output during steady state operations, the finite state machine switches states when a wrap-around condition is detected for one of the digital codes. The finite state machine uses different sets of equations in different states to derive the digital codes.

Method of calibrating a SAR A/D converter and SAR-A/D converter implementing said method

The present disclosure relates to a method of self-calibration of a successive approximation register-analog-to-digital converter. The method includes measuring an error value for each thermometer element of a plurality of thermometer elements and determining a mean value of measured error values. The method also includes generating a thermometer scale where each level of the thermometer scale will be an incremental sum of each value of a first subset, and each further level of the thermometer scale will be a sum of all values of a second subset plus the incremental sum of the elements of the first subset in any order. In addition, the method includes generating the output code according to the thermometer scale.

Capacitor-array d/a converter including a thermometer decoder and a capacitor array

D/A converter

D/A CONVERTING DEVICE

PROBLEM TO BE SOLVED: To provide a D/A covering device capable of improving accuracy in the output voltage of an analog signal. SOLUTION: When data D7-D0 of 8 bits are inputted to a decoder 4, a pair of switches to be connected to both terminals of a prescribed resistor R0 is selected out of respective switches S0A-S255A and S0B-S225B in respective switch groups 3A and 3B of a voltage selector circuit 3 by a control signal from the decoder 4, and the other respective switches are turned off. Then, voltages at both the terminals of the resistor R0 in a voltage generating circuit 2, to which a pair of turned-on switched is connected, and inputted to a differential amplifier 5 and the average voltage of voltages at both terminals of the resistor R0 to connect these turned-on switches is outputted from an output terminal 6 as an analog signal. COPYRIGHT: (C)2002,JPO ...

Successive aproximation A/D converter

METHOD OF CALIBRATING A SAR A/D CONVERTER AND SAR-A/D CONVERTER IMPLEMENTING SAID METHOD

The present disclosure relates to a method of self-calibration of a successive approximation register-analog-to-digital converter. The method includes measuring an error value for each thermometer element of a plurality of thermometer elements and determining a mean value of measured error values. The method also includes generating a thermometer scale where each level of the thermometer scale will be an incremental sum of each value of a first subset, and each further level of the thermometer scale will be a sum of all values of a second subset plus the incremental sum of the elements of the first subset in any order. In addition, the method includes generating the output code according to the thermometer scale.

Multistage scrambler for a digital to analog converter

A multistage scrambler for a digital to analog converter having a non-ideal transfer function resulting from an error function which causes harmonic distortion includes a first shuffling network having a first input for receiving digital data and a first output, the first shuffling network including a first set of data switches; a first sequence generator for selectively interconnecting the first set of data switches to reorder at the first output the digital data received at the first input to reduce the harmonic distortion to lower magnitude colored noise; a second shuffling network having a second input for receiving the reordered digital data from the first output and a second output, the second shuffling network including a second set of data switches; and a second sequence generator for selectively interconnecting the second set of data switches to reorder at the second output the digital data received at the second input to transform the colored noise toward lower power white noise ...

Charge redistribution digital-to-analog converter

Embodiments of the present disclosure may provide a charge redistribution DAC with an on-chip reservoir capacitor to provide charges to the DAC in lieu of traditional external reference voltages. The DAC may include the on-chip reservoir capacitor having a first plate and a second plate, an array of DAC capacitors to generate a DAC output, and an array of switches controlled by a DAC input word to couple the DAC capacitors to the reservoir capacitor. The charge redistribution DAC may further comprise a first switch connecting the first plate to an external terminal for a first external reference voltage, and a second switch connecting the second plate to an external terminal for a second external reference voltage. One embodiment may provide an ADC that includes the charge redistribution DAC.

Digital step attenuator utilizing thermometer encoded multi-bit attenuator stages

A digital step attenuator with thermometer encoded attenuator stages is disclosed. In one embodiment, Embodiments disclosed in the detailed description may include a digital step attenuator, programmable thermometer encoded attenuator stages, the digital step attenuator may include a cascade of programmable thermometer encoded attenuator stages. Each stage may be provided by a programmable impedance array including a plurality of impedances arranged in parallel. The impedance of each of the plurality of each stage may change monotonically by switchably inserting or removing one of the plurality of impedances in the arrays. The control circuit may govern the attenuation level of each of the thermometer encoded accumulator stages as a function of a thermometric codeword, which controls the switches in the arrays.

Digital-analog converter and control method thereof

A digital-analog converter circuit includes sampling capacitive elements ( 111, 112, . . . , 11 N) of which one ends are to be electrically connected to and disconnected from input terminals (D 1, D 2, . . . , DN), to which digital signals are input, via a switch unit (SWu 10 ), an operational amplifier ( 501 ), a switch ( 301 ) capable of electrically connecting and disconnecting the other ends of the sampling capacitive elements ( 111, 112, . . . , 11 N) and an inverting input terminal of the operational amplifier ( 501 ), and a switch unit (SWu 40 ) that is disposed between nodes between the switch unit (SWu 10 ) and the sampling capacitive elements ( 111, 112, . . . , 11 N) and the output terminal of the operational amplifier ( 501 ) and capable of connecting and disconnecting them. An on-resistance value of a MOS transistor included in the switch ( 301 ) is set to be larger than an on-resistance value of a MOS transistor included in the switch unit (SWu 40 ).

Programmable trim filter for successive approximation register analog to digital converter comparator

The disclosure includes a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a sampling network to store a sample of an analog signal. The SAR ADC also includes a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal. The comparator employs a plurality of comparator preamplifiers. The comparator also includes a programmable trim filter. The programmable trim filter is selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with a preamplifier settling time subceeding a preamplifier settling threshold.

PROGRAMMABLE TRIM FILTER FOR SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER COMPARATOR

The disclosure includes a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a sampling network to store a sample of an analog signal. The SAR ADC also includes a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal. The comparator employs a plurality of comparator preamplifiers. The comparator also includes a programmable trim filter. The programmable trim filter is selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with a preamplifier settling time subceeding a preamplifier settling threshold. 1. A converter for a successive approximation register analog to digital conversion , comprising:a capacitive network configured to store a sample of an analog signal;a plurality of comparator preamplifiers;a process monitor configured to determine a frequency response of the plurality of comparator preamplifiers; anda programmable trim filter selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with preamplifier settling time less than a preamplifier settling threshold based on the frequency response of the plurality of comparator preamplifiers.2. The converter of wherein the process monitor includes a ring oscillator.3. The converter of wherein the processor monitor is further configured to determine the frequency response of the plurality of comparator preamplifiers by determining the frequency response of the ring oscillator.4. The converter of wherein the ring oscillator includes a plurality of process monitor preamplifiers having a same configuration as the plurality of comparator preamplifiers.5. The converter of wherein the ring oscillator includes a test filter to vary capacitance applied to the process monitor preamplifiers.6. The converter of wherein the process monitor further includes a processor to measure the frequency ...

Method of calibrating a thermometer-code sar a/d converter and thermometer-code sar-a/d converter implementing said method

A method of calibrating a thermometer-code SAR-A/D converter is provided. The thermometer-code SAR-A/D converter includes an N bit -bit digital-to-analog converter (DAC) for outputting an N bit -bit output code. The DAC includes a first subconverter having a plurality of N Th thermometer elements T j and a second subconverter having a plurality of N Bin binary-weighted elements. The N bit output code is equal to the sum of N BitTh and N BitBin where N Th =2 N BitTh and N BitBin is equal to N Bin =N BitBin . The calibration method includes determining an Integral Non-Linearity error value (ε R ) of an R th thermometer-code level of the thermometer elements. The method further includes reducing the highest of the error value ε R to obtain a reduced error value, and generating the output code according to said reduced error.

SYSTEMS AND METHODS FOR DRIVING AN ELECTRONIC DISPLAY USING A RAMP DAC

A display device may include rows of pixels that displays image data on a display, data lines coupled to the rows of pixels, and a digital-to-analog converter (DAC) that outputs a ramp voltage signal including a data voltage to be depicted on a first pixel of the rows of pixels. The display device may also include a capacitor that receives the ramp voltage signal via the DAC and a circuit that sends a control signal to a circuit component that causes the DAC to couple to the capacitor via one of the data lines for a duration of time that comprises a first time when the ramp voltage signal is below the data voltage and a second time when the ramp voltage signal is approximately equal to the data voltage. The capacitor is coupled to the DAC when the ramp voltage signal is greater than zero. 1. A display device , comprising:a plurality of rows of pixels configured to display image data on a display;a plurality of data lines coupled to the plurality of rows of pixels;a digital-to-analog converter (DAC) configured to output a ramp voltage signal comprising a data voltage to be depicted on a first pixel of the plurality of rows of pixels; anda capacitor configured to receive the ramp voltage signal via the DAC, wherein the capacitor is associated with the first pixel; anda circuit configured to send a control signal to a circuit component configured to cause the DAC to couple to the capacitor via one of the plurality of data lines for a duration of time that comprises a first time when the ramp voltage signal is below the data voltage and a second time when the ramp voltage signal is approximately equal to the data voltage, wherein the capacitor is coupled to the DAC when the ramp voltage signal is greater than zero.2. The display device of claim 1 , comprising a switch configured to couple the DAC to the one of the plurality of data lines based on the control signal provided to the circuit component.3. The display device of claim 1 , wherein the circuit component ...

D/a converter

내용 없음. No content.

Two-stage digital-to-analog converter and LCD source driver

本发明提供一种二级数字模拟转换器与液晶显示器源级驱动器。源级驱动器包含二级数字模拟转换器。此二级数字模拟转换器是根据M位数字输入码来输出模拟电压。源级驱动器包含1位串行电荷重布数字模拟转换器和电压选择器。1位串行电荷重布数字模拟转换器具有可接收高参考电压的高参考电压输入节点以及可接收低参考电压的低参考电压输入节点。电压选择器是根据M位数字输入码的至少一部分来将高参考电压和低参考电压设定至选定电压。

Two-stage digital analog converter and liquid crystal display source electrode driver

本发明在此揭露一种二级数字模拟转换器与液晶显示器源级驱动器。此源级驱动器包含二级数字模拟转换器。此二级数字模拟转换器包含1位串行电荷重布数字模拟转换器、电压选择器以及伽玛校正扩充和决定逻辑(Gamma Correction Expansion&Decision Logic)。1位串行电荷重布数字模拟转换器包含一第一电容、终端电容、第一开关电路以及第二开关电路。第一电容是耦接至电容充电节点和低参考电压输入节点间。终端电容是耦接至电荷收集节点和低参考电压输入节点间。第一开关电路是于电容充电周期中，将电容充电节点耦接至低参考电压输入节点和高参考电压输入节点之一。第二开关电路是于电荷重布周期中，将电容充电节点连接至电荷收集节点。

Flash analog to digital converter (adc)

A flash ADC in which different thresholds are provided to different comparators in different time instances. Such a feature may be advantageously used in digital converters type components since the flash ADC would provide more time for amplifiers to generate amplified residue signals.

Correction of a value of a passive component

Correction d'une valeur d'un composant passif La présente description concerne un circuit intégré comprenant un premier composant passif (Comp) de type capacitif, résistif ou inductif comportant : une pluralité de deuxièmes et troisièmes composants passifs (Compu) dudit type ayant chacun une même première valeur théorique Compu_t, les deuxièmes composants étant connectés entre eux de sorte que leurs valeurs s'ajoutent, et chaque troisième composant étant associé à un premier interrupteur (208) dont l'état détermine si la valeur du troisième composant s'ajoute aux valeurs des deuxièmes composants ; et une pluralité de quatrièmes composants passifs (Compcorr) dudit type chacun associé à un deuxième interrupteur (214) dont l'état détermine si la valeur du quatrième composant s'ajoute aux valeurs des deuxièmes composants, au moins un (Compcorr) des quatrièmes composants (Compcorr) passifs ayant une deuxième valeur théorique égale à (1-P).Compu_t ou à (1+P).Compu_t, avec P positif strictement inférieur à 1/2. Figure pour l'abrégé : Fig. 2 Correction of a value of a passive component The present description relates to an integrated circuit comprising a first passive component (Comp) of the capacitive, resistive or inductive type comprising: a plurality of second and third passive components (Compu) of said type each having a same first theoretical value Compu_t, the second components being connected together so that their values are added, and each third component being associated with a first switch (208) whose state determines whether the value of the third component is added to the values of the second components; and a plurality of fourth passive components (Compcorr) of said type each associated with a second switch (214) whose state determines whether the value of the fourth component is added to the values of the second components, at least one (Compcorr) of the fourth components (Compcorr) liabilities having a second theoretical ...

Digital-to-analog converter

Analog-to-digital converter and related chip

提出了一种模数转换器(10)。所述模数转换器具有模数转换操作模式与量测操作模式。所述模数转换器包括输入端(100)、数模转换器(104)以及输出端(102)。输入端用来接收模拟信号。输出端用来输出数字信号。数模转换器包括多个数模转换单元。当所述模数转换器操作在所述模数转换操作模式时，所述模数转换器用来将所述模拟信号转换为所述数字信号，以及当所述模数转换器操作在所述量测操作模式时，所述数字信号相关于待测数模转换单元的电容值与所述多个数模转换单元的总电容值的比值。

Charge redistribution digital-to-analog converter

Embodiments of the present disclosure may provide a charge redistribution DAC with an on-chip reservoir capacitor to provide charges to the DAC in lieu of traditional external reference voltages. The DAC may include the on-chip reservoir capacitor having a first plate and a second plate, an array of DAC capacitors to generate a DAC output, and an array of switches controlled by a DAC input word to couple the DAC capacitors to the reservoir capacitor. The charge redistribution DAC may further comprise a first switch connecting the first plate to an external terminal for a first external reference voltage, and a second switch connecting the second plate to an external terminal for a second external reference voltage. One embodiment may provide an ADC that includes the charge redistribution DAC.

Method of calibrating a sar a/d converter and sar-a/d converter implementing said method

The present disclosure relates to a method of self-calibration of a SAR-A/D converter, comprising a N bit -bit digital-to-analog converter (DAC) for outputting a N bit -bit output code, said digital-to-analog converter (DAC) comprising a first subconverter (C MSB ) having a plurality N Th of thermometer elements T j (1) and a second subconverter (C LSB ) having a plurality of binary-weighted elements N Bin , said output code being defined by a thermometer scale S Th having a number of levels equal to 2 NBitTh +1. The method is characterized in that it comprises the steps of: - measuring, for each thermometer element of said plurality N Th of thermometer elements T j , an error value; - determining a mean value (µ) of these values; - dividing said plurality N Th of thermometer elements T j into a first subset (X) and a second subset (Y) each containing an identical number of values (x, y), equal to N Th /2, wherein said first subset (X) comprises the thermometer elements T j whose values are closer to said mean value (µ) as long as the error of the sum of thermometer elements T j of the first subset (X) is not worse than the error value of the element farthest from said mean value (µ) of said first subset (X) and said second subset (Y) comprising all the remaining thermometer elements T j ; - generating said thermometer scale, on the assumption that: - each level m i of said thermometer scale S Th , with i ranging from 0 to N Th /2, will be the incremental sum of each value (x) of said first ordered subset X; - each further level m i of said thermometer scale S Th , with i ranging from N Th /2+1 to N Th , will be the sum of all the values (y) of said second subset Y plus the incremental sum of the elements (x) of the subset X in any order; - generating said output code (OUTPUT) according to said thermometer scale S Th .

Method and apparatus for segmented, switched analog/digital converter

A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage such that it significantly reduces a DAC settling time interval during each bit trial. In one exemplary embodiment, the switched-capacitor circuit having first and second groups of capacitor banks is coupled to a first input of a comparator and to a control circuit which provides control signals such that during a switching sequence, an equal value of capacitance is selected from each of the first and second groups of capacitor banks to reduce the DAC settling time interval, thereby improving the conversion rate.

Integrated semiconductor circuit with redundant capacitors

The circuit has at least one capacitor (12) and at least one transfer element (14,15), responding to failure of the capacitor to switch over to a redundant capacitor (13). Pref. the circuit has a number of parallel capacitors (12) and a corresponding number of parallel redundant capacitors (13), with both terminals of each capacitor coupled to a respective transfer element (14,15), e.g. a NMOS-, PMOS-, CMOS-, or bipolar transfer gate.

Charge scaling digital analog converter

本公开的实施方案可提供有片上存储电容器的电荷再分配DAC以取代传统的外部参考电压来向DAC提供电荷。DAC可包括具有第一极板和第二极板的片上存储电容器，DAC电容器阵列以生成DAC输出，以及由DAC输入字控制的开关阵列以耦合DAC电容器到存储电容器。电荷再分配DAC还可包括第一开关，其连接第一极板到外部端子用于第一外部参考电压，以及第二开关，其连接第二极板到外部端子用于第二外部参考电压。一个实施方案可提供包括电荷再分配DAC的ADC。

Digital to analog interface with equalized total signal delay and method of making it

A method of equalizing total signal delay across a digital to analog interface includes constructing a plurality of unit digital to analog converter cells each having a clock input and a data input and an analog output; constructing an analog output network for summing the analog outputs for delivery to a termination which in combination with the analog output network defines a first predetermined time delay between the unit cells; constructing a clock input distribution network for propagating a clock input to each of the unit cells tapped along the clock input distribution network; and connecting a second termination to the clock input distribution network for establishing the clock input distribution network as a transmission line and defining in combination with the clock input distribution network a second predetermined time interval delay between the clock input to the unit cells equal to the first predetermined in the interval delay for synchronizing the propagation of the clock inputs propagating along the clock input distribution network with the analog outputs propagating along the analog output network.

Incremental preloading in an analog-to-digital converter

During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.

Digital-to-analog converter and method thereof

A digitally controlled analog circuit comprises a finite state machine configured for receiving a digital input word and generating at least two digital codes in a manner determined by a state of the finite state machine. The digital codes are decoded into respective sets of binary data. The sets of binary data control respective switched-circuit arrays to generate an analog output corresponding to the digital input word. To establish a monotonic function between the digital input word and the analog output during steady state operations, the finite state machine switches states when a wrap-around condition is detected for one of the digital codes. The finite state machine uses different sets of equations in different states to derive the digital codes.

Noise limitation of a signal dependent multibit digital to analog signal conversion

Several methods and a system of noise limitation of a signal dependent multibit digital to analog signal conversion are disclosed. An exemplary embodiment provides a method that includes receiving an output of a multibit analog to digital circuit of a continuous time sigma delta converter. The method further includes limiting a noise generation by adaptively selecting a digital to analog converter element out of a plurality of digital to analog converter elements in accordance with an input signal magnitude. In addition, the method includes implementing a selected digital to analog converter element to generate an analog signal.

Circuit for converting from analog signal into digital signal and vice versa by using insulated gate field effect transistors

A signal converting circuit for converting an analog signal to a digital signal, or vice versa, comprises a sampling capacitor which is charged to an input signal level during the period of a sampling pulse. A reference capacitor grounded at one end receives charges from the sampling capacitor in response to a first clock pulse. A predetermined reference potential is impressed on a terminal of the sampling capacitor at the time of the sampling pulse and a ground potential at the time the sampling pulse is not present. The reference capacitor is charged in response to the first clock pulse, and is discharged in response to a second clock pulse which alternates with the first clock pulse. The presence of a potential at the sampling capacitor less than the predetermined reference potential is detected, and the cycles of discharging of the reference capacitor that occur until the potential at the sampling capacitor is less than the reference potential are counted. Analog-to-digital (A/D) conversion is achieved by counting the number of discharges of the reference capacitor charged from the sampling capacitor. Digital-to-analog (D/A) conversion is carried out in the circuit when the sampling capacitor is charged to the predetermined potential of the sampling capacitor at the time a digital signal is taken out.

An untrimmed 12 bit montonic all capacitive a to d converter

내용 없음.

Capacitive digital to analog and analog to digital converters

A digital-to-analog converter (DAC) comprises a capacitive DAC that comprises N first capacitances that are connected in parallel and that have first ends and second ends, wherein N is an integer greater than one, and N first switches that selectively connect a selected one of the second ends of the N first capacitances to a common node and non-selected ones of the second ends of the N first capacitances to one of a voltage potential and a reference potential. Capacitance values of the N first capacitances are substantially equal. A second DAC communicates with the common node.

Linearity improvement for high resolution rfdac

A digital to analog converter (DAC) circuit to convert a digital input signal to an analog output signal, wherein the digital input signal comprises a plurality of Least Significant Bits (LSBs) and a plurality of Most Significant Bits (LSBs). The DAC circuit comprises a line decoder configured to receive the plurality of LSBs of the digital input signal and configured to generate line information based thereon. The DAC circuit further comprises a column decoder configured to receive the plurality of MSBs of the digital input signal and configured to generate column information based thereon. Further, the DAC circuit comprises one or more source cells arranged in a plurality of rows and a plurality of columns, wherein the one or more source cells are configured to be selectively activated and consequently generate an individual output signal based on the line information and the column information respectively.

Capacitive digital to analog and analog to digital converters

本发明公开了一种包括电容性DAC的数模转换器(DAC)，所述电容性DAC包括N个第一电容和N个第一开关，其中N是大于1的整数，这N个第一电容并联连接并且具有第一端和第二端，N个第一开关将这N个第一电容的第二端中被选中的一个连接到公共节点，并且将这N个第一电容的第二端中未选中的那些连接到电压电势和参考电势之一。这N个第一电容的电容值基本相等。第二DAC与公共节点通信。

Analogue-to-digital converter and method for using the same

The present invention is related to an analogue-to-digital (A/D) converter (1) for converting an input signal (V in ) to a digital code representing said input signal. The A/D converter comprises a comparator (3) for comparing the input signal with a reference signal (V A ), a search logic block (4) for determining the digital code and a digital-to-analogue converter (5) arranged for receiving input from the search logic block and for providing the reference signal to be applied to the comparator. The digital-to-analogue converter comprises at least a first portion implemented with equal capacitors (20). The ADC optionally further comprises a second portion implemented with binary weighted capacitors. The first portion is arranged for being controlled by a thermometer coded signal. The converter avoids charging-discharging of large capacitors during the search and therefore reduces the lost energy.

STRUCTURE OF CAPACITIVE MATRIX WITH CORRECT CAPACITIVE RATIO BETWEEN COMPONENT CAPACITORS, ESPECIALLY FOR CONVERTERS

Charge redistribution digital-to-analog converter

Embodiments of the present disclosure may provide a charge redistribution DAC with an on-chip reservoir capacitor to provide charges to the DAC in lieu of traditional external reference voltages. The DAC may include the on-chip reservoir capacitor having a first plate and a second plate, an array of DAC capacitors to generate a DAC output, and an array of switches controlled by a DAC input word to couple the DAC capacitors to the reservoir capacitor. The charge redistribution DAC may further comprise a first switch connecting the first plate to an external terminal for a first external reference voltage, and a second switch connecting the second plate to an external terminal for a second external reference voltage. One embodiment may provide an ADC that includes the charge redistribution DAC.

Multiplying digital-to-analog converter configured to maintain impedance balancing

A multiplying digital-to-analog converter suited to maintain impedance balancing during phases. In an embodiment, an input signal may be sampled onto nodes of impedance elements during an initial phase. In a second phase the impedance elements are directly coupled either to a non-inverting reference input or the inverting reference input of an amplifier depending on an output of a related flash ADC output. The determination as to which capacitor is to be coupled to inverting or non-inverting input nodes may be directly programmed into the MDAC using switches, such that a thermometric to binary converter is not required in an example embodiment. Thus, the number of impedance elements coupled to the non-inverting reference input or inverting reference input REFM remains constant in each cycle such that there is no need to settle the non-inverting reference input or inverting reference input to full accuracy.

Method for selecting capacitors

A method for selecting capacitors in a charge redistribution digital-to-analog converter. m capacitors are arranged in the charge redistribution digital-to-analog converter. First, a signal is input to the charge redistribution digital-to-analog converter to identify n output units of the charge redistribution digital-to-analog converter. Then, the initial capacitor at the initial address and the following n−2 capacitors at the following n−2 addresses are continuously selected and if the following n−2 capacitors comprise the blank capacitor, the next capacitor is selected instead of the blank capacitor and a new blank capacitor is identified. Next, the initial address is changed to the address of the capacitor next to the last selected capacitor. Finally, the n−1 selected capacitors are output for the output units of the charge redistribution digital-to-analog converter. The n and m are positive integers and m>n>=1.

Digital to analogue converter and analogue to digital converter using the same

An object of the present invention is to obtain a high A/D or D/A conversion accuracy, even when there exists a slope in the insulating layer film thickness distribution of the capacitors. The DAC comprises: a capacitor array for storing electric charges in accordance with a digital voltage signal; and an operational amplifier of which input terminal is connected with the capacitor array and amplifies a voltage which corresponds to the electric charges. Here, the capacitor array comprises a plurality of unit capacitors which comprises 2 n divisional capacitors which are of the same shape and are connected in parallel. The divisional capacitors are linearly disposed in mirror symmetry about a center line of the capacitor array and one half of the divisional capacitors every unit capacitor is disposed at one side of the center line and another half is disposed at the another side of the center line.

Digital analog converter apparatus and digital analog converter thereof

Radio frequency digital-to-analog converter (RFDAC) with dynamic impedance matching for high linearity

Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.

DAC architecture for LCD source driver

A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a two-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

D/A converter

A D/A converter, especially a cyclic type D/A converter, having an error detection and correction system including: a code conversion circuit (101) for converting a binary code (C) to a multi-states code; a digital-to-analog conversion circuit (102) connected to the code conversion circuit (101) for converting the multi-states code to an analog value; a detection circuit (103) operatively connected to the digital-to-analog conversion circuit for converting the analog value to a digital code; and a control circuit (104) operatively connected to the code conversion circuit (101), digital-to analog conversion circuit (102) and detection circuit (103) for calculating a voltage difference between the analog value at a predetermined code value and another analog value adjacent to the predetermined code value, and for calculating a differential non-linearity error from the voltage difference based on the digital code, in order to obtain error and correction values of capacitors forming the digital-to-analog conversion circuit.

Two-stage digital-to-analog converter and LCD source driver

本发明提供一种二级数字模拟转换器与液晶显示器源级驱动器。源级驱动器包含二级数字模拟转换器。此二级数字模拟转换器是根据M位数字输入码来输出模拟电压。源级驱动器包含1位串行电荷重布数字模拟转换器和电压选择器。1位串行电荷重布数字模拟转换器具有可接收高参考电压的高参考电压输入节点以及可接收低参考电压的低参考电压输入节点。电压选择器是根据M位数字输入码的至少一部分来将高参考电压和低参考电压设定至选定电压。

DIGITAL-ANALOGUE CONVERTER.

Window-Integrated Charge-Mode Digital-to-Analog Converter for Arbitrary Waveform Generator

A digital-to-analog converter circuit that creates an analog waveform from an input digital waveform. Operating the circuit comprises using the input digital waveform to 1) operate a charge control switch to set a charge time period, 2) operate a discharge control switch to set a discharge time period, 3) set a charge current magnitude using a charge gain, and 4) set a discharge current magnitude using a discharge gain. A charge source electrically charges a load capacitor during the charge time period (i.e., the charge mode). A discharge source electrically discharges the load capacitor during the discharge time period (i.e., the discharge mode). A circuit output transmits the analog waveform defined by the charge mode and the discharge mode. A charge current magnitude greater than the discharge current magnitude produces an upward-sloping analog waveform. A charge current magnitude less than the discharge current magnitude produces a downward-sloping analog waveform.

Correction of a value of a passive component

La présente description concerne un circuit intégré comprenant un premier composant passif (Comp) de type capacitif, résistif ou inductif comportant : une pluralité de deuxièmes et troisièmes composants passifs (Comp u ) dudit type ayant chacun une même première valeur théorique Compu_t, les deuxièmes composants étant connectés entre eux de sorte que leurs valeurs s'ajoutent, et chaque troisième composant étant associé à un premier interrupteur (208) dont l'état détermine si la valeur du troisième composant s'ajoute aux valeurs des deuxièmes composants ; et une pluralité de quatrièmes composants passifs (Comp corr ) dudit type chacun associé à un deuxième interrupteur (214) dont l'état détermine si la valeur du quatrième composant s'ajoute aux valeurs des deuxièmes composants, au moins un (Comp corr ) des quatrièmes composants (Comp corr ) passifs ayant une deuxième valeur théorique égale à (1-P).Compu_t ou à (1+P) .Compu_t, avec P positif strictement inférieur à 1/2. The present description relates to an integrated circuit comprising a first passive component (Comp) of capacitive, resistive or inductive type comprising: a plurality of second and third passive components (Comp u ) of said type each having the same first theoretical value Compu_t, the second components being interconnected so that their values add up, and each third component being associated with a first switch (208) whose state determines whether the value of the third component adds to the values of the second components; and a plurality of fourth passive components (Comp corr ) of said type each associated with a second switch (214) whose state determines whether the value of the fourth component adds to the values of the second components, at least one (Comp corr ) of the fourth passive components (Comp corr ) having a second theoretical value equal to (1-P) .Compu_t or to (1 + P) .Compu_t, with positive P strictly less than 1/2.

Capacitive digital to analog and analog to digital converters

Two-stage dac architecture for lcd source driver utilizing one-bit serial charge redistribution dac

A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Digital-to-analog converter

A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.

降低针对cdac参考电压的信号相关性

用于减小对于CDAC的参考电压的信号相关性包括：将去耦电容器划分为尺寸小于去耦电容器尺寸的多个电容器；在转换阶段期间从耦合至参考电压的采样缓冲器隔离多个电容器的至少一个；以及使用用于将虚设电荷泵入CDAC中的电荷泵来在每个转换步骤处提供补充由CDAC中电容器所汲取电荷所需的合适量电荷，从而CDAC针对每个转换步骤的每次代码改变汲取基本上相似量的电荷。

Analog-digital-wandler und verwendungsverfahren dafür

容量性デジタル／アナログおよびアナログ／デジタルコンバータ

【課題】容量性および／または抵抗性Ｄ／ＡおよびＡ／Ｄコンバータにおいて、単調性を確保する。 【解決手段】パイプライン型アナログ／デジタルコンバータ（ＡＤＣ）が、入力電圧信号を受信する第１のステージ手段であって、入力部および出力部を有する増幅器と、並列接続され、入力部と選択的に通信する第１の端部と第２の端部とを含むＮ個の容量と、第１のフェーズ中にＮ個の容量の第２の端部を電圧入力部と、第２のフェーズ中にＮ個の容量の第２の端部のうち１個を増幅器の出力部と、第２のフェーズ中にＮ個の容量の第２の端部のうち他の端部を電圧基準および基準電位の一方と、選択的に接続するＮ個のスイッチと、を含む、アナログ／デジタルコンバータ（ＡＤＣ）を備える第１のステージを備えている。 【選択図】図１２Ａ

容量性デジタル／アナログおよびアナログ／デジタルコンバータ

【課題】容量性および／または抵抗性Ｄ／ＡおよびＡ／Ｄコンバータにおいて、単調性を確保する。 【解決手段】デジタル／アナログコンバータ（ＤＡＣ）が、直列で互いに接続され、Ｘが１より大きい整数であるＸ個の容量性ＤＡＣを備えている。Ｘ個の容量性ＤＡＣのそれぞれが、Ｍが１よりも大きい整数であるＭ個のスイッチと、信号入力部と、信号出力部と、Ｍ個のスイッチとそれぞれ通信し、第１および第２の端部およびほぼ等しい容量値を有するＭ個の容量とを備えている。Ｍ個のスイッチが、Ｍ個の容量の第１の端部を信号出力部に選択的に接続する。Ｍ個のスイッチが、Ｍ個の容量のうち選択された１個の第２の端部を信号入力部と接続する。第１のＤＡＣが、Ｘ個の容量性ＤＡＣのうち１個の信号入力部と通信する信号出力部を有している。 【選択図】図９Ｂ

Capacitive digital to analog and analog to digital converters

A digital-to-analog converter (DAC) comprises a capacitive DAC that comprises N first capacitances that are connected in parallel and that have first ends and second ends, wherein N is an integer greater than one, and N first switches that selectively connect a selected one of the second ends of the N first capacitances to a common node and non-selected ones of the second ends of the N first capacitances to one of a voltage potential and a reference potential. Capacitance values of the N first capacitances are substantially equal. A second DAC communicates with the common node.

Control circuit of pipeline ADC

A control circuit of a pipeline analog-to-digital converter (ADC) is provided. The pipeline ADC includes a multiplying digital-to-analog converter (MDAC) which includes a capacitor. The control circuit includes six switches and two buffer circuits. The first and second switches are respectively coupled between one end of the capacitor and the first and second reference voltages. The output terminals of the first and second buffer circuits are respectively coupled to the first and second switches. The input terminal of the first buffer circuit is coupled to the third reference voltage through the third switch, or receives a control signal through the fifth switch. The input terminal of the second buffer circuit is coupled to the fourth reference voltage through the fourth switch, or receives the control signal through the sixth switch. The first and second reference voltages are different, and the first and second switches are not turned on simultaneously.

逐次逼近型a/d转换器及其控制方法、固体摄像器件和摄像装置

本发明提供了逐次逼近型A/D转换器及其控制方法、固体摄像器件和摄像装置，所述逐次逼近型A/D转换器包括：生成基准信号的基准信号生成部；比较器，所述比较器使输入至所述比较器中的模拟信号与所述基准信号相比较，并且将所述模拟信号转换为数字信号；以及控制部，所述控制部控制所述基准信号，通过在所述比较器处对所述模拟信号执行多次A/D转换过程来进行过采样，使得所述模拟信号在第一次A/D转换过程中被A/D转换为N位数字值，并且在所述第一次A/D转换过程中得到的所述N位数字值的较高n位是固定的情况下，从第(N-n)位以下的较低位开始进行第二次及后续的A/D转换过程。因此，本发明能够缩短包括过采样的过程所需要的时间，从而能够缩短A/D转换所需的时间。

캐패시터 어래이 정합을 개선시키는 캐패시터 어래이 배열

캐패시터 어래이 정합을 개선하는 캐패시터 어래이 레이아웃 기술. 캐패시터 어래이는 중심점을 갖는 기하학적인 형태로 놓이게된다. 가하학적인 형태는 복수의 제 1섹션들로 분할되고 각 복수의 제 1섹션들은 중심점으로부터 대각선으로 위치되고 중심점으로부터 상기 제 1섹션과 대략 같은 거리로 대응하는 제 2섹션을 가진다. 각 제 2섹션은 설정된 값의 캐패시터 세트를 수용하고 복수의 제 1섹션은 대응하는 제 2섹션과 같은 값의 캐패시터 세트를 수용한다.

Bipolarer elementenmittelnder Digital-Analog-Wandler

可変コンデンサ

(57)【要約】 可変コンデンサが開示されている。この可変コンデンサは、第１電極（２）と、第２電極（３）と、両電極間のガス放電管（７）のアレイとを含んでいる。このコンデンサは放電管内で放電させる手段を含んでおり、コンデンサの静電容量に影響を及ぼす。

キャパシタアレイマッチングを向上させるためのキャパシタアレイ構成

(57)【要約】 キャパシタアレイマッチングを向上させるためのキャパシタアレイレイアウト技術である。キャパシタアレイは、幾何学的配置にレイアウトされ、この幾何学的配置は、中心点を有する。幾何学的配置は、複数の第１のセクションに分割され、複数の第１のセクションの各々は、中心点から対角線上であって、中心点から第１のセクションとほぼ同じ距離に配置される対応する第２のセクションを有する。第２のセクションの各々は、所定値のキャパシタの組を格納し、複数の第１のセクションの各々は、対応する第２のセクションと等しい値のキャパシタの組を格納する。

Digital/analog converter and method for controlling same

Digital-to-analog converter

A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.

环路滤波器、量化器、数模转换器以及运算放大器

一种环路滤波器、量化器、数模转换器以及运算放大器。环路滤波器实现于∑Δ模数转换器中，包括：多个串行连接的积分器，包括第一积分器和第二积分器；第一正反馈电阻性元件，置于第二积分器的第一输出节点和第一积分器的第一输入节点之间的第一正反馈路径中；以及第一负反馈电阻性元件，置于第二积分器的第二输出节点和第一积分器的第一输入节点间的第一负反馈路径中。本发明可满足无线通信接收机应用的需求，能减小环路滤波器电阻器的大小，形成无泡沫错误的温度计码，且可降低谐波失真。

導管式類比數位轉換器之控制電路

一種導管式類比數位轉換器之控制電路。導管式類比數位轉換器包含乘法數位類比轉換器，且乘法數位類比轉換器包含電容。控制電路包含第一至第六開關，以及第一及第二緩衝電路。第一及第二開關分別耦接於電容之一端與第一及第二參考電壓之間。第一及第二緩衝電路之輸出端分別耦接第一及第二開關。第一緩衝電路之輸入端透過第三開關耦接第三參考電壓，或透過第五開關接收控制訊號。第二緩衝電路之輸入端透過第四開關耦接第四參考電壓，或透過第六開關接收控制訊號。第一參考電壓不等於第二參考電壓，且第一開關及第二開關不同時導通。

Digital to Analog Converter Cell for Signed Operation

A communication system receives an inputs signal and generates a converted output signal. A control signal selectively activates one or more source cells among an array of cells. The selected source cells generate a first charge package and a second charge package at a cell output terminal for the array of cells to generate the converted output signal. The first charge package and the second charge package are generated during the same clock cycle.

Reducing signal dependence for cdac reference voltage

Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step.

Cdac 레퍼런스 전압에 대한 신호 의존성 감소

CDAC의 레퍼런스 전압에 대한 신호 의존성을 감소시키는 방법은 디커플링 커패시터를 디커플링 커패시터의 사이즈보다 더 작은 사이즈의 복수의 커패시터들로 분할하는 단계; 변환 단계 동안에 레퍼런스 전압에 커플링된 샘플링 버퍼로부터 복수의 커패시터들 중 적어도 하나를 분리하는 단계; 및 CDAC의 결과적인 구성들이 각각의 변환 단계의 각각의 코드 변화를 위해 실질적으로 유사한 양의 전하를 인출하도록, 더미 전하를 CDAC로 펌핑하기 위하여 전하 펌프를 사용하여 각각의 변환 단계에서 CDAC의 커패시터들에 의해 인출되는 전하를 보충하는데 필요한 적합한 양의 전하를 공급하는 단계를 포함한다.

Ｃｄａｃ基準電圧についての信号依存性を低減すること

ＣＤＡＣの基準電圧についての信号依存性を低減することが、減結合キャパシタを、減結合キャパシタのサイズよりもサイズが小さい複数のキャパシタに分割することと、変換段階中に、複数のキャパシタのうちの少なくとも１つを、基準電圧に結合されたサンプリングバッファから分離することと、各変換ステップの各コード変化について、ＣＤＡＣの得られた構成が実質的に同様の電荷量を引き出すように、ＣＤＡＣにダミー電荷をポンピングするためのチャージポンプを使用して、各変換ステップにおいてＣＤＡＣ中のキャパシタによって引き出される電荷を補充するために必要とされる適切な電荷量を供給することとを含む。

Reducing signal dependence for cdac reference voltage

Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step.

類比數位轉換器之增量預載

在循序漸近式暫存器類比數位轉換器操作期間，可於執行位檢驗之前先對若干最高有效位預載預設位元判定。本發明之系統及方法即是進行預設位元判定之增量預載，例如用以將比較器輸入處之電壓維持在一有限之可接受輸入電壓範圍內。

A capacitor array arrangement for improving capacitor array matching

改善电容器矩阵匹配的电容器矩阵布置

本发明涉及一种改善电容器矩阵匹配的电容器矩阵布置方法。电容器矩阵布置在具有中心点的几何图形中。所述的几何图形被分成多个第一部分，其中多个第一部分的每个具有对应的第二部分，所述的第二部分在距第一部分的中心点近似相等的距离对角设置。每个第二部分放置预定值的电容器组，其中所述的多个第一部分的每一个放置与对应的第二部分等值的电容器组。

Digital-to-analog converter, digital-to-analog conversion system, electronic system, base station and mobile device

A digital-to-analog converter is provided. The digital-to-analog converter includes a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter includes a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells includes a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells include different numbers of inverter cells. The digital-to-analog converter additionally includes an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.

Pipelined type a/d converter

The present invention aims to provide a pipeline type A/D converter capable of realizing low power consumption while preventing a reduction in feedback factor of an amplifier. One embodiment of the present invention is of a pipeline type A/D converter which converts an analog signal to a digital signal, including a plurality of stages coupled in tandem and an error correction circuit which generates the digital signal, based on sub digital signals respectively outputted from the stages. When a sub digital signal of N bits is outputted at at least one of the stages in the pipeline type A/D converter according to the one embodiment of the present invention, the stage gain of a transfer function becomes 2 N−K−1 , the number of returns becomes 2 N −2 and an integer K has a relation of 1≦K≦N.

Variabler kondensator

Variable capacitor

A variable capacitor includes a first electrode (2), a second electrode (3) and, located between the first and second electrodes, an array of gas discharge tubes (7). The capacitor includes means for producing an electrical discharge in the tubes, thereby affecting the capacitance of the capacitor.

スイッチドキャパシタシステムに使用する方法および装置

Loop filter and quantizer and digital-to-analog converter and operational amplifier

Incremental preloading in an analog-to-digital converter

During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.

Digital-to-analog converter, digital-to-analog conversion system, electronic system, base station and mobile device

Verfahren und gerät zur anwendung in systemen mit geschalteten kapazitäten

Method and apparatus for use in switched capacitor systems

スイッチドキャパシタシステムに使用する方法および装置

デジタル・アナログ変換技術、アナログ・デジタル変換技術および／またはスイッチドキャパシタ技術を利用するシステム、方法、装置および送受器。

Window-integrated charge-mode digital-to-analog converter

A digital-to-analog converter circuit that creates an analog waveform from an input digital waveform. Operating the circuit comprises using the input digital waveform to 1) operate a charge control switch to set a charge time period, 2) operate a discharge control switch to set a discharge time period, 3) set a charge current magnitude using a charge gain, and 4) set a discharge current magnitude using a discharge gain. A charge source electrically charges a load capacitor during the charge time period (i.e., the charge mode). A discharge source electrically discharges the load capacitor during the discharge time period (i.e., the discharge mode). A circuit output transmits the analog waveform defined by the charge mode and the discharge mode. A charge current magnitude greater than the discharge current magnitude produces an upward-sloping analog waveform. A charge current magnitude less than the discharge current magnitude produces a downward-sloping analog waveform.

Hybrid digital-to-analog converter and method thereof

Hybrid digital-to-analog converter and method thereof are provided. The hybrid digital-to-analog converter (DAC) includes a data processor, at least one first type DAC, at least one second type DAC, and an output circuit. The data processor processes an input digital signal to output at least one of first and second digital signals which are related to a higher bit portion and a lower bit portion of the input digital signal, respectively. If the data processor outputs the first digital signal to the first type DAC, the first type DAC converts the first digital signal. The at least one second type DAC receives and converts the second digital signal outputted from the data processor. The output circuit receives at least one output signal of the first and the second type DACs to output an output analog signal.

Dia converter and dleta-sigma d/a converter