Устройство для формирования имитостойких нелинейных рекуррентных последовательностей

Изобретение относится к технике формирования сложных шумоподобных сигналов. Технический результат заключается в расширении функциональных возможностей за счет формирования различных словарей нелинейных рекуррентных последовательностей для различных кодовых словарей и их программную смену в процессе работы длительностью L=12. При этом процесс формирования нелинейных рекуррентных последовательностей (НЛРП) и нелинейных рекуррентных последовательностей неинверсно-изоморфной (НЛРПНИ) осуществлен таким образом, что через каждые 12 тактов будут формироваться новые НЛРП, сдвинутые на 3 символа влево, после чего записывают новый код цифры словаря, обеспечивая формирование таких словарей НЛРП и НЛРПНИ, в которых каждые последующие НЛРП и НЛРПНИ будут отличаться от предыдущих сдвигом тактов влево. 3 ил.

СПОСОБ, УСТРОЙСТВО И НОСИТЕЛЬ ДЛЯ КОДИРОВАНИЯ СОСТОЯЩЕЙ ИЗ МНОГИХ СЛОВ ИНФОРМАЦИИ

Изобретение относится к способам кодирования информации и декодирования перемеженной и защищенной от ошибок информации, а также к устройству и носителю для кодирования этой информации. Техническим результатом является обеспечение формата кодирования с меньшим объемом непроизводительных издержек. Устройство кодирования информации содержит средство пословного перемежения, средства пословного кодирования защиты от ошибок, формирующее средство для формирования ключей. Способ кодирования описывает работу указанного устройства. На носитель записан указанный способ. Способ декодирования заключается в обеспечении пословного обращенного перемежения и выведения ключей, определяющих местонахождение ошибок в словах группы, состоящей из многих слов. 5 н. и 15 з.п. ф-лы, 6 ил.

УСТРОЙСТВО И СПОСОБ ГЕНЕРАЦИИ КОДОВ В СИСТЕМЕ СВЯЗИ

Изобретение относится к передаче данных для генерации дополнительных кодов с использованием турбокодов в системе связи, работающей по схеме повторной передачи. Технический результат - повышение пропускной способности. Для этого генерируют исходную матрицу перфорации, из которой получают первый субкод в системе связи, содержащей турбокодер для генерации информационных символов, первых символов четности и вторых символов четности для входного потока информационных битов и генератор субкодов из информационных символов, первых символов четности и вторых символов четности с помощью матрицы перфорации, причем количество субкодов равно количеству матриц перфорации, при этом выбирают информационные символы в количестве, равном количеству столбцов исходной матрицы перфорации, их информационных символов, выдаваемых турбокодером. 4 с. и 17 з.п. ф-лы, 6 ил., 4 табл.

СПОСОБ И УСТРОЙСТВО ДЛЯ ОЦЕНКИ КАЧЕСТВА УСЛУГ НА КАНАЛАХ ПЕРЕДАЧИ В ЦИФРОВОЙ СИСТЕМЕ ПЕРЕДАЧИ

Изобретение относится к способу и устройству для оценки качества услуг на каналах передачи в цифровой системе передачи. Технический результат заключается в оценке качества услуг канала передачи без необходимости дополнительных затрат. Способ, при котором для кодирования каналов со стороны передатчика в турбокодере осуществляют турбокодирование, а со стороны приемника в турбодекодере осуществляют турбодекодирование с выходными сигналами с мягким решением, при этом качество услуг определяют по мгновенным значениям дисперсии выходных сигналов с мягким решением на турбодекодере. 2 с. и 12 з. п.ф-лы, 11 ил.

КОДИРОВАНИЕ И ПЕРЕОТОБРАЖЕНИЕ СООБЩЕНИЯ

Изобретение относится к связи, более конкретно к способам для передачи сообщений с кодированием. Описаны способы для переотображения сообщений до кодирования, в которых L обозначенных сообщений из общего числа К сообщений переотображают в L переотображенных сообщений, которые ассоциированы с L кодовыми словами, имеющими большее относительное расстояние между этими кодовыми словами, где L может быть намного меньше К. Эти L обозначенных сообщений могут быть чаще используемыми сообщениями и/или более важными сообщениями. Переотображение обеспечивает возможность отправлять L кодовых слов с большим относительным расстоянием для L обозначенных сообщений. Передатчик переотображает входное сообщение в переотображенное сообщение, кодирует это переотображенное сообщение для получения кодового слова и отправляет это кодовое слово для передачи этого входного сообщения. Приемник декодирует принятое кодовое слово для получения декодированного сообщения и восстанавливает это декодированное сообщение для ...

ЭФФЕКТИВНЫЕ СПОСОБЫ И УСТРОЙСТВА АВТОМАТИЧЕСКОГО ЗАПРОСА ПОВТОРЕНИЯ

Изобретение относится к области техники связи и, более конкретно, к способам автоматических запросов повторения в системе беспроводной связи множественного доступа. Сущность изобретения состоит в том, что используют различные сигналы ОПДТ (отрицательного подтверждения) для указания различных относительных уровней успеха в отношении неудачной попытки декодирования полученного сигнала. Сигнал ПДТ (подтверждения) используют в случае успешного декодирования. Устройство, которое сгенерировало и передало исходный кодированный сигнал, получает сигнал ОПДТ и выбирает часть избыточной информации, например дополнительные биты исправления ошибок, подлежащие передаче на основании значения сигнала ОПДТ. Если сигнал ОПДТ указывает низкий уровень успеха декодирования, указывающий относительно большое количество ошибок в декодированном сигнале, выбирают и передают большой набор избыточной информации. Если сигнал ОПДТ указывает относительно успешное декодирование, например относительно немного ошибок, выбирают ...

СПОСОБ ПРЕДОТВРАЩЕНИЯ ОШИБОК ДЛЯ МУЛЬТИМЕДИЙНОЙ СИСТЕМЫ

Изобретение относится к способу предотвращения ошибок при декодировании для мультимедийных систем. В процессе декодирования множества пакетов данной информации способ предотвращения ошибок включает следующие этапы: (а) декодирование одного из множества пакетов, (b) декодирование другого пакета, когда в процессе декодирования имеет место ошибка на этапе (а): (с) декодирование комбинации пакетов этапов (а) и (б) или третьего пакета, когда ошибка имеет место на этапе (b), и (d) повторение этапа (с) до тех пор, пока ошибка декодирования больше не будет возникать. Технический результат состоит в получении постоянной пропускной способности для канала, содержащего ошибки пакетов, канала, содержащего случайные ошибки, и канала, где оба типа ошибок присутствуют одновременно. 2 н. и 2 з.п. ф-лы, 6 ил.

Устройство для диагностики сигнально-кодовых конструкций

Полезная модель относится к технике связи и может быть использована для определения неизвестной структуры сигнально-кодовой конструкции (относительной решетчатой кодовой модуляции – trellis code modulation, TCM) со скоростью кодирования, равной 2/3, и кодовым ограничением, равным К, на основе анализа принимаемой кодовой последовательности. В устройстве предлагается определять структуру кодера сигнально кодовых конструкций, анализируя особенности принимаемых символов. При этом получаемый один из принятых символов используется как раскодированный информационный символ, а другой получается сравнением вариантов присвоения логических пар значениям фаз принятых сигналов и получением порождающих полиномов для каждого из вариантов. Таким образом, использование предлагаемого устройства диагностики позволяет определить неизвестную структуру используемого кодера для обеспечения работоспособности декодеров и повышения помехоустойчивости передачи информации.

УСТРОЙСТВО СДВИГА

Изобретение относится к области вычислительной техники и может быть использовано в процессорах обработки сигналов и процессорах общего назначения, устройствах кодирования и декодирования данных, устройствах криптографии. Технический результат - увеличение быстродействия, обеспечение возможности задания величины логических сдвигов в диапазоне от 0 до N разрядов и более N разрядов. Устройство сдвига содержит двунаправленную матрицу сдвига размерностью NxM, где M=logN, из М каскадов элементов 2И-2И-2И-3ИЛИ и 2И-2И-2ИЛИ, блок модификации количества сдвигов, содержащий группу из (М-2) элементов ИЛИ, первую группу из (М-1) элементов И и группу из (М-1) элементов ИСКЛЮЧАЮЩЕЕ ИЛИ, блок управления направлением сдвига, содержащий вторую группу из (М-1) элементов И, группу из (М-1) элементов И с входом запрета, группу из (М-1) элементов НЕ и третью группу из (М-1) элементов И, блок формирования флага нулевого результата, содержащий первый, второй и третий элементы И с входом запрета, первый и второй ...

РЕКОНФИГУРИРУЕМЫЙ КОДЕР ПОЛЯРНЫХ КОДОВ 5G СЕТЕЙ

Полезная модель относится к электротехнике, к области цифровой обработки сигналов (ЦОС). Техническим результатом полезной модели является создание реконфигурируемого кодера полярных кодов 5G сетей с увеличенным быстродействием и с меньшими аппаратными затратами, за счет использования одного массива памяти из N элементов, N/2 сумматоров XOR, а также за счет отсутствия мультиплексоров, вследствие отсутствия необходимости перенастройки коммутации с каждым тактом. 1 н.п. ф-лы, 3 ил.

СПОСОБ ПЕРЕДАЧИ ДИСКРЕТНОГО СООБЩЕНИЯ И СИСТЕМА ДЛЯ ЕГО ОСУЩЕСТВЛЕНИЯ

Изобретение относится к области связи, в частности к способам и средствам для передачи дискретных сообщений, и может быть использовано для передачи информации как в проводных каналах связи, так и в каналах связи, использующих электромагнитные волны. Технический результат - упрощение реализации за счет исключения из процесса кодирования и декодирования операций умножения и деления. Система передачи дискретного сообщения содержит кодер, модулятор, передатчик, приемник, демодулятор, декодер. Кодер содержит первый формирователь импульсов, блок памяти кодов операций дополнительной матрицы, генератор импульсов с частотой повторения fn/k, первый удвоитель частоты повторения импульсов, первый кольцевой счетчик до k, первую группу из m вычислителей проверочного элемента, первый ключ, кольцевой счетчик до (2k+1), первый элемент И, первый блок оперативной памяти, m вычислителей функции g2, первый триггер, второй блок оперативной памяти, первый кольцевой счетчик до n. Декодер содержит второй формирователь ...

СПОСОБ ПРИЕМА СИГНАЛОВ ОТНОСИТЕЛЬНОЙ ФАЗОВОЙ ТЕЛЕГРАФИИ В УСТРОЙСТВАХ ПРИЕМА СИГНАЛОВ С ФАЗОВОЙ МАНИПУЛЯЦИЕЙ

Изобретение относится к электросвязи. Технический результат – повышение помехоустойчивости приема сигналов. Он достигается в способе приема сигналов относительной фазовой телеграфии в устройствах приема сигналов с фазовой манипуляцией, в соответствии с которым входной сигнал ОФТ одновременно подают на входы формирователя опорного когерентного напряжения (ФОКН) и фазового детектора (ФД), в котором производят когерентное детектирование входного сигнала с использованием опорного когерентного напряжения с выхода ФОКН, видеосигнал с выхода ФД подают на регенератор, обеспечивающий регистрацию последовательности двоичных символов в моменты поступления тактовых импульсов с выхода блока выделения тактовой частоты на тактовые входы регенератора и последующего кодопреобразователя (КП), в котором производят перекодирование двоичной последовательности с выхода регенератора с целью снятия относительности, причем выход КП является выходом демодулированого двоичного сигнала, при этом дополнительно демодулированный ...

СПОСОБ КОДИРОВАНИЯ И ПЕРЕДАЧИ ЦИФРОВОЙ ИНФОРМАЦИИ

Изобретение относится к системам беспроводной связи. Технический результат - повышение эффективности способа расширения алфавита кодовых сообщений при одновременном упрощении конструкции антенного блока. Для этого предложен способ, который заключается в том, что цифровые сигналы излучают в виде радиоволн через антенный блок, одну антенну. При этом сигналы от источника цифровых сигналов поступают на блок управления, а затем на ряд ключей, на вторые входы которых подается одна из n, создаваемых синтезатором частот. Количество ключей и частот совпадает. Далее частоты, прошедшие через открытые ключи, поступают на сумматор, с выхода которого поступают на антенну и излучаются в эфир. Те ключи, на которые управляющие сигналы с блока управления не поступают, остаются закрытыми, и соответствующие частоты, соответственно, на сумматор не поступают и в эфир не излучаются. Набор частот, излучаемых в данный момент, соответствует передаваемому цифровому сигналу. 2 ил.

СПОСОБ И УСТРОЙСТВО ДЛЯ ПЕРЕМЕЖЕНИЯ БИТОВ СИГНАЛОВ В СИСТЕМЕ ЦИФРОВОГО ЗВУКОВОГО РАДИОВЕЩАНИЯ

... 1. Способ перемежения битов цифрового сигнала, представляющего данные и/или аудиоданные в системе цифрового звукового радиовещания, который содержит шаги: записи множества битов цифрового сигнала во внутреннюю матрицу; считывания битов из внутренней матрицы; при этом, по меньшей мере, один из шагов записи и считывания выполняется по непоследовательной схеме адресации; и записи битов в выходную матрицу. 2. Способ по п.1, по которому число битов в выходной матрице равно числу битов в кадре передачи цифрового сигнала. 3. Способ по п.1, по которому биты во внутренней матрице располагаются во множестве секторов. 4. Способ по п.3, по которому каждый из секторов содержит множество блоков. 5. Способ по п.3, по которому каждый из секторов содержит группу битов, представляющих логический канал. 6. Способ по п.5, по которому биты в каждом логическом канале скремблируются. 7. Способ радиопередачи цифровой информации, представляющей данные и/или аудиоданные в системе цифрового звукового радиовещания ...

Способ и устройство дл формировани (n,3) кода и (n,4)кода с использованием симплексных кодов

... 1. Устройство для кодирования информационного битового потока с 3 битами в (n, 3) кодовое слово с n кодовыми символами, содержащее симплексный кодер, предназначенный для формирования кодового слова Рида - Маллера первого порядка с (Р+1) кодовыми символами из входного информационного битового потока для n>Р, а также для выкалывания первого кодового символа из (Р+1) кодовых символов Рида - Маллера первого порядка для создания (Р, 3) симплексного кодового слова, перемежитель, предназначенный для перестановки Р кодовых символов (Р, 3) симплексного кодового слова столбцами согласно заданной конфигурации, и повторитель, предназначенный для повторения переставленного столбцами (Р, 3) кодового слова до тех пор, пока число повторяющихся кодов не станет равным n, и для выведения (n, 3) кодового слова с повторяющимися n кодовыми символами. 2. Устройство по п.1, отличающееся тем, что если k=3, то (Р, 3) симплексное кодовое слово переставляется столбцами согласно следующей конфигурации: [S1, S2, S3, ...

Устройство и способ генерации кодов в системе св зи

... 1. Способ переупорядочения субкодов двумерных квазидополнительных турбокодов (КДТК), заключающийся в том, что генерируют наборы субкодов КДТК с данными скоростями кодирования, и переупорядочивают субкоды, которые должны передаваться после субкода с заданной скоростью кодирования, из набора субкодов с той же самой или другой скоростью кодирования. 2. Способ по п.1, отличающийся тем, что субкод является матрицей с элементами, которые представляют выкалывание и повторение. 3. Способ по п.1, отличающийся тем, что при операции переупорядочения генерируют новые наборы субкодов, причем матрица для каждого субкода в каждом новом наборе субкодов имеет столько столбцов, каков наименьший общий множитель числа столбцов каждого субкода в наборах субкодов, и определяют приоритет матриц субкодов в каждом новом наборе субкодов таким образом, чтобы матрица, сгенерированная с помощью объединения матрицы двух новых наборов субкодов, имела характеристику КДТК, и переупорядочивают матрицы в каждом новом субкоде ...

КОДИРОВАНИЕ ИНФОРМАЦИИ В КОДОВОМ СЛОВЕ В СЕТЯХ БЕСПРОВОДНОЙ СВЯЗИ

... 1. Способ в сущности сети беспроводной связи, способ состоит в том, что ! кодируют данные с использованием кода с исправлением ошибок, чтобы сформировать кодовое слово, включающее в себя избыточность; ! генерируют второе кодовое слово посредством того, что кодируют дополнительные данные в части первого кодового слова, ! часть первого кодового слова, в которой закодированы дополнительные данные, находится в пределах возможности исправления ошибок первого кодового слова. ! 2. Способ по п.1, в котором формируют первое кодовое слово посредством того, что кодируют данные с использованием кода Файра. ! 3. Способ по п.1, в котором генерируют второе кодовое слово посредством того, что выполняют операцию исключающего ИЛИ дополнительных данных в части первого кодового слова. ! 4. Способ по п.1, в котором генерируют второе кодовое слово посредством того, что замещают часть первого кодового слова дополнительными данными. ! 5. Способ по п.1, в котором генерируют второе кодовое слово посредством того ...

СПОСОБ КОДИРОВАНИЯ ДАННЫХ И СИСТЕМА ХРАНЕНИЯ ДАННЫХ

Изобретение относится к способу кодирования данных в распределенной системе хранения данных и системе хранения данных. Технический результат заключается в повышении эффективности кодирования данных в распределенной системе хранения данных за счет снижения количества обращений к узлам распределенной системы хранения данных при кодировании данных. Способ содержит этапы, на которых: a) получают запрос на изменение по меньшей мере одного блока данных в структуре данных, расположенной в распределенной системе хранения данных; b) записывают по меньшей мере один блок измененных данных, полученный на этапе а), в первое хранилище данных узла хранения данных в виде реплики; c) определяют месторасположение блоков структуры данных во втором хранилище данных; d) осуществляют перемещение по меньшей мере одного измененного блока данных во второе хранилище данных, причем в процессе перемещения выполняют кодирование измененного блока данных, в ходе которого выполняют: i) чтение измененного блока данных, ...

Способ встраивания информации в цветное изображение

Изобретение относится к области защиты информации и может быть использовано для хранения и скрытой передачи конфиденциальной информации по открытым каналам связи. Техническим результатом изобретения является повышение пропускной способности стеганографического встраивания и усложнение обнаружения факта встраивания методами стегоанализа. В способе встраивания информации в цветное изображение, заключающемся в замене малозначимых битов цифрового сигнала контейнера битами конфиденциальной информации, выбранный контейнер цифрового изображения разделяют на квадратные блоки пикселей определенного размера, вычисляют значения пикселей в квадратных блоках, размер квадратных блоков выбирается исходя из детальности сокрытия, затем в каждом квадратном блоке вычисляют модуль детерминанта, ранжируют полученные значения модулей детерминантов квадратных блоков, производят встраивание информации в биты квадратных блоков с ненулевым значением модуля детерминанта.

Способ формирования М-последовательностей для генерации сигнально-кодовых конструкций

Изобретение относится к электронно-вычислительной технике. Техническим результатом является обеспечение более низкого уровня боковых лепестков апериодической автокорреляционной функции, чем у аналогичной АКФ канонических М-последовательностей, при этом ВКФ этих последовательностей носит равномерный характер, что обеспечивает выделение модулированных зондирующих сигналов в общем радиолокационном канале при реализации режимов многопозиционных бортовых систем. Технический результат достигается тем, что предлагаемый способ реализует поиск М-последовательностей за счет введения новых значений для каждой из кодовых структур, генерируемой в рамках группы полиномов одного порядка, что позволяет однозначно при приеме в общем радиолокационном канале идентифицировать модулированные этой новой последовательностью сигналы, при одновременном их излучении с N позиций многопозиционной системы бортовых РЛС, разнесенных в пространстве и объединенных во взаимодействующую группу. 1 ил.

СПОСОБ ПОМЕХОУСТОЙЧИВОЙ ПЕРЕДАЧИ ИНФОРМАЦИИ В КОРОТКОВОЛНОВЫХ СИСТЕМАХ СВЯЗИ

Изобретение относится к системам телекоммуникации. Технический результат состоит в повышении показателей помехозащищенности без введения структурной избыточности и в обнаружении ошибок. Для этого предложен способ помехоустойчивой передачи информации, при котором исходную последовательность бит подвергают операции рандомизации, после чего поток бит перекодируют в замещающий сжатый помехоустойчивый троичный код и обеспечивают при их приеме контроль целостности потока, затем передачу потока осуществляют по радиоканалам параллельного радиомодема, на приемной стороне осуществляют фазовую демодуляцию, осуществляют контроль ошибок на основе сравнений контрольного троичного символа, переданного по выделенному радиоканалу, и восстановленной его копии, при их различии используют результаты текущего контроля энергетики принятых двух контролируемых символов, ошибку исправляют в том радиоканале, в котором отношение сигнал/помеха было наименьшим, устраняют избыточность, в результате чего формируют копии ...

VORRICHTUNG ZUM DEKODIEREN EINES BCH KODIERTEN SIGNALS ZUM KORRIGIEREN EINES ZUSAMMENGESETZTEN FEHLERS

Verfahren und Vorrichtung zur Fehlerverdeckung in digitalen Übertragungssystemen

Vorrichtung und Verfahren zum Durchführen einer Codierung und Ratenabstimmung in einem CDMA-Mobilkommunikationssystem

Ein Sender führt gleichzeitig eine Kanalcodierung und eine Ratenabstimmung in einem CDMA-Mobilkommunikationssystem durch. Der Sender codiert Eingabebits zu codierten Bits mit einer vorgegebenen übergeordneten Coderate und führt eine Abschneidung auf den codierten Bits durch, um die Anzahl der codierten Bits an eine vorbestimmte Coderate anzupassen. Danach führt der Sender gleichzeitig eine Ratenabstimmung zum Wiederholen oder Abschneiden der codierten Bits durch, um die Anzahl der codierten Bits an die Anzahl der über einen Funkkanal übertragenen Bits anzupassen.

DIGITALES UEBERTRAGUNGSSYSTEM MIT EINEM FEHLERKORREKTURKODER UND DEKODER UND EINEM VERWUERFLER/ENTWUERFLER.

Verfahren und Anordnung zum Decodieren eines Codesymbolblocks, der zwei Arten von Codewörtern enthält, die durch je einen maximalabstandsseparierbaren Code geschützt sind

VERFAHREN ZUR UEBERTRAGUNG UND AUFZEICHNUNG VON DATEN.

Iterative Demodulation und Dekodierungeines Mehrpegel-Signals

VERFAHREN, SYSTEM, SENDER UND EMPFÄNGER ZUR ÜBERTRAGUNG VON DATEN

EFFIZIENTE NORMALISIERUNG VOM TRELLISZUSTANDSMETRISCHEM WERT

AUFZEICHNUNGSFORMAT FÜR DIGITALEN DATENSPEICHER

Decoder für teletextähnliche Signale

Datenempfänger und Empfangsverfahren für punktierte, faltungskodierte Daten

Maximum transition run length code

Data decoder and method of recovering data

Improvements in or relating to electron discharge apparatus

... 663,838. Cathode-ray tubes. WESTERN ELECTRIC CO., Inc. Dec. 12, 1947 [Dec. 13, 1946], No. 32804/47. Addition to 637,820 and 663,837. Class 39 (i). [Also in Groups XXXV and XL (c)] In a signalling system as claimed in the parent Specification in which the amplitude of a complex wave is sampled at recurrent intervals, an electron beam of a cathode-ray tube is deflected in. one direction by plates 20a, Fig. 1, to an extent in accordance with the amplitude of each sample to select a path and is swept along that path by a suitable sweep circuit, and a coding element 26 comprising a plate with rows of apertures formed therein produces pulses at the target 27 representing by a permutation code the sampled signal wave amplitude, a grid electrode 25 with a secondary emission coefficient of greater than unity is arranged in front of the coding element 26, and electrode 24, which collects the secondaries, is connected by a feed-back path comprising an amplifier to the deflecting plates 20a so that ...

Apparatus for measuring bit error ratio by using a viterbi decoder

AN IMPROVED INPUT CIRCUIT FOR A DIGITAL PHASE LOCKED LOOP

Decoding system

Binary data error correction using hint signal

An error detection and correction method and apparatus is described which permits the correction of double errors using a (15, 11) Hamming code and a parity bit. The Hamming code and parity bit allows the detection of double errors. A modulated waveform carrying the binary data is examined for anomalies such as noise pulses. A hint signal is generated based on the anomalies which points to a suspect bit. The state of this bit is changed to correct for double errors. ...

Apparatus for measuring bit error ratio by using a viterbi decoder

Error prevention method for multimedia

An error prevention method for multimedia improves data recovery and channel throughput in channels which cause a random error and a burst error by using a rate compatible punctured convolutional code (RCPC) and an automatic retransmission on request (ARQ). In a process of decoding a plurality of packets of given information, the error prevention method includes the steps of a) decoding one of the plurality of packets, b) decoding another packet when an error occurs during the decoding in step a), c) decoding a combination of the packets from steps a) and b) or a third packet when an error occurs in step b), and d) repeating step c) until the decoding error no longer occurs. The error prevention method has the characteristics of both Type-1 and Type-2 ARQ methods. Therefore, one can obtain constant channel throughput in the burst error containing channel, the random error containing channel, and a channel wherein the two error patterns coexist simultaneously.

full-rank error correction coder using weighted non-binary repeat accumulate and space-time coding

An apparatus and method for weighted non-binary Repeat Accumulate RA coding and space-time coding are disclosed. Transmission data is divided in the units of frames each having mN bits, and each frame is further segmented into N blocks, each block containing m bits. The N blocks are converted to N non-binary GF(2m) elements. These N non-binary symbols are repeated, using a repeater 202, by a repetition factor r. The rN symbols are multiplied by weighting factors, using a weighter 204, being GF(2m) elements other than zero. The rN weighted symbols are interleaved, using an interleaver 206, and accumulated by an accumulator 212. The rN accumulated symbols are transmitted to a receiver, or each of the rN accumulated symbols is demapped to m bits prior to transmission. Therefore, information can be transmitted reliably in a wireless communication system. The method achieves unity data rate and maximum antenna diversity by providing a full-rank error correction coder using ...

A TELETEXT DECODER OPERATING ON PIXEL WORDS

Convolutional interleaver and method for generating address

A convolutional interleaver for interleaving a data stream composed of N number of data with predetermined interleaving level B to randomize the data stream for burst error correction, comprises: an input buffer 21; a memory 22; an address generating unit 23; an output buffer 24; and a controller 25. In a method for generating an address of the memory, a basic memory (23-1) of which the number of vertical end is B-1 and horizontal length is (B-1)xM cell is transformed to an intermediate memory (23-2) of which the number of vertical end is B-1 and horizontal length is (B/2)xM cell, and a physical address (23-3) for accessing the intermediate memory is generated. The physical address is maintained during one clock period, while the memory reads the previous data stored in the memory position corresponding to the physical address during the first half period of the clock and stores the current input data in the same memory position corresponding to the physical address during the latter half ...

Communication system

Apparatus and method for generating codes in a communication system

Serial concatenated decoding with optional sub-optimal inner decoding

In a serial concatenated decoder 10 of eg. TV data blocks, demodulated data 14 is first decoded sub-optimally by inner decoder 26 to reduce computation and then by a second, outer decoder 34 and the number of error corrections monitored. If failure is indicated, a feedback signal from the outer decoder causes data to be reloaded from the buffer 14 and redecoded optimally by a different inner decoder 22. The inner decoders may be Viterbi, log-MAP turbo or LDPC decoders in which the optimal decoder has more Viterbi states or LDPC iterations than its sub-optimal counterpart, while the outer decoder is a Reed Solomon decoder. More than two inner decoders may be selected from.

Encoding/decoding apparatus and method in a CDMA mobile communication system

Signal decoding methods and apparatus

Data receiver

A DECODING SYSTEM FOR DISTINGUISHING DIFFERENT TYPES OF CONVOLUTIONALLY ENCODED SIGNALS

CODING OF MULTI-WORD INFORMATION WITH WORD ORIENTATED NESTING

ANORDNUNG ZUM UEBERTRAGEN VON DATEN MIT FEHLERKORREKTUR, DAMIT ERZEUGTER DATENTRAEGER UND DECODIERVORRICHTUNG ZUR VERWENDUNG BEI EINER DERARTIGEN ANORDNUNG

RATE ADJUSTMENT AND CHANNEL NESTING FOR A COMMUNICATION SYSTEM

CODEENTWURFSUND IMPLEMENTATION IMPROVEMENTS FOR LITTLE DENSITY PARITY VERIFICATION CODE FOR CHANNELS WITH SEVERAL ENTRANCES AND SEVERAL EXITS

SOFT DECISION IMPROVEMENT

ERROR HIDING FOR AN AUDIO SIGNAL

ACCEPTANCE/REJECTING CODE WORDS OF A REPETITION CODE AS A FUNCTION OF THE NUMBER OF ACCOMPLISHED CORRECTIONS

RATE-COMPATIBLE LOW DENSITY PARITY CHECK (LDPC) CODE

PROCEDURE AND DEVICE FOR DETECTING THE PRESENCE OF A SIGNAL IN A FREQUENCY BAND USING NOT HOMOGENEOUS SCANNING

PROCEDURE FOR THE RATE ADJUSTMENT FOR THE SUPPORT OF INKREMENTELLER REDUNDANCY WITH FLEXIBLE LAYER UNITY

PROCEDURE AND EQUIPMENT FOR DOTTING OF CODE SYMBOLS IN A COMMUNICATION SYSTEM

PROCEDURE FOR THE PRODUCTION OF PARITY SYMBOLS AND SWITCHING CONFIGURATION FOR THE EXECUTION OF THE PROCEDURE.

PROCEDURE AND ARRANGEMENT FOR THE ERROR CORRECTION OF DIGITAL ONES OF AUDIO SIGNALS.

HIGH-SPEED (CARRIAGE RETURN CHARACTER) CHECK SUM GENERATOR AND TEST SYSTEM WITH PROGRAMMABLE ARCHITECTURE

COMBINED CHANNEL - AND ENTROPY DECODING

PROCEDURE AND DEVICE FOR THE ALLOCATION OF FOLDING-CODED BITS TO SYMBOLS BEFORE THEIR MODULATION

REED SOLOMON ERROR CORRECTION WITH EUCLID ALGORITHM

GENERALIZED FOLDING EN AND - ENTSCHACHTELER

CORRECTION PROCEDURE FOR MISSING DATA AND CIRCUIT FOR IT

LISTENAUSGABEN VITERBI DECODING WITH (CARRIAGE RETURN CHARACTER) OUTER CODE FOR MULTI-RATE SIGNAL

DATA TRANSMISSION METHOD FOR A DISC

BYTE WRITE ERROR CODE METHOD AND APPARATUS

Efficient automatic repeat request methods and apparatus

Packet retransmission and memory sharing

METHOD FOR RATE MATCHING TO SUPPORT INCREMENTAL REDUNDANCY WITH FLEXIBLE LAYER ONE

TRELLIS-BASED RECEIVER

NOISE-ADAPTIVE DECODING

Optimized code table signaling

In various embodiments, computer-implemented methods, systems, and non-transitory computer-readable memory media are disclosed. In one aspect, the computer-implemented method comprises receiving, by a processor, a digital bit stream; transforming, by the processor, the digital bit stream to an encoded digital bit stream, wherein the encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof; and providing, by the processor, the encoded digital bit stream to a transmission system for transmission.

Method and apparatus for interleaving a data block

Method and apparatus for error concealment of encoded audio data

Transmitter and repetition method thereof

A transmitter is provided. The transmitter includes: a low density parity check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits; a repeater configured to select at least a part of bits constituting the LDPC codeword and add the selected bits after the input bits; and a puncturer configured to puncture at least a part of the parity bits.

Processing of speech coder parameters in the receiver of a communications system

Decoding device and method and signal transmission system

Embodiments of the present invention disclose a decoding device. By performing processing in a case in which a value of an updated code element exceeds a code element quantization range in a process of updating a code word of an LDPC code, the decoding device selectively abandons an update in the case in which the updated code element exceeds the code element quantization range, which prevents the decoding device from directly quantizing an updated code word that exceeds the code element quantization range, and improves an error correction capability of the decoding device in a decoding process. Decoding device 600 Acquiring unit 602 Storage module Variable node processing unit 6042 Check node processing unit 6044 Processing unit 604 Determining unit 606 ...

A method and an arrangement for making fixed length codes

Decoding device and decoding method

ARRAYED DISK DRIVE SYSTEM AND METHOD

Soft decision output decoder for decoding convolutionally encoded codewords

DIGITAL COMMUNICATION SYSTEM INCLUDING AN ERROR CORRECTING ENCODER/DECODER AND A SCRAMBLER/DESCRAMBLER

MULTI-VALUE SIGNAL MONITOR CIRCUIT

... 25307-140 A multi-value signal monitor circuit in a data transmission system which transmits a plurality of data after conversion into a multi-value signal and obtains original data of plural bits through analog-to-digital conversion of the received multi-value signal, wherein data is decided further minutely than the number of bits of data by a plurality bits on the occasion of analog-to-digital conversion in the receiving side and focusing degree of the received signal to the quantization level is detected by utilizing said extra bits, thereby an error rate is monitored quickly and accurately with simplified circuits.

VITERBI DECODER WITH REDUCED NUMBER OF DATA MOVE OPERATIONS

Disclosed is a modem including a transmitter having a convolutional encoder for transforming each time unit digital data into an expanded bit sequence having symbol-selecting bits and subset-selecting bits, the transmitter further providing modulation of a carrier signal and a receiver wherein a Viterbi decoder determines the maximum likelihood path through a trellis from a plurality of surviving paths using a wraparound memory wherein in each addressable location indexed to a current state of a surviving path there is stored a previous state of that surviving path.

APPARATUS AND METHOD FOR A DATA TRANSMISSION APPARATUS TO RECOGNIZE WHETHER OR NOT A REMOTE DATA TRANSMISSION APPARATUS HAS AN ERROR CONTROL FUNCTION

... 27598-60 The present invention provides a data transmission apparatus capable of data transmissions either with error control and/or without error control. The data transmission apparatus is operable such that a remote transmission apparatus recognizes whether or not the data transmission apparatus effects data transmission with the use of error control based upon an intermittent carrier sent from the data transmission apparatus. Additionally, the data transmission apparatus recognizes, based upon the existence of the interruption of a carrier signal sent from a remote data transmission apparatus, whether or not the remote data transmission apparatus has an error control function.

CIRCUIT AND METHOD FOR RAPID CHECKING OF ERROR CORRECTION CODES USING CYCLIC REDUNDANCY CHECK

A circuit and method uses CRC to check errors detected and corrected by an ECC unit (120) when reading data from a disk (116) in a disk drive (110). A CRC unit (118) monitors both the sector bytes read from the disk platter (114) and the error corrections made by the ECC unit (120) to the data and CRC bytes. The CRC unit (118) uses this information to determine whether the ECC- corrected data bytes stored in a buffer unit (122) were properly corrected. The CRC unit (118) reads data bytes and CRC bytes from the disk (116) simultaneously with the ECC unit (120). The CRC unit (118) begins generating a residue to detect errors in the data at approximately the same time the ECC unit (120) begins generating a residue to detect errors in the sector. The CRC unit (118) does not wait for the ECC unit (120) to finish and transfer the ECC error corrections into a buffer. The CRC error check is completed before any data is transferred to the host computer (112). In particular, the CRC unit (118) approves ...

METHODS OF CODING AND DECODING INFORMATION

The invention relates to information coding/decoding. As a result, the effectiveness of antinoise coding and decoding is enhanced due to the increase in the volume of transmitted and received information and due to the decrease in the number of elements used for coding/ decoding. During the coding method implementation a data array to be coded is divided into logically complete chunks, each of which is associated with at least one element of the molecular genetic system used for the coding; the set of elements in the system is supplemented by relevant indexing information consisting of i data bits; each code combination of data bits is supplemented by a combination of k check bits which is defined depending on i data bits combination; each piece of i+k bit data in binary form is written as a multiplet of the molecular genetic system consisting of the n number of nitrogenous bases or corresponding amino acids. The information to be coded is recorded together with a) the value n, whereas ...

DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA

A digital broadcasting system and method of processing data are disclosed . The digital broadcasting system includes a transmitting system and a recei ving system. The transmitting system comprises a distributed transmission ad apter and a plurality of transmitters each being operated as a slave of the distributed transmission adapter, and each sharing the same frequency and tr ansmitting the same signals.

PROCESSOR, METHOD AND COMPUTER PROGRAM FOR PROCESSING AN AUDIO SIGNAL USING TRUNCATED ANALYSIS OR SYNTHESIS WINDOW OVERLAP PORTIONS

A processor for processing an audio signal (200), comprises: an analyzer (202) for deriving a window control signal (204) from the audio signal (200) indicating a change from a first asymmetric window (1400) to a second window (1402), or indicating a change from a third window (1450) to a fourth asymmetric window (1452), wherein the second window (1402) is shorter than the first window (1400), or wherein the third window (1450) is shorter than the fourth window (1452); a window constructor (206) for constructing the second window (1402) using a first overlap portion (800) of the first asymmetric window (1400), wherein the window constructor (206) is configured to determine a first overlap portion (1000) of the second window (1402) using a truncated first overlap portion of the first asymmetric window, or wherein the window constructor is configured to calculate a second overlap portion (1330) of the third window (1450) using a truncated second overlap portion (814) of the fourth asymmetric ...

MOVING PICTURE CODING AND DECODING USING CONTEXT ADAPTIVE BINARY ARITHMETIC CODING WITH FIXED PROBABILITY FOR SOME SAMPLE ADAPTIVE OFFSET PARAMETERS

A moving picture coding method includes: performing context adaptive binary arithmetic coding in which a variable probability value is used, on first information among multiple types of sample adaptive offset (SAO) information used for SAO that is a process of assigning an offset value to a pixel value of a pixel included in an image generated by coding the input image (S11); and continuously performing bypass arithmetic coding in which a fixed probability value is used, on second information and third information among the multiple types of the SAO information (S12), wherein the coded second and third information are placed after the coded first information in the bit stream.

HYBRID ENCODING OF DATA TRANSMISSIONS IN A SECURITY SYSTEM

APPARATUS AND METHOD FOR LAYERED DECODING IN A COMMUNICATION SYSTEM USING LOW-DENSITY PARTIY-CHECK CODES

A channel decoding apparatus and method in a communication system using Low-Density Parity-Check (LDPC) codes are provided in which an encoded signal is received from a transmitter and decoded using a parity-check matrix. At least one of input orders and output orders of the parity-check matrix are determined so that same values are not overlapped in a column direction between the at least one of the input orders and the output orders.

Method and apparatus for encoding feedback signal

A method and apparatus for encoding feedback signal is provided. The method includes: encoding feedback signals of three carriers to output a bit sequence; and transmitting the bit sequence on a High Speed-Dedicated Physical Control Channel (HS-DPCCH). The encoding the feedback signals of the three carriers may specifically include: mapping the feedback signals of the three carriers into a codeword, in which the codeword can be selected from a codebook, and codewords in the codebook satisfy a particular code distance relationship. The method for jointly encoding feedback signals of three carriers in a Ternary Cell (TC) mode is provided. Feedback signals are transmitted over a single code channel. Therefore, power overhead is reduced, and system performance is improved.

Modulation method and device implementing a differential modulation, corresponding demodulation method and device, signal and computer software products

A method and apparatus are provided for modulating a binary source sequence including of a plurality of source words to generate modulated symbols. The method implements error-correction encoding of the plurality of source words, implementing one or more encoding modules, each implementing a separate error-correction code to generate a plurality of code words, the source words being encoded in series. The code words are interlaced to generate an interlaced sequence. The interlaced sequence is differentially modulated to generate modulated symbols. Each code word is broken down into at least one group with a number of bits equal to the base-2 logarithm of a number of states of a modulation implemented by the step of differentially modulating. The interlacing step distributes the groups such that two adjacent groups in the interlaced sequence belong to separate code words.

Hearing aid with audio codec and method

A hearing aid comprising a time domain codec. The codec comprises a decoder adapted to generate a decoded output signal based on an input quantization index and an encoder for generating an output quantization index based on an input signal, said encoder comprising said decoder and a predictor receiving an excitation signal derived from said decoder output signal and outputting a prediction signal. The output quantization index is determined by repeated decoding of the quantization indices in order to minimize the error between the input signal and the prediction signal, and the predictor uses a recursive autocorrelation estimate for the error minimization. The invention further provides a method of encoding an audio signal.

Decoding method and device for concatenated code

Disclosed are a decoding method and device for concatenated code, for the decoding of concatenated code composed of low density parity code (LDPC) and Reed-Solomon (RS) code. The method includes: carrying out LDPC soft decision iterative decoding on bit de-interleaved data flow, and carrying out check decision on LDPC codeword obtained from decoding by using a check matrix; carrying out de-byte-interleave on an information bit of the LDPC codeword obtained from decoding and converting check information of the LDPC codeword into puncturing information of RS codeword; selecting a decoding mode according to the puncturing information of the RS codeword to carry out RS decoding. By way of the solution of the present invention, the RS decoding performance can be improved without increasing the computation complexity, thus greatly improving the receiving performance of the CMMB terminal as compared to the conventional method.

Network quality as a service

A system is provided for improving the performance of an access network for coupling user devices to an application server. The system includes a user device coupled to an intermediate server via the access network. The user device has a processor adapted to encode data using a network performance enhancing coding (NPEC), and to transmit the encoded data via the access network to the intermediate server. The intermediate server is adapted to receive the encoded data and has a processor adapted to decode the encoded data using the NPEC, and to transmit the decoded data to the application server.

APPARATUS AND METHOD FOR TRANSMITTING/RECEIVING DATA IN COMMUNICATION SYSTEM

An apparatus and method for generating a parity bit sequence to be transmitted or received over a plurality of frames in a communication system are provided. The method includes puncturing a first parity bit sequence by encoding, the first parity bit sequence with a first puncturing pattern; outputting, as a basic parity bit sequence, non-punctured parity bits that are remaining after the puncturing of the first parity bit sequence with the first puncturing pattern; puncturing a second parity bit sequence that is punctured by puncturing of the first parity bit sequence with the first puncturing pattern, the second parity bit sequence with a second puncturing pattern; and outputting, as an additional parity bit sequence, non-punctured parity bits that are remaining after the puncturing of the second parity bit sequence with the second puncturing pattern. 1. A method for generating a parity bit sequence to be transmitted over a plurality of frames in a transmission device of a communication system , comprising:puncturing a first parity bit sequence by encoding, the first parity bit sequence with a first puncturing pattern;outputting, as a basic parity bit sequence, non-punctured parity bits that are remaining after the puncturing of the first parity bit sequence with the first puncturing pattern;puncturing a second parity bit sequence that is punctured by puncturing of the first parity bit sequence with the first puncturing pattern, the second parity bit sequence with a second puncturing pattern; andoutputting, as an additional parity bit sequence, non-punctured parity bits that are remaining after the puncturing of the second parity bit sequence with the second puncturing pattern.2. The method of claim 1 , wherein the second parity bit sequence is generated by encoding the first parity bit sequence.3. The method of claim 1 , wherein each of the first and second puncturing patterns is a masking pattern.4. The method of claim 3 , further comprising claim 3 , when ...

Apparatus and Method for Reconstructing a Bit Sequence with Preliminary Correction

A method for reconstructing a physically uncloneable function (PUF) A for use in an electronic device is provided. The method includes generating a potentially erroneous PUF Aand performing a preliminary correction of the potentially erroneous PUF Aby means of a stored correction vector Delta, to obtain a preliminarily corrected PUF B. The PUF A is reconstructed from the preliminarily corrected PUF Bby means of an error correction algorithm. A corresponding apparatus is also provided. 1. A method for reconstructing a physically uncloneable function (PUF) A for use in an electronic device , the method comprising:{'sub': 't', 'generating a potentially erroneous PUF A;'}{'sub': t', 't-1', 't, 'performing a preliminary correction of the potentially erroneous PUF Aby means of a stored correction vector Delta, to obtain a preliminarily corrected PUF B; and'}{'sub': 't', 'reconstructing the PUF A from the preliminarily corrected PUF Bby means of an error correction algorithm.'}2. The method as claimed in claim 1 , wherein reconstructing the PUF A from the preliminarily corrected PUF Bby means of an error correction algorithm comprises:{'sub': t', 't, 'applying the error correction algorithm to the preliminarily corrected PUF Bto obtain an error vector e; and'}{'sub': t', 't, 'XORing the preliminarily corrected PUF Band the error vector e.'}3. The method as claimed in claim 2 , wherein the error correction algorithm is an ECC algorithm.4. The method as claimed in claim 1 , wherein a current correction vector Deltais calculated by XORing the stored correction vector Deltaand the error vector e.5. The method as claimed in claim 4 , further comprising storing the current correction vector Deltaas a new correction vector in an error register claim 4 , the new correction vector being used as the correction vector Deltaduring a subsequent PUF reconstruction.6. The method as claimed in claim 1 , wherein the length of the potentially erroneous PUF Ais in a range from 64 bits to ...

PERFORMING A CYCLIC REDUNDANCY CHECKSUM OPERATION RESPONSIVE TO A USER-LEVEL INSTRUCTION

In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed. 1. A processor comprising: a first 32-bit register to store a first operand;', 'a second 32-bit register to store a second operand;', 'a first 64-bit register to store a third operand; and', 'a second 64-bit register to store a fourth operand;', a first execution unit coupled to the first and the second 32-bit registers to perform a first XOR operation on at least one bit of the first and the second operands and to store a result of the first XOR operation in a first destination register responsive to a first instruction of the ISA; and', 'a second execution unit coupled to the first and the second 64-bit registers to perform a second XOR operation on at least one bit of the third and the fourth operands and to store a result of the second XOR operation in a second destination register responsive to a second instruction of the ISA; and, 'a plurality of execution units to perform exclusive-OR (XOR) operations on data of a configurable size responsive to instructions of an instruction set architecture (ISA) for the processor, the plurality of execution units including], 'a set of registers, includinga memory interface logic to provide access to an external memory.2. The processor of claim 1 , wherein the first and the second execution units are to perform the first and the second XOR operations in the same number of cycles.3. The processor of claim 1 , wherein the first destination register comprises the first 32-bit register.4. The processor of claim 1 , wherein the first destination register comprises the second 32-bit register.5. The processor of claim 1 , ...

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

METHOD AND APPARATUS WITH ERROR CORRECTION FOR DIMMABLE VISIBLE LIGHT COMMUNICATION

An apparatus and method using error correcting for visible light communication are provided. The error correction includes generating an encoded message from an original message by using a predetermined coding method, puncturing the encoded message based on a determined dimming value or rate, and/or puncturing rate, generating a scrambled message by scrambling the punctured message, and providing the scrambled message to a visible light source. 1. A visible light communication method , the method comprising:encoding an information message using a predetermined error correction coding scheme that has a bit length N different from a bit length of the information message;puncturing the encoded message based on a desired dimming rate and a set pattern, with the punctured message including non-punctured bits and punctured bits;generating a scrambled message by scrambling the non-punctured bits of the punctured message and combining the scrambled non-punctured bits with the punctured bits of the punctured message; andproviding the scrambled message to a visible light source.2. The method of claim 1 , wherein the predetermined error correction coding minimizes a generation of errors during the puncturing of the encoded message.3. The method of claim 2 , wherein the predetermined error correction coding method is trellis-based turbo coding.4. The method of claim 1 , wherein the scrambling of the non-punctured bits equalizes a resultant total number of binary ones and a resultant total number of binary zeros in the scrambled non-punctured bits.5. The method of claim 1 , wherein the puncturing of the encoded message includes setting all of the punctured bits to binary zero.6. The method of claim 1 , wherein the punctured message and the scrambled message have respective bit lengths of N.7. The method of claim 6 , wherein a total number of non-punctured bits is based upon the desired dimming rate and is less than N claim 6 , and the generating of the scrambled message includes ...

Moving picture coding method, moving picture decoding method, moving picture coding apparatus, moving picture decoding apparatus, and moving picture coding and decoding apparatus

A moving picture coding method includes: performing context adaptive binary arithmetic coding in which a variable probability value is used, on first information among multiple types of sample adaptive offset (SAO) information used for SAO that is a process of assigning an offset value to a pixel value of a pixel included in an image generated by coding the input image; and continuously performing bypass arithmetic coding in which a fixed probability value is used, on second information and third information among the multiple types of the SAO information, wherein the coded second and third information are placed after the coded first information in the bit stream.

Rate Matching And Channel Interleaving For A Communications System

A method, an apparatus, and a computer program product for matching a rate of data bits to a desired rate by deletion of redundant data bits or repetition of data bits are disclosed. In a non-interleaved matrix of the data bits, a pattern of bits to be deleted or repeated to provide the desired data rate is determined. An address of each bit in the pattern in a manner inverse to the interleaving process is decoded to produce a respective address of the bit in the matrix. The respective bit in the interleaved data bits is deleted or repeated depending upon the respective address. The address decoding is performed in the same manner as a coding of addresses for producing the interleaved data bits from the non-interleaved matrix of the data bits.

Method and Apparatus for Detecting the Presence of a Signal in a Frequency Band Using Non-Uniform Sampling

A method and apparatus for detecting the presence of a signal in a frequency band using non-uniform sampling includes an analog to digital converter (ADC) ( 110 ) for sampling an analog input signal ( 105 ) to create discrete signal samples ( 115 ), an ADC exciter ( 120 ) for exciting the ADC to sample at non-uniform time periods, a digital filter ( 130 ) for converting the discrete signal samples into an energy versus frequency spectrum ( 300 ), and an energy comparator ( 140 ) coupled to an output of the digital filter. The energy comparator ( 140 ) detects the presence of any frequency bands exceeding an energy setpoint.

ENCODER, TRANSMITTING APPARATUS, CODING METHOD AND TRANSMISSION METHOD

Disclosed are an encoder, a transmitting device, a coding method and a transmission method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block coding is used. A puncture pattern setting unit searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code. 1. An encoder comprising:{'sub': 'b', 'a coding section that generates coded sequence s that is made up of z×nbits and satisfies equation 1-1, equation 1-2 and equation 1-3 for information bit sequence u; and'}{'sub': 'b', 'a selecting section that selects either of a puncturing pattern for removing a column group that corresponds to consecutive y bits and a puncturing pattern for not removing a column group that corresponds to the consecutive y bits as a puncturing pattern having a unit of divisor y of a number of columns z for each y bits from a first bit to a z×n-th bit,'}{'sub': 'b', 'a puncturing section that determines bits to be removed for each y bits based on the selected puncturing pattern, removes the bits determined to be removed from the z×nbits configuring the coded sequence s to form a transmission information bit sequence, and outputs the transmission information bit sequence, wherein'}the selecting section selects a column group from a plurality of column groups having column weight of 3 in a matrix that corresponds to the information bit sequence u, the matrix includes a plurality of column groups having column weight of equal to or greater than 3, and the matrix is included in a parity check matrix H of an low ...

Disparity reduction for high speed serial links

System, computer program product, and computer-implemented method to improve a running disparity of an encoded bit stream in a distributed network switch, the distributed network switch comprising a plurality of switch modules including a first switch module, by receiving, at the first switch module, a raw data stream comprising a plurality of bits, receiving a bit sequence, encoding at least a first bit of the raw data stream using a corresponding at least a first bit of the bit sequence, transmitting the encoded first bit, inverting the first bit of the bit sequence, and encoding a second bit of the raw data stream using the inverted first bit.

PACKET RETRANSMISSION

Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like. 1105.-. (canceled)106. A method of packet retransmission comprising:transmitting or receiving, using a transceiver, a plurality of packets,wherein at least one first packet of the plurality of packets is associated with a first delay requirement,wherein at least one second packet of the plurality of packets is associated with a second delay requirement, andwherein the second delay requirement is lower than the first delay requirement; andtransmitting or receiving, using the transceiver, a message comprising acknowledgement (ACK) information of the at least one first packet,wherein the ACK information is transmitted or received a plurality of times such that the ACK information is transmitted or received in a first DMT symbol and the ACK information is also transmitted or received in a second DMT symbol.107. The method of claim 106 , further comprising passing the at least one second packet when it is received without error to a higher layer without waiting for receipt of other retransmitted packets.108. The method of claim 106 , further comprising passing the at least one first packet when it is received without error to a higher layer without waiting for receipt of other retransmitted packets.109. The method of claim 106 , further comprising waiting for the receipt of other retransmitted packets before passing the at least one first packet a higher layer when they are ...

Method and System for Accelerated Stream Processing

Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams. 1. A system for making a reconfigurable logic device available in a network for loading a processing pipeline thereon for the reconfigurable logic device to apply parallelism when processing streaming data , the streaming data comprising data arranged in a plurality of fields , the system comprising:a reconfigurable logic device that is addressable within a network, the reconfigurable logic device arranged for configuration in response to a command over the network so that a processing pipeline for receiving and processing streaming data is loadable thereon;the loadable processing pipeline including a plurality of parallel paths, each of a plurality of the parallel paths including pipelined logic for performing different processing operations on the streaming data, and wherein each of a plurality of the parallel paths includes field selection logic that filters which fields of the streaming data that downstream pipelined logic in that parallel path will process, wherein a plurality of the parallel paths include field selection logic that filter for different fields of the streaming ...

METHOD AND APPARATUS FOR DATA PROCESSING WITH STRUCTURED LDPC CODES

The embodiments of the present disclosure provide a method and an apparatus for data processing with structured LDPC codes. The method includes: obtaining a code block size for structured LDPC coding; determining a coding expansion factor z based on at least one of the code block size, a parameter kb of a basic check matrix, a positive integer value p or the basic check matrix having mb rows and nb columns; and encoding a data sequence to be encoded, or decoding a data sequence to be decoded, based on the basic check matrix and the coding expansion factor. The present disclosure is capable of solving the problem in the related art associated with low flexibility in data processing with LDPC coding and improving the flexibility in data processing with LDPC coding. 1. A method for wireless communication , comprising:determining a code block size for Low Density Parity Check (LDPC) coding;determining a coding expansion factor Z from a set of coding expansion factors based on the code block size and a parameter kb associated with a basic check matrix, wherein the parameter kb is an integer larger than or equal to four and smaller than or equal to 64, and wherein the coding expansion factor Z is equal to a positive integer power of two minus one or a product of a positive integer power of two and a prime number; andencoding a data sequence based on the basic check matrix and the coding expansion factor Z.2. The method of claim 1 , wherein at least one value in the set of coding expansion factors is equal to a product of a positive integer power of two and a prime number.3. The method of claim 2 , wherein the prime number comprises one of: 3 claim 2 , 5 claim 2 , 7 claim 2 , 11 claim 2 , or 13.4. The method of claim 1 , wherein at least one value in the set of coding expansion factors is equal to a product of a positive integer power of two and an odd number.5. The method of claim 1 , wherein the set of coding expansion factors includes at least 6 claim 1 , 12 claim 1 , ...

COMMUNICATION METHOD AND APPARATUS

Embodiments of this application provides a communication method in a wireless communication network. A communication device obtains an information bit sequence and obtain a first sequence, wherein the first sequence comprises sequence numbers of N channels ordered in ascending order of channel reliability, wherein N is 1024 and wherein a channel whose sequence number is 0, a channel whose sequence number is 1, and a channel whose sequence number is 2 are ordered in ascending order of channel reliability; then polar encode the information bits based on the first sequence to obtain an encoded bit sequence and output the encoded bit sequence. 1. A method for polar coding , performed by a device in a wireless communication network , comprising:obtaining an information bit sequence comprising K information bits;polar encoding the information bit sequence based on a first sequence to obtain an encoded bit sequence, wherein the first sequence comprises sequence numbers of 1024 channels ordered in ascending order of channel reliability, wherein a channel whose sequence number is 0 is ranked first in channel reliability in the ascending order of channel reliability and has the least channel reliability among the 1024 channels, a channel whose sequence number is 1 is ranked second in channel reliability in the ascending order of channel reliability, and a channel whose sequence number is 2 is ranked third in channel reliability in the ascending order of channel reliability;rate matching the encoded bit sequence to obtain a rate-matched bit sequence; andoutputting the rate-matched bit sequence.2. The method according to claim 1 , wherein polar encoding the information bit sequence based on a first sequence to obtain an encoded bit sequence comprises:obtaining a second bit sequence according to the first sequence, wherein the second bit sequence has a length of N, and N>K;determining positions of the K information bits according to the second bit sequence; andpolar encoding the ...

LOW COMPLEXITY RATE MATCHING FOR POLAR CODES

Aspects of the disclosure provide polar code rate matching methods. A first method can include determining whether to puncture or shorten a mother polar code according to a mother code rate and/or a rate matched code rate, and selecting K positions in the sequence of N input bits for input of K information bits to a polar encoder according to an offline prepared index list ordered according to the reliabilities of respective synthesized channels. Frozen input bits caused by puncturing or shortening are skipped during the selection. A second method includes generating a mother polar code, rearranging code bits of the mother polar code to form a rearranged sequence that can be stored in a circular buffer, and performing, in a unified way, one of puncturing, shortening, or repetition on the rearranged sequence to obtain a rate matched code. 1. A method for polar code rate matching in a communication device , comprising:determining whether to puncture or shorten a mother polar code according to a mother code rate and/or a rate matched code rate in order to fit a to-be-transmitted code bits length M, the mother polar code including a sequence of N code bits to-be-generated from a polar encoder that encodes a sequence of N input bits to generate the mother polar code, each input bit corresponding to a synthesized channel having a reliability for transmitting the respective input bit over the synthesized channel, each input bit and respective synthesized channel corresponding to an index; andselecting K positions in the sequence of N input bits for input of K information bits to the polar encoder according to a predetermined index list that is ordered according to the reliabilities of the N synthesized channels, wherein the K positions correspond to K synthesize channels having the highest reliabilities among the N synthesized channels excluding synthesized channels of frozen input bits determined according to punctured code bits or shortened code bits.2. The method of ...

METHOD AND APPARATUS FOR CONVOLUTIONAL CODING TO SUPPORT MULTIPLEXING IN A WIDEBAND COMMUNICATIONS SYSTEM

An approach for encoding a physical layer (PL) header of a PL data frame is provided. The PL header comprises sixteen information bits u, (i=0, 1, 2, . . . , 15), and the encoding is based on a convolutional code, whereby, for each information bit, five associated parity bits P, (k=0, 1, 2, 3, 4) are generated, resulting in 80 codebits. The resulting 80 codebits are punctured to form a (16,77) codeword (c, c, c, . . . , c). The codebits of the (16,77) codeword are repeated to generate a (16,154) physical layer signaling codeword (c, c, c, c, c, c, . . . , c, c) for transmission of the PL data frame over a channel of a communications network. Further, for each information bit, each of the associated five parity bits is generated based on a parity bit generator, as follows: p=(u*g)⊕(s*g)⊕(S*g)⊕(S*g)⊕(S*g), where S=u, S=u, S=, S=u, and wherein generator polynomials for g=(g, g, g, g, g), are as follows: g=(1, 0, 1, 0, 1); g=(1, 0, 1, 1, 1) ; g=(1, 1, 0, 1, 1); g=(1, 1, 1, 1, 1); g=(1, 1, 0, 0, 1). 1. A method comprising:{'sub': i', 'i', 'i,k, 'encoding, by a processor of a device, a physical layer (PL) header of a PL data frame, wherein the PL header comprises sixteen information bits u, (i=0, 1, 2, . . . , 15), and the encoding is based on a convolutional code, whereby, for each information bit u, (i=0, 1, 2, . . . , 15), ten associated parity bits p, (k=0, 1, 2, . . . , 9) are generated, resulting in 160 codebits; and'}puncturing the resulting 160 codebits to form a (16,154) physical layer signaling (PLS) codeword for transmission of the PL data frame over a channel of a communications network;{'sub': i', 'i,k, 'claim-text': {'br': None, 'i': p', 'u', '*g', 'S', '*g', 'S', '*g', 'S', '*g', 'S', '*g, 'sub': i,k', 'i', 'k,0', '0', 'k,1', '1', 'k,2', '2', 'k,3', '3', 'k,4, '=()⊕()⊕()⊕()⊕(),'}, 'wherein, for each information bit u, (i=0, 1, 2, . . . , 15), each of the associated ten parity bits p, (k=0, 1, 2, . . . , 9) is generated based on a parity bit generator, as ...

Apparatus and method for sending and receiving broadcast signals

Disclosed herein is a broadcast signal receiver. The broadcast signal receiver according to an embodiment of the present invention includes a synchronization and demodulation module configured to perform detection and OFDM demodulation on a received broadcast signal, a frame parsing and deinterleaving module configured to parse and deinterleave the signal frame of the broadcast signal, a demapping and decoding module configured to convert the data of at least one Physical Layer Pipe (PLP) of the broadcast signal into a bit domain and to FEC-decode the PLP data, and an output processing module configured to receive the data of the at least one PLP and to output the received data in a data stream form.

METHOD FOR PERFORMING POLAR CODING AND APPARATUS THEREFOR

A method for performing polar encoding includes the steps of, if a length of a codeword is greater than 2and smaller than 2determining whether encoding is performed by a polar encoder of size 2or a polar encoder of size 2according to whether or not a length of the codeword is smaller than a prescribed value, and if the length of the codeword is smaller than the prescribed value, performing encoding by the polar encoder of the size 2. 1. A method for performing polar encoding , the method comprising:{'sup': x', 'x+1', 'x', 'x+1, 'when a length of a codeword is greater than 2and smaller than 2, determining whether encoding is performed by a polar encoder of size 2or a polar encoder of size 2according to whether or not the length of the codeword is smaller than a prescribed value; and'}{'sup': 'x', 'if the length of the codeword is smaller than the prescribed value, performing encoding by the polar encoder of the size 2.'}2. The method of claim 1 , further comprising:{'sup': 'x', 'generating an encoded bit sequence of size N by performing repetition on N−2bits when the length of the codeword corresponds to N.'}3. The method of claim 1 , further comprising:{'sup': 'x+1', 'performing encoding by the polar encoder of the size 2when the length of the codeword is greater than the prescribed value.'}4. The method of claim 3 , further comprising:{'sup': 'x+1', 'generating an encoded bit sequence of size N by performing puncturing on 2−N bits when the length of the codeword corresponds to N.'}5. The method of claim 2 , further comprising:performing interleaving by applying a bit-reversal pattern to the encoded bit sequence of the size N.6. The method of claim 4 , further comprising:performing interleaving by applying a bit-reversal pattern to the encoded bit sequence of the size N.7. The method of claim 1 , whether encoding is performed by a polar encoder of size 2is determined according whether a payload size of the codeword is smaller than a specific value.8. A communication ...

RATE CONVERTOR

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power. 1. A rate converter implemented in an audio processing circuit , the rate converter comprising:an input for receiving audio data sampled at an input sample rate;a sample index accumulator for determining a sample index for each output audio sample at an output sample rate different from the input sample rate;an error accumulator for determining and outputting an index error;a phase lock tracking loop for estimating a ratio between the input sample rate and the output sample rate;a gain value controller configured to adjust gain values during conversion between the first sample rate and the second sample rate; anda filter selector structured to select a filter from a plurality of filters for application to the audio data based on output of the gain value controller.2. The rate converter of claim 1 , in which each of the plurality of filters is configured to provide a different impulse response to the audio data during rate conversion.3. The rate converter of claim 2 , in which the plurality of filters are infinite impulse response (IIR) filters.4. The rate converter of claim 1 , in which the filter selector selects a new filter when an absolute value of the index error and a change of slope of the index error are both under or both over a threshold.5. The rate converter of claim 1 , in which ...

PARITY INTERLEAVING APPARATUS FOR ENCODING FIXED-LENGTH SIGNALING INFORMATION, AND PARITY INTERLEAVING METHOD USING SAME

A parity interleaving apparatus and method for fixed length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit. 1. A parity interleaving apparatus , comprising:a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; andmemory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.2. The parity interleaving apparatus of claim 1 , wherein the LDPC codeword includes zero-padded fixed length signaling information as information bits.3. The parity interleaving apparatus of claim 2 , wherein the parity bits correspond to 12960 bits claim 2 , the groups correspond to 36 groups each of which is composed of 360 bits.4. The parity interleaving apparatus of claim 3 , wherein the LDPC codeword includes an LDPC information bit string generated by filling all bits of information bit groups selected by using a shortening pattern order with 0.5. The parity interleaving apparatus of claim 4 , wherein the order of group-wise interleaving corresponds to a sequence of 36 numbers which indicate the order of the 36 groups.6. The parity interleaving apparatus of claim 5 , wherein the order of group-wise interleaving corresponds to a sequence [20 23 25 32 38 41 18 9 10 11 31 24 14 15 26 40 33 19 28 34 16 39 27 30 21 44 43 35 42 36 12 13 29 22 37 17].7. The parity ...

DATA SENDING METHOD AND APPARATUS

The present invention discloses a data sending method and apparatus, which resolves a problem that performance of a high coding rate LDPC code obtained in an existing puncturing manner based on a variable node degree distribution is relatively poor. The method includes: encoding, by using an LDPC code check matrix, an information bit that needs to be sent, to obtain a codeword sequence; determining a puncturing priority of each parity bit in the codeword sequence according to row destruction and/or cycle destruction, on the LDPC code check matrix, of a variable node corresponding to each parity bit; puncturing the codeword sequence according to the puncturing priority of each parity bit in the codeword sequence; and generating a bit sequence according to the punctured codeword sequence, and sending the bit sequence. In this way, performance of an obtained high coding rate LDPC code is improved. 1. A data sending method , wherein the method comprises:encoding, by using a low density parity check (LDPC) code check matrix, an information bit that needs to be sent, to obtain a codeword sequence, wherein the codeword sequence comprises the information bit and parity bits;determining a puncturing priority of each parity bit in the codeword sequence according to at least one of row destruction and cycle destruction, on the LDPC code check matrix, of a variable node corresponding to each parity bit;puncturing the codeword sequence according to the puncturing priority of each parity bit in the codeword sequence; andgenerating a bit sequence according to the punctured codeword sequence, and sending the bit sequence, whereinthe row destruction is used to measure impact of the variable node in the LDPC code check matrix on correct decoding of variable nodes adjacent to the variable node, wherein the adjacent variable nodes are variable nodes that are adjacent to the variable node and that are of variable nodes connected to check nodes connected to the variable node; and the ...

PARITY PUNCTURING DEVICE FOR VARIABLE-LENGTH SIGNALING INFORMATION ENCODING, AND PARITY PUNCTURING METHOD USING SAME

A parity puncturing apparatus and method for variable length signaling information are disclosed. A parity puncturing apparatus according to an embodiment of the present invention includes memory configured to provide a parity bit string for parity puncturing for the parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, and a processor configured to puncture a number of bits corresponding to a final puncturing size from the rear side of the parity bit string. 1. A parity puncturing apparatus , comprising:memory configured to provide a parity bit string for parity puncturing for parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15; anda processor configured to puncture a number of bits corresponding to a final puncturing size on a rear side of the parity bit string.2. The parity puncturing apparatus of claim 1 , wherein the LDPC codeword includes zero-padded variable length signaling information as information bits.3. The parity puncturing apparatus of claim 2 , wherein:the final puncturing size is calculated using a temporary puncturing size, a number of transmission bits, and a temporary number of transmission bits;the number of transmission bits is calculated using the temporary number of transmission bits and a modulation order;the temporary number of transmission bits is calculated using a difference between a sum of a length of a BCH-encoded bit string and 12960, and the temporary puncturing size; andthe temporary puncturing size is calculated using a value obtained by dividing a difference between a length of an LDPC information bit string and the length of the BCH-encoded bit string by 2.4. The parity puncturing apparatus of claim 3 , wherein the temporary puncturing size is calculated using a first integer claim 3 , multiplied by the value obtained by dividing the difference between the length of the LDPC information bit string and the length of the BCH-encoded bit string by 2 claim 3 , and a second ...

APPARATUS AND METHOD FOR SENDING AND RECEIVING BROADCAST SIGNALS

Disclosed herein is a broadcast signal receiver. The broadcast signal receiver according to an embodiment of the present invention includes a synchronization and demodulation module configured to perform detection and OFDM demodulation on a received broadcast signal, a frame parsing and deinterleaving module configured to parse and deinterleave the signal frame of the broadcast signal, a demapping and decoding module configured to convert the data of at least one Physical Layer Pipe (PLP) of the broadcast signal into a bit domain and to FEC-decode the PLP data, and an output processing module configured to receive the data of the at least one PLP and to output the received data in a data stream form. 114-. (canceled)15. A broadcast signal receiver , comprising:a demodulator to demodulate a broadcast signal;a pilot detector to detect pilots from the broadcast signal;a de-framer to de-frame a signal frame of the broadcast signal and to extract Physical Layer Pipe (PLP) data, the signal frame comprising a preamble and at least one subframe;wherein the subframe comprises data symbols and at least one Subframe Boundary Symbol (SBS), the data symbols comprising Scattered Pilots (SPs), and the SBS comprises data cells and subframe boundary pilots,the data cells of the SBS comprise active data cells and null cells,the active data cells are at a center and each half of the null cells are at each band edge within data carrier indices, and the de-framer determininga number of the active data cells of the SBS for an Fast Fourier Transform (FFT) size and an SP pattern is determined based on a coefficient to control a number of carriers and an SP boosting parameter for a boosted power level of the SPs;a de-interleaver configured to bit de-interleave the PLP data; anda decoder configured to decode the PLP data.21. The broadcast signal receiver of claim 15 , wherein the preamble comprises first information for indicating Fast Fourier Transform (FFT) size claim 15 , second ...

METHOD AND DEVICE FOR DE-PUNCTURING TURBO-CODED DIGITAL DATA, AND TURBO DECODER SYSTEM

A turbo decoder system decodes L-length digital data consisting of a systematic code and 1and 2parity check codes, and includes a trellis controller obtaining the ratio of the bit-number Ep of the 1/2parity check code to the bit-number D of an original systematic code and generating, based on the code rate of the digital data, a trellis control output indicating a target decoding trellis, which is selected by a turbo decoder to perform decoding operations. A zero-patch module patches zeros into the systematic code, and patches, based on the value of Ep/D, one or more zeros into the 1/2parity check code so that parity check bits of the 1/2parity check code and the zero-bit(s) form a periodically depunctured parity check code. 1. A method of de-puncturing turbo-coded digital data implemented by a de-puncturing device , the turbo-coded digital data corresponding to transmitted turbo-coded digital data that is obtained by puncturing original turbo-coded digital data based on a predetermined wireless communication protocol , the original turbo-coded digital data including a D-bit systematic code , and a D-bit parity check code for error correction , the turbo-coded digital data having an L-bit length and including a systematic code , which consists of a plurality of systematic bits , and a parity check code , which consists of a plurality of parity check bits , said method comprising steps of:a) obtaining a number Ep of the parity check bits of the parity check code of the turbo-coded digital data based on L, D, and a puncture parameter defined by the predetermined wireless communication protocol and associated with a number of punctured bits from the D-bit systematic code of the original turbo-coded digital data, where Ep is a positive integer;b) when there is any punctured bit existing in the systematic code of the turbo-coded digital data, patching one or more zeros into the systematic code of the turbo-coded digital data respectively at bit position(s) of the ...

COMPUTATIONALLY EFFICIENT CONVOLUTIONAL CODING WITH RATE-MATCHING

An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate. 1. A communication terminal for a mobile communications system , comprising , a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits;', 'an interleaver circuit for interleaving parity bits within each group of parity bits, wherein the interleaver circuit is configured to order parity bits such that odd parity bits precede even parity bits within each group of parity bits; and', 'a rate-matching circuit for outputting a selected number of said interleaved parity bits ordered by group to obtain a desired code rate., 'an error coding circuit, the error coding circuit further comprised of2. The communication terminal of claim 1 , wherein said interleaver circuit implements a reverse bit-reversal order interleaver for column permutation.3. The communication terminal of claim 1 , wherein said interleaver circuit implements a cyclically-shifted bit-reversal order interleaver for column permutation.4. The communication terminal of claim 1 , wherein said interleaver circuit implements a modulo-offset bit-reversal order interleaver for column permutation.5. The communication terminal of claim 1 , wherein the error coding circuit further comprises a channel interleaver following the rate-matching circuit.6. A communication terminal for a mobile communications system claim 1 , comprising claim 1 , a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits;', 'an interleaver circuit for interleaving parity bits within each group of parity bits; and', 'a rate-matching circuit for outputting a ...

PERFORMING A CYCLIC REDUNDANCY CHECKSUM OPERATION RESPONSIVE TO A USER-LEVEL INSTRUCTION

In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed. 120.-. (canceled)21. A processor comprising:{'claim-text': ['a cache;', 'a plurality of general-purpose registers; and', 'a plurality of execution units, including an integer execution unit and a single instruction multiple data (SIMD) execution unit, wherein at least one of the plurality of execution units comprises circuitry to:', 'perform a cyclic redundancy check (CRC) operation in response to one or more instructions executed in a 64-bit mode of operation, wherein the circuitry is to perform the CRC operation based on one of a plurality of data sizes, including a data size of 8-bits, 16-bits, 32-bits, and 64-bits, and wherein the one or more instructions are to indicate the data size to be used.'], '#text': 'a plurality of cores, wherein at least one of the cores comprises:'}22. The processor of claim 21 , wherein the plurality of general-purpose registers are 64-bit general-purpose registers.23. The processor of claim 21 , wherein said at least one of the plurality of execution units is to store a result of the CRC operation in a least significant 32-bits of a 64-bit general-purpose register and zeroes in a most significant 32-bits of the 64-bit general-purpose register.24. The processor of claim 21 , wherein the plurality of execution units include a floating point unit.25. The processor of claim 21 , wherein the at least one of the cores further comprises an address generation unit.26. The processor of claim 21 , wherein the CRC operation is to be performed with a polynomial that does not correspond to 11EDC6F41H.27. The processor of claim 21 , wherein the ...

METHODS AND APPARATUSES FOR CONSTRUCTING PUNCTURED POLAR CODE

Methods and apparatuses are provided for constructing a punctured polar code in the encoding and decoding field to improve decoding performance of a punctured polar code and reduce a frame error rate of the punctured polar code. The method is as follows: comparing a phase sequence number of a current bit channel with a period index of a puncturing pattern to obtain a comparison result; obtaining a transition probability of the bit channel according to the comparison result and bit parity conditions of a sequence number of the bit channel in each phase; obtaining a reliability value of each bit channel according to the transition probability; and determining an information bit index set according to the reliability values. 1. An apparatus for constructing a punctured polar code , comprising:a processor and a memory storage accessible to the processor, wherein the processor is configured to:compare a phase sequence number of a current bit channel with a period index of a puncturing pattern to obtain a comparison result;obtain a transition probability of the bit channel according to the comparison result and bit parity conditions of a sequence number of the bit channel in each phase; obtain a reliability value of each bit channel according to the transition probability; anddetermine an information bit index set according to the reliability values.2. The apparatus according to claim 1 , wherein the reliability value comprises Bhattacharyya parameters claim 1 , and the processor is further configured to:sort the Bhattacharyya parameters in ascending order, and form the information bit index set according to sequence numbers corresponding to bit channels of the first K Bhattacharyya parameters, wherein K is a positive integer less than or equal to a total quantity of the bit channels.3. The apparatus according to claim 1 , wherein the reliability value comprises an error probability claim 1 , and the processor is configured to:sort the error probabilities in ascending ...

Puncture-aware low density parity check (LDPC) decoding

A communication device or device includes a processor that generates and interprets signals that are transmitted and received via a communication interface. The processor receives an LDPC coded signal, via the communication interface, that is generated by puncturing at least one parity bit from another LDPC coded signal that is generated based on an LDPC code characterized by a first LDPC matrix. The processor operates on the first LDPC matrix to generate a second LDPC matrix by excluding at least one column and at least one row from the first LDPC matrix. The number of columns and rows excluded from the first LDPC matrix is based on the number of bits punctured from the other LDPC coded signal to generate the LDPC coded signal. The processor then decodes the LDPC coded signal using the second LDPC matrix to make estimates of information bits encoded within the LDPC coded signal.

METHOD AND APPARATUS FOR CHANNEL ENCODING/DECODING IN A COMMUNICATION OR BROADCASTING SYSTEM

A channel encoding method in a communication or broadcasting system is provided. The channel encoding method includes reading a first sequence corresponding to a parity check matrix, converting the first sequence to a second sequence by applying a certain rule to a block size corresponding to a parity check matrix and the first sequence, and encoding information bits based on the second sequence. The block size has at least two different integer values. 1. A method for encoding in a communication or broadcasting system supporting a low density parity check (LDPC) code , the method comprising:identifying a base matrix consisting of 0 and 1;identifying a predetermined number based on the base matrix;identifying a block size Z based on the predetermined number;identifying, from among a plurality of sets of block sizes, a set of block sizes associated with the block size Z;identifying an exponent matrix including at least one integer value based on the identified set of block sizes;obtaining a parity check matrix based on the base matrix, the block size Z, and the exponent matrix; andencoding information bits based on the parity-check matrix,wherein the parity-check matrix includes a submatrix consisting of Z×Z zero matrices and Z×Z circular permutation matrices.2. The method of claim 1 ,wherein a multiplication of the predetermined number and the block size Z is larger than or equal to a size of the information bits.3. The method of claim 1 , wherein the identifying of the block size comprises:identifying a size of the information bits to encode; andidentifying the block size based on the size of the information bits.4. The method of claim 1 , wherein the set of block sizes is associated with block sizes determined among {(A+i) claim 1 , 2(A+i) claim 1 , 2(A+i) claim 1 , . . . claim 1 , 2(A+i)} claim 1 , where i=0 claim 1 , 1 claim 1 , 2 claim 1 , . . . claim 1 , A−1 claim 1 , and A and S are positive integers.5. The method of claim 4 , wherein A is 8 and S is 4.6. The ...

HANDLING OPEN CIRCUITS WHILE WRITING DATA BY MOVING THEM TO THE LEAST VULNERABLE LOCATION IN AN ERROR CORRECTION CODE CODEWORD

Systems, apparatuses and methods may provide for recording, if a non-volatile memory (NVM) location satisfies an open circuit condition, open circuit location information associated with the NVM location. Additionally, a shift of one or more bits may be conducting during a write of a codeword to the NVM location to avoid open circuit in the NVM location. Moreover, an end of a parity portion of the codeword may be punctured by an amount of the shift. In one example, the end of the parity portion includes a last circulant of the codeword. 1. An apparatus comprising:an open circuit tracker to initiate a pre-read from a non-volatile memory (NVM) location in response to a request to perform a write of a codeword to the NVM location, determine whether the NVM location satisfies an open circuit condition based on the pre-read, and record, if the NVM location satisfies the open circuit condition, open circuit information associated with the NVM location;an encoder communicatively coupled to the open circuit tracker, the encoder to conduct, during the write of the codeword to the NVM location, a shift of one or more bits to avoid open circuits in the NVM location, wherein the encoder is to write the codeword to the NVM location without conducting the shift if the NVM location does not satisfy the open circuit condition; anda length adjuster communicatively coupled to the open circuit tracker, the length adjuster to puncture an end of a parity portion of the codeword by an amount of the shift, wherein the end of the parity portion is to include a last circulant of the codeword.2. The apparatus of claim 1 , wherein the open circuit tracker is to update an address indirection table to indicate that a page containing the NVM location is open circuit protected and store open circuit bit locations to a defect map.3. The apparatus of claim 1 , further including a decoder to detect a request to perform a read of the codeword from the NVM location claim 1 , retrieve open circuit bit ...

TIMING FOR IC CHIP

A integrated circuit (IC) chip can include a root timer that generates a frame pulse based on a start trigger signal. The IC chip can also include a hardware clock control that provides a clock signal based on a selected one of the frame pulse and the synchronization signal provided from one of the root timer and another IC chip. The IC chip can further include a plurality of analog to digital converters (ADCs). Each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal. 1. An integrated circuit (IC) chip comprising:a root timer that generates a frame pulse based on a start trigger signal;a hardware clock control that provides a clock signal based on a selected one of the frame pulse and a synchronization signal provided from one of the root timer and another IC chip; anda plurality of analog to digital converters (ADCs), each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal.2. The IC chip of claim 1 , further comprising:a microcontroller that controls a timing of software operations based on the frame pulse provided from the root timer, wherein operations controlled by the clock signal provided by the hardware clock control are synchronized within a tight window and the software operations are synchronized within a loose window.3. The IC chip of claim 2 , wherein the software operations include one or more of a calibration and a built-in self-test (BIST) for one or more of a plurality of RF transmitters and the plurality of RF receivers.4. The IC chip of claim 3 , wherein the software operations further include a radar chirp.5. The IC chip of claim 1 , wherein the root timer generates the synchronization signal and the synchronization signal is provided to a synchronization output terminal of the IC chip.6. The IC chip of claim 5 , further comprising:a ...

Digital broadcasting system and method of processing data

A digital broadcasting system including a transmitting system and a receiving system, and a method of processing data are disclosed. A method of processing data of a transmitting system includes sequentially grouping N number of columns (Kc) configured of A number of enhanced data bytes having information included therein, thereby creating a frame having a size of N (rows)*Kc (columns), wherein N and A are integers, encoding the created frame, and multiplexing and transmitting enhanced data included in the encoded frame and main data.

ENCODER, TRANSMITTING APPARATUS, CODING METHOD AND TRANSMITTING METHOD

Disclosed are an encoder, a transmitting device, a coding method and a transmission method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block coding is used. A puncture pattern setting unit searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code. 1. An encoder comprising:{'sub': 'b', 'claim-text': [{'br': None, 'i': 'GH', 'sup': 'T', '=0\u2003\u2003(Equation 1-1)'}, {'br': None, 'i': s', '=Gu, 'sup': T', 'T, '(Equation 1-2)'}, {'br': None, 'i': 'Hs=', '0\u2003\u2003(Equation 1-3)'}], 'a coder that generates a coded sequence s that is made up of z×nbits and satisfies Equation 1-1, Equation 1-2 and Equation 1-3 for information bit sequence u, where'}{'sub': b', 'b', 'b', 'b', 'b, 'where H is a parity check matrix of a low density parity check (LDPC) code of z×mrows and z×ncolumns configured by arranging submatrixes of z rows and z columns in mrows and ncolumns, G is a generator matrix holding a relationship of Equation 1-1 with the parity check matrix H of the LDPC code, and the coded sequence s is a coded sequence made up of z×nbits; and'}{'sub': 'b', 'a puncturer that forms a transmission information bit sequence by using either one of (i) a first puncturing pattern having a unit of devisor y of a number of columns z and determining bits to be removed for each y bits, (ii) a second puncturing pattern having a unit of the number of columns z and determining bits to be removed for each z bits, and (iii) a third puncturing pattern having a unit of k (integer equal to or ...

HARDWARE-EFFICIENT SYNDROME EXTRACTION FOR ENTANGLED QUANTUM STATES

A quantum-state-refresh module of a memory system is configured to detect an error in an entangled qubit state stored therein by performing a redundant measurement of syndrome values corresponding to a quantum stabilizer code, with the redundant measurement being based on a block error-correction code. The quantum-state-refresh module includes a plurality of measurement sub-modules, each configured to measure a respective syndrome value or a respective parity value corresponding to the entangled qubit state. The total number of the measurement sub-modules is smaller than the codeword length of the block error-correction code, and the initial approximation of the punctured syndrome values is replaced in the decoding process by erasure values. With the block error-correction code appropriately constructed for the use of erasure values, the quantum-state-refresh module is advantageously capable of providing reliable error detection with fewer quantum gates than that used for the full-length measurement of the codeword. 1. An apparatus comprising:a register configured to store a coded entangled qubit state generated using a quantum stabilizer code;a measurement circuit configured to perform a redundant measurement of a set of syndrome values corresponding to the coded entangled qubit state, wherein the redundant measurement is performed based on a block error-correction code;an erasure-value generator configured to generate a set of erasure values; anda decoder configured to determine a probable syndrome vector corresponding to the coded entangled qubit state using the block error-correction code and the redundant measurement of the set of syndrome values, and further configured to apply the set of erasure values generated by the erasure-value generator to a set of variable nodes not configured to receive a measured syndrome value from the measurement circuit.2. The apparatus of claim 1 , further comprising a state-recovery circuit configured to correct an error in the ...

PACKET RETRANSMISSION

Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like. 1105.-. (canceled)106. An apparatus comprising:a multicarrier transceiver including a processor and memory capable of:transmitting a packet using forward error correction encoding and interleaving, wherein the packet comprises a header field and a plurality of Reed-Solomon codewords, and wherein the header field comprises a sequence identifier (SID); andreceiving a message using forward error correction decoding and without using deinterleaving, wherein the message is received in a single DMT symbol, and wherein the message includes an acknowledgement (ACK) or a negative acknowledgement (NACK) of the transmitted packet.107. The apparatus of claim 106 , wherein the received message has a higher immunity to noise than the transmitted packet.108. The apparatus of claim 106 , wherein the transceiver is capable of retransmitting the packet using forward error correction encoding and interleaving.109. The apparatus of claim 106 , wherein a physical layer of the transceiver is capable of generating the packet and the message.110. The apparatus of claim 106 , wherein a layer above a physical layer of the transceiver is capable of generating the packet and the message.111. The apparatus of claim 107 , wherein a physical layer of the transceiver is capable of generating the packet and the message.112. The apparatus of claim 107 , a layer above a physical layer of the transceiver is ...

METHOD OF CODIFYING DATA INCLUDING GENERATION OF A QUASI-CYCLIC CODE

A method including selecting a factor based on a number of bits in a codeword and a natural number and generating a model matrix including first and second matrices having data and parity bits. Hamming weights of the model matrix are not constant and Hamming weights of columns of the model matrix follow a statistical distribution dependent upon a codification rate of a channel. A compact matrix is generated by replacing elements of the model matrix equal to: 1 with a pseudo-random positive whole number; and 0 with −1. A quasi-cyclic code is generated by replacing in the compact matrix: positive elements with identity matrices; and elements equal to −1 with null matrices. A number of rows and columns in each of the identity and null matrices is equal to the factor. The quasi-cyclic code is applied to a word to generate a codeword, which is transmitted on the channel. 1. A method comprising:selecting a factor at a first device, wherein the factor is equal to a number of bits in a codeword divided by a natural number;generating a model matrix, wherein the model matrix includes (i) a first matrix comprising data, and (ii) a second matrix comprising parity bits, wherein Hamming weights of columns and rows of the model matrix are not constant and the Hamming weights of the columns follow a statistical distribution dependent upon a codification rate of a channel such that the model matrix is irregular;generating a compact matrix by replacing (i) each element of the model matrix that is equal to 1 with a pseudo-random positive whole number, and (ii) each element of the model matrix that is equal to 0 with a −1, wherein the pseudo-random positive whole number is greater than or equal to 0 and less than the factor;generating a quasi-cyclic code including a parity matrix by replacing (i) each positive element of the compact matrix with an identity matrix, and (ii) each element of the compact matrix equal to −1 with a null matrix, wherein each of the identity matrices is ...

SOFTWARE DEFINED NETWORK WITH SELECTABLE LOW LATENCY OR HIGH THROUGHPUT MODE

Encoding and decoding systems are provided for reduced latency at the decoder. In the encode error detection codewords are produced from source bits. The error detection codewords are then encoded with a systematic error correction encoder to produce a set of parity bits. All of the systematic code source bits and at least some of the parity bits are mapped to modulation symbols for transmission. In the decoder, two signal processings are performed in parallel, one based on soft bit decisions and the other based on hard bit decisions. The soft bit decisions are processed using a systematic error correction decoder. The hard bit decisions are processed by re-encoding error detection codewords to produce parity bits. If the produced parity bits match received parity bits, then the hard bit decisions are reliable and are output without waiting for the result of the systematic error correction decoder. 1. A method comprising:generating a plurality of error detection codewords by, for each of a plurality of sets of source bits, encoding the set of source bits with an error detection encoder to produce an error detection codeword, the error detection codeword containing the set of source bits and a set of error detection bits;encoding a set of systematic code source bits with a systematic error correction encoder to produce a set of parity hits, the set of systematic code source bits consisting of the plurality of error detection codewords;mapping all of the systematic code source bits and at least some of the parity bits to modulation symbols;transmitting the modulation symbols.2. The method of wherein encoding each set of source bits to produce the set of error detection bits comprises computing a checksum on the set of source bits.3. The method of wherein encoding each set of source hits to produce the set of error detection bits comprises computing a cyclic redundancy check on the set of source bits.4. The method of wherein encoding the set of systematic code source ...

Method and System for Accelerated Stream Processing

Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams. 1. A system for applying parallelism to process streaming data at low latency and high throughput , the streaming data comprising data arranged in a plurality of fields , the system comprising:at least one member of the group consisting of (1) a reconfigurable logic device, (2) a graphics processor unit (GPU), and (3) a chip multi-processor (CMP);wherein a processing pipeline is deployed on the at least one member for receiving and processing the streaming data, the processing pipeline including a plurality of parallel paths, each of a plurality of the parallel paths including pipelined logic for performing different processing operations on the streaming data;wherein each of a plurality of the parallel paths includes field selection logic that filters which fields of the streaming data that downstream pipelined logic in that parallel path will process, wherein a plurality of the parallel paths include field selection logic that filter for different fields of the streaming data so that the processing pipeline is thereby configured to parallel process different fields of the streaming ...

GROUPS OF PHASE INVARIANT CODEWORDS

Disclosed herein are a system, non-transitory computer-readable medium, and method for encoding and decoding information on a data bearing medium. A message comprising a bit string is read. A plurality of substrings in the message may be associated with a phase invariant codeword. 1. A method of encoding a message , comprising:reading a message comprising a bit string of a first length;dividing the message into a plurality of substrings, each substring having a second length shorter than the first length;determining a phase invariant codeword associated with each substring; and,generating a composite codeword comprising each phase invariant codeword.2. A method as in claim 1 , wherein determining a phase invariant codeword associated with each substring comprises:based on selection criteria, and where each of a number of groups of phase invariant codewords has a different property, selecting a group of phase invariant codewords having a particular property; and,selecting a phase invariant codeword associated with the substring from within the selected group of phase invariant codewords.3. A method as in claim 1 , wherein the particular property is a range of values defining the number of active bits in the phase invariant codeword of each group.4. A method as in claim 2 , wherein the selection criteria comprise a selection criterion chosen from phase invariant codewords being selected from a single group claim 2 , and phase invariant codewords being selected from any combination of the groups.5. A method as in claim 1 , wherein generating a composite codeword comprising each phase invariant codeword comprises:interspersing each symbol of each phase invariant codeword with respective symbols of each of the other phase invariant codewords.6. A method as in claim 1 , wherein determining a phase invariant codeword associated with each substring comprises:searching a LUT (look up table) that comprises stored associations between phase invariant codewords and bit strings ...

Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals comprises an encoder encoding service data, a time interleaver interleaving the encoded service data, a mapper mapping the interleaved service data into a plurality of OFDM (Orthogonal Frequency Division Multiplex) symbols to build at least one signal frame, a frequency interleaver frequency interleaving data in the at least one signal frame by using a different interleaving-seed which is used for every OFDM symbol pair comprised of two sequential OFDM symbols, wherein the frequency interleaving is performed by using two memories, a modulator modulating the frequency interleaved data by an OFDM scheme and a transmitter transmitting the broadcast signals having the modulated data, wherein an interleaving-seed is generated based on a cyclic shift value and an FFT size of the modulating.

COMPUTATIONALLY EFFICIENT CONVOLUTIONAL CODING WITH RATE-MATCHING

An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate. 1. A communication terminal for a mobile communications system , comprising ,an error coding circuit, the error coding circuit further comprised of:a convolutional encoder configured to receive an input bit stream and to generate two or more groups of parity bits from the input bit stream;an interleaver circuit configured to separately interleave parity bits within each group of parity bits; anda rate-matching circuit configured to output a selected number of said interleaved parity bits, to obtain an output code rate, such that a first one of the groups is output before a second one of the groups.2. The communication terminal of claim 1 , wherein the rate-matching circuit includes a circular buffer storing the interleaved parity bits claim 1 , ordered by group claim 1 , and wherein said rate-matching circuit is configured to output the selected number of interleaved parity bits from the circular buffer.3. The communication terminal of claim 1 , wherein said interleaver circuit is configured to apply identical interleaving for each group of parity bits.4. The communication terminal of claim 1 , wherein the rate-matching circuit is configured to puncture parity bits claim 1 , when the two or more groups of parity bits include more bits than needed to achieve the output code rate claim 1 , by puncturing up to all of the parity bits in one of the groups of parity bits before puncturing bits in any other group of parity bits.5. The communication terminal of claim 1 , wherein the rate-matching circuit is configured to repeat parity bits claim 1 , when the two or more groups of parity bits include fewer ...

Processor, method and computer program for processing an audio signal using truncated analysis or synthesis window overlap portions

A processor for processing an audio signal has: an analyzer for deriving a window control signal from the audio signal indicating a change from a first asymmetric window to a second window, or indicating a change from a third window to a fourth asymmetric window, wherein the second window is shorter than the first window, or wherein the third window is shorter than the fourth window; a window constructor for constructing the second window using a first overlap portion of the first asymmetric window, wherein the window constructor is configured to determine a first overlap portion of the second window using a truncated first overlap portion of the first asymmetric window, or wherein the window constructor is configured to calculate a second overlap portion of the third window using a truncated second overlap portion of the fourth asymmetric window; and a windower for applying the first and second windows or the third and fourth windows to obtain windowed audio signal portions.

PUNCTURING FOR STRUCTURED LOW DENSITY PARITY CHECK (LDPC) CODES

Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low density parity check (LDPC) codes. A method for wireless communications by wireless node is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a matrix having a first number of variable nodes and a second number of check nodes, puncturing the code word to produce a punctured code word, wherein the puncturing is performed according to a first puncturing pattern designed to puncture bits corresponding to one or more of the variable nodes having a certain degree of connectivity to the check nodes, and transmitting the punctured code word 1. A method for wireless communications , comprising:encoding a set of information bits based on a low density parity check (LDPC) code to produce a code word, the LDPC code defined by a matrix having a first number of variable nodes and a second number of check nodes;puncturing the code word to produce a punctured code word, wherein the puncturing is performed according to a first puncturing pattern designed to puncture bits corresponding to one or more of the variable nodes having a certain degree of connectivity to the check nodes; andtransmitting the punctured code word.2. The method of claim 1 , wherein the first puncturing pattern is designed to puncture bits corresponding to at least one variable node having a highest degree of connectivity to the check nodes.3. The method of claim 2 , wherein the first puncturing pattern is designed to puncture a first number of bits at a start of the code word.4. The method of claim 3 , wherein the bits corresponding to the at least one variable node having the highest degree of connectivity to the check nodes comprise the first number of bits at the start of the code word.5. The method of claim 3 , wherein the first puncturing pattern is further designed to puncture remaining bits of the code ...

SYSTEM AND METHOD FOR COMMUNICATING WITH LOW DENSITY PARITY CHECK CODES

The present invention provides an approach for FEC encoding based on intermediate code block lengths not associated with any supported mother FEC code. A first string of kdata bits is received. The first string of data bits is encoded to generate an Nbit code block for transmission over a channel of a wireless communications network. The first data bit string is encoded based on a supported (N, k) forward error correction (FEC) code of a code rate R=k/N, configured to encode a string of data bits of a length kbits to generate a code block of a length Nbits. To facilitate the encoding of the first string of data bits based on the (N, k) FEC code, the encoding comprises padding, repeating and/or puncturing the first string of data bits and a resulting Nbit code block to generate the Nbit code block. 1. A method comprising:{'sub': '2', 'receiving a first string of data bits of a length kbits; and'}{'sub': '2', 'encoding the first string of data bits to generate a code block of a length Nbits for transmission over a channel of a wireless communications network;'}{'sub': 1', '1', '1', '1', '1', '1, 'wherein the first string of data bits is encoded based on a supported (N, k) forward error correction (FEC) code of a code rate R=k/Nconfigured to encode a string of data bits of a length kbits to generate a code block of a length Nbits; and'}{'sub': 1', '1', '1', '2, 'wherein, to facilitate the encoding of the first string of data bits based on the (N, k) FEC code, the encoding comprises one or more of padding, repeating and puncturing the first string of data bits and a resulting Nbit code block to generate the Nbit code block.'}2. The method of claim 1 , wherein k Подробнее

LENGTH AND RATE COMPATIBLE LDPC ENCODER AND DECODER

A method and apparatus for encoding data and for decoding data using LDPC (low density parity check) codes includes providing a mother LDPC matrix of a particular size. A data payload of a smaller size is encoded by shortening the mother matrix to a smaller daughter matrix corresponding in size to the data payload and using the smaller daughter matrix for the encoding. The portions of the mother matrix to be removed in the shortening are derived from a control signal. The encoded data is transmitted with the control signal so that the receiver can derive the portions of the mother matrix to be removed to obtain the daughter matrix. At the receiver, a mother matrix is shortened to a daughter matrix and is then used to decode the data. The data at the encoder may be further reduced by puncturing to remove selected information bits and selected parity bits. The decoder inserts the selected information bits and parity bits when decoding the data. 1. A method of modifying a code matrix according to a received digital signal , comprising:storing a mother code matrix in a memory, the mother code matrix having a predetermined size;receiving a digital signal of a predetermined payload length;determining the payload length of the received digital signal;deriving an information shortening set from at least the payload length;modifying the stored mother code matrix in response to the information shortening set to produce a modified code matrix;storing the modified code matrix in a memory of a coder element, the coder element being one of an encoder or a decoder; andcoding the received digital signal using the modified code matrix stored in the coder memory, the coding being one of encoding or decoding.2. A method as claimed in claim 1 , wherein the determining the payload length of the received digital signal includes receiving a control signal that includes payload length information.3. A method as claimed in claim 1 , wherein the modified code matrix is of a smaller size than ...

APPARATUS AND METHOD FOR SENDING AND RECEIVING BROADCAST SIGNALS

A broadcast signal transmitter is disclosed. A broadcast signal transmitter according to the present invention comprises a scrambler for scrambling signaling information; an FEC encoder for FEC encoding the signaling information; a bit interleaver for block interleaving and bit demultiplexing of the signaling information; and a constellation mapper for symbol mapping of the signaling information. 1. A broadcast signal transmitter for processing a broadcast signal including signaling information , the broadcast signal transmitter comprisinga scrambler for scrambling the signaling information;a FEC(Forward Error Correction) encoder for FEC encoding the signaling information;a bit demultiplexer for block interleaving and bit demultiplexing of the signaling information; anda constellation mapper for symbol mapping of the signaling information;wherein the FEC encoder comprisesa BCH encoding/zero inserting unit for BCH encoding the signaling information and inserting zero bits based on length of the BCH encoded signaling information;an LDPC encoding unit for LDPC encoding the signaling information and adding parity bits;a parity permutation unit for interleaving and permutating the parity bits of the LDPC encoded signaling information; anda parity puncturing/zero removal unit for puncturing the parity bits of the signaling information and removing the zero bits of the signaling information.2. The broadcast signal transmitter of claim 1 , wherein the parity permutation unit splits the interleaved parity bits into at least one bit group unit.3. The broadcast signal transmitter of claim 2 , wherein the parity permutation unit permutates the parity bits by the bit group unit.4. The broadcast signal transmitter of claim 1 , wherein the parity puncturing/zero removing unit punctures a predetermined number of last parity bits of the parity bits.5. The broadcast signal transmitter of claim 1 , wherein the BCH encoding/zero inserting unit pads the zero bits according to a ...

METHOD AND APPARATUS FOR DATA PROCESSING WITH STRUCTURED LDPC CODES

The embodiments of the present disclosure provide a method and an apparatus for data processing with structured LDPC codes. The method includes: obtaining a code block size for structured LDPC coding; determining a coding expansion factor z based on at least one of the code block size, a parameter kb of a basic check matrix, a positive integer value p or the basic check matrix having mb rows and nb columns; and encoding a data sequence to be encoded, or decoding a data sequence to be decoded, based on the basic check matrix and the coding expansion factor. The present disclosure is capable of solving the problem in the related art associated with low flexibility in data processing with LDPC coding and improving the flexibility in data processing with LDPC coding. 1. A method for wireless communication , comprising:determining a code block size for Low Density Parity Check (LDPC) coding;determining a coding expansion factor Z from a set of coding expansion factors based on the code block size and a parameter kb associated with a basic check matrix, wherein the parameter kb and the coding expansion factor Z are integers larger than 1;encoding a data sequence based on the basic check matrix and the coding expansion factor Z; andtransmitting a subset of the encoded data sequence, the subset excluding q*Z bits corresponding to q columns of the basic matrix, q being a positive integer.2. The method of claim 1 , wherein the code block size is determined based on a set of code block sizes organized in an ascending order.3. The method of claim 1 , wherein q=2.4. The method of claim 1 , wherein each of the q columns of the basic check matrix is given a column weight to indicate a number of elements each representing a square matrix obtained by cyclically shifting an identify matrix claim 1 , and wherein a difference between column weights of any two of q columns is equal to 1.5. The method of claim 1 , wherein the basic check matrix has mb rows and nb columns claim 1 , kb ...

Method and apparatus for channel encoding/decoding in a communication or broadcasting system

A channel encoding method in a communication or broadcasting system is provided. The channel encoding method includes reading a first sequence corresponding to a parity check matrix, converting the first sequence to a second sequence by applying a certain rule to a block size corresponding to a parity check matrix and the first sequence, and encoding information bits based on the second sequence. The block size has at least two different integer values.

System and method for maximal code polarization

An apparatus and a method. The apparatus includes a plurality of polarization processors, including n inputs and n outputs, where n is an integer; and at least one permutation processor, including n inputs and n outputs, wherein each of the at least one permutation processor is connected between two of the plurality of polarization processors, and connects the n outputs of a first of the two of the plurality of polarizations processors to the n inputs of a second of the two of the plurality of polarization processors between which each of the at least one permutation processor is connected in a permutation pattern that maximally polarizes the n outputs of the second of the two of the plurality of polarization processors.

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Transmission apparatus, transmission method, reception apparatus and reception method

Disclosed are an encoder, a transmitting device, a coding method and a transmission method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block coding is used. A puncture pattern setting unit searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code.

PERFORMING A CYCLIC REDUNDANCY CHECKSUM OPERATION RESPONSIVE TO A USER-LEVEL INSTRUCTION

In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed. 1. A processor comprising:a cache;a plurality of 64-bit registers including a first 64-bit register to store 64-bits of source data and a second 64-bit register to store a 32-bit initial value in bits [31:0]; and perform CRC32 computations on the 64-bits of source data and the 32-bit initial value based on a polynomial value of 11EDC6F41H; and', 'store a result of the CRC32 computations in bits [31:0] of a 64-bit destination and zeroes in bits [63:32] of the 64-bit destination., 'an execution unit coupled with the first and second 64-bit registers, the execution unit, responsive to a 32-bit cyclic redundancy check (CRC32) instruction of an instruction set architecture of the processor, to2. The processor of claim 1 , wherein the CRC32 computations comprise incremental CRC32 computations on a plurality of portions of the 64-bits of source data.3. The processor of claim 1 , wherein the CRC32 instruction is a user-level instruction.4. The processor of claim 1 , further comprising:a floating point unit;a reorder buffer (ROB);a load buffer; anda store buffer.5. The processor of claim 1 , further comprising a memory controller.6. A processor comprising:a cache;a plurality of 64-bit registers including a first 64-bit register to store source data and a second 64-bit register to store a 32-bit initial value in bits [31:0]; and perform CRC32 computations on the source data and the 32-bit initial value based on a polynomial value of 11EDC6F41H; and', 'store a result of the CRC32 computations in a destination., 'an execution unit coupled with the first and second 64-bit ...

PACKET RETRANSMISSION

Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like. 1. A method of packet retransmission comprising:transmitting or receiving a plurality of packets;identifying at least one packet of the plurality of packets as a packet that should not be retransmitted.2105-. (canceled) This application claims the benefit of and priority under 35 U.S.C. § 119(e) to U.S. Patent Application Nos. 60/792,236, filed Apr. 12, 2006, entitled “xDSL Packet Retransmission Mechanism,” and 60/849,650, filed Oct. 5, 2006, entitled “xDSL Packet Retransmission Mechanism with Examples,” which are both incorporated herein by reference in their entirety.This invention generally relates to communication systems. More specifically, an exemplary embodiment of this invention relates to retransmission of packets in a communication environment. An exemplary embodiment of this invention also relates to memory sharing between transmission functions and other transceiver functions.Exemplary aspects of the invention relate to handling of packets and the assignment of a packet handling identifier. Exemplary aspects relate to sharing of resources between retransmitted packets and other transceiver functions. In addition, exemplary aspects relate to sharing of resources between packets associated with the packet handling identifier and other transceiver functions.More specifically, aspects of the invention relate to assigning a packet handling identifier to one or more ...

OPTIMIZED CODE TABLE SIGNALING FOR AUTHENTICATION TO A NETWORK AND INFORMATION SYSTEM

In various embodiments, a system comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor is disclosed. The memory medium is configured to store a plurality of instructions configured to program the processor to receive a digital bit stream, transform the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof, and provides the encoded digital bit stream to the network interface for transmission. A non-transitory computer-readable memory medium and a computer-implemented method also are disclosed. 1. A computer-implemented method comprising:receiving, by a processor, an encoded digital bit stream, wherein the encoded digital bit stream comprises a gateway portion and a composite portion, wherein the gateway portion comprises a unique formatting function and an identification of the composite partition configuration;obtaining, by the processor, the unique formatting function from the encoded digital stream by applying pre-coordinated, pre-distributed information that identifies intended sender-receiver pairs; andtransforming, by the processor, the encoded digital bit stream to an unencoded digital bit stream by using the unique formatting function.2. The computer-implemented method of claim 1 , further comprising:maintaining, by the processor, the unique formatting function by utilizing the pre-coordinated, pre-distributed information.3. The computer-implemented method of claim 1 , wherein transforming the encoded digital bit stream to an unencoded digital bit stream comprises applying claim 1 , by the processor claim 1 , at least one m-element vector table to the encoded digital bit stream.4. The computer-implemented method of claim 3 , wherein applying the at least one m-element vector table to the encoded digital bit stream comprises performing claim 3 , by the ...

OPTIMIZED CODE TABLE SIGNALING FOR AUTHENTICATION TO A NETWORK AND INFORMATION SYSTEM

In various embodiments, a system comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor is disclosed. The memory medium is configured to store a plurality of instructions configured to program the processor to receive a digital bit stream, transform the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel and any combination thereof, and provides the encoded digital bit stream to the network interface for transmission. A non-transitory computer-readable memory medium and a computer-implemented method are disclosed. 1. A computer-implemented method comprising:receiving, by a processor, an encoded digital bit stream, wherein the encoded digital bit stream comprises a gateway portion and a composite portion, wherein the gateway portion comprises a unique formatting function and an identification of the composite partition configuration;obtaining, by the processor, the unique formatting function from the encoded digital stream by applying pre-coordinated, pre-distributed information that identifies intended sender-receiver pairs; andtransforming, by the processor, the encoded digital bit stream to an unencoded digital bit stream by using the unique formatting function.2. The computer-implemented method of claim 1 , further comprising:maintaining, by the processor, the unique formatting function by utilizing the pre-coordinated, pre-distributed information.3. The computer-implemented method of claim 1 , wherein transforming the encoded digital bit stream to an unencoded digital bit stream comprises applying claim 1 , by the processor claim 1 , at least one m-element vector table to the encoded digital bit stream.4. The computer-implemented method of claim 3 , wherein applying the at least one m-element vector table to the encoded digital bit stream comprises performing claim 3 , by the processor ...

RATE MATCHING METHOD AND APPARATUS FOR POLAR CODE

A rate matching method for a polar code is provided, to improve performance. The method includes: encoding, based on an N*N encoding matrix of a polar code, a sequence including N first bits, to generate a mother code including N second bits, where the N first bits are in a one-to-one correspondence with N rows in the encoding matrix in sequence, and the N second bits are in a one-to-one correspondence with N columns in the encoding matrix in sequence; determining N−M to-be-punctured second bits from the N second bits, where at least one first bit in N−M first bits participating in encoding of the N−M second bits belongs to the first M first bits in the N first bits, and the N−M first bits are fixed bits; and puncturing the N−M second bits, to obtain a target polar code including M second bits. 1. A rate matching method for a polar code , the method comprising:encoding, based on an N*N encoding matrix of a polar code, a sequence comprising N first bits to generate a mother code comprising N second bits, wherein the N first bits are in a one-to-one correspondence with N rows in the encoding matrix in sequence, and the N second bits are in a one-to-one correspondence with N columns in the encoding matrix in sequence;determining N−M to-be-punctured second bits from the N second bits, wherein at least one first bit in N−M first bits participating in encoding of the N−M second bits belongs to the first M first bits in the N first bits, and the N−M first bits are fixed bits; andpuncturing the N−M second bits, to obtain a target polar code comprising M second bits.6. The method according to claim 2 , wherein:{'sup': 'th', 'the N−M second bits are sequentially determined based on N−M rounds of operations; a first round of operation in the N−M rounds of operations comprises: determining a second bit corresponding to an Ncolumn in the N columns as a to-be-punctured second bit; and'}{'sup': 'th', 'claim-text': determining an (N−j)*(N−j) auxiliary encoding matrix, wherein the ...

SYSTEMS AND METHODS FOR INTER-CELL INTERFERENCE MITIGATION IN A FLASH MEMORY

The present inventions are related to systems and methods for accessing data from a flash memory, and more particularly to systems and methods for inter-cell interference handling in a flash memory. The systems and methods may include a soft information correction circuit that is operable to receive soft information corresponding to information accessed from a block of memory cells, and modify the soft information based upon a variance of the soft information and a median of the soft information to create corrected soft information, the corrected soft information being used to mitigate inter-cell interference in the block of memory cells. 1. A data processing system , the data processing system comprising: read one or more voltage levels from a block of flash memory cells;', 'convert each read voltage level to a bit pattern;', 'generate soft information corresponding to at least one bit pattern;', 'select a side of asymmetry based at least in part on the at least one bit pattern;', 'calculate an offset reduced output based on the selected side of asymmetry;', 'scale the offset reduced output to calculate corrected soft information; and', 'calculate a data output for the at least one bit pattern based at least in part on applying a data decoding algorithm to the corrected soft information., 'a soft information correction circuit operable to2. The data processing system of claim 1 , wherein the side of asymmetry is based on an asymmetric distribution of multiple voltage levels claim 1 , each of the multiple voltage levels being represented digitally by a bit pattern.3. The data processing system of claim 2 , wherein the side of asymmetry is selected based on a determination of whether at least one voltage value from the multiple voltage levels is less than a value of a sum of an estimated actual mean provided by a parameter calculation circuit and an estimated interference mean provided by the parameter calculation circuit.4. The data processing system of claim 1 , ...

ADJUSTED FRACTALLY ENHANCED KERNEL POLAR CODES FOR ACHIEVABLE SIGNAL-TO-NOISE RATIO SPIKE MITIGATION

Methods, systems, and devices for wireless communications are described. In some systems, wireless devices may implement adjusted fractally enhanced kernel polar coding. An encoder may receive a number of information bits and a block size for transmission, and may append an additional number of information bits to the information bits for transmission. The encoder may perform a recursive bit allocation process to allocate the aggregate set of information bits between a set of sub-blocks based on mutual information metrics. To obtain the correct number of information bits and block size, the encoder may remove a number of information bits equal to the number of appended additional bits (e.g., from a first half of the sub-blocks), assign the remaining information bits to bit channels in each sub-block, and block puncture a set of bits (e.g., from the first half). The resulting codeword may mitigate occurrences of achievable signal-to-noise ratio (SNR) spikes. 1. A method for wireless communication , comprising:identifying a plurality of information bits comprising a number of bits for encoding;determining an aggregate number of information bits for fractally enhanced kernel polar code construction, wherein the aggregate number of information bits is equal to a sum of the number of bits for encoding and an additional number of bits;allocating a total number of information bit channels according to the fractally enhanced kernel polar code construction and the aggregate number of information bits;removing a number of allocated information bit channels from the total number of information bit channels to obtain a final set of allocated information bit channels, wherein the number of removed allocated information bit channels is equal to the additional number of bits;generating a polar-encoded codeword based at least in part on assigning the plurality of information bits to the final set of allocated information bit channels; andtransmitting the polar-encoded codeword.2. ...

Method and System for Accelerated Stream Processing

Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams. 1. A system for making a compute resource available in a network for loading a processing pipeline thereon for the compute resource to apply parallelism when processing streaming data , the streaming data comprising data arranged in a plurality of fields , the system comprising:a processor that is addressable within a network, the processor arranged for configuration in response to a command over the network so that a processing pipeline for receiving and processing streaming data is loadable thereon;the loadable processing pipeline including a plurality of parallel paths for augmenting the streaming data with a plurality of flags indicative of a plurality of rule conditions, each of a plurality of the parallel paths including pipelined logic for performing different processing operations on the streaming data, and wherein each of a plurality of the parallel paths includes field selection logic that filters which fields of the streaming data that downstream pipelined logic in that parallel path will process, wherein a plurality of the parallel paths include field selection logic that ...

DETECTION, AVOIDANCE AND/OR CORRECTION OF PROBLEMATIC PUNCTURING PATTERNS IN PARITY BIT STREAMS USED WHEN IMPLEMENTING TURBO CODES

Detecting, avoiding and/or correcting problematic puncturing patterns in parity bit streams used when implementing punctured Turbo codes is achieved without having to avoid desirable code rates. This enables identification/avoidance of regions of relatively poor Turbo code performance. Forward error correction comprising Turbo coding and puncturing achieves a smooth functional relationship between any measure of performance and the effective coding rate resulting from combining the lower rate code generated by the Turbo encoder with puncturing of the parity bits. In one embodiment, methods to correct/avoid degradations due to Turbo coding are implemented by puncturing interactions when two or more stages of rate matching are employed. 1. An apparatus for use in wireless communications comprising:a first interleaver configured to interleave systematic bits;a second interleaver configured to interleave a first parity bit stream;a third interleaver configured to interleave a second parity bit stream;a buffer configured to buffer the interleaved systematic bits, the interleaved first parity bit stream and the interleaved second parity bit stream; anda rate matching unit configured to select bits for transmission based on a plurality of redundancy versions; wherein at least one redundancy version of the set selects systematic bits over first and second parity bits and at least one redundancy version of the set selects first and second parity bits over systematic bits.2. The apparatus of wherein selecting of bits by the rate matching unit in response to a selected redundancy version changes in response to a location of the bits in the buffer.3. A method for use in an apparatus of a wireless communications comprising:interleaving, by the apparatus, systematic bits;interleaving, by the apparatus, a first parity bit stream;interleaving, by the apparatus, a second parity bit stream;buffering, by the apparatus, the interleaved systematic bits, the interleaved first parity bit ...

CODEWORD PUNCTURING FOR VARYING CODE RATES

A system of codeword puncturing for varying code rates may include at least one transmitter circuit. The at least one transmitter circuit may be configured to perform error correction coding to generate codewords at a first code rate. The at least one transmitter circuit may be further configured to puncture a number of bits from a location within each of the codewords to implement a second code rate that is greater than the first code rate. The at least one transmitter circuit may be further configured to provide the punctured codewords for transmission. The device may further include at least one receiver circuit that may be configured to receive bit sequences comprising received punctured codewords. The at least one receiver circuit may be further configured to insert bits into the bit sequences to compensate for the puncturing and perform error correction decoding on the bit sequences including the inserted bits. 1. A device comprising: perform error correction coding to generate codewords at a first code rate;', 'puncture a number of bits from a location within each of the codewords to implement a second code rate that is greater than the first code rate; and', 'provide the punctured codewords for transmission., 'at least one transmitter circuit configured to2. The device of claim 1 , wherein the transmitter circuit is further configured to:negotiate, with at least one receiver circuit, the number of bits to puncture from each of the codewords and the location within each of the codewords to puncture the number of bits.3. The device of claim 1 , wherein the transmitter circuit is further configured to:transmit, to at least one receiver circuit, an indication of the number of bits being punctured from each codeword and the location of the number of bits being punctured from each codeword.4. The device of claim 1 , further comprising at least one memory circuit configured to store claim 1 , prior to the error correction coding claim 1 , the number of bits to ...

Method and system for the error-correcting transmission of a data record via a unidirectional communication unit

A method and a system for fault-correcting transfer of a dataset from a first network into a second network via a unidirectional communication unit, the receiving apparatus having a limited computing and main memory capacity is provided. The dataset is divided into partial datasets and are each coded by adding at least one correction mark. The marks and correction marks are decoded repeatedly in the second network, wherein marks and correction marks associated with a first encoded partial dataset are stored in a main memory, marks and correction marks associated with other encoded partial datasets are buffered in a background memory, and the first coded partial dataset is decoded, and then the previously received marks and/or correction marks of one of the other coded partial datasets are shifted from the background memory into the main memory. The dataset is reproduced from the decoded partial datasets in the second network.

TRANSMITTER AND REPETITION METHOD THEREOF

A transmitter is provided. The transmitter includes at least one processor configured to implement: a Low Density Parity Check (LDPC) encoder which encodes input bits to generate an LDPC codeword including the input bits and parity bits; a puncturer which calculates a number of bits to be punctured in the parity bits and punctures the parity bits based on the calculated number of bits; and a repeater which selects at least a part of bits of the LDPC codeword based on a repetition pattern, and repeats the selected bits after the parity bits, wherein the repetition pattern is a pattern for selecting at least one bit group including the selected bits among a plurality of bit groups configuring the LDPC codeword. 1. A transmitter comprising:a Low Density Parity Check (LDPC) encoder which encodes input bits to generate an LDPC codeword comprising the input bits and parity bits;a puncturer which calculates a number of bits to be punctured in the parity bits and punctures the parity bits based on the calculated number of bits; anda repeater which selects at least a part of bits of the LDPC codeword based on a repetition pattern, and repeats the selected bits after the parity bits,wherein the repetition pattern is a pattern for selecting at least one bit group comprising the selected bits among a plurality of bit groups configuring the LDPC codeword.2. The transmitter of claim 1 , wherein the puncturer punctures the parity bits as many as the calculated number Nof bits to be punctured in the parity bits when the calculated number Nof bits to be punctured is a positive integer and does not perform the puncturing when the calculated number Nof bits to be punctured is a negative integer.3. The transmitter as claimed in claim 2 , wherein the repeater determines −Nbits as the number of bits to be repeated when the Nis a negative integer claim 2 , and selects bits as many the determined number from the LDPC codeword as the bits to be repeated in the LDPC codeword.6. The ...

RATE CONVERTOR

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power. 1. An audio processing circuit , comprising:a multiplier accumulator having a multiplier and an adder, the multiplier accumulator configured to output an output sample;a first multiplexer configured to receive a sample index and a sample input and output one of the sample index and the sample output to the multiplier of the multiplier accumulator;a second multiplexer configured to receive a coefficient and the output sample and output one of the coefficient and the output sample to the multiplier;an output accumulator configured to receive and store the output sample; anda third multiplexer configured to receive the output sample from the output accumulator and the coefficient and output one of the coefficient and output sampler to the adder.2. The audio processing circuit of further comprising a coefficient buffer configured to store one or more coefficients.3. The audio processing circuit of further comprising a sample index accumulator for determining the sample index for each output audio sample at an output sample rate different from an input sample rate.4. The audio processing circuit of further comprising a gain value controller configured to adjust gain values during conversion between the input sample rate and an output sample rate.5. The audio processing circuit of further ...

MEMORY CONTROLLER SUPPORTING RATE-COMPATIBLE PUNCTURED CODES

Apparatus and methods store data in a non-volatile solid state memory device according to a rate-compatible code, such as a rate-compatible convolutional code (RPCC). An example of such a memory device is a flash memory device. Data can initially be block encoded for error correction and detection. The block-coded data can be further convolutionally encoded. Convolutional-coded data can be punctured and stored in the memory device. The puncturing decreases the amount of memory used to store the data. Depending on conditions, the amount of puncturing can vary from no puncturing to a relatively high amount of puncturing to vary the amount of additional error correction provided and memory used. The punctured data can be decoded when data is to be read from the memory device. 1. A method of determining a code rate for a block of memory space in a non-volatile solid-state memory device , the method comprising:determining whether a marginal condition exists for at least a portion of a block of data of the memory device; anddecreasing a code rate used with the block if the marginal condition exists.2. The method of claim 1 , wherein decreasing comprises reducing an amount of puncturing.3. The method of claim 2 , wherein the code rate after puncturing is in a range of 1/3 to 1/2.4. The method of claim 2 , wherein the punctured data is convolutionally encoded prior to puncturing.5. The method of claim 2 , wherein the punctured data corresponds to a convolutional code with a code rate of 1/4 prior to puncturing.6. The method of claim 1 , further comprising storing reference information in an unpunctured form from the one or more memory arrays claim 1 , wherein the reference information indicates the code rate used.7. The method of claim 1 , wherein the non-volatile memory device corresponds to a NAND flash memory device.8. An apparatus comprising:one or more memory arrays of a non-volatile memory device; anda memory controller configured to determine whether a marginal ...

Offset Lifting Method

A method and system for offset lifting is provided. In an embodiment, a method for encoding data includes receiving a K-bit source word input. The method also includes encoding the K-bit source word input according to a LDPC code, a lifting function, and a circulant size offset to generate an N-bit code word output. The circulant size and lifting function are determined according to an information length, a code rate, and a decoder. The method also includes storing the N-bit code word output in input/output memory. 1. A method for encoding data , comprising:receiving a K-bit source word input;encoding the K-bit source word input according to a LDPC code, a lifting function, and a circulant size offset to generate an N-bit code word output, wherein the circulant size and lifting function are determined according to an information length, a code rate, and a decoder; andstoring the N-bit code word output in input/output memory.2. The method of claim 1 , wherein circulant size claim 1 , Z claim 1 , is limited by a set of allowed values such that Z is in a form n*2̂s where n is a positive integer from a fixed set of integers and s is a non-negative integer claim 1 , such that the options for Z are first 2 or more smallest numbers that have a form of n*2̂s and are greater or equal to Z claim 1 , wherein Zis a minimal possible circulant size to encode the given number of information bits.3. The method of claim 1 , wherein shifts of non-zero circulants for predefined positions are unchanged.4. The method of claim 1 , wherein the lifting table is shared by at least some the one or more mother codes obtained by puncturing parity bits to change the rate of the code.5. The method of claim 1 , where the lifting functions for defining child shifts from the mother shift are defined as selecting the given number of bits from the binary representation of the mother shift at some predefined positions.6. The method of claim 1 , where the lifting functions for defining child shifts ...

Polar Code Interleaving and Bit Selection

Apparatus and methods are provided for polar code sub-block interleaving and bit selection. In one novel aspect, middle-part interlaced sub-block interleaving is provided for polar code interleaving. In one embodiment, the middle part of the polar code is interlaced and generates the interleaved polar code. In another embodiment, the lower part and the upper part are also sub-block interleaved with the middle-part interlaced method. In another novel, rate-dependent unified bit selection is provided. The bit selection is categorized into three operation categories of repetition, puncturing and the shortening. Each category follows unified bit selection rule with different categories differ only in the access scheme. In one embodiment, the circular buffer is used for bit selection. 1. A method comprising:dividing in sequence a polar code into a lower part, a middle part, and an upper part, wherein the system polar code has a polar code length N;performing a rate-independent interlaced interleaving for the middle part of the polar code to obtain an interleaved bit sequence; andperforming a rate-dependent bit selection from the interleaved bit sequence based on an output length E to obtain a transmission bit sequence.2. The method of claim 1 , the bit selection is categorized to bit-selection operations comprising: a repetition operation with E greater than or equal to N claim 1 , a puncturing operation with E smaller than N and a targeted code rate smaller than or equal to a predefined threshold T claim 1 , and a shortening operation with E smaller than N and a targeted code rate greater than T.3. The method of claim 2 , wherein the bit selection operation is the repetition operation claim 2 , and wherein the transmission bit sequence from index 0 to E is selected starting from a lowest index of the interleaved bit sequence and repeated from the lowest index of the interleaved bit sequence.4. The method of claim 2 , wherein the bit selection operation is the puncturing ...

METHOD AND APPARATUS FOR COMMUNICATION

Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position. 1. An apparatus , comprising:transmitting circuitry configured to transmit wireless signals; and encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits;', 'buffer the code word in a circular buffer;', 'determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits; and', 'transmit, via the transmitting circuitry, a selected portion of the code word from the start position., 'processing circuitry configured to2. The apparatus of claim 1 , wherein the processing circuitry is configured to:puncture a portion of the information bits from the code word; andbuffer the punctured code word in the circular buffer.3. The apparatus of claim 1 , wherein the processing circuitry is configured to:encode the set of information bits with a low density parity check (LDPC) code that is configured for incremental redundancy.4. The apparatus of claim 1 , further comprising:receiving circuitry configured to receive the redundancy version that ...

INTERLEAVING AND PUNCTURING APPARATUS AND METHOD THEREOF

An apparatus and method for interleaving and puncturing are provided. The apparatus includes: an interleaver formed of a plurality of columns and rows, configured to perform interleaving by writing bits input to the interleaver in the plurality of columns and reading the bits from each row of the plurality of columns in which the bits are written; and a puncturer configured to puncture a predetermined number of bits among the bits read from the interleaver. 1. An apparatus comprising at least one processor to implement:an interleaver configured to write bits in a plurality of columns, and read the written bits,wherein the plurality of columns comprise a first column and a second column, andwherein the interleaver reads the written bits by skipping a first bit written in a row of the first column and reading a second bit written in the row of the second column.2. The apparatus as claimed in claim 1 , wherein the first bit and the second bit are bits written claim 1 , respectively claim 1 , in columns which are not adjacent to each other.3. The apparatus as claimed in claim 1 , wherein claim 1 , the interleaver sequentially reads a third bit and the second bit from the row by skipping the first bit.4. The apparatus as claimed in claim 3 , wherein the interleaver reads the third bit adjacent the first bit from the row claim 3 , and reads the second bit which is not adjacent to the third bit from the row without reading the first bit.5. The apparatus as claimed in claim 1 , further comprising:a puncturer configured to puncture one or more bits of the read bits.6. A method comprising:writing bits in a plurality of columns; andreading the written bits,wherein the plurality of columns comprise a first column and a second column, and reading the written bits by skipping a first bit written in a row of the first column; and', 'reading a second bit written in the row of the second column., 'wherein the reading comprises7. The method as claimed in claim 6 , wherein the first ...

TRANSMITTER AND ADDITIONAL PARITY GENERATING METHOD THEREOF

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder which encodes input bits including outer encoded bits to generate an LDPC codeword including the input bits and parity bits to be transmitted to a receiver in a current frame; a puncturer which punctures a part of the parity bits which is not transmitted in the current frame; and an additional parity generator which selects at least a part of the parity bits to generate additional parity bits transmitted to the receiver in a previous frame of the current frame, wherein a number of the additional parity bits is determined based on a number of the outer encoded bits and a number of the parity bits left after the puncturing. 1. A transmitter comprising:a Low Density Parity Check (LDPC) encoder configured to encode input bits comprising outer encoded bits to generate parity bits;a puncturer configured to puncture at least a part of the parity bits which is not transmitted in a current frame; andan additional parity generator configured to select at least a part of the parity bits to generate additional parity bits transmitted to the receiver in a previous frame of the current frame,wherein a number of the additional parity bits is determined based on a number of the outer encoded bits and a number of remaining parity bits left after the puncturing.2. The transmitter of claim 1 , wherein the number of the additional parity bits is determined further based on a number of the punctured parity bits which are not transmitted to the receiver in the current frame.3. The transmitter of claim 1 , further comprising a repeater configured to repeat claim 1 , in a LDPC codeword comprising the input bits and the parity bits claim 1 , at least a part of bits of the LDPC codeword so that the repeated bits of the LDPC codeword are transmitted along with the LDPC codeword prior to the repetition in the current frame.4. The transmitter of claim 3 , wherein the number of the additional parity ...

TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform parity-permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern, wherein the first pattern determines parity bits to remain after the puncturing and then to be transmitted in the current frame. 1. A transmitter comprising:a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits;a parity permutator configured to group-wise interleaves a plurality of bit groups constituting the parity bits based on a group-wise interleaving pattern comprising a first pattern and a second pattern;a puncturer configured to puncture some of the group-wise interleaved parity bits; andan additional parity generator configured to select bits among the group-wise interleaved parity bits to generate additional parity bits to be transmitted in a previous frame of a current frame,wherein the additional parity bits are determined according to the first pattern and the second pattern, andwherein the first pattern determines parity bits to remain after the puncturing and then to be transmitted in the current frame2. The transmitter of claim 1 , wherein the second pattern determines bit groups to be always punctured in the plurality of bit groups regardless of a number of parity bits to be punctured by ...

TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to interleave the parity bits and group-wise interleave a plurality of parity bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern to perform parity permutation; a puncturer configured to puncture at least some of the group-wise interleaved parity bit groups; and an additional parity generator configured to select at least some of the punctured parity bit groups to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern. 1. A transmitter , comprising:a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits;a parity permutator configured to group-wise interleaves a plurality of bit groups constituting the parity bits based on a group-wise interleaving pattern comprising a first pattern and a second pattern;a puncturer configured to puncture at least a part of the group-wise interleaved parity bits; andan additional parity generator configured to select bits among the group-wise interleaved parity bits to generate additional parity bits to be transmitted in a previous frame of a current frame,wherein the additional parity bits are determined according to the first pattern and the second pattern, andwherein the first pattern determines parity bits to remain after the puncturing and then to be transmitted in the current frame.2. The transmitter of claim 1 , wherein the second pattern parity bit groups to be always punctured in the group-wise interleaved bit groups regardless of a number of parity bits to be punctured by the puncturer.3. The transmitter of claim 1 , wherein the additional parity ...

TRANSMITTER AND REPETITION METHOD THEREOF

A transmitter is provided. The transmitter includes: a low density parity check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits; a repeater configured to select at least a part of bits constituting the LDPC codeword and add the selected bits after the input bits; and a puncturer configured to puncture at least a part of the parity bits. 1. A transmitter comprising:a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits;a repeater configured to append at least a part of bits from an LDPC codeword comprising the input bits and the parity bits to the input bits, so that the at least a part of the LDPC codeword is repeated; anda puncturer configured to puncture at least a part of the parity bits.2. The transmitter of claim 1 , wherein the input bits comprise zero bits padded in the input bits claim 1 , and the repeater is configured to calculate a number of bits to be selected and added after the input bits based on a number of bits other than the padded zero bits in the input bits.3. The transmitter of claim 2 , wherein the repeater is configured to calculate the number of the bits to be selected and added after the input bits further based on a modulation order used to modulate the input bits and the parity bits left after adding the selected bits and puncturing the part of the parity bits claim 2 , for transmission to a receiver.4. The transmitter of claim 1 , wherein the input bits comprise outer encoded bits claim 1 , and the repeater is configured to calculate a number of bits to be selected and added after the input bits based on a number of the outer encoded bits.5. The transmitter of claim 4 , wherein the repeater is configured to calculate the number of the bits to be selected and added after the input bits further based on a modulation order used to modulate the input bits and the parity bits left after adding the selected bits and puncturing the ...

TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform by group-wise interleaving a plurality of bit groups configuring the parity bits based on a group-wise interleaving pattern comprising a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern. 1. A transmitter comprising:a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits;a parity permutator configured to group-wise interleaves a plurality of bit groups constituting the parity bits based on a group-wise interleaving pattern comprising a first pattern and a second pattern;a puncturer configured to puncture at least a part of the group-wise interleaved parity bits; andan additional parity generator configured to select bits among the group-wise interleaved parity bits to generate additional parity bits to be transmitted in a previous frame of a current frame,wherein the additional parity bits are determined according to the first pattern and the second pattern, andwherein the first pattern determines parity bits to remain after the puncturing and then to be transmitted in the current frame.2. The transmitter of claim 1 , wherein the second pattern represents bit groups to be always punctured in the plurality of bit groups regardless of a number of parity bits to be punctured by the puncturer.3. The transmitter of claim 2 , wherein the additional parity generator generates the additional parity bits by selecting at least some of bits included in the bit ...

APPARATUS FOR TRANSMITTING AND RECEIVING A SIGNAL AND METHOD OF TRANSMITTING AND RECEIVING A SIGNAL

The present invention relates to a method of transmitting and a method of receiving signals and corresponding apparatus. One aspect of the present invention relates to an efficient layer 1 (L1) processing method for a transmitter and a receiver using data slices. 115-. (canceled)16. A method of transmitting broadcasting data to a receiver , the method comprising:LDPC (Low-density parity-check) encoding Layer 1 signaling data to generate LDPC parity bits;puncturing the generated LDPC parity bits;interleaving the encoded Layer 1 signaling data on which the puncturing was performed;mapping the interleaved Layer 1 signaling data into Layer 1 signaling data symbols;LDPC encoding PLP (Physical Layer Pipe) data of a PLP carrying one or more services;interleaving the encoded PLP data;mapping the interleaved PLP data into PLP data symbols; andtransmitting a signal frame including the Layer 1 signaling data symbols and the PLP data symbols,wherein the PLP data symbols in the signal frame are located after the Layer 1 signaling data symbols for signaling the PLP,wherein the Layer 1 signaling data include information for indicating a change of the Layer 1 signaling data and identification information for identifying the PLP.17. The method of claim 16 , further comprising:frequency interleaving the Layer 1 signaling data symbols.18. The method of claim 16 , further comprising:time interleaving the PLP data symbols.19. The method of claim 16 , wherein the Layer 1 signaling data further include indication information for indicating whether the PLP contains table information for acquiring one or more services.20. A transmitter for transmitting broadcasting data to a receiver claim 16 , the transmitter comprising:a first encoder to LDPC encode Layer 1 signaling data to generate LDPC parity bits;a puncture to puncture the generated LDPC parity bits;a first interleaver to interleave the encoded Layer 1 signaling data on which the puncturing was performed;a first mapper to map the ...

ENHANCED POLAR CODE CONSTRUCTION

Methods, systems, and devices for wireless communications are described. An encoder of a wireless device may receive a number of information bits and a block size for transmission. If the block size is not a power of two, the encoder may round the block size up to the nearest power of 2, generate a larger codeword, and puncture the excess bits. The punctured bits may affect a rate of polarization when generating a polar code, and sub-blocks with a high number of punctured bits may produce too few sufficiently polarized channels. The encoder may implement a capacity backoff when polar coding to identify a greater number of polarized channels. The encoder may assign information bits to sufficiently polarized channels of the greater number of polarized channels. 1. A method for wireless communication , comprising:receiving a signal representing a codeword over a wireless channel, the codeword being encoded using a polar code having a code length;identifying, in the signal, unpunctured bit-channels of the codeword;identifying a set of bit locations of the polar code used for information bits for the encoding, wherein the set of bit locations is determined based at least in part on dividing a number of the information bits into partitions allocated to first bit-channel sub-blocks for at least one stage of polarization of the polar code, wherein the partitioning is based at least in part on a mutual information transfer function of an initial capacity of the unpunctured bit-channels of the codeword, respective numbers of unpunctured bit-channels in the first bit-channel sub-blocks, and respective numbers of delta bits for the first bit-channel sub-blocks, and wherein the respective numbers of delta bits for each of the first bit-channel sub-blocks are based at least in part on a capacity backoff function; anddecoding the signal according to the polar code to obtain an information bit vector at the set of bit locations.2. The method of claim 1 , further comprising: ...

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder to encode service data corresponding to a number of physical paths, a time interleaver to time interleave the encoded service data in each physical path, a frame builder to build at least one signal frame including the time interleaved service data, a modulator to modulate data in the built at least one signal frame by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter to transmitting the broadcast signals having the modulated data. 110-. (canceled)11. An apparatus for receiving a broadcast signal , the apparatus comprising:a tuner configured to receive a signal frame carrying broadcast data and signaling information including first information and second information,the first information related to a number of FEC blocks,the second information related to a maximum number of Forward Error Correction (FEC) blocks;a demodulator configured to demodulate the signal frame by an Orthogonal Frequency Division Multiplex (OFDM) scheme;a first deinterleaver configured to deinterleave the data based on a convolutional deinterleaving scheme; anda second deinterleaver configured to deinterleave a Time Interleaving (TI) block in the deinterleaved data based on the signaling information; anda decoder to decode the second deinterleaved data.12. The method of claim 11 ,wherein a number of FEC blocks vary between TI blocks.13. A method of receiving broadcast signals claim 11 , the method comprising:receiving a signal frame carrying broadcast data and signaling information including first information and second information,the first information related to a number of FEC blocks,the second information related to a maximum number of Forward Error Correction (FEC) blocks;demodulating the signal frame by an Orthogonal Frequency Division Multiplex (OFDM) scheme;deinterleaving the data based on a ...

ERROR CONCEALMENT METHOD AND APPARATUS FOR AUDIO SIGNAL AND DECODING METHOD AND APPARATUS FOR AUDIO SIGNAL USING THE SAME

An error concealment method and apparatus for an audio signal and a decoding method and apparatus for an audio signal using the error concealment method and apparatus. The error concealment method includes selecting one of an error concealment in a frequency domain and an error concealment in a time domain as an error concealment scheme for a current frame based on a predetermined criteria when an error occurs in the current frame, selecting one of a repetition scheme and an interpolation scheme in the frequency domain as the error concealment scheme for the current frame based on a predetermined criteria when the error concealment in the frequency domain is selected, and concealing the error of the current frame using the selected scheme. 1. A An apparatus for concealing an error in an audio or speech signal , the apparatus comprising:at least one processor configured to: 'conceal the frame based on the determined error concealment scheme.', 'determine an error concealment scheme of a frame from a plurality of error concealment schemes, based on signal characteristics including stationarity of the audio or speech signal and can error concealment scheme used for a previous frame of the frame, when the frame corresponds to a current error frame or a good frame after an error frame; and'}2. The apparatus of claim 1 , wherein the signal characteristics are obtained by using a length of the current frame.3. The apparatus of claim 1 , wherein the signal characteristics are obtained by using a window type of the previous frame.4.An apparatus for decoding an audio or speech signal claim 1 , the apparatus comprising: decode a first frame when an error does not occur in the first frame; and', 'determine an error concealment scheme of a second frame from a plurality of error concealment schemes, based on signal characteristics including stationarity of the audio or speech signal and an error concealment scheme used for a previous frame of the second frame, when the second ...

HARQ RATE-COMPATIBLE POLAR CODES FOR WIRELESS CHANNELS

A method, apparatus, and chipset are provided for constructing hybrid automatic repeat request (HARQ) rate-compatible polar codes for communication channels. The method includes constructing, in a terminal, a base polar code of length 2; and determining a sequence of m<2bits to puncture in the base polar code by testing a predetermined criterion at most (2+2)/2−1 times. 1. A method of constructing hybrid automatic repeat request (HARQ) rate-compatible polar codes for wireless channels , the method comprising:{'sup': 'n', 'constructing, in a terminal, a base polar code of length 2; and'}{'sup': n', '2n', 'n, 'determining a sequence of m<2bits to puncture in the base polar code by testing a predetermined criterion at most (2+2)/2−1 times.'}2. The method of claim 1 , wherein determining the m bits to puncture in the base polar code by testing the predetermined criterion at most (2+2)/2−1 times comprises:{'sup': 'n', 'setting, in the terminal, a counter i equal to 2;'}testing the predetermined design criterion i times;selecting one bit to puncture;decrementing i;{'sup': 'n', 'if i is not equal to 2−m, returning to the step of testing the predetermined design criterion i times; and'}{'sup': 'n', 'if i is equal to 2−m, terminating the method.'}3. The method of claim 1 , further comprising:searching, in the terminal, the base polar code for a puncturing sequence;puncturing the base polar code according to the puncturing sequence; and{'sup': n+t', 'n', 't, 'constructing a final polar code of length 2bits by encoding each of the 2bits in the punctured base polar code 2times.'}4. The method of claim 3 , further comprising:{'sup': n', 't, 'storing, in the terminal, the bits of the final polar code in an array of 2columns and 2rows;'}arrange the columns of the array according to a known puncturing sequence;reading the bits of final polar code column by column;transmitting, by the terminal, the read bits of the final polar code;receiving, by a receiver, the transmitted bits of ...

APPARATUS AND METHOD FOR SENDING AND RECEIVING BROADCAST SIGNALS

Disclosed herein is a broadcast signal receiver. The broadcast signal receiver according to an embodiment of the present invention includes a synchronization and demodulation module configured to perform detection and OFDM demodulation on a received broadcast signal, a frame parsing and deinterleaving module configured to parse and deinterleave the signal frame of the broadcast signal, a demapping and decoding module configured to convert the data of at least one Physical Layer Pipe (PLP) of the broadcast signal into a bit domain and to FEC-decode the PLP data, and an output processing module configured to receive the data of the at least one PLP and to output the received data in a data stream form. 114-. (canceled)20. The broadcast signal receiver of claim 15 , wherein the preamble comprises first information for indicating the Fast Fourier Transform (FFT) size claim 15 , second information related to the SP pattern and third information for indicating the SP boosting parameter.21. The broadcast signal receiver of claim 15 , wherein a number of null cells is obtained by subtracting the number of active data cells of the SBS from a number of data cells of the SBS.22. The broadcast signal receiver of claim 21 , wherein the number of active data cells of the SBS is obtained based on following equation:{'br': None, 'sub': SP,SBS', 'NSP-CP', 'SP, 'i': N', 'A, 'sup': '2', 'NoA−(N−NoC+NoA+)×(),'}{'sub': SP,SBS', 'NSP-CP', 'SP, 'the NoA being the number of active data cells in the data symbol, the Nbeing a number of SBS pilots, the NoC being a number of carriers, the Nbeing a number of non-Scattered Pilot (SP) bearing continual pilots (CPs) and the Abeing the amplitude of scattered pilots.'}29. The method of claim 23 , wherein the preamble comprises first information for indicating the Fast Fourier Transform (FFT) size claim 23 , second information related to the SP pattern and third information for indicating the SP boosting parameter.30. The method of claim 23 , wherein ...

METHOD AND APPARATUS FOR ERROR-CORRECTION ENCODING USING A POLAR CODE

An improved method of computer communication and networking with error-correction encoding and transmission using a punctured polar code construction that is based on polar code decomposition is provided. Advantageously, this allows sorting of a reliability sequence to be performed for a reduced-length vector to identify the information bit positions in the reduced-length polar code vector. Polar code decomposition is used to determine a number of information bits allocated to given reduced-length vector (e.g., Kand K). The polar code construction is a function of a puncturing pattern. In some embodiments, the puncturing pattern is a shortening pattern. 2. The method of further comprising:{'sub': 0', '1, 'determining respective puncturing patterns P, Pfor the two polar codes of length N/2 based on the puncturing pattern P;'}{'sub': 0', '1, 'determining respective punctured codeword lengths M, Mfor the two polar codes based on the puncturing patterns; and'}{'sub': 0', '1, 'determining respective capacities C, Cfor the two polar codes based on the respective determined punctured codeword lengths and the channel capacity C;'}{'sub': 0', '1', '0', '1', '0', '1, 'wherein determining the respective input information vector bit lengths Kand Kis based on at least one of the determined punctured codeword lengths M, Mand at least one of the determined capacities C,C.'}3. The method of further comprising:determining a revised channel capacity for the physical channel;updating the polar code construction using the revised channel capacity;encoding and transmitting using the updated polar code construction.4. The method of further comprising updating the constructed polar code based one or a combination of:Revised K;Revised N;Revised M;Revised P;Revised channel capacity.5. The method of wherein performing at least one iteration of polar code deconstruction comprises performing iterations in sequence for N=N claim 1 , N/2 claim 1 , N/4 claim 1 , . . . N/N claim 1 , and wherein ...

OPTIMIZING PHYSICAL PARAMETERS IN FAULT-TOLERANT QUANTUM COMPUTING TO REDUCE FREQUENCY CROWDING

A technique relates to quantum error correction. Code qubits are configured as target qubits, and the code qubits have a first dephasing time and a first anharmonicity. Syndrome qubits are configured as control qubits, and the syndrome qubits have a second dephasing time and a second anharmonicity. The target qubits and the control qubits are configured to form one or more controlled not (CNOT) gates. The first dephasing time is greater than the second dephasing time and the second anharmonicity is greater than the first anharmonicity. 1. A quantum error correction circuit comprising:a syndrome qubit; andcode qubits each coupled to the syndrome qubit to form controlled not (CNOT) gates, each of the code qubits being target qubits and the syndrome qubit being a control qubit, wherein the syndrome qubit is measured to obtain a parity.2. The quantum error correction circuit of claim 1 , wherein the code qubits are not coupled together.3. The quantum error correction circuit of claim 1 , wherein the syndrome qubit is a fixed state.4. The quantum error correction circuit of claim 1 , wherein the code qubits are in a superposition of states.5. The quantum error correction circuit of claim 1 , wherein the code qubits are configured to be coupled together.6. The quantum error correction circuit of claim 1 , wherein the syndrome qubit is a fixed state.7. The quantum error correction circuit of claim 1 , wherein the code qubits have a first dephasing time.8. The quantum error correction circuit of claim 7 , wherein the code qubits have a first anharmonicity.9. The quantum error correction circuit of claim 8 , wherein the syndrome qubit has a second dephasing time.10. The quantum error correction circuit of claim 9 , wherein the syndrome qubit has a second anharmonicity.11. The quantum error correction circuit of claim 10 , wherein the first dephasing time is different from the second dephasing time.12. The quantum error correction circuit of claim 10 , wherein the first ...

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder to encode service data corresponding to a number of physical paths, a time interleaver to time interleave the encoded service data in each physical path, a frame builder to build at least one signal frame including the time interleaved service data, a modulator to modulate data in the built at least one signal frame by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter to transmitting the broadcast signals having the modulated data. 110-. (canceled)11. A method for transmitting broadcast signals , the method comprising:encoding service data;time interleaving the encoded service data, wherein the time interleaving includes:twisted block interleaving the encoded service data by a Time interleaving (TI) block, wherein the twisted block interleaving includescolumn-wise writing at least one TI block into a memory, wherein a TI block includes at least one Forward Error Correction (FEC) block having the encoded service data;diagonal-wise reading the written at least one TI block; andconvolutional interleaving the twisted block interleaved service data;building at least one signal frame including the time interleaved service data;modulating data in the built at least one signal frame by an Orthogonal Frequency Division Multiplex (OFDM) scheme; andtransmitting the broadcast signals having the modulated data.12. The method of claim 11 ,wherein the convolutional interleaving includes:splitting the TI block into a number of interleaving units; andspreading the number of interleaving units over the at least one signal frame.13. The method of claim 11 ,wherein the encoded service data are grouped into an interleaving frame (IF) to be mapped onto the at least one signal frame, wherein the IF includes at least one TI block.14. The method of claim 11 ,wherein the TI block further includes at ...

MEASUREMENT METHOD, MEASUREMENT APPARATUS AND MEASUREMENT PROGRAM

[Problem] To shorten the measurement time, while maintaining the measurement precision, for a data converter of delta-sigma system. 1. A measurement method for delta-sigma type data converter , which converts data between analog domain and digital domain , which sequentially captures output digital codes through data conversion by said data converter, corresponding to ramp signal inputs generated by certain step input voltages;', 'which makes pairs of vary and neighbor output digital codes in order in said output digital codes;', 'which processes statistical calculations by using said output digital codes or input voltages corresponding to said output digital codes;', 'and which calculates non-linearity errors form said statistical calculations., 'wherein said measurement method2. Said measurement method described in claim 1 , which calculates first estimation values of input voltages, which is corresponding to said output digital codes, per said output digital codes;', 'which calculates differences between said first estimation values, corresponding to pairs of said output digital codes per pair;', 'and which processes said statistical calculations for said first estimation values., 'wherein said measurement method3. Said measurement method described in claim 1 , which calculates differences between pairs of said output digital codes per pair;', 'and which processes said statistical calculations for differences between pairs of said output digital codes., 'wherein said measurement method4. Said measurement method described in claim 1 , which calculates inverse numbers of differences between pairs of said output digital codes per pair;', 'and which processes said statistical calculations for inverse numbers of differences between pairs of said output digital codes., 'wherein said measurement method5. Said measurement method described in claim 1 , which calculates tentative non-linearity errors from pairs of said output digital codes per pair;', 'and which processes ...

METHOD AND APPARATUS FOR CONVOLUTIONAL CODING TO SUPPORT MULTIPLEXING IN A WIDEBAND COMMUNICATIONS SYSTEM

An approach for encoding a physical layer (PL) header of a PL data frame is provided. The PL header comprises sixteen information bits u, (i=0, 1, 2, . . . , 15), and the encoding is based on a convolutional code, whereby, for each information bit, five associated parity bits P, (k=0, 1, 2, 3, 4) are generated, resulting in 80 codebits. The resulting 80 codebits are punctured to form a (16,77) codeword (c, c, c, c). The codebits of the (16,77) codeword are repeated to generate a (16,154) physical layer signaling codeword (c, c, c, c, c, c, c, c) for transmission of the PL data frame over a channel of a communications network. Further, for each information bit, each of the associated five parity bits is generated based on a parity bit generator, as follows: p=(u*g)⊕(S*g)⊕(S*g)⊕(S*g)⊕(S*g), where S=u, S=u, S=u, S=u, and wherein generator polynomials for g=(g, g, g, g, g), are as follows: g=(1, 0, 1, 0, 1); g=(1, 0, 1, 1, 1); g=(1, 1, 0, 1, 1); g=(1, 1, 1, 1, 1); g=(1, 1, 0, 0, 1). 1. (canceled)2. A method comprising:{'sub': i', 'i', 'i,k, 'encoding, by a processor of a device, a physical layer header of a physical layer data frame, wherein the physical layer header comprises sixteen information bits u, i=0, 1, 2, . . . , 15, and the encoding is based on a rate 1/5 convolutional code, wherein, for each information bit u, i=0, 1, 2, . . . , 15, five associated parity bits p, k=0, 1, 2, 3, 4 are generated, resulting in a first codeword of 80 codebits; and'}repeating the codebits of the first codeword to generate a physical layer signaling codeword for transmission of the physical layer data frame over a channel of a communications network;{'sub': i', 'i,k', 'i,k', 'i', 'k,0)⊕(S', '0', 'k,1', '1', 'k,2', '2', 'k,3', '3', 'k,4', '0', 'i-1', '1', 'i-2', '2', 'i-3', '3', 'i-4, 'wherein, for each information bit u, i=0, 1, 2, . . . , 15, each of the associated five parity bits p, k=0, 1, 2, 3, 4 is generated based on a parity bit generator, as follows: p=(u*g*g)⊕(S*g)⊕(S*g)⊕( ...

Detection of adjacent two bit errors in a codeword

In an embodiment, a processor includes error correction code (ECC) circuitry to: receive a codeword comprising data bits and parity bits; generate, using a parity checking matrix H, a syndrome vector associated with the received codeword, where the parity-checking matrix H comprises a data segment comprising N data columns and a parity segment comprising K parity columns, where a total quantity of data columns in the data segment with even weight is equal to N+K−2 (K−1) +1; and detect an adjacent two bit error in the codeword based on a comparison of the syndrome vector to the parity checking matrix H. Other embodiments are described and claimed.

ENHANCED PUNCTURING AND LOW-DENSITY PARITY-CHECK (LDPC) CODE STRUCTURE

Certain aspects of the present disclosure generally relate to techniques for enhanced puncturing and low-density parity-check (LDPC) code structure. A method for wireless communications by a transmitting device is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a base matrix having a first number of variable nodes and a second number of check nodes; puncturing the code word according to a puncturing pattern designed to puncture bits corresponding to at least two of the variable nodes to produce a punctured code word; adding at least one additional parity bit for the at least two punctured variable nodes; and transmitting the punctured code word. 1. A method for wireless communications , comprising:encoding a set of information bits based on a low-density parity-check (LDPC) code to produce a code word, the LDPC code defined by a base matrix having a first number of variable nodes and a second number of check nodes;puncturing the code word according to a puncturing pattern designed to puncture bits corresponding to at least two of the variable nodes to produce a punctured code word;adding at least one additional parity bit to the base matrix for the at least two punctured variable nodes; andtransmitting the punctured code word.2. The method of claim 1 , wherein the at least two punctured variable nodes have a higher degree of connectivity to the check nodes than the other variable nodes in the base matrix.3. The method of claim 1 , wherein the at least one additional parity bit is formed by a parity of the at least one pair of the at least two punctured variable nodes.4. The method of claim 1 , wherein the at least two punctured variable nodes comprises M variable nodes claim 1 , and wherein the at least one additional parity bit is M−1 parity bits.5. The method of claim 1 , wherein the first number of variable nodes is 27 or 28 variable nodes.6. The method of claim 1 , ...

CODED BIT PUNCTURING FOR POLAR CODES

Aspects of the disclosure provide a method for polar code puncturing. The method can include receiving a mother polar code including a sequence of coded bits, the sequence of coded bits having indices {0, . . . , N−1} and including at least a first block of coded bits having indices {0, . . . , i−1}, a second block of coded bits having indices {i, . . . , i+k−1}, a third block of coded bits having indices {i+k, i+k+k−1}, interleaving the second block of coded bits with the third block of coded bits to form a rearranged sequence of coded bits including the N coded bits, and extracting the last M coded bits from the rearranged sequence of coded bits to generate a punctured code having a length of M. 1. A method for polar code puncturing , comprising:receiving a mother polar code including a sequence of coded bits, the sequence of coded bits having indices {0, . . . , N−1} and including at least a first block of coded bits having indices {0, . . . , i−1}, a second block of coded bits having indices {i, i+k−1}, a third block of coded bits having indices {i+k, i+k+k−1};interleaving the second block of coded bits with the third block of coded bits to form a rearranged sequence of coded bits including the N coded bits; andextracting the last M coded bits from the rearranged sequence of coded bits to generate a punctured code having a length of M.2. The method of claim 1 , wherein i=N/4 claim 1 , and i+k=N/2.5. The method of claim 1 , further comprising:storing the rearranged sequence of coded bits in a buffer,wherein extracting the last M coded bits from the rearranged sequence of coded bits includes reading the last M coded bits of the rearranged sequence of coded bits from the buffer.6. An apparatus for polar code puncturing claim 1 , comprising: receive a mother polar code including a sequence of coded bits, the sequence of coded bits having indices {0, . . . , N−1} and including at least a first block of coded bits having indices {0, . . . , i−1}, a second block of ...

Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals comprises an encoder encoding service data, a time interleaver interleaving the encoded service data, a mapper mapping the interleaved service data into a plurality of OFDM (Orthogonal Frequency Division Multiplex) symbols to build at least one signal frame, a frequency interleaver frequency interleaving data in the at least one signal frame by using a different interleaving-seed which is used for every OFDM symbol pair comprised of two sequential OFDM symbols, wherein the frequency interleaving is performed by using two memories, a modulator modulating the frequency interleaved data by an OFDM scheme and a transmitter transmitting the broadcast signals having the modulated data, wherein an interleaving-seed is generated based on a cyclic shift value and an FFT size of the modulating.

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder to encode service data corresponding to a number of physical paths, a time interleaver to time interleave the encoded service data in each physical path, a frame builder to build at least one signal frame including the time interleaved service data, a modulator to modulate data in the built at least one signal frame by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter to transmitting the broadcast signals having the modulated data. 110-. (canceled)11. An apparatus for receiving broadcast signals , the apparatus comprising:a tuner to receive the broadcast signals carrying at least one signal frame;a demodulator to demodulate the broadcast signals by an Orthogonal Frequency Division Multiplex (OFDM) scheme;a time deinterleaver to de-interleave data in the at least one signal frame based on a convolutional de-interleaver and a block de-interleaver,the convolutional de-interleaver to de-interleave the data in the at least one signal frame,the block de-interleaver to write the convolutional de-interleaved data to a memory based on a Time Interleaving (TI) block including a number of actual Forward Error Correction (FEC) blocks having the convolutional de-interleaved data, and to read the TI block from the memory; anda decoder to decode the time-de-interleaved data.12. A method of receiving broadcast signals , the apparatus comprising:receiving the broadcast signals carrying at least one signal frame;demodulating the broadcast signals by an Orthogonal Frequency Division Multiplex (OFDM) scheme;time de-interleaving data in the at least one signal frame based on a convolutional de-interleaving and a block de-interleaving,the convolutional de-interleaving de-interleaving the data in the at least one signal frame,the block de-interleaving writing the convolutional de-interleaved data ...

Groups of phase invariant codewords

Disclosed herein are a system, non-transitory computer-readable medium, and method for encoding and decoding information on a data bearing medium. A message comprising a bit string is read. A plurality of substrings in the message may be associated with a phase invariant codeword.

LINK BUDGET IMPROVEMENT IN PEER DISCOVERY

In an aspect, a method, an apparatus, and a computer program product for wireless communication are provided. The apparatus codes a peer discovery message for peer discovery. The apparatus generates a plurality of different redundancy versions of the coded peer discovery message. The apparatus transmits each of the different redundancy versions of the coded peer discovery message in a different allocated time period. In another aspect, a method, an apparatus, and a computer program product for wireless communication are provided. The apparatus receives at least one redundancy version of a coded peer discovery message. The apparatus attempts to decode the received at least one redundancy version of the coded peer discovery message. 1. A method of wireless communication of a user equipment (UE) , comprising:coding a peer discovery message for peer discovery;generating a plurality of different redundancy versions of the coded peer discovery message; andtransmitting each of the different redundancy versions of the coded peer discovery message in a different allocated time period.2. The method of claim 1 , wherein the coding the peer discovery message comprises appending cyclic redundancy check (CRC) bits to a peer discovery expression and encoding the peer discovery expression and the CRC bits.3. The method of claim 1 , wherein the generating the plurality of different redundancy versions comprises puncturing a different set of bits for each of the different redundancy versions of the coded peer discovery message.4. The method of claim 1 , further comprising receiving redundancy version information from a base station claim 1 , the redundancy version information including an indication of a transmission order of the different redundancy versions claim 1 , wherein each of the different redundancy versions is transmitted based on the transmission order indicated in the redundancy version information.5. The method of claim 1 , wherein each of the different redundancy ...

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder to encode service data corresponding to a number of physical paths, a time interleaver to time interleave the encoded service data in each physical path, a frame builder to build at least one signal frame including the time interleaved service data, a modulator to modulate data in the built at least one signal frame by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter to transmitting the broadcast signals having the modulated data. 110-. (canceled)11. An apparatus for receiving broadcast signals , the apparatus comprising:a receiver to receive the broadcast signals carrying at least one signal frame;a demodulator to demodulate the received broadcast signals by an OFDM (Orthogonal Frequency Division Multiplex) scheme;a time deinterleaver to time de-interleave data in at least one signal frame based on a convolutional de-interleaver and a block de-interleaver;wherein the convolutional de-interleaver performs de-interleaving over the data in at least one signal frame,wherein the block de-interleaver performs de-interleaving on the convolutional de-interleaved data based on a Time Interleaving (TI) block,wherein the TI block includes a number of actual Forward Error Correction (FEC) blocks having the convolutional de-interleaved data and zero or more virtual FEC blocks,wherein the number of virtual FEC blocks is equal to a difference between the number of actual FEC blocks of the TI block and a maximum number of FEC blocks of the TI block; anda decoder to decode the time-de-interleaved data.12. The apparatus of claim 11 , wherein the block de-interleaver performs interleaving by:writing the TI block into a memory; andreading out the written the TI block by skipping the zero or more virtual FEC blocks.13. A method of receiving broadcast signals claim 11 , the apparatus comprising: ...

PACKET RETRANSMISSION AND MEMORY SHARING

Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like. 1. A method of packet retransmission comprising:transmitting or receiving a plurality of packets;identifying at least one packet of the plurality of packets as a packet that should not be retransmitted.2105-. (canceled) This application is a Continuation of U.S. patent application Ser. No. 13/766,059, filed Feb. 13, 2013, now U.S. Pat. No. 8,645,784, which is a Continuation of U.S. patent application Ser. No. 12/783,758, filed May 20, 2010, now U.S. Pat. No. 8,407,546, which is a Continuation of U.S. patent application Ser. No. 12/295,828, filed Oct. 2, 2008, now U.S. Pat. No. 8,335,956, which is a national stage application under 35 U.S.C. 371 of PCT Application No. PCT/US2007/066522 having an international filing date of Apr. 12, 2007, which designated the United States, which PCT application claims the benefit of and priority under 35 U.S.C. § 119(e) to U.S. Patent Application Nos. 60/792,236, filed Apr. 12, 2006, entitled “xDSL Packet Retransmission Mechanism,” and 60/849,650, filed Oct. 5, 2006, entitled “xDSL Packet Retransmission Mechanism with Examples,” each of which are incorporated herein by reference in their entirety.This invention generally relates to communication systems. More specifically, an exemplary embodiment of this invention relates to retransmission of packets in a communication environment. An exemplary embodiment of this invention also relates to ...

Compact Low Density Parity Check (LDPC) Base Graph

A decoding method, an encoding method, a decoder and an encoder are disclosed. In an embodiment the decoding method includes receiving, at a receiver of a receiving side, signals from a transmitting side, the signals including a code word and decoding, at a decoder of the receiving side, the code word using a low density parity check (LDPC) code in which each n adjacent rows, n>1, in an extension part of a base parity check matrix (PCM) are orthogonal except for punctured information columns. 1. A decoding method comprising:receiving, at a receiver of a receiving side, signals from a transmitting side, the signals including a code word; anddecoding, at a decoder of the receiving side, the code word using a low density parity check (LDPC) code in which each n adjacent rows, n>1, in an extension part of a base parity check matrix (PCM) are orthogonal except for punctured information columns,wherein each two adjacent rows in a core matrix of the base PCM are orthogonal except for the punctured information columns and dual diagonal parity check columns.2. The method of claim 1 , wherein each m rows claim 1 , m>1 claim 1 , in the punctured information columns in the extension part of the base PCM have not more than 1 conflict.3. The method of claim 2 , wherein m=2.4. The method of claim 1 , wherein shifts of each 2 conflict cells in the punctured information columns of a labeled PCM in the extension part are equal.5. The method of claim 1 , wherein two last adjacent rows in a core matrix of the base PCM claim 1 , except for punctured information columns claim 1 , have shifts equal to zero.6. The method of claim 1 , wherein n=4.9. An encoding method comprising:encoding, at an encoder of a transmitting side, information bits into a code word; andtransmitting, at a transmitter of the transmitting side, signals to a receiving side, the signals including the code word, wherein the information bits are encoded using a LDPC code in which each n adjacent rows, n>1, in an ...