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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 3861. Отображено 100.
08-03-2012 дата публикации

Decoder based data recovery

Номер: US20120060074A1
Автор: Engling Yeo
Принадлежит: MARVELL WORLD TRADE LTD

Systems, methods, and other embodiments associated with decoder based data recovery are described. According to one embodiment, an apparatus includes a decoder configured to perform a decoding process on codewords to verify that the codewords meet coding constraints. The decoder includes a recovery unit configured to store recovery instructions for performing a modified decoding process. The recovery unit is further configured to execute the stored recovery instructions when a decoded codeword fails to meet the coding constraints.

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Номер записи: 1
05-07-2012 дата публикации

Decoding device, decoding method, and program

Номер: US20120173954A1
Автор: Hiroyuki Yamagishi
Принадлежит: Sony Corp

A decoding device includes: a determination unit that determines whether or not a decoding ending condition is satisfied at an interval shorter than an interval of one decoding process in repeated decoding and ends the process in the middle of the one decoding process in a case where the decoding ending condition is satisfied.

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Номер записи: 2
02-08-2012 дата публикации

Information reproduction apparatus and information reproduction method

Номер: US20120198304A1
Автор: Kenji Yoshida, Yosuke Kondo
Принадлежит: Toshiba Corp

According to one embodiment, an information reproduction apparatus includes a calculator, selector, and decoder. The calculator calculates parity-check passing ratios based on a check matrix of an LDPC code for code word candidates included in a reproduced signal. The selector selects one of the code word candidates based on the parity-check passing ratios calculated by the calculator. The decoder decodes the code word candidate selected by the selector by an iterative decoding process.

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Номер записи: 3
02-08-2012 дата публикации

Soft decoding systems and methods for flash based memory systems

Номер: US20120198314A1
Автор: Gregory Burd, Xueshi Yang
Принадлежит: MARVELL WORLD TRADE LTD

Systems and methods for decoding data using a decoder that includes a primary decoder and an auxiliary decoder are provided. A codeword is retrieved from a storage device. A primary decoder attempts to decode the codeword using hard data associated with the codeword. If the primary decoder fails, an indication of the failure may be received by a decoder controller, which activates an auxiliary decoder. The auxiliary decoder attempts to decode the codeword using either hard data or soft data associated with the codeword. The primary decoder is designed to consume less power, consume less silicon area, and have a higher throughput than the auxiliary decoder. The primary decoder is configured to have a higher probability of successfully decoding a codeword, stored in the storage device, in the first attempt to decode the codeword, than failing and requiring the auxiliary decoder to decode the codeword.

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Номер записи: 4
27-09-2012 дата публикации

Error correction method and device

Номер: US20120246537A1
Автор: Kazuo Kubo, Takashi Mizuochi
Принадлежит: Mitsubishi Electric Corp

Provided is an error correction method for an optical communication system that transmits a transmission frame formed of information data added with an overhead and an error correction code, the error correction method including adjusting a size of an FEC redundant area of an FEC frame for storing client signals of different signal types in accordance with the client signals so that transmission rates of the FEC frame for the respective client signals have an approximately N-multiple relationship (N is a positive natural number). With this, it is possible to obtain an error correction method and device capable of providing a high-quality and high-speed optical communication system without performance degradation caused by jitter or the like and with the common use of circuits having a reduced circuit scale.

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Номер записи: 5
04-10-2012 дата публикации

Software Defined Radio for Universal Demodulation of Digital and Analog TV Signals

Номер: US20120249888A1
Автор: Anindya SAHA, Gururaj Padaki, Hemant Mallapur, Parag Naik, Sunil HR
Принадлежит: Saankhya Labs Pvt Ltd

A Software Defined Radio (SDR) subsystem capable of supporting a multiple communication standards and platforms for modulation, demodulation and trans-modulation of an input signal is provided. The SDR subsystem includes a Signal Conditioning Cluster (SCC) unit that includes a signal conditioning CPU adapted for sample based signal processing, a Signal Processing Cluster (SPC) unit that includes a signal processing CPU adapted for block based signal processing, and a Channel Codec Cluster (CCC) unit that performs a channel encoding or a channel decoding operation.

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Номер записи: 6
18-10-2012 дата публикации

Header encoding/decoding

Номер: US20120266042A1
Автор: Ba-Zhong Shen, Trachewsky Jason A
Принадлежит: Broadcom Corp

In a communication device that is operative to perform decoding, a log-likelihood ratio (LLR) circuitry operates to calculate LLRs corresponding to every bit location within a received bit sequence. This received bit sequence may include a header and a data portion (both of which may be included within a frame that also includes a preamble). The header is composed of information bits, a duplicate of those information bits (such as may be generated in accordance with repetition encoding), and redundancy bits. The header includes information corresponding to frame or data including frame length, a code type by which the data are encoded, a code rate by which the data are encoded, and a modulation by which symbols of the data are modulated. Once the header has been decoded, then the data corresponding thereto is decoded by a block decoder circuitry to make estimates of that data.

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Номер записи: 7
08-11-2012 дата публикации

Decoding method and device for concatenated code

Номер: US20120284584A1
Автор: Nanshan Cao, Tao Zhang, Yangzhong Yao, Yueyi You
Принадлежит: ZTE Corp

Disclosed are a decoding method and device for concatenated code, for the decoding of concatenated code composed of low density parity code (LDPC) and Reed-Solomon (RS) code. The method includes: carrying out LDPC soft decision iterative decoding on bit de-interleaved data flow, and carrying out check decision on LDPC codeword obtained from decoding by using a check matrix; carrying out de-byte-interleave on an information bit of the LDPC codeword obtained from decoding and converting check information of the LDPC codeword into puncturing information of RS codeword; selecting a decoding mode according to the puncturing information of the RS codeword to carry out RS decoding. By way of the solution of the present invention, the RS decoding performance can be improved without increasing the computation complexity, thus greatly improving the receiving performance of the CMMB terminal as compared to the conventional method.

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Номер записи: 8
13-12-2012 дата публикации

Transmitter and method for transmitting data block in wireless communication system

Номер: US20120314801A1
Автор: Jong Ee OH, Min Ho CHEONG, Sok Kyu Lee
Принадлежит: Electronics and Telecommunications Research Institute ETRI

Provided are a transmitter and a method for transmitting a data block in a wireless communication system. The method comprises the following steps: deciding the number of bits (s) and encoders (NES) to allocate to one axis of a signal constellation; encoding an information bit based on the s and the NES and generating a coded block; parsing the coded block based on the s and the NES and generating a plurality of frequency sub-blocks; and transmitting the plurality of frequency sub-blocks to a receiver.

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Номер записи: 9
13-12-2012 дата публикации

Transmitter and method for transmitting data block in wireless communication system

Номер: US20120314802A1
Автор: Jong Ee OH, Min Ho CHEONG, Sok Kyu Lee
Принадлежит: Electronics and Telecommunications Research Institute ETRI

Provided are a transmitter and a method for transmitting a data block in a wireless communication system. The method comprises the following steps: encoding an information bit and generating a block coded with an NCBPSS bit; generating two sub-blocks by parsing the coded block; and transmitting the two sub-blocks to the transmitter. By preventing the bits that are contiguous to the encoding block from having continuous identical reliabilities on a signal constellation, the deterioration of the decoding performance of the transmitter can be prevented.

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Номер записи: 10
03-01-2013 дата публикации

Systems and methods for receiving and transferring video information

Номер: US20130002965A1
Автор: Eric Chan, Hiroshi Suzuki, Prijesh Patel, Sack Lee Chan
Принадлежит: Broadcom Corp

Devices and methods for receiving, processing and formatting digital video. The devices may include a single semiconductor chip on which is imprinted a radio frequency signal tuner module and a display interface module. The display interface module may be configured to receive programming information from the radio frequency signal tuner module. The display interface module may be configured to communicate the programming information to a digital video recorder. The radio frequency tuner module may include a first radio frequency input channel and a second radio frequency input channel. The radio frequency signal tuner module may include a system oscillator and a phase-locked loop (“PLL”) circuit configured to generate a clock signal. The phase-locked loop circuit may be configured to transmit the signal to the display interface module and to any other suitable modules on the chip.

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Номер записи: 11
18-04-2013 дата публикации

Apparatus and method for transmitting/receiving forward error correction packet in mobile communication system

Номер: US20130094502A1
Автор: Sung-hee Hwang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An apparatus and method for transmitting/receiving a Forward Error Correction (FEC) packet in a mobile communication system are provided. In the FEC packet transmission method, an FEC packet transmission apparatus transmits an FEC delivery block to an FEC packet reception apparatus. The FEC delivery block includes N payloads. Each of the N payloads includes a payload header. Each payload header included in each of C payloads among the N payloads includes packet oriented header information and an FEC delivery block oriented header information fragment. The packet oriented header information is applied to a related payload, and the FEC delivery block oriented header information fragment is generated by fragmenting FEC delivery block oriented header information applied to the N payloads.

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Номер записи: 12
06-06-2013 дата публикации

Wireless Transmission Reliability

Номер: US20130145236A1
Автор: Steven D. Baker
Принадлежит: Welch Allyn Inc

A method for performing error correction during a transmission of physiological data includes two or more data packets that are sent from a first electronic computing device to a second electronic computing device. Each of the data packets includes physiological data. Each of the data packets has a first packet size. Each of the data packets includes error correction information. The error correction information for each of the two or more packets is distributed across the two or more data packets.

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Номер записи: 13
20-06-2013 дата публикации

Systems and methods for changing decoding parameters in a communication system

Номер: US20130156118A1
Автор: Christopher H. Dick
Принадлежит: Xilinx Inc

A communication system includes an iterative multi-stage decoder that may be dynamically configured to achieve a particular bit-error-rate. In one embodiment, a circuit comprises a first decoder block and a second decoder block to decode data received over a communication channel. A control circuit may change a number of iterations performed by the decoder blocks to decode received data based on a specified bit error rate and a detected signal-to-noise ratio of said received data. The number of computational units used in the decoders may be changed dynamically to achieve desired system performance. In one embodiment, resources are allocated based on a system initiating the connection. Programmable circuits are used in some embodiments to reconfigure the multi-stage decoder.

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Номер записи: 14
18-07-2013 дата публикации

Joint encoding and decoding methods for improving the error rate performance

Номер: US20130185610A1
Автор: Youssouf Ould-Cheikh-Mouhamedou
Принадлежит: KING SAUD UNIVERSITY

Joint encoding and decoding methods for improving the error rate performance are described. In one aspect, the systems and methods determine values and positions of L desired symbols. In encoding unit receives data symbols for encoding. The encoding unit calculates, responsive to receiving the data symbols, values and positions of H help symbols. The encoding unit inserts the help symbols into the data symbols at respective help symbols positions, thereby generating new data symbols. Encoding unit encodes the new data symbols to produce a codeword C′ that contains the L desired symbols. The codeword C′ is communicated to a decoder that is instructed to explore some or all L desired symbols in C′.

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Номер записи: 15
12-09-2013 дата публикации

Apparatuses and methods for combining error coding and modulation schemes

Номер: US20130238952A1
Автор: Chandra C. Varanasi
Принадлежит: Micron Technology Inc

Methods and apparatuses for combining error coding and modulation schemes are described herein. One or more methods include encoding data using linear error correcting code, modulating the encoded data, writing the modulated data to memory, and decoding the written data using a Viterbi algorithm and a linear error correcting code decoder.

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Номер записи: 16
12-09-2013 дата публикации

Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code

Номер: US20130238953A1
Автор: Blanksby Andrew J., Shen Ba-Zhong, Trachewsky Jason A.
Принадлежит: BROADCOM CORPORATION

Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform encoding of respective information bit groups using more than one type of LDPC codes. A switching module can select any one of the LDPC codes within an in-place LDPC code for use by an LDPC encoder circuitry to generate an LDPC coded signal. Depending on which sub-matrices of a superimposed LDPC matrix are enabled or disabled, one of the LDPC matrices from within an in-place LDPC code matrix set may be selected. A corresponding, respective generator matrix may be generated from each respective LDPC matrix. Selection among the various LDPC codes may be in accordance with a predetermined sequence, of based operating conditions of the communication device or communication system. 1. An apparatus , comprising:an LDPC (Low Density Parity Check) decoder circuitry to decode:a first LDPC coded signal based on a first LDPC code using a first LDPC matrix, based on a first configuration of a superimposed LDPC matrix, to generate a first plurality of estimates of a first plurality of information bits encoded therein; anda second LDPC coded signal based on a second LDPC code using a second LDPC matrix, based on a second configuration of the superimposed LDPC matrix, to generate a second plurality of estimates of a second plurality of information bits encoded therein, wherein the apparatus compliant to operate based on a communication standard or recommended practice that includes a plurality of LDPC codes that includes the first LDPC code having a first code rate and the second LDPC code having a second code rate that is different than the first code rate.2. The apparatus of claim 1 , wherein:the first LDPC code having a first plurality of sub-matrix rows; andthe second LDPC code having a second ...

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Номер записи: 17
19-09-2013 дата публикации

Data processing device and data processing method

Номер: US20130246883A1
Автор: LACHLAN Bruce Michael, Osamu Shinya, Takashi Yokokawa
Принадлежит: Sony Corp

A data processing device and a data processing method that can readily process control data having its PAPR improved. In a transmission device, a padder pads control data necessary for demodulation with zeros as dummy data, and a scrambler scrambles the padded control data (post-padding control data). A replacement unit replaces scrambled dummy data in the scrambled post-padding control data with the dummy data, and a BCH encoder and an LDPC encoder perform BCH encoding and LDPC encoding as error correction encoding on the replacement data obtained through the replacement. A shortening unit performs shortening by deleting the dummy data contained in the LDPC code and puncturing the parity bits of the LDPC code. The device can be applied in cases where control data is subjected to error correction encoding and is then transmitted, for example.

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Номер записи: 18
26-09-2013 дата публикации

Systems and Methods for Variable Rate Coding in a Data Processing System

Номер: US20130254616A1
Автор: Shaohua Yang
Принадлежит: LSI Corp

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate coding in a data processing system.

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Номер записи: 19
03-10-2013 дата публикации

Multi-user communication using sparse space codes

Номер: US20130259149A1
Автор: Alireza Bayesteh, Amin Mobasher, Sagar Dhakal, Steve Hranilovic
Принадлежит: Individual

Multi-user sparse space codes are proposed as a new transmission scheme for uplink communication over a multi-user multiple-input-multiple-output (MIMO) communication channel.

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Номер записи: 20
03-10-2013 дата публикации

Coding schemes for wireless communication transmissions

Номер: US20130262961A1
Автор: Aamod Dinkar Khandekar, Thomas Joseph Richardson
Принадлежит: Qualcomm Inc

Systems and methodologies are described that facilitate transmitting low-density parity-check encoded communications in a wireless communications network and incrementing such codes in response to requests from receiving devices. The LDPC codes can have associated constraints allowing the codes to be error corrected upon receipt. The requests for incremented codes can be in cases of low transmission power or high interference, for example, where the original code can be too error-ridden to properly decode. In this case, additional nodes can be added to current and/or subsequent communications to facilitate adding a more complex constraint to the LDPC code. In this regard, the large codes can require less validly transmitted nodes to predict error-ridden values as the additional constraint renders less ambiguity in possible node value choices.

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Номер записи: 21
17-10-2013 дата публикации

Sparse superposition encoder and decoder for communications system

Номер: US20130272444A1
Автор: Andrew R. Barron, Antony Joseph
Принадлежит: YALE UNIVERSITY

A computationally feasible encoding and decoding arrangement and method for transmission of data over an additive white Gaussian noise channel with average codeword power constraint employs sparse superposition codes. The code words are linear combinations of subsets of vectors from a given dictionary, with the possible messages indexed by the choice of subset. An adaptive successive decoder is shown to be reliable with error probability exponentially small for all rates below the Shannon capacity.

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Номер записи: 22
07-11-2013 дата публикации

Zero-one balance management in a solid-state disk controller

Номер: US20130297986A1
Автор: Earl T. Cohen
Принадлежит: LSI Corp

An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.

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Номер записи: 23
05-12-2013 дата публикации

Magnetic tape recording in data format using an efficient reverse concatenated modulation code

Номер: US20130326311A1
Автор: Robert A. Hutchins, Roy D. Cideciyan, Sedat Oelcer, Thomas Mittleholzer
Принадлежит: International Business Machines Corp

In one embodiment, a method for writing data to a magnetic tape utilizing a rate-(232/234) reverse concatenated modulation code includes receiving a data stream comprising one or more data sets, separating each data set into a plurality of sub data sets, encoding each sub data set with a C2 encoding, encoding each C2-encoded sub data set with the modulation code, encoding each modulated sub data set with a C1 encoding, and simultaneously writing the encoded modulated sub data sets to data tracks of the magnetic tape. Other methods for writing data to a magnetic tape utilizing a rate-(232/234) reverse concatenated modulation code are described according to various other embodiments.

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Номер записи: 24
26-12-2013 дата публикации

Error correction device, error correction method and computer program product

Номер: US20130346825A1
Автор: Atsuhiro Kinoshita, Jiezhi Chen, Takahiro Kurita, Takao Marukame, Yoshifumi Nishi, Yusuke Higashi, Yuuichiro Mitani
Принадлежит: Toshiba Corp

According to an embodiment, an error correction device includes first calculators, second calculators, estimators, and an inverter. Each first calculator calculates a first message representing a probability that 1-bit data that is input in a corresponding variable node is 1, Each second calculator calculates a second message representing a probability that a value of the data input to the variable node is 1 for each of two or more variable nodes connected to the check node by using the first, messages of the variable nodes connected to the check node. Each estimator estimates a true value of the data input to the variable node to generate an estimated value by using the first and second messages. The inverter inverts the estimated value associated with at least one of the variable nodes with a probability higher than 0 and lower than 1.

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Номер записи: 25
16-01-2014 дата публикации

Accelerating error-correction decoder simulations with the addition of arbitrary noise

Номер: US20140019825A1
Автор: Aleksey Alexandrovich Letunovskiy, Alexander Nikolaevich Filippov, Denis Vladimirovich Parkhomenko, Dmitry N. Babin, Pavel Aleksandrovich Aliseychik
Принадлежит: LSI Corp

In one embodiment, a simulator, e.g., for a hard-disk drive selects for testing a signal-to-noise ratio (SNR) value from a range of ratios and an error-correction codeword pattern from a range of codeword patterns. The simulator simulates a communications channel by applying write noise, inter-symbol interference, and read noise to the codeword pattern to generate a noisy signal. In addition, the simulator adds arbitrary-noise to the codeword to accelerate the speed of the simulation. The arbitrary noise increases the probability of converging on a trapping set and does not represent any noise introduced by the communications channel. The simulator attempts to decode the noisy signal, and if decoding is unsuccessful, then the simulator increments an error counter corresponding to the selected signal-to-noise ratio. This process is repeated for all possible combinations of signal-to-noise ratio values and codeword patterns to determine the error rate for all of the signal-to-noise ratio values.

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Номер записи: 26
06-02-2014 дата публикации

Data independent error computation and usage with decision directed error computation

Номер: US20140040706A1
Автор: Jason Bellorado, Marcus Marrow, Zheng Wu
Принадлежит: SK Hynix Memory Solutions America Inc

An analog front end is adjusted by determining a signal quality based at least in part on digital sample(s). If the signal quality satisfies one or more criteria, a data independent gain gradient and a data independent offset gradient are selected to adjust the analog front end, where the two gradients are generated without taking into consideration an instantaneous value of an expected signal. If the signal quality does not satisfy the criteria, a decision directed gain gradient and a decision directed offset gradient are selected to adjust the analog front end, where the two gradients are generated based at least in part on decision(s).

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Номер записи: 27
06-03-2014 дата публикации

LDPC Decoder Irregular Decoding of Regular Codes

Номер: US20140068381A1
Автор: Zhang Fan
Принадлежит:

The present inventions are related to systems and methods for irregular decoding of regular codes in an LDPC decoder, and in particular to allocating decoding resources based in part on data quality. 1. An apparatus comprising:a low density parity check decoder operable to iteratively generate and process check node to variable node messages and variable node to check node messages between a plurality of check nodes and variable nodes, and to initially allocate more processing resources to variable node values identified as good quality than to variable node values identified as poor quality, wherein the low density parity check decoder is operable to process a regular low density parity check code.2. The apparatus of claim 1 , further comprising a quality determination circuit operable to calculate a quality metric for data symbols at an input to the low density parity check decoder.3. The apparatus of claim 2 , further comprising a data detector operable to yield log likelihood ratio values for the data symbols claim 2 , wherein the quality determination circuit is operable to calculate the quality metric for the data symbols based on the log likelihood ratio values.4. The apparatus of claim 2 , wherein the quality determination circuit is operable to calculate an information divergence for the data symbols.5. The apparatus of claim 1 , further comprising a comparison circuit operable to compare a quality metric for each data symbol at an input to the low density parity check decoder with a quality threshold to identify the variable node values for the data symbols as good quality or as poor quality.6. The apparatus of claim 5 , wherein the comparison circuit comprises a scheduler in the low density parity check decoder.7. The apparatus of claim 1 , wherein the low density parity check decoder is operable to freeze the variable node values identified as poor quality during a first portion of a plurality of decoding iterations as the variable node values identified ...

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Номер записи: 28
05-01-2017 дата публикации

VARIABLE CODE RATE SOLID-STATE DRIVE

Номер: US20170004031A1
Автор: Dick Christopher H.
Принадлежит: XILINX, INC.

An apparatus, as well as a method therefor, relates generally to managing reliability of a solid state storage. In such an apparatus, there is a memory controller for providing a code rate. An encoder is for receiving input data and the code rate for providing encoded data. The solid-state storage is for receiving and storing the encoded data. A decoder is for accessing the encoded data stored in the solid-state storage and for receiving the code rate for providing decoded data of the encoded data accessed. The decoded data is provided as soft decisions representing probabilities of the decoded data. The memory controller is for receiving the decoded data for adjusting the code rate responsive to the probabilities of the decoded data. 1. A method for managing reliability of a solid-state storage , comprising:reading encoded data stored in the solid-state storage;decoding the encoded data accessed to provide decoded data as soft decisions representing probabilities of the decoded data;assessing the probabilities of the decoded data; andadjusting a code rate of an encoder and a decoder responsive to the assessment.2. The method according to claim 1 , wherein the code rate is for a linear error correcting code.3. The method according to claim 2 , wherein the solid-state storage comprises memory cells selected from a group consisting of multi-level cells claim 2 , binary cells claim 2 , triple-level cells claim 2 , and single-level cells for storage of the encoded data.4. The method according to claim 2 , wherein:the encoder is a Low-Density Parity-Check encoder; andthe decoder is an LDPC decoder.5. The method according to claim 1 , further comprising:encoding input data with the encoder to provide the encoded data; andwriting the encoded data to the solid-state storage.6. The method according to claim 5 , wherein the accessing comprises reading a predefined amount of the encoded data from the solid-state storage.7. The method according to claim 6 , wherein the ...

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Номер записи: 29
04-01-2018 дата публикации

Masking Defective Bits in a Storage Array

Номер: US20180004594A1
Автор: Hari Kannan, John D. Davis, John Hayes, Nenad Miladinovic, Zhangxi Tan
Принадлежит: Pure Storage Inc

A method of failure mapping is provided. The method includes determining that a non-volatile memory block in the memory has a defect and generating a mask that indicates the non-volatile memory block and the defect. The method includes reading from the non-volatile memory block with application of the mask, wherein the reading and the application of the mask are performed by the non-volatile solid-state storage.

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Номер записи: 30
02-01-2020 дата публикации

ERROR CORRECTION DECODING AUGMENTED WITH ERROR TRACKING

Номер: US20200004628A1
Автор: Ben-Rubi Refael, SHARON ERAN
Принадлежит:

Enhanced error correction for data stored in storage devices are presented herein. A storage controller retrieves an initial encoded data segment stored on a storage media, computes information relating to errors resultant from decoding the initial encoded data segment, and stores the information in a cache. The storage controller retrieves subsequent encoded data segments stored on the storage media, augments a decoder using at least the information retrieved from the cache, and decodes the subsequent encoded data with the decoder to produce resultant data. 1. An apparatus , comprising:a storage media configured to store encoded data;a cache memory configured to store information relating to errors resultant from decoding one or more prior read operations directed to the encoded data; anda decoder configured to decode the encoded data retrieved from the storage media, the decoding augmented by the information relating to the errors.2. The apparatus of claim 1 , wherein the information relating to the errors comprises at least one error location index indicating decoding error location information relating to at least a portion of the encoded data read from the storage media; andwherein the decoding is augmented by the at least one error location index maintained in the cache memory.3. The apparatus of claim 2 , wherein the decoder is further configured to:augment decoding of the encoded data by at least initializing reliability parameters in a low-density parity-check (LDPC) scheme with the error location information indicated in the at least one error location index.4. The apparatus of claim 2 , wherein the decoder is further configured to:determine further error location information resultant from decoding the encoded data; andbased at least on the further error location information differing from the at least one error location index, update the at least one error location index with the further error location information.5. The apparatus of claim 4 , wherein ...

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Номер записи: 31
01-01-2015 дата публикации

MANUFACTURING TESTING FOR LDPC CODES

Номер: US20150006981A1
Автор: Bellorado Jason, Kou Yu, Marrow Marcus, Zeng Lingqi
Принадлежит:

A storage system includes a channel detector, an LDPC decoder, and an erasure block. The channel detector is configured to receive data corresponding to data read from a storage and output an LLR signal. The LDPC decoder is configured to receive the LLR signal and output a feedback signal to the channel detector. The erasure block is configured to erase at a portion of at least one of the LLR signal and the feedback signal. A method for testing includes generating an error rate function corresponding to an erasure pattern. The function is a function of a number of LDPC iterations. The method includes determining testing parameters at least in part based on the error rate function, wherein the testing parameters comprise a testing number of LDPC iterations, a passing error rate, and the erasure pattern. The method includes testing storage devices using the testing parameters. 1. A storage system , comprising:a channel detector configured to receive data corresponding to data that is read from a storage and output a log-likelihood ratio (LLR) signal;a low-density parity-check (LDPC) decoder configured to receive the LLR signal and output a feedback signal to the channel detector;an erasure block configured to erase at a portion of at least one of the LLR signal and the feedback signal.2. The system of claim 1 , wherein erasing includes reducing the amplitude or zeroing out the at least one of the LLR signal and the feedback signal.3. The system of claim 1 , wherein erasing comprises erasing in an evenly distributed erasure pattern.4. The system of claim 1 , wherein erasing comprises erasing a window of the at least one of is the LLR signal and the feedback signal.5. The system of claim 1 , wherein erasing is in response to an input signal to the storage system.6. The system of claim 1 , wherein erasing is performed in response to the system being unable to decode at least a portion of the data read from the storage claim 1 , wherein erasing is performed according to ...

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Номер записи: 32
07-01-2016 дата публикации

NON-VOLATILE MEMORY CONTROLLER WITH ERROR CORRECTION (ECC) TUNING VIA ERROR STATISTICS COLLECTION

Номер: US20160006462A1
Автор: BUXTON Neil, HANHAM Paul Edward, SYMONS David Malcolm
Принадлежит:

A non-volatile memory controller for a solid state drive includes a soft-decision LDPC decoder. The soft-decision LDPC decoder includes a probability generation module. A processor reads collected statistics collated from decoded frames and tunes the performance of the soft-decision LDPC decoder performance. Additional parameters may also be taken into account, such as the scramble seed and the type of non-volatile memory. An asymmetry in errors may also be detected and provided to a hard-decision LDPC decoder to adjust its performance. 1. A method of decoding non-volatile memory pages , comprising:monitoring, during use of a non-volatile memory controller, statistical errors in a decoded output of a soft-decision Low Density Parity Check Decoder (LDPC) decoder utilizing a set of soft-decision read values to determine a bit value; andgenerating updates, in response to the monitored statistical errors, for a probability lookup table (LUT) used by the soft-decision LDPC decoder to determine a transformation between the set of soft-decision read values and a probability of a bit having a particular binary value.2. The method of claim 1 , wherein the monitoring and generating of updates is performed to adapt to aging related changes in multi-level cell threshold voltage distributions of the non-volatile memory.3. The method of claim 2 , wherein the monitoring and generating is performed periodically over the lifetime of the non-volatile memory.4. The method of claim 1 , wherein the probability LUT determines the transformation based on the monitored statistical errors and a set of parameters for non-volatile memory pages being decoded that includes at least one of a type of page claim 1 , a scramble seed type claim 1 , and whether hard or soft information is read from the non-volatile memory.50110. The method of claim 1 , wherein the soft-decision decoder performs (2−1) (2 to the power N claim 1 , minus 1) soft read decision reads claim 1 , the results of which are ...

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Номер записи: 33
04-01-2018 дата публикации

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 4/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

Номер: US20180006663A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, PARK Sung-Ik
Принадлежит:

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The LDPC encoding method of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 17280 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1800 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 45720.3. The LDPC encoding method of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 17280 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1800 claim 2 , by the CPM size.4. The LDPC encoding method of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The LDPC encoding method of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of U.S. patent application Ser. No. 14/496,654, filed on Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106180 and 10-2014-0120014, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in their entirety.The present ...

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Номер записи: 34
04-01-2018 дата публикации

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

Номер: US20180006665A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, LEE Jae-Young, PARK Sung-Ik
Принадлежит:

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A BICM device , comprising:an error-correction coder configured to output a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15;a bit interleaver configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; anda modulator configured to perform 64-symbol mapping after generating the interleaved codeword, {'br': None, 'i': Y', '=X', 'j≦N, 'sub': j', 'π(j)', 'group, '0≦'}, 'wherein the interleaving is performed using the following equation using permutation order{'sub': j', 'j, 'where Xis the j-th bit group, Yis an interleaved j-th bit group, and π(j) is a permutation order for bit group-based interleaving.'}2. The BICM device of claim 1 , wherein the permutation order corresponds to an interleaving sequence represented by the following{'br': None, 'interleaving sequence={74 72 104 62 122 35 130 0 95 150 139 151 133 109 31 59 18 148 9 105 57 132 102 100 115 101 7 21 141 30 8 1 93 92 163 108 52 159 24 89 117 88 178 113 98 179 144 156 54 164 12 63 39 22 25 137 13 41 44 80 87 111 145 23 85 166 83 55 154 20 84 58 26 126 170 103 11 33 172 155 116 169 142 70 161 47 3 162 77 19 28 97 124 6 168 107 60 76 143 121 42 157 65 43 173 56 171 90 131 119 94 5 68 138 149 73 67 53 61 4 86 99 75 36 15 48 177 167 174 51 176 81 120 158 123 34 49 ...

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Номер записи: 35
07-01-2021 дата публикации

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 3/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME

Номер: US20210006265A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, LEE Jae-Young, LIM Bo-Mi, PARK Sung-Ik
Принадлежит:

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation. 1. A bit-interleaved coded modulation (BICM) reception method , comprising:performing demodulation corresponding to quadrature phase shift keying (QPSK);performing group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; andrestoring information bits by low-density parity check (LDPC) decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 16200 and a code rate of 3/15,wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception method of claim 1 , wherein the group-unit deinterleaving corresponds to a reverse process of interleaving performed by using a permutation order claim 1 , andthe permutation order corresponds to an interleaving sequence represented by the following interleaving sequence:{15 22 34 19 7 17 28 43 30 32 14 1 11 0 3 9 10 38 24 4 23 18 27 39 29 33 8 2 40 21 20 36 44 12 37 13 35 6 31 26 16 25 42 5 41}.3. The BICM reception method of claim 2 , wherein the parallel factor is 360 claim 2 , and the group includes 360 values.5. An apparatus for transmitting a broadcast signal claim 2 , comprising:a low-density parity check (LDPC) encoder configured to encode a low-density parity check (LDPC ...

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Номер записи: 36
07-01-2021 дата публикации

MOBILE COMMUNICATION SYSTEM USING SUBCODING TECHNIQUES

Номер: US20210006351A1
Автор: Drewes Christian, Mueck Markus Dominik, Sagi Mark
Принадлежит:

The disclosure relates to a mobile communication system including: a first transmission path configured to transmit a message according to a first radio access technology; a second transmission path configured to transmit the message according to a second radio access technology; and an encoder configured to encode the message by a code before transmission of the message over the first transmission path and the second transmission path, wherein the code comprises at least two subcodes, and wherein the encoder is configured to encode the message intended for transmission over the first transmission path with a first subcode of the at least two subcodes and to encode the message intended for transmission over the second transmission path with a second subcode of the at least two subcodes. 125.-. (canceled)26. A mobile communication system , comprising:a first transmission path configured to transmit a message according to a first radio access technology;a second transmission path configured to transmit the message according to a second radio access technology; andan encoder configured to encode the message via a code block before transmission of the message over the first transmission path and the second transmission path,wherein the code block comprises at least a first code block portion and a second code block portion, andwherein the encoder is configured to encode the message intended for transmission over the first transmission path with the first code block portion, and to encode the message intended for transmission over the second transmission path with the second code block portion.27. The mobile communication system of claim 26 , wherein a channel code of the first radio access technology is a Low Density Parity Check (LDPC) code.28. The mobile communication system of claim 26 , wherein at least one of the first radio access technology or the second radio access technology is a millimeter wave radio access technology.29. The mobile communication system of ...

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Номер записи: 37
03-01-2019 дата публикации

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

Номер: US20190007064A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, LOBETE Daniel Ansorregui, MOUHOUCHE Belkacem, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The receiving apparatus of claim 1 , wherein each of the plurality of groups comprises 360 values.3. The receiving apparatus of claim 1 , wherein π(j) is determined based on at least one of the code length claim 1 , a modulation method and the code rate. This is a continuation of U.S. patent application Ser. No. 15/435,042, filed Feb. 16, 2017, which is a continuation of U.S. patent application Ser. No. 15/130,204, filed on Apr. 15, 2016, issued as U.S. Pat. No. 9,692,454 on Jun. 27, 2017, which is a continuation of U.S. patent application Ser. No. 14/625,862, filed Feb. 19, 2015, issued as U.S. Pat. No. 9,602,137 on Mar. 21, 2017, which claims priority from U.S. Provisional Application No. 61/941,676 filed on Feb. 19, 2014, U.S. Provisional Application No. 62/001,170 filed on May 21, 2014, and Korean Patent Application No. 10-2015-0000671 filed on Jan. 5, 2015. The entire disclosures of the prior applications are considered part of the disclosure of this continuation application, and are hereby incorporated by reference.Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus and an interleaving method thereof, and more particularly, to a transmitting apparatus which processes data and transmits the data, and an interleaving method thereof.In the 21st century information-oriented society, broadcasting communication services are moving into the era of digitalization, ...

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Номер записи: 38
02-01-2020 дата публикации

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

Номер: US20200007165A1
Автор: IKEGAYA Ryoji, Shinohara Yuji, Yamamoto Makiko
Принадлежит: SONY CORPORATION

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 or 12/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code. This is a continuation of U.S. application Ser. No. 14/905,213, filed Jan. 14, 2016, which is a U.S. National Stage Application of International Application No. PCT/JP2015/063250, filed May 8, 2015, which is based on and claims priority to Japanese Application No. 2014-104806, filed May 21, 2014, the entire contents of each of which are incorporated herein by reference.The present technology relates to a data processing device and a data processing method, and more particularly, a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code, for example.Some of the information disclosed in this specification and the drawings was provided by Samsung Electronics Co., Ltd. (hereinafter referred to as Samsung), LG Electronics Inc., NERC, and CRC/ETRI (indicated in the drawings).A low density parity check (LDPC) code has a high error correction capability, and in recent years, the LDPC code has widely been employed in transmission schemes of digital broadcasting such as Digital Video Broadcasting (DVB)-S.2, DVB-T.2, and DVB-C.2 of Europe and the like, or Advanced Television Systems Committee (ATSC) 3.0 of the USA and the like (for example, see Non-Patent Literature 1).From a recent study, it is known that performance near a Shannon limit is obtained from the LDPC code when ...

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Номер записи: 39
02-01-2020 дата публикации

Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 2/15 and 256-symbol mapping, and bit interleaving method using same

Номер: US20200007166A1
Автор: Bo-Mi Lim, Heung-Mook Kim, Jae-Young Lee, Nam-Ho Hur, Sun-Hyoung Kwon, Sung-Ik Park
Принадлежит: Electronics and Telecommunications Research Institute ETRI

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

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Номер записи: 40
02-01-2020 дата публикации

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

Номер: US20200007167A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The apparatus of claim 1 , wherein each of the plurality of groups comprises 360 values.3. The apparatus of claim 1 , wherein the π(j) is determined based on at least one of the code length claim 1 , a modulation method for the mapping and the code rate.5. The method of claim 4 , wherein each of the plurality of groups comprises 360 values.6. The method of claim 4 , wherein the π(j) is determined based on at least one of the code length claim 4 , a modulation method for the mapping and the code rate. This is a continuation of U.S. application Ser. No. 15/639,614 filed Jun. 30, 2017, which is a continuation application of U.S. patent application Ser. No. 14/715,795 filed May 19, 2015, the disclosure of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus and an interleaving method thereof, and more particularly, to a transmitting apparatus which processes and transmits data, and an interleaving method thereof.In the 21st century information-oriented society, broadcasting communication services are moving into the era of digitalization, multi-channel, wideband, and high quality. In particular, as high quality digital televisions, portable multimedia players and portable broadcasting equipment are increasingly used in recent years, there is an increasing demand for methods for supporting various receiving methods ...

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Номер записи: 41
03-01-2019 дата публикации

OAM BASED PHYSICAL LAYER SECURITY USING HYBRID FREE-SPACE OPTICAL-TERAHERTZ TECHNOLOGY

Номер: US20190007137A1
Автор: DJORDJEVIC Ivan, Wang Ting, Zhang Shaoliang
Принадлежит:

Aspects of the present disclosure describe systems, methods, and structures for physical layer security using hybrid free-space optical and terahertz transmission technologies that advantageously overcome atmospheric characteristics that infirmed the prior art. 1. A communications system employing a hybrid free-space optical (FSO) terahertz (THz) physical layer security scheme comprising: a binary-to-nonbinary converter that converts an input binary sequence;', 'a non-binary LDPC encoder that encodes the nonbinary symbols and provides parity symbols to a mapper/modulator;', 'a multidimensional mapper that maps the nonbinary symbols; and', 'a free space optical and THz transmitter for transmitting the symbols via a FSO and THz channel(s) respectively;, 'a transmitter including a FSO and a THz receiver for receiving transmissions on the FSO and THz channel(s) respectively;', 'a nonbinary a posteriori probability (APP) demapper which receives any data from the FSO and THz receivers and the mapped/modulated parity symbols from the mapper/demodulator, said APP calculates symbol log-likelihood ratios (LLRs); and', 'a nonbinary LDPC decoder that receives the LLRs and outputs any corrected symbols transmitted., 'a receiver including2. The system of wherein the system employs N orbital angular momentum (OAM) modes in an optical domain and N OAM modes in a THz domain.3. The system of wherein nonbinary LDPC codes are chosen such that any information symbols remain intact while generalized parity-symbols are algebraically related to the information symbols.4. The system of wherein the information symbols are transmitted over the FSO and THz channels while the generalized parity symbols are transmitted over classical channel(s).5. The system of wherein multidimensional signaling is used exclusively over the FSO channels and THz channels.6. The system of wherein operating wavelength of the FSO is one selected from the group consisting of: 1550 nm claim 5 , 2 μm claim 5 , 3.85 μm ...

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Номер записи: 42
02-01-2020 дата публикации

SECTOR LEVEL SWEEP METHOD AND APPARATUS

Номер: US20200007211A1
Автор: LI Dejian, Liu Jinnan
Принадлежит:

A sector level sweep method and apparatus are provided. A local end generates a first sector sweep packet at the local end sector sweep stage, and the local end sends the first sector sweep packet to a peer end by using a first beam. A quantity of bytes of the first sector sweep packet is not greater than 27, the first sector sweep packet includes beam indication information of the first beam, the beam indication information includes antenna identification information of the beam, and a maximum quantity of antennas indicated by the antenna identification information is at least 8. 1. A sector level sweep method , comprising:generating, by a local end, a first sector sweep packet at a local end sector sweep stage; andsending, by the local end, the first sector sweep packet to a peer end by using a first beam, whereina quantity of bytes of the first sector sweep packet is 27; andthe first sector sweep packet comprises beam indication information of the first beam, the beam indication information comprises antenna identification information of the beam.2. The method according to claim 1 , wherein the beam indication information further comprises beam identification information of the beam; anda maximum quantity of beams indicated by the beam identification information of the beam is at least 2048.3. The method according to claim 1 , wherein the beam indication information further comprises countdown identification information corresponding to the beam at the local end sector sweep stage; anda maximum quantity of beams indicated by the countdown identification information of the beam is at least 16384.4. The method according to claim 1 , wherein before the generating claim 1 , by a local end claim 1 , a first sector sweep packet claim 1 , the method further comprises:receiving, by the local end, a second sector sweep packet by using a second beam at a previous peer end sector sweep stage adjacent to the local end sector sweep stage, wherein the second sector sweep ...

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Номер записи: 43
04-01-2018 дата публикации

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

Номер: US20180007438A1
Автор: HONG Sungryong, Ko Woosuk, Kwon Woosuk, Lee Jangwon, Moon Kyoungsoo, Oh Sejin
Принадлежит:

The present invention provides a method of transmitting broadcast signals. The method includes, formatting input streams into Data Pipe (DP) data, Low-Density Parity-Check (LDPC) encoding the DP data according to a code rate, bit interleaving the LDPC encoded DP data, mapping the hit interleaved DP data onto constellations, building at least one signal frame including the mapped DP data, and modulating data in the built signal frame by an Orthogonal Frequency Division Multiplexing (OFDM) method and transmitting the broadcast signals having the modulated data, wherein the input streams include Audio/Video (A/V) data and service guide data, and wherein the Audio/Video (A/V) data and service guide data are included in first ISO base media file format (ISOBMFF) files. 114-. (canceled)15. A method of receiving broadcast signals , the method including:receiving the broadcast signals,wherein the broadcast signals are generated by encapsulating and compressing data into link layer packets, Low-Density Parity-Check (LDPC) encoding the data according to a code rate, bit interleaving the LDPC encoded data, mapping the bit interleaved data, building at least one signal frame including the mapped data, and modulating data in the built at least one signal frame by an Orthogonal Frequency Division Multiplexing (OFDM) method; anddecoding the received broadcast signals;wherein a link layer packet includes a link layer packet header and a payload containing an input packet,wherein a packet type of the input packet corresponds to IP(Internet Protocol) packet, or MPEG-2 TS packet,wherein the input packet is segmented and contained as a part of the input packet in the payload, or the input packet is concatenated with another input packet and contained in the payload,wherein the link layer packet header has an information field that indicates whether a segmentation or a concatenation is performed,wherein when the packet type of the input packet corresponds to the IP packet, a header of ...

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Номер записи: 44
08-01-2015 дата публикации

Systems and Methods for Correlation Based Data Alignment

Номер: US20150012800A1
Автор: George Mathew, Jefferson E. Singleton, Jongseung Park, Richard Rauschmayer, Shaohua Yang
Принадлежит: LSI Corp

A data processing system is disclosed including a data detector, a data decoder and an alignment detector. The data detector is operable to apply a data detection algorithm to generate detected values for a data sector. The data decoder is operable to apply a data decode algorithm to a decoder input derived from the detected values to yield decoded values. The alignment detector is operable to calculate an offset between multiple versions of the data sector by correlating the multiple versions.

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Номер записи: 45
27-01-2022 дата публикации

APPARATUS AND METHOD FOR SENDING/RECEIVING PACKET IN MULTIMEDIA COMMUNICATION SYSTEM

Номер: US20220029743A1
Автор: Hwang Sung-hee
Принадлежит:

A method for sending forward error correction (FEC) configuration information by a sending apparatus in a multimedia system is provided. The method includes sending source FEC configuration information for an FEC source packet to a receiving apparatus, wherein the source FEC configuration information includes information related to an FEC source or repair packet that is sent first among at least one FEC source or repair packet if an FEC source or repair packet block includes the at least one FEC source or repair packet. 1. A sending apparatus in a broadcasting system , the sending apparatus comprising:a transmitter; and identify forward error correction (FEC) configuration information,', 'generate an FEC packet including a header, a payload and the FEC configuration information, and', 'send the FEC packet,, 'a controller coupled with the transmitter and configured to control towherein the header includes time stamp (TS) information indicating a TS of the FEC packet,wherein the FEC configuration information includes information related to a first FEC packet that is sent first among one or more FEC packets included in an FEC packet block, andwherein the information related to the first FEC packet includes a value for remaining bits, which exclude a most significant bit (MSB) 1 bit of a TS included in a header of the first FEC packet.2. The sending apparatus of claim 1 , wherein the FEC configuration information follows the payload.3. The sending apparatus of claim 1 , wherein the sending apparatus supports a one-stage FEC coding structure.4. The sending apparatus of claim 1 , wherein the sending apparatus supports a layer aware-forward error correction (LA-FEC) coding structure.5. The sending apparatus of claim 4 , wherein claim 4 , in case that the sending apparatus supports a two-stage FEC coding structure claim 4 , the FEC configuration information includes a TS indicator indicating that the information related to the first FEC packet is for the FEC packet block of ...

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Номер записи: 46
14-01-2016 дата публикации

Enabling efficient recovery from multiple failures together with one latent error in a storage array

Номер: US20160011941A1
Автор: Huan He, Mingqiang Li
Принадлежит: International Business Machines Corp

The present invention provides a method and apparatus of managing a storage array. The method comprises: striping the storage array to form a plurality of stripes; selecting F storage chunks from each stripe as local parity chunks, and selecting another L storage chunks from the storage array as global parity chunks; performing (F+L) fault tolerant erasure coding on all data chunks in a stripe to generate (F+L) groups of parity data, and storing F groups of parity data therein into the F local parity chunks; performing cross-stripe operation on another L groups of parity data to generate L groups of global parity data, and storing them into the L global parity chunks, respectively. The apparatus corresponds to the method. With the invention, a plurality of errors in the storage array can be detected and/or recovered to improve fault tolerance and space utilization of the storage array.

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Номер записи: 47
27-01-2022 дата публикации

Reception apparatus and reception method

Номер: US20220030663A1
Автор: Hiroyuki Motozuka, Masataka Irie, Takenori Sakamoto
Принадлежит: Panasonic Intellectual Property Corp of America

In a transmission device, a signal processing circuit generates an aggregate physical layer convergence protocol data unit (A-PPDU) by adding a guard interval to each of a first part of a first physical layer convergence protocol data unit (PPDU) transmitted over each of a first through L′th channel of a predetermined channel bandwidth, where L is an integer of 2 or greater, a second part of the first PPDU transmitted over each of an (L+1)′th through P′th channel, which is a variable channel bandwidth that is N times the predetermined channel bandwidth, where N is an integer of 2 or greater and P is an integer of L+1 or greater, and a second PPDU transmitted over the (L+1)′th through P′th channel. A wireless circuit transmits the A-PPDU.

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Номер записи: 48
11-01-2018 дата публикации

POOL-LEVEL SOLID STATE DRIVE ERROR CORRECTION

Номер: US20180011762A1
Автор: Klein Yaron
Принадлежит:

A method for performing error correction for a plurality of storage drives and a storage appliance comprising a plurality of storage devices is disclosed. In one embodiment, the method includes generating a first set of parity bits from a first set of data of at least one of the plurality of storage devices, the first set of parity bits capable of correcting a first number of error bits of the first set of data. The method further includes generating a second set of parity bits from a concatenated set of the first data and a second set of data from at least another of the plurality of storage devices, the second set of parity bits capable of correcting a second number of error bits of the first set of data, the second number being greater than the first number. The method further includes reading the first set of data and (i) correcting error bits within the first set of data with the first set of parity bits where a number of error bits is less than the first number of error bits; and (ii) correcting error bits within the first set of data with the second set of parity bits where the number of error bits is greater than the first number. 1. A method for performing error correction for a plurality of storage drives , the method comprising:generating a first set of parity bits from a first set of data of at least one of the plurality of storage devices, the first set of parity bits capable of correcting a first number of error bits of the first set of data;generating a second set of parity bits from a concatenated set of the first set of data and a second set of data from at least another of the plurality of storage devices, the second set of parity bits capable of correcting a second number of error bits of the first set of data, the second number being greater than the first number;reading the first set of data and correcting error bits within the first set of data with the first set of parity bits where a number of error bits is less than the first number of error ...

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Номер записи: 49
10-01-2019 дата публикации

Memory system and method for operating semiconductor memory device

Номер: US20190012227A1
Автор: Min Kyu Lee, Nam Hoon Kim
Принадлежит: SK hynix Inc

A method for operating a semiconductor memory device may include applying a program pulse for programming data of a first page included in the semiconductor memory device. The method may include determining whether the number of times of applying the program pulse has exceeded a first critical value. The method may include performing an error bit check on a second page coupled to the same word line as the first page, based on the determined result of whether the first critical value has been exceeded.

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Номер записи: 50
12-01-2017 дата публикации

Low density parity check encoder having length of 64800 and code rate of 5/15, and low density parity check encoding method using the same

Номер: US20170012646A1
Автор: Heung-Mook Kim, Nam-Ho Hur, Sun-Hyoung Kwon, Sung-Ik Park
Принадлежит: Electronics and Telecommunications Research Institute ETRI

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

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Номер записи: 51
12-01-2017 дата публикации

TIME AND CELL DE-INTERLEAVING CIRCUIT AND METHOD FOR PERFORMING TIME AND CELL DE-INTERLEAVING

Номер: US20170012737A1
Автор: Wang Chun-Chieh
Принадлежит:

A method for performing time and cell de-interleaving on an interleaved signal including a plurality of cells is provided. The method includes: providing a first memory for storing the cells, the first memory written and read each time in a unit of one cell group, the cell group including K cells, where K is a positive integer greater than 1; providing a second memory for storing the cells read from the first memory; reading the cells from the first memory, and writing the cells to the second memory according to a writing rule of a plurality of permutation rules, K consecutive cells written to the second memory being from the same cell group; and reading the cells from the second memory according to a reading rule of the permutation rules, to cause the cells read from the second memory to be complete with time de-interleaving and cell de-interleaving. 1. A time and cell de-interleaving circuit , located at a signal receiver of a communications system , performing time de-interleaving and cell de-interleaving on an interleaved signal , the interleaved signal comprising a plurality of cells , the time and cell de-interleaving circuit comprising:a first memory, storing the cells;a storage control circuit, controlling an access operation of the first memory, the access operation performed in a unit of one cell group, the cell group comprising K units, where K is a positive integer greater than 1;a second memory, storing the cells read from the first memory; anda rule generating unit, generating a plurality of permutation rules, writing the cells read from the first memory to the second memory according to a writing rule of the permutation rules, and reading the cells from the second memory according to a reading rule of the permutation rules, such that the cells read from the second memory are complete with cell de-interleaving and time de-interleaving.2. The time and cell de-interleaving circuit according to claim 1 , wherein the interleaved signal comprises a ...

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Номер записи: 52
10-01-2019 дата публикации

RATE MATCHING USING LOW-DENSITY PARITY-CHECK CODES

Номер: US20190013901A1
Автор: Nimbalker Ajit, Xu Tao
Принадлежит: Intel IP Corporation

Technology for a transmitter operable to perform data transmissions using low density parity check (LDPC) codes is disclosed. The transmitter can determine soft buffer information (Nsoft) for a receiver. The transmitter can determine a soft buffer partition per HARQ process (NIR) for the UE. The transmitter can obtain, for a transport block, a number of code block segments (C). The transmitter can select a shift size value (z). The transmitter can determine an amount of soft buffer available for the code block segments (Ncb) based on NIR, C, and z. The transmitter can encode the code block segments based on an LDPC coding scheme to obtain encoded parity bits. The transmitter can select a subset of the encoded parity bits based on the determined amount of soft buffer associated with the code block segments. 1. An apparatus of a transmitter operable to perform data transmissions using low density parity check (LDPC) coding , the apparatus comprising one or more processors and memory configured to:{'sub': soft', 'soft, 'determine, at the transmitter, soft buffer information (N) for a receiver, wherein the soft buffer information (N) is associated with a component carrier;'}{'sub': IR', 'soft, 'determine, at the transmitter, a soft buffer partition per HARQ process (N) for the receiver based on the soft buffer information (N) and a reference number of HARQ processes;'}obtain, for a transport block, a number of code block segments (C) and at least one code block segment size value associated with the transport block based on a code block segmentation;select, at the transmitter, a shift size value (z) associated with an LDPC coding scheme to be used for encoding at least one code block segment associated with the transport block;{'sub': cb', 'IR, 'determine, at the transmitter, an amount of soft buffer available for the at least one code block segment (N) based on the soft buffer partition per HARQ process (N), the number of code block segments (C), and the shift size ...

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Номер записи: 53
10-01-2019 дата публикации

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

Номер: US20190013979A1
Автор: BAEK Jongseob, HONG Sungryong, KIM Jaehyung, Ko Woosuk, Shin Jongwoong
Принадлежит:

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals comprises an encoder for encoding service data, a mapper for mapping the encoded service data into a plurality of OFDM (Orthogonal Frequency Division Multiplex) symbols to build at least one signal frame, a frequency interleaver for frequency interleaving data in the at least one signal frame by using a different interleaving-seed which is used for every OFDM symbol pair comprised of two sequential OFDM symbols, a modulator for modulating the frequency interleaved data by an OFDM scheme and a transmitter for transmitting the broadcast signals having the modulated data, wherein the different interleaving-seed is generated based on a cyclic shifting value and wherein an interleaving seed is variable based on an FFT size of the modulating. 120-. (canceled)21. A method comprising:at an electronic device with one or more processors for processing broadcast signals:encoding data for one or more services of the broadcast signals;building a signal frame carrying the encoded data; generating a main sequence, a same main sequence being used for two consecutive symbols to be processed by an OFDM (Orthogonal Frequency Division Multiplexing) scheme;', 'generating a symbol offset, a value of the symbol offset being constant for the two consecutive symbols;', 'generating a sequence based on the main sequence and the symbol offset; and', 'checking a validity of address of the generated sequence to output the interleaving sequence that corresponds to one or more valid addresses;, 'frequency interleaving data in the signal frame by a interleaving sequence that applies to a symbol in the data signal, wherein the interleaving sequence is generated bymodulating frequency interleaved data by the OFDM scheme; andtransmitting broadcast signals carrying modulated data.22. The method of claim 21 , wherein when the frequency interleaving applies to a signal ...

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Номер записи: 54
03-02-2022 дата публикации

Systems and Methods for Allocating Blocks of Memory to Multiple Zones Associated with Corresponding Error Correction Mechanisms

Номер: US20220035699A1
Автор: Karamcheti Vijay, Narasimha Ashwin, Singhai Ashish
Принадлежит:

Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone. 1. A method for a data storage system , the method comprising:allocating one or more first blocks of memory to a first zone, one or more second blocks of the memory to a second zone, and one or more third blocks of the memory to a third zone;assigning a first error correction mechanism to the first zone, a second error correction mechanism to the second zone, and the second error correction mechanism to the third zone;directing one or more first command requests into the first zone and one or more second command requests into the second zone;receiving one or more third command requests, wherein the one or more third command requests are for data that is overwritten more frequently than data for the one or more second command requests;changing an error correction mechanism of the third zone by assigning the first error correction mechanism to the third zone; anddirecting the one or more third command requests into the third zone.2. The method of claim 1 , comprising:assigning, to the first zone, a first error correction level associated with the first error correction mechanism; andassigning, to the second zone, a second error correction level associated with the second error correction mechanism.3. ...

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Номер записи: 55
03-02-2022 дата публикации

Chip

Номер: US20220035763A1
Автор: He Zhaojun, HUANG Junhong, WANG Fan
Принадлежит:

A chip includes a dedicated scheduler, a general scheduler, and a plurality of hardware accelerators. The hardware accelerators are connected, at least one hardware accelerator is connected to the dedicated scheduler, and at least one hardware accelerator is connected to the general scheduler. 1. A chip , comprising: a first hardware accelerator, and', 'a second hardware accelerator;, 'hardware accelerators, wherein two of the hardware accelerators are coupled to each other, and wherein the hardware accelerators comprisea general scheduler coupled to the first hardware accelerator and configured to schedule the first hardware accelerator; anda dedicated scheduler coupled to the second hardware accelerator and configured to schedule the second hardware accelerator.2. The chip of claim 1 , further comprising a bus coupled to the hardware accelerators.31. The chip of claim. claim 1 , further comprising a wire or a bus coupled to the second hardware accelerator and the dedicated scheduler.4. The chip of claim 1 , further comprising a wire claim 1 , or a bus coupled to the first hardware accelerator and the general scheduler.5. The chip of claim 1 , wherein the dedicated scheduler is coupled to the general scheduler claim 1 , and wherein the dedicated scheduler and the general scheduler are configured to collaboratively schedule the hardware accelerators.6. The chip of claim 5 , further comprising a wire or a bus coupling the dedicated scheduler and the general scheduler.7. The chip of claim 5 , wherein the first hardware accelerator is configured to send data status information to the dedicated scheduler claim 5 , and wherein the dedicated scheduler is further configured to determine claim 5 , based on the data status information claim 5 , that the dedicated scheduler should continue scheduling the first hardware accelerator or should instruct the general scheduler to schedule the first hardware accelerator.8. The chip of claim 7 , wherein the dedicated scheduler is ...

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Номер записи: 56
15-01-2015 дата публикации

Manufacturing testing for ldpc codes

Номер: US20150019926A1
Автор: Lingqi Zeng, Yu Kou
Принадлежит: SK Hynix Memory Solutions America Inc

An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.

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Номер записи: 57
18-01-2018 дата публикации

APPARATUS, SYSTEM AND METHOD OF COMMUNICATING A TRANSMISSION ENCODED ACCORDING TO A LOW-DENSITY PARITY-CHECK (LDPC) CODE

Номер: US20180019840A1
Автор: Cordeiro Carlos, Gagiev Iaroslav P., Genossar Michael, Lomayev Artyom, Maltsev Alexander
Принадлежит:

Some demonstrative embodiments include apparatus, system and method of communicating a transmission encoded according to a Low-Density Parity-Check (LDPC) code. For example, an apparatus may include logic and circuitry configured to cause a wireless station to encode a plurality of data bits into a plurality of codewords according to an LDPC code having an encoding rate of ⅞ and a codeword length of 1248 bits; and to transmit a transmission over a millimeter Wave (mmWave) frequency band based on the plurality of codewords. 1. An apparatus comprising logic and circuitry configured to cause a wireless station to:encode a plurality of data bits into a plurality of codewords according to a Low-Density Parity-Check (LDPC) code having an encoding rate of ⅞ and a codeword length of 1248 bits; andtransmit a transmission over a millimeter Wave (mmWave) frequency band based on the plurality of codewords.2. The apparatus of claim 1 , wherein a codeword of the plurality of codewords comprises 1092 data bits and 156 parity bits claim 1 , the 156 parity bits are based on the 1092 data bits.3. The apparatus of configured to cause the wireless station to determine a set of parity bits by applying a code matrix to the 1092 data bits claim 2 , the set of parity bits comprising more than 156 bits claim 2 , and to generate the codeword by appending 156 bits of the set of parity bits to the 1092 data bits.4. The apparatus of claim 3 , wherein the code matrix comprises a lifting matrix.5. The apparatus of claim 3 , wherein the set of parity bits comprises 252 parity bits.60122510110910110919697251. The apparatus of claim 5 , wherein the 252 parity bits comprise a sequence of bits denoted {p claim 5 , p claim 5 , p claim 5 , . . . claim 5 , p} claim 5 , the 1092 data bits comprise a sequence of bits denoted {S claim 5 , S claim 5 , . . . claim 5 , S} claim 5 , and the codeword comprises a sequence of the bits {S claim 5 , S claim 5 , . . . claim 5 , S claim 5 , p claim 5 , p claim 5 , . . ...

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Номер записи: 58
21-01-2021 дата публикации

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF10/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

Номер: US20210019228A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, LEE Jae-Young, LIM Bo-Mi, PARK Sung-Ik
Принадлежит:

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping. 1. A bit-interleaved coded modulation (BICM) reception device , comprising:a demodulator configured to perform demodulation corresponding to 256-symbol mapping;a bit deinterleaver configured to perform group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; anda decoder configured to restore information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 16200 and a code rate of 10/15, wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception device of claim 1 , wherein the group-unit deinterleaving corresponds to a reverse process of interleaving performed by using permutation order claim 1 , and the permutation order corresponds to an interleaving sequence represented by the followinginterleaving sequence ={128 20 18 38 39 2 3 30 19 4 14 36 7 0 25 17 10 6 33 15 8 26 42 24 11 21 23 5 40 41 29 32 37 44 43 31 35 34 22 1 16 27 9 13 12}.3. The BICM reception device of claim 2 , wherein the 256-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 256 constellations.4. The BICM reception device of claim 2 , wherein the parallel factor is 360 claim 2 , and the group includes 360 ...

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Номер записи: 59
17-04-2014 дата публикации

CODE DESIGN AND IMPLEMENTATION IMPROVEMENTS FOR LOW DENSITY PARITY CHECK CODES FOR WIRELESS ROUTERS USING 802.11n PROTOCOL

Номер: US20140105330A1
Автор: EROZ Mustafa, Lee Lin-Nan, Sun Feng-Wen
Принадлежит: THE DIRECTV GROUP, INC.

Method and apparatus for implementing LDPC codes in an IEEE 802.11 standard system configured to operate in a Multiple-Input, Multiple-Output (MIMO) schema. A method in accordance with the present invention comprises defining a base LDPC code, having a length equal to an integer number of data carriers in an ODFM symbol, transmitting the base LDPC code over a plurality of sub-carriers, wherein the base code is transmitted at an expected phase on sub-carriers specified by the IEEE 802.11 standard system, and transmitting the base LDPC code on other sub-carriers than those specified by the IEEE 802.11 standard system, wherein the base LDPC code on the other sub-carriers is transmit offset in phase from the base LDPC code on the specified sub-carriers. 1. A method for implementing Low Density Parity Check codes in an IEEE 802.11 standard system configured to operate in a Multiple-Input , Multiple-Output schema , and encoding an input information stream with the LDPC codes , comprising:a) defining a base LDPC code, having a length equal to an integer multiple of a number of data carriers in an ODFM symbol; characterized in thatb) transmitting the base LDPC code in place of a space-time code over a plurality of sub-carriers, wherein the base code is transmitted at an expected phase on sub-carriers specified by the IEEE 802.11 standard system, andc) transmitting the base LDPC code in place of the space-time code on other sub-carriers than those specified by the IEEE 802.11 standard system, wherein the base LDPC code on the other sub-carriers is transmit offset in phase from the base LDPC code on the specified sub-carriers.2. The method of claim 1 , wherein the base LDPC code is 192 bits long.3. The method of claim 2 , further comprising using a longer LDPC code instead of the base LDPC code claim 2 , wherein a length of the longer LDPC code is an integer multiple of the base LDPC code.4. The method of claim 2 , wherein the specified sub-carriers are transmitted by a first ...

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Номер записи: 60
17-01-2019 дата публикации

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

Номер: US20190020354A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, PARK Sung-Ik
Принадлежит:

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 1. A low density parity check (LDPC) decoder , comprising:a receiving unit configured to receive a signal corresponding to an LDPC codeword having a length of 64800 and a code rate of 3/15, the LDPC codeword encoded using a sequence corresponding to a parity check matrix (PCM); anda decoding unit configured to perform decoding the received signal, the decoding corresponding to the parity check matrix.3. The LDPC decoder of claim 2 , wherein the LDPC codeword comprises a systematic part corresponding to information bits and having a length of 12960 claim 2 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1800 claim 2 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 50040.4. The LDPC decoder of claim 3 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 3 , that is claim 3 , 12960 claim 3 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 3 , that is claim 3 , 360 claim 3 , and a value obtained by dividing a length of the first parity part claim 3 , that is claim 3 , 1800 claim 3 , by the CPM size.5. The LDPC decoder of claim 2 , wherein the LDPC codeword is generated by performing accumulation with respect to a memory and the accumulation is performed at parity bit addresses that are updated using the sequence.6. The LDPC decoder of claim 5 , wherein the ...

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Номер записи: 61
17-01-2019 дата публикации

ENCODING/DECODING METHOD, DEVICE, AND SYSTEM

Номер: US20190020358A1
Автор: Li Bin, Shen Hui
Принадлежит: Huawei Technologies CO.,Ltd.

Embodiments of the present disclosure provide an encoding/decoding method, apparatus, and system. The present disclosure is used to improve the decoding performance and improve accuracy of a survivor path. The method includes: encoding information bits to obtain a first-level encoded code word; obtaining a sorting value of each check bit of the first-level encoded code word, and adjusting each check bit to a corresponding position according to the sorting value of each check bit, where the sorting value refers to a value of S when the check bit is related to first S information bits of the information bits in the first-level encoded code word, and S is a non-zero integer; and performing second-level encoding on the first-level encoded code word after positions of the check bits are adjusted, thereby obtaining a second-level encoded code word. The present disclosure is applicable to various communication systems. 1. An encoding method , the method comprising:{'sup': 'th', 'non-polar encoding, by an encoding device, a plurality of information bits to obtain a first encoded code word that comprises the plurality of information bits and a plurality of check bits, wherein a first check bit of the plurality of check bits is positioned after S information bits and before (S+1)information bit of the first encoded code word, and S equals to a number of information bits related to the check bit and is an integer of at least 1; and'}polar encoding, by the encoding device, the first encoded code word to obtain a second encoded code word.2. The method according to claim 1 , the value of S is obtained by:obtaining the value of S according to a sorting value of a column vector of a generator matrix corresponding to the first check bit.3. The method according to claim 2 , wherein the method further comprises obtaining a sequence number as the value of S claim 2 ,wherein the sequence number is a first inverse non-zero value of the column vector corresponding to the first check bit ...

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Номер записи: 62
16-01-2020 дата публикации

TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

Номер: US20200021312A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method. 1. An interleaving method of a transmitting apparatus , the method comprising:splitting bits into a plurality of bit groups;interleaving the plurality of bit groups;interleaving the interleaved plurality of bit groups using a plurality of containers to provide an interleaved codeword, each of the plurality of containers comprising a first part and a second part;demultiplexing bits of the interleaved codeword to generate cells;mapping the cells onto constellation points, andtransmitting a signal which is based on the constellation points,wherein a number of bits to be written in the first part is determined based on a number of the plurality of containers and a number of bits of each of the plurality of bit groups, andwherein a number of bits to be written in the second part is determined based on the number of the plurality of containers and the number of the bits of each of the plurality of bit groups.2. The method as claimed in claim 1 , wherein the each of the plurality of bit groups comprises 360 bits.3. The method as claimed in claim 1 , wherein the number of the plurality of containers is equal to a modulation order for the mapping.4. A transmitting apparatus comprising:a group interleaver configured to split bits into a plurality of bit groups and interleave the plurality of bit groups;a block ...

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Номер записи: 63
21-01-2021 дата публикации

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 3/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

Номер: US20210021284A9
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, LEE Jae-Young, LIM Bo-Mi, PARK Sung-Ik
Принадлежит:

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A bit interleaver , comprising:a first memory configured to store a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15;a processor configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; anda second memory configured to provide the interleaved codeword to a modulator for 64-symbol mapping.2. The bit interleaver of claim 1 , wherein the 64-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 64 constellations.3. The bit interleaver of claim 2 , wherein the parallel factor is 360 claim 2 , and the bit group includes 360 bits.6. The bit interleaver of claim 5 , wherein the permutation order corresponds to an interleaving sequence represented by the following equation:{'br': None, 'interleaving sequence={19 34 22 6 29 25 23 36 7 8 24 16 27 43 11 35 5 28 13 4 3 17 15 38 20 0 26 12 1 39 31 41 44 30 9 21 42 18 14 32 10 2 37 33 40}'} This application is a continuation of U.S. application Ser. No. 14/717,174, filed May 20, 2015, which claims the benefit of Korean Patent Application Nos. 10-2014-0061874 and 10-2015-0009141, filed May 22, 2014 and Jan. 20, 2015, which are hereby incorporated by reference herein in their entirety.The present disclosure relates generally to an interleaver and, ...

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Номер записи: 64
21-01-2021 дата публикации

TRANSMITTER APPARATUS AND BIT INTERLEAVING METHOD THEREOF

Номер: US20210021285A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, LOBETE Daniel Ansorregui, MOUHOUCE Belkacem, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The transmitting method of claim 1 , wherein each of the plurality of bit groups comprises 360 bits.3. The transmitting method of claim 1 , wherein the interleaving further comprises:interleaving the interleaved plurality of bit groups.4. The transmitting method of claim 1 , wherein the π(j) is determined based on at least one of the code length claim 1 , a modulation method for the mapping claim 1 , and the code rate.6. The method of claim 5 , wherein each of the plurality of groups comprises 360 values.7. The method of claim 5 , wherein the π(j) is determined based on at least one of the code length claim 5 , a modulation method for the mapping claim 5 , and the code rate. This is a Continuation of U.S. application Ser. No. 16/460,305 filed Jul. 2, 2019, which is a Continuation of U.S. application Ser. No. 15/686,280 filed Aug. 25, 2017, which is a Continuation of application Ser. No. 14/716,503 filed May 19, 2015, and claims priority from U.S. Provisional Application No. 62/001,160 filed on May 21, 2014 and Korean Patent Application No. 10-2015-0069924 filed on May 19, 2015, the disclosures of which are incorporated herein by reference in their entirety.Apparatuses and methods consistent with exemplary embodiments ...

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Номер записи: 65
26-01-2017 дата публикации

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

Номер: US20170026213A1
Автор: HONG Sungryong, Hwang Jaeho, KIM Jinwoo, Ko Woosuk, Shin Jongwoong
Принадлежит:

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder for encoding service data corresponding to each of a plurality of data transmission path, wherein each of the data transmission path carries at least one service component for broadcast services, an encoder for encoding signaling data, wherein the signaling data includes static data and dynamic data, a frame builder for building signal frames, wherein each of signal frames includes the encoded service data and the encoded signaling data, wherein each of signal frames belongs to one of the broadcast services, wherein the static data remain constant in the signal frames belonging to the broadcast service in a duration of a super frame and the dynamic data changes by the signal frames, a modulator for modulating the signal frames by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter for transmitting the broadcast signals carrying the modulated signal frames. 120-. (canceled)21. A Method For Transmitting Broadcast Signals , Comprising:encoding service data corresponding to each of a plurality of data transmission paths;encoding signaling data;padding zero bits to the encoded signaling data, wherein a size of the padded zero bits is related to the variable size of the signaling data;LDPC encoding the zero padded signaling data by appending parity bits;building signal frames, wherein each of signal frames includes the encoded service data and the LDPC encoded signaling data;modulating the signal frames by an OFDM (Orthogonal Frequency Division Multiplex) scheme; andtransmitting the broadcast signals carrying the modulated signal frames.22. The method of claim 21 , wherein the method further comprises:segmenting the signaling data for the encoding.23. The method of claim 22 , wherein the method further comprises:scrambling the segmented signaling data.24. The method of claim 21 , ...

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Номер записи: 66
25-01-2018 дата публикации

Broadcasting of Digital Video to Mobile Terminals

Номер: US20180026745A1
Автор: Barak Ilan Saul, RAINISH Doron, SHANI RAZ
Принадлежит:

A method includes processing error correction encoded data by a first processing chain of a transmitter. The processing includes interleaving a first portion of the error correction encoded data with respect to a first interleaving period to generate a first output signal. Interleaving the first portion includes de-multiplexing the first portion among multiple branches having respective delays in accordance with a distribution order and re-multiplexing delayed data from the branches to form the first output signal. The method includes processing the error correction encoded data by a second processing chain of the transmitter without use of interleaving to generate a second output signal. The method includes multiplexing the first output signal and the second output signal into a multiplexed stream. The method also includes transmitting the multiplexed stream from the transmitter over a communication channel to a receiver. 1. A method comprising:processing error correction encoded data by a first processing chain of a transmitter, the processing including interleaving a first portion of the error correction encoded data with respect to a first interleaving period to generate a first output signal, wherein the interleaving the first portion comprises de-multiplexing the first portion among multiple branches having respective delays in accordance with a distribution order and re-multiplexing delayed data from the branches to form the first output signal;processing the error correction encoded data by a second processing chain of the transmitter without use of interleaving to generate a second output signal;multiplexing the first output signal and the second output signal into a multiplexed stream; andtransmitting the multiplexed stream from the transmitter over a communication channel to a receiver.2. The method of claim 1 , further comprising encoding input data with an error correction code encoder of the transmitter to produce the error correction encoded data.3. ...

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Номер записи: 67
10-02-2022 дата публикации

TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF

Номер: US20220045697A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform parity-permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern, wherein the first pattern determines parity bits to remain after the puncturing and then to be transmitted in the current frame. 1. A receiving method comprising:receiving a signal from a transmitting apparatus;demodulating the signal to generate values based on 64-quadrature amplitude modulation (QAM);inserting predetermined values;splitting the values and the inserted predetermined values into a plurality of groups;deinterleaving some groups among the plurality of groups based on a permutation order to provide deinterleaved plurality of groups in which the some groups are deinterleaved; anddecoding values of the deinterleaved plurality of groups based on a low density parity check (LDPC) code, a code rate of the LDPC code being 6/15 and a code length of the LDPC code being 16200 bits,wherein positions of the inserted predetermined values correspond to positions of parity bits punctured in the transmitting apparatus, andwherein groups having indices of 25, 42, 34, 18, 32, 38, 23, 30, 28, 36 and 41 among the deinterleaved plurality of groups comprise at least a part of the predetermined values.2. The receiving method of claim 1 , wherein a number ...

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Номер записи: 68
23-01-2020 дата публикации

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

Номер: US20200029123A1
Автор: HONG Sungryong, Ko Woosuk, Kwon Woosuk, Lee Jangwon, Moon Kyoungsoo, Oh Sejin
Принадлежит:

The present invention provides a method of transmitting broadcast signals. The method includes, formatting input streams into Data Pipe (DP) data, Low-Density Parity-Check (LDPC) encoding the DP data according to a code rate, bit interleaving the LDPC encoded DP data, mapping the bit interleaved DP data onto constellations, building at least one signal frame including the mapped DP data, and modulating data in the built signal frame by an Orthogonal Frequency Division Multiplexing (OFDM) method and transmitting the broadcast signals having the modulated data, wherein the input streams include Audio/Video (A/V) data and service guide data, and wherein the Audio/Video (A/V) data and service guide data are included in first ISO base media file format (ISOBMFF) files. 114-. (canceled)15. A method of receiving a broadcast signal in a receiver , the method comprising:receiving the broadcast signal including link layer packets into which Internet Protocol (IP) packets are encapsulated, wherein each link layer packet includes a link layer packet header and a payload, wherein the link layer packet header includes an information field for identifying whether the payload carries a segmentation of an IP packet or carries a concatenation of an IP packet with another IP packet, and wherein headers of the IP packets are compressed based on Robust Header Compression (RoHC) of unidirectional mode;decapsulating the link layer packets into the IP packets based on the information field; anddecompressing the headers of the IP packets.16. The method of claim 15 ,wherein the IP packets include files based on ISO base media file format (ISO BMFF) andwherein the files include Audio/Video (A/V) data.17. A receiver for receiving a broadcast signal claim 15 , the receiver comprising:an antenna to receive the broadcast signal including link layer packets into which Internet Protocol (IP) packets are encapsulated, wherein each link layer packet includes a link layer packet header and a payload, ...

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Номер записи: 69
04-02-2016 дата публикации

Storage Module and Method for Improved Error Correction by Detection of Grown Bad Bit Lines

Номер: US20160034353A1
Автор: Manohar Abjiheet, Tuers Daniel E.
Принадлежит: SANDISK TECHNOLOGIES INC.

A storage module and method are provided for improved error correction by detection of grown bad bit lines. In one embodiment, a storage module is provided comprising a controller and a memory having a plurality of bit lines. The controller detects an uncorrectable error in a code word read from the memory, determines location(s) of grown bad bit line(s) that contributed to the error in the code word being uncorrectable, and uses the determined location(s) of the grown bad bit line(s) to attempt to correct the error in the code word. 1. A storage module comprising:a memory having a plurality of bit lines; and detect an uncorrectable error in a code word read from the memory;', 'determine location(s) of grown bad bit line(s) that contributed to the error in the code word being uncorrectable; and', 'use the determined location(s) of the grown bad bit line(s) to attempt to correct the error in the code word., 'a controller in communication with the memory, wherein the storage controller is configured to2. The storage module of claim 1 , wherein the controller is configured to determine the location(s) of the grown bad bit line(s) by:reading a plurality of additional code words that share the same bit lines as the code word that has the uncorrectable error; andgenerating a histogram of error frequency of each of the bit lines.3. The storage module of claim 2 , wherein the controller is further configured to:apply a high-pass filter to the histogram to identify the location(s) of the grown bad bit line(s).4. The storage module of claim 2 , wherein the histogram also indicates an originally-stored value of a bit that was in error.5. The storage module of claim 1 , wherein the controller implements an ECC engine using low-density parity-check (LDPC) code claim 1 , and wherein the controller is configured modify the log likelihood ratio (LLR) of the ECC engine for the determined location(s) of the grown bad bit line(s) before attempting to correct the error.6. The storage ...

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Номер записи: 70
01-05-2014 дата публикации

Prevention of output supply boosting upon removal of input adapter

Номер: US20140117944A1
Автор: Christian G. Sporck, Thomas J. O'Brien
Принадлежит: Qualcomm Inc

A charging circuit using a switch mode power supply to charge a battery from a connected external power adapter may periodically turn off the switch mode power supply and disconnect its input terminal from the switch mode power supply. A load may be connected to the input terminal. The input terminal is monitored for voltage collapse, indicating whether or not the power adapter is connected.

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Номер записи: 71
02-02-2017 дата публикации

METHOD AND APPARATUS FOR CHANNEL ENCODING AND CHANNEL DECODING IN A WIRELESS COMMUNICATION SYSTEM

Номер: US20170033894A1
Автор: AHN Seok-Ki, JANG Min, Kim Jae-Yoel, KIM Kwang-Taik, LIM Chi-Woo, PARK Woo-Myoung
Принадлежит:

A method and apparatus for channel encoding and channel decoding in a wireless communication system are provided. The channel encoding method includes generating a first parity set and a second parity set based on information bits, determining a number of additional parity bits based on a number of the information bits and a required coding rate, generating the determined number of additional parity bits using the information bits, and generating a codeword including the information bits, the first parity set, the second parity set, and the generated additional parity bits. 1. A channel encoding method in a wireless communication system , the channel encoding method comprising:generating a first parity set and a second parity set based on information bits;determining a number of additional parity bits based on a number of the information bits and a required coding rate;generating the determined number of additional parity bits using the information bits; andgenerating a codeword including the information bits, the first parity set, the second parity set, and the generated additional parity bits.2. The channel encoding method of claim 1 , wherein the generation of the determined number of additional parity bits comprises:determining positions of information bits to be used in generating an additional parity bit according to the determined number of additional parity bits and a turn of the additional parity bit; andgenerating the additional parity bit by XOR-operating information bits at the determined positions,wherein the generation of the determined number of additional parity bits is performed until the determined number of additional parity bits are generated.3. The channel encoding method of claim 2 , wherein the determination of the positions of the information bits comprises determining the positions of the information bits by a function of the number of the information bits.4. The channel encoding method of claim 2 , wherein the determination of the positions ...

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Номер записи: 72
17-02-2022 дата публикации

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 3/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

Номер: US20220052708A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, LEE Jae-Young, LIM Bo-Mi, PARK Sung-Ik
Принадлежит:

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A method of transmitting a broadcast signal , comprising:storing a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15;generating an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword;performing 64-symbol mapping for generating a broadcast signal after generating the interleaved codeword; andtransmitting the broadcast signal over a physical channel, {'br': None, 'i': Y', '=X', 'j≤N, 'sub': j', 'π(j)', 'group, '0≤'}, 'wherein the interleaving is performed using the following equation using permutation order{'sub': π(j)', 'j', 'group, 'where Xis the π(j)th bit group, Yan interleaved j-th bit group, Nis the number of bit groups, and π(j) is a permutation order for bit group-based interleaving,'} {'br': None, 'interleaving sequence={19 34 22 6 29 25 23 36 7 8 24 16 27 43 11 35 5 28 13 4 3 17 15 38 20 0 26 12 1 39 31 41 44 30 9 21 42 18 14 32 10 2 37 33 40}.'}, 'wherein the permutation order corresponds to an interleaving sequence represented by the following'}2. The method of claim 1 , wherein the interleaving is performed by using the interleaving sequence before performing the 64-symbol mapping so as to distribute burst errors occurring in the broadcast signal transmitted over the physical channel.3. The method of claim 1 , wherein the ...

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Номер записи: 73
05-02-2015 дата публикации

TRANSMITTER APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

Номер: US20150039973A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol. 1. A transmitter apparatus comprising:an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding;an interleaver configured to interleave the LDPC codeword; anda modulator configured to map the interleaved LDPC codeword onto a modulation symbol,wherein the modulator is configured to map a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol.2. The transmitter apparatus of claim 1 , wherein each of the plurality of groups is formed of 360 bits.3. The transmitter apparatus of claim 1 , wherein the interleaver comprises:a parity interleaver configured to interleave parity bits constituting the LDPC codeword;a group interleaver configured to perform group-interleaving by dividing the parity-interleaved LDPC codeword into the plurality of groups and rearranging an order of the plurality of groups in; anda block interleaver configured to perform block-interleaving of the plurality of groups the order of which has been rearranged.4. The transmitter apparatus of claim 3 , wherein the group interleaver rearranges the order of the plurality of groups based on a following equation:{'br': None, 'i': Y', '=X', 'j Подробнее

Номер записи: 74
04-02-2021 дата публикации

FLASH MEMORY CONTROLLER, STORAGE DEVICE AND READING METHOD THEREOF

Номер: US20210034456A1
Автор: KUO Shiuan-Hao
Принадлежит:

A flash memory controller used to access a flash memory includes a read-only memory, a processor, and an error correction code unit. The read-only memory is used to store a code. The processor executes the code to control access to the flash memory. The error correction code unit includes a control module and a decoder. The control module respectively calculates a first correlation between innate bad-column information and a plurality of trapping sets of a plurality of preset LDPC (low-density parity check) codes and uses the preset LDPC code which has the lowest first correlation as a selected LDPC code. The decoder decodes read information obtained from the flash memory according to the selected LDPC code. 1. A flash memory controller , configured to access a flash memory , wherein the flash memory controller comprises:a read-only memory, configured to store a code;a processor, configured to execute the code to control access to the flash memory; andan error correction code unit, comprising:a control module, respectively calculating a first correlation between innate bad-column information and a plurality of trapping sets of a plurality of preset LDPC (low-density parity check) codes, and using the preset LDPC code which has the lowest first correlation as a selected LDPC code; anda decoder, decoding read information obtained from the flash memory according to the selected LDPC code.2. The flash memory controller as claimed in claim 1 , wherein the control module further calculates a second correlation between bad-column data and the tapping sets of selected LDPC code claim 1 , and determines whether the second correlation is greater than a first threshold claim 1 , wherein the bad-column data comprises run-time bad-column information and the innate bad-column information claim 1 , and when the second correlation is greater than the first threshold claim 1 , the control module further uses the preset LDPC code which has a third correlation that is lower than or ...

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Номер записи: 75
31-01-2019 дата публикации

STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE

Номер: US20190036546A1
Автор: BAE HYNSOO, CHO Yongwon, LEE DONG-RYOUL, LEE TAEHACK, LEEM HYOTAEK, YI HYUN JU
Принадлежит:

A storage device includes a nonvolatile memory device and a controller configured to read data from the nonvolatile memory device, to divide the read data into a plurality of segments, and to sequentially perform error correction decoding with respect to the plurality of segments. When the error correction decoding of each segment is completed, the controller adds error correction parity to each of the decoded segments and sends the decoded segments with added error correction parity to an external host device. When error correction decoding of a second segment is not completed after a threshold time has elapsed after sending a first segment of which error correction decoding is completed, the controller adds an incorrect error correction parity to dummy data and sends the dummy data with the added incorrect error correction parity to the external host device. 1. A storage device , comprising:a nonvolatile memory device; anda controller configured to read data from the nonvolatile memory device, to divide the read data into a plurality of segments, and to sequentially perform error correction decoding on the plurality of segments,wherein upon determination that error correction decoding of a first segment from among the plurality of segments is completed, the controller is configured to add first error correction parity to the first segment and send the first segment with the added first error correction parity to an external host device, andwherein upon determination that error correction decoding of a second segment from among the plurality of segments is not complete after a threshold time has elapsed from when sending of the first segment from among the plurality of segments was completed, the controller is configured to add an incorrect error correction parity to dummy data and send the dummy data with the added incorrect error correction parity to the external host device.2. The storage device of claim 1 , wherein upon determination that the error correction ...

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Номер записи: 76
31-01-2019 дата публикации

METHOD FOR ACCESSING FLASH MEMORY MODULE AND ASSOCIATED FLASH MEMORY CONTROLLER AND MEMORY DEVICE

Номер: US20190036549A1
Автор: HSU Hong-Jung, Yang Tsung-Chieh
Принадлежит:

A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block. 1. A method for accessing a flash memory module , wherein the flash memory module is a 3D NAND-type flash memory module including a plurality of flash memory chips , each flash memory chip is a 3D flash memory chip , each flash memory chip includes a plurality of blocks , each block includes a plurality of data pages , and the method comprises:configuring the flash memory chips to set at least one first super block and at least one second super block of the flash memory chips;allocating the at least one second super block to store temporary parity check codes generated by an encoding procedure during programming data into the at least one first super block;reading a plurality of temporary parity check codes from the second super block;generating a plurality of final parity check codes according to the temporary parity check codes, wherein each final parity check code is generated by using the temporary parity check codes corresponding to the data stored in different word line groups of the first super block, and each word line group has a plurality of word lines; andwriting the plurality of final parity check codes into the first super block.2. The method of claim 1 , wherein the second super block is dedicated to store the temporary parity check codes generated by the encoding procedure during programming data into the at least one first super block.3. The method of claim 1 , wherein the first super block includes one multiple ...

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Номер записи: 77
04-02-2021 дата публикации

TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

Номер: US20210036715A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method. 1. A transmitting apparatus comprising:an interleaver configured to interleave a codeword; anda constellation mapper configured to map bits of the interleaved codeword onto constellation points for 256-quadrature amplitude modulation (QAM),wherein the interleaver comprises:a block interleaver configured to interleave bits of the codeword using a plurality of containers, each of the plurality of containers comprising a first part and a second part, andwherein if a length of the codeword is 64800 bits, a number of bits to be written in the first part of the each of the plurality of containers is 7920, and a number of bits to be written in the second part of the each of the plurality of containers is 180, andwherein if the length of the codeword is 16200 bits, the number of the bits to be written in the first part of the each of the plurality of containers is 1800 and the number of the bits to be written in the second part of the each of the plurality of containers is 225.2. The transmitting apparatus claimed in claim 1 , wherein the codeword comprises input bits and parity bits claim 1 , andwherein the parity bits are generated by encoding the input bits based on a low density parity check (LDPC) code.3. A receiving apparatus comprising:a demodulator configured to demodulate a signal received from a ...

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Номер записи: 78
11-02-2016 дата публикации

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

Номер: US20160043740A1
Автор: IKEGAYA Ryoji, Shinohara Yuji, Yamamoto Makiko
Принадлежит: SONY CORPORATION

In group-wise interleaving, interleaving of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15 is performed in a unit of a bit group of 360 bits. In group-wise deinterleaving, an arrangement of the LDPC code that has undergone group-wise interleaving is returned to an original arrangement. The technology can be applied to a case of transmitting data using the LDPC code. The data processing device and data processing method can ensure excellent communication quality in data transmission using an LDPC code. 1. (canceled)2. A data processing method comprising:an encoding step of performing LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15;a group-wise interleaving step of performing group-wise interleaving of interleaving the LDPC code in a unit of a bit group of 360 bits; anda mapping step of mapping the LDPC code to any one of four signal points decided using a modulation method in a unit of 2 bits,wherein, in the group-wise interleaving, setting an i+1-th bit group from a head of the LDPC code as a bit group i, arrangement of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into arrangement of bit groups39, 47, 96, 176, 33, 75, 165, 38, 27, 58, 90, 76, 17, 46, 10, 91, 133, 69, 171, 32, 117, 78, 13, 146, 101, 36, 0, 138, 25, 77, 122, 49, 14, 125, 140, 93, 130, 2, 104, 102, 128, 4, 111, 151, 84, 167, 35, 127, 156, 55, 82, 85, 66, 114, 8, 147, 115, 113, 5, 31, 100, 106, 48, 52, 67, 107, 18, 126, 112, 50, 9, 143, 28, 160, 71, 79, 43, 98, 86, 94, 64, 3, 166, 105, 103, 118, 63, 51, 139, 172, 141, 175, 56, 74, 95, 29, 45, 129, 120, 168, 92, 150, 7, 162, 153, 137, 108, 159, 157, 173, 23, 89, 132, 57, 37, 70, 134, 40, 21, 149, 80, 1, 121, 59, 110, 142, 152, 15, 154, 145, 12, 170, 54, 155, 99, 22, 123, 72, 177, 131, 116, 44, 158, 73, 11, 65, 164, 119, 174, 34, 83, 53, 24, 42, 60, 26, 161, 68, 178, 41, 148, 109, 87, 144, 135, 20, 62, 81, 169, 124, 6, 19 ...

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Номер записи: 79
09-02-2017 дата публикации

Multiuse Data Channel

Номер: US20170041099A1
Автор: Ara Patapoutian, Hieu V. Nguyen
Принадлежит: SEAGATE TECHNOLOGY LLC

Presented is a data channel with selectable components, such as encoders or decoders. Also, data having different data signal characteristics can be processed through a data channel based on the data signal characteristics. Further, a data channel may have independent encoding path and an independent decoding path. For example, a first data transmission having first data signal characteristics may be processed via a data channel based on a first selected set of components of the data channel and a second data transmission having second data signal characteristics different than the first data signal characteristics may be processed via the data channel using a second selected set of components in the data channel. The first selected set of components may be different than the second selected set of components, but may share one or more common components.

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Номер записи: 80
08-02-2018 дата публикации

Zero padding apparatus for encoding variable-length signaling information and zero padding method using same

Номер: US20180041226A1
Автор: Heung-Mook Kim, Jae-Young Lee, Sun-Hyoung Kwon, Sung-Ik Park
Принадлежит: Electronics and Telecommunications Research Institute ETRI

A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.

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Номер записи: 81
11-02-2016 дата публикации

SYSTEMS AND METHODS FOR IMPROVED COMMUNICATION EFFICIENCY IN WIRELESS NETWORKS

Номер: US20160044675A1
Автор: Chen Jialing Li, Tandra Rahul, Tian Bin, Vermani Sameer, Yang Lin
Принадлежит:

Methods and apparatuses for providing wireless messages according to various tone plans can include a system configured to generate a message according to a 2048-tone plan having 1960 data tones. The 2048-tone plan includes two identical 1024-tone plans each having 980 data tones. The system can further perform segment parsing to divide data into two data portions, each portion for transmission over one of two 80 MHz bandwidths, according to one of the two identical 1024-tone plans. The system can further perform low density parity check (LDPC) tone mapping separately on each of the two data portions. The system can further provide the message for transmission over a 160 MHz bandwidth including the two 80 MHz bandwidths. 1. An apparatus configured to perform wireless communication , comprising:a memory that stores instructions; and generate a message according to a 2048-tone plan having 1960 data tones, the 2048-tone plan comprising two identical 1024-tone plans each having 980 data tones;', 'perform segment parsing to divide data into two data portions, each portion for transmission over one of two 80 MHz bandwidths, according to one of the two identical 1024-tone plans;', 'perform low density parity check (LDPC) tone mapping separately on each of the two data portions; and', 'provide the message for transmission over a 160 MHz bandwidth comprising the two 80 MHz bandwidths., 'a processing system coupled with the memory and configured to execute the instructions to2. The apparatus of claim 1 , wherein each of the two identical 1024-tone plans comprises 5 direct current tones corresponding to each of the two 80 MHz bandwidths.3. The apparatus of claim 1 , wherein the 2048-tone plan comprises 23 direct current tones corresponding to the 160 MHz bandwidth and 5 additional null tones corresponding to each of two 80 MHz segments.4. The apparatus of claim 1 , wherein performing LDPC tone mapping separately on each of the two data portions comprises using LDPC tone ...

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Номер записи: 82
24-02-2022 дата публикации

HIGH THROUGHPUT, LOW POWER, HIGH PARITY ARCHITECTURE FOR DATABASE SSD

Номер: US20220058140A1
Автор: ASFUR Mahmud, ZEHAVI Mordekhay, ZIMMERMAN Israel
Принадлежит:

A method and apparatus for the increase of internal data throughput and processing capability for SSD's, to enable processing of database commands on an SSD. A front-end ASIC is provided with 256 to 512 RISC processing cores to enable decomposition and parallelization of host commands to front-end module (FM) ASICs that each in turn are coupled to multiple NVM dies, as well as processing of host database operations such as insert, select, update, and delete. Each FM ASIC is architected to increase parity bits to 33.3% of NVM data, and process parity data with 14 LDPC's. By increasing the parity bits to 33.3%, BER is reduced, power consumption is reduced, and data throughput within the SSD is increased. 1. A data storage device , comprising:a front-end module ASIC (FM ASIC) comprising a plurality of LDPC engines, a plurality of flash interface modules (FIMs), each FIM coupled to a respective one of a plurality of NVM dies capable of storing data; anda front-end ASIC (FE ASIC) comprising a plurality of processing cores and coupled to the FM ASIC, configured to receive a database instruction from a host comprising one of a select, an update, an insert, and a delete instruction, and executing the database instruction with the plurality of processing cores within the data storage device.2. The data storage device of claim 1 , wherein more than about 10.0% of the data stored on one of the plurality of NVM dies is parity data.3. The data storage device of claim 2 , wherein about 33.3% of the data stored on one of the plurality of NVM dies is parity data.4. The data storage device of claim 3 , wherein at least one of the plurality of NVM dies is a BiCS 6 die.5. The data storage device of claim 2 , wherein the number of LDPC engines is less than about 54.6. The data storage device of claim 5 , wherein the number of LDPC engines is less than or equal to about 14 LDPC engines.7. The data storage device of claim 1 , wherein the number of processing cores is greater than about 5 ...

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Номер записи: 83
07-02-2019 дата публикации

ERROR CORRECTION CODE MEMORY SECURITY

Номер: US20190042362A1
Автор: Agarwal Rajat, Bolotov Anatoli, Grinchuk Mikhai
Принадлежит:

System and techniques for error correction code (ECC) memory security are described herein. A write request that includes data is received. An integrity check value (ICV) is computed for the data. Then, the write request is performed, including writing a representation of the data to a data area in memory and writing the ICV into an ECC area in memory. Here, the data area is addressable by a host and the ECC area corresponds to the data area via hardware of the memory. 1. A memory controller for error correction code (ECC) memory security , the memory controller comprising:a machine-readable medium including instructions; and receive a write request, the write request including data;', 'compute an integrity check value (ICV) for the data;', write a representation of the data to a data area in memory, the data area addressable by a host; and', 'write the ICV into an ECC area in memory, the ECC area corresponding to the data area via hardware of the memory., 'perform the write request including], 'processing circuitry that, when executing the instructions, operates to2. The memory controller of claim 1 , wherein claim 1 , to perform the write request claim 1 , the processing circuitry computes ECC information for the data.3. The memory controller of claim 2 , wherein claim 2 , to perform the write request claim 2 , the processing circuitry writes the ECC information to a second data area in the memory.4. The memory controller of claim 2 , wherein claim 2 , to compute the ECC information claim 2 , the processing circuitry restricts a size of the ECC information to be less than the ECC area.5. The memory controller of claim 4 , wherein the ECC information is a low-density parity-check (LDPC) code.6. The memory controller of claim 4 , wherein claim 4 , to perform the write request claim 4 , the processing circuitry writes the ECC information into the ECC area.7. The memory controller of claim 2 , wherein claim 2 , to perform the write request claim 2 , the processing ...

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Номер записи: 84
01-05-2014 дата публикации

Method and apparatus for channel coding and decoding in a communication system using a low-density parity-check code

Номер: US20140122961A1
Автор: Hong-Sil Jeong, Hyun-Koo Yang, Sung-Ryul Yun
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An apparatus and method are provided for channel coding in a communication system using a Low-Density Parity-Check (LDPC) code. The method includes determining degrees for each of a plurality of column groups of an information part; determining a shortening order based on the degrees; generating a parity check matrix based on the shortening order; and performing coding using the parity check matrix.

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Номер записи: 85
01-05-2014 дата публикации

Identification of non-volatile memory die for use in remedial action

Номер: US20140122963A1
Автор: Kiran Pangal, Ravi H. MOTWANI
Принадлежит: Intel Corp

Embodiments of apparatus, methods, storage drives, computer-readable media, systems and devices are described herein for identification of die of non-volatile memory for use in remedial action. In various embodiments, a first block may be configured to encode data to be stored in a non-volatile memory as a codeword. In various embodiments, the first block may be configured to store respective portions of the codeword in a distributed manner across a plurality of die of the non-volatile memory. In various embodiments, the first block may be configured to generate respective error detection codes for the plurality of die.

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Номер записи: 86
07-02-2019 дата публикации

TRANSMITTER, RECEIVER, AND SIGNAL PROCESSING METHOD THEREOF

Номер: US20190044652A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitter and receiver of a broadcasting signal and a method of processing the broadcasting signal are provided. The transmitter includes: a segmenter configured to segment an L signaling of a frame into a plurality of segmented L signalings such that each of the segmented L signalings has bits a number of which is equal to or smaller than a predetermined number; and an encoder configured to perform a Bose, Chaudhuri, Hocquenghem (BCH) and a low density parity check (LDPC) encoding, or the LDPC encoding without the BCH encoding, with respect to the segmented L signalings. 1. A signal generation and transmitting apparatus comprising:a segmenter configured to segment input bits into a plurality of segmented blocks according to a segmentation value, if a size of the input bits is greater than the segmentation value;a zero padder configured to fill a bit space of a predetermined size with bits and one or more zero padding bits, if a size of the bits is less than the predetermined size, the bits comprising bits of each of the plurality of segmented blocks;an encoder configured to encode bits included in the bit space to generate parity bits based on a code;a puncturer configured to puncture one or more parity bits from among the generated parity bits;a zero remover configured to remove the one or more zero padding bits from the encoded bits included in the bit space;a mapper configured to map remaining encoded bits after removing and remaining parity bits after the puncturing onto constellation points; anda transmitter configured to transmit a signal which is generated based on the constellation points,wherein the segmentation value is based on the code, a zero padding parameter and a puncturing parameter.2. The signal generation and transmitting as claimed in claim 1 , further comprising:an encoder configured to encode the plurality of segmented blocks based on a first code to generate a codeword respectively, the codeword comprising bits of a segmented block and ...

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Номер записи: 87
18-02-2021 дата публикации

Transmitting apparatus and method for controlling the transmitting apparatus

Номер: US20210050867A1
Автор: Yunkyoung HAN
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A transmitting apparatus and a method of controlling the transmitting apparatus are provided. The transmitting apparatus includes an encoder; a transmitter; and a processor. The processor is configured to: control the encoder to generate repair symbols by performing encoding of source symbols based on information received from a receiving apparatus, and control the transmitter to transmit, to the receiving apparatus, the source symbols and at least some of the repair symbols. The information includes information indicating whether a decoding of symbols received from the receiving apparatus is successful, the symbols including the source symbols and the repair symbols, and a number of repair symbols transmitted to the receiving apparatus varies according to the decoding of the receiving apparatus being successful.

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Номер записи: 88
18-02-2016 дата публикации

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 5/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

Номер: US20160049952A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, PARK Sung-Ik
Принадлежит:

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 1. A low density parity check (LDPC) encoder , comprising:first memory configured to store an LDPC codeword having a length of 64800 and a code rate of 5/15;second memory configured to be initialized to 0; anda processor configured to generate the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).2. The LDPC encoder of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 21600 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1440 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 41760.3. The LDPC encoder of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 21600 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1440 claim 2 , by the CPM size.5. The LDPC encoder of claim 4 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.6. The LDPC encoder of claim 5 , wherein the accumulation is performed while the rows of the sequence are being ...

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Номер записи: 89
18-02-2016 дата публикации

Low density parity check encoder having length of 16200 and code rate of 2/15, and low density parity check encoding method using the same

Номер: US20160049953A1
Автор: Heung-Mook Kim, Nam-Ho Hur, Sun-Hyoung Kwon, Sung-Ik Park
Принадлежит: Electronics and Telecommunications Research Institute ETRI

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

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Номер записи: 90
18-02-2016 дата публикации

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

Номер: US20160049954A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, PARK Sung-Ik
Принадлежит:

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 1. A low density parity check (LDPC) encoder , comprising:first memory configured to store an LDPC codeword having a length of 16200 and a code rate of 3/15;second memory configured to be initialized to 0; anda processor configured to generate the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).2. The LDPC encoder of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 3240 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1080 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 11880.3. The LDPC encoder of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 3240 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1080 claim 2 , by the CPM size.5. The LDPC encoder of claim 4 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.6. The LDPC encoder of claim 5 , wherein the accumulation is performed while the rows of the sequence are being ...

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Номер записи: 91
18-02-2016 дата публикации

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 4/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

Номер: US20160049955A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, PARK Sung-Ik
Принадлежит:

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 1. A low density parity check (LDPC) encoder , comprising:first memory configured to store an LDPC codeword having a length of 16200 and a code rate of 4/15;second memory configured to be initialized to 0; anda processor configured to generate the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).2. The LDPC encoder of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 4320 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1080 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 10800.3. The LDPC encoder of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 4320 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1080 claim 2 , by the CPM size.5. The LDPC encoder of claim 4 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.6. The LDPC encoder of claim 5 , wherein the accumulation is performed while the rows of the sequence are being ...

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Номер записи: 92
18-02-2016 дата публикации

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 5/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

Номер: US20160049956A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, PARK Sung-Ik
Принадлежит:

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 1. A low density parity check (LDPC) encoder , comprising:first memory configured to store an LDPC codeword having a length of 16200 and a code rate of 5/15;second memory configured to be initialized to 0; anda processor configured to generate the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).2. The LDPC encoder of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 5400 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 720 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 10080.3. The LDPC encoder of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 5400 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 720 claim 2 , by the CPM size.5. The LDPC encoder of claim 4 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.6. The LDPC encoder of claim 5 , wherein the accumulation is performed while the rows of the sequence are being ...

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Номер записи: 93
18-02-2016 дата публикации

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

Номер: US20160049957A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, PARK Sung-Ik
Принадлежит:

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 1. A low density parity check (LDPC) encoder , comprising:first memory configured to store an LDPC codeword having a length of 64800 and a code rate of 2/15;second memory configured to be initialized to 0; anda processor configured to generate the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).2. The LDPC encoder of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 8640 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1800 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 54360.3. The LDPC encoder of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 8640 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1800 claim 2 , by the CPM size.5. The LDPC encoder of claim 4 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.6. The LDPC encoder of claim 5 , wherein the accumulation is performed while the rows of the sequence are being ...

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Номер записи: 94
18-02-2016 дата публикации

Low density parity check encoder having length of 64800 and code rate of 3/15, and low density parity check encoding method using the same

Номер: US20160049958A1
Автор: Heung-Mook Kim, Nam-Ho Hur, Sun-Hyoung Kwon, Sung-Ik Park
Принадлежит: Electronics and Telecommunications Research Institute ETRI

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

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Номер записи: 95
18-02-2016 дата публикации

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 4/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

Номер: US20160049959A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, PARK Sung-Ik
Принадлежит:

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 1. A low density parity check (LDPC) encoder , comprising:first memory configured to store an LDPC codeword having a length of 64800 and a code rate of 4/15;second memory configured to be initialized to 0; anda processor configured to generate the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).2. The LDPC encoder of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 17280 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1800 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 45720.3. The LDPC encoder of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 17280 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1800 claim 2 , by the CPM size.5. The LDPC encoder of claim 4 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.6. The LDPC encoder of claim 5 , wherein the accumulation is performed while the rows of the sequence are being ...

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Номер записи: 96
06-02-2020 дата публикации

APPARATUS AND METHOD FOR CHANNEL CODING IN COMMUNICATION SYSTEM

Номер: US20200044665A1
Автор: Liu Xiaojian, Ma Liang, Wei Yuejun, Zeng Xin, Zheng Chen
Принадлежит: Huawei Technologies CO.,Ltd.

This application relates to communicating information between communication devices. A channel coding method is disclosed. A communication device obtains an input sequence of K bits. The communication device encodes the input sequence using a low density parity check (LDPC) matrix H, to obtain an encoded sequence. The LDPC matrix H is determined according to a base matrix and a lifting factor Z. The base matrix includes m rows and n columns, m is greater than or equal to 5, and n is greater than or equal to 27. The lifting factor Z satisfies a relationship of 22*Z≥K. According to the encoding method provided in the embodiments, information bit sequences of a plurality of lengths can be encoded for transmission between the communication devices. 3. The device according to claim 2 , wherein in obtaining the encoding matrix H by replacing each element of the LDPC base graph with a matrix of Z rows and Z columns claim 2 , the processor is configured to:replace each element of value 0 in the LDPC base graph with an all zero matrix of Z rows×Z columns; and{'sub': i,j', 'i,j', 'i,j', 'i,j', 'i,j', 'i,j', 'i,j', 'i,j, 'replace a {row index i, column index j} element of value 1 in the LDPC base graph by a circular permutation matrix I(P) of Z rows×Z columns, wherein the circular permutation matrix I(P) is obtained by circularly shifting an identity matrix of Z rows×Z columns to the right Ptimes, wherein P=mod (V, Z), Vis a shift value corresponding to a lifting factor set index of Z, Vis an integer, and V≥0.'}4. The device according to claim 1 , wherein K=22×Z.5. The device according to claim 1 , wherein the input sequence is c={c claim 1 ,c claim 1 ,c claim 1 , . . . claim 1 ,c} claim 1 , the encoded sequence is d={d claim 1 , d claim 1 , d claim 1 , . . . claim 1 , d} claim 1 , wherein c(i=0 claim 1 , 1 claim 1 , . . . K−1) are information bits claim 1 , d(j=0 claim 1 , 1 claim 1 , . . . N−1) are encoded bits claim 1 , N is a positive integer claim 1 , and N=66×Z.7. The ...

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Номер записи: 97
18-02-2021 дата публикации

CODING CONTROL METHOD AND APPARATUS IN A PASSIVE OPTICAL NETWORK, COMMUNICATION DEVICE AND STORAGE MEDIUM

Номер: US20210050943A1
Автор: GUO Yong, Huang Xingang, LIU ZHENG, LU Liuming, Yuan Liquan, Zhang Weiliang
Принадлежит:

Provided is a coding control method in a passive optical network (PON). The method includes acquiring a codeword length N corresponding to a service to be coded; acquiring a matched coding mode corresponding to the codeword length N in a preset table describing a correspondence between codeword length ranges and coding modes; and coding data of the service by using the matched coding mode. Further provided are a coding control apparatus in a PON, a communication device and a storage medium. 1. A coding control method in a passive optical network , comprising:acquiring a codeword length N corresponding to a service to be coded;matching, in a preset correspondence table between codeword length ranges and coding modes, a coding mode corresponding to the codeword length N; andcoding data of the service by using the matched coding mode.2. The method of claim 1 , whereinthe correspondence table between the codeword length ranges and the coding modes comprises at least two coding modes, each of the at least two coding modes corresponds to at least one of the codeword length ranges, and the codeword length N is N bits.3. The method of claim 2 , wherein the correspondence table between the codeword length ranges and the coding modes comprises Reed-Solomon (RS) coding claim 2 , low density parity check code coding claim 2 , a first codeword length range corresponding to the RS coding and a second codeword length range corresponding to the low density parity check code coding; matching the codeword length N with the first codeword length range and the second codeword length range;', 'in response to a matching result that the codeword length N is within the first codeword length range, determining that the coding mode corresponding to the codeword length N is the RS coding; and', 'in response to a matching result that the codeword length N is within the second codeword length range, determining that the coding mode corresponding to the codeword length N is the low density ...

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Номер записи: 98
06-02-2020 дата публикации

TRANSMISSION OF PROBABILISTICALLY SHAPED AMPLITUDES USING PARTIALLY ANTI-SYMMETRIC AMPLITUDE LABELS

Номер: US20200044770A1
Автор: Lefevre Yannick
Принадлежит: NOKIA SOLUTIONS AND NETWORKS OY

A communication system in which a constellation employing partially anti-symmetric amplitude labels is used to transmit probabilistically shaped amplitudes such that said amplitudes are also used to determine the signs applied thereto for transmission. In an example embodiment, a data transmitter is configured to use a suitable logic function (e.g., an XOR function) to place the parity generated by an FEC code into a selected amplitude bit while using the partially anti-symmetric amplitude labels to avoid placing the parity into the sign bits of the transmitted constellation symbols. In some embodiments, the FEC code can be a low-density parity-check code. Some embodiments are compatible with layered FEC coding, e.g., employing an outer FEC code and an inner FEC code. In some embodiments, FEC coding may be optional. Some embodiments can advantageously be used in communication systems relying on DMT modulation, such as the systems providing DSL access over copper wiring. 1. An apparatus comprising a data transmitter that comprises an electrical analog front end and a digital signal processor , the digital signal processor being configured to:redundancy-encode an input data stream to generate a constellation-symbol stream; anddrive the analog front end to cause one or more modulated electrical carriers generated by the analog front end to carry constellation symbols of the constellation-symbol stream; and a demultiplexer configured to demultiplex the input data stream to generate a first sub-stream and a second sub-stream;', 'a shaping encoder configured to generate a first encoded data stream and a second encoded data stream (by applying a shaping code to the first sub-stream; and', use the second encoded data stream to select constellation-symbol amplitudes for the constellation-symbol stream; and', 'use the first encoded data stream and the second sub-stream to select at least some signs applied to the constellation-symbol amplitudes., 'a constellation mapper ...

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Номер записи: 99
16-02-2017 дата публикации

TRANSMISSION METHOD, RECEPTION METHOD, TRANSMISSION DEVICE AND RECEPTION DEVICE

Номер: US20170048020A1
Автор: Kimura Tomohiro, MURAKAMI Yutaka, Ouchi Mikihiro
Принадлежит:

One coding method is selected from a plurality of coding methods per data symbol group, an information sequence is encoded by using the selected coding method. The plurality of coding methods includes at least a first coding method and a second coding method. The first coding method is a coding method with a first coding rate for generating a first codeword as a first encoded sequence by using a first parity check matrix. The second coding method is a coding method with a second coding rate different from the first coding rate and obtained after puncturing processing, where a second encoded sequence is generated by performing the puncturing processing on a second codeword by using a second parity check matrix different from the first parity check matrix. A number of bits of the first encoded sequence is equal to a number of bits of the second encoded sequence. 1. A transmission method using a plurality of coding methods , comprising:selecting one coding method from the plurality of coding methods per data symbol group, encoding an information sequence by using the selected coding method to obtain an encoded sequence;modulating the encoded sequence to obtain data symbols; andtransmitting a transmission frame that includes a plurality of data symbol groups, each of the plurality of data symbol groups including the obtained data symbols,whereinthe plurality of coding methods includes at least a first coding method and a second coding method,the first coding method is a coding method with a first coding rate for generating a first codeword as a first encoded sequence by using a first parity check matrix,the second coding method is a coding method with a second coding rate that is different from the first coding rate and is a coding rate after puncturing processing, in which a second encoded sequence is generated by performing the puncturing processing on a second codeword by using a second parity check matrix that is different from the first parity check matrix, anda ...

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Номер записи: 100