Multilayered printed circuit board and manufacturing method thereof

An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22 , the thickness of which is reduced (to 3 μm) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20 a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be prevented. Thus, the reliability of the connection of the via holes can be improved.

Wiring substrate and semiconductor package

A wiring substrate includes an insulating layer and a wiring layer buried in the insulating layer at a first surface of the insulating layer. The wiring layer includes a first portion and a second portion. The first portion is narrower and thinner than the second portion. The first portion includes a first surface exposed at the first surface of the insulating layer. The second portion includes a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer. The opening is open at a second surface of the insulating layer opposite to the first surface thereof.

WIRING BOARD

A wiring substrate includes: an insulating substrate comprising a corner constituted by two adjacent surfaces; wiring located continuously across the corner; wherein on at least one of the two adjacent surfaces, a part of the wiring disposed at an edge located at the corner has a thickness larger than a part of the wiring disposed away from the edge. 1. A wiring substrate for mounting an electronic element , comprising:an insulating substrate comprising a corner constituted by two adjacent surfaces;wiring located continuously across the corner;wherein on at least one of the two adjacent surfaces, a part of the wiring disposed at an edge located at the corner has a thickness larger than a part of the wiring disposed away from the edge.2. The wiring substrate according to claim 1 ,wherein the thickness of the wiring has a gradual increase from the part of the wiring disposed away from the edge toward the part of the wiring disposed at the edge.3. The wiring substrate according to claim 1 ,wherein on each of the two adjacent surfaces, the part of the wiring disposed at the edge located at the corner has the thickness larger than the part of the wiring disposed away from the edge.4. The wiring substrate according to claim 1 ,wherein one of the two adjacent surfaces is a main surface having an element mounting portion, and another of the two adjacent surfaces is a side-end surface.5. The wiring substrate according to claim 4 ,wherein the thickness of the wiring on the main surface has a gradual increase from the part of the wiring disposed away from the edge toward the part of the wiring disposed at the edge, andwherein the thickness of the wiring on the side-end surface has a gradual increase from the part of the wiring disposed away from the edge toward the part of the wiring disposed at the edge.6. The wiring substrate according to claim 5 ,wherein a gradient of the gradual increase of the thickness of the wiring on the main surface is less than a gradient of the ...

MEMORY CARD AND ELECTRONIC APPARATUS INCLUDING THE SAME

A memory card includes a substrate, first row terminals and second row terminals. The substrate has a first pair of side edges extending in a first direction and a second pair of side edges extending in a second direction perpendicular to the first direction. The first row terminals are arranged adjacent to an insertion side edge of the substrate, the first row terminals including a first power terminal, the insertion side edge being one of the first pair of side edges. The second row terminals are arranged further from the insertion side edge than the first row terminals, the second row terminals including a second power terminal. At least one terminal among the first and second row terminals includes a recess area in an exposed surface of the at least one terminal. 1. A memory card comprising:a substrate having a first pair of side edges extending in a first direction and a second pair of side edges extending in a second direction perpendicular to the first direction;first row terminals arranged adjacent to an insertion side edge of the substrate, the first row terminals including a first power terminal, the insertion side edge being one of the first pair of side edges; andsecond row terminals arranged further from the insertion side edge than the first row terminals, the second row terminals including a second power terminal,wherein at least one terminal among the first and second row terminals includes a recess area in an exposed surface of the at least one terminal.2. The memory card of claim 1 , wherein the recess area has a concave recess shape at a center portion of the at least one terminal.3. The memory card of claim 2 , wherein a side surface of the concave recess shape is tapered.4. The memory card of claim 3 , wherein the concave recess shape is a cone shape.5. The memory card of claim 3 , wherein the concave recess shape is a truncated cone shape having a radius decreasing toward a bottom.6. The memory card of claim 5 , wherein surface roughness of an ...

MEMORY CARD AND ELECTRONIC APPARATUS INCLUDING THE SAME

A memory card includes a substrate, first row terminals and second row terminals. The substrate has a first pair of side edges extending in a first direction and a second pair of side edges extending in a second direction perpendicular to the first direction. The first row terminals are arranged adjacent to an insertion side edge of the substrate, the first row terminals including a first power terminal, the insertion side edge being one of the first pair of side edges. The second row terminals are arranged further from the insertion side edge than the first row terminals, the second row terminals including a second power terminal. At least one recessed terminal among the first and second row terminals includes a recess area in an exposed surface of the at least one terminal. 1. A memory card comprising:a substrate having a first pair of side edges extending in a first direction and a second pair of side edges extending in a second direction perpendicular to the first direction; andterminals arranged adjacent to an insertion side edge of the substrate, the insertion side edge being one of the first pair of side edges,wherein at least one recessed terminal from among the terminals includes a recess area in an exposed surface of the at least one terminal.2. The memory card of claim 1 , wherein the recess area has a concave recess shape at a center portion of the at least one recessed terminal.3. The memory card of claim 2 , wherein a side surface of the concave recess shape is tapered.4. The memory card of claim 3 , wherein the concave recess shape is a cone shape.5. The memory card of claim 3 , wherein the concave recess shape is a truncated cone shape having a radius decreasing toward a bottom thereof.6. The memory card of claim 5 , wherein surface roughness of an exposed bottom surface of the concave recess shape is greater than surface roughness of an exposed upper surface of the at least one recessed terminal claim 5 , the exposed surface including the exposed ...

Multilayer printed wiring board and method for manufacturing the same

개구가 수지(20)에 레이저에 의하여 형성되고 그에 따라 바이어홀이 형성된다. 이때에 열전도율을 낮추기 위하여 에칭에 의하여 그 두께가 3 ㎛ 로까지 처리된 동박(22)이 콘포멀마스크로서 사용된다. 따라서 펄스형의 레이저빔의 조사수가 감소하여도 수지(20)에 개구(20a)가 형성된다. 따라서, 수지층의 층간절연을 수행하는 수지(20)의 언더컷의 발생이 방지된다. 그에 따라 바이어홀의 연결성의 신뢰도가 향상되는 것이다. An opening is formed in the resin 20 by a laser and a via hole is formed accordingly. At this time, in order to lower thermal conductivity, the copper foil 22 processed by the etching to 3 micrometers in thickness is used as a conformal mask. Therefore, even if the number of irradiation of the pulsed laser beam decreases, the opening 20a is formed in the resin 20. Therefore, occurrence of undercut of the resin 20 which performs interlayer insulation of the resin layer is prevented. As a result, the reliability of the via hole connectivity is improved. 다층프린트배선판 Multilayer printed wiring board

Method for forming a plated microvia interconnect

A method for forming a plated microvia interconnect. An external dielectric layer (EDL) is mounted on a substrate in direct mechanical contact with a conductive element thereon. An opening in the EDL exposes the conductive element and create a microvia in the EDL. A sidewall and bottom wall surface of the microvia are treated to promote adhesion of copper and are plated with a layer of copper that includes a copper layer on a copper seed layer and is in direct mechanical and electrical contact with the conductive element. A wet solder paste is deposited on the layer of copper to overfill a remaining portion of the microvia. The solder paste is reflowed to form a solder bump in and over the remaining portion of the microvia to form the plated microvia interconnect. A stiffener is attached to the EDL using a first adhesive.

Laminate having plated microvia interconnects and method for forming the same

A chip carrier structure and method for forming the same having a receptor pad formed therein. The structure comprises a circuitized substrate having a conductive element on the surface, an External Dielectric Layer mounted on the circuitized substrate with an opening positioned above the conductive element to form a microvia. The walls of the microvia are first treated to enhance copper adhesion and then are electroplated to provide a receptor pad. Finally, a solder paste is deposited within the microvia to create a solder deposit or bump.

Method for forming a plated microvia interconnect

A method for forming a plated microvia interconnect. An external dielectric layer (EDL) is mounted on a surface of the substrate and is in direct mechanical contact with a conductive element included in the surface. An opening formed in the EDL exposes the conductive element and creates a microvia in the EDL. A sidewall and bottom wall surface of the microvia is treated to promote copper adhesion to the sidewall and bottom wall surfaces. The sidewall and bottom wall surfaces are plated to form a layer of copper thereon. The layer of copper is in direct mechanical and electrical contact with the conductive element. A wet solder paste deposited on the layer of copper overfills a remaining portion of the microvia. The solder paste is reflowed to form a solder bump in and over the remaining portion of the microvia to form the plated microvia interconnect.

制造多层印刷电路板的方法

这样形成多层印刷电路板，即多个在其间分别插有绝缘层的导体层被叠置为一个整体，在绝缘层中设置以露出的导体层作为底部的非贯穿的孔，并在孔中设置用于导体层之间电连接的镀层，该孔被形成为在其轴向剖面图中，至少在孔的内周边到底面的延续区域处有半径在20-100μm的范围内的凹形曲面，由此因镀敷镀层产生的等电位面沿该延续区域也是弯曲的，因而用于镀层厚度均匀的电流密度均匀而不会在该延续区域处变薄。

Method for filling high aspect ratio via holes in electronic substrates and the resulting holes

High aspect ratio (5:1-30:1) and small (5 μm-125 μm) diameter holes in a dielectric substrate are provided, which are filled with a solidified conductive material, as well as a method of filling such holes using pressure and vacuum. In certain embodiments, the holes are lined with conductive material and/or capped with a conductive material. The invention also contemplates a chip carrier formed by such material.

Method for filling high aspect ratio via holes in electronic substrates and the resulting holes

High aspect ratio (5:1-30:1) and small (5 μm-125 μm) diameter holes in a dielectric substrate are provided, which are filled with a solidified conductive material, as well as a method of filling such holes using pressure and vacuum. In certain embodiments, the holes are lined with conductive material and/or capped with a conductive material. The invention also contemplates a chip carrier formed by such material.

Wiring board and manufacturing method thereof

Multilayer printed wiring board and method for manufacturing the same

개구가 수지(20)에 레이저에 의하여 형성되고 그에 따라 바이어홀이 형성된다. 이때에 열전도율을 낮추기 위하여 에칭에 의하여 그 두께가 3 ㎛ 로까지 처리된 동박(22)이 콘포멀마스크로서 사용된다. 따라서 펄스형의 레이저빔의 조사수가 감소하여도 수지(20)에 개구(20a)가 형성된다. 따라서, 수지층의 층간절연을 수행하는 수지(20)의 언더컷의 발생이 방지된다. 그에 따라 바이어홀의 연결성의 신뢰도가 향상되는 것이다. An opening is formed in the resin 20 by a laser and a via hole is formed accordingly. At this time, in order to lower thermal conductivity, the copper foil 22 processed by the etching to 3 micrometers in thickness is used as a conformal mask. Therefore, even if the number of irradiation of the pulsed laser beam decreases, the opening 20a is formed in the resin 20. Therefore, occurrence of undercut of the resin 20 which performs interlayer insulation of the resin layer is prevented. As a result, the reliability of the via hole connectivity is improved. 다층프린트배선판 Multilayer printed wiring board

Many circuit board and manufacture methods thereof in flakes

提供多连片布线基板及其制造方法，在分割时或在分割之前，难以从分割槽附近发生碎裂、裂纹或断裂并且具有高可靠性。多连片布线基板(1)通过层叠多层陶瓷层(s1)、(s2)形成并且具有正面(2)和背面(3)。多连片布线基板(1)包括：产品区域(4a)，其中以矩阵形式排列在平面图中具有矩形形状并且包括空腔(5)的多个布线基板部分(4)；沿着产品区域(4a)的外周定位的边缘部分(6)；以及沿着布线基板部分(4)和(4)之间的分界及布线基板部分(4)和边缘部分(6)之间的分界在正面(2)和背面(3)中的至少一个面形成的分割槽(8)和(9)。在与延伸方向正交的截面中，分割槽(8)和(9)的最深部分(8b)具有圆弧形状，且各分割槽(8)和(9)均包括位于最深部分(8b)和槽入口(8c)之间的中间部分(8a)。最深部分(8b)的宽度(w2)大于槽入口(8c)的宽度(w3)，并且中间部分(8a)的宽度(w1)等于或小于槽入口(8c)的宽度(w3)。

Electrical connection device and method of forming the same

Chip substrate for preventing burr generating and method for manufacturing the same

본 발명은 칩원판 및 이를 제조 방법에 관한 것으로, 보다 상세하게는 광소자 칩이 실장되는 칩원판에 관한 것으로, 절단에 따른 버를 방지하는 칩원판은 칩원판에 대하여 일 방향으로 적층된 복수의 전도층; 상기 전도층과 교호로 적층되어 상기 전도층을 전기적으로 분리시키는 적어도 하나의 절연층; 및 미리 결정된 칩기판 영역에 따른 상기 칩원판의 절단시 절단면과 상기 절연층이 접하는 영역에서, 상기 절연층을 포함하여 상기 칩원판을 관통하는 관통공을 포함한다. 본 발명에 따르면, 광디바이스의 절단면에 대하여 절연층을 포함하는 소정의 관통구를 형성함으로써, 칩원판에서 광디바이스의 분리, 즉 소잉(sawing) 또는 다이싱(dicing) 과정에서 버를 발생시키지 않아 발생된 버가 절연층을 타고 넘어가는 등의 상황에 의해 발생되는 전기적인 쇼트를 방지할 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a chip original plate and a method of manufacturing the same, and more particularly to a chip original plate on which an optical device chip is mounted, Conductive layer; At least one insulating layer stacked alternately with the conductive layer to electrically isolate the conductive layer; And a through hole penetrating the chip original plate including the insulating layer in a region where the cut surface and the insulating layer contact with each other when the chip original plate is cut along the predetermined chip substrate region. According to the present invention, by forming a predetermined through-hole including an insulating layer on a cut surface of an optical device, burring is not generated in the process of separating, i.e., sawing or dicing an optical device in a chip original plate It is possible to prevent electrical short-circuiting caused by a situation such that burrs that have been generated pass over the insulating layer.

Conductive circuit structure having an electrically conductive surface fixed by collar walls

An electrically conductive circuit conductor 2 is disposed on an insulating resin substrate 1, an electrically conductive surface 3 of the circuit conductor is exposed from the resin substrate continuously in a longitudinal direction, and both side portions 4 of the conductive surface are covered and fixed by collar walls 5 of the resin substrate. A bus bar or an electrically conductive resin material is used as the circuit conductor 2. The bus bar 2 is insert-molded onto the resin substrate. The electrically conductive resin material is poured and solidified in a groove portion in the resin substrate. A contact terminal on a mating circuit side or electrical component side is brought into contact with the conductive surface of the circuit conductor 2. A second circuit board is laminated on the resin substrate, and an insertion hole for allowing the conductive surface of the circuit conductor 2 to be exposed is provided in the second circuit board, and the contact terminal is inserted in the insertion hole. Other contact terminals on the mating circuit side or electrical component side are brought into contact with circuits of the second circuit board.

Wiring substrate including via interconnect whose side surface includes projection

A wiring substrate includes a first wiring layer on a surface of a first insulating layer; a via interconnect including a first portion connected to the first wiring layer and a second portion formed monolithically with the first portion and extending from an end of the first portion in a direction away from the first wiring layer; a second insulating layer on the first insulating layer; and a second wiring layer on the second insulating layer, contacting a first surface of the second portion. The area of a cross section of the first portion, parallel to the surface of the first insulating layer, increases as the position of the cross section approaches the first wiring layer from the second portion. The second portion includes a second surface that is opposite from its first surface and extends horizontally from the end of the first portion to overhang the first portion.

Method of manufacturing multilayered circuit board

An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22 , the thickness of which is reduced (to 3 μm) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20 a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.

Multi-layered wiring board, prefabricated material of multi-layered wiring board, manufacturing method of multilayered wiring board, method of forming electronic component, electronic component package and conductive filler

본 발명은 도전성 필러를 배선층의 충간접속에 이용한 다층배선기판에 관한 것이다. 이 다층배선기판의 배선층의 비아 랜드에는 관통공이 형성되어 있고, 도전성 필러와 배선층에 형성된 비아 랜드의 접속시에, 도전성 필러와 배선층의 사이에 걸리는 응력을 해방할 수 있다. 또, 도전성 필러와 비아 랜드의 접촉부는 도전성 필러의 외측면과 비아 랜드 표면이 매끈하게 연속한 형상을 갖고 있으므로, 노치효과를 완화할 수 있다. 따라서, 다층배선기판의 제조공정, 전자부품의 실장공정 등에서 층간접속부에 응력이 걸리는 경우에도 접속신뢰성을 확보할 수 있다. The present invention relates to a multilayer wiring board using a conductive filler for interlayer connection of a wiring layer. Through-holes are formed in the via lands of the wiring layer of the multilayer wiring board, and the stress applied between the conductive filler and the wiring layer can be released when the conductive filler and the via land formed in the wiring layer are connected. In addition, since the contact portion of the conductive filler and the via land has a shape in which the outer surface of the conductive filler and the via land surface are smoothly continuous, the notch effect can be alleviated. Therefore, connection reliability can be ensured even when stress is applied to the interlayer connection part in the manufacturing process of the multilayer wiring board, the mounting process of the electronic component, and the like.

PCB connector having a conductive base body having a spring body and a put-through body

The invention relates to a PCB connector for fastening a first printed circuit board on a second printed circuit board. The PCB connector may have a longitudinal base body with a clamping and fastening device for tool-free fastening of the PCB connector on a printed circuit board. The clamping and fastening device has a put-through body and a spring body which is formed extendable upon putting-through the put-through body through the land. The base body is thus pressed against the printed circuit board by the spring body.

Wiring board and mounting structure using same

Multilayer Printed Wiring Board

A multilayer printed wiring board comprises insulating layers and conductor layers being stacked alternately on each other. The conductor layers are electrically connected to each other through viaholes formed in the insulating layers. Each of the viaholes is formed to bulge in a direction generally orthogonal to the direction of thickness of the insulating layer. The multilayer printed wiring board is to have electronic components such as a capacitor, IC and the like mounted on the surface layer thereof.

Multilayer printed wiring board

A multilayer printed wiring board comprises insulating layers and conductor layers being stacked alternately on each other. The conductor layers are electrically connected to each other through viaholes formed in the insulating layers. Each of the viaholes is formed to bulge in a direction generally orthogonal to the direction of thickness of the insulating layer. The multilayer printed wiring board is to have electronic components such as a capacitor, IC and the like mounted on the surface layer thereof.

The manufacturing method of multi-layered wiring board

一种多层配线基板的制造方法，其具有：工序(1)，使用敷形法或直接激光法，设置从上层配线用金属箔到内层配线的通孔用孔、形成于该通孔用孔的开口部的上层配线用金属箔的突出、以及在该金属箔的突出与所述通孔用孔的内壁之间形成的下方空间；以及工序(2)，通过在所述通孔用孔内和上层配线用金属箔上形成填充电镀层来填埋所述通孔用孔，所述工序(2)中通过形成填充电镀层而进行的通孔用孔的填埋如下进行：在填充电镀的中途使填充电镀的电流密度暂时降低，再使其增加。

Method for manufacturing multilayer wiring substrate

一种多层配线基板的制造方法，其具有：工序(1)，使用敷形法或直接激光法，设置从上层配线用金属箔到内层配线的通孔用孔、形成于该通孔用孔的开口部的上层配线用金属箔的突出、以及在该金属箔的突出与所述通孔用孔的内壁之间形成的下方空间；以及工序(2)，通过在所述通孔用孔内和上层配线用金属箔上形成填充电镀层来填埋所述通孔用孔，所述工序(2)中通过形成填充电镀层而进行的通孔用孔的填埋如下进行：在填充电镀的中途使填充电镀的电流密度暂时降低，再使其增加。

PCB connector

本發明是關於一種用以將一第一印刷電路板固定於一第二印刷電路板上的印刷電路板(PCB)連接器。該PCB連接器包含一具有鉗夾及固定裝置的縱向導電基底本體，而該裝置可供按免工具的方式將該PCB連接器固定於一印刷電路板上。該鉗夾及固定裝置具有一貫穿本體，以及一當將該貫穿本體貫穿該銲點時可為延展所構成的彈簧本體。因此，該基底本體是藉由該彈簧本體以按壓於該印刷電路板上。

Multilayered printed circuit board and manufacturing method therefor

A multilayered printed circuit board comprising: a substrate (330) on which a conductive circuit (334) is formed; an interlayer insulating resin layer (350) formed on the conductive circuit (334); an opening (348) for forming a via hole (360) formed in the interlayer insulating resin layer (350); and another conductive circuit (358) including a via hole (360) and formed on the interlayer insulating resin layer (350), wherein the surface of the conductive circuit (334) is subjected to a coarsening process using etching solution containing cupric complex and organic acid, and stripe pits and projections are formed on the inner wall of the opening (348) for forming the via hole (360).

Substrate having through via and method of fabricating the same

A method of fabricating a substrate having a through via includes: providing a carrier board having a release layer thereon; attaching the substrate onto the carrier board via the release layer; applying a light beam to the substrate to form a first blind hole in the substrate, wherein the first blind hole penetrates a first surface and a second surface of the substrate; performing an enlargement process on the first blind hole to form a second blind hole; forming a through via in the second blind hole; and performing a de-bonding process to release the substrate having a through via from the carrier board.

Multilayer printed wiring board and method for manufacturing same

A multilayer printed wiring board is formed with a plurality of conductor layers laminated as a whole with insulating layers interposed, a non-penetrating via hole provided in the insulating layer as bottomed by the conductor layer exposed, a plated layer provided inside the via hole for electric connection between the conductor layers, the via hole being formed to be of a concave curved surface of a radius in a range of 20 to 100 μm in axially sectioned view at continuing zone of inner periphery to bottom surface of the via hole, whereby the equipotential surfaces occurring upon plating the plated layer are curved along the continuing zone to unify the density of current for rendering the plated layer uniform in the thickness without being thinned at the continuing zone.

Prevent from generating the bottom substrate and its manufacturing method of flash in cutting process

本发明涉及底部基板及其制造方法，具体地，涉及光学器件芯片安装在其上的底部基板，并且防止在切割过程中产生毛边的所述底部基板包括：相对于底部基板在一个方向上堆叠的多个导电层；至少一个绝缘层，其与所述导电层交替地堆叠并且电气隔离所述导电层；及通孔，在根据芯片基板的预定区域切割所述底部基板期间，该通孔在切割表面和所述绝缘层相交的接触区域处穿透覆盖所述绝缘层的所述底部基板。根据本发明，消除了由于毛边越过绝缘层及类似物而出现的电气短路，这是因为，通过相对于光学器件的切割表面形成了覆盖绝缘层的预定通孔，使得在光学器件从底部基板分离的过程中，即，在锯切或划片过程中，不会产生毛边。

Multilayer printed wiring board

Memory card and electronic apparatus including the same

본 발명의 기술적 사상에 따른 메모리 카드는, 제1 방향 및 제1 방향과 수직하는 제2 방향으로 각각 대향하는 2쌍의 가장자리들을 갖는 기판, 기판의 삽입측 가장자리에 인접하여 배열되고 제1 전원 단자를 포함하는 제1 열 단자들, 및 제1 열 단자들보다 삽입측 가장자리로부터 이격되어 배열되고 제2 전원 단자를 포함하는 제2 열 단자들을 포함하고, 제1 및 제2 열 단자들을 구성하는 단자들은 노출된 표면의 적어도 일부에 리세스 영역을 가지는 단자를 적어도 하나 포함한다.

Wiring board constructions and methods of making same

A wiring board construction includes at least one microvia disposed in a base substrate and includes a deep imprinted cup shaped in the top surface thereof. A conductor material is disposed within the recess, and has a portion disposed at the bottom thereof. A conductor disposed at a bottom surface of the substrate opposite to the conductor material bottom portion helps to complete an electrically conductor path through the substrate to help complete an electrically conductive path through the substrate.

Method for manufacturing multilayer wiring substrate

　A method for manufacturing a multilayer wiring substrate having: a step (1) for providing, using a conformal method or direct laser method, an opening for a via hole extending from a metallic foil for forming an upper layer wiring line to an inner layer wiring line, a protruding portion of the metallic foil for forming the upper layer wiring line formed in the aperture portion of the opening for a via hole, and a lower space formed between the protruding portion of the metallic foil and the inner wall of the opening for a via hole; and a step (2) for filling the opening for a via hole by forming an electrolytic filler plating layer in the opening for a via hole and on the metallic foil for the upper layer wiring line. The filling of the opening for a via hole by forming the electrolytic filler plating layer during step (2) is performed by first reducing the current density of electrolytic filler plating during electrolytic filler plating, and then increasing the current density.

Base Substrate Which Prevents Burrs Generated During the Cutting Process and Method for Manufacturing the Same

本发明涉及底部基板及其制造方法，具体地，涉及光学器件芯片安装在其上的底部基板，并且防止在切割过程中产生毛边的所述底部基板包括：相对于底部基板在一个方向上堆叠的多个导电层；至少一个绝缘层，其与所述导电层交替地堆叠并且电气隔离所述导电层；及通孔，在根据芯片基板的预定区域切割所述底部基板期间，该通孔在切割表面和所述绝缘层相交的接触区域处穿透覆盖所述绝缘层的所述底部基板。根据本发明，消除了由于毛边越过绝缘层及类似物而出现的电气短路，这是因为，通过相对于光学器件的切割表面形成了覆盖绝缘层的预定通孔，使得在光学器件从底部基板分离的过程中，即，在锯切或划片过程中，不会产生毛边。

Multi-cavity wiring board and method for manufacturing same

분할시나 당해 분할 전에 있어서 분할홈 부근에서부터의 파손이나 결손이나 균열이 발생하기 어렵기 때문에 높은 신뢰성을 가지는 다수개 취득 배선기판 및 그 제조방법을 제공한다. 복수의 세라믹층(s1,s2)을 적층하여 이루어지고, 표면(2) 및 이면(3)을 가지고 있고, 평면측에서 보았을 때 직사각형을 이루고 또한 캐비티(5)를 가지는 복수의 배선기판부분(4)을 종횡으로 배열한 제품영역(4a)과, 상기 제품영역(4a)의 주위를 따라서 위치하는 테두리부(6)와, 배선기판부분(4,4) 간의 경계 및 배선기판부분(4)과 테두리부(6)의 경계를 따라서 표면(2) 및 이면(3) 중 적어도 어느 일측에 형성한 분할홈(8,9)을 구비하는 다수개 취득 배선기판(1)으로서, 분할홈(8,9)은, 길이방향과 직교하는 단면에 있어서, 상기 분할홈(8,9)의 최심부(8b)가 원호형이고 또한 상기 최심부(8b)와 홈입구(8c)의 사이에 중간부(8a)를 가지고 있고, 최심부(8b)의 폭(w2)은 홈입구(8c)의 폭(w3)보다도 크고, 중간부(8a)의 폭(w1)은 홈입구(8c)의 폭(w3)과 같거나 이것보다도 작은 다수개 취득 배선기판(1). Provided is a multiple number of acquired wiring boards and a method of manufacturing the same that have high reliability since breakage, defects and cracks from the vicinity of the dividing grooves are hardly generated at the time of division or prior to the division. A plurality of wiring board portions 4 having a front surface 2 and a rear surface 3 laminated with a plurality of ceramic layers s1 and s2 and having a rectangular shape as viewed from the plane side and having a cavity 5, A border portion 6 positioned along the periphery of the product region 4a and a boundary between the wiring substrate portions 4 and 4 and a wiring board portion 4 (8, 9) formed on at least one of the front surface (2) and the back surface (3) along the border of the rim portion (6) 9 are formed such that the deepest portion 8b of the dividing grooves 8 and 9 is arcuate and the intermediate portion 8b is formed between the deepest portion 8b and the groove inlet 8c The width w2 of the deepest portion 8b is larger than the width w3 of the groove inlet 8c and the width w1 of the intermediate portion 8a is greater than the width w3 of the groove inlet 8c ) Or a plurality of smaller than this (1).

Multilayer wiring board, base for multilayer wiring board, printed wiring board and its manufacturing method

A multilayer wiring board assembly component comprises: an insulating substrate component (the insulating resin layer 111 ); a conductive layer 112 formed on one surface of said insulating substrate component 111 in the form of an electrode pattern; an adhesive layer 113 formed on the other surface of said insulating substrate component 111 ; and a conductive resin composition 115 with which is filled a through hole passing through said insulating substrate component 111 , said adhesive layer and said conductive layer in order to make interlayer interconnection. The bore diameter of the conductive layer portion 114 b of the through hole 114 is smaller than the bore diameter of the insulating resin layer portion and the adhesive layer portion 114 a to establish electrical connection between the conductive resin composition 115 and the conductive layer 112 by the rare surface 112 a of the conductive layer 112.

Method for producing a doublesided wiring board

The method for producing a printed wiring board comprising the steps of preparing a conductive substrate, forming an insulating layer on one surface of the said substrate, forming at least one via hole in the insulating layer, thermally curing the insulating layer, and reducing at least one oxidized layer formed on the other conductive surface of the substrate during the curing operation. Alternatively, the thermal cure may be accomplished in an atmosphere (e.g., reducing gas, inactive gas, or mixtures thereof) not conducive to oxide formation on metallized circuit surfaces.

Printed wiring board and method of manufacturing the same

A method of manufacturing a printed wiring board (210) comprising at least two insulating layers (211,212,213) made of a synthetic resin, an innerlayer conductor circuit (221-225) arranged between the insulating layers, and a plurality of blind via- holes (3A-3E) formed from an outermost surface toward the innerlayer conductor circuit (221-225) and having different depths by successively irradiating a laser beam every a portion forming the blind via-hole (3A-3E), characterized in that a shallowest blind via-hole (3A-3E) is formed as a standard hole by using a standard laser beam (242) having an energy strength required for the formation of the standard hole, and the standard laser beam (242) is irradiated plural times in the formation of the blind via-holes having deeper depths (3B,3D,3E).

Bump process

Multi-piece wiring substrate and method for manufacturing the same

Multilayer printed wiring board

一种多层印刷电路板，是交替层叠绝缘层和导体层，并将导体层通过设置在绝缘层上的导通孔相互电连接而成，该导通孔形成为在至少其中一部分中具有朝向与绝缘层的厚度方向大致垂直的方向鼓出的鼓出部，能抑制落下时的冲击力等的外部应力，绝缘基板不易翘起，能防止导体电路断裂或断线等，能减少安装基板的可靠性下降和耐落下性下降。

Printed wiring board and method for manufacturing printed wiring board

A printed wiring board includes an insulating substrate having a penetrating hole formed through the substrate, a first conductive pattern formed on first surface of the substrate, a second conductive pattern formed on second surface of the substrate on the opposite side of the first surface, and a through-hole conductor formed in the penetrating hole in the substrate such that the conductor is connecting the first conductive pattern on the first surface of the substrate and the second conductive pattern on the second surface of the substrate. The penetrating hole has a first opening portion opening on the first surface of the substrate, a second opening portion opening on the second surface of the substrate and a third opening portion connecting the first and second opening portions, and the third opening portion has the maximum diameter which is greater than the minimum diameters of the first and second opening portions.

Capacitive micromachined ultrasonic transducer (cmut) with through-substrate via (tsv) substrate plug

A capacitive micromachined ultrasonic transducer (CMUT) device 100 includes at least one CMUT cell 100a including a first substrate 101 of a single crystal material having a top side including a patterned dielectric layer thereon including a thick 106 and a thin 107 dielectric region, and a through- substrate via (TSV) 111 extending a full thickness of the first substrate. The TSV is formed of the single crystal material, is electrically isolated by isolation regions 131 in the single crystal material, and is positioned under a top side contact area 102a of the first substrate. A membrane layer 120b is bonded to the thick dielectric region and over the thin dielectric region to provide a movable membrane over a microelectromechanical system (MEMS) cavity 114. A metal layer 161 is over the top side substrate contact area and over the movable membrane including coupling of the top side substrate contact area to the movable membrane.

Wiring substrate

A wiring substrate includes: an insulating substrate comprising a corner constituted by two adjacent surfaces; wiring located continuously across the corner; wherein on at least one of the two adjacent surfaces, a part of the wiring disposed at an edge located at the corner has a thickness larger than a part of the wiring disposed away from the edge.

Capacitive micromachined ultrasonic transducer (cmut) with through-substrate via (tsv) substrate plug

Method of manufacturing a printed wiring board having a previously formed opening hole in an innerlayer conductor circuit

A method of producing a printed wiring board comprising innerlayer conductor circuits among insulating layers and blind via-holes formed by irradiating laser beams from the outermost surface of the insulating layer toward the innerlayer conductor circuit. A central portion of the innerlayer conductor circuit contains a previously formed opening hole located at the bottom of the blind via-hole. Thereafter, a metal plated film is formed on surfaces of the innerlayer conductor circuits and the blind via-holes.

Multilayer wiring board, base for multilayer wiring board, printed wiring board and its manufacturing method

A multilayer wiring board assembly component comprises: an insulating substrate component (the insulating resin layer 111 ); a conductive layer 112 formed on one surface of said insulating substrate component 111 in the form of an electrode pattern; an adhesive layer 113 formed on the other surface of said insulating substrate component 111 ; and a conductive resin composition 115 with which is filled a through hole passing through said insulating substrate component 111 , said adhesive layer and said conductive layer in order to make interlayer interconnection. The bore diameter of the conductive layer portion 114 b of the through hole 114 is smaller than the bore diameter of the insulating resin layer portion and the adhesive layer portion 114 a to establish electrical connection between the conductive resin composition 115 and the conductive layer 112 by the rare surface 112 a of the conductive layer 112.

Cost-reducing and process-simplifying wiring board and manufacturing method thereof

Multi-cavity wiring board and method for manufacturing same

提供多图案化布线基板及其制造方法，在分割时或在分割之前，难以从分割槽附近发生碎裂、裂纹或断裂并且具有高可靠性。多图案化布线基板（1）通过层叠多层陶瓷层（s1）、（s2）形成并且具有正面（2）和背面（3）。多图案化布线基板（1）包括：产品区域（4a），其中以矩阵形式排列在平面图中具有矩形形状并且包括空腔（5）的多个布线基板部分（4）；沿着产品区域（4a）的外周定位的边缘部分（6）；以及沿着布线基板部分（4）和（4）之间的分界及布线基板部分（4）和边缘部分（6）之间的分界在正面（2）和背面（3）中的至少一个面形成的分割槽（8）和（9）。在与延伸方向正交的截面中，分割槽（8）和（9）的最深部分（8b）具有圆弧形状，且各分割槽（8）和（9）均包括位于最深部分（8b）和槽入口（8c）之间的中间部分（8a）。最深部分（8b）的宽度（w2）大于槽入口（8c）的宽度（w3），并且中间部分（8a）的宽度（w1）等于或小于槽入口（8c）的宽度（w3）。

Multi-piece wiring substrate and method for manufacturing the same

Chip substrate for preventing burr generating and method for manufacturing the same

본 발명은 칩원판 및 이를 제조 방법에 관한 것으로, 보다 상세하게는 광소자 칩이 실장되는 칩원판에 관한 것으로, 절단에 따른 버를 방지하는 칩원판은 칩원판에 대하여 일 방향으로 적층된 복수의 전도층; 상기 전도층과 교호로 적층되어 상기 전도층을 전기적으로 분리시키는 적어도 하나의 절연층; 및 미리 결정된 칩기판 영역에 따른 상기 칩원판의 절단시 절단면과 상기 절연층이 접하는 영역에서, 상기 절연층을 포함하여 상기 칩원판을 관통하는 관통공을 포함한다. 본 발명에 따르면, 광디바이스의 절단면에 대하여 절연층을 포함하는 소정의 관통구를 형성함으로써, 칩원판에서 광디바이스의 분리, 즉 소잉(sawing) 또는 다이싱(dicing) 과정에서 버를 발생시키지 않아 발생된 버가 절연층을 타고 넘어가는 등의 상황에 의해 발생되는 전기적인 쇼트를 방지할 수 있다.

Method of manufacturing multilayer wiring board

【課題】絶縁層厚と同程度の径を有するビアホール穴に対しても、電解フィルドめっき層のめっきボイドを抑制可能な多層配線基板の製造方法を提供する。 【解決手段】コンフォーマル工法又はダイレクトレーザ工法を用いて、上層配線用の金属箔から内層配線に到るビアホール用穴と、このビアホール用穴の開口部に形成される上層配線用の金属箔の飛び出しと、この金属箔の飛び出しと前記ビアホール用穴の内壁との間に形成される下方空間と、を設ける工程（１）と、前記ビアホール用穴内及び上層配線用の金属箔上に電解フィルドめっき層を形成することによって前記ビアホール用穴を穴埋めする工程（２）と、を有し、前記工程（２）における、電解フィルドめっき層の形成によるビアホール用穴の穴埋めが、電解フィルドめっきの電流密度を電解フィルドめっきの途中で一旦低下させ、再び増加させて行われる多層配線基板の製造方法。 【選択図】図１

包含用於高速且高密度之電連接器的連接器佔位面積之印刷電路板和互連系統以及其製造方法

一種印刷電路板包括：複數個層，其包括由介電層所分開的導電層；及，至少一個通孔，其裝配以用於焊接到一表面安裝連接器的一連接器引線，該至少一個通孔包括從印刷電路板的一上表面延伸通過該複數個層的一者或多者之一導電元件，該導電元件在其一表面中具有一凹部。該凹部裝配以容納該表面安裝連接器的連接器引線的一尖端部分。該印刷電路板可具有其包括訊號通孔與接地通孔之通孔型樣。

布线基板

在布线基板，配置遍及包含绝缘基板的相邻的两个面的角部而连续的布线。配置在位于角部的缘部的部位的布线的厚度比远离缘部的部位的布线的厚度大。布线的厚度从远离缘部的部位向配置在缘部的部位递增。相对于侧端面上，在搭载安装电子元件的主面上，布线的厚度大，此外梯度平缓。

部件承载件及制造部件承载件的方法

提供了一种制造部件承载件(130)的方法及一种部件承载件(130)。该方法包括：在电绝缘层结构(102)的顶部上提供导电层结构(100)；通过第一激光束(106)在导电层结构(100)中形成窗口(104)并移除电绝缘层结构(102)在窗口(104)下方的材料；以及随后通过第二激光束(108)移除电绝缘层结构(102)在窗口(104)下方的另外的材料，该第二激光束的大小(D)小于窗口(104)的大小(L)。

Elektronisch apparaat, in het bijzonder een elektronisch apparaat voor het uitstralen van magnetische golven

Elektronisch apparaat, in het bijzonder een elektronisch apparaat voor het uitstralen van magnetische golven 5 Een elektronisch apparaat heeft een behuizing met een voorwand 5 voorzien van ten minste een te belichten gedeelte 7. In de behuizing 3 is een printplaat 11 aanwezig die is voorzien van een naar de voorwand 5 toegekeerde voorzijde Ma en een van de voorwand 5 afgekeerde achterzijde 11b. De printplaat 11 strekt zich achter het te 10 belichten gedeelte 7 uit. Op de printplaat 11 zijn lichtuitstralende diodes 14 aanwezig voor het belichten van het gedeelte 7. Ter plaatse van dit gedeelte 7 zijn een doorgaande gaten 13 in de printplaat 11 aanwezig en de lichtuitstralende diodes 14 zijn aan de achterzijde 11b van de printplaat 11 ter plaatse van de gaten 13 aanwezig. Hierdoor is er een relatief grote afstand tussen de diode en het te verlichten gedeelte 7 waardoor een 15 groter deel van de voorwand van achteren verlicht kan worden.

Printed circuit board

A printed circuit board includes a substrate; and a hole passing through first and second surfaces of the substrate. The hole includes an area in which a width of the hole formed in an inner side of the substrate is formed larger than that of an opening formed on the first surface and/or the second surface.

Circuit module and method for manufacturing the same

A circuit module includes a substrate on which a first electrode and a second electrode are provided, a first electronic component, and a first resin layer. The first electrode includes a first electrode base body and a first plating film. The second electrode and the first electronic component are covered with the first resin layer. The second electrode includes a second electrode base body, a metal column, whose one end is directly connected to the second electrode base body and another end is positioned in an inner side relative to an outer surface of the first resin layer, a second plating film with a cylindrical shape covering a side surface of a connection body of the second electrode base body and the metal column, and a covering portion connected to the other end of the metal column.

Wiring board and method of forming hole thereof

A wiring board includes a photosensitive insulating layer and a first wiring layer. The photosensitive insulating layer has a hole, a first surface and a second surface opposite to each other. The hole has a first end opening formed in the first surface, a second end opening formed in the second surface, an axis, and a sidewall surrounding the axis. Part of the sidewall extends toward the axis to form at least one annular flange. The first wiring layer is disposed on the first surface and includes a first pad, in which the hole exposes the first pad. There is at least one recessed cavity between the annular flange and the first pad. The minimum width of the annular flange is smaller than the maximum width of the recessed cavity.

Manufacturing holes in component carrier material

A method includes providing an electrically conductive layer structure on top of an electrically insulating layer structure, forming a window in the electrically conductive layer structure and removing material of the electrically insulating layer structure below the window by a first laser beam, and subsequently removing further material of the electrically insulating layer structure below the window by a second laser beam having a smaller size than a size of the window.

인쇄배선기판 및 그의 제조방법

본 발명에 따르면, 주석 입자(61)들과 은 입자(62)들을 포함하는 도전성 페이스트는 도체 패턴(22) 사이에 개재되는 열가소성 수지 필름(23)에 형성된 대략 원통형 비아 홀내에 충전되고, 양측에서 고온 가압된다. 상기 도전성 페이스트(50)에 포함된 금속 입자는 일체화된 도전성 조성물(51)을 형성하도록 소결되며, 상기 도전성 페이스트(50)의 체적은 감소된다. 이와 동시에, 상기 비아 홀(23) 주위의 수지 필름(23)은 비아 홀(24)로 돌출한다. 따라서, 상기 도전성 조성물(51)의 측벽 단면 형태는 아치 형태로 제공되고, 상기 도체 패턴(22)과 접촉하는 도전성 조성물(51)의 접속부와 인접하는 측벽은 경사지게 형성된다. 따라서, 기판의 변형으로 인한 응력 집중을 방지할 수 있다.

Leiterplattenkonstruktionen und deren herstellungsverfahren

用于制造印刷电路板的方法

公开了一种用于制造印刷电路板的方法。在该方法中，在具有至少三层的基板中形成狭槽，该狭槽延伸穿过所述层中的至少两个。该狭槽具有长度和宽度，该长度大于该宽度。该基板围绕该狭槽的侧壁涂覆有导电层。随后，导电层被分隔成沿着基板的侧壁电绝缘的至少两段。

Gedruckte leiterplatte und verfahren zu deren herstellung

多層基板用コネクタ

【課題】平板状ケーブルを多層基板の中間層に接続するものでありながら、多層基板の寸法精度や強度のバラツキによる影響を小さくしたり、又は／或いは多層基板２の変形を防止し、接触の安定性を向上させる。 【解決手段】多層基板２の板厚面に形成された挿入口２ａ内に配置される基板側接続部１と、平板状ケーブル３の先端部に設けられ、挿入口２ａに対する挿入により多層基板２の中間層で基板側接続部１と電気的に接続されるケーブル側接続部１０１と、を備える多層基板用コネクタであって、基板側接続部１が柱状端子６１、ケーブル側接続部１０１が平板状端子１５１、１６１を備え、柱状端子６１は、多層基板２の中間層から板厚方向に突出形成され、平板状端子１５１、１６１は、挿入口２ａに対するケーブル側接続部１０１の挿入に応じて、柱状端子６１の側面部に挿入口２ａの幅方向から弾性的に接触する弾性接触部１５５、１６５を備える。 【選択図】図１

プリント配線板

【課題】 ビア導体とビア導体底面側の導体回路との接続信頼性を高めたプリント配線板を提供する。 【解決手段】 スルーホール導体３６内の樹脂充填材３８は、心材を備えるコア基板３０よりも熱膨張係数が大きく、蓋めっき層（スルーホールランド）４２上のビア導体６２は、ヒートサイクルで大きな引き離し力が加わる。ビア導体６２は、表面側から底面側に向かって広がる逆テーパーが付いており、底面部６２Ｄの面積が広く成っている。このため、ビア導体６２の底面部６２Ｄと蓋めっき層４２との接続信頼性が改善され、プリント配線板の信頼性を高めることができる。 【選択図】 図５

인쇄배선기판 및 그의 제조방법

본 발명에 따르면, 주석 입자(61)들과 은 입자(62)들을 포함하는 도전성 페이스트는 도체 패턴(22) 사이에 개재되는 열가소성 수지 필름(23)에 형성된 대략 원통형 비아 홀내에 충전되고, 양측에서 고온 가압된다. 상기 도전성 페이스트(50)에 포함된 금속 입자는 일체화된 도전성 조성물(51)을 형성하도록 소결되며, 상기 도전성 페이스트(50)의 체적은 감소된다. 이와 동시에, 상기 비아 홀(23) 주위의 수지 필름(23)은 비아 홀(24)로 돌출한다. 따라서, 상기 도전성 조성물(51)의 측벽 단면 형태는 아치 형태로 제공되고, 상기 도체 패턴(22)과 접촉하는 도전성 조성물(51)의 접속부와 인접하는 측벽은 경사지게 형성된다. 따라서, 기판의 변형으로 인한 응력 집중을 방지할 수 있다.

电子装置及其制造方法

本发明公开一种电子装置及其制造方法，其中该电子装置包括一电子元件、以及一保护基板。保护基板包括一凹陷部、以及一平坦部。凹陷部具有一凹陷面以及相对于凹陷面的一凸出面。平坦部连接于凹陷部。电子元件重叠于凹陷部，并且设置于凸出面下。

Electronic device and manufacturing method thereof

An electronic device is provided, including an electronic element, and a protective substrate. The protective substrate includes a concave portion, and a flat portion. The concave portion has a concave surface and a convex surface that is opposite to the concave surface. The flat portion is connected to the concave portion. The electronic element overlaps the concave portion and is arranged under the convex surface.

인쇄회로기판

본 발명은 인쇄회로기판에 관한 것으로, 기판; 및 상기 기판을 관통하며, 상기 기판의 내측에 형성되는 폭은 상기 기판의 일면 또는 타면에 형성되는 폭보다 크게 형성되는 홀(hole);을 포함한다.

プリント基板およびその製造方法

(57)【要約】 【課題】 層間接続の信頼性低下を防止できるプリント 基板およびプリント基板の製造方法を提供すること。 【解決手段】 （ａ）に示すように、ビアホール２４内 に錫粒子６１と銀粒子６２とを含む導電ペースト５０を 充填した銅パターン２２を有する絶縁基材２３を適宜積 層し、両面から加熱プレスする。これにより、（ｂ）に 示すように、錫粒子６１は融解し銀粒子６２と合金化す るとともに焼結して一体化した導電性組成物５１とな る。また、導電性組成物５１中の錫成分と銅パターン２ ２とは相互に固相拡散して固相拡散層５２を形成し、複 数の導体パターン２２（下方の導体パターンは図示せ ず）の層間を、接触導通によらない信頼性の高い接合に より電気的接続を行なうことができる。

Capacitive micromachined ultrasonic transducer (cmut) with through-substrate via (tsv) substrate plug

Multilayer Cores, Variable Width Vias, and Offset Vias

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly, for implementing a semiconductor package or a chip package including a core or a multilayer core having one or more variable width vias or one or more offset vias. In various embodiments, an apparatus includes a substrate. The substrate includes a core. The core may include one or more vias extending through the core. At least one via of the one or more vias includes a cross-section that varies along a length of the at least one via as the via extends through the core. The cross-section of the via may vary based on at least one of varying a width of the at least one via or offsetting a first portion of the at least one via from a second portion of the at least one via.

Printed circuit board and package structure

A printed circuit board includes an insulating material with a bump pad buried in one surface, an adhesive layer stacked on the one surface of the insulating material, an insulating layer stacked on the adhesive layer, and a cavity passing through both of the adhesive layer and the insulating layer to expose the bump pad, wherein the cavity has a cross-sectional area decreasing in a direction toward the insulating material.

線路板及其孔洞形成方法

一種線路板包括光敏絕緣層與第一線路層。光敏絕緣層具有孔洞、彼此相對的第一表面與一第二表面。孔洞具有形成於第一表面的第一端口、形成於第二表面的第二端口、軸心以及環繞軸心的孔壁。部分孔壁朝向軸心延伸而形成至少一環形凸緣。第一線路層配置於第一表面，並包括第一接墊，其中孔洞暴露第一接墊。環形凸緣與第一接墊之間存有至少一凹陷空腔。環形凸緣的最小寬度小於上述凹陷空腔的最大寬度。

Printed wiring board and method for manufacturing printed wiring board

Conductive paste (50) containing tin particles (61) and silver particles (62) is packed in a substantially cylindrical via hole (24) formed in a thermoplastic resin film (23) that interposes between conductor patterns (22) and is hot-pressed from both sides. When the metal particles contained in the conductive paste (50) are sintered to form a unified conductive compound (51), the volume of the conductive paste (50) shrinks. Synchronously, the resin film (23) around the via-hole (24) protrudes into the via-hole (24). Therefore, the shape of the side wall on the cross-section of the conductive compound (51) provides an arch shape, and a side wall (51a) adjacent to a junction part (51b) of the conductive compound (51), which contacts the conductor pattern (22), is formed with an inclination. Therefore, it is possible to prevent the stress concentration due to deformation of the board.

Printed wiring board and method for manufacturing printed wiring board

多層配線基板の製造方法

　コンフォーマル工法又はダイレクトレーザ工法を用いて、上層配線用の金属箔から内層配線に到るビアホール用穴を設ける工程（１）と、前記ビアホール用穴内に、電解フィルドめっき層を形成することによって、ビアホールを形成する工程（２）とを有し、前記工程（２）における、電解フィルドめっき層の形成が、電解フィルドめっきの電流密度を電解フィルドめっきの途中で一旦低下させた後に再び増加させる電流密度変化を、前記電解フィルドめっき層が前記ビアホール用穴の開口部を塞ぐ前に、２回以上繰り返して行われる多層配線基板の製造方法。

电路板及其制作方法

本发明公开一种电路板及其制作方法，该电路板包含基材、电路层以及导电材料。基材具有相反的第一表面及第二表面，还具有贯穿第一表面与第二表面的穿孔。穿孔具有相连通的第一穿孔部以及第二穿孔部分别邻接第一表面与第二表面。第一穿孔部相对第二穿孔部内缩，进而在第一穿孔部与第二穿孔部之间形成断差部。电路层设置于第一表面，并覆盖第一穿孔部的开口。导电材料填满穿孔。

印刷线路板和制造印刷线路板的方法

通过用一种层间导电材料填充在线路板(100)的绝缘薄膜层中形成的通孔,制造加热并压制的印刷线路板(100)。把绝缘薄膜与导体图案(22)叠层,每个导体图案(22)封闭一个通孔(24)。在加热压制过程后,层间导电材料在通孔(24)中形成固体导电材料(51,52)。固体导电材料(51,52)包括两类导电材料。第一类导电材料(51)包括金属,第二类导电材料包含由所述金属与导体图案(22)的导体金属形成的合金。导体图案(22)可靠地电连接,而不仅仅依靠机械接触。

Printed wiring board and method of manufacturing a printed wiring board

Mounting substrate, manufacturing method for the same, and component mounting method

A mounting substrate includes a through-hole 13 formed in a substrate 10 , a first land part 21 , a second land part 31 , a first component attaching part 22 , a second component attaching part 32 , a conductive layer 14 , and a filling member 15 filled into a part of the through-hole 13 . A shortest distance allowable value L 0 from the center of the first land part 21 to a component 51 is determined on the basis of the volume V h of a part of the through-hole 15 positioned above a top surface of the filling member 15 on the side of the first land part 21 , the length L 1 of the component 51 to be mounted to the first component attaching part 22 , and the maximum allowable value of the inclination of the component 51 to be mounted to the first component attaching part 22 relative to the first surface 11 of the substrate 10.

Mehrschichtige Kerne, Durchkontaktierungen variabler Breite und versetzte Durchkontaktierungen

Neuartige Werkzeuge und Techniken werden für die Implementierung eines Halbleitergehäuses oder eines Chipgehäuses bereitgestellt, und insbesondere für die Implementierung eines Halbleitergehäuses oder eines Chipgehäuses, das einen Kern oder einen mehrschichtigen Kern mit einer oder mehreren Durchkontaktierungen variabler Breite oder einer oder mehreren versetzten Durchkontaktierungen aufweist. In verschiedenen Ausführungsformen weist eine Vorrichtung ein Substrat auf. Das Substrat weist einen Kern auf. Der Kern mag eine oder mehrere Durchkontaktierungen aufweisen, die sich durch den Kern erstrecken. Zumindest eine Durchkontaktierung der einen oder mehreren Durchkontaktierungen weist einen Querschnitt auf, der entlang der Länge der zumindest einen Durchkontaktierung variiert, indem sich die Durchkontaktierung durch den Kern erstreckt. Der Querschnitt der Durchkontaktierung mag basierend auf einem Variieren einer Breite der zumindest einen Durchkontaktierung und/oder einem Versetzen eines ersten Abschnitts der zumindest einen Durchkontaktierung von einem zweiten Abschnitt der zumindest einen Durchkontaktierung variieren.

多层核心、可变宽度通路及偏移通路

本公开涉及多层核心、可变宽度通路及偏移通路。提供用于实施半导体封装或芯片封装，且更具体地说，用于实施包含具有一或多个可变宽度通路或一或多个偏移通路的核心或多层核心的半导体封装或芯片封装的新颖工具及技术。在各种实施例中，一种设备包含衬底。所述衬底包含核心。所述核心可包含延伸穿过所述核心的一或多个通路。所述一或多个通路中的至少一个通路包含横截面，所述横截面在通路延伸穿过所述核心时沿着所述至少一个通路的长度变化。所述通路的所述横截面基于改变所述至少一个通路的宽度或使所述至少一个通路的第一部分从所述至少一个通路的第二部分偏移中的至少一者而变化。

Manufacturing Holes In Component Carrier Material

A method includes providing an electrically conductive layer structure on top of an electrically insulating layer structure, forming a window in the electrically conductive layer structure and removing material of the electrically insulating layer structure below the window by a first laser beam, and subsequently removing further material of the electrically insulating layer structure below the window by a second laser beam having a smaller size than a size of the window.

Electronic device module and method of manufacturing the same

The electronic device module and method thereof includes a board, an electronic device, a sealing part, and a connection conductor. The board includes external connection electrodes. The electronic device is mounted on the board. The sealing part is configured to seal the electronic device. The connection conductor is configured to penetrate through the sealing part and including one end bonded to the external connection electrodes of the board. One of the external connection electrodes includes a reinforcing via disposed in the board.

Backplane footprint for high speed, high density electrical connectors

A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers; and at least one via configured for solder attachment to a connector lead of a surface mount connector, the at least one via including a conductive element that extends from an upper surface of the printed circuit board through one or more of the plurality of layers, the conductive element having a recess in a surface thereof. The recess is configured to receive a tip portion of the connector lead of the surface mount connector. The printed circuit board may have via patterns including signal vias and ground vias.

Backplane footprint for high speed, high density electrical connectors

A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers; and at least one via configured for solder attachment to a connector lead of a surface mount connector, the at least one via including a conductive element that extends from an upper surface of the printed circuit board through one or more of the plurality of layers, the conductive element having a recess in a surface thereof. The recess is configured to receive a tip portion of the connector lead of the surface mount connector. The printed circuit board may have via patterns including signal vias and ground vias.

降低成本、简化工艺的布线板及其制造方法

本发明公开了一种布线板，包括第一绝缘层，在所述第一绝缘层的一个表面上形成的导体，和在所述第一绝缘层和所述导体的表面上形成的第二绝缘层。所述布线板上设有半球形或锥形的形成孔的部分，该部分穿过第二绝缘层进入所述导体中。

실장용 기판 및 그 제조 방법, 및, 부품 실장 방법

실장용 기판은, 기판(10)에 형성된 관통구멍(13), 제1의 랜드부(21), 제2의 랜드부(31), 제1의 부품 부착부(22), 제2의 부품 부착부(32), 도통층(14), 및, 관통구멍(13)의 일부분에 충전된 충전부재(15)를 구비하고 있고, 제1의 랜드부(21)측의 충전부재(15)의 정상면의 상방에 위치하는 관통구멍(15)의 부분의 체적(V h ), 제1의 부품 부착부(22)에 실장하여야 할 부품(51)의 길이(L 1 ), 제1의 부품 부착부(22)에 실장하여야 할 부품(51)의 기판(10)의 제1면(11)에 대한 경사의 최대 허용치에 의거하여 제1의 랜드부(21)의 중심부터 부품(51)까지의 최단거리 허용치(L 0 )가 결정된다.

実装用基板及びその製造方法、並びに、部品実装方法

実装用基板は、基板１０に形成された貫通孔１３、第１のランド部２１、第２のランド部３１、第１の部品取付部２２、第２の部品取付部３２、導通層１４、及び、貫通孔１３の一部分に充填された充填部材１５を備えており、第１のランド部２１側の充填部材１５の頂面の上方に位置する貫通孔１５の部分の体積Ｖ h 、第１の部品取付部２２に実装すべき部品５１の長さＬ 1 、第１の部品取付部２２に実装すべき部品５１の基板１０の第１面１１に対する傾きの最大許容値に基づき第１のランド部２１の中心から部品５１までの最短距離許容値Ｌ 0 が決定される。

Mounting substrate, manufacturing method for the same, and component mounting method

A mounting substrate includes a through-hole 13 formed in a substrate 10 , a first land part 21 , a second land part 31 , a first component attaching part 22 , a second component attaching part 32 , a conductive layer 14 , and a filling member 15 filled into a part of the through-hole 13 . A shortest distance allowable value L 0 from the center of the first land part 21 to a component 51 is determined on the basis of the volume V h of a part of the through-hole 15 positioned above a top surface of the filling member 15 on the side of the first land part 21 , the length L 1 of the component 51 to be mounted to the first component attaching part 22 , and the maximum allowable value of the inclination of the component 51 to be mounted to the first component attaching part 22 relative to the first surface 11 of the substrate 10.

配線基板、実装構造体及び配線基板の製造方法

本発明の一実施形態に係る配線基板２は、ビア導体１０が埋設されている絶縁層７を有している。ビア導体１０は、上部よりも下部が幅狭な第１導体部１０ａと、第１導体部１０ａの直下に形成され、第１導体部１０ａと接続されるとともに、第１導体部１０ａの上端幅よりも最大幅が幅広な第２導体部１０ｂと、を含んでいる。絶縁層７は、ビア導体１０と接する表面に複数の凹部Ｔ１ａ，Ｔ１ｂを有し、凹部Ｔ１ａ，Ｔ１ｂにビア導体の凸部Ｔ２ａ，Ｔ２ｂが配されている。

多層配線基板の製造方法

【課題】表面の金属箔上の電解めっき層が厚くならないようにしつつ、ビアホール用穴内のめっきボイドの発生を抑制し、かつ、電解フィルドめっきにより充填されない一般的なビアホールを、電解フィルドめっき設備によって形成可能とする多層配線基板の製造方法を提供することを目的とする。【解決手段】コンフォーマル工法又はダイレクトレーザ工法を用いて、上層配線用の金属箔から内層配線に到るビアホール用穴を設ける工程（１）と、前記ビアホール用穴内に、電解フィルドめっき層を形成することによって、ビアホールを形成する工程（２）とを有し、前記工程（２）における、電解フィルドめっき層の形成が、電解フィルドめっきの電流密度を電解フィルドめっきの途中で一旦低下させた後に再び増加させる電流密度変化を、前記電解フィルドめっき層が前記ビアホール用穴の開口部を塞ぐ前に、２回以上繰り返して行われる多層配線基板の製造方法。【選択図】図１

Wiring structure and method for manufacturing the same

A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are substantially arranged in a row and spaced apart from one another. The conductive through via extends through the dam portions.

多层线路基板、多层线路基板用基材、印刷线路基板及其制造方法

一种多层线路基板用基材，在绝缘性基材(绝缘树脂层(111))的一面上设有构成线路图形的导电层(112)，另一面上设有用于层间粘接的粘着层(113)，在贯通导电层、绝缘性基材和粘着层的贯通孔(114)中填充了用于实现层间导通的导电性树脂组成物(115)，其中，贯通孔的导电层部分(114b)的口径比绝缘性基材部分及粘着层部分(114a)的口径小，以确保在导电层的内侧面(112a)导电性树脂组成物和导电层的导通连接。

制造多层印刷电路板的方法

这样形成多层印刷电路板，即多个在其间分别插有绝缘层的导体层被叠置为一个整体，在绝缘层中设置以露出的导体层作为底部的非贯穿的孔，并在孔中设置用于导体层之间电连接的镀层，该孔被形成为在其轴向剖面图中，至少在孔的内周边到底面的延续区域处有半径在20-100μm的范围内的凹形曲面，由此因镀敷镀层产生的等电位面沿该延续区域也是弯曲的，因而用于镀层厚度均匀的电流密度均匀而不会在该延续区域处变薄。