Systems for assembling electronic devices with internal moisture-resistant coatings

A system for assembling electronic devices includes at least one coating element for applying a moisture-resistant coating to surfaces of a device under assembly, or an electronic device under assembly. As components and one or more moisture-resistant coatings are added to the electronic device under assembly to form a finished electronic device, at least one surface on which the coating resides and, thus, at least a portion of the coating itself, is located internally within the finished electronic device. Methods for assembling electronic devices that include internally confined moisture-resistant coatings are also disclosed.

THERMAL MANAGEMENT CIRCUIT MATERIALS, METHOD OF MANUFACTURE THEREOF, AND ARTICLES FORMED THEREFROM

A thermal management circuit material comprises a thermally conductive metallic core substrate having at least one through-hole via, non-metallic dielectric layers deposited on both sides of the metallic core substrate and on the containing walls of the through-hole via, electrically conductive metal layers on the non-metallic dielectric layers and an electrically conductive metal-containing core element filling the insulated through-hole via connecting at least a portion of each of the electrically conductive metal layers. Also disclosed are methods of making such circuit materials, comprising forming non-metallic dielectric layers by vapor deposition of a non-metallic material, for example by reacting an oxygen-containing precursor with an aluminum containing precursor and/or reacting a nitrogen-containing precursor with an aluminum or boron containing precursor on the surface of the metallic core substrate. Articles having a heat-generating electronic device such as an HBLED mounted in the circuit material are also disclosed. 1. A thermal management circuit material , capable of use for mounting an electronic device , comprising:a thermally conductive metallic core substrate;a first non-metallic dielectric layer on a first side of the metallic core substrate;a second non-metallic dielectric substrate layer on a second side of the thermally conductive metallic core substrate, which second side is opposite from the first side of the metallic core substrate;a first electrically conductive metal layer on the first oxide non-metallic dielectric layer;a second electrically conductive metal layer on the second non-metallic dielectric layer;at least one through-hole via filled with an electrically conductive metal forming a metal-containing core element that electrically connects at least a portion of each of the first and second electrically conductive metal layers, wherein the walls defining the through-hole via have an intermediate non-metallic dielectric layer ...

COATED ELECTRICAL ASSEMBLY

An electrical assembly which has a multi-layer conformal coating comprising three or more layers on at least one surface of the electrical assembly, wherein the lowest layer of the multi-layer conformal coating, which is in contact with the at least one surface of the electrical assembly, is obtainable by plasma deposition of a precursor mixture comprising (a) one or more organo-silicon compounds, (b) optionally O, NO, NO, H, NHand/or N, and (c) optionally He, Ar and/or Kr; the uppermost layer of the multi-layer conformal coating is obtainable by plasma deposition of a precursor mixture comprising (a) one or more organosilicon compounds, (b) optionally O, NO, NO, H, NHand/or N, and (c) optionally He, Ar and/or Kr; and the multi-layer coating comprises one or more layers which is obtainable by plasma deposition of a precursor mixture comprising (a) one or more hydrocarbon compounds of formula (A), (b) optionally NH, NO, N, NO, CH, CH, CHand/or CH, and (c) optionally He, Ar and/or Kr, Zrepresents C-Calkyl or C-Calkenyl; Zrepresents hydrogen, C-Calkyl or C-Calkenyl; Zrepresents hydrogen, C-Calkyl or C-Calkenyl; Zrepresents hydrogen, C-Calkyl or C-Calkenyl; Zrepresents hydrogen, C-Calkyl or C-Calkenyl; and Zrepresents hydrogen, C-Calkyl or C-Calkenyl. 2. The electrical assembly according to claim 1 , wherein the multi-layer conformal coating has three to thirteen layers.3. The electrical assembly according to or claim 1 , wherein the plasma deposition is plasma enhanced chemical vapour deposition (PECVD).4. The electrical assembly according to any one of the preceding claims claim 1 , wherein the plasma deposition occurs at a pressure of 0.001 to 10 mbar.5. The electrical assembly according to any one of the preceding claims claim 1 , wherein the lowest layer of the multi-layer conformal coating is organic.6. The electrical assembly according to any one of the preceding claims claim 1 , wherein the lowest layer of the multi-layer conformal coating is obtainable by ...

WATERPROOF STRUCTURE FOR IMPLANTED ELECTRONIC DEVICE

A waterproof structure for an implanted electronic device is capable of preventing the liquid or moist from entering and damaging the circuit board of the electronic device. The waterproof structure includes a shell, a first material layer, a second material layer, and a third material layer. The first material layer covers at least a part of the implanted electronic device. The second material layer covers the first material layer. The internal space of the shell is configured for accommodating the implanted electronic device. The shell is made of PEEK (polyether ether ketone). The third material layer is disposed between the second material layer and the shell. 1. A manufacturing method of a waterproof structure applied to a circuit board of an implanted electronic device , comprising steps of:forming a first material layer on the circuit board for covering at least a part of the circuit board;forming a second material layer for covering the first material layer;after forming the second material layer, disposing the circuit board, the first material layer and the second material layer in a shell, wherein the shell is made of PEEK (polyether ether ketone); andfilling a third material layer between the second material layer and the shell.2. The manufacturing method of claim 1 , wherein after filling the third material layer between the second material layer and the shell claim 1 , a porosity in the shell is less than 5%.3. The manufacturing method of claim 1 , wherein each of the first material layer and the third material layer is made of epoxy or silicone.4. The manufacturing method of claim 1 , wherein the second material layer comprises poly-para-xylene claim 1 , and the second material layer is formed by CVD (chemical vapor deposition).5. The manufacturing method of claim 1 , wherein the second material layer comprises a combination of aluminum oxide and titanium oxide claim 1 , and the second material layer is formed by ALD (atomic layer deposition). This ...

SCALABLE, PRINTABLE, PATTERNED SHEET OF HIGH MOBILITY GRAPHENE ON FLEXIBLE SUBSTRATES

The present invention provides methods for fabricating graphene workpieces. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention. 1. A method of forming a workpiece , the method comprising:growing pristine monolayer or few-layer continuous graphene on a catalytic film to form a graphene/catalytic film bilayer;disposing a first layer of material on top of the graphene surface in a predetermined pattern; andreleasing the graphene from the catalytic film so that the graphene is in the form of the patterned layer.2. The method of claim 1 , wherein the growing pristine monolayer continuous graphene on a catalytic film is performed by chemical vapor deposition at either atmospheric or low pressure.3. The method of claim 1 , wherein the disposing a first layer of material on top of the graphene surface is performed by printing on the surface of the graphene surface with a laser printer.4. The method of claim 1 , wherein the disposing a first layer of material on top of the graphene surface is performed by printing on the surface of the graphene surface with an inkjet printer with a polymer ink.5. The method of claim 1 , wherein the disposing a patterned first layer of material on top of the graphene surface is performed by screen printing claim 1 , flexography claim 1 , gravure claim 1 , offset lithography claim 1 , nanoimprint lithography claim 1 , or any combination thereof.6. The method of claim 1 , wherein the disposing a first layer of material on top of the graphene surface is performed by selective sintering of material in a 3D printer.7. The method of claim 6 , wherein the selective sintering comprises one or more of selective heat sintering and selective laser sintering.8. The method of claim 1 , wherein the disposing a first layer of polymer on top of the graphene surface is performed by selectively depositing a liquid binding material in a powder ...

Scalable, Printable, Patterned Sheet Of High Mobility Graphene On Flexible Substrates

The present invention provides methods for fabricating graphene workpieces. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention. 1. A patterned structure comprising:a patterned layer; anda graphene layer coupled to the patterned layer and separated from a substrate according to a pattern of the patterned layer.2. The patterned structure of claim 1 , wherein the patterned layer provides support for the graphene layer that is separated from the substrate.3. The patterned structure of claim 1 , wherein the separated graphene layer has the same pattern as the patterned layer.4. The patterned structure of claim 1 , wherein the patterned structure is a free-standing structure that is separated from the substrate.5. The patterned structure of claim 1 , wherein the patterned structure is configured to be coupled to a base substrate. This application is a continuation of U.S. patent application Ser. No. 16/752,421, filed Jan. 24, 2020; which is a continuation of U.S. patent application Ser. No. 16/214,601, filed Dec. 10, 2018; which is a continuation of U.S. patent application Ser. No. 15/850,046, filed Dec. 21, 2017 (now U.S. Pat. No. 10,165,679, issued Dec. 25, 2018); which is a continuation of U.S. patent application Ser. No. 15/305,167, filed Oct. 19, 2016 (now U.S. Pat. No. 9,930,777, issued Mar. 27, 2018); which is a National Stage Application of International Patent Application No. PCT/US2015/027193, filed Apr. 23, 2015; which claims the benefit of and priority to U.S. Patent Application No. 61/983,014, filed Apr. 23, 2014. The disclosures of the foregoing applications are incorporated herein by reference in their entireties for any and all purposes.This invention was made with government support under Contract No. DMR08-32802 awarded by the Nano/Bio Interface NSF NSEC. The government has certain rights in the invention.The disclosed invention is ...

PREPREG, PRINTED CIRCUIT BOARD INCLUDING PREPREG, AND METHOD OF FABRICATING THE SAME

A prepreg, a printed circuit board and a method of manufacturing the same are provided. A prepreg includes a core layer including nanofibers having a thickness in a range of 10 to 100 nm, a first insulating layer on a first surface of the core layer, and a second insulating layer on a second surface of the core layer. 1. A prepreg comprising:a core layer comprising nanofibers having a thickness in a range of 10 to 100 nm;a first insulating layer on a first surface of the core layer; anda second insulating layer on a second surface of the core layer.2. The prepreg of claim 1 , wherein the core layer comprises one selected from the group consisting of an aramid-based organic material claim 1 , nylon claim 1 , a silica-based inorganic material and a titania-based inorganic material.3. The prepreg of claim 1 , wherein a portion of a material forming the first insulating layer claim 1 , the second insulating layer or both is impregnated into the core layer.4. The prepreg of claim 1 , wherein the nanofiber is a hollow fiber.5. The prepreg of claim 4 , wherein a portion of a material forming the first insulating layer claim 4 , the second insulating layer or both is impregnated into the hollow of the hollow fiber.6. The prepreg of claim 1 , wherein a thickness of the first insulating layer is different from a thickness of the second insulating layer.7. A printed circuit board comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a prepreg of ; and'}a base layer disposed on at least one of the first insulating layer and the second insulating layer of the prepreg.8. The printed circuit board of claim 7 , wherein the base layer comprises a copper foil.9. A method for manufacturing a prepreg claim 7 , the method comprising:obtaining a first insulating layer disposed on a copper foil;forming a core layer comprising nanofibers on the first insulating layer; andforming a second insulating layer on the core layer.10. The method of claim 9 , wherein the nanofibers have a ...

COATED ELECTRICAL ASSEMBLY

An electrical assembly which has a multi-layer conformal coating on at least one surface of the electrical assembly, wherein each layer of the multi-layer coating is obtainable by plasma deposition of a precursor mixture comprising (a) one or more organosilicon compounds, (b) optionally O, NO, NO, H, NH, N, SiFand/or hexafluoropropylene (HFP), and (c) optionally He, Ar and/or Kr. The chemistry of the resulting plasma-deposited material chemistry can be described by the general formula: SiOHCFN. The properties of the conformal coating are tailored by tuning the values of x, y, z, a and b. 120.-. (canceled)21. An electrical assembly which has a multi-layer conformal coating on at least one surface of the electrical assembly , wherein the multi-layer conformal coating is obtained by:{'sub': 2', '2', '2, 'contacting the electrical assembly with a first precursor mixture comprising at least one organosilicon compound, under plasma deposition conditions suitable to form a first layer of the multi-layer conformal coating in contact with the electrical assembly, wherein the first layer is organic and hydrophobic, and wherein the first precursor mixture contains no, or substantially no, O, NO or NO; and'}{'sub': 2', '2', '2, 'contacting the electrical assembly with a second precursor mixture comprising at least one organosilicon compound, under plasma deposition conditions suitable to form a second layer of the multi-layer conformal coating, wherein the second layer is organic and hydrophobic, and wherein the second precursor mixture contains no, or substantially no, O, NO or NO.'}22. The electrical assembly according to claim 21 , wherein the multi-layer conformal coating has two to ten layers.23. The electrical assembly according to claim 21 , wherein the plasma deposition is plasma enhanced chemical vapour deposition (PECVD).24. The electrical assembly according to claim 21 , wherein the plasma deposition occurs at a pressure of 0.001 to 10 mbar.25. The electrical ...

ARRAYS OF LIGHT EMITTERS AND METHODS OF FORMING THEREOF

There are provided methods of growing arrays of light emitters on substrates. An example method includes adjusting a growth parameter of a given light emitter of an array of light emitters on a substrate to obtain an adjusted growth parameter. The adjusting may be based on a location of the given light emitter on the substrate. The adjusting may be to compensate for nonuniformity in a growth profile of the light emitters across the substrate. The nonuniformity may be associated with a corresponding nonuniformity among wavelengths of light generated by the light emitters. Adjusting the growth parameter may be to adjust the corresponding nonuniformity. The method may also include growing the given light emitter on the substrate based on the adjusted growth parameter. Arrays of corresponding light emitters are also described. 1. A method of growing an array of light emitters on a substrate , the method comprising:adjusting a growth parameter of a given light emitter of the array of the light emitters to obtain an adjusted growth parameter, the adjusting based on a location of the given light emitter on the substrate, the adjusting to compensate for nonuniformity in a growth profile of the light emitters across the substrate, the nonuniformity associated with a corresponding nonuniformity among wavelengths of light generated by the light emitters, the adjusting the growth parameter to adjust the corresponding nonuniformity; andgrowing the given light emitter on the substrate based on the adjusted growth parameter.2. The method of claim 1 , further comprising: obtaining the growth profile of the light emitters across the substrate; and', 'determining the nonuniformity in the growth profile across the substrate., 'before the adjusting the growth parameter3. The method of claim 1 , wherein the light emitters comprise solid-state light emitters each comprising a corresponding quantum well to emit light.4. The method of claim 3 , wherein one or more of the light emitters ...

Micro-fabricated group electroplating technique

Methods, and devices produced by the methods, for electroplating a multitude of micro-scale electrodes that are electrically isolated from each other on a cable or other device is described. A localized area of connections on another end of the cable is shorted together by depositing a metal sheet or other conductive material over the localized area. The metal sheet is connected to a terminal of a power supply, and the electrode end of the cable is immersed in an electrolyte solution for electrodeposition by electroplating. After the electrodes are electroplated, the metal sheet is removed from the cable in order to re-isolate the electrodes.

Scalable, Printable, Patterned Sheet Of High Mobility Graphene On Flexible Substrates

The present invention provides methods for fabricating graphene workpieces. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention. 1. A patterned structure comprising:a patterned layer; anda graphene layer coupled to the patterned layer and separated from a substrate according to a pattern of the patterned layer.2. The patterned structure of claim 1 , wherein the patterned layer provides support for the graphene layer that is separated from the substrate.3. The patterned structure of claim 1 , wherein the separated graphene layer has the same pattern as the patterned layer.4. The patterned structure of claim 1 , wherein the patterned structure is a free-standing structure that is separated from the substrate.5. The patterned structure of claim 1 , wherein the patterned structure is configured to be coupled to a base substrate. This application is a continuation application of U.S. patent application Ser. No. 15/850,046, filed Dec. 21, 2017, which is a continuation application of U.S. patent application Ser. No. 15/305,167, filed Oct. 19, 2016, now U.S. Pat. No. 9,930,777, issued Mar. 27, 2018 which is a National Stage Application of International Patent Application No. PCT/US2015/027193, filed Apr. 23, 2015, which claims benefit of U.S. Patent Application No. 61/983,014, filed Apr. 23, 2014, the disclosures of which are both incorporated herein by reference in their entirety.This invention was made with government support under Contract No. DMR08-32802 awarded by the Nano/Bio Interface NSF NSEC. The government has certain rights in the invention.The disclosed invention is directed toward the fields of graphene workpieces and of manufacturing methods thereof.The present application generally relates to methods and apparatus for transfer of films from one or more substrates to another, where the film to be transferred is patterned during the transfer ...

Waterproof structure for implanted electronic device

A waterproof structure for an implanted electronic device is capable of preventing the liquid or moist from entering and damaging the circuit board of the electronic device. The waterproof structure includes a shell, a first material layer, a second material layer, and a third material layer. The first material layer covers at least a part of the implanted electronic device. The second material layer covers the first material layer. The internal space of the shell is configured for accommodating the implanted electronic device. The shell is made of PEEK (polyether ether ketone). The third material layer is disposed between the second material layer and the shell.

ENCAPSULATION OF DOWNHOLE MICROELECTRONICS

A method of encapsulating an electronic assembly comprises disposing a plurality of electrically non-conductive particles on a substrate which carries one or more components of the electronic assembly; introducing a reactive parylene monomer in a vapor form into interstitial spaces among the plurality of the electrically non-conductive particles; and forming a parylene binder in the interstitial spaces of the electrically non-conductive particles from the reactive parylene monomer. 1. A method of encapsulating an electronic assembly , the method comprising:disposing a plurality of electrically non-conductive particles on a substrate which carries one or more components of the electronic assembly;introducing a reactive parylene monomer in a vapor form into interstitial spaces among the plurality of the electrically non-conductive particles; andforming a parylene binder in the interstitial spaces of the electrically non-conductive particles from the reactive parylene monomer.2. The method of claim 1 , wherein the electrically non-conductive particles have an electrical resistivity of greater than 10Ω*cm determined at 23° C. in accordance with ASTM D 1829.3. The method of claim 1 , wherein the electrically non-conductive particles comprises hexagonal boron nitride claim 1 , silicon nitride claim 1 , or a combination comprising at least one of the foregoing.4. The method of claim 1 , wherein the electronically non-conductive particles have an irregular shape.5. The method of claim 1 , wherein the electronically non-conductive particles comprise a first powder having first particles with a first regular shape and a first average diameter and a second powder having second particles with a second regular shape and a second average diameter claim 1 , wherein the first regular shape is different from the second regular shape claim 1 , the first average diameter is different from the second average diameter claim 1 , or a combination thereof.6. The method of claim 1 , wherein ...

Scalable, Printable, Patterned Sheet of High Mobility Graphene On Flexible Substrates

The present invention provides methods for fabricating graphene workpieces. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention.

Selective Repairing Process For Barrier Layer

A selectively repairing process for a barrier layer is provided. A repair layer is formed by chemical vapor deposition using an organosilicon compound as a precursor gas. The precursor gas adsorbed on a low-k dielectric layer exposed by defects in a barrier layer is transformed to a porous silicon oxide layer has a density more than the density of the low-k dielectric layer. 1. A method of repairing defects in a barrier layer , comprising:forming a damascene opening in a dielectric layer on a substrate, wherein a surface of the dielectric layer has free hydroxyl groups;forming a barrier layer on the dielectric layer to cover inner surfaces of the damascene opening; and{'sub': 3', '3, 'selectively depositing a repair layer on the dielectric layer exposed by defects in the barrier layer by chemical vapor deposition using an organosilicon as a precursor gas, wherein the organosilicon has a chemical formula of (CH)Si—X, and X is a leaving group.'}2. The method of claim 1 , wherein the dielectric layer has a dielectric constant smaller than a dielectric constant of silicon dioxide.3. The method of claim 2 , wherein the dielectric layer is fluorine-doped silicon dioxide claim 2 , carbon-doped silicon dioxide claim 2 , porous silicon dioxide claim 2 , porous carbon-doped silicon dioxide claim 2 , hydrogen silsesquioxane claim 2 , or methylsilsesquioxane.4. The method of claim 1 , wherein the barrier layer is made from a metal containing Co claim 1 , Ru claim 1 , Ta or any combinations thereof claim 1 , or a conductive ceramics claim 1 , which is tantalum nitride claim 1 , indium oxide claim 1 , copper silicide claim 1 , tungsten nitride or titanium nitride.5. The method of claim 1 , wherein the organosilicon is a silane claim 1 , silazane claim 1 , or a siloxane.6. The method of claim 5 , wherein the silane comprises (CH)Si—H.7. The method of claim 5 , wherein the silazane comprises (CH)Si—N(CH)or [(CH)Si]—NH.8. The method of claim 5 , wherein the siloxane comprises (CH)Si ...

Fusion bonded liquid crystal polymer electrical circuit structure

A method of making a fusion bonded circuit structure. A substrate is provided with a seed layer of a conductive material. A first resist layer is deposited on the seed layer. The first resist layer is processed to create first recesses corresponding to a desired first circuitry layer. The first recesses expose, portions of the seed layer of conductive material. The substrate is electroplated to create first conductive traces defined by the first recesses. The first resist layer is removed to reveal the first conductive traces. The substrate is etched to remove exposed portions of the seed layer adjacent the first conductive traces. A portion of the seed layer is interposed between the first conductive traces and the substrate. A first layer of LCP is fusion boned to the first major surface of the substrate to encapsulate the first conductive traces in an LCP material. The first LCP layer can be laser drilled to expose the conductive traces.

PLASTIC FILM/SHEET AS REPLACEMENT FOR TYPICAL CONFORMAL COATINGS

A system for protecting electronics includes a printed wiring assembly (PWA) having a surface with at least one electronic component. The system also includes a water resistant film configured to be used as a conformal coating on the PWA and further configured to be placed on the surface of the PWA and to shrink about the at least one electronic component. 1. A system for protecting electronics , comprising:a printed wiring assembly (PWA) having a surface with at least one electronic component; anda water resistant film separate from the PWA, being cut to a desired shape to contact the PWA at locations in which a conformal coating is desired and to avoid contacting the PWA at other locations, providing the conformal coating on the PWA, located on the surface of the PWA, and shrunk about the at least one electronic component and the PWA to couple the water resistant film to the at least one electronic component and the PWA.2. The system of wherein the film is capable of holding an electric charge to facilitate a static cling of the film to the PWA to resist movement of the film relative to the PWA prior to shrinking.3. The system of claim 1 , further comprising an adhesive positioned between the film and the PWA to resist movement of the film relative to the PWA prior to shrinking of the film.4. The system of claim 3 , wherein the adhesive includes at least one of acrylic or polyamide.5. The system of claim 1 , wherein the film is provided as multiple strips configured to be positioned adjacent to each other on the PWA prior to shrinking.6. The system of claim 1 , wherein the film is transparent or semi-transparent to facilitate viewing of the at least one electronic component in response to the film being coupled to the PWA.7. The system of claim 1 , wherein the film operates as an electrical insulator.8. The system of claim 1 , wherein the film is sufficiently flexible to surround and contact all exposed surfaces of the at least one electronic component in response ...

Coated Electrical Assembly

The present invention relates to an electrical assembly which has a conformal coating, wherein said conformal coating is obtainable by a method which comprises: (a) plasma polymerization of a compound of formula (I) and a fluorohydrocarbon, wherein the molar ratio of the compound of formula (I) to the fluorohydrocarbon is from 5:95 to 50:50, and deposition of the resulting polymer onto at least one surface of the electrical assembly: wherein: Rrepresents C-Calkyl or C-Calkenyl; Rrepresents hydrogen, C-Calkyl or C-Calkenyl; Rrepresents hydrogen, C-Calkyl or C-Calkenyl; Rrepresents hydrogen, C-Calkyl or C-Calkenyl; Rrepresents hydrogen, C-Calkyl or C-Calkenyl; and Rrepresents hydrogen, C-Calkyl or C-Calkenyl, and (b) plasma polymerization of a compound of formula (I) and deposition of the resulting polymer onto the polymer formed in step (a). 2. The method of claim 1 , further comprising:(c) plasma polymerization of a compound of formula (I) and a fluorohydrocarbon, wherein the molar ratio of the compound of formula (I) to the fluorohydrocarbon is from 5:95 to 50:50, and deposition of the resulting polymer onto the polymer formed in step (b), and(d) plasma polymerization of a compound of formula (I) and deposition of the resulting polymer onto the polymer formed in step (c).3. The method of claim 2 , further comprising:(e) plasma polymerization of a compound of formula (I) and a fluorohydrocarbon, wherein the molar ratio of the compound of formula (I) to the fluorohydrocarbon is from 5:95 to 50:50, and deposition of the resulting polymer onto the polymer formed in step (d), and(f) plasma polymerization of a compound of formula (I) and deposition of the resulting polymer onto the polymer formed in step (e).4. The method of claim 1 , further comprising plasma polymerization of a fluorohydrocarbon and deposition of the resulting polymer onto a previously deposited polymer to form an outer layer.5. The method of claim 1 , wherein at least one of the compounds of formula ( ...

METHOD FOR MANUFACTURING ELECTRONIC PRODUCTS, RELATED ARRANGEMENT AND PRODUCT

A method for manufacturing an electronic product, comprising providing a flexible, optionally optically substantially transparent or translucent, substrate film, printing a number of conductive traces of conductive ink on the substrate film, said traces defining a number of conductors and conductive contact areas for the contacts of at least one electronic surface-mountable component, disposing the at least one electronic surface-mountable component, such as an integrated circuit, on the substrate film so that the contacts meet the predefined contact areas when they are still wet to establish the electrical connection therebetween, and further securing, optionally overmoulding, the component. Related arrangement and electronic product are presented. 1. A method for manufacturing an electronic product , comprising:providing a flexible, optionally optically substantially transparent or translucent, substrate film,printing a number of conductive traces of conductive ink on the substrate film, said traces defining a number of conductors and conductive contact areas for the contacts of at least one electronic surface-mountable component,disposing the at least one electronic surface-mountable component, such as an integrated circuit, on the substrate film so that the contacts meet the predefined contact areas when they are still wet to establish the electrical connection therebetween, andfurther securing the physical connection between said at least one component and the substrate.2. The method of claim 1 , wherein the substrate film is 3d-shaped preferably through thermoforming.3. The method of claim 1 , wherein said at least one component is overmoulded claim 1 , optionally injection moulded claim 1 , so as to at least partly encapsulate it in the molded material claim 1 , preferably plastics claim 1 , to protect and further secure it.4. The method of claim 1 , wherein said at least one component is overmoulded claim 1 , optionally injection moulded claim 1 , so as to ...

CONDUCTIVE NANOSTRUCTURE-BASED FILMS WITH IMPROVED ESD PERFORMANCE

Optical stacks containing one or more patterned transparent conductor layers may be damaged by electrostatic discharges that occur during the optical stack manufacturing process. Such damage may result in non-conductive conductors within the patterned transparent conductor layer. An electrostatic discharge protected optical stack may include a substrate layer, a first anti-static layer having a sheet resistance of from about 10ohms per square (Ω/sq) to about 10Ω/sq, and a patterned transparent conductor layer. Methods of testing and assessing damage to patterned transparent conductors are provided. 1. An electrostatic discharge protected optical stack comprising:a substrate layer;{'sup': 6', '9, 'a first anti-static layer having a sheet resistance of from about 10ohms per square (Ω/sq) to about 10Ω/sq;'}a transparent conductor layer.2. The electrostatic discharge protected optical stack of wherein the first anti-static layer interposes between at least a portion of the substrate layer and at least a portion of the transparent conductor layer.3. The electrostatic discharge protected optical stack of claim 2 , further comprising:a nonconductive overcoat layer proximate at least a portion of the transparent conductor layer laterally opposite the first anti-static layer.4. The electrostatic discharge protected optical stack of claim 3 , further comprising a second anti-static layer disposed proximate at least a portion of the substrate layer laterally opposite the first anti-static layer.5. The electrostatic discharge protected optical stack of wherein the transparent conductor layer comprises:a printed patterned transparent conductor layer.6. The electrostatic discharge protected optical stack of wherein the transparent conductor layer comprises:a laser ablated patterned transparent conductor layer.7. The electrostatic discharge protected optical stack of wherein the transparent conductor layer comprises a transparent conductor layer that includes a plurality of silver ...

PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME

A wiring board includes a core substrate including an insulative substrate and a first inner conductive-circuit layer formed on first surface of the insulative substrate, an electronic component positioned in a penetrating hole formed in the insulative substrate and having a positive electrode terminal on first end portion and a negative electrode terminal on second end portion on the opposite side, a first interlayer insulative resin layer formed on first surface of the core such that the first insulative layer is positioned over the core and component in the penetrating hole, and an outer conductive-circuit layer formed on surface of the first insulative layer such that thicknesses of the first insulative layer between the outer conductive-circuit layer and the terminals are less than thickness of the first insulative layer between the first inner conductive-circuit layer and the outer conductive-circuit layer. 1. A wiring board , comprising:a core substrate comprising an insulative substrate and a first inner conductive-circuit layer formed on a first surface of the insulative substrate;an electronic component positioned in a penetrating hole formed in the insulative substrate of the core substrate and having a positive electrode terminal on a first end portion and a negative electrode terminal on a second end portion on an opposite side with respect to the first end portion;a first interlayer insulative resin layer formed on a first surface of the core substrate such that the first interlayer insulative resin layer is positioned over the core substrate and the electronic component in the penetrating hole; andan outer conductive-circuit layer formed on a surface of the first interlayer insulative resin layer such that thicknesses of the first interlayer insulative resin layer between the outer conductive-circuit layer and the positive electrode terminal and between the outer conductive-circuit layer and negative electrode terminal are less than a thickness of the ...

Physical contact layer for body-worn leadware using selective disposition

A printed electrical circuit and methods for additively printing electrical circuits. Patterned layers of conductive, insulating, semi-conductive materials, and other materials are print deposited on a flexible or rigid substrate to form electrical circuits. A buffering layer is selectively deposited to cover or encapsulate these materials to comprise a comfort layer that provides a soft and comfortable interface to the skin of a wearer. The comfort layer can be selectively deposited on the same press that the conductive, insulating, semi-conductive materials, and other materials are deposited. Further, the comfort layer is selectively deposited only where it is desired and exactly where it is desired.

Hybrid electronic sheets

In accordance with the present disclosure, a hybrid electronic sheet which exhibits superior electrical property and allows biomaterial functionalization and flexible device patterning may be provided by binding a graphitic material in colloidal state to a biomaterial capable of binding thereto specifically and nondestructively. Since the electronic sheet is an electronic sheet wherein a biomaterial and an electrical material (graphitic material) are hybridized, it exhibits good compatibility with biomaterials and can be further functionalized with, for example, an enzyme that selectively reacts with a biochemical substance. Accordingly, an electrical material and a chemical or biological material may be effectively nanostructurized and it can be realized as a multi-functional, high-performance electronic sheet.

Solder mask

A method for formation of a patterned solder mask ( 10 ) on a substrate is provided, in which method the mask is deposited by a process of chemical deposition in vapor phase. A method for manufacturing a printed circuit board and/or an electronic component comprising formation of said patterned solder mask is further provided.

Systems for assembling electronic devices with internal water-resistant coating

A system for assembling electronic devices includes at least one coating element for applying a moisture-resistant coating to surfaces of a device under assembly, or an electronic device under assembly. As components and one or more moisture-resistant coatings are added to the electronic device under assembly to form a finished electronic device, at least one surface on which the coating resides and, thus, at least a portion of the coating itself, is located internally within the finished electronic device. Methods for assembling electronic devices that include internally confined moisture-resistant coatings are also disclosed.

Oleophobic Coatings for Glass Structures in Electronic Devices

An electronic device includes electrical components in a housing. The components may include optical components such as a display. Protective structures may be used to protect the optical components. The protective structures may include one or more protective transparent layers such as layers of glass or crystalline material such as sapphire. The protective transparent layers may be coated with an oleophobic coating. To enhance coating durability, catalyst may be used to help bond the oleophobic coating. An adhesion promotion layer such as a silicon oxide layer may be deposited on the transparent protective layer. A catalyst layer such as a layer of sodium fluoride may be deposited on the adhesion promotion layer. The oleophobic material may be evaporated or otherwise deposited on the catalyst layer. Heat and moisture may help the oleophobic material form chemical bonds with the adhesion promotion layer, thereby forming a durable oleophobic coating.

Sensors, systems and methods for detecting analytes using same

Sensors, as well as systems and methods of using the same are provided. Aspects of the sensors include a piezoelectric base, a plurality of surface-associated compositions that are stably associated with the piezoelectric base, and a plurality of crosslinking compositions that are configured to crosslink one or more surface-associated compositions in the presence of an analyte. The sensors, systems and methods described herein find use in a variety of applications, including the detection of an analyte in a sample.

Hybrid electronic sheets

Provided is an electronic sheet including a graphitic material and a phage which displays a peptide having a binding ability to the graphitic material on its coat protein or a fragment thereof.

PROCESS FOR LAMINATING GRAPHENE-COATED PRINTED CIRCUIT BOARDS

Processes for laminating a graphene-coated printed circuit board (PCB) are disclosed. An example laminated PCB may include a lamination stack that may include an inner core, an adhesive layer, and at least one graphene-metal structure. Pressure and heat—which may be applied under vacuum or controlled gas atmosphere—may be applied to the lamination stack, after all materials have been placed. The graphene of the graphene-metal structure is designed to promote high frequency performance and heat management within the PCB. 1. A method of forming a lamination stack comprising:providing a core;applying an adhesive layer to a top surface of the core; andattaching a graphene-metal structure to a top surface of the core via the adhesive layer, wherein the graphene-metal structure comprises a metal layer and a graphene layer on at least one of a top surface of the metal layer or a bottom surface of the metal layer.2. The method according to claim 1 , further comprising applying a cool down period to the lamination stack claim 1 , wherein the cool down period comprises a steady decrease in temperature over a duration of the cool down period.3. The method according to claim 1 , further comprising heating the lamination stack from a base of the lamination stack.4. The method according to claim 1 , wherein the graphene-metal structure is a first graphene-metal structure claim 1 , the method further comprising attaching a second graphene-metal structure to a top surface of the first graphene-metal structure claim 1 , wherein the second graphene-metal structure comprises a second metal layer and a second graphene layer on at least one of a top surface of the second metal layer or a bottom surface of the second metal layer.5. The method according to claim 4 , further comprising defining one or more holes through the metal layer of the first graphene-metal structure claim 4 , the second metal layer of the second graphene-metal structure claim 4 , and intervening layers.6. The method ...

Printed circuit boards

A printed circuit board to which a localised solder connection is to be made, the surface of said printed circuit board having a continuous or non-continuous coating of a composition comprising a halo-hydrocarbon polymer at a thickness of from 1 nm to 10 μm.

Method for manufacturing printed circuit boards

A method including: attaching a plurality of conductive tracks to at least one surface of a substrate, depositing a coating comprising at least one halo-hydrocarbon polymer on the at least one surface of the substrate, and soldering through the coating.

Coated electrical assembly

FIELD: chemistry. SUBSTANCE: invention relates to a coated electrical assembly and methods of making a coated electrical assembly. Electric assembly has multilayer conformal coating on at least one surface of electrical assembly. Each layer of the multilayer coating can be obtained by plasma deposition of a precursor mixture containing (a) one or more organosilicon compounds, (b) optionally O 2 , N 2 O, NO 2 , H 2 , NH 3 , N 2 , SiF 4 and/or hexafluoropropylene (HFP), and (c) optionally - He, Ar and/or Kr. First and lowest layer of the multilayer conformal coating is organic and is in contact with the surface of the electrical assembly. EFFECT: invention enables to form coatings which would provide improved levels of protection from moisture. 19 cl, 7 dwg, 3 tbl РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2 717 842 C2 (51) МПК H05K 3/28 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (52) СПК H05K 3/28 (2020.01) (21)(22) Заявка: 2017144870, 09.06.2016 (24) Дата начала отсчета срока действия патента: Дата регистрации: 26.03.2020 R U 09.06.2016 (72) Автор(ы): АРЕСТА, Джанфранко (GB), ХЕННИГЭН, Гарет (GB), БРУКС, Эндрю Саймон Холл (GB), СИНГХ, Шайлендра Викрам (GB) (73) Патентообладатель(и): СЕМБЛАНТ ЛИМИТЕД (GB) 10.06.2015 GB 1510091.0 (43) Дата публикации заявки: 12.07.2019 Бюл. № 20 (45) Опубликовано: 26.03.2020 Бюл. № 9 (56) Список документов, цитированных в отчете о поиске: US 2004229051 A1, 18.11.2004. RU 2563978 C2, 27.09.2015. WO 03016589 A1, 27.02.2003. RU 2007115923 A, 10.11.2008. RU 2467046 C2, 20.11.2012. (85) Дата начала рассмотрения заявки PCT на национальной фазе: 10.01.2018 2 7 1 7 8 4 2 Приоритет(ы): (30) Конвенционный приоритет: GB 2016/051702 (09.06.2016) C 2 C 2 (86) Заявка PCT: (87) Публикация заявки PCT: R U 2 7 1 7 8 4 2 WO 2016/198870 (15.12.2016) Адрес для переписки: 197101, Санкт-Петербург, а/я 128, "АРСПАТЕНТ", С.В. Новоселовой (54) ИМЕЮЩИЙ ПОКРЫТИЕ ЭЛЕКТРИЧЕСКИЙ УЗЕЛ (57) Реферат: Изобретение ...

인쇄회로기판 및 그 제조방법

본 발명은 인쇄회로기판 및 그 제조방법에 관한 것이다. 본 발명에 따른 인쇄회로기판은 기판의 베이스를 이루는 베이스층; 베이스층의 상면에 형성되며, 회로 및 비아홀의 형성을 위한 절연층; 절연층의 상면에 형성되며, 도전성 물질의 적층 형성이 원활하게 이루어지도록 하기 위한 제1 씨드층; 제1 씨드층의 상면 및 상기 절연층 내에 형성되어 있는 비아홀의 내면에 걸쳐 형성되며, 도전성 물질의 적층 형성이 원활하게 이루어지도록 하기 위한 제2 씨드층; 및 제2 씨드층의 상면에 형성되며, 회로 구성 및 상부층과의 도통을 위한 도전층을 포함한다. 이와 같은 본 발명에 의하면, 구리(Cu)와는 다른 이종 금속을 제1 씨드층으로 사용하여 구리 씨드층과의 선택적 에칭을 수행함으로써, 회로 하단부의 언더컷을 최소화할 수 있다. 또한, 비아홀의 내부에는 제1 씨드층이 형성되지 않기 때문에, 비아 도통 저항의 상승을 억제할 수 있고, 절연층 표면의 조도의 형성 없이도 씨드층과의 높은 밀착력을 얻을 수 있다.

도전체, 그 제조 방법, 및 이를 포함하는 전자 소자

기판, 기판 위에 형성되고, 2 이상의 아일랜드형 그래핀을 포함하는 제1 도전층, 및 제1 도전층 위에 형성되고, 도전성 금속 나노와이어를 포함하는 제2 도전층을 포함하고, 아일랜드형 그래핀의 상부면과 하부면 중 적어도 하나는 P 타입 도펀트에 의해 P-도핑되어 있는 도전체와, 그 제조 방법, 및 도전체를 포함하는 전자 소자를 제공한다.

Hybrid electronic sheets

그래피틱 물질(graphitic material) 및 상기 그래피틱 물질에 대한 결합능을 갖는 펩티드가 파지의 외피 단백질 또는 그의 일부에 디스플레이된 파지를 포함하는 전자 시트를 제공한다. A graphitic material and an electronic sheet, wherein the peptide having binding ability to the graphitic substance comprises a phage displayed on the envelope protein of the phage or a part thereof.

Printed-circuit boards

FIELD: physics, computer engineering. SUBSTANCE: invention relates to articles having printed-circuit boards with a halohydrocarbon polymer coating. The result is achieved due to that the surface of the printed-circuit board, having a localised soldered connection, has a continuous or discontinuous coating from a composition which includes more than one fluorohydrocarbon polymer with thickness of 1 nm to 10 mcm. EFFECT: preventing oxidation of current-conducting tracks of the printed-circuit board workpiece and (or) other damages under the effect of the environment, for example, corrosion. 5 cl, 15 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2 563 978 C2 (51) МПК H05K 1/18 (2006.01) H05K 3/28 (2006.01) H05K 3/34 (2006.01) H05K 3/26 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ (21)(22) Заявка: ИЗОБРЕТЕНИЯ К ПАТЕНТУ 2009130670/07, 18.02.2008 (24) Дата начала отсчета срока действия патента: 18.02.2008 Приоритет(ы): (30) Конвенционный приоритет: (72) Автор(ы): ФЕРДИНАНДИ Фрэнк (GB), СМИТ Родни Эдвард (GB), ХАМФРИЗ Марк Робсон (GB) 19.02.2007 GB 0703172.7 (43) Дата публикации заявки: 10.04.2011 Бюл. № 10 R U (73) Патентообладатель(и): СЕМБЛАНТ ЛИМИТЕД (GB) (45) Опубликовано: 27.09.2015 Бюл. № 27 2 5 6 3 9 7 8 (56) Список документов, цитированных в отчете о поиске: WO 97/39610 A1, 23.10.1997. US 2006/ 0001700 A1, 05.01.2006. US 3931454 A, 06.01.1976. WO 01/14612A1, 01.03.2001. US 2006/0292354 A1, 28.12.2006. RU 2177934 C2, 10.01.2002. RU 2104263 C1, 10.02.1998 (85) Дата начала рассмотрения заявки PCT на национальной фазе: 21.09.2009 GB 2008/000552 (18.02.2008) C 2 C 2 (86) Заявка PCT: (87) Публикация заявки PCT: R U 2 5 6 3 9 7 8 WO 2008/102113 (28.08.2008) Адрес для переписки: 105215, Москва, а/я 26, Рыбиной Н.А. (54) ПЕЧАТНЫЕ ПЛАТЫ (57) Реферат: Изобретение относится к изделиям, включающим печатные платы с нанесенным на них галогенуглеводородным полимерным покрытием. Технический результат предотвращение окисления токопроводящих дорожек ...

Long-term packaging for the protection of implant electronics

The present invention provides a micropackaged device comprising: a substrate for securing a device; a corrosion barrier affixed to said substrate; optionally at least one feedthrough disposed in said substrate to permit at least one input and or at least one output line into said micropackaged device; and an encapsulation material layer configured to encapsulate the micropackaged device.

Double-sided circuit non-oxide ceramic substrate and method for producing same

本发明提供一种散热性优异且低成本的双面电路非氧化物系陶瓷基板及其制造方法。本发明的双面电路非氧化物系陶瓷基板(1)具备：具有通孔(11)的高导热性非氧化物系的陶瓷基板(10)；形成于上述通孔(11)的壁面(11a)的保持层(20)；以及由上述保持层(20)保持于上述通孔(11)的内部的、不含活性金属的导电性金属部(30S)。本发明的双面电路非氧化物系陶瓷基板(1)优选具备覆盖露出于上述陶瓷基板(10)的表背面的上述保持层(20)的端面(20a、20b)及上述导电性金属部(30S)的端面(30a、30b)的电极(薄膜电极(41、42))。

Printed circuit boards

本发明涉及一种其上将进行局部焊接的印刷电路板，所述印刷电路板的表面具有厚度为1nm至10μm的连续或不连续的组合物涂层，所述组合物包括卤代烃聚合物。

Method for forming copper wiring and storage mideum

[과제] 배리어막을 오목부에 비하여 얇고 또한 균일하게 형성할 수 있고 또한 배리어성이 높은 것으로 하여 Cu 배선의 저저항화를 실현할 수 있는 Cu 배선의 형성 방법을 제공하는 것. [해결 수단] 표면에 소정 패턴의 트렌치(203)가 형성된 층간 절연막(202)을 가지는 웨이퍼(W)에 대하여, 트렌치(203)를 매립하는 Cu 배선(208)을 형성하는 Cu 배선의 형성 방법으로서, 적어도 트렌치(203)의 표면에, 열ALD 또는 열CVD에 의한 TaAlN막으로 이루어지는 배리어막(204)을 형성하고, Cu막(206)을 형성해서 트렌치(203)내에 Cu막을 매립하고, CMP에 의해 전면을 연마하여 트렌치(203)내에 Cu 배선(208)을 형성하는 것을 포함한다. [PROBLEMS] To provide a method of forming a Cu wiring capable of realizing low resistance of a Cu wiring by making it possible to form a barrier film thinner and more uniformly than a concave portion and to have a high barrier property. A method of forming a Cu wiring for forming a Cu wiring 208 for filling a trench 203 with respect to a wafer W having an interlayer insulating film 202 having a predetermined pattern of trenches 203 formed on its surface A barrier film 204 made of a TaAlN film by thermal ALD or thermal CVD is formed on at least the surface of the trench 203 and a Cu film 206 is formed so that a Cu film is buried in the trench 203, To form a Cu wiring 208 in the trench 203. The Cu wiring 208 is formed by etching the entire surface of the trench 203 by polishing.

METHOD FOR MANUFACTURING CONNECTIONS CROSSING IN A SUBSTRATE AND SUBSTRATE EQUIPPED WITH SUCH CONNECTIONS

L'invention conceme les procédés de fabrication de connexions conductrices traversantes dans un substrat et les substrats équipés de telles connexions.Le procédé de fabrication de connexions conductrices traversantes entre la face avant (2) et la face arrière (3) d'un substrat (1) consiste :- à creuser dans le substrat (1), du côté de la face arrière (3), des cavités (5) ayant une profondeur et une section déterminées pour délimiter des plots (4) de section déterminée destinés à assurer la conduction électrique entre les deux faces (2, 3) et,- à combler les cavités (5) avec un matériau diélectrique (7).Le substrat est équipé de connexions conductrices traversantes entre sa face avant (2) et sa face arrière (3). Les connexions conductrices sont assurées par des plots (4) délimités par des cavités (5) comblées avec un matériau diélectrique (7).Application, en particulier, à des substrats utilisés pour la fabrication de micro-capteurs.

Process for protecting an electronic device by selective deposition of polymer coatings.

Se describen métodos para la protección de un dispositivo electrónico de contaminantes por medio de la aplicación de diferentes materiales poliméricos a diferentes componentes vitales de un dispositivo. En una modalidad, el método comprende la aplicación (110, 120) de un primer polímero, tal como (210, 220) un polímero de base acrílica, a uno o más conectores y componentes localizados sobre la tarjeta de circuitos impresos del dispositivo. El método además comprende la aplicación (140) de un segundo polímero, tal como un polímero de base silicona, a diferentes conectores y componentes sobre la tarjeta de circuitos impresos. El método lleva a que diferentes componentes sean revestidos con un polímero diferente, sin la necesidad de revestimientos de capas múltiples sobre ningún componente. También se describen dispositivos electrónicos que son protegidos mediante tales revestimientos poliméricos e hidrofóbicos. Ejemplos no limitantes de tales dispositivos incluyen teléfonos inteligentes, computadoras, y dispositivos de juego.

Monitoring dry-etching of polymer layer for transferring semiconductor devices

Embodiments relate to placing light emitting diodes from a carrier substrate to a target substrate. At least one LED is embedded in a polymer layer on a substrate. The polymer layer is etched between the at least one LED and the substrate. A thickness of the polymer layer is monitored during etching of the polymer layer. The etching of the polymer layer is terminated responsive to determining that the thickness of the polymer layer is in a target range or a target value. A pick-up-tool (PUT) is brought into contact with at least one surface of the at least one LED facing away from the substrate responsive to dry-etching the polymer layer, and the PUT is lifted with the at least one LED attached to the PUT.

Ceramic Board Manufacturing Method and Ceramic Board manufactured by thereof

본 발명은 세라믹 기판 제조 방법 및 이 제조방법으로 제조된 세라믹 기판에 관한 것으로, 세라믹 기재 상에 시드층, 도금으로 형성된 브레이징 필러층, 금속박을 적층하여 브레이징하여 상기 세라믹 기재에 상기 금속박을 브레이징 접합층을 통해 견고히 접합하는 것으로 금속박과 세라믹 기재의 접합력을 크게 향상시킴은 물론 도금으로 형성된 브레이징 필러층의 두께를 10㎛ 이하로 형성하여 세라믹 기판의 두께를 슬림하게 하고, 금속박과 세라믹 기재와의 간격을 최소화하여 방열 효과를 극대화한다. The present invention relates to a method of manufacturing a ceramic substrate and a ceramic substrate produced by the method. The ceramic substrate is laminated by brazing a seed layer, a brazing filler layer formed by plating, and a metal foil on the ceramic substrate, The bonding strength between the metal foil and the ceramic base material is greatly improved and the thickness of the brazing filler layer formed by plating is set to 10 μm or less to make the thickness of the ceramic substrate slimmer and the distance between the metal foil and the ceramic base material Minimize to maximize heat dissipation effect.

Scalable, printable, patterned sheet of high mobility graphene on flexible substrates

The present invention provides methods for fabricating graphene workpieces. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention.

Long-term packaging for the protection of implant electronics

The present invention provides a micropackaged device comprising: a substrate for securing a device; a corrosion barrier affixed to said substrate; optionally at least one feedthrough disposed in said substrate to permit at least one input and or at least one output line into said micropackaged device; and an encapsulation material layer configured to encapsulate the micropackaged device.

Double-Sided Circuit Non-Oxide-Based Ceramic Substrate and Method for Manufacturing Same

本發明提供一種散熱性優異、且低成本之雙面電路非氧化物系陶瓷基板及其製造方法。 本發明之雙面電路非氧化物系陶瓷基板1具備：高導熱性非氧化物系陶瓷基板10，其具有通孔11；保持層20，其形成於上述通孔11之壁面11a；及導電性金屬部30S，其藉由上述保持層20保持於上述通孔11之內部，且不包含活性金屬。本發明之雙面電路非氧化物系陶瓷基板1較佳為具備電極(薄膜電極41、42)，該電極(薄膜電極41、42)被覆露出於上述陶瓷基板10之正背面之上述保持層20之端面20a、20b、及上述導電性金屬部30S之端面30a、30b。

Nickel diffusion bonded to metallized ceramic body and method

Packless cementation is used to diffusion bond nickel to discrete exposed areas of tungsten or molybdenum that are in turn bonded to the surface of a ceramic body, e.g. in the preparation of a ceramic chip carrier or other premetallized ceramic device.

Substrate and its manufacturing method

本发明涉及一种基板及其制造方法。该基板包括：基材；和离子注入层，其注入到基材的表面下方。制造基板的方法包括：对基材进行前处理(S1)；以及通过离子注入将导电材料注入到经前处理后的基材的表面下方，形成离子注入层(S2)。

Method for forming copper wiring

In a Cu wiring forming method for forming a Cu wiring by filling Cu in a recess which is formed in a substrate in a predetermined pattern, a barrier film formed of a TaAlN film is formed at least on the surface of the recess by thermal ALD or thermal CVD. Then a Cu film is formed to fill the recess with the Cu film. Further, the Cu wiring is formed in the recess by polishing the entire surface of the substrate by CMP.

Method for forming thin film conductors on a substrate

A method for forming thin film conductors is disclosed. A thin film precursor material is initially deposited onto a porous substrate. The thin film precursor material is then irradiated with a light pulse in order to transform the thin film precursor material to a thin film such that the thin film is more electrically conductive than the thin film precursor material. Finally, compressive stress is applied to the thin film and the porous substrate to further increase the thin film's electrical conductivity.

Apparatus and method for conformal coating of integrated circuit packages

An electronic system includes a printed circuit board (PCB), a component affixed to the PCB, and a conformal coating layer on the PCB and the component. The conformal coating layer includes parylene. Furthermore, the electronic system includes an underfill layer adjacent to the conformal coating layer, filling a gap between the PCB and the component. Other embodiments being described and/or claimed.

Thin integral resistor/capacitor/inductor package, method of manufacture

A thin electrical circuitry structure is formed which contains conductive circuitry traces, integral capacitors and integral resistors. A first laminate structure comprises a conductive foil having a layer of embeddable dielectric material laminated thereto. A second laminate structure comprises a conductive foil having a layer of resistive material on one side, the thickness of the resistive material layer being less than that of the layer of embeddable dielectric material. The resistive material layer is circuitized to produce resistive patches, and the two structures are laminated together, embedding the resistive patches in the dielectric material layer. One of the foils is circuitized providing circuitry traces, optional inductor coils, and capacitor plates. That foil embedded in dielectric laminate to support the structure for further processing. The other foil is then circuitized providing circuitry traces, optional inductor coils and capacitor plates. Traces on one side connector with the resistive material patches to provide the resistors.

Protective coating

A method for depositing a protective coating onto a substrate, wherein the protective coating comprises (i) a moisture-barrier layer which is in contact with the substrate and which comprises a first sub-layer, optionally one or more intermediate sub-layers, and a final sub-layer, (ii) a mechanical-protective layer which is inorganic, and (iii) a gradient layer interposing the moisture-barrier layer and the mechanical-protective layer.

Multilayer printed circuit board and method for manufacturing same

Electronic device case, electronic device, and composite body

本发明提供了电子设备壳体、电子设备和复合体。其中，电子设备壳体包括：框体；封接层，所述封接层设置在所述框体的至少一部分外表面上，所述封接层包括依次层叠设置的多个封接子层；背壳，所述背壳通过所述封接层与所述框体相连；其中，所述封接层的热膨胀系数在所述框体和所述背壳的热膨胀系数之间，且所述框体、多个所述封接子层和所述背壳中相邻两结构之间的热膨胀系数差异在±10％以内。该电子设备壳体中背壳和框体结合牢固、力学性能良好，同时外观效果美观，使用寿命长，且能够很好的满足信号使用要求，避免信号屏蔽问题，既可满足用户日益增强的审美要求，又具有较佳的使用性能，提高用户体验。

Scalable, printable, patterned sheet of high mobility graphene on flexible substrates

The present invention provides methods for fabricating graphene workpieces. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention.

Printed circuit boards

국소화 땜납 연결이 만들어지는 인쇄 회로 기판에 관한 것으로, 상기 인쇄 회로 기판의 표면은 1 nm 내지 10 ㎛의 두께의 할로-탄화수소(halo-hydrocarbon) 중합체를 포함하는 조성물의 연속 또는 불연속 코팅을 갖는다. A printed circuit board in which localized solder connections are made, the surface of the printed circuit board having a continuous or discontinuous coating of a composition comprising a halo-hydrocarbon polymer having a thickness of 1 nm to 10 μm.

Coating electric component

一种电气组件，所述电气组件在其至少一个表面上具有包括三层或更多层的多层保形涂层，其中：与所述电气组件的至少一个表面接触的所述多层保形涂层的最下层通过包含(a)一种或多种有机硅化合物；(b)可选地，O 2 、N 2 O、NO 2 、H 2 、NH 3 和/或N 2 ；和(c)可选地，He、Ar和/或K的前体混合物的等离子体沉积获得；所述多层保形涂层的最上层通过包含(a)一种或多种有机硅化合物；(b)可选地，O 2 、N 2 O、NO 2 、H 2 、NH 3 和/或N 2 ；和(c)可选地，He、Ar和/或Kr的前体混合物的等离子体沉积获得；并且所述多层涂层包括一层或多层，所述一层或多层通过包含(a)一种或多种式(A)的烃类化合物；(b)可选地，NH 3 、N 2 O、N 2 、NO 2 、CH 4 、C 2 H 6 、C 3 H 6 和/或C 3 H 8 ；和(c)可选地，He、Ar和/或Kr的前体混合物的等离子体沉积获得，式(A)中Z 1 表示C 1 ‑C 3 烷基或C 2 ‑C 3 烯基；Z 2 表示氢、C 1 ‑C 3 烷基或C 2 ‑C 3 烯基；Z 3 表示氢、C 1 ‑C 3 烷基或C 2 ‑C 3 烯基；Z 4 表示氢、C 1 ‑C 3 烷基或C 2 ‑C 3 烯基；Z 5 表示氢、C 1 ‑C 3 烷基或C 2 ‑C 3 烯基；和Z 6 表示氢、C 1 ‑C 3 烷基或C 2 ‑C 3 烯基。

Solder mask

A method for formation of a patterned solder mask (10) on a substrate comprising apertures and/or non-planar surfaces is provided, in which method the mask is deposited by a process of chemical deposition in vapor Phase. Mask patterning is implemented by a process of lift-off patterning with water-soluble lift-off material (21). A method for manufacturing a printed circuit board and/or an electronic component comprising formation of said patterned solder mask is further provided.

Laminate sheet for metal-clad laminate and method for producing same, and metal-clad laminate and method for producing same

本发明的课题为提供一种覆金属层压板用层压片及其制造方法，该覆金属层压板用层压片包括包含液晶聚合物或氟聚合物的基材及粘接剂层，并且与形成于粘接剂层上的金属层的密合性优异。并且，本发明的另一课题为提供一种覆金属层压板及其制造方法。本发明的覆金属层压板用层压片是依次层叠包含液晶聚合物或氟聚合物的基材、无机氧化物层及粘接剂层而成。

Coated electrical assembly

The present invention relates to an electrical assembly which has a conformal coating, wherein said conformal coating is obtainable by a method which comprises: (a) plasma polymerization of a compound of formula (I) and a fluorohydrocarbon, wherein the molar ratio of the compound of formula (I) to the fluorohydrocarbon is from 5:95 to 50:50, and deposition of the resulting polymer onto at least one surface of the electrical assembly: wherein: R 1 represents C 1 -C 3 alkyl or C 2 -C 3 alkenyl; R 2 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl; R 3 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl; R 4 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl; R 5 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl; and R 6 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl, and (b) plasma polymerization of a compound of formula (I) and deposition of the resulting polymer onto the polymer formed in step (a).

Coated electrical assembly

An electrical assembly which has a multi-layer conformal coating on at least one surface of the electrical assembly, wherein each layer of the multi-layer coating is obtainable by plasma deposition of a precursor mixture comprising (a) one or more organosilicon compounds, (b) optionally O 2 , N 2 O, NO 2 , H 2 , NH 3 , N 2 , SiF 4 and/or hexafluoropropylene (HFP), and (c) optionally He, Ar and/or Kr. The chemistry of the resulting plasma-deposited material chemistry can be described by the general formula: SiO x H y C z F a N b . The properties of the conformal coating are tailored by tuning the values of x, y, z, a and b.

Coated electrical assembly

An electrical assembly which has a multi-layer conformal coating comprising three or more layers on at least one surface of the electrical assembly, wherein the lowest layer of the multi-layer conformal coating, which is in contact with the at least one surface of the electrical assembly, is obtainable by plasma deposition of a precursor mixture comprising (a) one or more organosilicon compounds, (b) optionally O2, N2O, NO2, H2, NH3 and/or N2, and (c) optionally He, Ar and/or Kr; the uppermost layer of the multi-layer conformal coating is obtainable by plasma deposition of a precursor mixture comprising (a) one or more organosilicon compounds, (b) optionally O2, N2O, NO2, H2, NH3 and/or N2, and (c) optionally He, Ar and/or Kr; and the multi-layer coating comprises one or more layers which is obtainable by plasma deposition of a precursor mixture comprising (a) one or more hydrocarbon compounds of formula (A), (b) optionally NH3, N2O, N2, NO2, CH4, C2H6, C3H6 and/or C3H8, and (c) optionally He, Ar and/or Kr, Z1 represents C1-C3 alkyl or C2-C3 alkenyl; Z2 represents hydrogen, C1-C3 alkyl or C2-C3 alkenyl; Z3 represents hydrogen, C1-C3 alkyl or C2-C3 alkenyl; Z4 represents hydrogen, C1-C3 alkyl or C2-C3 alkenyl; Z5 represents hydrogen, C1-C3 alkyl or C2-C3 alkenyl; and Z6 represents hydrogen, C1-C3 alkyl or C2-C3 alkenyl.

Thin integral resistor/capacitor/inductor package, method of manufacture

A thin electrical circuitry structure is formed which contains conductive circuitry traces, integral capacitors and integral resistors. A first laminate structure comprises a conductive foil having a layer of embeddable dielectric material laminated thereto. A second laminate structure comprises a conductive foil having a layer of resistive material on one side, the thickness of the resistive material layer being less than that of the layer of embeddable dielectric material. The resistive material layer is circuitized to produce resistive patches, and the two structures are laminated together, embedding the resistive patches in the dielectric material layer. One of the foils is circuitized providing circuitry traces, optional inductor coils, and capacitor plates. That foil embedded in dielectric laminate to support the structure for further processing. The other foil is then circuitized providing circuitry traces, optional inductor coils and capacitor plates. Traces on one side connector with the resistive material patches to provide the resistors.

Systems for assembling electronic devices with internal moisture-resistant coatings

A system for assembling electronic devices includes at least one coating element for applying a moisture-resistant coating to surfaces of a device under assembly, or an electronic device under assembly. As components and one or more moisture-resistant coatings are added to the electronic device under assembly to form a finished electronic device, at least one surface on which the coating resides and, thus, at least a portion of the coating itself, is located internally within the finished electronic device. Methods for assembling electronic devices that include internally confined moisture-resistant coatings are also disclosed.

Formation of thin film resistors

The invention is directed to thin film resistors which may be embedded in multi-layer printed circuit boards. The invention is also directed to structures for forming such thin film resistors and to methods for forming such structures, including the use of combustion chemical vapor deposition. The invention is also directed to chemical precursor solutions by which resistive materials can be deposited on a substrate by combustion chemical vapor deposition techniques.

System and method for providing a moisture resistant coating on a refurbished or remanufactured electronic device

電子デバイスを改修又は再製品化することに対する手法は、電子デバイスの内部の内に置かれている電気的構成要素を露出させる段階を伴う。本手法は、更に、電子デバイスの欠陥のある１つ又はそれ以上の構成要素を１つ又はそれ以上の交換用構成要素と交換する段階、及び保護被覆を電子デバイスの内部の少なくとも一部分へ塗工する段階を備えている。保護被覆は、回路板及びそれが担持する電子的構成要素を覆う。保護被覆は、更に、電子デバイスの電気的接続箇所の少なくとも幾つか覆うこともある。保護被覆は、再組立に先立って交換用構成要素へ塗工されるようになっていてもよい。得られる改修又は再製品化電子デバイスには、而して、電子デバイスを湿分への曝露によって引き起こされる損害から保護するのに役立つ耐湿性が備わる。【選択図】図２

Formation of thin film resistors

本发明涉及可以埋入多层印刷线路板中的薄膜电阻，也涉及用来形成这些薄膜电阻的结构和形成这些结构的方法，包括使用燃烧化学气相淀积法。本发明还涉及化学前体溶液，使用该化学前体溶液可以通过燃烧化学气相淀积技术将电阻材料淀积到底材上。

Wiring substrate, and method for manufacturing wiring substrate

A wiring board includes a first substrate having stretchability, wiring disposed adjacent to a first surface of the first substrate and extending in a first direction, and a stopper disposed adjacent to the first surface or second surface of the first substrate. While stretch length of the wiring board is being increased in the first direction, electrical resistance of the wiring exhibits a first turning point at a first stretch length and tension applied to the wiring board exhibits a second turning point at a second stretch length smaller than the first stretch length. The first turning point is a point at which an increase in electrical resistance per unit stretch length changes. The second turning point is a point at which an increase in tension per unit stretch length changes.

Method for preparing waterproof and electric breakdown-resistant coating

A method for preparing a waterproof and electric breakdown-resistant coating, comprising the following steps: (1) placing a substrate in a reaction cavity, continuously vacuumizing, and introducing an inert gas or nitrogen; and (2) introducing monomer vapor and enabling plasma discharge to prepare a waterproof and electric breakdown-resistant coating on the surface of the substrate, the component of the monomer vapor being: a mixture of at least one monofunctional unsaturated fluorocarbon resin and at least one polyfunctional unsaturated hydrocarbon derivative, the mass fraction of the polyfunctional unsaturated hydrocarbon derivative in the monomer vapor being 30-50%.

Orthogonal grid circuit interconnect method

Methods for making low cost, high density circuits for multichip modules using a two-layer interconnect pattern. The circuit is comprised of parallel line segments on each side of the dielectric film, orthogonal to each other to form a mesh or grid when viewed through the film. Line segments are interrupted, as required, to form signal lines connected to each other with metalized vias at appropriately selected intersections of the grid through the dielectric film. Power and ground lines are placed between the signal lines to prevent crosstalk between long parallel line segments. Power and ground lines are also appropriately connected at intersections to form co-connected mesh planes in the two surfaces. The novelty of the invention also resides in the methods of constructing the circuit, wherein circuit patterns on each side and vias are formed simultaneously in a single set of plating operations. Virtually no subtractive etching is required, making the methods environmentally friendly and very low cost. Line feature sizes approach 25 microns or smaller, with line pitch of 50 microns or smaller. Fabricated circuits can accommodate wire-, TAB-, or flip-chip-mounted components, and passive components by adhesive bonding or soldering. Because all lines are formed with additive copper, total circuit resistance is low, typically forty percent lower circuit resistance than signal lines 15 made with aluminum conductors.

Evacuated core circuit board

Method for modifying circuit within substrate

A method is provided for modifying a circuit containing a plurality of electrodes, within a substrate, comprising the steps of: (a) selecting at least two electrodes for making a connection; (b) removing materials covering the electrodes with a focused ion beam (FIB) or a laser to form contact holes for respectively exposing the electrodes; (c) depositing in the contact holes a conductive material for forming electrically conductive piers, by applying the focused ion beam (FIB) or laser, with gas molecules ejected from a nozzle; (d) disposing an electrically conductive viscid material over each of the electrically conductive piers; and (e) disposing an electrically conductive bridge floor to connect with the electrically conductive viscid material to form an electrically conductive bridge.

Printed circuit boards

A printed circuit board to which a localised solder connection is to be made, the surface of said printed circuit board having a continuous or non-continuous coating of a composition comprising a halo-hydrocarbon polymer at a thickness of from 1nm to 10µm.

Patent RU2018130110A3

COVERED ELECTRICAL ASSEMBLY

Systems for assembling electronic devices with internal moisture-resistant coatings

A system for assembling electronic devices includes at least one coating element for applying a moisture-resistant coating to surfaces of a device under assembly, or an electronic device under assembly. As components and one or more moisture-resistant coatings are added to the electronic device under assembly to form a finished electronic device, at least one surface on which the coating resides and, thus, at least a portion of the coating itself, is located internally within the finished electronic device. Methods for assembling electronic devices that include internally confined moisture-resistant coatings are also disclosed.

Multilayer wiring board and manufacture method thereof

In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.

Method for repairing conductor on board and repaired structure

Sensors, systems and methods for detecting analytes using same

Sensors, as well as systems and methods of using the same are provided. Aspects of the sensors include a piezoelectric base, a plurality of surface-associated compositions that are stably associated with the piezoelectric base, and a plurality of crosslinking compositions that are configured to crosslink one or more surface-associated compositions in the presence of an analyte. The sensors, systems and methods described herein find use in a variety of applications, including the detection of an analyte in a sample.

PROTECTIVE COVERING

Via Filled Substrate, Manufacturing Method and Precursor

본 발명은 구멍부를 가지는 절연성 기판의 구멍부 벽면에 활성 금속을 포함하는 금속막을 형성하는 금속막 형성 공정, 소성 전후의 체적 변화율이 ―10%∼20%인 도체 페이스트를, 금속막을 형성한 구멍부에 충전하는 충전 공정, 도체 페이스트가 충전된 절연성 기판을 소성하는 소성 공정을 포함하는 비아 충전 기판의 제조 방법에 관한 것이다. The present invention provides a metal film forming step of forming a metal film containing an active metal on a hole wall surface of an insulating substrate having a hole, and a conductor paste having a volume change rate of -10% to 20% before and after firing. And a firing step of firing an insulating substrate filled with a conductor paste and a firing step of filling in the conductive paste.

Sensors, systems and metheods for detecting analytes using same

Sensors, as well as systems and methods of using the same are provided. Aspects of the sensors include a piezoelectric base, a plurality of surface-associated compositions that are stably associated with the piezoelectric base, and a plurality of crosslinking compositions that are configured to crosslink one or more surface-associated compositions in the presence of an analyte. The sensors, systems and methods described herein find use in a variety of applications, including the detection of an analyte in a sample.

Printed Circuit Boards

A printed circuit board to which a localised solder connection is to be made, the surface of said printed circuit board having a continuous or non-continuous coating of a composition comprising a halo-hydrocarbon polymer at a thickness of from 1 nm to 10 μm.

Formation of thin film resistors

本发明涉及可以埋入多层印刷线路板中的薄膜电阻，也涉及用来形成这些薄膜电阻的结构和形成这些结构的方法，包括使用燃烧化学气相淀积法。本发明还涉及化学前体溶液，使用该化学前体溶液可以通过燃烧化学气相淀积技术将电阻材料淀积到底材上。

Electrical resistor

(57)【要約】 【課題】 印刷回路に対して好ましい薄層抵抗体を提供 すること。 【解決手段】 絶縁基板上に設けられた抵抗体材料の層 及び前記抵抗体材料の層の上に離間して配置された前記 抵抗体材料の層の電気的接続手段を含む電気抵抗体であ って、前記抵抗体材料が約９５〜約９９．５重量％のゼ ロ原子価金属及び約５〜約０．５重量％の誘電性材料の 均質混合物を含む抵抗体。

Structure having laser ablated features and method of fabricating

Embedded flush circuitry features are provided by providing a conductive seed layer on the sidewalls and bottom of laser ablated trench features plating a layer of conductive metal onto the seed layer and depositing a layer of dielectric material.

Method for patterning of conductive polymer

Disclosed herein is a method of patterning a circuit using a self-assembly lithography. More specifically, the present invention is directed to a method of a circuit by a self-assembly lithography, which comprises the steps of: coating a substrate; forming the primary circuit; completing the patterning; and washing the substrate, a self-assembled lithographic circuit prepared by said method, and a method of forming an electrode circuit using said circuit. The inventive method of patterning a circuit using a self-assembly lithography is a new patterning process which does not use any typical photoresists and developers, thereby greatly reducing the manufacturing cost. Further, the inventive method converts the conventional top-down process into a bottom-up process, which enables to form more fine circuits with freedom. The circuit prepared according to the present invention can be effectively used for the photo process in a semiconductor and a display.

Systems for assembling electronic devices with internal moisture-resistant coatings

本发明涉及一种用于装配具有内部防水涂层的电子装置的系统。用于装配电子装置的系统包括：至少一个涂覆元件，用于把防水涂层施加于装配中的装置或电子子配件的表面。当组件和一个或多个防水涂层被添加到电子子配件以形成制成电子装置时，涂层所在的至少一个表面在内部布置在制成电子装置内，因此涂层自身的至少一部分在内部布置在制成电子装置内。还公开了用于装配包括限制于内部的防水涂层的电子装置的方法。

Wiring board and method of producing wiring board

A wiring board capable of suppressing migration between wires and to provide a method of producing the same, in a method of producing a wiring board provided with a first wiring board in which a first wiring layer is formed, and a second wiring board in which a second wiring layer finer than the first wiring layer is formed, the second wiring board is formed by performing steps of forming a first insulating resin layer provided with a wiring pattern and openings, forming a first inorganic insulating film on the first insulating resin layer, forming a first conductor layer corresponding to the wiring pattern and the openings on the inorganic insulating film, and forming a second inorganic insulating film on the first conductor layer.

Wiring board and method for manufacturing wiring board

A wiring board (10) includes a substrate (11) that is transparent and a wiring pattern region (20) that is disposed on the substrate (11) and that includes a plurality of wiring lines (21, 22). The wiring pattern region (20) has a sheet resistance of less than or equal to 5 Ω/sq, and each wiring line (21, 22) has a maximum width of less than or equal to 3 µm when viewed at a viewing angle of 120°.

Waterproof structure for implanted electronic device

A waterproof structure for an implanted electronic device is capable of preventing the liquid or moist from entering and damaging the circuit board of the electronic device. The waterproof structure includes a shell, a first material layer, a second material layer, and a third material layer. The first material layer covers at least a part of the implanted electronic device. The second material layer covers the first material layer. The internal space of the shell is configured for accommodating the implanted electronic device. The shell is made of PEEK (polyether ether ketone). The third material layer is disposed between the second material layer and the shell.

Coated electrical assembly

An electrical assembly which has a multi-layer conformal coating comprising three or more layers on at least one surface of the electrical assembly, wherein the lowest layer of the multi-layer conformal coating, which is in contact with the at least one surface of the electrical assembly, is obtainable by plasma deposition of a precursor mixture comprising (a) one or more organosilicon compounds, (b) optionally O 2 , N 2 O, NO 2 , H 2 , NH 3 and/or N 2 , and (c) optionally He, Ar and/or Kr; the uppermost layer of the multi-layer conformal coating is obtainable by plasma deposition of a precursor mixture comprising (a) one or more organosilicon compounds, (b) optionally O 2 , N 2 O, NO 2 , H 2 , NH 3 and/or N 2 , and (c) optionally He, Ar and/or Kr; and the multi-layer coating comprises one or more layers which is obtainable by plasma deposition of a precursor mixture comprising (a) one or more hydrocarbon compounds of formula (A), (b) optionally NH 3 , N 2 O, N 2 , NO 2 , CH 4 , C 2 H 6 , C 3 H 6 and/or C 3 H 8 , and (c) optionally He, Ar and/or Kr, Z 1 represents C 1 -C 3 alkyl or C 2 -C 3 alkenyl; Z 2 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl; Z 3 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl; Z 4 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl; Z 5 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl; and Z 6 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl.

Coated electrical assembly

An electrical assembly which has a multi-layer conformal coating comprising three or more layers on at least one surface of the electrical assembly, wherein the lowest layer of the multi-layer conformal coating, which is in contact with the at least one surface of the electrical assembly, is obtainable by plasma deposition of a precursor mixture comprising (a) one or more organosilicon compounds, (b) optionally O2, N2O, NO2, H2, NH3 and/or N2, and (c) optionally He, Ar and/or Kr; the uppermost layer of the multi-layer conformal coating is obtainable by plasma deposition of a precursor mixture comprising (a) one or more organosilicon compounds, (b) optionally O2, N2O, NO2, H2, NH3 and/or N2, and (c) optionally He, Ar and/or Kr; and the multi-layer coating comprises one or more layers which is obtainable by plasma deposition of a precursor mixture comprising (a) one or more hydrocarbon compounds of formula (A), (b) optionally NH3, N2O, N2, NO2, CH4, C2H6, C3H6 and/or C3H8, and (c) optionally He, Ar and/or Kr, Z1 represents C1-C3 alkyl or C2-C3 alkenyl; Z2 represents hydrogen, C1-C3 alkyl or C2-C3 alkenyl; Z3 represents hydrogen, C1-C3 alkyl or C2-C3 alkenyl; Z4 represents hydrogen, C1-C3 alkyl or C2-C3 alkenyl; Z5 represents hydrogen, C1-C3 alkyl or C2-C3 alkenyl; and Z6 represents hydrogen, C1-C3 alkyl or C2-C3 alkenyl.

Nanolaminated thin film circuitry materials

Nanolaminates are formed by alternating deposition, e.g., by combustion chemical vapor deposition (CCVD), layers of resistive material (11) and layers of dielectric material (12). Outer resistive material layers (11) are patterned to form discrete patches of resistive material. Electrical pathways between opposed patches of resistive material (11) on opposite sides of the laminate (10) act as capacitors. Electrical pathways horizontally through resistive material layers (11), which may be connected by via plated holes (14), act as resistors.

Nanolaminated thin film circuitry materials

미소적층체(nanolaminates)는 저항체의 층과 유전체 층을 교대로 증착, 예를 들어 연소 화학 기상 증착(combustion chemical vapor deposition; CCVD)함으로서 형성된다. 외부 저항체 층들은 패터닝되어 저항체의 개별 패치들(patches)을 형성한다. 적층체의 마주보는 측부상의 저항체의 마주보는 패치들 간의 전기적 경로는 캐패시터로 작용한다. 전기적 경로들은 레지스터(resistor)로 작용하는 저항체 층들을 수평으로 관통하며, 저항체 층들은 도금된 비아 홀(via hole)에 의하여 연결될 수 있다. Nanolaminates are formed by alternately depositing a layer of a resistor and a dielectric layer, for example, combustion chemical vapor deposition (CCVD). The outer resistor layers are patterned to form individual patches of resistor. The electrical path between the opposing patches of the resistor on the opposite side of the stack acts as a capacitor. The electrical paths pass horizontally through the resistor layers acting as resistors, which can be connected by plated via holes. 미소적층체, 캐패시터/레지스터 Microlayers, Capacitors / Registers

Evacuated core circuit board

An evacuated core circuit board (10) for dissipating heat from a heat generating electronic component, the evacuated core circuit board comprising: at least one circuit layer (12) to which the heat generating electronic component (14) is electronically coupled; a base layer (16) a comprising a body structure (19) having a substantially hollow interior (20); and a dielectric layer (18) provided between at least a portion of the circuit layer (12) and the base layer (16), wherein the hollow interior (20) is at least partially evacuated.

Protective coating

本發明提供一種在基板上沉積保護塗層之方法，其中該保護塗層包含(i)防潮層，其係與該基板接觸且其包含第一子層、可選的一或多個中間子層及最終子層；(ii)係無機之機械保護層；及(iii)插入該防潮層與該機械保護層之間之梯度層。

Wiring board and method for manufacturing wiring board

A wiring board (10) according to the present invention comprises: a transparent substrate (11); and a wiring pattern region (20) that is disposed on the substrate (11) and includes a plurality of wirings (21, 22). The wiring pattern region (20) has a sheet resistance value of 5 Ω/□ or less, and the wirings (21, 22) have a maximum width of 3 μm or less when viewed at a viewing angle of 120°.