Verfahren zur Herstellung eines flächigen Schaltungsträgers

Verfahren zur Herstellung eines flächigen Schaltungsträgers, bei dem auf einem Stützkörper zumindest zwei Leiterbilder (3, 3.n) erzeugt werden, wobei als Stützkörper als Hilfsträger (1) aus einer kontinuierlich ausgebildeten metallischen Basisfolie einer Dicke von mindestens 5 mum verwendet wird, auf die zunächst zumindest eine erste, kontinuierlich ausgebildete Isolierschicht (2) aufgebracht wird und wobei auf die Isolierschicht (2) in der erforderlichen Anzahl abwechselnd jeweils ein Leiterbild (3) und daran nach Bedarf eine kontinuierlich ausgebildete, weitere Isolierschicht (2.n) aufgebracht und festgelegt wird, wonach das so erhaltene Gebilde auf einen flächig ausgebildeten elektrisch isolierenden Stützkörper (5) auflaminiert wird.

DIE-GEHÄUSE UND VERFAHREN ZUM BILDEN EINES DIE-GEHÄUSES

Ein Die-Gehäuse ist bereitgestellt. Das Die-Gehäuse kann Folgendes beinhalten: einen Die mit einem ersten Die-Kontakt auf einer ersten Seite des Die und einem zweiten Die-Kontakt auf einer zweiten Seite des Die, die der ersten Seite des Die gegenüberliegt, ein Isolationsmaterial, das lateral dem Die benachbart ist, eine Metallstruktur, die die gesamte Oberfläche des zweiten Die-Kontakts des Die im Wesentlichen direkt kontaktiert, wobei die Metallstruktur aus dem gleichen Material wie der zweite Die-Kontakt gefertigt ist, einen ersten Padkontakt auf der ersten Seite des Die, der den ersten Die-Kontakt elektrisch kontaktiert, und einen zweiten Padkontakt auf der ersten Seite des Die, der den zweiten Die-Kontakt über die Metallstruktur elektrisch kontaktiert, wobei das Isolationsmaterial die Metallstruktur elektrisch von dem ersten Die-Kontakt isoliert.

Verfahren und Vorrichtung zur Herstellung einer Rolle von Antennenelementen und zur Ausgabe derartiger Antennenelemente

Method of surface-mounting components

A carrier substrate 105 is provided with a plurality of electronic components 103, each of the electronic components having at least one electrical contact coated with electrically conductive adhesive 102. The carrier substrate 105 is attached to the flexible circuit board 106 such that the electronic components 103 are adhered to the flexible circuit board 106 in electrical contact therewith via the conductive adhesive 102. The conductive adhesive may be applied to the components via a flexible substrate. The components may be attached to the carrier substrate by a thermal release adhesive so that when the conductive adhesive is cured, the carrier substrate is released from the components. The flexible circuit board may be stored on a roll after the electronic components are adhered to it (Fig. 12).

Verfahren zum Herstellen einer Leiterplatte sowie Leiterplatte

A method for producing a printed circuit board (10) with at least one embedded sensor chip (3), in which at least one sensor face (5) and connectors (4) are arranged on a face of the chip, comprising the following steps: a) providing an adhesive film (1), b) printing a conductor structure (2) made of a conductive paste onto a surface of the adhesive film, c) placing the at least one sensor chip (3) with the face having the at least one sensor face (5) and the connectors (4) onto the conductor structure (2) made of a conductive paste in a registered manner, d) curing the conductive paste, e) applying an insulation layer (6) with a conductor layer (7) lying thereabove onto the surface having the chip (3) of the structure created in the preceding steps, f) laminating the structure created in the preceding steps, g) structuring the conductor layer (7) and forming vias (9) from the conductor layer to the printed conductors (7b, 7c) of the conductor structure on the surface of the adhesive film ...

VERFAHREN ZUM HERSTELLEN, INSBESONDERE BEARBEITEN ODER BESTÜCKEN, EINES LEITERPLATTENELEMENTS SOWIE TRÄGER ZUR VERWENDUNG IN EINEM DERARTIGEN VERFAHREN

In a method for producing a circuit board element, the following steps are provided: providing a substantially whole-area carrier having an adhesive surface; arranging and fixing a starting material of the circuit board element to be produced on the adhesive surface of the carrier; producing the circuit board element fixed on the carrier in a position fixed on the carrier; and removing the produced circuit board element from the carrier. Furthermore, a carrier for use in such a method is provided, wherein it is possible, in particular, to dispense with complex steps for separating or singulating circuit board elements and, with conservation of resources as a result of reusability of a carrier, it is possible to obtain cost savings in the production of circuit board elements.

Verfahren zur Herstellung einer Leiterplatte mit zumindest einer optoelektronischen Komponente

The invention relates to a method for producing a circuit board having at least one optoelectronic component, which method is characterized by the following steps: a) applying a transparent curable adhesive layer (1) to a carrier layer (2), b) placing at least one optoelectronic component (3) onto the adhesive layer (1) by means of an optically relevant side (4) of the component, c) curing the adhesive layer (1) into a window element (1'), d) embedding the component (3) in a circuit-board composite, e) structuring the carrier layer (2) in order to at least partially expose the window element (1') and to contact the component (3).

配线基板的制造方法

... 本发明的目的在于简单制造可靠性高的配线基板。通过热固化性树脂前驱体形成受理层。在受理层的上面，通过含有导电性微粒的分散液来形成配线层。使热固化性树脂前驱体进行固化反应，向受理层和配线层供给使导电性微粒相互结合的热。 ...

Interposer substrate and method of fabricating same

CHART OF RESIN WIRING ORGANIC STRATIFIEE AND PROCEEDED FOR SA MANUFACTURE

WIRING BOARD IN WHICH A PAD FOR MOUNTING A SEMICONDUCTOR DEVICE IS INSTALLED AND A MANUFACTURING METHOD THEREOF

PURPOSE: A wiring board is provided to maintain reliability of connection and not to obstruct the miniaturization of wiring and not to cause performance degradation of the wiring board by including a pad for outside connection. CONSTITUTION: A wiring board comprises: Insulating layer(7); a wiring layer installed at the single-side of the insulating layer; a pad for outside connection(1) installed at the other surface of the insulating layer; a surface coating layer(2), which is formed on the outside pad, for connection with the external circuit; a plurality of wiring layers; and a plurality of insulating layers installed between a plurality of wiring layers. The area of the pad for outside connection is smaller than the area of the surface coating layer. The pad for outside connection characterizes to be the pad for mounting the electronic component including the semiconductor device etc. in the wiring board. © KIPO 2009 ...

METHOD OF TEMPORARILY ATTACHING A RIGID CARRIER TO A SUBSTRATE

Method for temporarily attaching a substrates to a rigid carrier is described which includes forming a sacrificial layer of a thermally-decomposable polymer, e.g., poly(alkylene carbonate), and bonding the flexible substrate to the rigid carrier with the sacrificial layer positioned therebetween. Electronic components and/or circuits may then be fabricated or other semiconductor processing steps employed (e.g., backgrinding) on the attached substrate. Once fabrication is completed, the substrate may be detached from the rigid carrier by heating the assembly to decompose the sacrificial layer. © KIPO & WIPO 2009 ...

METHOD FOR ATTACHING A DOME SHEET CAPABLE OF DRASTICALLY REDUCING A DEFECTIVE ATTACHMENT RATE

PURPOSE: A method for attaching a dome sheet is provided to attach a first film or a second film to the first point and the second point of a dome metal by one integration operation, thereby increasing work efficiency. CONSTITUTION: A plurality of receiving grooves(105) is formed on a work panel(100). The shape of the receiving grooves corresponds to the shape of dome metals(200). First location arranging protrusions(110) are protruded upward the work panel. A first tape(310) is separated from the lower surface of a first film(300). A second tape(320) is separated from the lower surface of a second film. COPYRIGHT KIPO 2011 ...

FLEXIBLE COPPER CLAD LAMINATE CAPABLE OF PREVENTING OPEN/SHORT CIRCUIT AND METHOD FOR MANUFACTURING SAME

Disclosed is a flexible copper-clad laminate capable of preventing open and/or short circuit by ensuring uniform chemical polishing, and a method for manufacturing the same. The flexible copper clad laminate of the present invention comprises a nonconductive polymer substrate, a tiecoat layer on the nonconductive polymer substrate, and a copper layer on the tiecoat layer. When performing the chemical polishing to reduce the thickness of the copper layer by 1 to 2 μm, the polished copper layer has surface roughness (Rz) of 0.1 to 0.15 μm and ND direction average grain of 2 μm or less. COPYRIGHT KIPO 2018 ...

CIRCUIT BOARD, CIRCUIT BOARD MANUFACTURING METHOD, AND ELECTRONIC DEVICE THEREOF

The present invention provides a circuit board having short manufacturing processes and obtaining a uniform thickness. A method for manufacturing the circuit board of the present invention comprises the steps of: adhering a plastic-deformative insulation material on a surface on which a first metal layer is formed, of a second metal layer and on the first metal layer, in a laminate having the second metal layer formed with a second metal and the first metal layer formed in a pattern shape on the second metal layer and having a metal at least different from the second metal; hardening the insulation material; forming a plate-shape structure on which the first metal layer in a pattern shape is formed, by removing the second metal layer; making a hole reaching the first metal layer on the hardened insulation material from the surface having the first metal layer formed thereon and the opposite surface of the plate-shape structure; charging the hole with conductive paste and forming the plate-shape ...

Method of forming an electronic device on a substrate supported by a carrier and resultant device

A method for forming an electronic device on a flexible substrate conditions the surface of a carrier to form a holding area for retaining the flexible substrate. A contact surface of the flexible substrate is applied against the carrier with an intermediate binding material applied between at least the holding area of the carrier and the corresponding area of the contact surface. Entrapped gas between the flexible substrate and the carrier is removed and the substrate processed to form the electronic device thereon. The substrate can then be removed from the holding area to yield the resultant electronic device.

Method of preparing a flexible substrate assembly and flexible substrate assembly therefrom

Some embodiments teach a method of preparing a flexible substrate assembly. The method can include: (a) providing a carrier substrate; (b) providing a cross-linking adhesive; (c) providing a plastic substrate; and (d) coupling the carrier substrate to the plastic substrate using the cross-linking adhesive. Other embodiments are disclosed in this application.

Method of filling vias with ink

A method for selective processing of a panel, the method may include receiving a panel that has a bottom side and a top side and comprises a first group of drilled holes and a second group of drilled holes; at least partially sealing a bottom of any through hole of the first group; filling, by a selective filing process, any drilled hole of the first group that has a top opening to provide at least partially filled drilled holes of the first group without filling the second group of drilled holes; and plugging, by a selective plugging process, a top of any drilled hole of the first group.

Component embedded package carrier and manufacturing method thereof

ASSEMBLIES AND METHODS FOR REDUCING WARP AND BOW OF A FLEXIBLE SUBSTRATE DURING SEMICONDUCTOR PROCESSING

ASSEMBLIES AND METHODS FOR REDUCING WARP AND BOW OF A FLEXIBLE SUBSTRATE DURING SEMICONDUCTOR PROCESSINGMethods are described for addressing the bowing and/or warping of flexible substrates, attached to a rigid carrier, which occurs as a result of the thermal challenges of semiconductor processing. In particular, viscoelastic adhesives are provided which can bond a flexible substrate to a rigid carrier and mediate the thermal mismatch which often is present due to the distinctly different materials properties of most flexible substrates, such as plastic films, with respect to rigid carriers, such as silicon wafers. Assemblies are also provided which are produced according to the methods described herein.Figure for publication: None ...

Stretchable flexible printed circuit (fpc) and fabricating method thereof

Substrate structure and fabrication method thereof

METHOD FOR PRODUCING A FLEXIBLE CIRCUIT CONFIGURATION

For a method for producing a flexible circuit configuration in the form of a layer sequence of at least one insulating layer and at least one conductive layer, typically multiple insulating layers (N1, N2, N3, NF) and multiple structured conductive layers (L1, L2), the layer sequence for the flexible circuit configuration is deposited on a rigid substrate so that the adhesion of the layer sequence with respect to the substrate is less in an inner area, in which at least one, preferably multiple flexible circuit configurations are created, than in an edge area (RB) which surrounds the inner area (ZB). An intermediate layer can advantageously be deposited for this purpose in the edge area, which causes a stronger adhesion of the layer sequence over the edge area than the inner area, which is not provided with an intermediate layer.

POLYMER LAYER COMPRISING SILICONE AND AT LEAST ONE METAL TRACE AND A PROCESS OF MANUFACTURING THE SAME

The present invention relates to a process for embedding at least one layer of at least one metal trace in a silicone containing polymer, comprising: a) applying a non adhering on a substrate; b) applying a polymer layer on the non adhering agent; c) irradiation at least one surface area of said polymer with a light beam emitted by an excimer laser; d) immersing said irradiated polymer in at least one autocatalytic bath containing metal ions of at least one metal and metallizing the polymer; e) thermally treating said metallized polymer; f) applying a polymer layer on said thermally treated metallized polymer; and g) thermally treating said metallized polymer.

Electronic component with metal plate above element and fabrication method of the same, and electronic device including the same

An electronic component includes: an element that is located on a substrate; a signal wiring that is located on the substrate and electrically connected to the element; a metal plate that is located so as to form a cavity on a functional part of the element and covers an upper surface of the cavity; a support post that is located on the substrate so as not to be located on the signal wiring, and supports the metal plate; and an insulating portion that covers the metal plate and the support post, and contacts a side surface of the cavity.

Method for manufacturing wiring board

A method for manufacturing a wiring board, comprising the steps of: forming a first electrode layer having first and second opening portions, forming a dielectric layer formed on the first electrode layer and having third and fourth opening portions, forming a second electrode layer formed on the dielectric layer and having fifth and sixth opening portions, wherein the first electrode layer, the dielectric layer, and the second electrode layer form a capacitor; forming an insulating layer inside a first opening defined by the first, third, and fifth opening portions, and a second opening defined by the second, fourth, and sixth opening portions; using a laser beam having a processing diameter to form first and second via holes extending through the insulating layer formed inside the first and second openings, respectively; and forming first and second via wiring portions in the first and second via holes, respectively.

Substrate carrier jig and method of producing liquid crystal display element by using the substrate carrier jig

A substrate carrier jig is a jig which supports a substrate of a liquid crystal display element on its surface and carries the substrate with the jig to a process. A sticky layer whose adhesion for holding the substrate to be stuck to the surface of the jig is maintained constant even after repeated use. The substrate composed of a thin sheet glass, plastic, etc. is stuck to the jig, and the substrate when the jig is carried to a process for producing a liquid crystal display element. As a result, it is possible to produce a liquid crystal display element by commonly using a producing line for a conventional liquid crystal display element for glass even if substrate materials such as thin sheet glass, plastic, etc. which independently have no strength and stiffness are used. Furthermore, since the jig can be repeatedly used, the cost of producing a liquid crystal display element can be greatly reduced as compared to a disposable jig. Also a method of producing the carrier jig is provided ...

Multilayered substrate for semiconductor device

A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Co-Fired Passive Integrated Circuit Devices

Co-fired integrated circuit devices and methods for fabricating and integrating such on a workpiece are disclosed herein. An exemplary method includes forming a first passive device and a second passive device over a carrier substrate. The first passive device and the second passive device each include at least one material layer that includes a co-fired ceramic material. The carrier substrate is removed after performing a co-firing process to cause chemical changes in the co-fired ceramic material. The first passive device may include a conductive loop disposed between a first magnetic layer and a second magnetic layer. The first magnetic layer, the second magnetic layer, or both includes a co-fired ceramic magnetic material. The second passive device may include a first conductive layer and a second conductive layer separated by a dielectric layer. The first conductive layer, the second conductive layer, or both includes a co-fired ceramic conductive material. 1. A device comprising:a first wafer including a first passive device and a second passive device, wherein the first passive device is different than the second passive device, the first passive device is disposed laterally adjacent to the second passive device, and the first passive device and the second passive device each include at least one layer that includes a co-fired ceramic material; anda second wafer attached to the first wafer, wherein a circuit element of the second wafer is connected to the first passive device and the second passive device.2. The device of claim 1 , wherein:the first passive device includes a conductive loop disposed between a first magnetic layer and a second magnetic layer, wherein the first magnetic layer, the second magnetic layer, or both includes a co-fired ceramic magnetic material; andthe second passive device includes a first conductive layer and a second conductive layer separated by a dielectric layer, wherein the first conductive layer, the second conductive layer, ...

Surface treated copper foil, copper foil with carrier, laminate, method for manufacturing printed wiring board, and method for manufacturing electronic device

Also disclosed is a surface treated copper foil, comprising a copper foil, and a surface treatment layer on one or both sides of the copper foil, wherein the surface treatment layer has a primary particle layer, or has a primary particle layer and s secondary particle layer in this order from the side of the copper foil; the surface treatment layer contains Zn, a deposition amount of Zn in the surface treatment layer is 150 μg/dm2 or more; the surface treatment layer does not contain Ni, or in the case where the surface treatment layer contains Ni, a deposition amount of Ni in the surface treatment layer is 800 μg/dm2 or less; the surface treatment layer does not contain Co, or in the case where the surface treatment layer contains Co, a deposition amount of Co in the surface treatment layer is 3000 μg/dm2 or less; and a ten point average roughness Rz of an outermost surface of the surface treatment layer is 1.5 μm or less.

DISPLAY DEVICE

A display device includes a flexible insulating substrate, an insulating layer on the insulating substrate, and a plurality of terminals made of a conductive material on the insulating layer. The insulating layer is disposed outside the area located between the terminals. The insulating substrate has a groove between the terminals.

Electronic system modules and method of fabrication

This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables. Module packaging layers are ...

High frequency circuit block unit, method for producing same, high frequency module device and method for producing same

A high frequency module device having a high frequency circuit block unit including a passive device. A plural number of unit wiring layers, each formed by an insulating layer, having a passive device unit in its portion, and by a pattern wiring, are layered on a dummy substrate, and are released from the dummy substrate to form the high frequency circuit block unit (2), which is mounted on a motherboard (3). The major surfaces of the respective unit wiring layers are planarized. The passive device unit and the pattern wiring, formed on the major surface of each unit wiring layer in the high frequency circuit block unit (2), can be formed with high accuracy to improve high frequency characteristics. The high frequency circuit block unit (2) is not in need of a base substrate, thus achieves reduction in size and cost.

ELECTRONIC DEVICE MODULE

An electronic device module adapted to be removably attached by a heat-resistant tape includes a substrate, a waterproof enclosure and an electronic device. The substrate has a front surface and a rear surface that is opposite to the front surface. The waterproof enclosure is disposed on the rear surface of the substrate to form a closed path and is adapted to be attached by the heat-resistant tape so as to be interposed between the rear surface and the heat-resistant tape. The electronic device is formed on the front surface of the substrate.

SUBSTRATE STRUCTURES APPLIED IN FLEXIBLE ELECTRICAL DEVICES AND FABRICATION METHOD THEREOF

A substrate structure applied in flexible electrical devices is provided. The substrate structure includes a carrier, a release layer overlying the carrier with a first area and a flexible substrate overlying the release layer and the carrier with a second area, wherein the second area is larger than the first area and the flexible substrate has a greater adhesion force than that of the release layer to the carrier. The invention also provides a method for fabricating the substrate structure.

MICROFLUIDIC CHANNEL DETECTION SYSTEM

A microfluidic channel detection system for environmental or biomedical detection includes a chip having a first surface where a sensing region is located, a substrate having a recess for containing the chip, in which the first surface is exposed, a first inactive layer filling gaps between the chip and the substrate in the recess, so as to form a plane with the first surface of the chip, an electrical connection member electrically connected to the chip, a cover having a microfluidic channel and disposed on the plane. The flow path in the microfluidic channel is smooth, and further the measurement accuracy is improved via the plane formed by the first inactive layer and the first surface.

CIRCUIT BOARD AND METHOD OF MAKING CIRCUIT BOARD

A circuit board includes a first conductive circuit layer, a cover layer, and a second conductive circuit layer. The cover layer includes an adhesive layer and a base film. The first conductive circuit layer is embedded within the adhesive layer. One side of the first conductive circuit layer is revealed from the adhesive layer. The second conductive circuit layer is located on a side of the base film facing away from the adhesive layer. The cover layer defines a first through hole and a second through hole passing through the cover layer. A diameter of the first through hole is greater than a diameter of the second through hole. The first through hole is filled with a copper post adjacent to the first conductive circuit layer and an electroplating layer adjacent to the second conductive circuit layer. The second through hole is filled with the electroplating layer.

Producing method of flexible wired circuit board

A producing method of a flexible wired circuit board that can prevent the formation of a gap between an elongate substrate and a stiffener sheet bonded thereto to prevent contamination of the flexible wired circuit board obtained. In the process subsequent to the process of forming a conductive pattern 3 on a surface of the elongate substrate 1 by the semi-additive process using electrolysis plating and then annealing the elongate substrate 1 with the conductive pattern 3 in its wound up state, a stiffener sheet 9 having a width narrower than the elongate substrate 1 is bonded to the back side of the elongate substrate 1. Thereafter, an oxidized film formed on a surface of the conductive pattern 3 is removed and then a solder resist 11 is formed thereon. This prevents the strip of the stiffener sheet 9 from the elongate substrate 1 and in turn prevents etching solution or developing solution from entraining in a gap therebetween.

Method for collective production of 3D electronic modules comprising only valid PCBs

Method for securing and processing thin film materials

To secure a thin film (10) to a rigid carrier (11) for subsequent exposure to processing chemicals, the thin film (10) is initially adhered to the rigid carrier (11) with a light adhesive (12) from which the thin film (10) may later be peeled. Then a photoresist (17) is applied over the thin film (10) extending over a peripheral region (15) of the carrier (11) along the perimeter of the thin film (10). The photoresist (17) is exposed to actinic radiation in a pattern such that when the photoresist (17) is subsequently developed, a perimeter region (17b) of the photoresist (17) remains over the perimeter region (15) of the carrier (11) and extending inward over the periphery of the thin film (10) sufficiently to secure the thin film (10) during conveyorized chemical processing. Finally the resist is stripped to release the thin film (10) and the thin film peeled from the adhesive pattern (12).

WIRING SUBSTRATE FOR MOUNTING SEMICONDUCTOR, ITS MANUFACTURING METHOD, AND SEMICONDUCTOR PACKAGE

PROBLEM TO BE SOLVED: To provide a wiring substrate for mounting a semiconductor which is effective in the increase of terminal and close narrowness of space between terminals due to the high integration, high speedup, and multi-functionalization of a semiconductor device, and which can particularly mount semiconductors on both sides of the substrate in high density and with high accuracy, and which is excellent in reliability too; to provide its manufacturing method; and to provide a semiconductor package. SOLUTION: The wiring substrate 5 for mounting a semiconductor is composed of at least an insulating film 1, wiring 2 formed in the insulating film 1, and a plurality of electrode pads 4 connected with the wiring 2 and a via 3. The electrode pad 4 is located on both sides of the surface/back with the surface exposed, and at least a part of side of the electrode pad is buried in the insulating film 1. After the electrode pads 4 are formed on the two sheets of metal plate and then the insulating ...

ELASTISCH VERFORMBARE INTEGRIERTE SCHALTUNG

HERSTELLUNG VON GEDRUCKTEN SCHALTUNGEN.

Electronic biometric devices and methods of construction

Flexible supercapacitors and manufacture thereof

ELECTRICAL D�NNSCHICHT ELEMENT WITH POLYMER SUBSTRATE

A method of manufacturing a printed circuit board and a printed circuit board

Ein Verfahren zum Herstellen einer Leiterplatte (10) mit zumindest einem eingebetteten Sensorchip (3), bei welchem zumindest eine Sensorfläche (5) und Anschlüsse (4) auf einer Fläche des Chips angeordnet sind, die folgenden Schritte aufweisend: a) Bereitstellen einer Klebefolie (1), b) Aufdrucken einer Leiterstruktur (2) aus einer leitfähigen Paste auf eine Oberfläche der Klebefolie, c) registriertes Aufsetzen des zumindest einen Sensorchips (3) mit der die zumindest eine Sensorfläche (5) und die Anschlüsse (4) aufweisenden Fläche auf die Leiterstruktur (2) aus einer leitfähigen Paste, d) Aushärten der leitfähigen Paste, e) Aufbringen einer Isolierschicht (6) mit einer darüber liegenden Leiterschicht (7) auf die den Chip (3) aufweisende Oberfläche des in den vorgehenden Schritten geschaffenen Aufbaus, f) Laminieren des in den vorgehenden Schritten geschaffenen Aufbaus, g) Strukturieren der Leiterschicht (7) und Bilden von Durchkontaktierungen (9) von der Leiterschicht zu Leiterbahnen (7b ...

FLEXIBLY DUCTILE ONE INTEGRATED CIRCUIT

Additive electronic circuits on thermally unstable substrates

THIN FILM ELECTRICAL COMPONENT

MANUFACTURE OF ELECTRICAL CIRCUITS

FLEXIBLE, HERMETIC ELECTRICAL INTERCONNECT FOR ELECTRONIC AND OPTOELECTRONIC DEVICES FOR IN VIVO USE

An electronic device can comprise a first electronic module; a second electronic module; and a hermetic electric interconnect to hermetically couple them, The hermetic electric interconnect can comprise a bottom metal layer; a bottom insulating layer, deposited on the bottom metal layer to insulate the bottom metal layer; an interconnect metal layer, deposited on the bottom insulating layer, and deposited to form a bottom sealing ring; and patterned to form electrical connections between contact pads, and to form a middle sealing ring: a patterned top insulating layer, deposited on the interconnect metal layer to insulate the interconnect metal layer; and patterned to form feedthrough holes; and a top metal layer, deposited on the top insulating layer to start forming contacts by filling the feedthrough holes; and patterned to complete forming contacts through the feedthrough holes, to form a separate barrier layer, and to complete forming the top sealing ring.

METHOD FOR MANUFACTURING POLYIMIDE MULTILAYER WIRING SUBSTRATE

Substrate structure and fabrication method thereof

SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING THE SAME, LIQUID CRYSTAL MODULE AND PROCESS FOR MOUNTING THE SAME

METHOD FOR MANUFACTURING ELECTRONIC DEVICE AND SEPARATION APPARATUS USED THEREFOR

A printed circuit board and a fabricating method the same

Carrier tape for loading flexible printed circuits

RELEASE PROCESS FILM

프린트 배선판용 수지 조성물, 프리프레그, 수지 복합 시트 및 금속박 피복 적층판

... 내열성, 난연성을 가질 뿐만 아니라, 흡습 내열성도 우수한 프린트 배선판을 실현할 수 있는 수지 조성물의 제공을 목적으로 한다. 당해 수지 조성물은, 나프톨-디하이드록시나프탈렌아르알킬 수지 또는 디하이드록시나프탈렌아르알킬 수지를 시아네이트화하여 얻어지는 시안산에스테르 화합물 (A) 와 에폭시 수지 (B) 를 함유하는 프린트 배선판용 수지 조성물이다.

기판의 표면에서 밀리미터, 마이크로미터 또는 나노미터 구조물을 처리하기 위한 방법

... 본 발명은 밀리미터 및/또는 나노미터 구조물을 가진 기판을 처리하기 위한 방법에 관한 것이다.

액체 유리의 응용

... 도전성 기둥들을 갖는 기판, 회로를 내장한 기판 및 유리 막을 준비하기 위하여 액체 유리를 사용하는, 액체 유리 응용이 제공된다. 상기 액체 유리는 다수의 사용 편리 특성을 보유한다. 따라서, 준비 비용(preparation cost)을 크게 줄일 수 있다. 게다가, 전통적인 유리 형상 한계를 깨고 유리 두께를 현저하게 줄일 수 있으며, 그로 인하여 오늘날 전자 제품에 대한 경박단소의 요구를 만족시킨다.

적층체의 제조 방법

... 내열성(예를 들어, 땜납 내열성)이 우수하고, 소직경의 비아 홀을 형성 가능한 적층체를 제조하기 위한 방법을 제공하는 것이다. 지지체 위에, 열경화성 수지 조성물을 포함하는 경화성 수지 조성물층을 형성함으로써, 지지체 부착 경화성 수지 조성물층을 얻는 공정과, 상기 지지체 부착 경화성 수지 조성물층을, 경화성 수지 조성물층 형성면측에서, 기재에 적층시킴으로써, 기재와, 지지체 부착 경화성 수지 조성물층을 포함하는 지지체 부착 경화 전 복합체를 얻는 공정과, 상기 복합체에 대하여 제1 가열을 행하여, 상기 경화성 수지 조성물층을 열경화시킴으로써, 경화 수지층으로 함으로써, 기재와, 지지체 부착 경화 수지층을 포함하는 지지체 부착 경화 복합체를 얻는 공정과, 상기 지지체 부착 경화 복합체의 상기 지지체측으로부터 천공을 행함으로써, 상기 경화 수지층에 비아 홀을 형성하는 공정과, 상기 지지체 부착 경화 복합체로부터 상기 지지체를 박리함으로써, 기재 및 경화 수지층을 포함하는 경화 복합체를 얻는 공정과, 상기 경화 복합체에 대하여 제2 가열을 행하는 공정과, 상기 경화 복합체의 비아 홀 내의 수지 잔사를 제거하는 공정과, 상기 경화 복합체의 비아 홀 내벽면, 및, 상기 경화 수지층 위에, 도체층을 형성하는 공정을 갖고, 상기 비아 홀에 대한 도체층의 형성을, 무전해 도금, 또는, 무전해 도금과 전해 도금의 조합에 의해 행하는 것을 특징으로 하는 적층체의 제조 방법을 제공한다.

ADHESIVE SHEET

An adhesive sheet comprising a base material and an adhesive layer formed on at least one surface of the base material, wherein an adhesive agent contained in the adhesive layer comprises an acrylate ester copolymer and a citrate plasticizer, the acrylate ester copolymer has a glass transition temperature of-45°C or lower, the citrate plasticizer is contained in an amount of 1.0 to 50.0 parts by mass (solid content) relative to 100 parts by mass (solid content) of the acrylate ester copolymer, and the gel fraction of the adhesive agent in the adhesive layer is 70% or greater. The adhesive sheet has a slightly-adhesive property and a repeelable property, and therefore can be suitably used as a process sheet or the like. © KIPO & WIPO 2009 ...

Polyimide precursor aqueous solution composition and method for producing the same

This invention relates to polyimide precursor aqueous solution composition that is produced by dissolving polyamic acid, obtained by the reaction of a tetracarboxylic acid component with a diamine component, in aqueous solvent, along with imidazoles of 1.6 fold or more moles to the tetracarboxylic acid component in the polyamic acid.

Process for producing layered product, layered product, process for producing layered product with device using said layered product, and layered product with device

Provided is a backing-supported layered polyimide which has a smooth surface to enable a sophisticated device to be formed thereon and in which the layered polyimide does not readily peel off even in a high-temperature process for device formation and can be easily separated from the backing after the device formation on the layered polyimide. A polyimide film is used in which the surface that is to face a backing has undergone a surface treatment. At least either of the surfaces of the backing and polyimide film which are to face each other is patterned using a coupling agent to form a satisfactorily bondable part and an easily releasable part which differ in adhesion/peel strength. Thereafter, the backing and the polyimide film are superposed and laminated by pressing and heating. The surface of the polyimide film is treated with an organic alkali, and subsequently a polyamic acid solution containing no lubricant ingredient is applied and then dried and imidized. Thus, a layered product ...

Manufacturing method for circuit wiring board

A manufacturing method for a circuit wiring board includes the steps of: forming (S1) a polyimide precursor resin layer containing a precursor of polyimide resin; impregnating (S2) the polyimide precursor resin layer with metal ions; forming (S3) a resist mask into a pattern on the surface of the polyimide precursor resin layer; forming (S4) a metal deposition layer by reducing metal ions present in the polyimide precursor resin layer; forming (S5) circuit wiring having a pattern by plating on the metal deposition layer; and forming (S6) a polyimide resin layer by imidizing the polyimide precursor resin layer by heat treatment.

Method of manufacturing a wiring substrate

The object of the present invention is to provide a method of manufacturing a wiring substrate wherein the wiring substrate comprises a lamination structure where at least one layer of a conductor layer and at least one resin insulation layer are alternately laminated on two sides of a core substrate is provided, and the wiring substrate can be thinned without reduction of the yield rate thereof. A method of manufacturing a wiring substrate of the present invention comprises: a step of forming a first lamination structure where at least one layer of a conductor layer and at least one layer of a resin insulation layer are alternately laminated on a support substrate; a step of forming a metal core substrate, which is provided with a metallic layer on a main surface, in such a manner that a lower main surface of the metal core substrate is in contact with the first lamination structure; and a step of forming a second lamination structure, where at least one layer of a conductor layer and ...

POLYMER LAYER COMPRISING SILICONE AND AT LEAST ONE METAL TRACE AND A PROCESS OF MANUFACTURING THE SAME

The present invention relates to a process for embedding at least one layer of at least one metal trace in a silicone containing polymer, comprising: a) applying a non adhering on a substrate; b) applying a polymer layer on the non adhering agent; c) irradiation at least one surface area of said polymer with a light beam emitted by an excimer laser; d) immersing said irradiated polymer in at least one autocatalytic bath containing metal ions of at least one metal and metallizing the polymer; e) thermally treating said metallized polymer; f) applying a polymer layer on said thermally treated metallized polymer; and g) thermally treating said metallized polymer.

DEPOSITING BULK OR MICRO-SCALE ELECTRODES

Thicker electrodes are provided on microelectronic device using thermo-compression bonding. A thin-film electrical conducting layer forms electrical conduits and bulk depositing provides an electrode layer on the thin-film electrical conducting layer. An insulating polymer layer encapsulates the electrically thin-film electrical conducting layer and the electrode layer. Some of the insulating layer is removed to expose the electrode layer.

PARYLENE-BASED FLEXIBLE MULTI-ELECTRODE ARRAYS FOR NEURONAL STIMULATION AND RECORDING AND METHODS FOR MANUFACTURING THE SAME

Method for manufacturing a parylene-based electrode array that includes an underlying parylene layer, one or more patterned electrode layers comprising a conductive material such as a metal, and one or more overlying parylene layers. The overlying parylene is etched away or otherwise processed to expose the electrodes where stimulation or recording is to occur. All other conductive material in the device is occluded from the environment by the two layers of parylene surrounding it.

MULTILAYER SUBSTRATE AND FABRICATING METHOD THEREOF

A multilayer substrate and fabricating method thereof are provided. The multilayer substrate comprises: a number of dielectric layers (602, 606) and a number of metal wiring layers (604), these dielectric layers and these metal wiring layers laminated alternately, these metal layers sticking to each other, such that these metal wiring layers are embedded in the corresponding dielectric layer, respectively. The dielectric layers are formed by coating. The method can improve quality and yield of the substrate, reduce crosstalk, remain the integrality of the signal, and reduce the cost.

METHODS OF FIXTURING FLEXIBLE CIRCUIT SUBSTRATES AND A PROCESSING CARRIER, AND PROCESSING A FLEXIBLE CIRCUIT

Methods of fixturing a flexible circuit substrate (20) to a processing carrier (60) are disclosed. In one implementation, the flexible circuit substrate (20) and processing carrier (60) are attached with an adhesive film (40) provided therebetween. The adhesive film (40) comprises acrylic, silicone or a silicone acrylic blend in a preferred embodiment of the present invention. Ideally, substantially the total surface area of a first surface (22) of the flexible circuit substrate (20) is attached to the processing carrier (60). The flexible circuit substrate (20) is removed from the adhesive film (40) following processing thereof. In a preferred embodiment of the present invention, the adhesive film (40) is monolithic. An electrical component (36) is attached to the flexible circuit substrate (20) and the flexible circuit substrate (20) is encapsulated in accordance with one implementation of the present invention.

MANUFACTURE OF ELECTRICAL CIRCUITS

A method of providing an electrical circuit on a surface of a three-dimensionally shaped substrate of insulating plastics material comprising providing a carrier film (33) of insulating plastics material with a circuit pattern (31) of electro-conductive or electro-resistive, heat-resistant synthetic resin applied to at least one face (32); supporting a face of the carrier; forming a carrier into a given three-dimensional shape; and, moulding, by the application of heat and pressure in a mould cavity (38), a substrate (34) of insulating plastics material against the unsupported face of the carrier; so that the circuit is embedded in or within a three-dimensional surface of the moulded substrate.

TECHNIQUE FOR REDUCING WASTED MATERIAL ON A PRINTED CIRCUIT BOARD PANEL

A process for assembling a rigid-flex printed circuit board (PCB) is presented. During operation, the process receives rigid-flex PCBs that are to be coupled together, wherein a rigid-flex PCB includes flexible PCBs coupled to rigid PCBs. The process then places the PCBs onto a carrier which is configured to: align the PCBs so that bond regions located on the flexible PCBs overlap with bond regions located on corresponding flexible PCBs, and apply pressure to the overlapped bond regions. The process then sends the carrier through a reflow oven which reflows solder on the PCBs so that the components become mechanically and electrically coupled to the PCBs. The temperature profile generated by the reflow oven and the pressure applied by the carrier cures and sets an anisotropic conductive film located in the bond regions so that the overlapped flexible PCBs become mechanically and electrically coupled together.

Monitoring dry-etching of polymer layer for transferring semiconductor devices

Embodiments relate to placing light emitting diodes from a carrier substrate to a target substrate. At least one LED is embedded in a polymer layer on a substrate. The polymer layer is etched between the at least one LED and the substrate. A thickness of the polymer layer is monitored during etching of the polymer layer. The etching of the polymer layer is terminated responsive to determining that the thickness of the polymer layer is in a target range or a target value. A pick-up-tool (PUT) is brought into contact with at least one surface of the at least one LED facing away from the substrate responsive to dry-etching the polymer layer, and the PUT is lifted with the at least one LED attached to the PUT.

Aromatic Polyester Film

A film containing an aromatic polyester with aromatic biphenyl repeating units having the following general Formula I: is provided. The film is annealed and exhibits a relatively isotropic tensile property.

FABRICATION METHOD OF FLEXIBLE ELECTRONIC DEVICE

A fabrication method of a flexible electronic device is provided. A flexible substrate is placed directly on a rigid substrate. A portion of an edge of the flexible substrate is heated, such that the heated portion of the edge of the flexible substrate constitutes a melted edge. An electronic element is formed on the flexible substrate and located in an area region surrounded by the melted edge. A separation process is performed, such that the melted edge is separated from the flexible substrate to form a flexible electronic device.

Polyimide multilayer wiring board and method of producing same

A polyimide multilayer wiring board is constructed by using a plurality of laminated blocks each of which has a plurality of wiring layers and interlaminar insulating layers of polyimide. On a base block having a substrate, the other blocks are laid on top of another, bonded to each other with a polyimide used in each block or another adhesive and electrically connected to each other by using, for example, metal bumps formed on each block. Each of the blocks except the base block is formed on a temporary substrate, and the temporary substrate is removed after bonding each block to the base block or precedingly bonded blocks. This multilayer wiring board can be produced in a shortened time with increased yield.

Circuit board construction

A method of forming a circuit board includes, a) providing a temporary substrate; b) depositing an uncured electrically insulative circuit board material over the temporary substrate, the circuit board material adhering to the temporary substrate; c) substantially curing the uncured circuit board material into at least one self supporting sheet; d) providing circuit traces atop the cured self supporting sheet; e) mounting an electronic circuit component atop the cured self supporting sheet in electrical communication with the circuit traces; and f) peeling the temporary substrate and cured self supporting sheet from one another. An electronic circuit of the invention includes, i) a self-supporting electrically insulative ink or paint substrate, the ink or paint substrate having an outer surface; ii) circuit traces provided on the ink or paint substrate outer surface; and iii) at least one electronic circuit component mounted to the ink or paint substrate outer surface in electrical connection ...

Manufacturing method of double layer circuit board

A manufacturing method of a double layer circuit board comprises forming a connecting pillar on a first circuit, wherein the connecting pillar comprises a first end, connected to the first circuit, and a second end, opposite to the first end; forming a substrate on the first circuit and the connecting pillar; drilling the substrate to expose a portion of the second end of the connecting pillar, wherein the other portion of the second end of the connecting pillar is covered by the substrate; and forming a second circuit on the substrate and the portion of the second end of the connecting pillar, wherein an area of the first end connected to the first circuit layer is greater than an area of the portion of the second end connected to the second circuit layer.

METHOD FOR MANUFACTURING FLEXIBLE CIRCUIT BOARD

A method for manufacturing a flexible circuit board is provided. The method for manufacturing a flexible circuit board includes the following steps: providing a carrier substrate, forming a flexible substrate on the carrier substrate, and forming a plurality of circuit strings on the flexible substrate. A flexible circuit board manufactured by the above method is also provided.

Method of surface-mounting components

A method of connecting a plurality of electronic components to a flexible circuit board comprises: providing a carrier substrate carrying the electronic components, each of the electronic components having at least one electrical contact coated with electrically conductive adhesive; and applying the carrier substrate to the flexible circuit board such that the electronic components are adhered to the flexible circuit board in electrical contact therewith via the conductive adhesive. The electronic components may comprise LEDs and there may be provided one or more optical layers over the flexible circuit board.

A substrate having high electrical connection reliability of a penetrating via connected to wirings and a method for manufacturing the same

A disclosed substrate (50) is composed of a base member (51) having a through-hole (52), a penetrating via (54) provided in the through-hole, and a wiring (68) connected to the penetrating via. The penetrating via includes a penetrating part (55) having two ends on both sides of the base member, which is provided in the through-hole, a first protrusion (56) protruding from the base member, which is formed on a first end of the penetrating part so as to be connected to the wiring, and a second protrusion protruding (57) from the base member, which is formed on a second end of the penetrating part. The first protrusion and second protrusion are wider than a diameter (R1) of the through-hole.

Double-sided pressure-sensitive adhesive tape or sheet for wiring circuit board and wiring circuit board

The present invention relates to a double-sided pressure-sensitive adhesive tape or sheet for wiring circuit board, which comprises a pressure-sensitive adhesive layer formed by a pressure-sensitive adhesive composition containing an acrylic polymer and a chain transfer substance, in which the pressure-sensitive adhesive layer has characteristics that a gel fraction in the initial stage is from 40 to 70% by weight, and a difference between a gel fraction (% by weight) of the pressure-sensitive adhesive layer after the following solder reflow step and the gel fraction (% by weight) of the pressure-sensitive adhesive layer in the initial stage is 10 or less. The solder reflow step satisfies the following heat treatment conditions. Surface temperature of the double-sided pressure-sensitive adhesive tape or sheet reaches 175 ± 10°C within 130 to 180 seconds, the surface temperature reaches 230 ± 10°C within 200 to 250 seconds, the surface temperature reaches 255 ± 15°C within 260 to 300 seconds ...

Method for manufacturing polyimide multilayer wiring substrate

A layered structure comprising wiring layers and polyimide layers is formed on a ceramics board and a layered structure comprising wiring layers and polyimide layers is formed on an aluminum board. Both the structures are bonded together through adhesives to bring metal bumps formed on the former structure into electric contact with metal bumps formed on the surface of the latter structure and thereafter the aluminum board is removed. ...

Structure and process for thin film interconnect

СТРУКТУРА НА ОСНОВЕ ГИБКИХ ТОКОПРОВОДЯЩИХ ДОРОЖЕК И СПОСОБ ЕЕ ИЗГОТОВЛЕНИЯ

Группа изобретений относится к медицинской технике. Описана структура на основе гибких токопроводящих дорожек, обладающая заранее изогнутым состоянием, причем структура в основном плоская. Токопроводящие дорожки сформированы из слоя металла, и они покрыты сверху и снизу слоями изолятора. Удлиненные токопроводящие дорожки являются в основном плоскими, но локально образуют гофрирование перпендикулярно основной плоскости. Это позволяет улучшить характеристики скрепления, например, для формирования тугой намотки с использованием токопроводящих дорожек. 3 н. и 13 з.п. ф-лы, 9 ил.

СПОСОБЫ ПЕРЕНОСА ЭЛЕКТРОПРОВОДЯЩИХ МАТЕРИАЛОВ

Electronic Biometric Devices and Methods of Construction

Improvements in or relating to the manufacture of flexible printed circuits

A method of manufacturing a flexible printed circuit board comprising bonding, by means of a thermoplastic adhesive film, a sheet of flexible substrate material to a rigid base board of for example fibre glass, prior to processing the sheet to form a printed circuit. The flexible printed circuit board is then removed from the base board by peeling. ...

Flexible supercapacitors and manufacture thereof

PROCEDURE FOR THE ATTACHMENT AND TREATMENT OF THIN SECTION MATERIALS

PROCEDURE AND DEVICE FOR THE PRODUCTION OF A ROLE OF ARTICLES

Flexible circuit structure with stretchability and method of manufacturing the same

In one example embodiment, a flexible circuit structure with stretchability is provided that includes a flexible substrate, a plurality of flexible bumps formed on the flexible substrate, and a metal layer formed on the plurality of flexible bumps and the flexible substrate.

system and a method for solder mask inspection

A system and a method for method for printing a solder mask on a printed circuit board (PCB), the method includes: acquiring images of multiple areas of a PCB by an inspection unit while the PCB is supported by a mechanical stage; determining spatial differences between a model of the PCB and the PCB based on the images; determining solder mask ink deposition locations based on (i) the spatial differences, and (ii) locations of the model of the PCB that should be coated with the solder mask ink; and printing solder mask ink on the solder mask deposition locations by a printing unit, while the PCB is supported by the mechanical stage.

Wet lamination of photopolymerizable dry films onto substrates and compositions relating thereto

The invention is directed to a lamination fluid useful in processes for wet laminating a photopolymerizable film onto circuit board panels or other substrates. The lamination system comprises 1) a dry film photoresist, 2) a laminate comprising i) copper ii) stainless steel iii) non metal on a surface, 3) a lamination fluid and 4) fluid application device on the laminates. The lamination fluid comprises water and a surface energy modification agent. The surface energy modification agent is present in a range between 0.0001 and 3.0 moles/liter, and the pH of the fluid is between 3 and 11.

METHOD OF FABRICATING A WIRING BOARD

A method of fabricating a wiring board includes forming a surface plating layer on a support member, and forming an external connecting pad on the surface plating layer formed on the support member such that an area of the external connecting pad formed on the surface plating layer is smaller than an area of the surface plating layer. The method also includes forming an insulating layer and a wiring layer on a surface of the support member where the external connecting pad is formed, and removing the support member. 1. A method of fabricating a wiring board , comprising steps of:forming a surface plating layer on a support member, and forming an external connecting pad on the surface plating layer formed on the support member such that an area of the external connecting pad formed on the surface plating layer is smaller than an area of the surface plating layer;forming an insulating layer and a wiring layer on a surface of the support member where the external connecting pad is formed; andremoving the support member.2. The method of fabricating a wiring board according to claim 1 , wherein forming the external connecting pad on the surface plating layer such that the area of the external connecting pad formed on the surface plating layer is smaller than the area of the surface plating layer includes processing the external connecting pad to make the area of the external connecting pad smaller than the area of the surface plating layer.3. The method of fabricating a wiring board according to claim 2 , wherein the processing of the external connecting pad to make the area of the external connecting pad smaller than the area of the surface plating layer is carried out by etching.4. The method of fabricating a wiring board according to claim 2 , wherein the processing of the external connecting pad to make the area of the external connecting pad smaller than the area of the surface plating layer creates an interval in a horizontal direction between an outer peripheral ...

ELECTRONIC COMPONENT AND FABRICATION METHOD OF THE SAME, AND ELECTRONIC DEVICE INCLUDING THE SAME

An electronic component includes: an element that is located on a substrate; a signal wiring that is located on the substrate and electrically connected to the element; a metal plate that is located so as to form a cavity on a functional part of the element and covers an upper surface of the cavity; a support post that is located on the substrate so as not to be located on the signal wiring, and supports the metal plate; and an insulating portion that covers the metal plate and the support post, and contacts a side surface of the cavity. 1. An electronic component by comprising:an element that is located on a substrate;a signal wiring that is located on the substrate and electrically connected to the element;a metal plate that is located so as to form a cavity on a functional part of the element and covers an upper surface of the cavity;a support post that is located on the substrate so as not to be located on the signal wiring, and supports the metal plate; andan insulating portion that covers the metal plate and the support post, and contacts a side surface of the cavity.2. The electronic component according to claim 1 , whereinthe support post is made of a metal.3. The electronic component according to claim 1 , whereinthe support posts are located along opposing sides of the metal plate so as to have lengths shorter than lengths of the sides.4. The electronic component according to claim 1 , further comprising:a connection terminal that is located on the substrate so as to penetrate through the insulating portion, and provides an external electrical connection to the element, whereina height from the substrate to an upper surface of the connection terminal is equal to a height from the substrate to an upper surface of the metal plate.5. The electronic component according to claim 4 , whereinthe metal plate electrically connects to the connection terminal connected to a ground.6. The electronic component according to claim 5 , whereinthe metal plate extends to ...

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

CIRCUIT BOARD AND METHOD OF MANUFACTURING THE CIRCUIT BOARD

A circuit board includes a core substrate portion, an insulating layer, a second wiring, and a via to be a cured product of a via paste. The via paste has a first latent curing agent and a second latent curing agent, an uncured resin mixture, and a conductive particle. Both a softening temperature of the first latent curing agent and that of the second latent curing agent are equal to or higher than 40° C. and are equal to or lower than 200° C., and a difference between the softening temperature of the first latent curing agent and that of the second latent curing agent is equal to or higher than 10° C. and is equal to or lower than 140° C. 1. A circuit board comprising:a core substrate portion having a first wiring provided on a surface thereof;a second wiring laminated on the core substrate portion through an insulating layer; anda via filled in a hole formed on the insulating layer, such that the via has a protruded portion in the hole, for electrically connecting the first wiring to the second wiring,wherein the insulating layer is formed of a cured product of a prepreg,the via is formed of a cured product of a via paste,the via paste has a first latent curing agent and a second latent curing agent, an uncured resin mixture to be cured by the first latent curing agent and the second latent curing agent, and a conductive particle,both a softening temperature of the first latent curing agent and that of the second latent curing agent are equal to or higher than 40° C. and are equal to or lower than 200° C., and a difference between the softening temperature of the first latent curing agent and that of the second latent curing agent is equal to or higher than 10° C. and is equal to or lower than 140° C.,the prepreg is softened between the softening temperature of the first latent curing agent and that of the second latent curing agent, andthe via paste is cured by increase in a viscosity and is thus changed into the cured product of the via paste in the hole of the ...

PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME

A method for manufacturing a printed wiring board includes forming a removable layer on a support substrate, forming an interlayer resin insulation layer on the removable layer, forming a penetrating hole in the interlayer resin insulation layer, forming a first conductive layer on the interlayer resin insulation layer and on a side wall of the penetrating hole, forming a conductive circuit on the interlayer resin insulation layer, forming a via conductor in the penetrating hole, removing the support substrate from the interlayer resin insulation layer by using the removable layer, forming a protruding portion of the via conductor protruding from a surface of the interlayer resin insulation layer, and forming a surface-treatment coating on a surface of the protruding portion of the via conductor. 1. A method for manufacturing a printed wiring board , comprising:forming a removable layer on a support substrate;forming an interlayer resin insulation layer on the removable layer;forming a penetrating hole in the interlayer resin insulation layer;forming a first conductive layer on the interlayer resin insulation layer and on a side wall of the penetrating hole;forming a conductive circuit on the interlayer resin insulation layer;forming a via conductor in the penetrating hole;removing the support substrate from the interlayer resin insulation layer by using the removable layer;forming a protruding portion of the via conductor protruding from a surface of the interlayer resin insulation layer; andforming a surface-treatment coating on a surface of the protruding portion of the via conductor.2. The method for manufacturing a printed wiring board according to claim 1 , wherein the forming of the protruding portion of the via conductor comprises reducing a thickness of the interlayer resin insulation layer.3. The method for manufacturing a printed wiring board according to claim 1 , wherein the forming of the via conductor comprises forming a second conductive layer on the ...

MANUFACTURING METHOD OF CIRCUIT BOARD

A manufacturing method of a circuit board is provided. Providing a substrate, where a first laser resistant structure is disposed on a first dielectric layer and at the periphery of a pre-removing area, a second dielectric layer covers the first laser resistant structure, a circuit layer is disposed on the second dielectric layer, a second laser resistant structure is disposed on the second dielectric layer and at the periphery of the pre-removing area, a third dielectric layer covers the circuit layer and the second laser resistant structure. There are gaps between the second laser resistant structure and the circuit layer, and the vertical projection of the gaps on the first dielectric layer overlaps the first laser resistant structure. A laser machining process is performed to etch the third dielectric layer at the periphery of the pre-removing area. The portion of the third dielectric layer within the pre-removing area is removed. 1. A manufacturing method of a circuit board , comprising: a first dielectric layer;', 'a first laser resistant structure, disposed on a first surface of the first dielectric layer and located at a periphery of the pre-removing area;', 'a second dielectric layer, disposed on the first dielectric layer and covering the first laser resistant structure;', 'a circuit layer, disposed on a second surface of the second dielectric layer, wherein a portion of the circuit layer is extended from outside of the pre-removing area into the pre-removing area;', 'a second laser resistant structure, disposed on the second surface, located at the periphery of the pre-removing area, and insulated from the circuit layer, wherein there is at least one gap between the second laser resistant structure and the circuit layer, and a vertical projection of the gap on the first surface overlaps the first laser resistant structure;', 'a third dielectric layer, disposed on the second dielectric layer, and covering the circuit layer and the second laser resistant ...

COPPER FOIL AND MANUFACTURING METHOD THEREFOR, COPPER FOIL WITH CARRIER AND MANUFACTURING METHOD THEREFOR, PRINTED CIRCUIT BOARD, AND MULTILAYER PRINTED CIRCUIT BOARD

Provided is a copper foil with a carrier capable of realizing wiring at line/space=15 μm/15 μm or less on a printed circuit board on which the copper foil is laminated. Further provided is a printed circuit board or a multilayer printed circuit board capable of realizing fine-pattern wiring at line/space=15 μm/15 μm or less using the copper foil. The copper foil is obtained by forming a release layer and a copper foil in this order on a carrier foil having a surface on which a mean spacing Sm as defined in JIS-B-06012-1994 between irregularities of ridges is 25 μm or more, and peeling off the copper foil from the carrier foil. The copper foil with a carrier is obtained by forming a release layer and a copper foil in this order on a carrier foil that is said copper foil, wherein a spacing between irregularities of ridges on a surface of the carrier foil on which the copper foil is formed is 25 μm or more in a mean spacing Sm as defined in JIS-B-06012-1994. A roughening treatment layer as necessary and a surface treatment layer are formed in this order on a surface of the copper foil. 1. A copper foil obtained by a process comprising:forming a release layer and a copper foil in this order on a carrier foil having a surface on which a mean spacing Sm as defined in JIS-B-06012-1994 between irregularities of ridges is 25 μm or more; and thenpeeling off the copper foil from the carrier foil.2. A copper foil comprising a copper foil and a surface treatment layer , wherein the copper foil is obtained by a process comprising:forming a release layer, the copper foil, a roughening treatment layer, and the surface treatment layer in this order on a carrier foil having a surface on which a mean spacing Sm as defined in JIS-B-06012-1994 between irregularities of ridges is 25 μm or more; and thenpeeling off the copper foil with the roughening treatment layer and the surface treatment layer from the carrier foil.3. The copper foil according to claim 2 , wherein the copper foil has ...

WIRING BASE PLATE AND METHOD FOR MANUFACTURING THE SAME

In a method for manufacturing a circuit board, as a photomask adapted to form an etching mask for selective removal of a seed layer covering a conductive portion exposed on an insulating film, a photomask whose opening area has an outline having two sides along two straight lines approaching to each other as the two straight lines extend from a center portion of the opening area in an extending direction of a wiring path is used. 1. A circuit board comprising:a conductive portion extending in an insulating film in a thickness direction of the insulating film and formed to conform an end surface thereof to a surface of the insulating film;a seed layer formed on the surface of the insulating film so as to facilitate deposition of a conductive material on the surface of the insulating film and having an opening opened to the end surface of the conductive portion; anda wiring path made of a conductive material deposited in the opening of the seed layer and on the seed layer, passing through the opening of the seed layer to continue into the end surface of the conductive portion, and extending in one direction on the seed layer,wherein the opening of the seed layer has an outline having two sides along two straight lines approaching to each other as the two straight lines extend from a center portion of the opening in an extending direction of the wiring path.2. The circuit board according to claim 1 , wherein the opening of the seed layer decreases a width dimension of the opening perpendicular to the extending direction of the wiring path toward the extending direction of the wiring path between the two sides.3. The circuit board according to claim 1 , wherein the conductive portion has a rectangular cross-sectional shape or a circular cross-sectional shape having a pair of opposed sides along the extending direction of the wiring path claim 1 , and the opening of the seed layer has a polygonal cross-sectional shape.4. The circuit board according to claim 3 , wherein ...

Method of manufacturing coreless substrate having filled via pad

A method of manufacturing a coreless substrate having filled via pads, including: forming a first insulating layer on one side of a carrier forming a build-up layer including a build-up insulating layer and a build-up circuit layer having a build-up via on the first insulating layer, and forming a second insulating layer on the build-up layer; removing the carrier, and forming via-holes in the first and second insulating layers; and conducting a filled plating process in the via-holes of the first and second insulating layers thus forming first and second filled via pads therein.

Rolled Copper Foil or Electrolytic Copper Foil for Electronic Circuit, and Method of Forming Electronic Circuit Using Same

A rolled copper foil or electrolytic copper foil for an electronic circuit to be used for forming a circuit by etching, characterized in comprising a layer of metal of one or more types among a platinum group, gold and silver with an etching rate that is lower than the copper formed on an etching surface side of the rolled copper foil or the electrolytic copper foil, or alternatively comprising a layer of an alloy having the above-described metal as its main component. The following can be achieved upon forming a circuit by etching a copper foil of a copper clad laminate: sagging caused by the etching is prevented; a uniform circuit of the intended circuit width is formed; the time required to form a circuit by etching is reduced; etching properties in pattern etching are improved; and the occurrence of short circuits and defects in the circuit width are prevented. 1. A rolled copper foil or electrolytic copper foil for an electronic circuit to be used for forming a circuit by etching and removing any unwanted portion of copper , comprising a layer of gold or a layer of an alloy having gold as its main component with an etching rate that is lower than the copper formed on an etching surface side of the rolled copper foil or the electrolytic copper foil where the circuit is to be formed upon removing any unwanted portion of the copper.2. The rolled copper foil or electrolytic copper foil for an electronic circuit according to claim 1 , further comprising a heat resistance layer.3. The rolled copper foil or electrolytic copper foil for an electronic circuit according to claim 2 , wherein the heat resistance layer is a layer made of zinc alloy claim 2 , and the zinc alloy contains as an alloy element claim 2 , one or more elements selected from a group consisting of a platinum group element claim 2 , gold claim 2 , a palladium group element claim 2 , and silver.4. The rolled copper foil or electrolytic copper foil for an electronic circuit according to claim 3 , ...

METHODS OF PATTERNING A CONDUCTOR ON A SUBSTRATE

A method of patterning a conductor on a substrate includes providing an inked elastomeric stamp inked with self-assembled monolayer-forming molecules and having a relief pattern with raised features. Then the raised features of the inked stamp contact a metal-coated visible light transparent substrate. Then the metal is etched to form an electrically conductive micropattern corresponding to the raised features of the inked stamp on the visible light transparent substrate. 1. A method of patterning a conductor on a substrate , comprising: a two-dimensional mesh of raised linear features having an average area density value of raised features between 0.5% to 20%, wherein the raised linear features have a width value between 0.5 to 25 micrometers;', 'a distance value between adjacent raised linear features of less than 1 millimeter;, 'providing an inked elastomeric stamp inked with self-assembled monolayer-forming molecules and having a relief pattern with raised features, the relief pattern having a low density region with a fill factor between 0.5% and 20%, measuring at least 5 square millimeters comprisingthe relief pattern further having a raised feature measuring at least 50 micrometers in width, wherein for a junction formed between the raised linear features and a larger raised feature, the raised linear feature width is widened by tapering before making contact to the larger raised feature;contacting the raised linear features of the inked elastomeric stamp to a metal-coated visible light transparent substrate; andetching the metal to form an electrically conductive micropattern corresponding to the raised features of the inked elastomeric stamp on the visible light transparent substrate.2. A method according to claim 1 , wherein the contacting step has a contact time in a range from 0.1 to 30 seconds.3. A method according to claim 1 , wherein the two-dimensional mesh of raised linear features has an average area density value of raised features between 0.5% to ...

METHOD FOR PRODUCING MORE PARTICULARLY PROCESSING OR POPULATING, A CIRCUIT BOARD ELEMENT AND CARRIER FOR USE IN SUCH A METHOD

In a method for producing a circuit board element, the following steps are provided: 1. A method for producing , in particular processing or loading , a circuit board element , comprising the steps ofproviding a substantially full-area carrier having an adhering surface;disposing and fixing on said adhering surface of the carrier a starting material of the circuit board element to be produced, in particular processed or loaded;producing, in particular processing or loading, the circuit board element fixed to the carrier in a position fixed on the carrier; andremoving the produced, in particular processed or loaded, circuit board element from the carrier,wherein a circuit board element configured with a surface deviating from a flat surface is disposed on the carrier in a recess or depression having a profile complementary to the surface contour of the circuit board element.2. The method according to claim 1 , wherein the circuit board element is disposed on the adhering surface of the carrier by referring to at least two marks claim 1 , in particular registration marks claim 1 , provided in or on the circuit board element.3. The method according to claim 1 , wherein claim 1 , during producing claim 1 , in particular processing or loading claim 1 , the circuit board element together with the carrier is subjected to a treatment under elevated pressure and/or elevated temperature relative to ambient conditions.4. The method according to claim 1 , wherein claim 1 , during producing claim 1 , in particular processing or loading claim 1 , the circuit board element claim 1 , mounting or forming at least one further layer or ply of the circuit board element claim 1 , structuring at least one layer or ply of the circuit board element claim 1 , fixing and/or inserting at least one active or passive component on or in the circuit board element is/are performed.5. The method according to claim 1 , wherein the circuit board element is comprised of a rigid claim 1 , flexible or ...

NOVEL POLYAMIC ACID, PHOTOSENSITIVE RESIN COMPOSITION, DRY FILM AND CIRCUIT BOARD

The present invention relates to novel polyamic acid; a photosensitive resin composition satisfying excellent flexibility and low stiffness and exhibiting excellent heat resistance and plating resistance; a dry film obtained from the photosensitive resin composition; and a circuit board including the dry film. 2. The polyamic acid according to claim 1 , wherein in the Chemical Formula 1 claim 1 , R claim 1 , R claim 1 , Rand Rare independently a methylene group claim 1 , an ethylene group claim 1 , an n-propylene group claim 1 , an iso-propylene group claim 1 , an n-butylene group claim 1 , an iso-butylene group claim 1 , an n-pentylene group claim 1 , an iso-pentylene group or a neo-pentylene group claim 1 ,x, y and z are independently an integer of from 1 to 30, andn is an integer of from 0 to 30.7. The polyamic acid according to claim 6 , comprising0.1 to 30 mol % of the repeat unit of the Chemical Formula 1;2 to 50 mol % of the repeat unit of the Chemical Formula 8; and20 to 97.9 mol % of the repeat unit of the Chemical Formula 3.8. The polyamic acid according to claim 1 ,wherein the polyamic acid has a weight average molecular weight of 5,000 to 200,000.9. A photosensitive resin composition comprising a polymer resin comprising the polyamic acid of ; a photocrosslinking agent; an organic solvent; and a photopolymerization initiator.10. The photosensitive composition according to claim 9 , wherein the photocrosslinking agent includes a (meth)acrylate-based compound including a double bond between carbons.11. The photosensitive composition according to claim 9 , wherein the photopolymerization initiator includes a compound selected from the group consisting of an acetophenone based compound claim 9 , a biimidazole based compound claim 9 , a triazine base compound claim 9 , and an oxime based compound.12. The photosensitive composition according to claim 9 , wherein the polymer resin has a solid concentration of 20 to 90 wt % claim 9 , based on the total weight of ...

Carrier for manufacturing printed circuit board, method of manufacturing the same and method of manufacturing printed circuit board using the same

Disclosed is a carrier for manufacturing a printed circuit board, which includes a first carrier including a first binder having a first opening and a first metal layer formed in the first opening of the first binder, and a second carrier, stacked with the first carrier and including a second binder having a second opening and a second metal layer which is formed in the second opening of the second binder and which partially overlaps with the first metal layer, so that the carrier is simply configured and the binders are formed not only on the lateral surfaces of the metal layers but also on the upper surfaces thereof, thus improving the reliability of bonding of the carrier at the periphery. A method of manufacturing the carrier and a method of manufacturing a printed circuit board using the carrier are also provided.

PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING A PRINTED CIRCUIT BOARD

A printed circuit board is disclosed. The printed circuit board includes a solder mask area and at least one chip attachment area. The at least one chip attachment area has an isolation solder mask layer such that the chip attachment area forms a plurality of chip sub-attachment areas to reduce an area of a solder paste smeared on the chip attachment area, and the isolation solder mask layer has at least one hole. 1. A printed circuit board used for setting at least one chip , the printed circuit board comprising a copper foil substrate and at least one hole , wherein the copper foil substrate comprises a surface of the substrate , the surface of the substrate comprising:a solder mask area, which has a main solder mask layer; andat least one chip attachment area, which allows at least one chip to be mounted; the at least one chip attachment area has an isolation solder mask layer used to divide the at least one chip attachment area into a plurality of chip sub-attachment areas; each of the chip sub-attachment areas has a sub-attachment area solder paste layer used to connect to the at least one chip, wherein the at least one hole is located in the isolation solder mask layer.2. The printed circuit board as claimed in claim 1 , wherein the surface of the substrate comprises a plurality of pin areas claim 1 , and each pin area has a pin area solder paste layer.3. The printed circuit board as claimed in claim 1 , wherein the shape of the top view of the isolation solder mask layer is substantially a cross.4. The printed circuit board as claimed in claim 1 , wherein the top view shape of the isolation solder mask layer is substantially a form of intersecting parallel lines.5. The printed circuit board as claimed in claim 2 , wherein the number of the at least one holes is plural claim 2 , and the distances between the holes are substantially equal.6. A method for manufacturing a printed circuit board claim 2 , comprising the following steps:setting at least one hole in ...

Methods of making packages using thin cu foil supported by carrier cu foil

In an embodiment, there is provided a method of creating a package, the method comprising: providing an initial substrate, wherein the initial substrate comprises a carrier foil, a functional copper foil, and an interface release layer between the carrier foil and the functional copper foil; building up copper portions on the functional copper foil; attaching a chip to a first copper portion; coupling the chip to a second copper portion; encapsulating at least the chip and the copper portions with a mold; and removing the carrier foil and interface release layer.

Method of manufacturing printed circuit board

Disclosed herein is a method of manufacturing a printed circuit board, the method including: preparing a base substrate having an insulating layer and a connection pad formed in the insulating layer; forming a photosensitive resist on the insulating layer; forming an opening part of which a side surface has a foot shape by patterning the photosensitive resist; forming a via hole exposing the connection pad by etching the insulating layer exposed by the opening part; and forming a via by filling the via hole.

Wiring board and method for manufacturing wiring board

A wiring board includes a substrate having a cavity, and an electronic component accommodated in the cavity of the substrate. The substrate has a thickness which is greater than a thickness of the electronic component such that a ratio of the thickness of the substrate to the thickness of the electronic component is set in a range of 0.3 or greater and 0.7 or less.

WIRING BOARD AND MANUFACTURING METHOD OF WIRING BOARD

There is provided a wiring board including a stiffener bonded to a circuit board, and a laminate formed by laminating a plurality of insulating layers and a plurality of wiring layers on a face of the stiffener opposite to a face bonded to the circuit board. On both faces of the laminate in a laminating direction, terminal connection parts connected to the wiring layers and connected to a terminal part of an electronic component are formed. Further, a component disposition hole, in which the terminal connection parts formed on one of the faces of the laminate are positioned and the electronic component is disposed, and a through hole for connection to the circuit board are formed in the stiffener. 1. A wiring board comprising:a stiffener bonded to a circuit board; anda laminate formed by laminating a plurality of insulating layers and a plurality of wiring layers on a face of the stiffener opposite to a face bonded to the circuit board,wherein, on both faces of the laminate in a laminating direction, terminal connection parts connected to the wiring layers and connected to a terminal part of an electronic component are formed, andwherein a component disposition hole, in which the terminal connection parts formed on one of the faces of the laminate are positioned and the electronic component is disposed, and a through hole for connection to the circuit board are formed in the stiffener.2. The wiring board according to claim 1 , wherein the stiffener is formed in a frame shape.3. A manufacturing method of a wiring board claim 1 , comprising:bonding two stiffeners in each of which a through hole for connection to a circuit board is formed and between which a bonding material is sandwiched;forming laminates by laminating a plurality of insulating layers and a plurality of wiring layers on respective faces of the respective stiffeners opposite to bonded faces, the laminates each having, on both faces in a laminating direction, a terminal connection part connected to the ...

PRINTED CIRCUIT BAORD AND METHOD FOR MANUFACTURING SAME

A printed circuit board includes a base, a number of conductive pads, a dielectric layer, an activated metal layer, a first metal seed layer, a second metal seed layer, and a plurality of metal bumps. The conductive pads are formed on the base. The dielectric layer is formed on a surface of the conductive pads and portions of the base are exposed from the c conductive pads. The dielectric layer includes blind vias corresponding to the conductive pads, and a laser-activated catalyst. The activated metal layer is obtained by laser irradiation at the wall of the blind via. The activated metal layer is in contact with the dielectric layer. The second metal seed layer is formed on the activated metal layer and the conductive pads. Each metal bump is formed on the second metal seed layer, and each metal bump protrudes from the dielectric layer. 1. A method for manufacturing a printed circuit board , comprising:providing a circuit substrate, the circuit substrate comprising a base and a plurality of conductive pads;forming a dielectric layer on a surface of the conductive pads and a surface of the base exposed from the conductive pads, the solder mask comprising a laser-activated catalyst;forming a first metal seed layer on a surface of the dielectric layer furthest from the circuit substrate;forming a photoresist layer on a surface of the first metal seed layer furthest from the dielectric layer, the photoresist layer comprising a trace portion;exposing the trace portion of the photoresist layer;defining a plurality of blind vias in the photoresist layer, the first metal seed layer, and the solder mask using a laser, the blind vias spatially corresponding to the conductive pads, each conductive pad exposed from the corresponding blind via, the laser-activated catalyst at the wall of blind via being activated by laser, thereby obtaining an activated metal layer;forming a second metal seed layer on the activated metal layer, the second metal seed layer being electrically ...

Printed Circuit Board and Method for Manufacturing the Same

Provided is a method for manufacturing a printed circuit board. The method for manufacturing the printed circuit board includes applying an adhesive on a support board, attaching an electronic device on the adhesive, forming an insulation layer for burying the electronic device, separating the insulation layer from the support board, forming a lower insulation layer under the insulation layer, and forming a via connected to terminals of the electronic device in the insulation layer or the lower insulation layer. Thus, since an adhesion material of an adhesion film does not remain between the internal circuit patterns, and the internal circuit patterns are not stripped by an adhesion force of the adhesion film, device reliability may be secured.

EMBEDDED ARCHITECTURE USING RESIN COATED COPPER

Electronic assemblies and methods for their manufacture are described, including those related to the formation of an assembly including a carrier and a resin coated copper layer positioned on the carrier. The resin coated copper layer includes a first layer comprising a resin and a second layer comprising copper, with the first layer bonded to the second layer. The first layer of the resin coated copper is positioned between the carrier and the second layer of the resin coated copper. An opening is formed in the second layer of the resin coated copper. A die is positioned in the opening. A plurality of dielectric layers and metal pathways are positioned on the second layer and on the die. Other embodiments are described and claimed. 1. An assembly comprising:a carrier structure;a resin coated copper layer positioned on the carrier structure, the resin coated copper layer including a first layer comprising a resin and a second layer comprising copper, the first layer bonded to the second layer, the first layer positioned between the carrier and the second layer;an opening in the second layer of the resin coated copper;a die positioned in the opening; anda plurality of dielectric layers and metal interconnections positioned on the second layer and on the die.2. The assembly of claim 1 , wherein the carrier comprises:a core;a first metal layer on the core; anda second metal layer on the first metal layer.3. The assembly of claim 1 , wherein the first metal layer and the second metal layer each comprise copper.4. The assembly of claim 2 , further comprising an adhesive layer positioned between the first metal layer and the second metal layer.5. The assembly of claim 4 , the adhesive layer selected from the group consisting of an organic adhesive claim 4 , a metal oxide adhesive claim 4 , and a thermally releasing adhesive.6. The assembly of claim 1 , wherein the core comprises a prepreg material.7. The assembly of claim 1 , wherein the resin comprises an epoxy.8. The ...

FABRICATION METHOD FOR FLEXIBLE CIRCUIT BOARD

A fabrication method for a flexible circuit board is provided. The fabrication method includes the following steps. Firstly, a release film having an upper surface and a lower surface opposite to each other is provided. Next, two flexible substrates are respectively disposed on the upper surface and the lower surface. Next, a plurality of nano-scale micro-pores are formed on each flexible substrate to form two non-smooth flexible substrates. The nano-scale micro-pores evenly distributed over an outer surface of each non-smooth flexible substrate. Each non-smooth flexible substrate being adapted to be performed a plating process directly on the outer surface thereof. 1. A fabrication method for a flexible circuit board , the fabrication method comprising:providing a release film having an upper surface and a lower surface opposite to each other; anddisposing two flexible substrates respectively on the upper surface and the lower surface;forming a plurality of nano-scale micro-pores on each flexible substrate to form two non-smooth flexible substrates, the nano-scale micro-pores evenly distributed over an outer surface of each non-smooth flexible substrate;directly forming two metal layers respectively on the outer surfaces of the non-smooth flexible substrates by electroplating;forming a plurality of openings on each of the metal layers, each of the openings exposing a part of the corresponding outer surface; andseparating the release film from the non-smooth flexible substrates to form the two independent flexible circuit boards.2. The fabrication method for the flexible circuit board as claimed in claim 1 , wherein the method of forming a plurality of nano-scale micro-pores on each flexible substrate comprises micro-etching process.3. (canceled)4. The fabrication method for the flexible circuit board as claimed in claim 1 , wherein each of the non-smooth flexible substrates comprises evenly distributed nano-scale silicon dioxide particles.5. A fabrication method ...

NANOWIRE GRID STRUCTURE

Provided is a method of manufacturing a nanowire, including: forming a plurality of grid patterns on a grid base layer; forming a sacrificial layer on the grid base layer on which the grid patterns are formed; producing a nanowire grid structure by forming a nanowire base layer on the sacrificial layer; forming a nanowire by wet etching the nanowire base layer; and separating the grid patterns from the nanowire by etching the sacrificial layer. Thus, the method can be provided with the following advantages; Because a wet etching time is adjusted, a width and a height of the nanowire to be produced can be adjusted; the nanowire can be produced at room temperature with a low cost; the nanowire can be produced in large quantities; and in spite of the mass production, the nanowire having high uniformity can be produced. 1. A nanowire grid structure , comprising:a grid base layer on which a plurality of grid patterns is are formed;a sacrificial layer formed on the grid base layer on which the grid patterns are formed; anda nanowire base layer formed on the sacrificial layer so that a void is formed between the respective grid patterns.2. The structure of claim 1 , wherein a ratio between a width of the grid patterns and a thickness of the sacrificial layer formed on a side of the grid patterns is 1:0.1 to 1:0.5.3. The structure of claim 1 , wherein a ratio between the width of the grid patterns and a thickness of the nanowire base layer formed on the side of the grid patterns is 1:0.1 to 1:0.5.4. The structure of claim 1 , wherein a ratio between the thickness of the sacrificial layer formed on the side of the grid patterns and the thickness of the nanowire base layer is 1:0.1 to 1:1.5.5. The structure of claim 1 , wherein the width of the grid patterns is formed in a range of 20 nm to 200 nm.6. The structure of claim 5 , wherein an etchant of the sacrificial layer and an etchant of the nanowire base layer are formed of different materials from each other.7. The ...

Printed wiring board and method for manufacturing printed wiring board

A method for manufacturing a printed wiring board includes forming metal posts on a conductor circuit formed on a resin insulating layer, forming the outermost resin layer on the resin insulating layer such that the metal posts is embedded in the outermost resin layer, forming a mask at a dam formation site for a dam structure of the outermost resin layer to surround at least part of a pad group including the metal posts on the outermost resin layer, and reducing a thickness of the outermost resin layer exposed from the mask such that end portions of the metal posts are exposed from the outermost resin layer, that the metal posts form the pad group, and that the outermost resin layer has the dam structure forming part of the outermost resin layer and formed to surround at least part of the pad group including the metal posts.

METHOD OF FABRICATING AN ELECTRICAL DEVICE PACKAGE STRUCTURE

A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is foamed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed. 1. A method of packaging an electrical device comprising:providing a circuit board, wherein the circuit board comprises a substrate and a first conductive pattern disposed on the substrate;disposing an electrical device on the circuit board, wherein the electrical device has at least one electrode;forming a dielectric layer on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein the first conductive pattern forms a first caving pattern on the dielectric layer;patterning the dielectric layer to form a through hole extended to the first conductive pattern and a second caving pattern connecting with the through hole and exposing the electrode;filling a conductive material in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern;removing the substrate; andforming a first solder mask and a second solder mask on the first conductive pattern and the second conductive pattern, respectively, wherein the first solder mask exposes portions of the first conductive pattern and the second solder mask exposes portions ...

METHODS FOR PRODUCING AN ETCH RESIST PATTERN ON A METALLIC SURFACE

A method of forming a metallic pattern on a substrate is provided. The method includes applying onto a metallic surface, a chemically surface-activating solution having an activating agent that chemically activates the metallic surface; non-impact printing an etch-resist ink on the activated surface to produce an etch resist mask according to a predetermined pattern, wherein at least one ink component within the etch-resist ink undergoes a chemical reaction with the activated metallic surface to immobilize droplets of the etch-resist ink when hitting the activated surface; performing an etching process to remove unmasked metallic portions that are not covered with the etch resist mask; and removing the etch-resist mask. 1. A method of forming a metallic pattern on a substrate , the method comprising:activating a metallic surface of a substrate by applying an aqueous solution comprising an inorganic activating agent onto the metallic surface;after chemically activating the metallic layer, selectively printing an etch-resist ink onto the metallic surface;reacting a component of the etch-resist ink with ions of the metallic surface to produce an etch-resist mask;performing an etching process to remove portions of the metallic layer that are not covered by the etch-resist mask; andremoving the etch-resist mask to form the metallic pattern.2. The method of claim 1 , wherein the metallic pattern formed by performing the etching process comprises multiple metallic lines each of the multiple metallic lines having a width of less than 50 microns.3. The method of claim 1 , wherein the etch-resist mask produced from the non-impact printing comprises lines having a width of less than 50 microns.4. The method of claim 1 , wherein the metallic pattern formed by performing the etching process comprises metallic lines having a width of less than 30 microns.5. The method of claim 1 , further comprising claim 1 , prior to printing claim 1 , removing the chemically surface-activating ...

MICROELECTRONIC DEVICES DESIGNED WITH ULTRA-HIGH-K DIELECTRIC CAPACITORS INTEGRATED WITH PACKAGE SUBSTRATES

Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers and a capacitor that is integrated with a first organic dielectric layer of the plurality of organic dielectric layers. The capacitor includes first and second conductive electrodes and an ultra-high-k dielectric layer that is positioned between the first and second conductive electrodes. 1. A microelectronic device comprising:a plurality of organic dielectric layers; anda capacitor that is integrated with a first organic dielectric layer of the plurality of organic dielectric layers, and the capacitor includes first and second conductive electrodes and a plurality of vertically arranged ultra-high-k dielectric layers.2. The microelectronic device of claim 1 , wherein the capacitor has a capacitance density of at least 10 nanoFarad per millimeter.3. The microelectronic device of claim 1 , wherein each of the plurality of ultra-high-k dielectric layers has a relative permittivity of at least 100 up to 10 claim 1 ,000.4. The microelectronic device of claim 1 , further comprising:first and second connections formed in the first organic dielectric layer, the first connection contacts the first conductive electrode and the second connection contacts the second electrode.5. The microelectronic device of claim 1 , further comprising:first and second connections formed in a second organic dielectric layer of the plurality of organic dielectric layers, the first connection contacts the first conductive electrode and the second connection contacts the second electrode.6. The microelectronic device of claim 5 , further comprising:a first connection formed in the first organic dielectric layer and a second connection formed in a second organic dielectric layer of the plurality of organic dielectric layers, the first connection contacts the first conductive electrode and the second connection contacts the second electrode.7. The microelectronic device of claim 1 , ...

SUBSTRATE WITH ELECTRONIC COMPONENT EMBEDDED THEREIN

A substrate with an electronic component embedded therein includes: a core structure having a cavity; a metal layer disposed on a bottom surface of the cavity of the core structure; and an electronic component disposed on the metal layer in the cavity of the core structure. The substrate with the electronic component embedded therein has an excellent heat dissipation effect. 1. A substrate with an electronic component embedded therein , comprising:a core structure including a first insulating body, a plurality of first wiring layers respectively disposed on or in the first insulating body, and one or more first via layers disposed in the first insulating body, the core structure having a cavity penetrating through at least a portion of the first insulating body;a first metal layer disposed on a bottom surface of the cavity;an electronic component disposed on the first metal layer in the cavity; anda second metal layer disposed on a side surface of the electronic component.2. The substrate with the electronic component embedded therein of claim 1 , wherein the second metal layer is in physical contact with the side surface of the electronic component.3. The substrate with the electronic component embedded therein of claim 2 , wherein the second metal layer surrounds four side surfaces of the electronic component.4. The substrate with the electronic component embedded therein of claim 1 , wherein the second metal layer is physical contact with the first metal layer.5. The substrate with the electronic component embedded therein of claim 4 , wherein the first metal layer has a groove portion claim 4 , and a portion of the second metal layer is disposed in the groove portion.6. The substrate with the electronic component embedded therein of claim 5 , wherein the groove portion extends along four side surfaces of the electronic component.7. The substrate with the electronic component embedded therein of claim 1 , further comprising a first passivation layer disposed ...

COMPOSITE CARRIER FOR WARPAGE MANAGEMENT

A composite carrier is disclosed for warpage management as a temporary carrier in semiconductor process. Warpage is reduced for a product, semi-product, or build-up layer processed on the temporary composite carrier which is peeled off the temporary carrier in a later step. The composite carrier comprises a top substrate and a bottom substrate, an adhesive layer is configured in between the top substrate and a bottom substrate. One of the embodiments discloses the top substrate of the composite carrier having a lower CTE and the bottom substrate of the composite carrier having a higher CTE. 1. A composite carrier for fabricating a build-up circuitry thereon , comprising:a polymer;a top substrate;a bottom substrate below the top substrate; andan adhesive layer between the top substrate and the bottom substrate, the adhesive layer bonding the top substrate to the bottom substrate; [ top and bottom surfaces opposite to each other in a thickness direction of the composite carrier, and', 'a side surface extending in the thickness direction and connecting the top and bottom surfaces,, 'each of the top substrate, the bottom substrate and the adhesive layer has'}, 'the top surface of the top substrate includes an area for semiconductor processing thereon,', 'the polymer wraps around the side surface of each of the top substrate, the adhesive layer and the bottom substrate,', 'the area for semiconductor processing on the top surface of the top substrate is free of the polymer, and', 'in a cross-section taken in a plane perpendicular to the top surface of the top substrate, the polymer has an outer surface curved and convex outwardly away from the top substrate, the adhesive layer and the bottom substrate., 'wherein'}2. The composite carrier as claimed in claim 1 , whereinthe top substrate has a lower CTE and the bottom substrate has a higher CTE.3. The composite carrier as claimed in claim 1 , wherein Invar having a coefficient of thermal expansion (CTE) around 1 ppm,', ' ...

Co-Fired Passive Integrated Circuit Devices

Co-fired integrated circuit devices and methods for fabricating and integrating such on a workpiece are disclosed herein. An exemplary method includes forming a first passive device and a second passive device over a carrier substrate. The first passive device and the second passive device each include at least one material layer that includes a co-fired ceramic material. The carrier substrate is removed after performing a co-firing process to cause chemical changes in the co-fired ceramic material. The first passive device may include a conductive loop disposed between a first magnetic layer and a second magnetic layer. The first magnetic layer, the second magnetic layer, or both includes a co-fired ceramic magnetic material. The second passive device may include a first conductive layer and a second conductive layer separated by a dielectric layer. The first conductive layer, the second conductive layer, or both includes a co-fired ceramic conductive material. 1. A method comprising:forming a first passive device and a second passive device over a carrier substrate, wherein the first passive device is different than the second passive device, and further wherein the first passive device and the second passive device each include at least one material layer that includes a co-fired ceramic material; andremoving the carrier substrate after performing a co-firing process to cause chemical changes in the co-fired ceramic material.2. The method of claim 1 , wherein:the forming the first passive device includes forming a conductive loop disposed between a first magnetic layer and a second magnetic layer, wherein the first magnetic layer, the second magnetic layer, or both includes a co-fired ceramic magnetic material; andthe forming the second passive device includes forming a first conductive layer and a second conductive layer separated by a dielectric layer, wherein the first conductive layer, the second conductive layer, or both includes a co-fired ceramic ...

Partitioned Hybrid Substrate for Radio Frequency Applications

The presently claimed invention is to provide a package for compact RF signal system, and a method to form the package thereof in order to miniaturize the size of package, improve signal integrity, and reduce manufacturing cost. The package comprises a hybrid substrate with a sandwiched structure, in which the hybrid substrate comprises an upper layer and a lower layer with different dielectric properties being separated by an interposer for improving electrical isolation and mechanical stiffness. Metal layers are formed on the sidewalls of the opening to surround an active component, such that the metal sidewalls together with two ground plates in the upper and lower layers constitute a self-shielding enclosure inside the package to protect the active component. 1. A package for compact radio frequency signal system , comprising:a hybrid substrate with a sandwiched structure, and the hybrid substrate comprising a first dielectric layer and a second dielectric layer being separated by an interposer;wherein the first dielectric layer, located on one side of the interposer, with a first value of loss tangent carries one or more first components operable for transmitting radio frequency signal of at least one active component to at least one antenna arranged on top of the first dielectric layer;wherein the second dielectric layer, located on another side of the interposer, with a second value of loss tangent carries one or more second components operable for transmitting low frequency signal of at least one active component to at least one outside circuit;wherein the at least one active component is embedded in the hybrid substrate; andwherein the first value of loss tangent is lower than the second value of loss tangent.2. The package of claim 1 , wherein the active component includes a radio frequency integrated circuit chip claim 1 , power management chip or digital signal chip.3. The package of claim 1 , wherein the first value of loss tangent is lower than 0.01 ...

Manufacturing method of circuit board structure

Provided is a manufacturing method of a circuit board structure including steps as below. A glass film is provided on an electrostatic chuck (E-chuck). A dicing process is performed, such that at least one slit is formed in the glass film. A plurality of first conductive vias are formed in the glass film. A first circuit layer is formed on the glass film. A polymer layer is formed on the first circuit layer. The polymer layer covers surfaces of the first circuit layer and the glass film. A plurality of second conductive vias are formed in the polymer layer. A second circuit layer is formed on the polymer layer, such that a first circuit board structure is formed. A singulation process is performed, such that the first circuit board structure is divided into a plurality of second circuit board structures.

Semi-additive process for printed circuit boards

A circuit board has a dielectric core, a foil top surface, and a thin foil bottom surface with a foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling. A sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step are performed, which provide dot vias of fine linewidth and resolution. 1) A process for forming fine pitch dot vias on a laminate having a bottom thin foil bonded to the laminate , a comparatively thicker backing foil adjacent to the bottom thin foil , and an optional thin top foil , the process comprising:laser drilling blind vias through the laminate top surface to the bottom thin foil, optionally also drilling through holes penetrating through the laminate, bottom thin foil, and backing foil;removing the backing foil;treating the surfaces of the laser drilled vias and drilled holes with a catalyst;electroless plating the optional top foil surface and bottom foil surface, the inner surfaces of the vias, and the inner surfaces of the optionally drilled through holes;applying patterned resist over the top and bottom surface;electro-plating the circuit board until copper is deposited to a level below the patterned resist;tin plating the exposed copper regions of the circuit board;stripping the patterned resist;quick etching the exposed copper regions to the underlying laminate;optionally etching the tin plating.2) The process of where said bottom thin foil or said optional top thin foil is copper foil approximately 0.12 mil to 0.15 mil in thickness.3) The process of where said laser drilled vias are less than 5 mils in diameter.4) The process of where said electroless plating and said electroplating deposits copper.5) The process of where said catalyst is at least one of: Palladium (Pd) claim 1 , ...

PRINTED CIRCUIT BOARD

A printed circuit board is disclosed. The printed circuit board includes a first substrate portion, and a second substrate portion connected to the first substrate portion and having a flexible insulation layer which is bendable, and the second substrate portion includes a frame member inserted into the flexible insulation layer. 1. A printed circuit board , comprising:a first substrate portion; anda second substrate portion connected to the first substrate portion, and having a flexible insulation layer which is bendable and comprises a first insulation layer having a through-hole therein and a second insulation layer,wherein the second substrate portion includes a frame member disposed in the through-hole, andthe second insulation layer fills at least a portion of a gap between the frame member and the first insulation layer.2. The printed circuit board of claim 1 , wherein the second substrate portion includes:a first region, adjacent to the first substrate portion and connected to the first substrate portion, and which is bendable; anda second region spaced apart from the first substrate portion, and into which the frame member is inserted.3. The printed circuit board of claim 2 , wherein one side of the flexible insulation layer is provided with a pad on which a first electronic element is mounted is formed claim 2 , andthe pad is formed on the second region.4. The printed circuit board of claim 1 , wherein the frame member is provided with an accommodation space which is penetrated claim 1 , andthe printed circuit board further includes a second electronic element disposed in the accommodation space, and embedded in the flexible insulation layer.5. The printed circuit board of claim 4 , wherein the frame member includes an electromagnetic interference (EMI) shielding material.6. The printed circuit board of claim 5 , wherein the frame member includes at least one of a magnetic material and a metal.7. The printed circuit board of claim 1 , wherein the flexible ...

PRINTED CIRCUIT BOARD AND MANUFACTURE METHOD THEREOF

Disclosed herein is a printed circuit board capable of implementing slimness by decreasing the number of entire layers through an asymmetrical build-up structure in which an electric device is embedded, the printed circuit board including: a core layer including a cavity formed therein so that an electric device is embedded and a circuit pattern and a pad formed on upper and lower surfaces thereof; a through via formed in the core layer so as to connect the upper and the lower pads of the core layer to each other; a plurality of insulating layers built-up on the core layer and including a plurality of vias so as to be electrically connected to the through via; and a solder resist layer applied onto a lower portion of the core layer so that a lower surface of the through via is partially exposed. 1. A printed circuit board comprising:a core layer including a cavity formed therein so that an electric device is embedded and a circuit pattern and a pad formed on upper and lower surfaces thereof;a through via formed in the core layer so as to connect the upper and the lower pads of the core layer to each other;a plurality of insulating layers built-up on the core layer and including a plurality of vias so as to be electrically connected to the through via; anda solder resist layer applied onto a lower portion of the core layer so that a lower surface of the through via is partially exposed.2. The printed circuit board according to claim 1 , wherein a solder resist of the solder resist layer is partially filled between the electric device and the cavity.3. The printed circuit board according to claim 1 , wherein a resin of the insulating layer is partially filled between the electric device and the cavity.4. The printed circuit board according to claim 2 , wherein the solder resist of the solder resist layer and the resin of the insulating layer are partially filled between the electric device and the cavity.5. The printed circuit board according to claim 1 , wherein a ...

Wiring substrate and semiconductor package

A wiring substrate includes an insulating layer and a wiring layer buried in the insulating layer at a first surface of the insulating layer. The wiring layer includes a first portion and a second portion. The first portion is narrower and thinner than the second portion. The first portion includes a first surface exposed at the first surface of the insulating layer. The second portion includes a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer. The opening is open at a second surface of the insulating layer opposite to the first surface thereof.

PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME

There are provided a printed circuit board and a method of manufacturing the same. The printed circuit board according to an exemplary embodiment of the present disclosure includes: a first insulating layer; a second insulating layer formed below the first insulating layer; a via pad formed on an upper surface of the second insulating layer and formed so as to be buried in the second insulating layer; a double via formed on an upper surface of the via pad, formed so as to penetrate through the first insulating layer, and including an auxiliary via and a first via; and a second via formed on a lower surface of the via pad and formed so as to penetrate through the second insulating layer.

METHOD FOR PRODUCING A PRINTED CIRCUIT BOARD WITH AN EMBEDDED SENSOR CHIP, AND PRINTED CIRCUIT BOARD

A method for producing a printed circuit board () having at least one embedded sensor chip (), in which at least one sensor face () and terminals () are arranged on a face of the chip, said method comprising the following steps: 1103543. A method for producing a printed circuit board () having at least one embedded sensor chip () , in which at least one sensor face () and terminals () are arranged on a face of the sensor chip () , the method comprising the following steps in the order below:{'b': '1', 'a) providing an adhesive film (),'}{'b': 2', '1, 'b) printing a conductor structure () formed from a conductive paste onto a surface of the adhesive film (),'}{'b': 3', '5', '4', '2, 'c) placing the at least one sensor chip () with the face comprising the at least one sensor face () and the terminals () onto the conductor structure () formed from a conductive paste, in an indexed manner,'}d) curing the conductive paste,{'b': 6', '7, 'e) applying an insulation layer () having a conductor layer () arranged thereabove to the surface of the structure, created in the previous steps, comprising the sensor chip (3),'}f) laminating the structure created in the previous steps,{'b': 7', '9', '7', '7', '1, 'i': b,', 'c, 'g) structuring the conductor layer () and forming vias () from the conductor layer to conductive tracks () of the conductor structure on the surface of the adhesive film (), and'}{'b': '1', 'h) removing the adhesive film ().'}2. The method of claim 1 , wherein the conductive paste is an epoxy resin adhesive.3. The method of claim 2 , wherein in step e) the curing is performed by applying UV light and/or heat.46. The method of claim 1 , wherein the insulation layer () is a prepreg.57. The method a of claim 1 , wherein the conductor layer () is a copper layer.61. The method of claim 1 , wherein the adhesive film () is a silicone-based adhesive film.7. The method of claim 1 , wherein the printing in step b) is carried out with the aid of a screen-printing method. ...

FLEXIBLE ELECTRONIC DEVICE AND FABRICATING METHOD THEREOF

A flexible electronic device including a first flexible substrate, an electronic component, and a control device is provided. The electronic component includes a conductive layer. The control device includes at least one integrated circuit and a circuit layer set. The circuit layer set includes a plurality of circuit layers and at least one first dielectric layer, and at least a portion of the first dielectric layer is interposed between two adjacent circuit layers. The integrated circuit is electrically connected to the electronic component through the circuit layer set and the conductive layer. At least a portion of the conductive layer and at least a portion of one circuit layer are integrally formed, and the conductive layer and the circuit layer are both disposed on the first flexible substrate. A fabricating method of a flexible electronic device is also provided. 1. A flexible electronic device , comprising:a first flexible substrate having a surface;an electronic component comprising a conductive layer; and at least one integrated circuit; and', 'a circuit layer set disposed between the at least one integrated circuit and the first flexible substrate and comprising a plurality of circuit layers and at least one first dielectric layer, wherein at least a portion of the at least one first dielectric layer is interposed between two adjacent circuit layers, and the at least one integrated circuit is electrically connected to the electronic component through the circuit layer set and the conductive layer, wherein at least a portion of the conductive layer and at least a portion of one of the circuit layers are integrally formed, and the conductive layer and the one of the circuit layers are both disposed on the first flexible substrate., 'a control device disposed on the surface and comprising2. The flexible electronic device according to claim 1 , wherein the circuit layer set comprises a plurality of conductive through holes that penetrate at least a portion of ...

BOARD-TO-BOARD CONNECTORS AND MOUNTING STRUCTURE

A circuit card assembly includes a first printed wiring board with a first receiving feature and a trace attached to the first printed wiring board. The three dimensional trace is formed by layer-by-layer additive manufacturing. The three dimensional trace includes first and second ends. The first end of the three dimensional trace engages with the first receiving feature of the first printed wiring board. The second end of the three dimensional trace is configured to engage with a second printed wiring board. 1. A circuit card assembly comprising:a first printed wiring board with a first receiving feature;a second printed wiring board with a second receiving feature and a first three dimensional trace attached to the first printed wiring board, wherein the first three dimensional trace is formed by a layer-by-layer additive manufacturing process, wherein the first three dimensional trace comprises a first end and a second end, wherein the first end of the first three dimensional trace engages with the first receiving feature of the first printed wiring board, wherein the second end of the first three dimensional trace engages with the second printed wiring board.2. The circuit card assembly of claim 1 , wherein the circuit card assembly comprises a second three dimensional trace.3. The circuit card assembly of claim 1 , wherein the first receiving feature of the first printed wiring board comprises a solder cup claim 1 , a socket claim 1 , a surface mount claim 1 , or a thru-hole.4. The circuit card assembly of wherein the second end of the first three dimensional trace comprises a pin or a socket.5. The circuit card assembly of and further comprising a structural support claim 1 , a stop claim 1 , a chamfer claim 1 , a heat sink claim 1 , a test point lead claim 1 , an electromagnetic shield claim 1 , a locating feature claim 1 , or a resilient element with a spring constant.6. The circuit card assembly of claim 5 , wherein the structural support claim 5 , stop ...

DESMEAR PROCESSING METHOD AND MANUFACTURING METHOD FOR MULTILAYER PRINTED WIRING BOARD

The purpose of the present invention is to provide a desmear processing method capable of sufficiently removing a smear while preventing the surface of a substrate from being rough. The desmear processing method according to the present invention is a desmear processing method for removing smear from a substrate in which a hole is formed, the desmear processing method comprising a first desmear processing step for dissolving and decomposing a part of the smear, and a second desmear processing step for performing ultrasonic treatment on the substrate after the first desmear processing step. Further, in the second desmear processing step, at least one of: changing the frequency of the ultrasonic waves; and moving an oscillation source of the ultrasonic waves and the substrate in two or more directions relatively to each other, is performed during the ultrasonic treating. 1. A desmear processing method for removing smear from a substrate having holes formed therein , comprising:a first desmear processing operation of dissolving or decomposing part of the smear; anda second desmear processing operation of subjecting the substrate to an ultrasonic treatment subsequent to the first desmear processing operation,the second desmear processing operation comprising, during the ultrasonic treatment, at least one of: changing an ultrasonic frequency; and moving the substrate and an ultrasonic oscillation source relative to each other in two or more directions.2. The desmear processing method according to claim 1 , wherein ultrasonic waves radiated during the ultrasonic treatment have a frequency more than or equal to 15 kHz and less than or equal to 200 kHz.3. The desmear processing method according to claim 1 , wherein a distance D of the relative movement of the substrate and the ultrasonic oscillation source satisfies the relational expression claim 1 ,{'br': None, 'i': '≦D', '{sonic speed/(ultrasonic frequency×2)}/4≦150×{sonic speed/(ultrasonic frequency×2)}\u2003\u2003(1)'} ...

METHOD FOR MANUFACTURING A CIRCUIT

A method for manufacturing a circuit, in particular of a hearing aid, in which method a printed circuit board is made available with a first region and with a second region which are separated by means of a boundary. A component is mounted on the printed circuit board, wherein the component is positioned on the boundary. The first region is covered by means of a mask which has an edge, wherein the edge is positioned on the component, and the printed circuit board is provided with a coating. The coating is cut away in the region of the component and the mask is removed. 1. A method for manufacturing a circuit , the method comprising:providing a printed circuit board having a first region and a second region that are separated by a boundary;mounting on the printed circuit board, a component that is positioned on the boundary;covering the first region via a mask comprising an edge that is positioned on the component;providing the printed circuit board with a coating;cutting the coating away in a region of the component; andremoving the mask.2. The method according to claim 1 , wherein the coating is a gaseous coating and/or a parylene coating.3. The method according to claim 1 , wherein the coating is cut away via a blade.4. The method according to claim 1 , wherein the coating is cut away along the edge of the mask and/or a serrated edge is chosen.5. The method according to claim 1 , wherein the mask is formed of a rubber claim 1 , a silicone claim 1 , or a metal.6. The method according to claim 1 , wherein the first region is an edge region of the printed circuit board and/or a mask with a gap into which the printed circuit board is inserted.7. The method according to claim 1 , wherein the component is secured to the printed circuit board by SMD technology.8. The method according to claim 7 , wherein a further electronic or electrical component is secured to the printed circuit board by SMD technology.9. The method according to claim 1 , wherein the component is made ...

INTERCONNECT CIRCUIT METHODS AND DEVICES

Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators. 1. A method of forming an interconnect circuit , the method comprising: wherein the conductive layer comprises a first side and a second side, opposite of the first side,', 'wherein the substrate is laminated to the second side of the conductive layer;, 'laminating a substrate to a conductive layer,'} wherein patterning the conductive layer forms a first conductive portion and a second conductive portion of the conductive layer, at least partially separated from the first conductive portion,', 'wherein the substrate maintains orientation of the first conductive portion relative to the second conductive portion;, 'patterning the conductive layer, while the conductive layer remains laminated to the substrate,'}laminating a first insulator to the first side of the conductive layer; and 'wherein the first insulator maintains the orientation of the first conductive portion relative to the second conductive portion after the substrate is removed.', 'removing the substrate from the conductive layer,'}2. The method of ...

STRESS-REDUCED CIRCUIT BOARD AND METHOD FOR FORMING THE SAME

A stress-reduced circuit board includes an insulating substrate, and first and second electrically conductive layers which are stacked one upon the other, and which respectively have peripheral marginal regions that are configured in a stepped arrangement. The first electrically conductive layer is configured to have an area dimension larger than that of the second electrically conductive layer and a thickness not greater than that of the second electrically conductive layer so as to minimize stress caused by a difference in coefficients of thermal expansion between the insulating substrate and the first and second electrically conductive layers. 1. A circuit board comprising:an insulating substrate; andan electrically conductive unit including a first electrically conductive layer formed on said insulating substrate, and a second electrically conductive layer stacked on said first electrically conductive layer, said first and second electrically conductive layers respectively having peripheral marginal regions which are configured in a stepped arrangement such that said first electrically conductive layer is configured to have an area dimension larger than that of said second electrically conductive layer, and a thickness not greater than that of said second electrically conductive layer, so as to minimize stress caused by a difference in coefficients of thermal expansion between said electrically conductive unit and said insulating substrate.2. The circuit board of claim 1 , wherein said peripheral marginal regions respectively have marginal edges claim 1 , a distance between two adjacent ones of said marginal edges ranging from 1 μm to 1 cm.3. The circuit board of claim 2 , wherein the distance ranges from 10 μm to 500 μm.4. The circuit board of claim 1 , wherein said insulating substrate is made from a ceramic material claim 1 , and said electrically conductive layers are made from copper.5. A method for forming a stress-reduced circuit board comprising the ...

CONFORMAL COATING MATERIALS

In an example, a process for reversibly bonding a conformal coating to a dry film solder mask (DFSM) material is disclosed. The process includes applying a first conformal coating material to a DFSM material. The first conformal coating material includes a first functional group, and the DFSM material includes a second functional group that is different from the first functional group. The process also includes reversibly bonding the first conformal coating material to the DFSM material via a chemical reaction of the first functional group and the second functional group. 1. A process for reversibly bonding a conformal coating material to a dry film solder mask (DFSM) material , the process comprising:applying a first conformal coating material to a dry film solder mask (DFSM) material, wherein the first conformal coating material includes a first functional group, and wherein the DFSM material includes a second functional group that is different from the first functional group; andreversibly bonding the first conformal coating material to the DFSM material via a chemical reaction of the first functional group and the second functional group.2. The process of claim 1 , wherein the first functional group includes a dienophile functional group claim 1 , and wherein the second functional group includes a diene functional group.3. The process of claim 2 , further comprising:de-bonding the first conformal coating material from the DFSM material to form a diene-functionalized DFSM material;applying a second conformal coating material to the diene-functionalized DFSM material, wherein the second conformal coating material includes a second dienophile functional group; andreversibly bonding the second conformal coating material to the DFSM material via a chemical reaction of the second dienophile functional group and a diene functional group of the diene-functionalized DFSM material.4. The process of claim 3 , wherein:the first conformal coating material is reversibly ...

STABLE PHOTORESIST COMPOSITIONS COMPRISING ORGANOSULPHUR COMPOUNDS

The present invention provides a photoresist composition Part A, comprising a carboxylic functional ethylenically unsaturated resin having an acid value equal to or greater than 10 mg KOH/g, and an organosulphur compound. The photoresist composition may further comprise a Part B, comprising a resin that may react with the carboxylic groups of Part A. The photoresist compositions are shelf-stable, alkali developable, and provide cured resists with improved surface- and through-cure, improved gloss, and reduced undercut and overcut. 1. An energy curable thermosetting resin composition comprising:a) a carboxylic functional ethylenically unsaturated resin; andb) an organosulphur compound;wherein the acid value of the composition is equal to or greater than 10 mg KOH/g; andwherein the composition is developable with an aqueous alkali solution, such that the uncured composition is removable by an aqueous alkali solution.2. (canceled)3. (canceled)4. The composition of claim 1 , wherein the organosulphur compound is a thiol or thioether.5. The composition of claim 4 , wherein the thiol is a mercaptan.6. The composition of claim 1 , further comprising a resin that is reactive with the carboxylic acid of the carboxylic functional ethylenically unsaturated resin.7. The composition of claim 6 , wherein the resin that is reactive with the carboxylic acid of the carboxylic functional ethylenically unsaturated resin is selected from the group consisting of polyepoxides claim 6 , polyoxetane claim 6 , an aminoresin claim 6 , a blocked isocyanate claim 6 , polyoxazoline claim 6 , and polycarbodiimide.8. The composition of claim 6 , prepared as a 2-pack system claim 6 , wherein:a) Part A comprises a carboxylic functional ethylenically unsaturated resin and an organosulphur compound, wherein the acid value of Part A is equal to or greater than 10 mg KOH/g; andb) Part B comprises a resin that is reactive with the carboxylic acid of Part A.9. (canceled)10. (canceled)11. The composition ...

Substrateless device and the method to fabricate thereof

A substrateless device comprises a plurality of first conductive elements and an encapsulant. The encapsulant encapsulates the plurality of first conductive elements, wherein the locations of the plurality of first conductive elements are fixed by the encapsulant; and a plurality of terminals of the plurality of first conductive elements are exposed outside the encapsulant, wherein the plurality of first conductive elements are not supported by a substrate.

CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

A circuit board including a substrate, a patterned circuit layer and a photo-imaginable dielectric layer is provided. The substrate has a first surface and a second surface opposite to each other. The patterned circuit layer is disposed on the first surface, and a line width of the patterned circuit layer gradually reduces from the first surface towards the second surface. The photo-imaginable dielectric layer is disposed in the substrate corresponding to the patterned circuit layer. In addition, a manufacturing method of the circuit board is also proposed. 1. A circuit board , comprising:a substrate, having a first surface and a second surface opposite to each other;a patterned circuit layer, disposed on the first surface, and a line width of the patterned circuit layer gradually reducing from the first surface towards the second surface; anda patterned photo-imaginable dielectric layer, disposed in the substrate corresponding to the patterned circuit layer.2. The circuit board according to claim 1 , wherein a cross section outline of the patterned circuit layer is an inverted-trapezoid.3. The circuit board according to claim 1 , wherein the substrate has a plurality of through holes respectively connecting the first surface and the second surface.4. The circuit board according to claim 1 , wherein the patterned photo-imaginable dielectric layer correspondingly contacts the patterned circuit layer.5. The circuit board according to claim 1 , further comprising: a first surface finish layer claim 1 , exposed on the second surface and covering a bottom surface of a part of the patterned circuit layer.6. The circuit board according to claim 5 , wherein a composite material of the first surface finish layer comprises Ni claim 5 , Au or an alloy thereof.7. The circuit board according to claim 1 , further comprising: a carrier claim 1 , disposed on the second surface of the substrate.8. The circuit board according to claim 1 , wherein a composite material of the substrate ...

Method for Manufacturing Shape-Retaining Non-Flat Devices

Methods are provided for manufacturing shape-retaining non-flat devices comprising components integrated on a device surface, the non-flat devices being made by deformation of a flat device. Based on the layout of a non-flat device, a layout of a flat device is designed. A method for designing the layout of such a flat device is provided, wherein the method includes inserting mechanical interconnections between pairs of elements to define the position of the elements on a surface of the non-flat device, thus leaving zero or less degrees of freedom for the location of the components. Based on the layout of a flat device thus obtained, the flat device is manufactured and next transformed into the shape-retaining non-flat device by means of a thermoforming process, thereby accurately and reproducibly positioning the elements at a predetermined location on a surface of the non-flat device. 1. A method for designing a layout of a flat device , wherein the method comprises:providing a layout of a non-flat device, the non-flat device having a shape with a surface comprising a non-flat surface part, the non-flat device comprising at least one element positioned at a predetermined location on the surface, the non-flat device comprising a device perimeter delineating a device area of the non-flat device;defining a design area for the layout of the flat device, the design area comprising a flat device area corresponding to the device area of the non-flat device after deformation, the design area further comprising a border area adjacent to the flat device area;if the layout of the non-flat device comprises less than three elements, inserting at least one additional element at a predetermined location within the design area to obtain at least three elements;selecting at least two pairs of elements, each pair of elements consisting of a first element and a second element; wherein the distance for each selected pair is calculated as the shortest distance between the first element ...

Preparation of Electrical Circuits by Adhesive Transfer

Multilayer articles that include electrical circuits are prepared by the adhesive transfer of electrical circuit elements to the surface of an adhesive. A number of different methodologies are used, with all of the methodologies including the use of simple layers of circuit-forming material on a releasing substrate and structuring to generate circuit elements which can be transferred to an adhesive surface. In some methodologies, a structured releasing substrate is used to selectively transfer circuit-forming material, either from protrusions on the releasing substrate or from depressions on the releasing substrate. In other methodologies, an unstructured releasing substrate is used and either embossed to form a structured releasing substrate or contacted with a structured adhesive layer to selectively transfer circuit-forming material. 1. A method of preparing an electrical circuit on a surface comprising:providing a structured releasing substrate comprising a series of protrusions and depressions on the surface of the releasing substrate, and having a fluorinated release layer on the surface of the releasing substrate, wherein the fluorinated release layer comprises a release surface prepared by plasma deposition;preparing a layer of circuit-forming material on the release layer on the surface of the structured releasing substrate;providing an adhesive layer;contacting the adhesive layer to the circuit-forming material on protrusions of the structured releasing substrate; andremoving the adhesive layer from the surface of the structured releasing substrate, such that at least a portion of the circuit-forming material on the protrusions of the structured releasing substrate at least partially adheres to the surface of the adhesive layer upon removal to form an adhesive surface with an electrical circuit on it.2. The method of claim 1 , wherein the series of protrusions and depressions on the surface of the releasing substrate comprise a pattern of hemispheres claim ...

METHOD FOR PRODUCING A FLEXIBLE DEVICE, FLEXIBLE ELECTRONIC DEVICE AND FLEXIBLE ARRANGEMENT OF A PLURALITY OF ELECTRONIC DEVICES

A method for producing a flexible device is described. The method includes providing a support substrate, coating the support substrate with an adhesive layer, providing a device having a microstructure on the adhesive layer, attaching a flexible substrate to the device, and removing the adhesive layer. 1. A method for producing a flexible device , the method comprising:providing a support substrate,coating the support substrate with an adhesive layer, the adhesive layer comprising a decomposable material, the decomposable material being a positive photo resist material or a negative photo resist material;providing a device having a microstructure on the adhesive layer,attaching a flexible substrate to the device, andremoving the adhesive layer.2. (canceled)3. The method of claim 1 , wherein the decomposable material is a light-sensitive material.4. The method of claim 1 , wherein the decomposable material is a dissolvable material.5. (canceled)6. The method of claim 1 , wherein providing the device having the microstructure on the adhesive layer comprises depositing one or more layers of functional materials.7. The method of claim 6 , wherein providing the device having the microstructure on the adhesive layer further comprises patterning the one or more layers of functional materials.8. The method of claim 1 , wherein attaching the flexible substrate to the device comprises attaching the flexible substrate to the device via an adhesive provided on the flexible substrate.9. The method of claim 1 , wherein removing the adhesive layer comprises decomposing the adhesive layer.10. The method of claim 9 , wherein decomposing the adhesive layer comprises dissolving the adhesive layer.11. The method of claim 9 , wherein decomposing the adhesive layer comprises exposing the adhesive layer to light.12. The method of claim 1 , wherein the support substrate is a flexible substrate.13. A method for producing a flexible device claim 1 , the method comprising:providing a support ...

High temperature resistant masking adhesive composition

Hot melt processable adhesive compositions to mask electronic components include at least one block copolymer, at least one tackifying resin, at least one semi-crystalline polyolefin polymer, at least one plasticizer, and at least one anti-oxidant. The adhesive composition is a hot melt processable pressure sensitive adhesive composition that is thermally stable, such that the composition when disposed on a surface withstands heating to 260° C. without degradation or flowing, remains optically transparent, and after heating to 260° C. remains cleanly removable.

Carrier-Attached Copper Foil, Laminate, Method For Manufacturing Printed-Wiring Board And Method For Manufacturing Electronic Device

A carrier-attached copper foil having good circuit formability is provided. The carrier-attached copper foil has a carrier, an intermediate layer and an ultra-thin copper layer in this order, the number of crystal grains per unit cross-sectional area of the ultra-thin copper layer in the through-thickness direction is 0.1 to 5 grains/μm, and a ten point average roughness Rz of a surface on a side of the ultra-thin copper layer is 0.1 to 2.0 μm. 1. A carrier-attached copper foil having a carrier , an intermediate layer and an ultra-thin copper layer in this order ,{'sup': '2', 'wherein a number of crystal grains per unit cross-sectional area of the ultra-thin copper layer in a through-thickness direction is 0.1 to 5 grains/μm, and a ten point average roughness Rz of a surface on a side of the ultra-thin copper layer is 0.1 to 2.0 μm.'}2. The carrier-attached copper foil according to claim 1 , wherein the ten point average roughness Rz of the surface on the side of the ultra-thin copper layer is 0.11 to 1.9 μm.3. The carrier-attached copper foil according to claim 2 , wherein the ten point average roughness Rz of the surface on the side of the ultra-thin copper layer is 0.12 to 1.8 μm.4. The carrier-attached copper foil according to claim 1 , wherein the number of crystal grains per unit cross-sectional area of the ultra-thin copper layer in the through-thickness direction is 0.2 to 4.8 grains/μm.5. The carrier-attached copper foil according to claim 4 , wherein the number of crystal grains per unit cross-sectional area of the ultra-thin copper layer in the through-thickness direction is 0.3 to 4.5 grains/μm.6. The carrier-attached copper foil according to claim 1 , wherein the number of crystal grains per unit cross-sectional area of the ultra-thin copper layer in the through-thickness direction is 1.15 grains/μmor less.7. The carrier-attached copper foil according to claim 1 , wherein the average grain size of crystal grains that form the ultra-thin copper layer is ...

Reflective photomask blank, reflective photomask, and integrated circuit device manufactured by using reflective photomask

A reflective photomask blank, a reflective photomask and an integrated circuit device manufactured by using a reflective photomask, include a multi-layered reflection layer; a capping layer on the multi-layered reflection layer and including a first transition metal; a passivation film contacting at least a portion of the capping layer on a side opposite to the multi-layered reflection layer and including a second transition metal and a nitrogen (N) atom; and a light absorption pattern covering a portion of the capping layer.

Embedding Component in Component Carrier by Component Fixation Structure

A method of manufacturing a component carrier, includes providing a base structure having a main surface that is at least partially covered by a component fixation structure; providing a component, the component intrinsically comprising warpage; mounting the component on a surface provided on a plate structure and/or on the base structure to remove the warpage of the component at least partially; and fixating the component to the component carrier through the component fixation structure. 120.-. (canceled)21. A method of manufacturing a component carrier , the method comprising:providing a base structure having a main surface that is at least partially covered by a component fixation structure;providing a component, the component intrinsically comprising warpage;mounting the component on a surface provided on a plate structure and/or on the base structure to remove the warpage of the component at least partially; andfixating the component to the component carrier through the component fixation structure.22. The method according to claim 21 , wherein mounting the component on the surface comprises adhering the component to said surface.23. The method according to claim 21 , wherein said surface comprises a planar sticky surface.24. The method according to claim 21 , further comprising:removing the plate structure after the fixation of the component to the component carrier.25. The method according to claim 21 , wherein the plate structure is an integral part of the component carrier.26. The method according to claim 21 , wherein mounting the component on the surface comprises applying a pressure on the component to force it against said surface.27. The method according to claim 21 , wherein mounting the component on the surface comprises applying heat to at least one of the component and the surface.28. The method according to claim 21 , wherein the component fixation structure is placed between the component and the base structure.29. The method according to claim ...

PRINT HEAD MAINTENANCE

A maintenance unit for an inkjet system with a print head assembly having at least one print head being an integral unit configured to eject droplets of ink fluid from nozzles arranged in a surface of the at least one print head towards a substrate includes a wiper to wipe along the surface of the at least one print head; a force actuator to apply a force to the wiper in a direction perpendicular to the surface of the at least one print head; a force measuring unit configured to determine a wiping force with which the wiper is pressed against the surface of the at least one print head; and a controller configured to control the force applied by the force actuator in dependency of an output of the force measuring unit in order to press the wiper against the surface of a print head with a predetermined wiping force. 1. A maintenance unit for an inkjet system with a print head assembly , said print head assembly comprising at least one print head , the at least one print head being an integral unit configured to eject droplets of ink fluid from nozzles arranged in a surface of the at least one print head towards a substrate , the maintenance unit comprising:a wiper to wipe along the surface of the at least one print head;a force actuator to apply a force to the wiper in a direction perpendicular to the surface of the at least one print head;a force measuring unit configured to determine a wiping force with which the wiper is pressed against the surface of the at least one print head; anda controller configured to control the force applied by the force actuator in dependency of an output of the force measuring unit in order to press the wiper against the surface of a print head with a predetermined wiping force.2. The maintenance unit for an inkjet system according to claim 1 , wherein the maintenance unit further comprises:a position sensor to measure the position of the wiper relative to the surface of the at least one print head; anda set point generator for ...

METHOD OF MANUFACTURING A THIN SUPPORT PACKAGE STRUCTURE

A method of manufacturing a thin support package structure includes the steps of: preparing a support plate formed with a plurality of grooves adjacent to an outer rim thereof, forming a releasing material layer on the support plate; forming a first circuit layer on the releasing material layer so as to form a thin circuit board; forming a dielectric layer on the releasing material layer; forming a plurality of openings in the dielectric layer; forming a second circuit layer on the dielectric layer; forming connection plugs by filling the openings; forming a solder mask on the dielectric layer; forming a plurality of notches on the lower surface of the support plate to communicate with the grooves, respectively; and removing the central part of the support plate between the notches and the central part of the releasing material on the support plate. 1. A method of manufacturing a thin support package structure , comprising steps of:preparing a support plate, which has an upper surface formed with a plurality of grooves adjacent to a rim of the support plate;forming a releasing material layer on the upper surface of the support plate and sidewalls of the grooves;forming a first circuit layer on the releasing material layer not corresponding to the grooves so as to form a thin circuit board, wherein the first circuit layer includes a plurality of first circuit patterns and a plurality of first connection pads connected with the first circuit patterns;forming a dielectric layer on the releasing material layer, wherein the dielectric layer covers the first circuit layer without filling the grooves;forming a plurality of openings on the dielectric layer, wherein each opening corresponds to the connection pad;forming a second circuit layer on the dielectric layer, wherein the openings are filled with the second circuit layer to form connection plugs, each connection plug is connected with the corresponding first connection pad, the second circuit layer includes a ...

COPPER FOIL PROVIDED WITH CARRIER FOIL, MANUFACTURING METHOD OF THE COPPER FOIL PROVIDED WITH CARRIER FOIL, AND COPPER CLAD LAMINATE FOR LASER DRILLING MANUFACTURED BY USING THE COPPER FOIL PROVIDED WITH CARRIER FOIL

An object of the present invention is to improve the laser drilling performance of a copper clad laminate whose black-oxide treated surface is used as a laser drilled surface. To achieve the object, a copper foil provided with a carrier foil comprising a layer structure of the carrier foil/the releasing layer/the bulk copper layer characterized in that metal element-containing particles are disposed between the releasing layer and the bulk copper layer is employed. If the present copper foil provided with a carrier foil is used, a black-oxide treated layer having a color tone excellent in the laser drilling performance can be formed on the surface of the bulk copper layer in the copper clad laminate manufactured. 1. A copper foil provided with a carrier foil comprising a layer structure of a carrier foil/a releasing layer/a bulk copper layer ,wherein metal element-containing particles are disposed between the releasing layer and the bulk copper layer.2. The copper foil provided with a carrier foil according to claim 1 , wherein the metal element-containing particles contain one or more of elements selected from nickel claim 1 , cobalt claim 1 , molybdenum claim 1 , tin and chromium.3. The copper foil provided with a carrier foil according to claim 1 , wherein the metal element-containing particles are disposed to make the amount transferred on the surface of the bulk copper layer after releasing carrier foil (F) 0 mgs/m Подробнее

PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME

A printed wiring board includes an insulating layer, a first conductor layer embedded into a first surface of the insulating layer and including connecting portions to connect an electronic component, a second conductor layer projecting from a second surface of the insulating layer, a solder resist layer covering the first conductor layer and having an opening structure exposing the connecting portions, a barrier metal layer formed on the connecting portions such that the barrier layer is projecting from the first surface of the insulating layer, and metal posts formed on the barrier layer such that the metal posts are positioned on the connecting portions, respectively. Each metal post has width which is greater than width of a respective connecting portion, and the barrier metal layer includes a metal material which is different from a metal material forming the metal posts and a metal material forming the first conductor layer. 1. A printed wiring board , comprising:a resin insulating layer;a first conductor layer embedded into a first surface of the resin insulating layer and comprising a plurality of connecting portions positioned to connect an electronic component;a second conductor layer projecting from a second surface of the resin insulating layer on an opposite side of the resin insulating layer with respect to the first surface;a solder resist layer formed on the first surface of the resin insulating layer such that the solder resist layer is covering the first conductor layer and has an opening structure exposing the plurality of connecting portions of the first conductor layer;a barrier metal layer formed on the plurality of connecting portions of the first conductor layer such that the barrier layer is projecting from the first surface of the resin insulating layer; anda plurality of metal posts formed on the barrier layer such that the plurality of metal posts is positioned on the plurality of connecting portions of the first conductor layer, ...

METHOD FOR PRODUCING A CIRCUIT BOARD ELEMENT

The invention relates to a method for producing a circuit board element having at least one electronic component, which component has a connection side defined by electrical contacts or a conductive layer and is connected to a temporary carrier for positioning and embedded in an insulating material; the component is attached in a specified position directly to a plastic film as a temporary carrier, whereupon a composite layer having at least a carrier and an electrical conductor, preferably also having an insulating material, is attached on the side of the component opposite the plastic film, with the carrier facing away from the component, and thereafter the plastic film is removed; then the component is embedded in insulating material, After the embedding of the component in the insulating material, an additional composite layer is preferably attached to the component and the embedding of the component on the side opposite the first composite layer. 1112912212447655712159. A method for producing a printed circuit board element comprising at least one electronic component () which has a connection side defined by electrical contacts or a conductive layer , wherein the component () for positioning is connected to a temporary carrier () and is embedded in an insulating material () , characterised in that the component () is affixed directly on a plastic film () as a temporary carrier () in a predetermined position , whereupon , on the side of the component () opposite the plastic film () , a composite layer ( , ′) with at least one carrier () and an electrical conductor () , preferably also with an insulating material ( , A) , with the carrier () facing away from the component () , is affixed and thereafter the plastic film () is detached , and in that the component () is then embedded in insulating material (A; ).215911131412441. The method according to claim 1 , characterised in that after the embedding of the component () in insulating material (A; ) a further ...

Carrier-Attached Copper Foil, Laminate, Method For Producing Printed Wiring Board, And Method For Producing Electronic Device

Provided herein is a carrier-attached copper foil having desirable fine circuit formability. The carrier-attached copper foil includes a carrier, an interlayer, and an ultrathin copper layer in this order, wherein D2-D1 is 0.30 to 3.83 μm, where D1 is the gravimetrically measured thickness of the carrier-attached copper foil excluding the carrier and the interlayer, and D2 is the maximum thickness of the layer remaining on a bismaleimide-triazine resin substrate in case of detaching the carrier after the carrier-attached copper foil is laminated to the resin substrate from the ultrathin copper layer side by being heat pressed under a pressure of 20 kgf/cm 2 at 220° C. for 2 hours.

FLEXIBLE SUBSTRATE ASSEMBLY AND ITS APPLICATION FOR FABRICATING FLEXIBLE PRINTED CIRCUITS

A method of fabricating a flexible substrate assembly includes forming a first polyimide layer on a rigid support base, wherein the step of forming the first polyimide layer includes incorporating in a polyamic acid solution, an adhesion promoting agent and a release agent for achieving different adhesion strength at two opposite sides of the first polyimide layer, and forming a flexible second polyimide layer on the first polyimide layer, the second polyimide layer being adhered in contact with the first polyimide layer, and a peeling strength between the first and second polyimide layers being less than a peeling strength between the first polyimide layer and the support base so that the second polyimide layer is peelable from the first polyimide layer while the first polyimide layer remains adhered in contact with the support base. 1. A method of fabricating a flexible substrate assembly , comprising:forming a first polyimide layer on a rigid support base, wherein the step of forming the first polyimide layer includes incorporating in a polyamic acid solution, an adhesion promoting agent and a release agent for achieving different adhesion strength at two opposite sides of the first polyimide layer; andforming a flexible second polyimide layer on the first polyimide layer, the second polyimide layer being adhered in contact with the first polyimide layer, and a peeling strength between the first and second polyimide layers being less than a peeling strength between the first polyimide layer and the support base so that the second polyimide layer is peelable from the first polyimide layer while the first polyimide layer remains adhered in contact with the support base.2. The method according to claim 1 , wherein the support base is made of a rigid material including glass claim 1 , metal or silicon.3. The method according to claim 1 , wherein the adhesion promoting agent includes a silane compound.4. The method according to claim 1 , wherein the adhesion promoting ...

METHOD OF FORMING PATTERN AND METHOD OF PRODUCING PROCESSING SUBSTRATE,OPTICAL PART, CIRCUIT BOARD, OR ELECTRONIC PART

A pattern is formed by arranging a photocurable composition on a substrate; bringing a mold having a concavo-convex pattern into contact with the composition; irradiating the composition with light to form a cured film; releasing the mold from the cured film; forming a reversal layer on the cured film having a concavo-convex pattern transferred from the mold; partially removing the reversal layer to expose the convexes of the pattern in such a manner that the reversal layer remains in the concaves of the pattern formed on the cured film; and etching the photocurable composition layer using the reversal layer remaining in the concaves as a mask to form a reversal pattern, wherein the mold is brought into contact with the photocurable composition in an atmosphere of a soluble gas having a solubility in the composition; and the soluble gas has a saturation solubility of 38% by volume or more. 2. The method of forming a pattern according to claim 1 , wherein the photocurable composition at least includes a polymerizable compound (A) and a photopolymerization initiator (B).3. The method of forming a pattern according to claim 1 , wherein the photocurable composition has a viscosity of 1 mPa*s or more and 12 mPa*s or less.4. The method of forming a pattern according to claim 1 , wherein the mold has a concavo-convex pattern height of 10 nm or more and 30 nm or less.5. The method of forming a pattern according to claim 1 , wherein the photocurable composition further includes a solvent (D).6. The method of forming a pattern according to claim 1 , wherein the reversal layer is made of a spin-on-glass material.7. The method of forming a pattern according to claim 1 , wherein the substrate has an outermost layer of a carbon material.8. The method of forming a pattern according to claim 1 , wherein the mold has a surface of quartz.9. The method of forming a pattern according to claim 1 , wherein the bringing of the mold into contact with the photocurable composition is ...

SMART CONNECTOR AND METHOD OF MANUFACTURING SAME USING AN APPLICATION SPECIFIC ELECTRONICS PACKAGING MANUFACTURING PROCESS

In an embodiment, a smart connector includes an Application Specific Electronics Packaging (ASEP) device formed by an ASEP manufacturing process, and a separate printed circuit board electrically connected to electrical components of the ASEP device. The ASEP manufacturing process includes forming a continuous carrier web having a plurality of lead frames, overmolding a substrate onto the fingers of each lead frame, each substrate having a plurality of openings which exposes a portion of the fingers, electroplating the traces, and electrically attaching at least one electrical component to the traces to form a plurality of ASEP devices. In some embodiments, the printed circuit board has electrical components configured to control the functionality of the electrical components. In some embodiments, the printed circuit board has electrical components configured to modify properties of the smart connector. 1. A smart connector comprising:an Application Specific Electronics Packaging; device, wherein forming the Application Specific Electronics Packaging device comprises: forming a continuous carrier web haying a plurality of lead frames, each lead frame defining an opening and haying a plurality of fingers which extend into the opening, overmolding a substrate onto the fingers of each lead frame, each substrate haying a plurality of openings provided therethrough which exposes a portion of the fingers to form exposed portions, electroplating the traces, and electrically attaching at least one electrical component to the traces to form a plurality of Application Specific Electronics Packaging devices; anda separate printed circuit board electrically connected to the exposed portion of some of the fingers of the Application Specific Electronics Packaging device, the separate printed circuit board having electrical components configured to control the functionality of the at least one electrical component of the Application Specific Electronics Packaging device.2. The ...

METHOD OF PROCESSING CAVITY OF CORE SUBSTRATE

A method of processing a cavity of a core substrate is disclosed. The method of processing a cavity of a core substrate in accordance with an embodiment of the present invention can include: forming a first processing area on one surface of a core substrate, the first processing area being demarcated by a circuit pattern; forming a second processing area on the other surface of the core substrate, the second processing area being demarcated by a circuit pattern; and processing a cavity by removing the entire first processing area from the one surface of the core substrate. 1. A method of processing a cavity of a core substrate , comprising:forming a first processing area on one surface of a core substrate, the first processing area being demarcated by a circuit pattern;forming a second processing area on the other surface of the core substrate, the second processing area being demarcated by a circuit pattern; andprocessing a cavity by removing the entire first processing area from the one surface of the core substrate.2. The method of claim 1 , wherein the second processing area is wider than the first processing area.3. The method of claim 2 , wherein a center of the first processing area and a center of the second processing area are placed on a same vertical line.4. The method of claim 3 , wherein the first processing area and the second processing area have a similar shape.57-. (canceled) This application claims the benefit of Korean Patent Application No. 10-2009-0102504 and 10-2009-0078738, filed with the Korean Intellectual Property Office on Oct. 27, 2009 and Aug. 25, 2009, respectively, the disclosure of which is incorporated herein by reference in its entirety.1. Technical FieldThe present invention is related to a method of processing a cavity of a core substrate.2. Description of the Related ArtIn order to manufacture an embedded substrate, in which an electronic device is embedded in a substrate, it is necessary to process a cavity, which is the space ...

METHOD FOR MANUFACTURING PRINTED CIRCUIT BOARD

Disclosed herein is a method for manufacturing a printed circuit board, wherein a protective film for stripping and a metal layer closely adhered to the protective film for stripping are formed on an inner layer pad to protect the inner layer pad at the time of laser processing related to cavity processing and applying an etchant, thereby making it possible to improve reliability of a product. 1. A method for manufacturing a printed circuit board , the method comprising:preparing a base substrate having a circuit layer formed on one surface thereof or the other surface thereof; the circuit layer including an inner layer pad and a circuit pattern;forming an insulating layer for stripping on an outer surface of the inner layer pad in the circuit layer;forming a first insulating layer on the base substrate as well as the insulating layer for stripping and the circuit layer, the first insulating layer having an open part corresponding to the insulating layer for stripping;forming a copper clad laminate (CCL) layer on the first insulating layer so that a first metal layer for a stopper contacts an upper surface of the insulating layer for stripping exposed through the open part;performing cavity processing so that an edge region in an upper surface of the first metal layer is exposed by performing laser processing on the CCL layer;removing the exposed first metal layer in a thickness direction;removing the insulating layer for stripping exposed by removing the first metal layer in the thickness direction;separating the first metal layer contacting the insulating layer for stripping and the insulating layer for stripping from each other; andremoving the insulating layer for stripping.2. The method as set forth in claim 1 , wherein a diameter of the first metal layer formed to contact the upper surface of the insulating layer for stripping is formed to be larger than that of the insulating layer for stripping claim 1 , in a length direction of the substrate.3. The method ...

METHOD FOR MANUFACTURING RESIN MULTILAYER BOARD

A method for manufacturing a resin multilayer board formed from a thermoplastic resin, which method allows for improvement in accuracy of the position of a component relative to the resin multilayer board, is provided. A method for manufacturing a resin multilayer board includes: a step of bonding a component to a pressure-sensitive adhesive layer of a pressure-sensitive adhesive sheet having the pressure-sensitive adhesive layer on a surface thereof; a step of opposing a thermoplastic resin sheet to the pressure-sensitive adhesive layer, and fixing the component bonded to the pressure-sensitive adhesive sheet and the thermoplastic resin sheet to each other by heating; a step of peeling the pressure-sensitive adhesive sheet from the component fixed to the thermoplastic resin sheet; and stacking and thermally welding a plurality of thermoplastic resin sheets including the thermoplastic resin sheet to which the component has been transferred. 1. A method for manufacturing a resin multilayer board , the method comprising the steps of:bonding a component to a pressure-sensitive adhesive layer of a pressure-sensitive adhesive sheet having the pressure-sensitive adhesive layer on a surface thereof;opposing a thermoplastic resin base material to a side of the pressure-sensitive adhesive sheet to which the pressure-sensitive adhesive layer is bonded, and joining the component bonded to the pressure-sensitive adhesive sheet and the thermoplastic resin base material to each other by heating;peeling the pressure-sensitive adhesive sheet from the component joined to the thermoplastic resin base material; andstacking and thermally welding a plurality of thermoplastic resin base materials including the thermoplastic resin base material to which the component has been joined and from which the pressure-sensitive adhesive sheet has been peeled.2. The method for manufacturing the resin multilayer board according to claim 1 , whereinthe component includes a conductor portion on a ...

CIRCUIT BOARD STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A method for manufacturing a circuit board structure is provided. First, a first circuit layer is formed on a carrier. Then, a first dielectric layer is formed on the carrier and the first circuit layer. Thereafter, at least one first hole is formed in the first dielectric layer to expose a portion of the first circuit layer. Then, a second dielectric layer is formed on the first dielectric layer and the first circuit layer. Thereafter, at least one trench and at least one second hole are formed in the second dielectric layer, in which the trench exposes a portion of the first dielectric layer, and the second hole exposes the portion of the first circuit layer. The second hole is disposed in the first hole. Then, a metal layer is formed to fill the trench and the second hole. 1. A method for manufacturing a circuit board structure , the method comprising:forming a first circuit layer on a carrier;forming a first dielectric layer on the carrier and the first circuit layer;forming at least one first hole in the first dielectric layer, wherein the first hole exposes a portion of the first circuit layer;forming a second dielectric layer on the first dielectric layer and the first circuit layer;forming at least one trench in the second dielectric layer, and forming a second hole in a portion of the second dielectric layer corresponding to the first hole, the trench exposing a portion of the first dielectric layer, the second hole exposing the portion of the first circuit layer, wherein the second hole is disposed in the first hole, and a diameter of the second hole is smaller than a diameter of the first hole; andforming a metal layer filling the trench and the second hole, wherein a portion of the metal layer filling the trench becomes a second circuit layer, and another portion of the metal layer filling the second hole becomes a conductive via.2. The method of claim 1 , wherein the trench and the second hole are formed simultaneously.3. The method of claim 1 , wherein ...

Entry sheet for drilling holes, and hole drilling method using same

Entry sheet for drilling including a metallic foil and a layer of a resin composition, the layer formed on the metallic foil without interposing an adhesion layer, in which the layer of the resin composition has a peak attributable to a carbon atom-oxygen atom double bond appearing at 1700 to 1750 cm −1 and a peak attributable to a carbon atom-oxygen atom single bond appearing at 1080 to 1300 cm −1 in infrared spectroscopy, and when the absorbance at the peak attributable to the carbon atom-oxygen atom double bond appearing at 1700 to 1750 cm −1 is represented by Abs(C═O)L, and the absorbance at the peak of the carbon atom-oxygen atom single bond appearing at 1080 to 1300 cm −1 is represented by Abs(C—O)L, the layer of the resin composition has an absorbance ratio (C) of 0.12 to 1.80, the absorbance ratio (C) represented by the following expression (1). Absorbance ratio( C )=Abs(C═O) L /Abs(C—O) L    Expression (1)

WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE

A wiring substrate has a frame including a metal material and having a connecting portion, and a piece substrate connected to the connecting portion of the frame and having a metal pattern. The metal pattern of the piece substrate has a contour which is corresponding to an outer edge of the connecting portion of the frame. 1. A wiring substrate , comprising:a frame comprising a metal material and having a connecting portion; anda piece substrate connected to the connecting portion of the frame and having a metal pattern,wherein the metal pattern of the piece substrate has a contour which is corresponding to an outer edge of the connecting portion of the frame.2. The wiring substrate according to claim 1 , wherein the frame has a thickness which is less than a thickness of the piece substrate.3. The wiring substrate according to claim 2 , wherein the piece substrate comprises a pair of substrates.4. The wiring substrate according to claim 3 , wherein each of the substrates has a first portion and a second portion claim 3 , and the pair of substrates is formed such that the first portion of one of the substrates is positioned beside the second portion of the other one of the substrates.5. The wiring substrate according to claim 1 , wherein the piece substrate has a fitting portion configured to engage with the connecting portion of the frame claim 1 , and the metal pattern of the piece substrate is formed in the fitting portion of the piece substrate.6. The wiring substrate according to claim 5 , wherein the piece substrate has a main body claim 5 , and the fitting portion of the piece substrate is projecting outward from the main body of the piece substrate.7. The wiring substrate according to claim 1 , wherein the metal pattern of the piece substrate is formed on a surface of the piece substrate.8. The wiring substrate according to claim 1 , wherein the metal pattern of the piece substrate is configured to block laser irradiation.9. The wiring substrate according to ...

WEARABLE SMART DEVICE

The present invention provides to a wearable smart device having electrical wiring comprising a stretchable conductive composition having excellent in durability such as repeated bending properties and repeated twisting properties, a material for realizing the wearable smart device, and a method for producing the wearable start device. 1. A wearable smart device comprising a stretchable electrical wiring comprising a stretchable conductor composition capable of maintaining electrical continuity even after repeating 20% elongation 10 times ,wherein the electrical wiring when unstretched has a line interval of 50 μm or more and 1 mm or less, and the electrical wiring has a ratio of width/thickness in a range of 1 to 50.2. The wearable smart device comprising a stretchable electrical wiring according to claim 1 ,wherein the electrical wiring when unstretched has a line width of 50 μm or more and less than 1 mm.3. The wearable smart device comprising a stretchable electrical wiring according to claim 1 ,wherein a portion of the stretchable conductor composition of the stretchable electrical wiring has a thickness in a range of 3 μm or more and 200 μm or less.4. The wearable smart device comprising a stretchable electrical wiring according to claim 1 ,{'sup': '−3', 'wherein a specific resistance of the stretchable conductor composition of the stretchable electrical wiring when unstretched is 1×10Ωcm or less.'}5. The wearable smart device comprising a stretchable electrical wiring according to claim 1 ,wherein the stretchable conductor composition comprises substantially no solvent and comprises at least 40 to 90% by mass of conductive particles having an average particle diameter of 0.5 μm or more and 5 μm or less, and 15 to 60% by mass of a non-crosslinked elastomer.6. The wearable smart device comprising a stretchable electrical wiring according to claim 1 ,wherein the stretchable conductor composition comprises substantially no solvent and comprises at least 40 to 83% ...

Nanoparticle ink compositions, process and applications

Provided herein are conductive ink compositions having a good balance between adhesion to substrate, nanoparticle stability, the ability to be sintered at relatively low temperatures, and good electrical conductivity. In one aspect, there are provided conductive networks prepared from compositions according to the present invention. In certain aspects, such conductive networks are suitable for use in touch panel displays. In certain aspects, the invention relates to methods for adhering nanoparticulate silver to a non-metallic substrate. In certain aspects, the invention relates to methods for improving the adhesion of nanoparticulate silver-filled formulation to a non-metallic substrate.

ELEMENT SUBSTRATE, DISPLAY APPARATUS AND MANUFACTURING METHOD OF ELEMENT SUBSTRATE

An element substrate comprises a flexible substrate, an element layer, a buffer layer and an interface layer. The element layer is disposed on the flexible substrate. The buffer layer is disposed on the flexible substrate. The buffer layer and the element layer are disposed on the opposite sides of the flexible substrate. The interface layer is disposed between the flexible substrate and the buffer layer and includes partial material of both of the flexible substrate and the buffer layer. A display apparatus including the element substrate and a manufacturing method of the element substrate are disclosed. 1. An element substrate , comprising:a flexible substrate;an element layer disposed on the flexible substrate;a buffer layer disposed on the flexible substrate and disposed on the opposite sides of the flexible substrate with the element layer; andan interface layer disposed between the flexible substrate and the buffer layer and including partial material of both of the flexible substrate and the buffer layer.2. The element substrate as recited in claim 1 , wherein the flexible substrate includes organic polymer material.3. The element substrate as recited in claim 1 , wherein the buffer layer includes polymer material of polyimide (PI) claim 1 , polyamic acid claim 1 , acrylic or polysiloxane.4. The element substrate as recited in claim 1 , wherein the interface layer is formed by an interpenetrating polymer network (IPN).5. The element substrate as recited in claim 1 , further comprising:a de-bonding layer disposed on the buffer layer.6. A display apparatus claim 1 , comprising:an element substrate comprising:a flexible substrate;an element layer disposed on the flexible substrate;a buffer layer disposed on the flexible substrate and disposed on the opposite sides of the flexible substrate with the element layer; andan interface layer disposed between the flexible substrate and the buffer layer and including partial material of both of the flexible substrate and ...

CIRCUIT BOARD AND METHOD OF MANUFACTURING CIRCUIT BOARD

The circuit board provided with a first conductive pattern and a second conductive pattern performed by different types of surface treatments are disclosed. The circuit board in accordance with one embodiment of the present invention forms the first conductive pattern and the second conductive pattern on an insulating layer, wherein the first metal plating layer and the second metal plating layer are formed on the surface of the first conductive pattern, the second metal plating layer is formed on the surface of the second conductive pattern, and the second metal plating layer is made of the material different from that of the first metal plating layer to be exposed to the outside, whereby the pattern pitch is easily reduced, the reduction of the electrical characteristics due to the surface treatment can be minimized and the efficiency of the manufacturing process may be improved. 1. A circuit board comprising:an insulating layer;a first conductive pattern formed on a surface of the insulating layer and provided with a first metal plating layer and a second metal plating layer; anda second conductive pattern formed on the surface of the insulating layer and provided with a second metal plating layer,wherein the first metal plating layer and the second metal plating layer are made of different metals.2. The circuit board according to claim 1 , wherein the first metal plating layer is in contact with a surface of the first conductive pattern and the second metal plating layer is in contact with the second conductive pattern.3. The circuit board according to claim 1 , wherein the second metal plating layer is exposed to an outside of the circuit board.4. The circuit board according to claim 1 , wherein the first metal plating layer is formed on a surface of the first conductive pattern and the second metal plating layer is formed on a surface of the first metal plating layer.5. The circuit board according to claim 1 , wherein the first metal plating layer is formed on ...

FAN-OUT WAFER LEVEL PACKAGES HAVING PREFORMED EMBEDDED GROUND PLANE CONNECTIONS

Fan-Out Wafer Level Packages (FO-WLPs) having Embedded Ground Plane (EGP) connections are provided. In one embodiment, the FO-WLP includes a molded package body having a frontside and an opposing backside. An EGP and a first preformed EGP connection are contained within the molded package body. The first preformed EGP connection is bonded to the EGP and extends therefrom to the backside of the molded package body. The FO-WLP further includes an electrically-conductive structure, such as an Electromagnetic Interference (EMI) shield, provided on the backside of the molded package body. The electrically-conductive structure is electrically coupled to the EGP through the first preformed EGP connection. 1. A Fan-Out Wafer Level Package (FO-WLP) , comprising:a molded package body having a frontside and an opposing backside;an Embedded Ground Plane (EGP) contained within the molded package body;a first preformed EGP connection further contained within the molded package body, the first preformed EGP connection bonded to the EGP and extending therefrom to the backside of the molded package body; andan electrically-conductive structure located on the backside of the molded package body, the electrically-conductive structure electrically coupled to the EGP through the first preformed EGP connection.2. The FO-WLP of wherein the electrically-conductive structure comprises an Electromagnetic Interference (EMI) shield at least partially covering the backside of the molded package body.3. The FO-WLP of wherein the EMI shield comprises a substantially continuous claim 2 , electrically-conductive layer deposited onto the backside of the molded package body and in contact with the first preformed EGP connection.4. The FO-WLP of further comprising:a semiconductor die embedded in the molded package body; andone or more Redistribution Layers (RDLs) containing interconnect lines electrically coupled to the semiconductor die and to the EGP.5. The FO-WLP of wherein the EGP comprises:an ...

POLYIMIDE FILM AND WIRING BOARD

A polyimide film for production of a wiring board having a metal wiring, which is formed by forming a metal layer on one side (Side B) of the polyimide film, and etching the metal layer; the polyimide film is curled toward the side (Side A) opposite Side B; and the curling of the polyimide film is controlled so as to reduce the drooping of the wiring board having a metal wiring formed thereon. The handling characteristics and productivity in IC chip mounting may be improved by the use of the polyimide film. 111-. (canceled)12. A polyimide film produced byproviding a solution of a polyimide precursor prepared from an aromatic tetracarboxylic acid component comprising 3,3′,4,4′-biphenyltetracarboxylic dianhydride as a main component and an aromatic diamine component comprising p-phenylenediamine as a main component;flow-casting the polyimide precursor solution on a support, followed by heating, thereby preparing a self-supporting film of a polyimide precursor solution;applying a solution containing a coupling agent onto one side (Side B) of the self-supporting film which has been in contact with the support when producing the film; and 'the polyimide film is curled toward the side (Side A) opposite Side B, and the curling amount toward Side A of the polyimide film is controlled to within a range of from −14 mm to −30 mm.', 'heating the self-supporting film onto which the coupling agent solution is applied to effect imidization; wherein'}13. The polyimide film as claimed in claim 12 , wherein the coupling agent is a silane coupling agent.14. The polyimide film as claimed in claim 12 , wherein the curling of the polyimide film is controlled by adjusting at least one of the content of the solvent in the self-supporting film claim 12 , the inlet temperature of the heating furnace for heating the self-supporting film to effect imidization claim 12 , and the width of the film when both widthwise edges of the film are fixed in the heating furnace.15. A wiring board produced ...

PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME

A printed circuit board is provided. The printed circuit board comprises a base substrate comprising a chip mounting region on an upper surface thereof, a plurality of connection pad structures in the chip mounting region, and an extension pattern on the base substrate, spaced from each of two adjacent connection pad structures from among the plurality of connection pad structures, and extending along the two adjacent connection pad structures. Upper surfaces of the plurality of connection pad structures are positioned at a higher level than an upper surface of the extension pattern. 1. A printed circuit board comprising:a base substrate comprising a chip mounting region on an upper surface thereof;a plurality of connection pad structures in the chip mounting region; andan extension pattern on the base substrate, spaced apart from each of two adjacent connection pad structures, and extending between the two adjacent connection pad structures,wherein upper surfaces of the plurality of connection pad structures are positioned at a higher level than an upper surface of the extension pattern.2. The printed circuit board of claim 1 , wherein substantially no solder resist layer exists between each of the two adjacent connection pad structures and a portion of the extension pattern extending between the two adjacent connection pad structures.3. The printed circuit board of claim 1 , wherein the extension pattern is at least partially embedded in the base substrate.4. The printed circuit board of claim 1 , wherein the upper surface of the extension pattern is positioned at substantially the same level as an upper surface of the base substrate.5. The printed circuit board of claim 1 , wherein the upper surface of the extension pattern is arranged at a lower level than the upper surface of the base substrate.6. The printed circuit board of claim 1 , wherein the extension pattern comprise a recessed portion claim 1 , and a first height of two side walls of the extension ...

PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD

A printed wiring board includes a first circuit substrate having a first surface and a second surface on the opposite side, and a second circuit substrate having a third surface and a fourth surface on the opposite side such that the first circuit substrate is laminated on the third surface and that the first surface and the third surface are opposing each other. The second circuit substrate has a mounting area on the third surface and includes pads positioned to mount an electronic component in the mounting area and a connection wire structure connected to the pads, and the first circuit substrate includes through-hole conductors extending from the first surface to the second surface and connected to the pads through the connection wire structure and has an opening portion formed through the first circuit substrate such that the opening portion is exposing the pads formed in the mounting area. 1. A printed wiring board , comprising:a first circuit substrate having a first surface and a second surface on an opposite side with respect to the first surface; anda second circuit substrate having a third surface and a fourth surface on an opposite side with respect to the third surface such that the first circuit substrate is laminated on the third surface and that the first surface and the third surface are opposing each other,wherein the second circuit substrate has a mounting area on the third surface and comprises a plurality of pads positioned to mount an electronic component in the mounting area and a connection wire structure connected to the plurality of pads, and the first circuit substrate comprises a plurality of through-hole conductors extending from the first surface to the second surface and connected to the plurality of pads through the connection wire structure and has an opening portion formed through the first circuit substrate such that the opening portion is exposing the plurality of pads formed in the mounting area.2. A printed wiring board according ...

FABRICATION OF A FLEXIBLE CIRCUIT BOARD

The present disclosure relates, according to some embodiments, to the fabrication of a flexible circuit board, which includes forming a base layer comprising polyimide, forming a polyimide layer on the base layer, the polyimide layer having a first surface and a second surface opposite to each other, the first surface being peelably adhered in contact with the base layer, forming a metal layer on the second surface of the polyimide layer, and peeling the base layer from the polyimide layer with the metal layer remaining on the second surface of the polyimide layer. 1. A method of fabricating a flexible circuit board , comprising:forming a base layer comprising polyimide;forming a polyimide layer on the base layer, the polyimide layer having a first surface and a second surface opposite to each other, the first surface being peelably adhered in contact with the base layer;forming a metal layer on the second surface of the polyimide layer; andpeeling the base layer from the polyimide layer with the metal layer remaining on the second surface of the polyimide layer.2. The method of claim 1 , wherein the polyimide layer or the base layer has a surface energy less than 35 dyne/cc.3. The method according to claim 1 , wherein the base layer or the polyimide layer comprises a filler having a surface energy less than 35 dyne/cc claim 1 , the filler being comprised of particles having an average particle size equal to or less than 20 μm.4. The method according to claim 1 , wherein the filler is selected from the group consisting of polyvinyl fluoride (PVF) claim 1 , polyfluorinated vinylidene (PVDF) claim 1 , polytetrafluoroethylene (PTFE) claim 1 , fluorinated ethylene propylene (FEP) claim 1 , perfluoropolyether (PEPE) claim 1 , perfluorosulfonic acid (PFSA) claim 1 , perfluoroalkoxy (PFA) claim 1 , chlorotrifluoroethylene (CTFE) and ethylene chlorotrifuloroethylene (ECTFE).5. The method according to claim 1 , wherein the base layer or the polyimide layer comprises siloxane ...

Circuit board, package structure and method for manufacturing same

A circuit board includes at least one core substrate, at least one insulating layer and at least one dielectric sheet. An opening is defined in the insulating layer corresponding to the core substrate. An area of cross-section of the opening is larger than that of the core substrate. The core substrate is received in the opening. The dielectric sheet is positioned on one side surface of the core substrate and the insulating layer. A cavity is defined in the circuit board. A number of pads of the core substrate are exposed via the cavity. The present disclosure also provides a method for manufacturing the circuit board and package structure.

MULTI-LAYER SUBSTRATE STRUCTURE WHICH CAN BE PEELED OFF PRECISELY AND A METHOD FOR MANUFACTURING THE SAME

A multi-layer substrate structure which can be peeled off precisely includes: a substrate; a first flexible dielectric layer formed on the substrate; a peel-off layer formed on the first flexible dielectric layer; and a unit to be peeled off formed on the peel-off layer; wherein an adhesive force between the peel-off layer and the first flexible dielectric layer is smaller than an adhesive force between the first flexible dielectric layer and the substrate, and the substrate, the first flexible dielectric layer, the peel-off layer, and the unit to be peeled off together form the multi-layer substrate structure. A method for manufacturing a multi-layer substrate structure which can be peeled off precisely is also provided. 1. A multi-layer substrate structure which can be peeled off precisely , comprising:a substrate;a first flexible dielectric layer formed on the substrate;a peel-off layer formed on the first flexible dielectric layer; anda unit to be peeled off formed on the peel-off layer;wherein an adhesive force between the peel-off layer and the first flexible dielectric layer is smaller than an adhesive force between the first flexible dielectric layer and the substrate, and the substrate, the first flexible dielectric layer, the peel-off layer, and the unit to be peeled off together form the multi-layer substrate structure.2. The multi-layer substrate structure according to claim 1 , wherein the substrate is a single-layer substrate or a multi-layer substrate.3. The multi-layer substrate structure according to claim 1 , wherein the substrate is selected from the group consisting of a circuit board claim 1 , a glass substrate claim 1 , and a ceramic substrate.4. The multi-layer substrate structure according to claim 1 , wherein the substrate comprises at least one dielectric layer and at least one metal layer which are alternately stacked.5. The multi-layer substrate structure according to claim 4 , wherein the at least one metal layer is selected from the ...

MANUFACTURING METHOD OF METAL STRUCTURE

A manufacturing method of a metal structure is disclosed, which includes the following steps: forming a seed layer on a substrate; forming a patterned metal layer on the seed layer, wherein the patterned metal layer includes a metal member; forming a first patterned photoresist layer on the seed layer, wherein a thickness of the first patterned photoresist layer is less than a thickness of the patterned metal layer; and performing a first patterning process to the seed layer through the first patterned photoresist layer to form a patterned seed layer, wherein after the first patterning process, the metal member includes a first part and a second part, the first part is disposed between the patterned seed layer and the second part, and a width of the first part is greater than a width of the second part. 1. A manufacturing method of a metal structure , comprising:forming a seed layer on a substrate;forming a patterned metal layer on the seed layer, wherein the patterned metal layer comprises a metal member;forming a first patterned photoresist layer on the seed layer, wherein a thickness of the first patterned photoresist layer is less than a thickness of the patterned metal layer; andperforming a first patterning process to the seed layer through the first patterned photoresist layer to form a patterned seed layer,wherein after the first patterning process, the metal member comprises a first part and a second part, the first part is disposed between the patterned seed layer and the second part, and a width of the first part is greater than a width of the second part.2. The manufacturing method of the metal structure according to claim 1 , wherein the first part of the metal member comprises a first side surface claim 1 , the second part of the metal member comprises a second side surface claim 1 , and a gap exists between the first side surface and the second side surface claim 1 , wherein a ratio of the gap to a thickness of the seed layer is greater than or equal ...

MANUFACTURING METHOD OF METAL STRUCTURE

A manufacturing method of a metal structure is disclosed, which includes the following steps: forming a seed layer on a substrate; forming a patterned metal layer on the seed layer, wherein the patterned metal layer includes a metal member; forming a first patterned photoresist layer on the seed layer, wherein a thickness of the first patterned photoresist layer is less than a thickness of the patterned metal layer; and performing a first patterning process to the seed layer through the first patterned photoresist layer to form a patterned seed layer, wherein after the first patterning process, the metal member includes a first part and a second part, the first part is disposed between the patterned seed layer and the second part, and a width of the first part is greater than a width of the second part. 1. A manufacturing method of a metal structure , comprising:forming a seed layer on a substrate;forming a patterned metal layer on the seed layer, wherein the patterned metal layer comprises a metal member;forming a first patterned photoresist layer on the seed layer, wherein a thickness of the first patterned photoresist layer is less than a thickness of the patterned metal layer; andperforming a first patterning process to the seed layer through the first patterned photoresist layer to form a patterned seed layer,wherein after the first patterning process, the metal member comprises a first part and a second part, the first part is disposed between the patterned seed layer and the second part, and a width of the first part is greater than a width of the second part.2. The manufacturing method of the metal structure according to claim 1 , wherein the first part of the metal member comprises a first side surface claim 1 , the second part of the metal member comprises a second side surface claim 1 , and a gap exists between the first side surface and the second side surface claim 1 , wherein a ratio of the gap to a thickness of the seed layer is greater than or equal ...

FAN-OUT WAFER LEVEL PACKAGES HAVING PREFORMED EMBEDDED GROUND PLANE CONNECTIONS AND METHODS FOR THE FABRICATION THEREOF

Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs having Embedded Ground Plane (EGP) connections are provided. In one embodiment, the method includes forming a molded panel around an EGP array from which a plurality of preformed EGP connections project. One or more Redistribution Layers (RDLs) are produced over the molded panel. The molded panel is then singulated to yield a plurality of FO-WLPs each including a molded package body containing an EGP from the EGP array and one or more of preformed EGP connections. 1. A method for fabricating Fan-Out Wafer Level Packages (FO-WLPs) , comprising:forming a molded panel around an Embedded Ground Plane (EGP) array to which a plurality of preformed EGP connections has been bonded;producing one or more Redistribution Layers (RDLs) over the molded panel; andsingulating the molded panel to yield a plurality of FO-WLPs, each FO-WLP including a molded package body containing a singulated EGP separated from the EGP array and one or more of the preformed EGP connections.2. The method of wherein forming comprises forming the molded panel to have a backside to which the preformed EGP connections extend.3. The method of further comprising providing an Electromagnetic Interference (EMI) shield on the backside of the molded package body and electrically coupled to the singulated EGP through the one or more preformed EGP connections.4. The method of wherein the molded panel has a backside and an opposing frontside over which the one or more RDLs are produced claim 1 , and wherein the method further comprises removing material from the backside of the molded panel to expose the plurality of preformed EGP connections.5. The method of further comprising depositing at least one continuous electrically-conductive layer over the backside of the molded panel and in ohmic contact with the plurality of preformed EGP connections claim 4 , the at least one continuous electrically-conductive layer forming Electromagnetic ...

Manufacturing method of multilayer flexible circuit structure

A manufacturing method of multilayer flexible circuit structure including the following steps is provided. Two first flexible substrates are correspondingly bonded on two sides of a release film, and two conductive materials are correspondingly formed on the two first flexible substrates. The two conductive materials are patterned to form two first inner-layer circuits. Two outer build-up structures are bonded on the two corresponding first flexible substrates. The release film is removed, so as to separate the two first flexible substrates. An outer-layer circuit is formed on each of the first flexible substrates and the corresponding outer build-up structure, wherein the outer-layer circuit is connected to the corresponding first inner-layer circuit, and each of the first flexible substrates, the corresponding first inner-layer circuit, the outer build-up structure and the outer-layer circuit correspondingly form a multilayer flexible circuit structure. Another manufacturing method of multilayer flexible circuit structure is also provided.

METHOD FOR MANUFACTURING MULTILAYER WIRING BOARD

A multilayer wiring board has a high degree of freedom of wiring design and can realize high-density wiring, and a method to simply manufacture the multilayer wiring board. A core substrate with two or more wiring layers provided thereon through an electrical insulating layer. The core substrate has a plurality of throughholes filled with an electroconductive material, and the front side and back side of the core substrate have been electrically conducted to each other by the electroconductive material. The throughholes have an opening diameter in the range of 10 to 100 μm. An insulation layer and an electroconductive material diffusion barrier layer are also provided, and the electroconductive material is filled into the throughholes through the insulation layer. A first wiring layer provided through an electrical insulating layer on the core substrate is connected to the electroconductive material filled into the throughhole through via. 1. A method for manufacturing a multilayer wiring board comprising a core substrate and two or more wiring layers provided through an electrical insulating layer on the core substrate , said method comprising the steps of:boring pores having an opening diameter in the range of 10 to 100 μm from one side of a core material constituting the core substrate by dry etching utilizing plasma to a predetermined depth;forming an insulation layer and an electroconductive material diffusion barrier layer on the surface of the core material including the inner wall surface of the pores so that the electroconductive material diffusion barrier layer is covered with the insulation layer, and then forming an electroconductive base layer on the insulation layer at least in its part located on the inner wall surface of the pores;forming a desired resist film on the core material excluding the inside of the pores and filling an electroconductive material into the pores by electroplating using the electroconductive base layer as a seed layer;removing ...

PRIMER LAYER FOR PLATING PROCESS, LAMINATE FOR CIRCUIT BOARD AND PRODUCTION METHOD FOR SAME, AND MULTILAYER CIRCUIT BOARD AND PRODUCTION METHOD FOR SAME

Disclosed are a primer layer for plating process exhibiting high adhesiveness to an electroless copper plating and capable of coping with high density of wirings of semiconductor packages; a laminate for wiring board having the primer layer and a method for manufacture thereof; and a multilayer wiring board having the primer layer and a method for manufacture thereof. Specifically disclosed are a primer layer for plating process formed of a resin composition for primer layer including (A) a polyfunctional epoxy resin, (B) an epoxy resin curing agent, and (C) a phenolic hydroxyl group-containing polybutadiene-modified polyamide resin having specified structural units, wherein a blending proportion of the component (C) is 5 parts by mass or more and less than 25 parts by mass based on 100 parts by mass of a total sum of the component (A) and the component (B); a laminate for wiring board having the primer layer and a method for manufacture thereof; and a multilayer wiring board having the primer layer and a method for manufacture thereof. 2. The primer layer for plating process according to claim 1 , having a thickness of from 1 to 10 μm.3. The primer layer for plating process according to claim 1 , wherein the polyfunctional epoxy resin (A) contained in the resin composition for primer layer includes an aralkyl type epoxy resin having a biphenyl structure.4. The primer layer for plating process according to claim 1 , wherein the resin composition for primer layer contains (D) an inorganic filler having an average primary particle diameter of not more than 100 nm.5. The primer layer for plating process according to claim 4 , wherein the inorganic filler (D) is fumed silica.6. The primer layer for plating process according to claim 4 , wherein the inorganic filler (D) is subjected to a surface treatment.7. The primer layer for plating process according to claim 1 , wherein a surface roughness (Ra) of the primer layer for plating process after a roughening treatment is ...

PRINTED WIRING BOARD WITH METAL POST AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD WITH METAL POST

A printed wiring board includes a wiring board, and multiple posts formed on the wiring board and positioned to mount a second printed wiring board onto the wiring board. Each of the metal posts has a first surface connected to the wiring board, a second surface formed to connect the second printed wiring board, and a side surface between the first surface and the second surface, and the side surface of each of the metal posts forms a curved surface. 1. A printed wiring board , comprising:a wiring board; anda plurality of metal posts formed on the wiring board and positioned to mount a second printed wiring board onto the wiring board,wherein each of the metal posts has a first surface connected to the wiring board, a second surface configured to connect the second printed wiring board, and a side surface between the first surface and the second surface, and the side surface of each of the metal posts forms a curved surface.2. A printed wiring board according to claim 1 , wherein each of the metal posts has a thinnest portion between the first surface and the second surface.3. A printed wiring board according to claim 1 , further comprising:a plurality of second joining portions formed on the plurality of meal posts such that each of the second joining portions connects the second printed wiring board and the second surface of each of the metal posts,wherein each of the second joining portions is formed on the second surface and side surface of each of the metal posts.4. A printed wiring board according to claim 3 , further comprising:a plurality of first joining portions formed on the plurality of meal posts such that each of the first joining portions connects the wiring board and the first surface of each of the metal posts,wherein the plurality of first joining portions is made of a material which is different from a material of the plurality of second joining portions.5. A printed wiring board according to claim 3 , further comprising:the second printed wiring ...

MANUFACTURING METHOD OF CIRCUIT CARRIER BOARD STRUCTURE

A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided. 1. A manufacturing method of a circuit carrier board structure , comprising:providing a temporary carrier board;forming a first substrate on the temporary carrier board, wherein the first substrate has a first surface and a second surface opposite to the first surface;providing a second substrate having a third surface and a fourth surface opposite to the third surface;disposing an adhesive layer on one of the first substrate and the second substrate, wherein the adhesive layer is located between the first substrate and the second substrate;combining the second surface of the first substrate to the third surface of the second substrate; andremoving the temporary carrier board,wherein the first substrate is electrically connected to the second substrate.2. The manufacturing method of the circuit carrier board structure of claim 1 , wherein the step of forming the first substrate comprises:forming a release layer on the temporary carrier board; andforming a plurality of first build-up layers stacked on the release layer in sequence,wherein each of the first build-up layers comprises ...

WIRING BODY, WIRING BOARD, TOUCH SENSOR, AND PRODUCTION METHOD FOR WIRING BODY

A wiring body includes a resin layer, an electrode layer provided on a surface of the resin layer at one side and including a first line-like conductor layer, and a lead wiring layer provided on the surface of the resin layer at the one side and including one second line-like conductor layer. The at least one second line-like conductor layer is formed integrally with the electrode layer. The lead wiring layer has a single-layer structure made of a material having same composition as that of a material of which the electrode layer is made, and a following Expression is satisfied: T Подробнее

SUBSTRATE STRUCTURE AND METHOD OF FABRICATING THE SAME

The present invention provides a substrate structure and a method of fabricating the substrate substrure. The method includes: forming a first wiring layer on a first carrier, forming a dielectric layer on the first wiring layer, forming a second wiring layer on the dielectric layer, forming an insulating protection layer on the second wiring layer, forming a second carrier on the insulative protection layer, and remvoing the first carrier. The formation of the second carrier provides the substrate structure with adequate rigidity to avoid breakage or warpage such that the miniaturization requirement can be satisfied. 1. A method of fabricating a substrate structure , comprising:forming on a first carrier a first wiring layer having opposing first and second surfaces, with the first surface of the first wiring layer coupled to the first carrier;forming on the second surface of the first wiring layer a dielectric layer that has at least one hole exposing a portion of the first wiring layer;forming a second wiring layer on the dielectric layer, and forming in the at least one hole, from which the portion of the first wiring layer is exposed, at least a conductive via that is electrically connected to the second wiring layer and the first wiring layer;forming on the dielectric layer and the second wiring layer an insulating protection layer that has at least one opening that exposes a portion of the second wiring layer;forming a second carrier on the insulating protection layer; andremoving the first carrier.2. The method of claim 1 , wherein the first carrier comprises a main body and a seed layer formed on the main body claim 1 , and the first wiring layer is formed on the seed layer.3. The method of claim 2 , wherein the first wiring layer is formed by:forming a patterned resist layer on the seed layer, with a portion of the seed layer exposed from the patterned resist layer and the first wiring layer formed on the exposed portion of the first seed layer; ...

PASSIVES IN THIN FILM

Due to the presence of a glass substrate, it is difficult to fabricate thin conventional passive-on-glass (POG) devices. Also glass dicing has been a throughput bottleneck in fabricating the conventional POG device. To address such disadvantages, devices without the glass substrates are proposed. Support structures may be provided to provide mechanical support. The devices are significantly thinner and allow access to the passive components from both first and second surfaces, which are opposite and exposed surfaces. The proposed POM devices may also be incorporated in a package substrate. 1. A device , comprising:a substrate comprising a first layer with a first surface and a second layer with a second surface, wherein the first and second surfaces are opposite and exposed surfaces of the substrate;a passive component embedded in the substrate;a first connect located in the first layer and a second connect located in the second layer, wherein the first connect is configured to electrically couple to the second connect; anda support structure formed on and/or in the substrate and configured to define an interior region,wherein the first and second connects are within the interior region, and are respectively exposed at the first and second surfaces of the substrate.2. The device of claim 1 , wherein the support structure is configured to be electrically isolated from the first and second connects.3. The device of claim 1 , wherein the support structure is configured to surround the first and second connects.4. The device of claim 1 , wherein the support structure is formed on the first surface and/or on the second surface of the substrate.5. The device of claim 1 , wherein the support structure is embedded at least partially in the substrate.6. The device of claim 5 , wherein the support structure is embedded in an entire thickness of the substrate.7. The device of claim 1 , further comprising a passivation layer on the second surface of the substrate.8. The device ...

DETACH CORE SUBSTRATE AND METHOD FOR MANUFACTURING THEREOF

The present invention relates to a detach core substrate and a method of manufacturing a detach core substrate. In accordance with one embodiment of the present invention, there is proposed a detach core substrate that a conductive layer including a metal layer with an etching property different from copper is formed on a top surface and a bottom surface of an insulating layer formed thereon a surface roughness. At this time, the contact interface between the top surface and the bottom surface of the insulating layer is the detachment interface to be separated during the manufacture of the circuit board. In addition, a method of manufacturing the detach core substrate is proposed. 1. A detach core substrate comprising:an insulating layer provided with a top surface and a bottom surface where surface roughness is formed; andconductive layers including a metal layer with an etching property different from copper and formed on the top surface and the bottom surface of the insulating layer, respectively,wherein interfaces between the top surface and the bottom surface of the insulating layer and the conductive layers are detachment interfaces to be separated during manufacturing a circuit board.2. The detach core substrate according to claim 1 , wherein the metal layer is formed on the top surface and the bottom surface of the insulating layer claim 1 , respectively.3. The detach core substrate according to claim 1 , wherein the conductive layer further includes:a first copper layer formed between the metal layer and the top surface and the bottom surface of the insulating layer, respectively.4. The detach core substrate according to claim 2 , wherein the conductive layer further includes:a second copper layer formed on each outer side surface of the metal layer.5. The detach core substrate according to claim 1 , wherein the metal layer has an etch resistance during copper etching.6. The detach core substrate according to claim 5 , wherein the metal layer includes Ni or ...

SUBSTRATE HAVING TRANSPARENT ELECTRODE FOR FLEXIBLE DISPLAY AND METHOD OF FABRICATING THE SAME

A substrate having a transparent electrode for a flexible display which has flexibility and transparency and is resistant to stress of bending, and a method of fabricating the same are provided. By forming a transparent electrode of nanowires resistant to stress of bending on a substrate formed of a shape memory polymer (SMP) material, an increase in resistance due to bending can be prevented and the original form can be recovered. The method for fabricating a substrate having a transparent electrode for a flexible display includes: applying a nanowire dispersion solution of methanol to a glass substrate to form a nanowire electrode; coating the glass substrate with the nanowire electrode formed thereon, with an acrylic shape memory polymer (SMP) to form an SMP thin film; curing the SMP thin film through UV irradiation to form an SMP substrate; and removing the glass substrate from the SMP substrate. 1. A substrate having a transparent electrode for a flexible display comprising:a substrate of a shape memory polymer (SMP); anda transparent electrode comprising nanowires on the substrate.2. The substrate of claim 1 , wherein the nanowires are made of a material selected from the group consisting of silver claim 1 , a copper oxide (CuO) claim 1 , copper (Cu) claim 1 , or a zinc oxide (ZnO).3. The substrate of claim 1 , wherein the SMP is made of a coating solution obtained by adding a photoinitiator and an additive to monomers A and B.4. The substrate of claim 3 , wherein the monomer A claim 3 , the monomer B claim 3 , the photoinitiator claim 3 , and the additive are contained in amounts of 90 claim 3 , 10 claim 3 , 5 claim 3 , and 0.1 wt % over the entire 105. 1 wt % (solid content 100 wt %) claim 3 , respectively.5. The substrate of claim 3 , wherein the monomer A is are made of a material selected from the group consisting of Ethoxylated(4) bisphenol A dimethacrylate claim 3 , and the monomer B is formed of Ethoxylated(2) bisphenol A dimethacrylate.6. The ...

Fabrication of flexible electronic devices

Disclosed are methods for fabrication of flexible circuits and electronic devices in cost effective manner that can include integration of submicron structures directly onto target substrates compatible with industrial microfabrication techniques. In one aspect, a method to fabricate an electronic device, includes depositing an electrically conductive layer on a processing substrate including a weakly-adhesive interface layer on a support substrate; depositing an insulating layer on the conductive layer to attach to the conductive layer; forming a circuit on the processing substrate by etching selected portions of the conductive layer based on a circuit design; and producing a flexible electronic device by attaching a flexible substrate to the formed circuit on the processing substrate and detaching the circuit and the flexible substrate from the interface layer, in which the flexible electronic device includes the circuit attached to the flexible substrate.