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29-03-2012 дата публикации

DRAWN DUMMY FeCAP, VIA AND METAL STRUCTURES

Номер: US20120077287A1

Автор: Rajni J. Aggarwal, Scott R. Summerfelt

Принадлежит: Texas Instruments Inc

A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.

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Номер записи: 1

14-06-2012 дата публикации

Schottky diode switch and memory units containing the same

Номер: US20120149183A1

Автор: Dadi Setiadi, Insik Jin, Nurul Amin, Venugopalan Vaithyanathan, WEI Tian, Young Pil Kim

Принадлежит: SEAGATE TECHNOLOGY LLC

A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

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Номер записи: 2

28-06-2012 дата публикации

Magnetic tunnel junction device

Номер: US20120161262A1

Автор: Shinji Yuasa

Принадлежит: JAPAN SCIENCE AND TECHNOLOGY AGENCY, National Institute of Advanced Industrial Science and Technology AIST

The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared as follows: A single-crystalline MgO (001) substrate is prepared. An epitaxial Fe(001) lower electrode (a first electrode) is grown on a MgO(001) seed layer at room temperature, followed by annealing under ultrahigh vacuum. A MgO(001) barrier layer is epitaxially formed on the Fe(001) lower electrode (the first electrode) at room temperature, using a MgO electron-beam evaporation. A Fe(001) upper electrode (a second electrode) is then formed on the MgO(001) barrier layer at room temperature. This is successively followed by the deposition of a Co layer on the Fe(001) upper electrode (the second electrode). The Co layer is provided so as to increase the coercive force of the upper electrode in order to realize an antiparallel magnetization alignment.

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Номер записи: 3

05-07-2012 дата публикации

Ferroelectric memory and manufacturing method thereof, and manufacturing method of ferroelectric capacitor

Номер: US20120171783A1

Автор: Kouichi Nagai

Принадлежит: Fujitsu Semiconductor Ltd

Provided is a ferroelectric memory including a silicon substrate, a transistor formed on the silicon substrate, and a ferroelectric capacitor formed above the transistor. The ferroelectric capacitor includes a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film, and a metal film formed on the upper electrode.

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Номер записи: 4

19-07-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120181659A1

Автор: Wensheng Wang

Принадлежит: Fujitsu Semiconductor Ltd

A ferroelectric capacitor formed above a semiconductor substrate includes a lower electrode, a dielectric film (ferroelectric film) having ferroelectric characteristics, and an upper electrode. The upper electrode includes a conductive oxide film made of a ferroelectric material to which conductivity is provided by adding a conductive material such as Ir, and the conductive oxide film is in contact with the dielectric film.

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Номер записи: 5

04-10-2012 дата публикации

Semiconductor Device and Method of Manufacturing the Same

Номер: US20120252187A1

Автор: Dong-Hyun Im, Dong-Hyun Kim, Gyu-Hwan OH, Kyung-min Chung

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other , forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.

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Номер записи: 6

01-11-2012 дата публикации

Semiconductor cell and method for forming the same

Номер: US20120273919A1

Автор: Song Hyeuk Im

Принадлежит: Hynix Semiconductor Inc

A semiconductor cell includes storage node contact plugs disposed on a semiconductor substrate, a bit line formation area which is disposed between the storage node contact plugs and exposes the semiconductor substrate, and an air gap which is in contact with a lower portion of a sidewall of the bit line formation area and extends in a direction perpendicular to a direction in which the bit line formation area extends. Therefore, the coupling effect between adjacent bit lines as well as the coupling effect caused between adjacent storage node contact plugs and the coupling effect caused between the storage node contact plug and the bit line are controlled to improve characteristics of semiconductor devices.

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Номер записи: 7

06-12-2012 дата публикации

Switching device having a non-linear element

Номер: US20120305879A1

Автор: Sung Hyun Jo, Wei Lu

Принадлежит: Crossbar Inc

A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

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Номер записи: 8

14-02-2013 дата публикации

Method for fabricating a damascene self-aligned ferroelectric random access memory (f-ram) device structure employing reduced processing steps

Номер: US20130037897A1

Автор: John Cronin, Shan Sun, Thomas E. Davenport

Принадлежит: Ramtron International Corp

Disclosed is a novel non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM device structure on a planar surface using a reduced number of masks and etching steps.

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Номер записи: 9

23-05-2013 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20130130407A1

Автор: Wensheng Wang

Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

A semiconductor device includes a capacitor, the capacitor includes a lower electrode, which includes platinum, provided above a semiconductor substrate; a first ferroelectric film, which includes lead zirconate titanate added with La, provided on the lower electrode; a second ferroelectric film, which includes lead zirconate titanate added with La, Ca, and Sr, provided directly on the first ferroelectric film, the second ferroelectric film having a thickness smaller than that of the first ferroelectric film and includes amounts of Ca and Sr greater than amounts of Ca and Sr that may be present in the first ferroelectric film; and an upper electrode, which includes a conductive oxide, provided on the second ferroelectric film.

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Номер записи: 10

13-06-2013 дата публикации

Method of manufacturing semiconductor device

Номер: US20130149794A1

Автор: Wensheng Wang

Принадлежит: Fujitsu Semiconductor Ltd

A method of manufacturing a semiconductor device includes: forming a conductive film over a semiconductor substrate; forming a first ferroelectric film over the conductive film; forming an amorphous second ferroelectric film over the first ferroelectric film; forming a transition metal oxide material film containing ruthenium over the second ferroelectric film; forming a first conductive metal oxide film over the transition metal oxide material film without exposing the transition metal oxide material film to the air; annealing and crystallizing the second ferroelectric film; and patterning the first conductive metal oxide film, the first ferroelectric film, the second ferroelectric film, and the conductive film to form a ferroelectric capacitor.

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Номер записи: 11

03-10-2013 дата публикации

Nand memory array with mismatched cell and bitline pitch

Номер: US20130258779A1

Автор: Zengtao Liu

Принадлежит: Individual

Embodiments of the present disclosure describe methods, apparatus, and system configurations for NAND memory arrays with mis-matched cell and bitline pitch. Other embodiments may be described and claimed.

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Номер записи: 12

28-11-2013 дата публикации

Integrated circuit with integrated decoupling capacitors

Номер: US20130313679A1

Автор: Huang-Chun Wen, John A. Rodriguez, Scott Robert Summerfelt, Steven Craig Bartling

Принадлежит: TEXAS INSTRUMENTS INCORPORATED

Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.

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Номер записи: 13

06-02-2014 дата публикации

Switching device having a non-linear element

Номер: US20140034898A1

Автор: Sung Hyun Jo, Wei Lu

Принадлежит: Crossbar Inc

A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

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Номер записи: 14

03-04-2014 дата публикации

Multilayer dielectric memory device

Номер: US20140091429A1

Автор: Kyu S. Min

Принадлежит: Intel Corp

A memory device has multiple dielectric barrier regions. A memory device has multiple barrier regions that provide higher or lower current-voltage slope compared to a memory device having a single barrier region. The device also has electrode regions that provide further control over the current-voltage relationship.

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Номер записи: 15

03-04-2014 дата публикации

Method for fabricating a damascene self-aligned ferrorelectric random access memory (f-ram) having a ferroelectric capacitor aligned with a three dimensional transistor structure

Номер: US20140093983A1

Автор: John Cronin, Shan Sun, Tom E. Davenport

Принадлежит: Cypress Semiconductor Corp

A method for a non-volatile, ferroelectric random access memory (F-RAM) device that includes a ferroelectric capacitor aligned with a preexisting structure is described. In one embodiment, the method includes forming an opening in an insulating layer over a contact in a planar surface of a substrate to expose at least a portion of the contact. Next a self-aligned contact (SAC) is formed electrically coupling to the contact, the SAC medially located in the opening and proximal to a sidewall thereof. A ferroelectric spacer is then formed in the opening medially of the SAC, and a top electrode spacer formed in the opening over the insulating cap and medially of the ferroelectric spacer.

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Номер записи: 16

07-01-2021 дата публикации

Memory block select circuitry including voltage bootstrapping control

Номер: US20210005262A1

Автор: Aaron Yip

Принадлежит: Micron Technology Inc

Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate.

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Номер записи: 17

04-01-2018 дата публикации

Semiconductor memory device and method of manufacturing the same

Номер: US20180006053A1

Автор: Fumiki Aiso, Takuo Ohashi

Принадлежит: Toshiba Memory Corp

According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.

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Номер записи: 18

03-01-2019 дата публикации

Ferroelectric memory cells

Номер: US20190005999A1

Автор: Christopher J. KAWAMURA, Scott J. Derner

Принадлежит: Micron Technology Inc

Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.

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Номер записи: 19

02-01-2020 дата публикации

Ferroelectric-capacitor integration using novel multi-metal-level interconnect with replaced dielectric for ultra-dense embedded sram in state-of-the-art cmos technology

Номер: US20200006352A1

Автор: Daniel Morris, Ian Young, Ruth Brain, Seiyon Kim, Uygar Avci, Yih Wang

Принадлежит: Individual

Embodiments include a memory array and a method of forming the memory array. A memory array includes a first dielectric over first metal traces, where first metal traces extend along a first direction, second metal traces on the first dielectric, where second metal traces extend along a second direction perpendicular to the first direction, and third metal traces on the second dielectric, where third metal traces extend along the first direction. The memory array includes a ferroelectric capacitor positioned in a trench having sidewalls and bottom surface, where the trench has a depth defined from a top surface of first metal trace to the top surface of third metal trace. The memory array further includes an insulating sidewall, a first electrode, a ferroelectric, and a second electrode disposed in the trench, where the trench has a rectangular cylinder shape defined by the first, second, and third metal traces.

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Номер записи: 20

02-01-2020 дата публикации

Method for forming an integrated circuit and an integrated circuit

Номер: US20200006360A1

Автор: Kuo-Chi Tu, Tzu-Yu Chen, Wen-Ting Chu, Yong-Shiuan Tsair

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method for forming an integrated circuit (IC) and an IC are disclosed. The method for forming the IC includes: forming an isolation structure separating a memory semiconductor region from a logic semiconductor region; forming a memory cell structure on the memory semiconductor region; forming a memory capping layer covering the memory cell structure and the logic semiconductor region; performing a first etch into the memory capping layer to remove the memory capping layer from the logic semiconductor region, and to define a slanted, logic-facing sidewall on the isolation structure; forming a logic device structure on the logic semiconductor region; and performing a second etch into the memory capping layer to remove the memory capping layer from the memory semiconductor, while leaving a dummy segment of the memory capping layer that defines the logic-facing sidewall.

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Номер записи: 21

16-01-2020 дата публикации

Disposable laser/flash anneal absorber for embedded neuromorphic memory device fabrication

Номер: US20200020542A1

Автор: Deborah A. Neumayer, Kam-Leung Lee, Martin M. Frank, Son Nguyen, Vijay Narayanan

Принадлежит: International Business Machines Corp

A conformal disposable absorber is disclosed which is capable of providing efficient heat transfer to an embedded memory device during a localized absorber anneal, without adversary impacting the back-end-of-the-line (BEOL) structure. The disposable absorber is composed of an amorphous carbonitride material that can be designed to have a low reflection coefficient for laser/flash illumination, and a high extinction coefficient for efficient laser/flash illumination absorption. The disposable absorber is formed at a temperature of 400° C. or less.

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Номер записи: 22

26-01-2017 дата публикации

Variable capacitance diode, method for producing a variable capacitance diode, and storage device and detector comprising such a variable capacitance diode

Номер: US20170025552A1

Автор: Agnieszka Bogusz, Danilo Buerger, Heidemarie Schmidt, Ilona Skorupa, Laveen Selvaraj, Slawomir Prucnal

Принадлежит: Helmholtz Zentrum Dresden Rossendorf eV, Hemlholtz-Zentrum Dresden-Rossendorf Ev

A capacitance diode or variable capacitance diode includes first and second electrodes and a layer configuration disposed in contact-making fashion between the two electrodes. The layer configuration has, one after the other in a direction from the first electrode towards the second electrode, a layer formed of a ferroelectric material and an electrically insulating layer formed of a dielectric material having electrically charged defects. A method for producing a capacitance diode or a variable capacitance diode, a storage device and a detector including a capacitance diode or a variable capacitance diode are also provided.

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Номер записи: 23

02-02-2017 дата публикации

Metal line connection for improved rram reliability, semiconductor arrangement comprising the same, and manufacture thereof

Номер: US20170033161A1

Автор: Chun-Yang Tsai, Kuo-Ching Huang, Yu-Wei Ting

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.

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Номер записи: 24

30-01-2020 дата публикации

Memory device, method of manufacturing the same, and electronic device including the same

Номер: US20200035696A1

Автор: Huilong Zhu

Принадлежит: Institute of Microelectronics of CAS

A memory device may include first and second pillar-shaped active regions formed on a substrate and extending upward. The first and second active regions are arranged in a first array and a second array, respectively. Each of the first active regions comprises alternatively stacked source/drain layers and channel layers, wherein the channel layers of the respective first active regions at a corresponding level are substantially coplanar with each other, and the source/drain layers of the respective first active regions at a corresponding level are substantially coplanar with each other. Each of the second active regions comprises an active semiconductor layer extending integrally. The memory device may include multiple layers of first storage gate stacks surrounding peripheries of and being substantially coplanar with the respective levels of the channel layers, and multiple layers of second storage gate stacks which surround peripheries of the respective second active regions.

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Номер записи: 25

04-02-2021 дата публикации

Nonvolatile memory device including ferroelectric layer having negative capacitance

Номер: US20210035990A1

Автор: Hyangkeun YOO, Jae Gil Lee, Se Ho LEE

Принадлежит: SK hynix Inc

A nonvolatile memory device according to an aspect of the present disclosure includes a substrate having a channel layer, a gate dielectric layer structure disposed on the channel layer, a ferroelectric layer disposed on the gate dielectric layer structure, and a gate electrode layer disposed on the ferroelectric layer. The gate dielectric layer structure has a positive capacitance. The ferroelectric layer has a negative capacitance. The gate dielectric layer structure includes a charge tunneling layer, a charge trap layer and a charge barrier layer disposed on the channel layer.

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Номер записи: 26

04-02-2021 дата публикации

Integration method for memory cell

Номер: US20210035992A1

Автор: Chih-Hsiang Chang, Fu-Chen Chang, Kuo-Chi Tu, Sheng-Hung SHIH, Tzu-Yu Chen, Wen-Ting Chu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.

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Номер записи: 27

11-02-2016 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20160043165A1

Автор: Hitoshi Saito, Wensheng Wang

Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device includes: a semiconductor substrate; a base above the semiconductor substrate; a first conductive plug in the base; a memory cell region in the base; and a logic circuit region connected to the memory cell region, the logic circuit including a first capacitor. The first capacitor includes: a first bottom electrode, a part of a lower surface of the first bottom electrode being in contact with the first conductive plug; a first insulating film on the first bottom electrode; and a first top electrode on the first insulating film. The first top electrode is spaced apart from the first conductive plug in planar view.

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Номер записи: 28

26-02-2015 дата публикации

Semiconductor device with pads of enhanced moisture blocking ability

Номер: US20150054129A1

Автор: Kaoru Saigoh, Kouichi Nagai

Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

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Номер записи: 29

03-03-2022 дата публикации

Small line or pillar structure and process

Номер: US20220069211A1

Автор: Chiao-Wen Yeh, Hsiang-Lan Lung

Принадлежит: Macronix International Co Ltd

A pillar-shaped structure and a line-shaped structure are described that include a supporting top conductive layer, an active material layer, such as a memory material or switching material, and a bottom conductive layer. The active material layer is more narrow than the supporting top conductive layer. A supporting side insulating layer is formed connecting the top and bottom conductive layers to provide structure stability. A void, or air gap, is formed between the active material layer and the supporting side insulating layer, which can provide improved thermal isolation between adjacent pillar-shaped or line-shaped structures.

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Номер записи: 30

14-02-2019 дата публикации

Void formation in charge trap structures

Номер: US20190051656A1

Автор: Chris M. Carlson, Ugo Russo

Принадлежит: Micron Technology Inc

Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.

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Номер записи: 31

14-02-2019 дата публикации

Apparatuses and methods for reading memory cells

Номер: US20190051657A1

Автор: Yasushi Matsubara

Принадлежит: Micron Technology Inc

Apparatuses and methods for reading memory cells are described. An example method includes sharing a first voltage to increase a voltage of a first sense line coupled to a first capacitor plate of a ferroelectric capacitor of a memory cell, sharing a second voltage to decrease a voltage of a second sense line coupled to a second capacitor plate of the ferroelectric capacitor of the memory cell, sharing a third voltage to increase the voltage of the second sense line, and sharing a fourth voltage to decrease the voltage of the first sense line. A voltage difference between the first sense line and the second sense line that results from the voltage sharing is amplified, wherein the voltage difference is based at least in part on a polarity of the ferroelectric capacitor.

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Номер записи: 32

13-02-2020 дата публикации

Methods of Forming Memory Arrays

Номер: US20200051849A1

Автор: Durai Vishak Nirmal Ramaswamy

Принадлежит: Micron Technology Inc

Some embodiments include an integrated memory having an array of capacitors. The array has edges. The capacitors along the edges are edge capacitors, and the other capacitors are internal capacitors. The edge capacitors have inner edges facing toward the internal capacitors, and have outer edges in opposing relation to the inner edges. An insulative beam extends laterally between the capacitors. The insulative beam is along upper regions of the capacitors. First void regions are under the insulative beam, along lower regions of the internal capacitors, and along the inner edges of the edge capacitors. Peripheral extensions of the insulative beam extend laterally outward of the edge capacitors, and second void regions are under the peripheral extensions and along the outer edges of the edge capacitors. Some embodiments included integrated assemblies having two or more memory array decks stacked on atop another. Some embodiments include methods of forming memory arrays.

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Номер записи: 33

01-03-2018 дата публикации

Hybrid memory device

Номер: US20180059958A1

Автор: Durai Vishak Nirmal Ramaswamy, Kevin J. Ryan, Kirk D. Prall, Robert Quinn

Принадлежит: Micron Technology Inc

Methods, systems, and devices for a hybrid memory device are described. The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.

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Номер записи: 34

03-03-2016 дата публикации

Semiconductor device structures including ferroelectric memory cells

Номер: US20160064655A1

Автор: Beth R. Cook, D.V. Nirmal Ramaswamy, Matthew N. Rocklein, Qian Tao

Принадлежит: Micron Technology Inc

A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

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Номер записи: 35

02-03-2017 дата публикации

Methods of operating ferroelectric memory cells, and related ferroelectric memory cells and capacitors

Номер: US20170062037A1

Автор: Ashonita A. Chavan, Matthew N. Rocklein, Steven C. Nicholes

Принадлежит: Micron Technology Inc

Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.

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Номер записи: 36

17-03-2022 дата публикации

Configurable Three-Dimensional Neural Network Array

Номер: US20220083836A1

Автор: Fu-Chang Hsu, Kevin Hsu

Принадлежит: Individual

Configurable three-dimensional neural network array. In an exemplary embodiment, a three-dimensional (3D) neural network array includes a plurality of stacked synapse layers having a first orientation, and a plurality of synapse lines having a second orientation and passing through the synapse layers. The neural network array also includes synapse elements connected between the synapse layers and synapse lines. Each synapse element includes a programmable resistive element. The neural network array also includes a plurality of output neurons, and a plurality of select transistors connected between the synapse lines and the output neurons. The gate terminals of the select transistors receive input signals.

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Номер записи: 37

17-03-2022 дата публикации

Flash memory having improved performance as a consequence of program direction along a flash storage cell column

Номер: US20220084606A1

Автор: Ali Khakifirooz, Guangyu Huang, Narayanan RAMANAN, Pranav Kalavade, Xiang Yang

Принадлежит: Intel NDTM US LLC

A method is described. The method includes programming a column of flash storage cells in a direction along the column in which a parasitic transistor that resides between a cell being programmed and an immediately next cell to be programmed has lower resistivity as compared to a corresponding parasitic transistor that exists if the programming were to be performed in an opposite direction along the column.

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Номер записи: 38

29-05-2014 дата публикации

Process-compatible sputtering target for forming ferroelectric memory capacitor plates

Номер: US20140147940A1

Автор: Mark Robert Visokay, Scott Robert Summerfelt

Принадлежит: Texas Instruments Inc

A sputtering target for a conductive oxide, such as SrRuO 3 , to be used for the sputter deposition of a conductive film that is to be in contact with a ferroelectric material in an integrated circuit. The sputtering target is formed by the sintering of a powder mixture of the conductive oxide with a sintering agent of an oxide of one of the constituents of the ferroelectric material. For the example of lead-zirconium-titanate (PZT) as the ferroelectric material, the sintering agent is one or more of a lead oxide, a zirconium oxide, and a titanium oxide. The resulting sputtering target is of higher density and lower porosity, resulting in an improved sputter deposited film that does not include an atomic species beyond those of the ferroelectric material deposited adjacent to that film.

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Номер записи: 39

10-03-2016 дата публикации

Ferroelectric memory device

Номер: US20160071852A1

Автор: Fabrice Domingues Dos Santos, Thierry Lannuzel

Принадлежит: Arkema France SA

The invention relates to a ferroelectric memory device comprising at least one layer comprising a ferroelectric polymer, and at least two electrodes either side thereof, the ferroelectric polymer being of general formula P(VDF-X-Y), wherein VDF is vinylidene fluoride motifs, X is trifluoroethylene or tetrafluoroethylene motifs, and Y is motifs from a third monomer, the molar proportion of Y motifs in the polymer being less than or equal to 6.5%.

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Номер записи: 40

27-02-2020 дата публикации

Efficient utilization of memory die area

Номер: US20200066339A1

Автор: Christophe Vincent Antoine Laurent

Принадлежит: Micron Technology Inc

Methods, systems, and apparatus that support efficient utilization of die area for cross-point memory architecture are described. A memory array may include active memory cells overlying each portion of the substrate that includes certain types of support circuitry, such as decoders and sense amplifiers. Boundary tiles, which may be portions of an array having a different configuration from other portions of the array, may be positioned on one side of an array of memory tiles. The boundary tiles may include support components to access both memory cells of neighboring memory tiles and memory cells overlying the boundary tiles. Column lines and column line decoders may be integrated as part of a boundary tile. Access lines, such as row lines may be truncated or omitted at or near borders of the memory portion of the memory device.

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Номер записи: 41

19-03-2015 дата публикации

Thermal Treatment for Reducing Transistor Performance Variation in Ferroelectric Memories

Номер: US20150079698A1

Автор: Kemal Tamer San, Kezhakkedath R. Udayakumar

Принадлежит: Texas Instruments Inc

Thermal treatment of a semiconductor wafer in the fabrication of integrated circuits including MOS transistors and ferroelectric capacitors, including those using lead-zirconium-titanate (PZT) ferroelectric material, to reduce variation in the electrical characteristics of the transistors. Thermal treatment of the wafer in a nitrogen-bearing atmosphere in which hydrogen is essentially absent is performed after formation of the transistors and capacitor. An optional thermal treatment of the wafer in a hydrogen-bearing atmosphere prior to deposition of the ferroelectric treatment may be performed.

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Номер записи: 42

15-03-2018 дата публикации

Memory device and method for manufacturing the same

Номер: US20180076204A1

Автор: Daisuke Matsubayashi

Принадлежит: Semiconductor Energy Laboratory Co Ltd

A memory device that is as small in area as possible and has an extremely long data retention period. A transistor with extremely low leakage current is used as a cell transistor of a memory element in a memory device. Moreover, in order to reduce the area of a memory cell, the transistor is formed so that its source and drain are stacked in the vertical direction in a region where a bit line and a word line intersect each other. Further, a capacitor is stacked above the transistor.

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Номер записи: 43

15-03-2018 дата публикации

Three-dimensional semiconductor memory device

Номер: US20180076212A1

Автор: Jaeduk LEE, Jaesung SIM, Shinhwan Kang, Youngwoo Park, Yunghwan Son

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

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Номер записи: 44

15-03-2018 дата публикации

Integrated ferroelectric capacitor/ field effect transistor structure

Номер: US20180076334A1

Автор: Alexander Reznicek, Pouya Hashemi, Takashi Ando

Принадлежит: International Business Machines Corp

A replacement gate structure (i.e., functional gate structure) is formed and recessed to provide a capacitor cavity located above the recessed functional gate structure. A ferroelectric capacitor is formed in the capacitor cavity and includes a bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure. The bottom electrode structure has a topmost surface that does not extend above the U-shaped ferroelectric material liner. A contact structure is formed above and in contact with the U-shaped ferroelectric material liner and the top electrode structure of the ferroelectric capacitor

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Номер записи: 45

12-06-2014 дата публикации

Nitride-based memristors

Номер: US20140158973A1

Автор: Gilberto Medeiros Ribeiro, Jianhua Yang, R. Stanley Williams

Принадлежит: Hewlett Packard Development Co LP

A nitride-based memristor memristor includes: a first electrode comprising a first nitride material; a second electrode comprising a second nitride material; and active region positioned between the first electrode and the second electrode. The active region includes an electrically semiconducting or nominally insulating and weak ionic switching nitride phase. A method for fabricating the nitride-based memristor is also provided.

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Номер записи: 46

18-03-2021 дата публикации

Semiconductor memory device

Номер: US20210082956A1

Автор: Kunifumi Suzuki, Masumi SAITOH

Принадлежит: Kioxia Corp

Provided is a semiconductor memory device according to an embodiment including: a stacked body including gate electrode layers stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; and a gate insulating layer provided between the semiconductor layer and at least one of the gate electrode layers, and the gate insulating layer including a first region containing a first oxide including at least one of a hafnium oxide and a zirconium oxide, in which a first length of the at least one of the gate electrode layers in the first direction is larger than a second length of the first region in the first direction.

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Номер записи: 47

22-03-2018 дата публикации

Electronic device including a semiconductor memory

Номер: US20180082727A1

Автор: Min-Suk Lee

Принадлежит: SK hynix Inc

This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a contact plug; a first stack structure disposed over the contact plug and coupled to the contact plug, wherein the first stack structure includes a pinning layer controlling a magnetization of a pinned layer; and a second stack structure disposed over the first stack structure and coupled to the first stack structure, wherein the second stack structure includes a MTJ (Magnetic Tunnel Junction) structure which includes the pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein a width of the first stack structure is larger than a width of the contact plug and a width of the second stack structure.

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Номер записи: 48

22-03-2018 дата публикации

Multilevel Ferroelectric Memory Cell for an Integrated Circuit

Номер: US20180082729A1

Автор: Halid MULAOSMANOVIC, Stefan Slesazeck

Принадлежит: NaMLab GmbH

An integrated circuit includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric layer stack comprising at least one ferroelectric material oxide layer. Each of the ferroelectric material oxide layers includes a ferroelectric material that is at least partially in a ferroelectric state. The ferroelectric layer stack comprises at least two ferroelectric domains. Further, the voltage which is to applied to the layer stack to induce polarization reversal differs for the individual domains such that polarization reversal of individual domains or of a portion of the totality of ferroelectric domains within the ferroelectric material of can be attained.

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Номер записи: 49

29-03-2018 дата публикации

Memory Cell Having Resistance Variable Film and Method of Making the Same

Номер: US20180090680A1

Автор: Chern-Yow Hsu, Chia-Shiung Tsai, Ching-Pei Hsieh, Fu-Ting Sung, Shih-Chang Liu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.

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Номер записи: 50

12-04-2018 дата публикации

Ferroelectric composition on semiconductor and method for producing same

Номер: US20180102372A1

Автор: Joseph Ho Yeen Ngai, Kamyar Ahmadi-Majlan, Reza M. Moghadam

Принадлежит: University of Texas System

Techniques for fabricating ferroelectric materials and semiconductor devices using the materials. Material compositions including strontium, zirconium, titanium, and oxygen are disposed on a substrate material to produce ferroelectric devices.

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Номер записи: 51

29-04-2021 дата публикации

Semiconductor devices and methods for fabricating the same

Номер: US20210125993A1

Автор: Chang Mu An, Jong-bom Seo, Sang Yeol Kang, Se Hyoung Ahn, Young-Lim Park

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad, the lower electrode being electrically connected to the landing pad, a dielectric layer on the lower electrode, the dielectric layer extending along a profile of the lower electrode, an upper electrode on the dielectric layer, and an upper plate electrode on the upper electrode and including first fluorine (F) therein, wherein the upper plate electrode includes an interface facing the upper electrode, and wherein the upper plate electrode includes a portion in which a concentration of the first fluorine decreases as a distance from the interface of the upper plate electrode increases.

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Номер записи: 52

18-04-2019 дата публикации

Layer transferred ferroelectric memory devices

Номер: US20190115353A1

Автор: Brian S. Doyle, Charles C. Kuo, Kaan OGUZ, Kevin P. O'brien, Mark L. Doczy, Tejaswi K. Indukuri

Принадлежит: Intel Corp

A monocrystalline metal-oxide stack including a ferroelectric (FE) tunneling layer and a buffer layer is epitaxially grown on a growth substrate. A first polycrystalline metal electrode layer is deposited over the tunneling layer. A bonding material layer is further deposited over the electrode layer. The bonding material layer is then bonded to a material layer on a front or back side of a host substrate that further comprises a transistor cell. Once bonded, the growth substrate may be removed from the metal-oxide stack to complete a transfer of the metal-oxide stack from the growth substrate to the host substrate. A second polycrystalline metal electrode layer is then deposited over the exposed buffer layer, placing both electrodes in close proximity to the FE tunneling layer.

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Номер записи: 53

03-05-2018 дата публикации

Methods of Forming an Array Comprising Pairs of Vertically Opposed Capacitors and Arrays Comprising Pairs of Vertically Opposed Capacitors

Номер: US20180122817A1

Автор: Durai Vishak Nirmal Ramaswamy

Принадлежит: Micron Technology Inc

A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in insulative-comprising material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. A capacitor insulator is formed laterally inward of the upper and lower capacitor electrode linings in the individual capacitor openings. Conductive material is formed laterally inward of the capacitor insulator in the individual capacitor openings and elevationally between the capacitor electrode linings. The conductive material is formed to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors. Additional methods and structure independent of method are disclosed.

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Номер записи: 54

04-05-2017 дата публикации

Rps assisted rf plasma source for semiconductor processing

Номер: US20170125220A1

Автор: Jang-Gyoo Yang, Saurabh Garg, Xinglong Chen

Принадлежит: Applied Materials Inc

Embodiments of the disclosure generally relate to a hybrid plasma processing system incorporating a remote plasma source (RPS) unit with a capacitively coupled plasma (CCP) unit for substrate processing. In one embodiment, the hybrid plasma processing system includes a CCP unit, comprising a lid having one or more through holes, and an ion suppression element, wherein the lid and the ion suppression element define a plasma excitation region, a RPS unit coupled to the CCP unit, and a gas distribution plate disposed between the ion suppression element and a substrate support, wherein the gas distribution plate and the substrate support defines a substrate processing region. In cases where process requires higher power, both CCP and RPS units may be used to generate plasma excited species so that some power burden is shifted from the CCP unit to the RPS unit, which allows the CCP unit to operate at lower power.

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Номер записи: 55

27-05-2021 дата публикации

Redundant array of independent nand for a three-dimensional memory array

Номер: US20210157673A1

Автор: Jung Sheng Hoei, Kishore K. Muchherla, Peter Feeley, Renato C. Padilla, Sampath K. Ratnam, Sivagnanam Parthasarathy

Принадлежит: Micron Technology Inc

The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.

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Номер записи: 56

25-04-2019 дата публикации

3D Processor

Номер: US20190123024A1

Автор: Ilyas Mohammed, Javier Delacruz, Kenneth Duong, Steven L. Teig

Принадлежит: Xcelsis Corp

Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks defined on each die (1) overlap with other circuit blocks defined on one or more other dies, and (2) electrically connect to these other circuit blocks through connections that cross one or more bonding layers that bond one or more pairs of dies. In some embodiments, the overlapping, connected circuit block pairs include pairs of computation blocks and pairs of computation and memory blocks. The connections that cross bonding layers to electrically connect circuit blocks on different dies are referred to below as z-axis wiring or connections. This is because these connections traverse completely or mostly in the z-axis of the 3D circuit, with the x-y axes of the 3D circuit defining the planar surface of the IC die substrate or interconnect layers. These connections are also referred to as vertical connections to differentiate them from the horizontal planar connections along the interconnect layers of the IC dies.

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Номер записи: 57

31-07-2014 дата публикации

Adjustable dummy fill

Номер: US20140215425A1

Автор: Robert G. Fleck, Scott R. Summerfelt

Принадлежит: Texas Instruments Inc

A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2 ). The method includes identifying a sub-region of the substrate ( 210 ). A density of a layer in the sub-region is determined ( 212 ). A pattern of the dummy fill layer is selected to produce a predetermined density ( 216 ). The selected pattern is placed in the sub-region ( 208 ).

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Номер записи: 58

17-05-2018 дата публикации

Writing to cross-point non-volatile memory

Номер: US20180137908A1

Автор: Adam Johnson, Alessandro Calderoni, Bei Wang, Durai Vishak Nirmal Ramaswamy, Wayne Kinney

Принадлежит: Micron Technology Inc

Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.

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Номер записи: 59

17-05-2018 дата публикации

Apparatus and methods including establishing a negative body potential in a memory cell

Номер: US20180137922A1

Автор: Jeremy Binfet, Koji Sakui, Mark Hawes, Toru Tanzawa

Принадлежит: Micron Technology Inc

Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation on the memory cell, in response to a timer, or during an access operation of another memory cell.

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Номер записи: 60

09-05-2019 дата публикации

Applications of back-end-of-line (beol) capacitors in compute-in-memory (cim) circuits

Номер: US20190138893A1

Автор: ABHISHEK Sharma, Amrita MATHURIYA, Gregory K. Chen, Huseyin Ekin Sumbul, Ian A. Young, Jack T. Kavalieros, Nazila Haratipour, Phil Knag, Raghavan Kumar, Ram Krishnamurthy, Sasikanth Manipatruni, Uygar Avci, Van H. Le

Принадлежит: Intel Corp

An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

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Номер записи: 61

08-09-2022 дата публикации

Wakeup free approach to improve the ferroelectricity of feram using a stressor layer

Номер: US20220285374A1

Автор: Bi-Shen LEE, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsun-Chung KUANG, Tzu-Yu Lin, Yi Yang Wei

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.

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Номер записи: 62

26-05-2016 дата публикации

Electronic device and method for fabricating the same

Номер: US20160149121A1

Автор: Choon-Kun Ryu, Hyung-Suk Lee, Jae-Geun Oh

Принадлежит: SK hynix Inc

This technology provides an electronic device and method for fabricating the same. A method for fabricating an electronic device comprising a transistor includes forming a junction region which is partially amorphized in the semiconductor substrate at a side of the gate; forming a metal layer over the junction region; and performing a heat treatment process on the metal layer into a metal-semiconductor compound layer while crystallizing the junction region.

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Номер записи: 63

25-05-2017 дата публикации

Multi-bit ferroelectric memory device and methods of forming the same

Номер: US20170148512A1

Автор: Chandra V. Mouli, D.V. Nirmal Ramaswamy, F. Daniel Gealy, Kamal M. Karda

Принадлежит: Micron Technology Inc

Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.

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Номер записи: 64

25-05-2017 дата публикации

Semiconductor apparatus and method for fabricating the same

Номер: US20170148986A1

Автор: Hyung Keun Kim

Принадлежит: SK hynix Inc

A method for fabricating a semiconductor apparatus includes providing a semiconductor substrate, stacking a conductive layer, a variable resistance layer, and a sacrificial layer on the semiconductor substrate, etching the conductive layer, the variable resistance layer, and the sacrificial layer to form a pillar structure including a lower electrode, a variable resistor device, and a sacrificial layer pattern, removing the sacrificial layer pattern, and forming an upper electrode over the variable resistor device in a hole which is formed by removing the sacrificial layer pattern.

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Номер записи: 65

31-05-2018 дата публикации

Device including a floating gate electrode and a layer of ferroelectric material and method for the formation thereof

Номер: US20180151577A1

Автор: Johannes Mueller, Stefan Flachowsky, Stefan Mueller

Принадлежит: Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV, NaMLab GmbH

An illustrative device disclosed herein includes a semiconductor substrate. The substrate includes a source region, a drain region and a channel region. The channel region is arranged between the source region and the drain region. A gate insulation layer is provided over the channel region. A floating gate electrode is provided over the gate insulation layer. A layer of a ferroelectric material is provided over the floating gate electrode. A top electrode is provided over the layer of ferroelectric material. A projected area of the top electrode onto a plane that is perpendicular to a thickness direction of the semiconductor substrate is smaller than a projected area of the floating gate electrode onto the plane.

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Номер записи: 66

01-06-2017 дата публикации

Electronic device and method for fabricating the same

Номер: US20170154817A1

Автор: Joo-Young Moon

Принадлежит: SK hynix Inc

A semiconductor device may include: a plurality of first contacts arranged at a predetermined distance in a first direction and a second direction crossing the first direction; a plurality of second contacts alternately arranged between the first contacts and arranged at a predetermined distance in the first direction and the second direction; a plurality of dog bone-type conductive lines connected to the second contacts arranged in the second direction, respectively, among the plurality of second contacts, and having concave parts and convex parts; and a plurality of etching prevention patterns formed over the plurality of conductive lines so as to overlap the conductive lines, respectively.

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Номер записи: 67

11-06-2015 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20150162342A1

Автор: Ki Hong Lee, Seung Ho Pyi, Seung Jun Lee

Принадлежит: SK hynix Inc

A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.

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Номер записи: 68

17-06-2021 дата публикации

Three-dimensional semiconductor device

Номер: US20210183861A1

Автор: Hyun-Sil Oh, Kiseok LEE, Min Hee Cho, Minsu Lee, Minwoo Song

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A three-dimensional semiconductor device includes a first channel pattern on and spaced apart from a substrate, the first channel pattern having a first end and a second end that are spaced apart from each other in a first direction parallel to a top surface of the substrate, and a first sidewall and a second sidewall connecting between the first end and the second end, the first and second sidewalls being spaced apart from each other in a second direction parallel to the top surface of the substrate, the second direction intersecting the first direction, a bit line in contact with the first end of the first channel pattern, the bit line extending in a third direction perpendicular to the top surface of the substrate, and a first gate electrode adjacent to the first sidewall of the first channel pattern.

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Номер записи: 69

17-06-2021 дата публикации

Film structure including hafnium oxide, electronic device including the same, and method of manufacturing the same

Номер: US20210183993A1

Автор: Haeryong Kim, Jooho Lee, Jungmin Park, Yongsung Kim

Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided are a film structure including hafnium oxide, an electronic device including the same, and a method of manufacturing the same. The film structure including hafnium oxide includes a hafnium oxide layer including hafnium oxide crystallized in a tetragonal phase, and first and second stressor layers apart from each other with the hafnium oxide layer therebetween and applying compressive stress to the hafnium oxide layer.

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Номер записи: 70

09-06-2016 дата публикации

Semiconductor device

Номер: US20160163635A1

Автор: Jaesun Yun, Jang-Gn Yun, Joon-Sung LIM

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure. A conductive shielding pattern is disposed between the cell semiconductor pattern and the semiconductor substrate and above the first circuit and the first interconnection structure.

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Номер записи: 71

22-09-2022 дата публикации

Three-dimensional memory device structures and methods

Номер: US20220302143A1

Автор: Chung-Liang Cheng

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of fabricating a semiconductor device includes forming a first stack of semiconductor layers on a substrate. The first stack of semiconductor layers includes alternating first and second semiconductor strips. The first and second semiconductor strips includes first and second semiconductor materials, respectively. The method also includes removing the first semiconductor strips to form voids between the second semiconductor strips in the first stack of semiconductor layers. The method further includes depositing a dielectric structure layer and a first conductive fill material in the voids to surround the second semiconductor strips. Further, the method includes removing the second semiconductor strips to form a second set of voids, and depositing a third semiconductor material in the second sets of voids.

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Номер записи: 72

14-05-2020 дата публикации

Vertical memory device having improved electrical characteristics and method of operating the same

Номер: US20200152273A1

Автор: Yo-Han Lee

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of operating a memory device including a substrate; at least one dummy word line over the substrate; a plurality of word lines over the dummy word line; and a plurality of vertical holes extending through the at least one dummy word line and the plurality of word lines in a direction perpendicular to the substrate and classified into channel holes and dummy holes, each of the channel holes being connected to a bit line, the method including: performing an erase operation on dummy cells formed as the dummy word line and the dummy holes; verifying the erase operation; and performing a program operation on at least one of the dummy cells such that the at least one dummy cell has a higher threshold voltage than main cells formed as the dummy word line and the channel holes.

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Номер записи: 73

14-05-2020 дата публикации

Array of Cross Point Memory Cells and Methods of Forming an Array of Cross Point Memory Cells

Номер: US20200152633A1

Автор: Durai Vishak Nirmal Ramaswamy

Принадлежит: Micron Technology Inc

A method of forming an array of cross point memory cells comprises using two, and only two, masking steps to collectively pattern within the array spaced lower first lines, spaced upper second lines which cross the first lines, and individual programmable devices between the first lines and the second lines where such cross that have an upwardly open generally U-shape vertical cross-section of programmable material laterally between immediately adjacent of the first lines beneath individual of the upper second lines. Arrays of cross point memory cells independent of method of manufacture are disclosed.

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Номер записи: 74

21-05-2020 дата публикации

Film stress control for memory device stack

Номер: US20200161547A1

Автор: Chih-Chao Yang, ChoongHyun Lee, Injo OK, Seyoung Kim, Soon-Cheon Seo

Принадлежит: International Business Machines Corp

Semiconductor structures are provided that include a memory device buried within interconnect dielectric materials and in which a combination of a compressive metal-containing layer and a tensile metal-containing layer have been used to minimize wafer bow and litho overlay shift as well as a method of forming such semiconductor structures.

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Номер записи: 75

01-07-2021 дата публикации

Integration method of ferroelectric memory array

Номер: US20210202510A1

Автор: Amrita MATHURIYA, Gaurav Thareja, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Sasikanth Manipatruni

Принадлежит: Kepler Computing Inc

Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.

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Номер записи: 76

01-07-2021 дата публикации

Ferroelectric capacitor and method of patterning such

Номер: US20210202689A1

Автор: Amrita MATHURIYA, Gaurav Thareja, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Sasikanth Manipatruni

Принадлежит: Kepler Computing Inc

Ferroelectric capacitor is formed by conformably depositing a non-conductive dielectric over the etched first and second electrodes, and forming a metal cap or helmet over a selective part of the non-conductive dielectric, wherein the metal cap conforms to portions of sidewalls of the non-conductive dielectric. The metal cap is formed by applying physical vapor deposition at a grazing angle to selectively deposit a metal mask over the selective part of the non-conductive dielectric. The metal cap can also be formed by applying ion implantation with tuned etch rate. The method further includes isotopically etching the metal cap and the non-conductive dielectric such that non-conductive dielectric remains on sidewalls of the first and second electrodes but not on the third and fourth electrodes.

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Номер записи: 77

04-06-2020 дата публикации

Vertical decoder

Номер: US20200176039A1

Автор: Andrea Redaelli, Fabio Pellizzer

Принадлежит: Micron Technology Inc

Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may be configured to apply a voltage to an access line of the array of memory cells as part of an access operation. The decoder may include a first conductive line configured to carry the voltage applied to the access line of the array of memory cells. In some cases, the decoder may include a doped material extending between the first conductive line and the access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells.

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Номер записи: 78

15-07-2021 дата публикации

Memory cell, memory cell arrangement, and methods thereof

Номер: US20210217454A1

Автор: Johannes Ocker

Принадлежит: Ferroelectric Memory GmbH

According to various aspects, a memory cell is provided, the memory cell may include a field-effect transistor; a first control node and a second control node, a first capacitor structure including a first electrode connected to the first control node, a second electrode connected to a gate region of the field-effect transistor, and a remanent-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure; and a second capacitor structure including a first electrode connected to the second control node, a second electrode connected to the gate region of the field-effect transistor. In some aspects, the first capacitor structure may have a first capacitance and the second capacitor structure may have a second capacitance different from the first capacitance.

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Номер записи: 79

20-06-2019 дата публикации

Memory Cells

Номер: US20190189626A1

Автор: Ashonita Chavan, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kamal M. Karda, Kirk D. Prall, Qian Tao

Принадлежит: Micron Technology Inc

A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

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Номер записи: 80

12-07-2018 дата публикации

Arrays Of Memory Cells Individually Comprising A Capacitor And An Elevationally-Extending Transistor, Methods Of Forming A Tier Of An Array Of Memory Cells, And Methods Of Forming An Array Of Memory Cells Individually Comprising A Capacitor And An Elevationally-Extending Transistor

Номер: US20180195049A1

Автор: Durai Vishak Nirmal Ramaswamy

Принадлежит: Micron Technology Inc

A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending transistor, the method comprising using two, and only two, sacrificial masking steps within the array area of the tier in forming the memory cells. Other methods are disclosed, as are structures independent of method of fabrication.

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Номер записи: 81

21-07-2016 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20160211269A1

Автор: Hideki Ito, Wensheng Wang, Youichi Okita

Принадлежит: Fujitsu Semiconductor Ltd

A method of manufacturing a semiconductor device includes: forming an insulating film above a semiconductor substrate; forming a conductive film on the insulating film; forming a dielectric film on the conductive film; forming a plurality of upper electrodes at intervals on the dielectric film; forming a first protective insulating film on the upper electrodes and the dielectric film by a sputtering method; forming a second protective insulating film on the first protective insulating film by an atomic layer deposition method, thereby filling gaps of a grain boundary of the dielectric film with the second protective insulating film; and patterning the conductive film after the second protective insulating film is formed to provide a lower electrode.

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Номер записи: 82

18-06-2020 дата публикации

Three-dimensional semiconductor memory devices

Номер: US20200194373A1

Автор: Jisung Cheon, Junhyoung Kim, Seokcheon Baek

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A three-dimensional semiconductor memory device includes a stack structure disposed on a substrate and including lower and upper stack structures, first and second isolation trenches defining the stack structure, extending in a first direction, and spaced apart from each other in a second direction, a middle isolation trench penetrating the upper stack structure between the first and second isolation trenches and extending in the first direction, and a horizontal isolation pattern connected to the middle isolation trench and dividing the upper stack structure in the second direction. The horizontal isolation pattern includes horizontal isolation portions, each of which extends in the first direction and is offset from an extension line of the middle isolation trench in the second direction or an opposite direction to the second direction.

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Номер записи: 83

25-06-2020 дата публикации

Ferroelectrics using thin alloy of para-electric materials

Номер: US20200203358A1

Автор: Ian A. Young, Joshua M. HOWARD, Seiyon Kim, Uygar E. Avci

Принадлежит: Intel Corp

Described is an apparatus which comprises: a first layer comprising a metal; a second layer comprising a first para-electric material, the second layer adjacent to the first layer; and a third layer comprising a second para-electric material, the third layer adjacent to the second layer, wherein the first para-electric material is different from the second para-electric material.

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Номер записи: 84

03-08-2017 дата публикации

Three-dimensional addressing for erasable programmable read only memory

Номер: US20170221566A1

Автор: Boon Bing NG, Hang Ru GOY

Принадлежит: Hewlett Packard Development Co LP

Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, a column select data signal, and a bank select data signal.

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Номер записи: 85

02-08-2018 дата публикации

Electronic device and method for fabricating the same

Номер: US20180218945A1

Автор: Joo-Young Moon

Принадлежит: SK hynix Inc

A semiconductor device may include: a plurality of first contacts arranged at a predetermined distance in a first direction and a second direction crossing the first direction; a plurality of second contacts alternately arranged between the first contacts and arranged at a predetermined distance in the first direction and the second direction; a plurality of dog bone-type conductive lines connected to the second contacts arranged in the second direction, respectively, among the plurality of second contacts, and having concave parts and convex parts; and a plurality of etching prevention patterns formed over the plurality of conductive lines so as to overlap the conductive lines, respectively.

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Номер записи: 86

12-08-2021 дата публикации

Semiconductor plug having an etch-resistant layer in three-dimensional memory devices

Номер: US20210249428A1

Автор: Chengxing Yu, Haifeng Guo, Lin Lai, Xiaojin Wang

Принадлежит: Yangtze Memory Technologies Co Ltd

3D memory devices with an etch-resistant layer and methods for forming the same are disclosed. A memory device includes a substrate and a memory stack disposed on the substrate. The memory stack includes a plurality of interleaved conductor layers and dielectric layers. The memory device also includes a plurality of memory strings each extending vertically through the memory stack and including a semiconductor plug at a bottom portion of the memory string. The semiconductor plug is in contact with the substrate and includes a top portion doped with an etch-resistant material.

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Номер записи: 87

16-07-2020 дата публикации

3d processor

Номер: US20200227389A1

Автор: Ilyas Mohammed, Javier Delacruz, Kenneth Duong, Steven L. Teig

Принадлежит: Xcelsis Corp

Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks defined on each die (1) overlap with other circuit blocks defined on one or more other dies, and (2) electrically connect to these other circuit blocks through connections that cross one or more bonding layers that bond one or more pairs of dies. In some embodiments, the overlapping, connected circuit block pairs include pairs of computation blocks and pairs of computation and memory blocks. The connections that cross bonding layers to electrically connect circuit blocks on different dies are referred to below as z-axis wiring or connections. This is because these connections traverse completely or mostly in the z-axis of the 3D circuit, with the x-y axes of the 3D circuit defining the planar surface of the IC die substrate or interconnect layers. These connections are also referred to as vertical connections to differentiate them from the horizontal planar connections along the interconnect layers of the IC dies.

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Номер записи: 88

08-08-2019 дата публикации

Semiconductor device including an electrode lower layer and an electrode upper layer and method of manufacturing semiconductor device

Номер: US20190244966A1

Автор: Yuichi Nakao

Принадлежит: ROHM CO LTD

The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.

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Номер записи: 89

30-07-2020 дата публикации

Slit oxide and via formation techniques

Номер: US20200243440A1

Автор: Hongqi Li, Kaushik Varma Sagi, Manzar Siddik

Принадлежит: Micron Technology Inc

Methods and apparatuses for slit oxide and via formation techniques are described, for example, for fabricating three dimensional memory devices that may include multiple decks of memory cells that each include memory cell stacks and associated access lines. The techniques may create an interconnect region without removing a portion of the memory cell stacks. The interconnect region may include one or more conductive vias extending through the decks of memory cells to couple the access lines with logic circuitry that may be located underneath the decks of memory cells. Further, the techniques may divide an array of memory cells into multiple subarrays of memory cells by forming trenches, which may sever the access lines. In some cases, each subarray of memory cells may be electrically isolated from other subarrays of memory cells. The techniques may reduce a total number of fabrication process steps.

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Номер записи: 90

15-09-2016 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20160268263A1

Автор: Ki Hong Lee, Seung Ho Pyi

Принадлежит: SK hynix Inc

A semiconductor device includes a substrate in which a cell region and contact regions located at both sides of the cell region are defined, a first source layer formed over the substrate, a second source layer formed over the first source layer, a reinforcement pattern formed in the second source layer, a stacked structure including conductive layers and insulating layers alternately stacked over the second source layer and the reinforcement pattern, channel layers passing through the stacked structure and the second source layer and electrically coupled to the second source layer, and an isolation insulating pattern passing through at least one top conductive layer of the conductive layers.

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Номер записи: 91

15-08-2019 дата публикации

Access devices formed with conductive contacts

Номер: US20190252553A1

Автор: Deepak Chandra Pandey, Haitao Liu, Kamal M. Karda, Litao YANG, Sanh D. Tang, Yunfei GAO

Принадлежит: Micron Technology Inc

Systems, apparatuses and methods related to access devices formed with conductive contacts are described. An example apparatus may include an access device that includes a field-effect transistor (FET). A vertical pillar may be formed to include a channel of the FET, with a portion of the vertical pillar formed between at least two gates of the FET (i.e., a multi-gate Fin-FET). A conductive contact may be coupled to a body region of the vertical pillar.

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Номер записи: 92

13-09-2018 дата публикации

Three-dimensional semiconductor memory device and method of fabricating the same

Номер: US20180261626A1

Автор: Dongchul Yoo, Dongkyum Kim, Dongwoo Kim, Gukhyon Yon, Kihyun Hwang

Принадлежит: SAMSUNG ELECTRONICS CO. LTD.

A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.

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Номер записи: 93

11-12-2014 дата публикации

Nonvolatile Resistive Memory Element With A Metal Nitride Containing Switching Layer

Номер: US20140361235A1

Автор: Imran Hashim, Takeshi Yamaguchi, Tim Minvielle, Tony P. Chiang, Yun Wang

Принадлежит: Intermolecular Inc, SanDisk 3D LLC, Toshiba Corp

A nonvolatile resistive memory element has a novel variable resistance layer that includes a metal nitride, a metal oxide-nitride, a two-metal oxide-nitride, or a multilayer stack thereof. One method of forming the novel variable resistance layer comprises an interlayer deposition procedure, in which metal oxide layers are interspersed with metal nitride layers and then converted into a substantially homogeneous layer by an anneal process. Another method of forming the novel variable resistance layer comprises an intralayer deposition procedure, in which various ALD processes are sequentially interleaved to form a metal oxide-nitride layer. Alternatively, a metal oxide is deposited, nitridized, and annealed to form the variable resistance layer or a metal nitride is deposited, oxidized, and annealed to form the variable resistance layer.

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Номер записи: 94

18-12-2014 дата публикации

Self-rectifying rram element

Номер: US20140367631A1

Автор: Bogdan Govoreanu

Принадлежит: Interuniversitair Microelektronica Centrum vzw IMEC

The disclosed technology generally relates to semiconductor devices and more particularly to memory devices having a resistance switching element, and to methods of operating such memory devices. In one aspect, a memory cell includes a first electrode and a second electrode formed of one of a metallic material or a semiconducting material. The memory cell additionally includes a resistance switching element formed between the first electrode and the second electrode. The memory cell additionally includes a tunnel rectifier formed between the resistance-switching element and the first electrode. The tunnel rectifier includes a a multi-layer tunnel stack comprising at least two dielectric layers each having a dielectric constant (k i ), a conduction band offset (Φ i ), and a thickness, wherein one of the dielectric layers has a higher dielectric constant, a lower conduction band offset and a higher thickness compared to any other dielectric layer of the multi-layer tunnel stack.

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Номер записи: 95

08-10-2015 дата публикации

Resistive random access memory and method of fabricating the same

Номер: US20150287914A1

Автор: Bo-Lun Wu, Chia-Hua Ho, Hsiu-Han Liao, Meng-Hung Lin, Po-Yen Hsu, Shuo-Che Chang, Ting-Ying SHEN

Принадлежит: Winbond Electronics Corp

Provided is a resistive random access memory including a first electrode layer, a second electrode layer, and a variable resistance layer disposed between the first electrode layer and the second electrode layer, wherein the second electrode layer includes a first sublayer, a second sublayer, and a conductive metal oxynitride layer disposed between the first sublayer and the second sublayer.

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Номер записи: 96

29-09-2016 дата публикации

Use of ambient-robust solution processing for preparing nanoscale organic ferroelectric films

Номер: US20160284714A1

Автор: Husam N. Alshareef, Ihab N. Odeh, Ji Hoon Park

Принадлежит: SABIC Global Technologies BV

Disclosed is a method for preparing a ferroelectric film having ferroelectric hysteresis properties, the method comprising (a) obtaining a composition comprising a solvent and an organic ferroelectric polymer solubilized therein, (b) heating the composition to above 75° C. and below the boiling point of the solvent, (c) depositing the heated composition onto a substrate; and (d) annealing the heated composition to form a ferroelectric film having ferroelectric hysteresis properties and a thickness of 400 nm or less.

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Номер записи: 97

27-08-2020 дата публикации

High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor

Номер: US20200273864A1

Автор: Rajeev Kumar Dokania, Ramamoorthy Ramesh, Sasikanth Manipatruni

Принадлежит: Kepler Computing Inc

Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

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Номер записи: 98

12-09-2019 дата публикации

Methods Of Forming An Array Of Capacitors, Methods Of Forming An Array Of Memory Cells Individually Comprising A Capacitor And A Transistor, Arrays Of Capacitors, And Arrays Of Memory Cells Individually Comprising A Capacitor And A Transistor

Номер: US20190280082A1

Автор: Durai Vishak Nirmal Ramaswamy

Принадлежит: Micron Technology Inc

A method of forming an array of capacitors comprises forming elevationally-extending and longitudinally-elongated capacitor electrode lines over a substrate. Individual of the capacitor electrode lines are common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed. A capacitor insulator is formed over a pair of laterally-opposing sides of and longitudinally along individual of the capacitor electrode lines. An elevationally-extending conductive line is formed over the capacitor insulator longitudinally along one of the laterally-opposing sides of the individual capacitor electrode lines. The conductive line is cut laterally through to form spaced individual other of the two capacitor electrodes of the individual capacitors. Other methods are disclosed, including structures independent of method of manufacture.

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Номер записи: 99

03-09-2020 дата публикации

Three-dimensional non-volatile ferroelectric memory

Номер: US20200279598A1

Автор: Anquan Jiang, Xiaojie CHAI, Yan Zhang

Принадлежит: FUDAN UNIVERSITY

Disclosed is a three-dimensional non-volatile ferroelectric memory including a ferroelectric memory array structure, wherein the ferroelectric memory array structure includes multiple layers of ferroelectric memory cell array disposed in a stacked way, and each layer of the ferroelectric memory cell array includes ferroelectric memory cells arranged in rows and columns; wherein word lines and bit lines which are substantially orthogonal to each other are oppositely disposed on two sides of the corresponding ferroelectric memory cell respectively, and a reference ferroelectric body is disposed adjacent to the corresponding ferroelectric memory cell. A polarization direction of an electric domain in the ferroelectric memory cell is not perpendicular to an electric field direction of a write voltage signal applied to the word line and the bit line; and when the write voltage signal is applied between the word line and the bit line.

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Номер записи: 100

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