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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 5754. Отображено 100.

05-01-2012 дата публикации

Carbon-based memory element

Номер: US20120001142A1

Автор: Abu Sebastian, Charalampos Pozidis, Christophe P. Rossel, Daniele Caimi, Evangelos S. Eleftheriou

Принадлежит: International Business Machines Corp

One embodiment of the disclosure can provide a storage layer of a resistive memory element comprising a resistance changeable material. The resistance changeable material can include carbon. Contact layers can be provided for contacting the storage layer. The storage layer can be disposed between a bottom contact layer and a top contact layer. The resistance changeable material can be annealed at a predetermined temperature over a predetermined annealing time for rearranging an atomic order of the resistance changeable material.

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Номер записи: 1

05-01-2012 дата публикации

High-precision resistor and trimming method thereof

Номер: US20120001679A1

Автор: Antonello Santangelo, Stefania Maria Serena PRIVITERA

Принадлежит: STMICROELECTRONICS SRL

An embodiment of an electrically trimmable electronic device, wherein a resistor of electrically modifiable material is formed by a first generally strip-shaped portion and by a second generally strip-shaped portion, which extend transversely with respect to one another and are in direct electrical contact in a crossing area. The first and second portions have respective ends connected to own contact regions, coupled to a current pulse source and are made of the same material or of the same composition of materials starting from a same resistive layer of the material having electrically modifiable resistivity, for example, a phase-change material, such as a Ge—Sb—Te alloy, or polycrystalline silicon, or a metal material used for thin-film resistors. The trimming is performed by supplying a trimming current to the second portion so as to heat the crossing area and modify the resistivity thereof, without flowing longitudinally in the first portion.

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Номер записи: 2

12-01-2012 дата публикации

RESTIVE MEMORY USING SiGe MATERIAL

Номер: US20120008366A1

Автор: Wei Lu

Принадлежит: Crossbar Inc

A resistive memory device includes a first electrode; a second electrode having a polycrystalline semiconductor layer that includes silicon; a non-crystalline silicon structure provided between the first electrode and the second electrode. The first electrode, second electrode and non-crystalline silicon structure define a two-terminal resistive memory cell.

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Номер записи: 3

19-01-2012 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20120012944A1

Автор: Jae-Yun YI

Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a memory block including a transistor region and a memory region. A variable resistance layer of the memory region acts as a gate insulating layer in the transistor region.

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Номер записи: 4

03-05-2012 дата публикации

Method for obtaining smooth, continuous silver film

Номер: US20120108030A1

Автор: Scott Brad Herner

Принадлежит: Crossbar Inc

A method for forming a semiconductor device including a resistive memory cell includes providing a substrate having an upper surface. A first conductive layer is formed over the upper surface of the substrate. An amorphous silicon layer is formed over the first conductive layer. A surface of the amorphous silicon layer is cleaned to remove native oxide formed on the surface of the amorphous silicon layer. A silver layer is deposited over the amorphous silicon layer after removing the native oxide by performing the cleaning step. The resistive memory cell includes the first conductive layer, the amorphous silicon layer, and the second conductive layer. The surface of the amorphous silicon layer is cleaned to prevent silver agglomeration on the native oxide.

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Номер записи: 5

17-05-2012 дата публикации

Forming Heaters for Phase Change Memories

Номер: US20120121864A1

Автор: Carla Maria Lazzari, Silvia Borsari

Принадлежит: Individual

A heater for a phase change memory may be formed by depositing a first material into a trench such that the material is thicker on the side wall than on the bottom of the trench. In one embodiment, because the trench side walls are of a different material than the bottom, differential deposition occurs. Then a heater material is deposited thereover. The heater material may react with the first material at the bottom of the trench to make Ohmic contact with an underlying metal layer. As a result, a vertical heater may be formed which is capable of making a small area contact with an overlying chalcogenide material.

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Номер записи: 6

24-05-2012 дата публикации

Upwardly Tapering Heaters for Phase Change Memories

Номер: US20120126196A1

Автор: Federico Pio

Принадлежит: Individual

A substantially planar heater for a phase change memory may taper as it extends upwardly to contact a chalcogenide layer. As a result, the contact area between heater and chalcogenide is reduced. This reduced contact area can reduce power consumption in some embodiments.

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Номер записи: 7

07-06-2012 дата публикации

Programmable metallization memory cell with planarized silver electrode

Номер: US20120142169A1

Автор: DeXin Wang, Dimitar V. Dimitrov, Ivan Petrov Ivanov, Ming Sun, Muralikrishnan Balakrishnan, Venugopalan Vaithyanathan, WEI Tian, Yang Dong

Принадлежит: SEAGATE TECHNOLOGY LLC

Programmable metallization memory cells having a planarized silver electrode and methods of forming the same are disclosed. The programmable metallization memory cells include a first metal contact and a second metal contact, an ion conductor solid electrolyte material is between the first metal contact and the second metal contact, and either a silver alloy doping electrode separates the ion conductor solid electrolyte material from the first metal contact or the second metal contact, or a silver doping electrode separates the ion conductor solid electrolyte material from the first metal contact. The silver electrode includes a silver layer and a metal seed layer separating the silver layer from the first metal contact.

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Номер записи: 8

14-06-2012 дата публикации

Method for manufacturing integrated circuit device

Номер: US20120149195A1

Автор: Takuji Kuniya

Принадлежит: Toshiba Corp

According to one embodiment, a method for manufacturing an integrated circuit device, includes etching a metal member using a gas including a halogen, forming a silicon oxide film so as to cover an etching face of the etched metal member without exposing the metal member to atmospheric air, and removing the silicon oxide film.

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Номер записи: 9

06-09-2012 дата публикации

Methods for increasing bottom electrode performance in carbon-based memory devices

Номер: US20120223414A1

Автор: April D. Schricker, Er-Xuan Ping

Принадлежит: SanDisk 3D LLC

In some aspects, a method of forming a reversible resistance-switching metal-insulator-metal (“MIM”) stack is provided, the method including: forming a first conducting layer comprising a titanium nitride material having between about 50% Ti and about 95% Ti, forming a carbon nano-tube (CNT) material above the first conducting layer, forming a second conducting layer above the CNT material, and etching the first conducting layer, CNT material and second conducting layer to form the MIM stack. Numerous other aspects are provided.

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Номер записи: 10

13-09-2012 дата публикации

Memory Cell Constructions, and Methods for Fabricating Memory Cell Constructions

Номер: US20120228573A1

Автор: JIAN Li, Jun Liu

Принадлежит: Micron Technology Inc

Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals.

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Номер записи: 11

27-09-2012 дата публикации

Fabrication of RRAM Cell Using CMOS Compatible Processes

Номер: US20120241710A1

Автор: Chee Mang NG, Kin-Leong Pey, Nagarajan Raghavan, Wenhu Liu

Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD, NANYANG TECHNOLOGICAL UNIVERSITY

Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode. A method of making a resistance random access memory device is disclosed that includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device.

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Номер записи: 12

04-10-2012 дата публикации

Variable resistance element and manufacturing method thereof

Номер: US20120252184A1

Автор: Takeki Ninomiya, Takumi Mikawa, Yoshio Kawashima, Yukio Hayakawa

Принадлежит: Panasonic Corp

A variable resistance element comprises, when M is a transition metal element, O is oxygen, and x and y are positive numbers satisfying y>x; a lower electrode; a first oxide layer formed on the lower electrode and comprising MO x when a content ratio of O with respect to M is x; a second oxide layer formed on the first oxide layer and comprising MO y when a content ratio of O with respect to M is y; an upper electrode formed on the second oxide layer; a protective layer formed on the upper electrode and comprising an electrically conductive material having a composition different from a composition of the upper electrode; an interlayer insulating layer formed to cover the protective layer; and an upper contact plug formed inside an upper contact hole penetrating the interlayer insulating layer.

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Номер записи: 13

04-10-2012 дата публикации

Semiconductor Device and Method of Manufacturing the Same

Номер: US20120252187A1

Автор: Dong-Hyun Im, Dong-Hyun Kim, Gyu-Hwan OH, Kyung-min Chung

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other , forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.

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Номер записи: 14

18-10-2012 дата публикации

Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells

Номер: US20120262973A1

Автор: Jun Liu

Принадлежит: Individual

An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed.

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Номер записи: 15

01-11-2012 дата публикации

Semiconductor cell and method for forming the same

Номер: US20120273919A1

Автор: Song Hyeuk Im

Принадлежит: Hynix Semiconductor Inc

A semiconductor cell includes storage node contact plugs disposed on a semiconductor substrate, a bit line formation area which is disposed between the storage node contact plugs and exposes the semiconductor substrate, and an air gap which is in contact with a lower portion of a sidewall of the bit line formation area and extends in a direction perpendicular to a direction in which the bit line formation area extends. Therefore, the coupling effect between adjacent bit lines as well as the coupling effect caused between adjacent storage node contact plugs and the coupling effect caused between the storage node contact plug and the bit line are controlled to improve characteristics of semiconductor devices.

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Номер записи: 16

22-11-2012 дата публикации

Method of manufacturing non-volatile semiconductor memory element and method of manufacturing non-volatile semiconductor memory device

Номер: US20120295413A1

Автор: Satoru Fujii, Takumi Mikawa

Принадлежит: Panasonic Corp

A method of manufacturing a non-volatile semiconductor memory element including a variable resistance element and a non-ohmic element. The variable resistance element includes a first electrode, a variable resistance layer, and a shared electrode. The non-ohmic element includes the shared electrode, a semiconductor or insulator layer, and a second electrode. The method includes: forming the first electrode on a substrate; forming the variable resistance layer on the first electrode; forming the shared electrode by nitriding a front surface of the variable resistance layer; forming the semiconductor or insulator layer on the shared electrode; and forming the second electrode. In the forming of the shared electrode, a front surface of a transition metal oxide is nitrided by a plasma nitriding process to form the shared electrode comprising a transition metal nitride.

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Номер записи: 17

29-11-2012 дата публикации

Semiconductor memory device, method of manufacturing the same and method of forming contact structure

Номер: US20120299189A1

Автор: Shingo Nakajima

Принадлежит: Toshiba Corp

When a first wiring and/or a second wiring is formed, a connection portion is formed in the first wiring and/or the second wiring which covers a part of a lower electrode layer outside the memory cell array. An etching suppressing portion is formed above the connection portion. A contact hole is formed in which a portion under the etching suppressing portion reaches up to a connection potion, and the other portion reaches up to the lower electrode layer by performing etching to a laminated body in a range including the etching suppressing portion. The laminated body includes the insulating layer, the first wiring, a memory cell layer, the second wiring, and the etching suppressing portion. The contact layer is formed by burying a conductive material in the contact hole.

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Номер записи: 18

13-12-2012 дата публикации

Surface treatment to improve resistive-switching characteristics

Номер: US20120315725A1

Автор: April Schricker, Michael Miller, Prashant Phatak, Tanmay Kumar, Tony Chiang, Xiyang Chen

Принадлежит: Intermolecular Inc

This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

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Номер записи: 19

20-12-2012 дата публикации

Variable resistance memory device having reduced bottom contact area and method of forming the same

Номер: US20120319073A1

Автор: Hasan Nejad

Принадлежит: Individual

A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit.

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Номер записи: 20

27-12-2012 дата публикации

Memory Device

Номер: US20120329237A1

Автор: Regino Sandoval, Wolodymyr Czubatyj

Принадлежит: Ovonyx Inc

A phase-change memory device includes a first insulator having a hole therethrough, a first electrode that conforms at least partially to the hole, a phase-change material in electrical communication with the first electrode, and a second electrode in electrical communication with the phase-change material. When current is passed from the first electrode to the second electrode through the phase-change material, at least one of the first and second electrodes remains unreactive with the phase change material.

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Номер записи: 21

31-01-2013 дата публикации

Phase change memory electrode with sheath for reduced programming current

Номер: US20130026436A1

Автор: Bipin Rajendran, Matthew J. Breitwisch

Принадлежит: International Business Machines Corp

An example embodiment is a phase change memory cell that includes a bottom contact and an electrically insulating layer disposed over the bottom contact. The electrically insulating layer defines an elongated via. Furthermore, a bottom electrode is disposed at least partially in the via. The bottom electrode includes a sleeve of a first electrically conductive material surrounding a rod of a second electrically conductive material. The first electrically conductive material and the second electrically conductive material have different specific electrical resistances. The memory cell also includes a phase change layer electrically coupled to the first electrode.

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Номер записи: 22

21-03-2013 дата публикации

Select devices for memory cell applications

Номер: US20130070511A1

Автор: D.V. Nirmal Ramaswamy, David H. Wells

Принадлежит: Micron Technology Inc

Select devices for memory cell applications and methods of forming the same are described herein. As an example, one or more memory cells comprise a a select device structure including a two terminal select device having a current-voltage (I-V) profile associated therewith, and a non-ohmic device in series with the two terminal select device. The combined two terminal select device and non-ohmic device provide a composite I-V profile of the select device structure that includes a modified characteristic as compared to the I-V profile, and the modified characteristic is based on at least one operating voltage associated with the memory cell.

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Номер записи: 23

13-06-2013 дата публикации

Contact for memory cell

Номер: US20130149861A1

Автор: Jun Liu

Принадлежит: Micron Technology Inc

A contact for memory cells and integrated circuits having a conductive layer supported by the sidewall of a dielectric mesa, memory cells incorporating such a contact, and methods of forming such structures.

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Номер записи: 24

27-06-2013 дата публикации

Resistive memory

Номер: US20130163310A1

Автор: Bao Tran

Принадлежит: Individual

A memory device includes an upper conductive layer, a lower conductive layer, and a resistive, optical or magnetic matrix positioned between the upper and lower conductive layers.

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Номер записи: 25

11-07-2013 дата публикации

Integrated Circuitry, Methods of Forming Memory Cells, and Methods of Patterning Platinum-Containing Material

Номер: US20130175495A1

Автор: Andrey V. Zagrebelny, Chet E. Carter

Принадлежит: Micron Technology Inc

Some embodiments include methods of patterning platinum-containing material. An opening may be formed to extend into an oxide. Platinum-containing material may be formed over and directly against an upper surface of the oxide, and within the opening. The platinum-containing material within the opening may be a plug having a lateral periphery. The lateral periphery of the plug may be directly against the oxide. The platinum-containing material may be subjected to polishing to remove the platinum-containing material from over the upper surface of the oxide. The polishing may delaminate the platinum-containing material from the oxide, and may remove the platinum-containing material from over the oxide with an effective selectivity for the platinum-containing material relative to the oxide of at least about 5:1. Some embodiments include methods of forming memory cells. Some embodiments include integrated circuitry having platinum-containing material within an opening in an oxide and directly against the oxide.

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Номер записи: 26

18-07-2013 дата публикации

Memory cells having a common gate terminal

Номер: US20130182486A1

Автор: Farid Nemati, Rajesh N. Gupta

Принадлежит: Micron Technology Inc

Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.

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Номер записи: 27

29-08-2013 дата публикации

Memory Device Having An Integrated Two-Terminal Current Limiting Resistor

Номер: US20130221314A1

Автор: Dipankar Pramanik, Mankoo Lee, Tony P. Chiang

Принадлежит: Intermolecular Inc

A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

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Номер записи: 28

12-09-2013 дата публикации

Nanoscale switching device with an amorphous switching material

Номер: US20130234103A1

Автор: Gilberto Medeiros Ribeiro, Jianhua Yang, R. Stanley Williams

Принадлежит: Hewlett Packard Development Co LP

Nanoscale switching devices are disclosed. The devices have a first electrode of a nanoscale width; a second electrode of a nanoscale width; and a layer of an active region disposed between and in electrical contact with the first and second electrodes. The active region contains a switching material capable of carrying a significant amount of defects which can trap and de-trap electrons under electrical bias. The switching material is in an amorphous state. A nanoscale crossbar array containing a plurality of the devices and a method for making the devices are also disclosed.

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Номер записи: 29

12-09-2013 дата публикации

Memory cell that includes a sidewall collar for pillar isolation and methods of forming the same

Номер: US20130234104A1

Автор: Scott Brad Herner

Принадлежит: SanDisk 3D LLC

A method of forming a memory cell is provided. The method includes forming a steering element pillar having a first stiffness and a sidewall, forming a sidewall collar along at least a portion of the sidewall of the steering element pillar, the sidewall collar having a second stiffness, wherein the second stiffness is greater than the first stiffness, and forming a memory element coupled to the steering element pillar. Numerous other aspects are provided.

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Номер записи: 30

26-09-2013 дата публикации

Semiconductor memory device and method of manufacturing the same

Номер: US20130249114A1

Автор: Naohito Morozumi, Tomoya Osaki

Принадлежит: Toshiba Corp

A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region.

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Номер записи: 31

19-12-2013 дата публикации

3d memory with vertical bit lines and staircase word lines and vertical switches and methods thereof

Номер: US20130339571A1

Автор: Raul Adrian Cernea, Roy E. Scheuerlein

Принадлежит: SanDisk 3D LLC

A 3D memory with vertical local bit lines global bit lines has an in-line vertical switch in the form of a thin film transistor (TFT) formed as a vertical structure, to switch a local bit line to a global bit line. The TFT is implemented to switch a maximum of current carried by the local bit line by a strongly coupled select gate which must be fitted within the space around the local bit line. Maximum thickness of the select gate is implemented with the select gate exclusively occupying the space along the x-direction from both sides of the local bit line. The switches for odd and even bit lines of the row are staggered and offset in the z-direction so that the select gates of even and odd local bit lines are not coincident along the x-direction. The switching is further enhanced with a wrap-around select gate.

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Номер записи: 32

02-01-2014 дата публикации

Efficient layer-2 multicast topology construction

Номер: US20140003285A1

Автор: Aseem S. Rastogi, Nitin Jain

Принадлежит: Brocade Communications Systems LLC

One embodiment of the present invention provides a switch. The switch includes a processor and a computer-readable storage medium. The computer-readable storage medium stores instructions which when executed by the processor cause the processor to perform a method. The method comprises determining whether the switch is a leaf switch of a multicast distribution tree of a multicast group based on a multicast topology query message from a root switch of the multicast distribution tree. If the switch is a leaf switch, the method further comprises constructing a multicast topology report message comprising layer-2 topology information of the multicast group associated with the switch.

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Номер записи: 33

06-02-2014 дата публикации

Multifunctional Electrode

Номер: US20140038380A1

Автор: Dipankar Pramanik, Hieu Pham, Hong Sheng YANG, Imran Hashim, Takeshi Yamaguchi, Tim Minvielle, Vidyut Gopal, Yun Wang

Принадлежит: Intermolecular Inc, Toshiba Corp

A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 Ωcm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.

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Номер записи: 34

10-04-2014 дата публикации

Resistive memory device fabricated from single polymer material

Номер: US20140097395A1

Автор: Husam N. Alshareef, Mahmoud N. Almadhoun, Mohd Adnan KHAN, Unnat S. Bhansali

Принадлежит: Saudi Basic Industries Corp

A polymer-based device comprising a substrate; a first electrode disposed on the substrate; an active polymer layer disposed on and in contact with the first electrode; and a second electrode disposed on and in contact with the active polymer layer, wherein the first and the second electrodes are organic electrodes comprising a doped electroconductive organic polymer, the active polymer layer comprises the electroconductive organic polymer of the first and the second electrodes, and the first and the second electrodes have conductivity at least three orders of magnitude higher than the conductivity of the active polymer layer.

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Номер записи: 35

07-01-2016 дата публикации

Methods of Forming Structures

Номер: US20160005966A1

Автор: Hyun Sik Kim, Irina V. Vasilyeva, Kyle B. Campbell, Kyuchul Chong

Принадлежит: Micron Technology Inc

Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. Liners are formed along sidewalls of the features under conditions which do not expose the temperature-sensitive material to a temperature exceeding 300° C. The liners extend along the temperature-sensitive material and narrow gaps between the spaced-apart features. The narrowed gaps are filled with flowable material which is cured under conditions that do not expose the temperature-sensitive material to a temperature exceeding 300° C. In some embodiments, the features contain memory cell regions over select device regions. The memory cell regions include first chalcogenide and the select device regions include second chalcogenide. The liners extend along and directly against the first and second chalcogenides.

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Номер записи: 36

02-01-2020 дата публикации

Three-dimensional memory device containing cobalt capped copper lines and method of making the same

Номер: US20200006431A1

Автор: Satoru Mayuzumi, Wei Kuo Shih, Yuji Takahashi

Принадлежит: SanDisk Technologies LLC

A memory device includes first conductive rails laterally extending along a first horizontal direction over a substrate, where the first conductive rails include a fill portion, and a first cobalt-containing cap liner contacting a top surface of the fill portion, a rectangular array of first memory pillar structures overlying top surfaces of the first conductive rails, where each first memory pillar structure includes a respective first resistive memory element, and second conductive rails laterally extending along a second horizontal direction and overlying top surfaces of the rectangular array of first memory pillar structures.

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Номер записи: 37

14-01-2021 дата публикации

Resistive random access memory structure and method for manufacturing the same

Номер: US20210013403A1

Автор: Chuan-Fu Wang, Chun-hung Cheng, Wen-Jen Wang

Принадлежит: United Microelectronics Corp

A resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.

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Номер записи: 38

14-01-2021 дата публикации

Electronic device and method of manufacturing electronic device

Номер: US20210013409A1

Автор: Beom Seok Lee, Woo Tae Lee

Принадлежит: SK hynix Inc

A method of manufacturing an electronic device including a semiconductor memory may include forming a first active layer, forming a first electrode material over the first active layer, performing a heat treatment process on the first electrode material and the first active layer, and forming a second electrode material over the heat-treated first electrode material.

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Номер записи: 39

03-02-2022 дата публикации

Memory cell array circuit and method of forming the same

Номер: US20220035981A1

Автор: Chi-Hsiang Weng, Yu-Der Chih

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A memory cell array includes a first and a second column of memory cells, a first and a second bit line, a source line and a first set of vias. The first or second bit line includes a first conductive line located on a first metal layer, and a second conductive line located on a second metal layer. The first and second conductive lines overlap a source of a transistor of a memory cell of the first column or second column of memory cells. The source line is coupled to the first and second column of memory cells. The first set of vias is electrically coupled to the first and second conductive line. A pair of vias of the first set of vias is located above where the first conductive line overlaps each memory cell of the first or second column of memory cells.

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Номер записи: 40

22-01-2015 дата публикации

Device switching using layered device structure

Номер: US20150021538A1

Автор: Sung Hyun Jo, Wei Lu

Принадлежит: Crossbar Inc

A resistive switching device. The device includes a first electrode comprising a first metal material overlying the first dielectric material and a switching material comprising an amorphous silicon material. The device includes a second electrode comprising at least a second metal material. In a specific embodiment, the device includes a buffer material disposed between the first electrode and the switching material. The buffer material provides a blocking region between the switching material and the first electrode so that the blocking region is substantially free from metal particles from the second metal material when a first voltage is applied to the second electrode.

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Номер записи: 41

16-01-2020 дата публикации

Dynamic random access memory

Номер: US20200020696A1

Автор: Xi Lin, Yi Hua SHEN

Принадлежит: Semiconductor Manufacturing International Beijing Corp, Semiconductor Manufacturing International Shanghai Corp

A dynamic random access memory (DRAM) is provided and includes a base substrate. The base substrate includes a semiconductor substrate, a plurality of fins formed on the semiconductor substrate, and an isolation structure formed on the semiconductor substrate and covering portions of side surfaces of the plurality of fins. The dynamic random access memory further includes an interlayer dielectric layer formed over the base substrate and covering top surfaces of the plurality of fins and the isolation structure; and a memory structure, formed in an opening passing through the interlayer dielectric layer and each of the plurality of fins, the opening extending to and exposing a top surface of a portion of the isolation structure. The memory structure includes a first conductive layer, a memory medium layer on the first conductive layer, and a second conductive layer on the memory medium layer.

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Номер записи: 42

25-01-2018 дата публикации

Redundant column or row in resistive random access memory

Номер: US20180025790A1

Автор: Brent Buchanan, Emmanuelle J. Merced Grafals, Le Zheng

Принадлежит: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Examples include a resistive random access memory (RRAM) array to support a redundant column. Some examples include an RRAM cell at a cross point of a column line and a row line of the RRAM array. A first column line may be coupled to a first input of a first current-steering multiplexer and the first current-steering multiplexer may have an output coupled to a first current sense amplifier and a select input coupled to a first column select signal. A second column line may be coupled to a second input of the first current-steering multiplexer and coupled to a first input of a second current-steering multiplexer. The second current-steering multiplexer may have an output coupled to a second current sense amplifier and a select input coupled to a second column select signal. A third column line may be coupled to a second input of the second current-steering multiplexer.

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Номер записи: 43

25-01-2018 дата публикации

Nonvolatile resistive switching memory device and manufacturing method thereof

Номер: US20180026183A1

Автор: Haitao Sun, Hangbing Lv, Kangwei Zhang, Keke Zhang, Ming Liu, QI Liu, Shibing Long, Writam Banerjee

Принадлежит: Institute of Microelectronics of CAS

A nonvolatile resistive switching memory, comprising an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode, and characterized in that: a graphene barrier layer is inserted between the inert metal electrode and the resistive switching functional layer, which is capable of preventing the easily oxidizable metal ions from migrating into the inert metal electrode through the resistive switching functional layer under the action of electric field during the programming of the device. The manufacturing method therefore comprises adding a monolayer or multilayer graphene thin film between the inert electrode and the solid-state electrolyte resistive switching functional layer which services as a metal ion barrier layer to stop electrically-conductive metal filaments formed in the resistive switching layer from diffusing into the inert electrode layer during a RRAM device programming process, eliminating erroneous programming phenomenon occurring during the erasing process, improving device reliability.

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Номер записи: 44

23-01-2020 дата публикации

Confined phase change memory with double air gap

Номер: US20200028078A1

Автор: BALASUBRAMANIAN Pranatharthiharan, Injo OK, Wei Wang

Принадлежит: International Business Machines Corp

A method is presented for reducing heat loss to adjacent semiconductor structures. The method includes forming a plurality of conductive lines within an interlayer dielectric, forming a barrier layer over at least one conductive line of the plurality of conductive lines, forming a via extending to a top surface of the barrier layer, and defining dual air gaps within the via and over the barrier layer.

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Номер записи: 45

02-02-2017 дата публикации

Metal line connection for improved rram reliability, semiconductor arrangement comprising the same, and manufacture thereof

Номер: US20170033161A1

Автор: Chun-Yang Tsai, Kuo-Ching Huang, Yu-Wei Ting

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.

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Номер записи: 46

17-02-2022 дата публикации

Rram device structure and manufacturing method

Номер: US20220052258A1

Автор: Chung-Liang Cheng

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A resistive random access memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element.

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Номер записи: 47

30-01-2020 дата публикации

Multi-layer structure to increase crystalline temperature of a selector device

Номер: US20200035916A1

Автор: Hai-Dang Trinh

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In some embodiments, a semiconductor device is provided. The semiconductor device includes a first amorphous switching structure disposed over a first electrode. A buffer structure is disposed over the first amorphous switching structure. A second amorphous switching structure is disposed over the buffer structure. A second electrode is disposed over the second amorphous switching structure, where the first and second amorphous switching structures are configured to switch between low resistance states and high resistance states depending on whether a voltage from the first electrode to the second electrode exceeds a threshold voltage.

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Номер записи: 48

07-02-2019 дата публикации

Resistive random accress memory containing a conformal titanium aluminum carbide film and method of making

Номер: US20190044064A1

Автор: Genji Nakamura, Sara Aoki, Takahiro Hakamata, Takamichi Kikuchi, Toshio Hasegawa

Принадлежит: Tokyo Electron Ltd

A plurality of embodiments for ReRAM devices and method of making are described. According to one embodiment, the ReRAM device includes a first electrode film formed on a substrate, a metal oxide film with oxygen vacancies formed on a first electrode film, a conformal TiAlC film, oxidized by diffused oxygen atoms from the metal oxide film, formed on the metal oxide film, and a second electrode film formed on the TiAlC film. According to another embodiment, the ReRAM device includes a pair of vertical metal oxide films, a pair of vertical conformal TiAlC films formed on the pair of vertical metal oxide films, the pair of vertical conformal TiAlC films oxidized by diffused oxygen atoms from the pair of vertical metal oxide films, and an electrode film formed between the pair of vertical conformal TiAlC films.

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Номер записи: 49

15-02-2018 дата публикации

Memory Devices and Memory Device Forming Methods

Номер: US20180047783A1

Автор: Chandra Mouli

Принадлежит: Micron Technology Inc

Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

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Номер записи: 50

03-03-2022 дата публикации

Small line or pillar structure and process

Номер: US20220069211A1

Автор: Chiao-Wen Yeh, Hsiang-Lan Lung

Принадлежит: Macronix International Co Ltd

A pillar-shaped structure and a line-shaped structure are described that include a supporting top conductive layer, an active material layer, such as a memory material or switching material, and a bottom conductive layer. The active material layer is more narrow than the supporting top conductive layer. A supporting side insulating layer is formed connecting the top and bottom conductive layers to provide structure stability. A void, or air gap, is formed between the active material layer and the supporting side insulating layer, which can provide improved thermal isolation between adjacent pillar-shaped or line-shaped structures.

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Номер записи: 51

15-05-2014 дата публикации

Logic compatible rram structure and process

Номер: US20140131651A1

Автор: Chih-Yang Chang, Chin-Chieh YANG, Hsia-Wei CHEN, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen LIAO

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A memory cell and method including a first electrode conformally formed through a first opening in a first dielectric layer, a resistive layer conformally formed on the first electrode, a second electrode conformally formed on the resistive layer, and a second dielectric layer conformally formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer is formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond a region defined by the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the region defined by the first opening. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

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Номер записи: 52

25-02-2021 дата публикации

ReRAM STRUCTURE AND METHOD OF FABRICATING THE SAME

Номер: US20210057643A1

Автор: Chin-Fu Lin, Hsin-Fu Huang, Hui-Ting Lin, Kuo-Chih Lai, Nien-Ting Ho, Shih-Min Chou, Szu-Yao Yu, Wei-Ming Hsiao

Принадлежит: United Microelectronics Corp

An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

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Номер записи: 53

25-02-2021 дата публикации

Resistive memory device having an oxide barrier layer

Номер: US20210057644A1

Автор: Seshubabu Desu

Принадлежит: 4DS Memory Ltd

A memory device is disclosed. The memory device includes a bottom contact, and a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a top contact on the top electrode, and a first barrier layer, including a first oxide material and a second oxide material, where the first oxide material is different from the second oxide material, and where the first barrier layer is between one of A) the memory layer and the bottom contact, and B) the top electrode and the top contact, where the first barrier layer is configured to substantially prevent the conduction of ions or vacancies therethrough.

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Номер записи: 54

23-02-2017 дата публикации

Resistive memory devices with a multi-component electrode

Номер: US20170053968A1

Автор: Hans S. Cho, Jianhua Yang, Richard H. Henze, Xia Sheng, Yoocharn Jeon

Принадлежит: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

A resistive memory device includes a conductor and a resistive memory stack in contact with the conductor. The resistive memory stack includes a multi-component electrode and a switching region. The multi-component electrode includes a base electrode having a surface, and an inert material electrode on the base electrode surface in a form of i) a thin layer, or ii) discontinuous nano-islands. A switching region is in contact with the conductor and with the inert material electrode when the inert material electrode is in the form of the thin layer; or the switching region is in contact with the conductor, with the inert material electrode, and with an oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands.

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Номер записи: 55

13-02-2020 дата публикации

Variable resistance memory devices

Номер: US20200052038A1

Автор: Byongju Kim, Jeong-hee Park, Jong-Uk Kim, Kwangmin Park, Young-Min Ko

Принадлежит: SAMSUNG ELECTRONICS CO LTD

There is provided a variable resistance memory device including a first electrode line layer including first electrode lines extending in a first direction and spaced apart from each other on a substrate, a second electrode line layer that is above the first electrode line layer and including second electrode lines extending in a second direction orthogonal to the first direction and spaced apart from each other, and a memory cell layer including memory cells between the first electrode line layer and the second electrode line layer. Each of the memory cells includes a selection device layer, an intermediate electrode layer, and a variable resistance layer. A first insulating layer is between the first electrode lines, a second insulating layer is between the memory cells, and a third insulating layer is between the second electrode lines. The second insulating layer includes air gaps on side surfaces of the memory cells.

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Номер записи: 56

13-02-2020 дата публикации

Storage element

Номер: US20200052197A1

Автор: Chiara Sabbione, Gabriele Navarro, Marie-Claire Cyrille, Mathieu Bernard

Принадлежит: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA

A phase-change storage element including, in a first portion, a stack of amorphous layers, the thickness of each layer in the stack being smaller than or equal to 5 nm.

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Номер записи: 57

10-03-2022 дата публикации

Semiconductor devices and methods of forming semiconductor devices

Номер: US20220077234A1

Автор: Benfu Lin, Juan Boon Tan, Lup San Leong, Yi Jiang

Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

A semiconductor device may be provided, including a first insulating layer; a second insulating layer arranged over the first insulating layer; a memory structure arranged within a memory region and including a resistance changing memory element within the first insulating layer; and a logic structure arranged within a logic region. In the memory region, the first insulating layer may contact the second insulating layer and in the logic region, the semiconductor device may further include a stop layer arranged between the first insulating layer and the second insulating layer.

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Номер записи: 58

10-03-2022 дата публикации

Memory device and method of manufacturing the same

Номер: US20220077235A1

Автор: Jinhong Kim, Seyun KIM, Soichiro Mizusaki, Youngjin Cho, Yumin KIM

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory device may include an insulating structure including a first surface and a protrusion portion protruding from the first surface in a first direction, a recording material layer on the insulating structure and extending along a protruding surface of the protrusion portion to cover the protrusion portion and extending onto the first surface of the insulating structure, a channel layer on the recording material layer and extending along a surface of the recording material layer, a gate insulating layer on the channel layer; and a gate electrode formed on the gate insulating layer at a location facing a second surface of the insulating structure. The second surface of the insulating structure may be a protruding upper surface of the protrusion portion.

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Номер записи: 59

10-03-2022 дата публикации

Resistive random-access memory devices with multi-component electrodes and discontinuous interface layers

Номер: US20220077389A1

Автор: Minxian Zhang, Ning Ge

Принадлежит: Tetramem Inc

The present disclosure relates to resistive random-access memory (RRAM) devices. An RRAM device may include a first electrode, a first interface layer fabricated on the first electrode; a switching oxide layer fabricated on the first interface layer; and a second electrode fabricated on the switching oxide layer. The switching oxide layer includes a transition metal oxide. The first interface layer includes a discontinuous film of a first material that is more chemically stable than the transition metal oxide. The RRAM device may further include a second interface layer positioned between the switching oxide layer and the second electrode. The second interface layer includes a discontinuous film of a second material that is more chemically stable than the transition metal oxide. The second electrode may include multiple electrode components that may include an alloy, a first layer of a first metallic material, and/or a second layer of a second metallic material.

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Номер записи: 60

20-02-2020 дата публикации

Electrode structure to improve rram performance

Номер: US20200058858A1

Автор: Tong-Chern Ong, Wen-Ting Chu, Ying-Lang Wang

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a bottom electrode that is disposed over a lower interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A data storage structure is arranged over the bottom electrode and a multi-layer top electrode is disposed over the data storage structure. The multi-layer top electrode includes conductive top electrode layers separated by an oxygen barrier structure that is configured to mitigate movement of oxygen between the conductive top electrode layers. A sidewall spacer is disposed directly over the bottom electrode and has a sidewall that covers outermost sidewalls of the conductive top electrode layers and the oxygen barrier structure.

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Номер записи: 61

20-02-2020 дата публикации

Phase-Change Material (PCM) Radio Frequency (RF) Switch with Reduced Parasitic Capacitance

Номер: US20200058862A1

Автор: David J. Howard, Gregory P. Slovin, Jefferson E. Rose, Nabil El-Hinnawy

Принадлежит: Newport Fab LLC

A significantly reduced parasitic capacitance phase-change maternal (PCM) radio frequency (RF) switch includes an RF clearance zone including a step-wise structure of intermediate interconnect segments and vias to connect PCM contacts to setback top routing interconnects. The said RF clearance zone does not include cross-over interconnect segments. A low-k dielectric is situated in the RF clearance zone. A closed-air gap is situated in the RF clearance zone within the low-k dielectric. The setback top routing interconnects are situated higher over a substrate than the PCM contacts and the intermediate interconnect segments. The PCM RF switch may further include an open-air gap situated between the setback top routing interconnects.

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Номер записи: 62

17-03-2022 дата публикации

Method for forming a flat bottom electrode via (beva) top surface for memory

Номер: US20220085280A1

Автор: Chih-Yang Chang, Chin-Chieh YANG, Hsia-Wei CHEN, I-Ching Chen, Jen-Sheng Yang, Sheng-Hung SHIH, Tung-Sheng Hsiao, Wen-Ting Chu, Yu-Wen LIAO

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

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Номер записи: 63

17-03-2022 дата публикации

Rram bottom electrode

Номер: US20220085288A1

Автор: Fu-Chen Chang, Kuo-Chi Tu, Wen-Ting Chu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.

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Номер записи: 64

17-03-2022 дата публикации

Semiconductor storage device

Номер: US20220085291A1

Автор: Hiroyuki Ode

Принадлежит: Kioxia Corp

A semiconductor storage device includes a first region, a second region, and a third region. The first region includes first wirings extending in a first direction, second wirings extending in a second direction, and a memory cells provided at intersections of the first and second wirings. The second region includes a contact extending in a third direction. The third region includes first dummy wirings extending in the first direction, and a second dummy wirings extending in the second direction. A width in the first direction of a first one of the second dummy wirings, closest to the first region or the second region in the first direction, is equal to or less than a width in the first direction of a second one of the second dummy wirings next closest to the first region or the second region in the first direction.

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Номер записи: 65

27-02-2020 дата публикации

Phase change memory with a dielectric bi-layer

Номер: US20200066977A1

Автор: Injo OK, Iqbal Rashid Saraf, Kevin W. Brew, Nicole Saulnier, Robert Bruce

Принадлежит: International Business Machines Corp

Techniques regarding protecting a dielectric material during additive patterning of one or more phase change memories are provided. For example, one or more embodiments described herein can comprise a method, which can comprise forming a bi-layer adjacent a phase change memory element. The bi-layer can comprise a dielectric material and a capping material that can protect a thickness of the dielectric material during a patterning process.

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Номер записи: 66

11-03-2021 дата публикации

Nonvolatile memory device having resistance change memory layer

Номер: US20210074354A1

Автор: Hyangkeun YOO, Jae Hyun Han, Se Ho LEE

Принадлежит: SK hynix Inc

A nonvolatile memory device according to an embodiment includes a substrate, a source electrode structure disposed on the substrate, a channel structure disposed to be contact a sidewall surface of the source electrode structure, a resistance change memory layer disposed on a sidewall surface of the channel structure, a drain electrode structure disposed to contact the resistance change memory layer, a plurality of gate dielectric structures extending in the first direction and disposed to be spaced apart from each other in a second direction, and a plurality of gate electrode structures disposed to extend in the first direction in the plurality of the gate dielectric structure.

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Номер записи: 67

05-06-2014 дата публикации

Resistive random access memory devices formed on fiber and methods of manufacturing the same

Номер: US20140151623A1

Автор: Ji-Hyun Bae, Jong-Jin Park, Sang-Hun Jeon

Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided is a memory device formed on a fiber. The memory device includes a lower electrode, a memory resistance layer, and an upper electrode, which are sequentially formed on a surface of the fiber. The memory resistance layer may have variable resistance properties. The memory device may further include an intermediate electrode and a switching layer formed between the memory resistance layer and the upper electrode.

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Номер записи: 68

07-03-2019 дата публикации

Resistive random access memory and manufacturing method thereof

Номер: US20190074435A1

Автор: Bin Gao, HE Qian, Huaqiang Wu, Wei Wu

Принадлежит: TSINGHUA UNIVERSITY

A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.

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Номер записи: 69

17-03-2016 дата публикации

Nonvolatile memory element and method of manufacturing the same

Номер: US20160079530A1

Автор: Eun-Mi Kim, Takashi Nakagawa, Yuichi Otani

Принадлежит: Canon Anelva Corp

The present invention provides a nonvolatile memory element, in a nonvolatile memory element having a variable resistance layer possessing a stacked structure, in which the variable resistance layer has a high resistance change ratio, and a method of manufacturing the same. The nonvolatile memory element according to one embodiment of the present invention includes a first electrode, a second electrode, and a variable resistance layer which is interposed between the first electrode and second electrode and in which the resistance value changes into at least two different resistance states. The variable resistance layer possesses a stacked structure having a first metal oxide layer containing Hf and O, and a second metal oxide layer that is provided between the first metal oxide layer and at least one of the first electrode and the second electrode and contains Al and O.

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Номер записи: 70

24-03-2022 дата публикации

Multitier Arrangements of Integrated Devices, and Methods of Protecting Memory Cells During Polishing

Номер: US20220093529A1

Автор: Mihir BOHRA, Tarun Mudgal

Принадлежит: Micron Technology Inc

Some embodiments include a method of forming an arrangement. A first tier is formed to include CMOS circuitry. A second tier is formed to include an assembly which has first and second sets of memory cells on opposing sides of a coupling region. A support material is adjacent the first and second sets of the memory cells, and an intervening material is adjacent the support material. The support material has a different composition than the intervening material. A conductive interconnect extends through the intervening material. An upper surface of the assembly is polished to reduce an overall height of the assembly. The support material provides support during the polishing to protect the memory cells from being eroded during the polishing. The conductive interconnect of the second tier is coupled with the CMOS circuitry of the first tier. Some embodiments include multitier arrangements.

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Номер записи: 71

18-03-2021 дата публикации

Semiconductor storage device

Номер: US20210083183A1

Автор: Masanori Komura, Takayuki Tsukamoto

Принадлежит: Kioxia Corp

A semiconductor storage device includes first to third wirings extending in a first direction and adjacent in a second direction intersecting the first direction, fourth to sixth wirings extending in the second direction and adjacent in the first direction, memory cells each having one end connected to one of the first to third wirings and the other end connected to one of the fourth to sixth wirings, a circuit configured to output a first voltage, second and third voltages higher than the first voltage, a fourth voltage higher than the second voltage and the third voltage, and a fifth voltage higher than the fourth voltage. In a write operation for memory cells connected to the first and fourth wirings, the first, fourth, second, fifth and third voltages are transferred to the first, second, third, fourth, and fifth wirings, respectively, and the third voltage is transferred to the sixth wiring.

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Номер записи: 72

23-03-2017 дата публикации

Electrode materials and interface layers to minimize chalcogenide interface resistance

Номер: US20170084835A1

Автор: Andrea Gotti, Davide Colombo, F. Daniel Gealy, Kuo-Wei Chang

Принадлежит: Intel Corp

A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm.

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Номер записи: 73

19-06-2014 дата публикации

Phase change memory cell with large electrode contact area

Номер: US20140166962A1

Автор: Alejandro G. Schrott, Chung H. Lam, Jing Li, Matthew J. BrightSky, Norma E. Sosa Cortes

Принадлежит: International Business Machines Corp

A phase change memory cell and a method for fabricating the phase change memory cell. The phase change memory cell includes a bottom electrode and a first non-conductive layer. The first non-conductive layer defines a first well, a first electrically conductive liner lines the first well, and the first well is filled with a phase change material in the phase change memory cell.

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Номер записи: 74

29-03-2018 дата публикации

Resistive random access memory, manufacturing method thereof, and operation thereof

Номер: US20180090207A1

Автор: Boris Hudec, Che-Chia Chang, Tuo-Hung Hou

Принадлежит: Winbond Electronics Corp

A resistive random access memory (RRAM) including a first electrode, a second electrode, and a charge trapping layer is provided. The second electrode is located on the first electrode. The charge trapping layer is located between the first electrode and the second electrode. The charge trapping includes a first region and a second region. The first region has a first dopant and is close to the first electrode. The second region has a second dopant and is close to the second electrode.

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Номер записи: 75

29-03-2018 дата публикации

Memory Cell Having Resistance Variable Film and Method of Making the Same

Номер: US20180090680A1

Автор: Chern-Yow Hsu, Chia-Shiung Tsai, Ching-Pei Hsieh, Fu-Ting Sung, Shih-Chang Liu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.

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Номер записи: 76

21-03-2019 дата публикации

Correlated electron material devices using dopant species diffused from nearby structures

Номер: US20190088876A1

Автор: Kimberly Gay Reid, Lucian Shifren

Принадлежит: ARM LTD

Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, a correlated electron material may be doped using dopant species derived from one or more precursors utilized to fabricate nearby structures such as, for example, a conductive substrate or a conductive overlay.

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Номер записи: 77

05-05-2022 дата публикации

Semiconductor device having three-dimensional cell structure and method of manufacturing the same

Номер: US20220140238A1

Автор: Jae Hyun Han

Принадлежит: SK hynix Inc

A semiconductor device includes a substrate, a plurality of word line structures disposed over the substrate to be spaced apart from each other in a first direction perpendicular to a surface of the substrate. Each of the plurality of word line structures extends in a second direction parallel to the surface of the substrate. In addition, the semiconductor device includes a switching layer disposed over the substrate to contact side surfaces of the plurality of word line structures, and bit line structures disposed over the substrate to extend in the first direction and to contact a surface of the switching layer. The switching layer is configured to perform a threshold switching operation, and has a variable programmable threshold voltage.

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Номер записи: 78

30-03-2017 дата публикации

Arrays Of Memory Cells And Methods Of Forming An Array Of Memory Cells

Номер: US20170092695A1

Автор: Jun Liu, Kunal R. Parekh

Принадлежит: Micron Technology Inc

An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.

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Номер записи: 79

30-03-2017 дата публикации

Bromine containing silicon precursors for encapsulation layers

Номер: US20170092857A1

Автор: Dennis M. Hausmann

Принадлежит: Lam Research Corp

Methods of depositing silicon nitride encapsulation layers by atomic layer deposition over memory devices including chalcogenide material are provided herein. Methods include using iodine-containing and/or bromine-containing silicon precursors and depositing thermally using ammonia or hydrazine as a second reactant, or iodine-containing and/or bromine-containing silicon precursors and depositing using a nitrogen-based or hydrogen-based plasma.

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Номер записи: 80

26-06-2014 дата публикации

Resistive random access memory (rram) structure and method of making the rram structure

Номер: US20140175365A1

Автор: Chih-Yang Chang, Chin-Chieh YANG, Hsia-Wei CHEN, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen LIAO

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure provides a resistive random access memory (RRAM) cell. The RRAM cell includes a transistor, a bottom electrode adjacent to a drain region of the transistor and coplanar with the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the drain region.

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Номер записи: 81

19-03-2020 дата публикации

Electrode structure to improve rram performance

Номер: US20200091425A1

Автор: Tong-Chern Ong, Wen-Ting Chu, Ying-Lang Wang

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure, in some embodiments, relates to a method of forming a resistive random access memory (RRAM) device. The method includes forming one or more bottom electrode films over a lower interconnect layer within a lower inter-level dielectric layer. A data storage film having a variable resistance is formed above the one or more bottom electrode films. A lower top electrode film including a metal is over the data storage film, one or more oxygen barrier films are over the lower top electrode film, and an upper top electrode film including a metal nitride is formed over the one or more oxygen barrier films The one or more oxygen barrier films include one or more of a metal oxide film and a metal oxynitride film. The upper top electrode film is formed to be completely confined over a top surface of the one or more oxygen barrier films.

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Номер записи: 82

16-04-2015 дата публикации

Memory device, method of controlling memory device, and memory system

Номер: US20150103581A1

Автор: Kenichi Murooka

Принадлежит: Toshiba Corp

A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to generate first intermediate data; a data write processing circuit that sequentially sets a voltage difference between a selected row line and a selected global bit line based on the first intermediate data; a data read processing circuit that detects a current flowing in the selected global bit line or a voltage of the selected global bit line and sequentially generates second intermediate data from a result of that detection; and a data read post-processing circuit that processes the second intermediate data to generate output data, the data write pre-processing circuit and the data read post-processing circuit having a correcting function that corrects a difference that may occur between the input data and the output data.

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Номер записи: 83

28-03-2019 дата публикации

Semiconductor memory device

Номер: US20190096481A1

Автор: Chika Tanaka, Masumi SAITOH

Принадлежит: Toshiba Memory Corp

A semiconductor memory device includes a substrate, a stacked body comprising a plurality of first conductors extending in a first direction away from a surface of the substrate and spaced from one another in second and third directions intersecting the first direction and each other, the stacked body having a first region and a second region, a plurality of second conductors extending in the second direction, a plurality of third conductors extending in the third, each third conductor connected to a first end, in the second direction, of a plurality of second conductors in the first region, a plurality of fourth connectors extending in the first direction, each fourth conductor connected to the plurality of second conductors in the second region, and memory cells located between adjacent surfaces of the first and second conductors in the first region.

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Номер записи: 84

12-05-2022 дата публикации

Self-Selective Multi-Terminal Memtransistor for Crossbar Array Circuits

Номер: US20220149115A1

Автор: Kah Wee Ang, Xuewei Feng

Принадлежит: NATIONAL UNIVERSITY OF SINGAPORE

This disclosure describes a self-selective multi-terminal memtransistor suitable for use in crossbar array circuits. In particular, the memtransistor comprises a sapphire substrate that has a single-layer of polycrystalline molybdenum disulphide (MoS2) thin film formed on the surface of the substrate, wherein the MoS2 thin film comprise MoS2 grains that are oriented along terraces provided on the surface of the substrate. The memtransistor has a drain electrode and a source electrode that is formed on the MoS2 thin film such that a channel is defined in the MoS2 thin film between the drain and source electrodes, and a gate electrode formed above the channel, whereby the gate electrode is isolated from the channel by a gate dielectric layer.

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Номер записи: 85

23-04-2015 дата публикации

Double patterning method to form sub-lithographic pillars

Номер: US20150108422A1

Автор: Fabio Pellizzer, Giorgio Servalli, Marcello Mariani

Принадлежит: Micron Technology Inc

A method and resulting structure, is disclosed to fabricate vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a at least one dimension below the minimum lithographical resolution, F, of the lithographic technique employed. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars.

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Номер записи: 86

08-04-2021 дата публикации

Three-dimensional stacked memory and preparation method thereof

Номер: US20210104670A1

Автор: Hao Tong, Xiangshui Miao, Yushan SHEN

Принадлежит: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

The disclosure discloses a three-dimensional stacked memory and a preparation method thereof. The storage unit adopts a constrained structure phase change storage unit, and uses a crossbar storage array structure to build a large-capacity storage array. The preparation method includes: preparing N first strip-shaped electrodes along a crystal direction on a substrate; preparing a first insulating layer with M*N array of through holes; filling the M*N array of through holes of the first insulating layer with a phase change material to form first phase change units; preparing M second strip-shaped electrodes; preparing a second insulating layer, using spin-coated photoresist as a sacrificial material, performing a local planarization on the surface of the second insulating layer; forming M*N array of through holes on the second insulating layer; filling a phase change material to form second phase change units; preparing N third strip-shaped electrodes to form a two-layer stacked phase change memory.

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Номер записи: 87

26-03-2020 дата публикации

Interconnect landing method for rram technology

Номер: US20200098828A1

Автор: Chih-Yang Chang, Chin-Chieh YANG, Hsia-Wei CHEN, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen LIAO

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a memory device over a substrate and forming an inter-level dielectric (ILD) layer over the memory device. The ILD layer is selectively etched to define a first cavity that exposes a top of the memory device and to define a second cavity that is laterally separated from the first cavity by the ILD layer. The second cavity is defined by a smooth sidewall of the ILD layer that extends between upper and lower surfaces of the ILD layer. A conductive material is formed within the first cavity and the second cavity.

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Номер записи: 88

02-06-2022 дата публикации

Horizontal rram device and architecture fore variability reduction

Номер: US20220173313A1

Автор: Christopher J. Penny, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Timothy Mathew Philip, Youngseok Kim

Принадлежит: International Business Machines Corp

An apparatus comprising a dielectric layer located between a first electrode and a second electrode and a third electrode located on the dielectric layer between the first electrode and the electrode, wherein the first electrode is separated from a first side of the third electrode by a first portion of the dielectric layer, and the second electrode is separated from a second side of the third electrode by a second portion of the dielectric layer.

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Номер записи: 89

10-07-2014 дата публикации

Reduced diffusion in metal electrode for two-terminal memory

Номер: US20140192589A1

Автор: Steven Patrick MAXWELL, Sung-Hyun JO

Принадлежит: Crossbar Inc

Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.

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Номер записи: 90

07-05-2015 дата публикации

Electronic device and method for fabricating the same

Номер: US20150123067A1

Автор: Dong-Hyeon Lee

Принадлежит: SK hynix Inc

An electronic device including a semiconductor memory includes a plurality of first electrodes and a plurality of second electrodes, which are disposed over a substrate and alternately arrayed in a first direction that is parallel to a plane of the substrate; and a plurality of resistance variable patterns, each of which is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, wherein the first and second electrodes and the resistance variable patterns extend upwards by a predetermined height from the substrate.

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Номер записи: 91

07-05-2015 дата публикации

Data storage device and methods of manufacturing the same

Номер: US20150123196A1

Автор: Jaekyu Lee, Jungwoo Song

Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided are data storage devices and methods of manufacturing the same. The device may include a plurality of cell selection parts formed in a substrate, a plate conductive pattern covering the cell selection parts and electrically connected to first terminals of the cell selection parts, a plurality of through-pillars penetrating the plate conductive pattern and insulated from the plate conductive pattern, and a plurality of data storage parts directly connected to the plurality of through-pillars, respectively. The data storage parts may be electrically connected to second terminals of the cell selection parts, respectively.

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Номер записи: 92

09-06-2022 дата публикации

Resistive interface material

Номер: US20220181549A1

Автор: Andrea Gotti, Dale W. Collins, Fabio Pellizzer

Принадлежит: Micron Technology Inc

Methods, systems, and devices for a resistive interface material are described. A memory device may be fabricated using a sequence of steps that include forming a stack of materials by depositing a first metal layer, depositing a first electrode layer on the metal layer, depositing a memory material on the first electrode layer to form one or more memory cells, depositing a second electrode layer on the memory material, and depositing a second metal layer on the second electrode layer. A lamina (or multiple) having a relatively high resistivity may be included in the stack of materials to reduce or eliminate a current spike that may otherwise occur across the memory cells during an access operation.

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Номер записи: 93

05-05-2016 дата публикации

Electrically reconfigurable interposer with built-in resistive memory

Номер: US20160126291A1

Автор: Seung Hyuk KANG, Vidhya Ramachandran, Yu Lu

Принадлежит: Qualcomm Inc

An integrated interposer may include a substrate and a resistive-type non-volatile memory (NVM) array(s). The integrated interposer may also include a contact layer on a first surface of the substrate. The contact layer may include interconnections configured to couple the resistive-type NVM array(s) to a die(s). The resistive-type NVM array(s) may be partially embedded within the contact layer of the integrated interposer.

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Номер записи: 94

03-05-2018 дата публикации

Nonvolatile Resistive Memory Device and Manufacturing Method Thereof

Номер: US20180122856A1

Автор: Haitao Sun, Hangbing Lv, Kangwei Zhang, Ming Liu, QI Liu, Writam Banerjee

Принадлежит: Institute of Microelectronics of CAS

A nonvolatile resistive switching memory comprising an insulating substrate, a lower electrode, a lower graphene barrier layer, a resistive switching functional layer, an upper graphene barrier layer, and an upper electrode, wherein the lower and/or the upper graphene barrier layer is/are capable of preventing the metal ions/atoms in the lower/upper metal electrode from diffusing into the resistive switching functional layer under an applied electric field. According to the nonvolatile resistive switching memory device of the present invention and manufacturing method thereof, a monolayer or multilayer graphene film as a metal ions/atoms barrier layer is inserted between the upper/lower metal electrode and the resistive switching functional layer, which is capable of preventing the metal ions/atoms in the lower/upper metal electrode from diffusing into the resistive switching functional layer during the programming or erasing process of the resistive switching device, thereby improving the reliability of the device.

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Номер записи: 95

14-05-2015 дата публикации

Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

Номер: US20150132917A1

Автор: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala

Принадлежит: Unity Semiconductor Corp

Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

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Номер записи: 96

25-04-2019 дата публикации

Selector device for two-terminal memory

Номер: US20190122732A1

Автор: Sung Hyun Jo

Принадлежит: Crossbar Inc

Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.

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Номер записи: 97

25-04-2019 дата публикации

Novel resistive random access memory device

Номер: US20190123270A1

Автор: Chun-Chieh Mo, Shih-Chi Kuo

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A memory cell includes: a first electrode; a resistive material layer comprising one horizontal portion and two vertical portions that are respectively coupled to ends of the horizontal portion; and a second electrode, wherein the second electrode is partially surrounded by a top boundary of the U-shaped profile and the first electrode extends along part of a bottom boundary of the U-shaped profile.

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Номер записи: 98

16-04-2020 дата публикации

Memory cells with asymmetrical electrode interfaces

Номер: US20200119273A1

Автор: Agostino Pirovano, Anna Maria Conti, Fabio Pellizzer, Kolya Yastrebenetsky

Принадлежит: Micron Technology Inc

Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.

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Номер записи: 99

27-05-2021 дата публикации

3D ReRAM FORMED BY METAL-ASSISTED CHEMICAL ETCHING WITH REPLACEMENT WORDLINE AND WORDLINE SEPARATION

Номер: US20210159409A1

Автор: Chen Zhang, Kangguo Cheng, Wenyu Xu, Xin Miao

Принадлежит: International Business Machines Corp

Metal-assisted chemical etching is employed to form a three-dimensional (3D) resistive random access memory (ReRAM) in which the etching aspect ratio limit is extended and the top trench and bottom trench CD uniformity is improved. The 3D ReRAM includes a metal catalyst located between a bitline electrode and a selector device. Further, the 3D ReRAM includes vertically stacked and spaced apart replacement wordline electrodes that are located adjacent to the bitline electrode.

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Номер записи: 100