Phase change device

A phase change device (PCD) has a first and second semiconductor layer. The first semiconductor layer made of a first semiconductor material and has a first semiconductor thickness, a first interface surface, and a first electrode surface. The first interface surface and first electrode surface are on opposite sides of the first semiconductor layer. The first semiconductor material can transition between a first amorphous state and a first crystalline state at one or more first conditions. The second semiconductor layer is made of a second semiconductor material and has a second semiconductor thickness, a second interface surface, and a second electrode surface. The second interface surface and second electrode surface are on opposite sides of the second semiconductor layer. The first interface surface and the second interface surface are in electrical, physical, and chemical contact with one another at an interface. The second semiconductor material can transition between a second amorphous ...

Multi-terminal phase change memory device

A phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal in the electrically insulating wall, and two read terminals in the electrically insulating wall.

Electronic device and method for fabricating the same

A semiconductor memory includes a substrate including a cell region, first and second peripheral circuit regions disposed on two sides of the cell region; first lines extending across the cell region and a first peripheral circuit region; second lines disposed over the first lines and extending across the cell region and the second peripheral circuit region; a contact plug in the second peripheral circuit region and connected to the second line; third lines disposed over the second lines and respectively overlapping the second lines; and first memory cells disposed in the cell region and located at intersections of the first lines and the second lines between the first lines and the second lines, wherein portions of the third line located in the cell region and over the contact plug contact the second line, and part of a remainder of the third line is spaced apart from the second line.

Integration of selector on confined phase change memory

A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

Resistive random access memory and manufacturing method thereof

Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes a substrate having a pillar protruding from a surface of the substrate, a gate surrounding a part of a side surface of the pillar, a gate dielectric layer, a first electrode, a second electrode, a variable resistance layer, a first doped region and a second doped region. The gate dielectric layer is disposed between the gate and the pillar. The first electrode is disposed on a top surface of the pillar. The second electrode is disposed on the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The first doped region is disposed in the pillar below the gate and in a part of the substrate below the pillar. The second doped region is disposed in the pillar between the gate and the first electrode.

Discrete and monolithic phase-change material (PCM) radio frequency (RF) switches with sheet of thermally conductive and electrically insulating material

A radio frequency (RF) device includes a phase-change material (PCM) situated over a sheet of thermally conductive and electrically insulating material, a heating element situated under the sheet of thermally conductive and electrically insulating material, and an input/output terminal situated over the PCM. The heating element is situated in a dielectric. A heat spreader is situated under the dielectric and over a substrate. Metal interconnect layers can be situated under and/or over the PCM, with the substrate situated below the metal interconnect layers.

SWITCH BASED ON PHASE-CHANGE MATERIAL

The present description concerns a switch based on a phase-change material comprising: a region of the phase-change material; a heating element electrically insulated from the region of the phase-change material; and one or a plurality of pillars extending in the region of the phase-change material, the pillar(s) being made of a material having a thermal conductivity greater than that of the phase-change material.

PHASE CHANGE HETEROSTRUCTURE, AND PHASE CHANGE MEMORY DEVICE INCLUDING THE SAME

Provided are a phase change heterostructure and a phase change memory device including the same. The phase change memory device including the phase change heterostructure may include a plurality of memory cells. Each of the plurality of memory cells may include a first electrode and a second electrode, which may be spaced apart from each other, and a phase change heterostructure between the first electrode and the second electrode. The phase change heterostructure may include a plurality of phase change material layers and a plurality of thermal barrier layers alternately stacked on each other. A material of the plurality of thermal barrier layers have a thermal conductivity lower than a materials of the plurality of phase change material layers.

Multi-terminal phase change memory device

A phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal in the electrically insulating wall, and two read terminals in the electrically insulating wall.

MEMORY DEVICE HEATING IN COLD ENVIRONMENTS

Methods, systems, and devices for memory device heating in cold environments are described. A memory system may use system components to accelerate the heating of a non-volatile memory device that stores boot data associated with a boot up procedure at a host system. For example, the memory system may determine that a temperature associated with the memory system fails to satisfy a threshold. Based on the temperature failing to satisfy the threshold, a controller of the memory system may perform a heating procedure that increases a heat of and emitted by the controller (e.g., a heating element coupled with the controller) to accelerate the heating of the non-volatile memory device. The memory system may read the boot data from the non-volatile memory device based on the heating procedure and transmit the boot data to the host system.

Upwardly Tapering Heaters for Phase Change Memories

A substantially planar heater for a phase change memory may taper as it extends upwardly to contact a chalcogenide layer. As a result, the contact area between heater and chalcogenide is reduced. This reduced contact area can reduce power consumption in some embodiments.

Thermally insulated phase material cells

A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.

High density low power nanowire phase change material memory device

A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction.

Memory Cell Constructions, and Methods for Fabricating Memory Cell Constructions

Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals.

Programmable phase-change memory and method therefor

A non-volatile memory is disclosed. A contiguous layer of phase change material is provided. Proximate the contiguous layer of phase change material is provided a first pair of contacts for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing heating thereof within a first region. Also adjacent the contiguous layer is provided a second pair of contacts disposed for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing heating thereof within a second region thereof, the second region different from the first region.

Methods, apparatuses, and circuits for programming a memory device

Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

Selector Device for Memory Applications

The present disclosure is related to a selector device for memory applications. The selector device for selecting a memory element in a memory array comprises an MIT element and a decoupled heater, thermally linked to the MIT element. The MIT element comprises a MIT material component and a barrier component and is switchable from a high to a low resistance state by heating the MIT element above a transition temperature with the decoupled heater. The barrier component is provided to increase the resistance of the MIT element in the high resistance state.

Thermal isolation in memory cells

Thermal isolation in memory cells is described herein. A number of embodiments include a storage element, a selector device formed in series with the storage element, and an electrode between the storage element and the selector device, wherein the electrode comprises an electrode material having a thermal conductivity of less than 0.15 Watts per Kelvin-centimeter (W/K-cm).

Memristor cell structures for high density arrays

A memristor array includes a lower layer of crossbars, upper layer of crossbars intersecting the lower layer of crossbars, memristor cells interposed between intersecting crossbars, and pores separating adjacent memristor cells. A method forming a memristor array is also provided.

Non-volatile memory device and manufacturing method thereof

A non-volatile memory device of the present invention comprises a first electrode; a variable resistance layer formed on and above the first electrode; a second electrode formed on and above the variable resistance layer; a side wall protective layer having an insulativity and covering a side wall of the first electrode, a side wall of the variable resistance layer and a side wall of the second electrode; and an electrically-conductive layer connected to the second electrode; the non-volatile memory device including a connection layer which is provided between the second electrode and the electrically-conductive layer to connect the second electrode and the electrically-conductive layer to each other, and comprises an electrically-conductive material different from a material constituting the electrically-conductive layer; wherein the side wall protective layer extends across the second electrode to a position which is above an upper end of the second electrode and below an upper end of the connection layer such that an upper end of the side wall protective layer is located above the upper end of the second electrode and below the upper end of the connection layer, when viewed from a side.

Methods of Forming Structures

Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. Liners are formed along sidewalls of the features under conditions which do not expose the temperature-sensitive material to a temperature exceeding 300° C. The liners extend along the temperature-sensitive material and narrow gaps between the spaced-apart features. The narrowed gaps are filled with flowable material which is cured under conditions that do not expose the temperature-sensitive material to a temperature exceeding 300° C. In some embodiments, the features contain memory cell regions over select device regions. The memory cell regions include first chalcogenide and the select device regions include second chalcogenide. The liners extend along and directly against the first and second chalcogenides.

Phase change memory device with reduced read disturb and method of making the same

A method of operating a phase change memory device includes flowing a write current of a first polarity through a phase change memory element of a selected phase change memory cell, and flowing a read current of a second polarity opposite to the first polarity through the phase change memory element of the selected phase change memory cell. A first junction between the phase change memory element and a first electrode and a second junction between the phase change memory element and a second electrode exhibit asymmetric thermoelectric heat generation during the step of flowing the write current.

Phase-change random access memory device and method of manufacturing the same

A phase-change random access memory (PCRAM) device includes a semiconductor substrate; switching elements formed on the semiconductor substrate; a plurality of phase-change structures formed on the switching elements; and heat absorption layers buried between the plurality of phase-change structures, wherein the plurality of phase-change structures are insulated from the heat absorption layers.

Confined phase change memory with double air gap

A method is presented for reducing heat loss to adjacent semiconductor structures. The method includes forming a plurality of conductive lines within an interlayer dielectric, forming a barrier layer over at least one conductive line of the plurality of conductive lines, forming a via extending to a top surface of the barrier layer, and defining dual air gaps within the via and over the barrier layer.

Methods, apparatuses, and circuits for programming a memory device

Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

Integrated phase change switch

Various methods and devices that involve phase change material (PCM) switches are disclosed. An exemplary integrated circuit comprises an active layer with a plurality of field effect transistor (FET) channels for a plurality of FETs. The integrated circuit also comprises an interconnect layer comprising a plurality of conductive interconnects. The plurality of conductive interconnects couple the plurality of field effect transistors. The integrated circuit also comprises an insulator layer covering at least a portion of the interconnect layer. The integrated circuit also comprises a channel of a radio-frequency (RF) PCM switch. The channel of the RF PCM switch is formed on the insulator layer.

Variable resistance memory devices

There is provided a variable resistance memory device including a first electrode line layer including first electrode lines extending in a first direction and spaced apart from each other on a substrate, a second electrode line layer that is above the first electrode line layer and including second electrode lines extending in a second direction orthogonal to the first direction and spaced apart from each other, and a memory cell layer including memory cells between the first electrode line layer and the second electrode line layer. Each of the memory cells includes a selection device layer, an intermediate electrode layer, and a variable resistance layer. A first insulating layer is between the first electrode lines, a second insulating layer is between the memory cells, and a third insulating layer is between the second electrode lines. The second insulating layer includes air gaps on side surfaces of the memory cells.

Phase-Change Material (PCM) Radio Frequency (RF) Switches

A radio frequency (RF) switch includes a stressed phase-change material (PCM) and a heating element underlying an active segment of the stressed PCM and extending outward and transverse to the stressed PCM. In one approach, at least one transition layer is situated over the stressed PCM. An encapsulation layer is situated over the at least one transition layer and on first and second sides of the stressed PCM. A stressor layer is situated over the encapsulation layer and the said stressed PCM. Alternatively or additionally, contacts of the RF switch extend into passive segments of a PCM, wherein adhesion layers adhere the passive segments of the PCM to the contacts.

Phase-Change Material (PCM) Radio Frequency (RF) Switch with Reduced Parasitic Capacitance

A significantly reduced parasitic capacitance phase-change maternal (PCM) radio frequency (RF) switch includes an RF clearance zone including a step-wise structure of intermediate interconnect segments and vias to connect PCM contacts to setback top routing interconnects. The said RF clearance zone does not include cross-over interconnect segments. A low-k dielectric is situated in the RF clearance zone. A closed-air gap is situated in the RF clearance zone within the low-k dielectric. The setback top routing interconnects are situated higher over a substrate than the PCM contacts and the intermediate interconnect segments. The PCM RF switch may further include an open-air gap situated between the setback top routing interconnects.

Heating element designs for phase-change material (pcm) radio frequency (rf) switches

A radio frequency (RF) switch includes a heating element, a phase-change material (PCM) situated over the heating element, and PCM contacts situated over passive segments of the PCM. The heating element extends transverse to the PCM. The heating element can have a heater line underlying an active segment of the PCM. Alternatively, the heating element can have a split heater lines underlying an active segment of the PCM. The split heater lines increase an area of the active segment of the PCM and reduce a heater-to-PCM parasitic capacitance. A fan-out structure having fan-out metal can connect the heater line to a heater contact. The fan-out structure reduces heat generation outside the active segment of the PCM and reduces a heater contact-to-PCM parasitic capacitance. The fan-out structure can have dielectric segments interspersed between the fan-out metal to reduce dishing.

Read Out Integrated Circuit (ROIC) for Rapid Testing and Characterization of Resistivity Change of Heating Element in Phase-Change Material (PCM) Radio Frequency (RF) Switch

A rapid testing read out integrated circuit (ROIC) includes phase-change material (PCM) radio frequency (RF) switches residing on an application specific integrated circuit (ASIC). Each PCM RF switch includes a PCM and a heating element transverse to the PCM. The ASIC is configured to provide amorphizing and crystallizing electrical pulses to a selected heating element in a selected PCM RF switch. The ASIC is also configured to generate data for determining and characterizing resistivity change of the selected heating element in the selected PCM RF switch after the ASIC performs a plurality of OFF/ON cycles. In one implementation, a testing method using the ASIC is disclosed.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes: a first and a second wirings; a third wiring disposed between them; a first phase change layer disposed between the first and the third wirings; a first conducting layer disposed on a first wiring side surface of the first phase change layer; a second conducting layer disposed on a third wiring side surface of the first phase change layer; a second phase change layer disposed between the third and the second wirings; a third conducting layer disposed on a third wiring side surface of the second phase change layer; and a fourth conducting layer disposed on a second wiring side surface of the second phase change layer. The first and the fourth conducting layers have coefficients of thermal conductivity larger or smaller than the coefficients of thermal conductivity of the second and the third conducting layers.

Resistive random access memory and manufacturing method thereof

A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.

Rf/dc decoupling system for rf switches based on phase change material

An RF switch provided with a first region based on a phase change material disposed between a first conductive element and a second conductive element and state control means for said first region, the switch being further provided with at least one first decoupling switch provided with a second region of phase change material.

Bromine containing silicon precursors for encapsulation layers

Methods of depositing silicon nitride encapsulation layers by atomic layer deposition over memory devices including chalcogenide material are provided herein. Methods include using iodine-containing and/or bromine-containing silicon precursors and depositing thermally using ammonia or hydrazine as a second reactant, or iodine-containing and/or bromine-containing silicon precursors and depositing using a nitrogen-based or hydrogen-based plasma.

Phase-Change Material (PCM) Radio Frequency (RF) Switch

A radio frequency (RF) switch includes a heating element, thermally conductive and electrically insulating layer over the heating element, a wetting dielectric layer over the thermally conductive and electrically insulating layer, and a phase-change material (PCM) over the wetting dielectric layer. At least one cladding dielectric layer can be situated over sides and/or over a top surface of the PCM. Each of the wetting dielectric layer, phase change material, and cladding dielectric layer can comprise at least germanium. A transitional dielectric layer can be situated between the thermally conductive and electrically insulating layer and the wetting dielectric layer. A contact uniformity support layer can be situated over the cladding dielectric layer.

Thermal dispersion layer in programmable metallization cell

Some embodiments relate to a method for manufacturing a memory device. The method includes forming a bottom electrode over a substrate. A heat dispersion layer is formed over the bottom electrode. A dielectric layer is formed over the heat dispersion layer. A top electrode is formed over the dielectric layer. The heat dispersion layer comprises a first dielectric material.

Cross-point memory and methods for fabrication of same

A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.

Memory cell comprising a phase-change material

A memory cell includes a phase-change material. A via is electrically connected with a transistor and an element for heating the phase-change material. An electrically-conductive thermal barrier is positioned between the via and the heating element.

Memory Arrays and Methods of Forming Memory Cells

Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.

Uniform Plate Slot Contacts for Improving Performance in Phase-Change Material (PCM) Radio Frequency (RF) Switches

A radio frequency (RF) switch includes a phase-change material (PCM) and a heating element underlying an active segment of the PCM, the PCM and heating element being situated over a substrate. A contact dielectric is over the PCM. PCM contacts have upper portions and uniform plate slot lower portions. The uniform plate slot lower portions have a total plate resistance R PLATE , and a total plate slot interface resistance R PLATE-INT . The upper portions have a total capacitance C UPPER to the uniform plate slot lower portions, and the PCM has a total capacitance C PCM to the substrate. The uniform plate slot lower portions significantly reduce a product of (R PLATE +R PLATE-INT ) and (C UPPER +C PCM ). As an alternative to the uniform plate slot lower portions, PCM contacts have segmented lower portions. The segmented lower portions significantly reduce C UPPER .

Display apparatus

Display apparatuses are disclosed. In one arrangement, a display apparatus comprises a plurality of pixel units. Each pixel unit comprises: an optically switchable element; a heater operable to apply heating to the optically switchable element and thereby change an optical property of the optically switchable element; and a drive unit for driving the heater in response to a drive signal. The drive unit is provided within a first layer. The optically switchable elements and heaters of the plurality of pixel units are separated from the first layer by at least a portion of a second layer. An average thermal conductivity of the second layer is lower than an average thermal conductivity of the first layer.

Phase change material switch and method of making the same

A phase change material (PCM) switch is disclosed that includes a resistive heater element, and a PCM element proximate the resistive heater element. A thermally conductive electrical insulating barrier layer positioned between the PCM heating element and the resistive heating element, and conductive lines extend from ends of the PCM element and control lines extend from ends of the resistive heater element

Dual resistance heater for phase change devices and manufacturing method thereof

A dual resistance heater for a phase change material region is formed by depositing a resistive material. The heater material is then exposed to an implantation or plasma which increases the resistance of the surface of the heater material relative to the remainder of the heater material. As a result, the portion of the heater material approximate to the phase change material region is a highly effective heater because of its high resistance, but the bulk of the heater material is not as resistive and, thus, does not increase the voltage drop and the current usage of the device.

Memory device having a ring heater

A semiconductor device includes a base structure of a memory device including a first electrode, first dielectric material having a non-uniform etch rate disposed on the base structure, a via within the first dielectric material, and a ring heater within the via on the first electrode. The ring heater has a geometry based on a shape of the via that produces a resistance gradient.

Multistage set procedure for phase change memory

Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

Phase change memory cell

A phase change memory cell includes a first circuit and a second circuit. The first circuit includes a first electrode, a carbon nanotube wire and a second electrode electrically connected in series; wherein the first circuit is adapted to write data into the phase change memory cell or reset the phase change memory cell. The second circuit includes a third electrode, a phase change layer, the carbon nanotube wire, and the first electrode or the second electrode electrically connected in series, wherein the second circuit is adapted to read data from the phase change memory cell or reset the phase change memory cell, the carbon nanotube wire includes a bending portion, the third electrode is spaced from the bending portion, and the phase change layer covers the bending portion of the carbon nanotube wire.

Integration of confined phase change memory with threshold switching material

A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.

Memory Arrays and Methods of Forming Memory Arrays

Some embodiments include memory arrays having a plurality of memory cells vertically between bitlines and wordlines. The memory cells contain phase change material. Heat shields are laterally between immediately adjacent memory cells along a bitline direction. The heat shields contain electrically conductive material and are electrically connected with the bitlines. Some embodiments include memory arrays having a plurality of memory cells arranged in a first grid. The first grid has columns along a first direction and has rows along a second direction substantially orthogonal to the first direction. First heat shields are between adjacent memory cells along the first direction and are arranged in a second grid offset from the first grid along the first direction. Second heat shields are between adjacent memory cells along the second direction, and are arranged lines in lines extending along the first direction. Some embodiments include methods for forming memory arrays.

Multistage set procedure for phase change memory

Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

Fast erasing memristors

A fast erasing memristor includes an active region, a resistive heater, and a dielectric sheath. The active region has a switching layer coupled between a first conducting layer and second conducting layer. The resistive heater is coupled to the active region to provide heat to the active region. The dielectric sheath separates the active region and the resistive heater.

Semiconductor memory device and manufacturing methods thereof

According to one embodiment, the semiconductor memory device includes a first electrode, a first material layer, comprising a first material, located on the first electrode, a second material, surrounded by the first material of the first material layer, comprising a phase change material, and a second electrode provided on the first material.

Thermal-disturb mitigation in dual-deck cross-point memories

A thermal isolation layer is formed between the bit line (BL) layers or word line (WL) layers of the decks of a multi-deck phase-change cross-point memory to mitigate thermal problem disturb of memory cells that tends to increase as memory sizes are scaled smaller. Embodiments of the subject matter disclosed herein are suitable for, but are not limited to, solid-state memory arrays and solid-state drives.

Resistance change element and method of manufacturing such

A resistance change element includes a first lead electrode, a resistance change layer provided on the first lead electrode, and a second lead electrode provided on the resistance change layer. The surface of the first lead electrode on the resistance change layer side includes a first region in which the resistance change layer is provided, and a second region that is a region other than the first region. In the second region, a second material having a work function that is larger than that of a first material configuring the first lead electrode is unevenly distributed.

Method for Rapid Testing of Functionality of Phase-Change Material (PCM) Radio Frequency (RF) Switches

A rapid testing read out integrated circuit (ROIC) includes phase-change material (PCM) radio frequency (RF) switches residing on an application specific integrated circuit (ASIC). Each PCM RF switch includes a PCM and a heating element transverse to the PCM. The ASIC is configured to provide amorphizing and crystallizing electrical pulses to a selected PCM RF switch. The ASIC is also configured to determine if the selected PCM RF switch is in an OFF state or in an ON state. In one implementation, a testing method using the ASIC is disclosed.

Phase change memory

A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.

Semiconductor memory device

A semiconductor memory device includes a first wiring extending in a first direction, a second wiring above the first wiring and extending in a second direction, first and second memory cells electrically connected in parallel between the first and second wirings and each including a phase change material, a first insulating film on a side portion of the first cell facing the second cell in the second direction, a third wiring above the second wiring and extending in the second direction, a fourth wiring above the third wiring and extending in the first direction, third and fourth memory cells electrically connected between the third and fourth wirings in parallel and each including a phase change material, and a second insulating film on a side of the third cell facing the fourth cell in the second direction. The first film has a higher thermal insulation capacity than the second film.

Phase change memory element

A phase-change memory element is provided. The phase-change memory element may include an electrode; a phase-change material that contacts the electrode; a first conductor that contacts the phase-change material; and a second conductor that contacts the phase-change material. The second conductor may be electrically connected to the first conductor only through the phase-change material, and each of the first and second conductors may be electrically connected to the electrode only through the phase-change material.

Electronic device and operation method thereof

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a plurality of first lines extending in a first direction and arranged in parallel to each other; a plurality of second lines extending in a second direction crossing the plurality of first lines and arranged in parallel to each other; and a plurality of memory cells disposed in intersection regions of the plurality of first lines and the plurality of second lines, respectively, and wherein each of the memory cells may include: a selecting element including a switching element and a thermoelectric element that are coupled to each other, the switching element having a non-linear current-voltage characteristic; a variable resistance element coupled to the selecting element; and a heat insulating member surrounding at least a sidewall of the selecting element.

Reducing cell-to-cell switch variation in crossbar array circuits

Technologies relating to one-selector-one-memristor (1S1R) crossbar array circuits methods for reducing 1S1R cell-to-cell switch variations are disclosed. An example apparatus includes: a bottom electrode; a filament forming layer formed on the bottom electrode; an oxidized filament forming layer; a channel forming layer formed on the filament forming layer; an oxidized filament forming layer; a top electrode formed on the channel forming layer, wherein the filament forming layer is configured to form a filament within the filament forming layer, the channel forming layer is configured to form a channel within the channel forming layer when applying a switching voltage upon the filament forming layer and the channel forming layer, and wherein the filament forming layer is surrounded by the oxidized filament forming layer and the channel forming layer is surrounded by the oxidized channel forming layer.

Thermally optimized phase change memory cells and methods of fabricating the same

A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.

Phase change memory apparatus

A phase change memory apparatus comprises at least one heating layer; and at least one phase change layer comprising a vanadium dioxide layer, wherein each of the at least one phase change layer is set corresponding to each of the at least one heating layer, the at least one heating layer is configured to heat the at least one phase change layer.

Method for producing a device

A method for producing a device includes depositing a lower electrode metal and a film whose resistance changes. The film whose resistance changes and the lower electrode metal are etched to form a pillar-shaped phase-change layer and a lower electrode. A reset gate insulating film and a reset gate metal are deposited and etched to form reset gates.

Providing thermal shield to rram cells

The technology of a crossbar array circuit and method of improving thermal shielding are disclosed. An example apparatus includes a bottom wire; a first vertical thermal shielding layer formed on the bottom wire, a bottom electrode formed on the first vertical thermal shielding layer; a filament forming layer formed on the bottom electrode; a top electrode formed on the filament forming layer; a second vertical thermal shielding layer formed on the top electrode; a top wire formed on the second vertical thermal shielding layer, wherein the filament forming layer is configured to form a filament within the filament forming layer when applying a switching voltage upon the filament forming layer, and wherein a material of the first vertical thermal shielding layer and the second vertical thermal shielding layer includes ReO x , RuO x , IrO x , ITO, a combination thereof, or an alloy or doping thereof (with or without other thermally conductive materials).

Memory device with low density thermal barrier

Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.

Pcm switch and method of making the same

One example includes a method for making a switch. The method includes forming an insulating layer over a substrate. The method also includes forming a resistive heating material over the insulating layer. The method also includes depositing a thermally conductive electrically insulating barrier layer over the heating material. The method also includes forming a phase-change material (PCM) component over the barrier layer spaced apart and proximal to the resistive heating material. The method also includes forming a quench layer proximal to at least one of the resistive heating material and the PCM component. The method further includes forming conductive lines from ends of the PCM component and control lines from ends of the resistive heating material.

Memory cell comprising a phase-change material

A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.

상변화 메모리 소자와 그 동작 및 제조 방법

상변화 메모리 소자(PRAM)와 그 동작 및 제조 방법에 관해 개시되어 있다. 여기서, 본 발명은 스위칭 소자와 이에 연결된 스토리지 노드를 포함하는 상변화 메모리 소자에 있어서, 상기 스토리지 노드는 상기 스위칭 소자에 연결된 하부전극과, 상기 하부전극 상에 형성된 상변화층과, 상기 상변화층 상에 형성된 상부전극을 포함하되, 상기 하부 및 상부전극은 상기 상변화층보다 녹는점이 높고 상이한 타입의 열전 물질로 이루어진 것을 특징으로 하는 상변화 메모리 소자와 이것의 동작 및 제조 방법을 제공한다. 상기 하부전극의 상부면은 오목하게 될 수 있고, 상기 하부전극과 상기 상변화층사이에 하부전극 콘택층이 더 구비될 수 있다. 또한, 상기 상변화층의 두께는 100nm이하이며, 하부전극은 N형 열전 물질(thermoelectric material)로, 상기 상부전극은 P형 열전 물질로 각각 형성될 수 있고, 반대로 형성될 수 있다. 상기 하부전극, 상변화층 및 상부전극의 씨백 계수는 서로 다를 수 있다.

Laser-Written Submicron Pixels with Tunable Circular Polarization and Write-Read-Erase-Reuse Capability on a Nano Material or Two-Dimensional Heterostructure at Room Temperature

A method of laser-writing submicron pixels with tunable circular polarization and write-read-erase-reuse capability on Bi2Se3/WS2 at room temperature, comprising the steps of applying a laser to the Bi2Se3/WS2, writing a submicron pixel, wherein the submicron pixel has a circular polarization, modifying the circular polarization, allowing the circular polarization to be tuned across a range of 39.9%, tuning photoluminescence intensity, and tuning photoluminescence peak position. A method of growing Bi2Se3/WS2 as a nano-material or two-dimensional heterostructure for laser-writing submicron pixels with tunable circular polarization and write-read-erase-reuse capability on the Bi2Se3/WS2 heterostructure at room temperature.

Phase-Change Material Switches with Isolated Heating Elements

Circuits and methods that enable stacking of phase change material (PCM) switches and that accommodate variations in the resistance of the resistive heater(s) of such switches. Stacking is enabled by providing isolation switches for the resistive heater(s) in a PCM switch to reduce parasitic capacitance caused by the proximity of the resistive heater(s) to the PCM region of a PCM switch. Variations in the resistance of the resistive heater(s) of a PCM switch are mitigated or eliminated by sensing the actual resistance of the resistive heater(s) and then determining a suitable adjusted electrical pulse profile for the resistive heater(s) that generates a precise thermal pulse to the PCM region, thereby reliably achieving a desired switch state while extending the life of the resistive heater(s) and the phase-change material.

Tunable inductor device

Disclosed is a tunable inductor device having a substrate, a planar spiral conductor having a plurality of spaced-apart turns disposed over the substrate, and a phase change switch (PCS) having a patch of a phase change material (PCM) disposed over the substrate between and in contact with a pair of adjacent segments of the plurality of spaced-apart turns, wherein the patch of the PCM is electrically insulating in an amorphous state and electrically conductive in a crystalline state. The PCS further includes a thermal element disposed adjacent to the patch of PCM, wherein the thermal element is configured to maintain the patch of the PCM to within a first temperature range until the patch of the PCM converts to the amorphous state and maintain the patch of the PCM within a second temperature range until the first patch of PCM converts to the crystalline state.

듀얼 히터를 갖는 비-휘발성 메모리소자 및 그 형성 방법

기판 상에 제1 도전성 라인이 배치된다. 상기 제1 도전성 라인 상에 스위칭 소자가 형성된다. 상기 스위칭 소자 상에 하부 히터가 형성된다. 상기 하부 히터 상에 데이터 저장 패턴이 형성된다. 상기 데이터 저장 패턴 상에 상부 히터가 형성된다. 상기 상부 히터 상에 제2 도전성 라인이 형성된다. 상기 상부 히터의 측면은 상기 하부 히터의 측면 및 상기 데이터 저장 패턴의 측면에 수직 정렬된다.

3차원 스택 구조를 갖는 상변화 메모리 장치

상변화 메모리 장치는 반도체 기판, 상기 반도체 기판상의 일 방향으로 연장되는 워드 라인 구조체, 및 상기 워드 라인 구조체의 양 측벽 각각으로부터 상호 평행하게 연장되는 하나 또는 그 이상의 상변화 구조체를 포함하며, 상기 상변화 구조체는 상기 워드 라인과 측벽과 콘택되는 스위칭 소자, 상기 스위칭 소자의 측부에 형성되는 가열 전극, 및 상기 가열 전극과 콘택되는 상변화 패턴으로 구성되는 상변화 메모리 셀을 포함한다.

Semiconductor devices

반도체 소자는, 기판 상에, 적층된 캡핑막, 선택막, 버퍼막, 가변 저항막 및 상부 전극막을 포함하는 셀 구조물들 구비된다. 상기 셀 구조물들이 반복 적층된 구조물이 구비된다. 상기 구조물을 관통하는 개구부 내부에는 상기 버퍼막, 가변 저항막 및 상부 전극막과 전기적으로 절연되고, 상기 선택막과 전기적으로 연결되는 전극 구조물이 구비된다. 상기 가변 저항막 및 상부 전극막 사이에 구비되고, 상기 가변 저항막으로 열을 가하기 위한 가열 전극이 구비된다. 상기 반도체 소자는 셀 들이 수직 적층됨으로써 고집적화될 수 있다.

Programmable switch device and fabricating method thereof

SiGeSb 히터의 제조 과정을 조정하여 스위치 소자의 성능을 향상시키는 프로그래머블 스위치 소자 및 그 제조 방법에 관한 것으로, 기판상에 형성된 SiO 2 층, 상기 SiO 2 층상에 형성된 SiGeSb 박막층, 상기 SiGeSb 박막층상에 형성된 GeSbTe 박막층, 상기 GeSbTe 박막층상에 형성된 제1 단자를 포함하고, 상기 SiGeSb 박막층은 고저항 발열층으로 기능하고, 상기 제1 단자는 비어 홀을 통해 상기 GeSbTe 박막층과 연결되는 구성을 마련한다. 상기와 같은 프로그래머블 스위치 소자 및 그 제조 방법을 이용하는 것에 의해, SiGeSb 합금을 적용한 칼코겐화물 프로그래머블 스위치 동작을 고찰하고, 열처리 온도 및 안티몬 원자 양을 조절하여 스위치 소자의 성능을 최적화할 수 있다. Adjusting the manufacturing process of SiGeSb heaters formed on the programmable switch element, and that relates to a production method, SiO 2 layer formed on a substrate, SiGeSb thin film layer formed on the SiO 2 layer, the SiGeSb thin film layer to improve the switch device performance GeSbTe The thin film layer includes a first terminal formed on the GeSbTe thin film layer, wherein the SiGeSb thin film layer functions as a high resistance heating layer, and the first terminal is connected to the GeSbTe thin film layer through a via hole. By using such a programmable switch element and its manufacturing method, the chalcogenide programmable switch operation to which the SiGeSb alloy is applied can be considered, and the heat treatment temperature and the amount of antimony atoms can be adjusted to optimize the performance of the switch element.

Phase-change memory device and method of manufacturing the same

상변화 메모리 장치 및 그 제조 방법이 개시된다. 콘택 영역이 형성된 반도체 기판 상에 반도체 기판에 대하여 수평한 방향으로 가변 저항 부재를 형성한 후, 가변 저항 부재의 일측으로부터 상기 콘택 영역까지 연장되는 제1 전극을 형성한다. 이어서, 상기 제1 전극에 대향하여 상기 가변 저항 부재의 타측으로부터 연장되는 제2 전극을 형성한다. 상기 상변화 메모리 장치는 자기 열 제한 구조의 가변 저항 부재를 포함하기 때문에 열 손실이나 상변화 물질층의 열화를 감소시키면서 없이 낮은 전류로 동작할 수 있다. 또한, 더욱이, 인접하는 상변화 메모리 장치가 하나의 전극을 공유하기 때문에 상변화 메모리 장치의 구조를 단순화시킬 수 있는 동시에 상변화 메모리 장치의 제조비용과 시간을 크게 절감할 수 있다. A phase change memory device and a method of manufacturing the same are disclosed. After the variable resistance member is formed in a horizontal direction with respect to the semiconductor substrate on the semiconductor substrate on which the contact region is formed, a first electrode extending from one side of the variable resistance member to the contact region is formed. Subsequently, a second electrode extending from the other side of the variable resistance member is formed to face the first electrode. Since the phase change memory device includes a variable resistance member having a magnetic thermal limiting structure, the phase change memory device may operate at a low current without reducing heat loss or degradation of the phase change material layer. Furthermore, since adjacent phase change memory devices share one electrode, the structure of the phase change memory device can be simplified, and the manufacturing cost and time of the phase change memory device can be greatly reduced.

Memory device and method for fabricating the same

본 발명의 기술적 사상은 본 발명의 기술적 사상이 해결하고자 하는 과제는 메모리 소자의 메모리 셀 형성 시, 가변 저항층의 식각 손상이 최소화되고 미스-얼라인 마진이 감소하여 신뢰성 있는 메모리 소자 및 그 제조방법을 제공한다. 그 메모리 소자는 메모리 셀들의 하부 물질층들은 양각 식각 공정을 통해 형성되되, 가변 저항층은 하부 물질층들과는 별도로 하드 마스크 또는 희생막을 이용하여 다마신 공정으로 형성됨으로써, 가변 저항층의 손상이 최소화된 메모리 셀들을 구현할 수 있도록 한다. 또한, 상기 하드 마스크 또는 희생막을 이용한 다마신 공정에 기인하여, 가변 저항층이 메모리 셀들의 하부 물질층들에 셀프-얼라인 되므로, 미스-얼라인 마진이 최소화될 수 있다. The technical idea of the present invention is to solve the problem to be solved by the technical idea of the present invention, a reliable memory device and method for manufacturing the same by minimizing etch damage of the variable resistance layer and reducing the misalignment margin when forming a memory cell of a memory device provides In the memory device, the lower material layers of the memory cells are formed through an embossed etching process, and the variable resistance layer is formed separately from the lower material layers by a damascene process using a hard mask or a sacrificial film, thereby minimizing damage to the variable resistance layer. It enables the implementation of memory cells. Also, due to the damascene process using the hard mask or the sacrificial layer, the variable resistance layer is self-aligned to the lower material layers of the memory cells, so that the misalignment margin can be minimized.

Phase change memory device and methods of manufacturing the same

상변화 메모리 장치는 제1 방향으로 연장하며 제1 방향에 수직한 제2 방향을 따라 배치되는 복수의 워드 라인, 워드 라인 상에 배열되며 제1 방향에 대해 제1 경사 각도의 사선 방향으로 배치되는 복수의 하부 전극들 및 각 하부 전극 상에 배치되는 상변화 물질 패턴을 포함한다. 인접하는 하부 전극 및 상변화 물질 패턴 사이의 거리를 증가시켜 메모리 셀들 사이의 써멀 크로스토크 현상을 방지할 수 있다. The phase change memory device comprises a plurality of word lines extending in a first direction and arranged along a second direction perpendicular to the first direction, arranged on the word lines and arranged in a diagonal direction at a first tilt angle relative to the first direction A plurality of lower electrodes and a phase change material pattern disposed on each lower electrode. It is possible to increase the distance between the adjacent lower electrodes and the phase change material pattern to prevent thermal crosstalk between the memory cells.

Phase change material memory device

一种可使用单一的、杯状相变材料(18)形成的相变材料存储器单元(10)。该杯状相变材料(18)的内部可使用热绝缘材料(22)填充。结果是，可通过该杯状相变材料(18)减少在一些实施例中的向上的热损失以及相变材料(18)和装置(10)的剩余部分之间的粘附问题。此外，阻挡层(20)可被设置在上部电极(28)和装置(10)的剩余部分之间，以减少一些实施例中从上部电极向相变材料(18)中的物质引入。可使用化学机械抛光以限定相变材料(18)，减少一些实施例中的相变材料干法蚀刻的影响。

Non-volatile memory device and manufacturing method thereof

A non-volatile memory device of the present invention comprises a first electrode; a variable resistance layer formed on and above the first electrode; a second electrode formed on and above the variable resistance layer; a side wall protective layer having an insulativity and covering a side wall of the first electrode, a side wall of the variable resistance layer and a side wall of the second electrode; and an electrically-conductive layer connected to the second electrode; the non-volatile memory device including a connection layer which is provided between the second electrode and the electrically-conductive layer to connect the second electrode and the electrically-conductive layer to each other, and comprises an electrically-conductive material different from a material constituting the electrically-conductive layer; wherein the side wall protective layer extends across the second electrode to a position which is above an upper end of the second electrode and below an upper end of the connection layer such that an upper end of the side wall protective layer is located above the upper end of the second electrode and below the upper end of the connection layer, when viewed from a side.

Non-volatile memory device and manufacturing method thereof

A non-volatile memory device of the present invention comprises a first electrode; a variable resistance layer formed on and above the first electrode; a second electrode formed on and above the variable resistance layer; a side wall protective layer having an insulativity and covering a side wall of the first electrode, a side wall of the variable resistance layer and a side wall of the second electrode; and an electrically-conductive layer which is in contact with the second electrode; wherein the electrically-conductive layer covers an entire of the second electrode and at least a portion of the side wall protective layer located outward relative to the second electrode, when viewed from a thickness direction; and the side wall protective layer extends across the second electrode to a position above an upper end of the second electrode such that an upper end of the side wall protective layer is located above the upper end of the second electrode, when viewed from a side.

Phase change memory with adjustable resistance ratio and fabricating method thereof

Phase change memory unit and preparation method thereof

一种相变存储器单元及其制备方法，其从下到上依次包括位于衬底上的底电极、相变单元、加热电极和顶电极；其中，相变单元为纵向连接设置于底电极上的柱体，其由内而外依次设置有柱形相变材料层、环形散热层和环形选择器件层；顶电极与加热电极和相变材料层依次连接，环形选择器件层连接底电极。因此，本发明通过采用散热层包覆相变电阻层使电流密度和热量分布更加集中，从而固定相变有效操作区域，使相变电阻层有效区域体积减小，降低了器件功耗；同时，散热层与相变电阻层非有效操作区域的接触面积增大，减小非有效操作区域的热量聚集，降低非有效区域转化为有效区域的可能，提高器件可靠性。

Thin film fuse phase change cell and manufacture method thereof with insulating liners

本发明公开一种存储器件，其包括：第一电极，该第一电极具有顶侧；第二电极，该第二电极具有顶侧；以及位于第一与第二电极之间的绝缘构件。绝缘构件在第一与第二电极之间、接近第一电极的顶侧处与第二电极的顶侧处具有一厚度，并从第一与第二电极的顶侧向外延伸，限定具有顶侧的绝缘材料侧壁。存储材料导桥横跨侧壁顶侧的绝缘构件，并在第一与第二电极间、横跨绝缘构件处限定一电极间路径。本发明还提供了这种存储单元的阵列。此导桥在侧壁的顶侧上包括存储材料活性层，其具有至少二固态相，以及于存储材料之上的一层热绝缘材料，其导热性低于第一与第二电极的导热性。

Phase change memory devices and methods for fabricating the same

본 발명은 상변화 메모리 소자 및 그 제조방법에 관한 것으로, 제1 방향으로 연장되는 워드라인들과 상기 제1 방향과 교차하는 제2 방향으로 연장되는 비트라인들 사이의 교차점들에 제공된 메모리 셀들과, 상기 메모리 셀들 사이에 제공되고 상기 메모리 셀들 사이를 이격시키는 에어 갭들을 갖는 몰드막을 포함한다. 상기 메모리 셀은 상기 워드라인과 전기적으로 연결되고 상기 제1 방향을 따라 제1 폭을 갖는 하부전극과, 상기 비트라인과 전기적으로 연결되고 상기 제1 방향을 따라 상기 제1 폭에 비해 큰 제2 폭을 갖는 상부전극과, 그리고 상기 하부전극과 상기 상부전극 사이에 제공되고 상기 제1 방향을 따라 상기 제1 폭을 갖는 상변화막을 포함한다. The present invention relates to a phase-change memory device and a method of manufacturing the same, and more particularly, to a phase-change memory device and a method of manufacturing the same, in which a memory cell is provided at intersections between word lines extending in a first direction and bit lines extending in a second direction crossing the first direction And a mold film provided between the memory cells and having air gaps for spacing between the memory cells. The memory cell comprising a lower electrode electrically connected to the word line and having a first width along the first direction and a second electrode electrically connected to the bit line and having a second, And a phase change film provided between the lower electrode and the upper electrode and having the first width along the first direction.

Phase change memory devices and methods of manufacturing the same

상변화 메모리 장치는 상변화 메모리 유닛 및 히트 싱크를 포함한다. 상변화 메모리 유닛은 상변화 물질막 패턴, 상변화 물질막 패턴 하부에 형성되어 상변화 물질막 패턴을 가열하는 하부 전극 및 상변화 물질막 패턴 상부에 형성된 상부 전극을 포함한다. 히트 싱크는 상부 전극의 저면보다 낮은 상면을 갖고 상변화 메모리 유닛과 이격되며, 상변화 메모리 유닛으로부터 발산되는 열을 흡수한다.

The manufacture method of nonvolatile semiconductor memory member and nonvolatile semiconductor memory member

本发明涉及一种非易失性存储器件和非易失性存储器件的制造方法。在所述非易失性存储器件中层叠有第一电极、具有正的珀尔帖系数的第一材料层、信息存储层、具有负的珀尔帖系数的第二材料层和第二电极。根据本发明，能够抑制由于焦耳热导致的所述信息存储层的温度上升，因此能够抑制读干扰现象的发生。

Memory stack

本发明提供存储器堆叠及其形成方法。存储器堆叠包含：底部电极层、顶部电极层以及位于底部电极层与顶部电极层之间的相变层。顶部电极层的宽度大于相变层的宽度。未被相变层覆盖的顶部电极层的第一部分比被相变层覆盖的顶部电极层的第二部分更粗糙。

Thin film self-switching device

A self-switching device includes a thin film conductive line and a gap in the thin film conductive line having disposed therein a resistance change (RC) material. Upon application of a current across the gap, the RC material transitions from a low resistance state (LRS) to a high resistance state (HRS), and wherein upon attaining the HRS, the RC material transitions from the HRS to the LRS by self-switching.

Resistive random access memory access cells having thermally isolating structures

Provided are resistive random access memory (ReRAM) cells including resistive switching layers and thermally isolating structures for limiting heat dissipation from the switching layers during operation. Thermally isolating structures may be positioned within a stack or adjacent to the stack. For example, a stack may include one or two thermally isolating structures. A thermally isolating structure may directly interface with a switching layer or may be separated by, for example, an electrode. Thermally isolating structures may be formed from materials having a thermal conductivity of less than 1 W/m*K, such as porous silica and mesoporous titanium oxide. A thermally isolating structure positioned in series with a switching layer generally has a resistance less than the low resistance state of the switching layer. A thermally isolating structure positioned adjacent to a switching layer may have a resistance greater than the high resistance state of the switching layer.

Information recording medium and its mfg. method

本发明提供了记录层和介电体层之间即使不设界面层也能确保高可靠性、良好的反复改写性能的信息记录介质。在基板1的表面上形成记录层4和介电体层2和6，记录层4通过光照射或施加电能在晶相和非晶相之间产生相转变，介电体层2和6是例如用式(ZrO 2 ) M (Cr 2 O 3 ) 100-M (摩尔%)(式中M在20≤M≤80)表示的材料组成的Zr-Cr-O基材料层。

Method to manufacture a phase change memory

Briefly, in accordance with an embodiment of the invention, a method to manufacture a phase change memory is provided. The method may include forming a first electrode contacting the sidewall surface and the bottom surface of the phase change material. The method may further include forming a second electrode contacting the top surface of the phase change material.

MEMORY PROGRAMMABLE MEMORY MICROELECTRONIC DEVICE COMPRISING A DOPE CHALCOGENURE LAYER RESISTANT AT HIGH TEMPERATURES

NON-VOLATILE MEMORY CHIP ON BOARD WITH PHASE CHANGE MATERIAL

L'invention concerne un procédé de fabrication d'une puce électronique comportant des points mémoire à matériau à changement de phase (134) et des transistors (110, 112), comprenant : a) former les transistors et des premiers et deuxièmes vias (120B, 120A) s'étendant depuis des bornes (122A, 122B) des transistors et atteignant une même hauteur ; b) former un premier niveau de métal comprenant des premières pistes d'interconnexion (202) en contact avec les premiers vias (120B) ; c) former des éléments de chauffage (132) des matériaux à changement de phase sur les deuxièmes vias (120A) ; d) former les matériaux à changement de phase (134) sur les éléments de chauffage (132) ; et e) former un deuxième niveau de métal comprenant des deuxièmes pistes d'interconnexion et situé au-dessus des matériaux à changement de phase, et former des troisièmes vias (204) s'étendant des matériaux à changement de phase jusqu'aux deuxièmes pistes. The invention relates to a method for manufacturing an electronic chip comprising phase change material memory cells (134) and transistors (110, 112), comprising: a) forming the transistors and first and second vias (120B , 120A) extending from the terminals (122A, 122B) of the transistors and reaching the same height; b) forming a first metal level comprising first interconnect tracks (202) in contact with the first vias (120B); c) forming heating elements (132) of the phase change materials on the second vias (120A); d) forming the phase change materials (134) on the heating elements (132); and e) forming a second metal level including second interconnect tracks and located above the phase change materials, and forming third vias (204) extending from the phase change materials to the second tracks .

Programmable metallization cell-type non-volatile rewritable memory, has heating unit placed directly under inert cathode without contact between anode and cathode, where voltage is applied between contacts to permit heating of active zone

The memory has an active zone (4), an inert cathode (6) and an anode (8). A heating unit (20) is placed directly under the inert cathode without any contact between the anode and the cathode. A voltage is applied between contacts (10, 16) to permit writing in the zone and a voltage is applied between contacts (16, 18) to permit heating of the zone during writing.

Patent FR2098516A5

A metal-insulator semiconductor structure for use in particular as a switching element with thermally reversible memory and comprising a semiconductor substrate, a film of amorphous insulator material on the said substrate and a metallic film which is deposited at least partially on the said insulator film, characterized in that the said amorphous insulator film exhibits a resistivity which is lower than the intrinsic resistivity of the said amorphous insulator material and which is comprised between 107 and 1011 OMEGA -cm at ambient temperature, the decrease in the said resistivity being due to the diffusion of ions into the said amorphous insulator film, the said structure being in a conducting or insulating stage within a predetermined temperature range, in an insulating state above the said range and in a conducting state below the said range.

METHOD FOR MANUFACTURING A CBRAM MEMORY HAVING IMPROVED RELIABILITY

L'invention concerne un procédé de réalisation d'une pluralité de mémoires de type CBRAM, comportant chacune une cellule mémoire en un électrolyte solide de type chalcogénure, une anode, et une cathode, ce procédé comportant la mise en oeuvre d'une sous-couche (30) de matériau de conductivité thermique élevée, supérieure à 1,3W/m/K, qui recouvre l'ensemble des contacts (28), puis la formation, sur ladite sous-couche d'un tricouche (32, 34, 36), comportant une couche de chalcogénure (32), puis une couche d'anode (34), et une couche de deuxièmes contacts (36), et enfin une étape de gravure. The invention relates to a method for producing a plurality of CBRAM type memories, each comprising a memory cell made of a chalcogenide solid electrolyte, an anode, and a cathode, this method comprising the implementation of a sub-type element. layer (30) of high thermal conductivity material, greater than 1.3W / m / K, which covers all of the contacts (28), then forming, on said sub-layer of a trilayer (32, 34, 36), having a chalcogenide layer (32), then an anode layer (34), and a second contact layer (36), and finally an etching step.

MEMORY POINT A PHASE CHANGE MATERIAL

L'invention concerne un point mémoire à matériau à changement de phase, comprenant, sur un via (108) de liaison avec un transistor, un élément de chauffage (116) du matériau à changement de phase (118), et, entre le via et l'élément de chauffage (116), une couche (202) en un matériau électriquement isolant ou de résistivité électrique supérieure à 2,5·10-5 Ω.m, les interfaces entre ladite couche et les matériaux en contact avec les deux faces de ladite couche formant une barrière thermique, ladite couche étant suffisamment mince pour pouvoir être traversée par un courant électrique par un effet de type effet tunnel.

Current adjustment device for electrical circuit

Semiconductor memory device and method for fabricating semiconductor memory device

According to an aspect of the present invention, there is provided a semiconductor memory device, including, a semiconductor substrate, a phase-change element formed on the semiconductor substrate, the phase-change element including a phase-change film and electrode films, a joule heat portion contacting with the electrode film, the phase-change film being formed around the joule heat portion, and a radiation-shield film suppressing dissipation of thermal radiation emitted from the joule heat portion.

Memory erasure using proximity heaters

A memory array with memory cells may have one or more heaters integrated into the memory array between the memory cells. A processor in communication with the heater may notify the heater to activate when a trigger event occurs.

Phase change memory devices with reduced programming current

A phase change memory device and a method of forming the same are provided. The phase change memory device includes a conducting electrode in a dielectric layer, a bottom electrode over the conducting electrode, a phase change layer over the bottom electrode, and a top electrode over the phase change layer. The phase change memory device may further include a heat sink layer between the phase change layer and the top electrode. The resistivities of the bottom electrode and the top electrode are preferably greater than the resistivity of the phase change material in the crystalline state.

Phase-change memory cell and method of fabricating the phase-change memory cell

A memory cell (and method of fabricating the memory cell) includes a stencil layer having a first opening, a phase-change material layer formed on a first electrode layer, and an electrically conductive layer formed on the first electrode layer, the electrically conductive layer having a pillar-shaped portion which is formed on the phase-change material layer and fills the first opening.

Memory devices with enhanced isolation of memory cells, systems including same and methods of forming same

Memory cells of a memory device including a variable resistance material have a cavity between the memory cells. Electronic systems include such memory devices. Methods of forming a memory device include providing a cavity between memory cells of the memory device.

Phase change memory device and method for manufacturing the same

본 발명은 히터의 콘택 저항을 낮추면서 상변화막의 비정질 상을 안정적으로 형성할 수 있는 상변화 기억 소자 및 그 제조방법을 개시한다. 개시된 본 발명의 상변화 기억 소자는, 셀 지역 및 주변 지역을 갖는 실리콘 기판; 상기 실리콘 기판의 셀 지역 상에 형성되며, 다수의 홀을 갖는 제1절연막; 상기 홀 내에 리세스되게 형성된 셀 스위칭 소자; 상기 셀 스위칭 소자가 형성된 홀 상에 상기 제1절연막으로부터 돌출되게 형성된 히트싱크; 상기 실리콘 기판의 주변 지역에 형성되며, 게이트절연막, 제1게이트도전막, 제2게이트도전막 및 하드마스크막의 적층 구조로 이루어진 게이트; 상기 히트싱크 및 게이트가 형성된 실리콘 기판의 전면 상에 형성되며, 상기 히트싱크를 노출시키는 콘택홀을 구비하고 상기 게이트의 하드마스크막이 노출되도록 형성된 제2절연막; 상기 콘택홀 내에 형성된 히터; 및 상기 히터 상에 형성된 상변화막과 상부전극의 적층 패턴;을 포함한다. The present invention discloses a phase change memory device capable of stably forming an amorphous phase of a phase change film while lowering a contact resistance of a heater and a method of manufacturing the same. The disclosed phase change memory device comprises: a silicon substrate having a cell region and a peripheral region; A first insulating layer formed on a cell region of the silicon substrate and having a plurality of holes; A cell switching element formed to be recessed in the hole; A heat sink protruding from the first insulating layer on the hole where the cell switching element is formed; A gate formed in a peripheral region of the silicon substrate and having a stacked structure of a gate insulating film, a first gate conductive film, a second gate conductive film, and a hard mask film; A second insulating layer formed on an entire surface of the silicon substrate on which the heat sink and the gate are formed, and having a contact hole exposing the heat sink and formed to expose a hard mask film of the gate; A heater formed in the contact hole; And a stacked pattern of a phase change film and an upper electrode formed on the heater.

Multi-level memory cell having phase change element and asymmetrical thermal boundary

A multi-level, phase change memory cell has first and second thermal isolation materials having different thermal conductivity properties situated in heat-conducting relation to first and second boundaries of the phase change material. Accordingly, when an electrical current is applied to raise the temperature of the memory material, heat is drawn away from the memory material asymmetrically along a line orthogonal to electric field lines between the electrodes.

Wafer-to-wafer and die-to-wafer bonding of phase-change material (PCM) switches with integrated circuits and bonded two-die devices

In a method for wafer-to-wafer bonding, an integrated circuit (IC) wafer and a phase-change material (PCM) switch wafer are provided. The IC includes at least one active device, and has an IC substrate side and a metallization side. The PCM switch wafer has a heat spreading side and a radio frequency (RF) terminal side. A heat spreader is formed in the PCM switch wafer. In one approach, the heat spreading side of the PCM switch wafer is bonded to the metallization side of the IC wafer, then a heating element is formed between the heat spreader and a PCM in the PCM switch wafer. In another approach, a heating element is formed between the heat spreader and a PCM in the PCM switch wafer, then the RF terminal side of the PCM switch wafer is bonded to the metallization side of the IC wafer.

Phase-change material RF switch

In manufacturing a radio frequency (RF) switch, a heat spreader is provided. A first dielectric is deposited over the heat spreader. A trench is etched in the first dielectric. A heating element is deposited in the trench and over at least a portion of the first dielectric. A thermally conductive and electrically insulating material is deposited over at least the heating element, where the thermally conductive and electrically insulating material is self-aligned with the heating element. A conformability support layer is optionally deposited over the thermally conductive and electrically insulating material and the first dielectric. A phase-change material is deposited over the optional conformability support layer and the underlying thermally conductive and electrically insulating material and the first dielectric.

Programmable via devices

A device comprises a heater, a dielectric layer, a phase-change element, and a capping layer. The dielectric layer is disposed at least partially on the heater and defines an opening having a lower portion and an upper portion. The phase-change element occupies the lower portion of the opening and is in thermal contact with the heater. The capping layer overlies the phase-change element and occupies the upper portion of the opening. At least a fraction of the phase-change element is operative to change between lower and higher electrical resistance states in response to an application of an electrical signal to the heater.

Directly heated rf phase change switch

An RF switch is provided with a direct heating method. The RF switch is comprised of two RF electrodes disposed on opposing sides of a phase change element. Depending on the state of the phase change material, the RF electrodes form a conductive path through the phase change material for an RF signal. To control the state of the phase change material, the RF switch further includes a heater formed from two heater electrodes. The two heater electrodes are configured to draw a current through the phase change element in a direction transverse to the conductive path.