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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 44. Отображено 44.
11-04-2016 дата публикации

METHOD FOR DESIGNING SEMICONDUCTOR DEVICE AND SYSTEM FOR DESIGNING SEMICONDUCTOR DEVICE

Номер: KR1020160039526A
Автор: BAEK, SANG HOON, SONG, TAE JOONG, YANG, GI YOUNG, DO, JEONG HO
Принадлежит:

A method for designing a semiconductor device and a system for designing a semiconductor device are provided. The method for designing a semiconductor device includes: providing a standard cell layout which includes an active region and a dummy region; determining a first fin pitch between a first active fin and a second active fin in the active region, and a second fin pitch between a first dummy fin and a second dummy fin in the dummy region; designing so that the first and second active fins can be arranged in the active region and the first and second dummy fins in the dummy region using the first and second fin pitches; and verifying the standard cell layout. COPYRIGHT KIPO 2016 (AA) Start (BB) End (S100) Provide standard cell layout including active region and dummy region (S110) Determine first and second pin pitch (S120) Design placement of active pin and dummy pin (S130) Verification ...

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Номер записи: 1
09-03-2017 дата публикации

SEMICONDUCTOR DEVICE

Номер: KR1020170027241A
Автор: SONG, TAE JOONG, KIM, HA YOUNG, DO, JUNG HO, BAEK, SANG HOON, LIM, JIN YOUNG, JEONG, KWANG OK
Принадлежит:

The present invention relates to a semiconductor device including a field effect transistor. More specifically, the semiconductor device comprises: a substrate having first and second active regions which have different conductivity types and are separated from each other in a first direction; gate electrodes which cross the first and the second active regions and are extended in the first direction; a first shallow separation pattern provided on an upper portion of the first active region and extended in the first direction; and a deep separation pattern provided on an upper portion of the second active region and extended in the first direction. The first shallow separation pattern and the deep separation pattern are arranged side by side in the first direction. The deep separation pattern divides the second active region into a first region and a second region. COPYRIGHT KIPO 2017 ...

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Номер записи: 2
22-02-2016 дата публикации

STATIC RANDOM ACCESS MEMORY DEVICE INCLUDING WRITE ASSIST CIRCUIT

Номер: KR1020160019594A
Автор: RIM, WOO JIN, SONG, TAE JOONG, KIM, GYU HONG, JUNG, SEONG OOK, JEONG, HAN WOOL
Принадлежит:

According to the present invention, a static random access memory device comprises: a write driver configured to float one of a first bit line and a second bit line connected to a memory cell and apply a write voltage to the other bit line in response to a logic state of a data signal; a write failure detection unit configured to receive a voltage of the floated bit line and output a write failure signal; and an assist voltage generation unit configured to generate a write assist voltage in response to the write failure signal. The write driver additionally provides the write assist voltage to a bit line to which the write voltage is applied. COPYRIGHT KIPO 2016 ...

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Номер записи: 3
30-05-2017 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: KR1020170059363A
Автор: DO, JUNG HO, JUNG, JONG HOON, BAEK, SANG HOON, LEE, SEUNG YOUNG, SONG, TAE JOONG, LIM, JIN YOUNG
Принадлежит:

A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of: forming first trenches defining active patterns extended in a first direction on a substrate; forming first mask patterns extended in the first direction with a first width in a second direction; forming a second mask pattern extended in the first direction with a second width in the second direction; and forming a second trench partially defining the active region by etching the active patterns using the first mask patterns and the second mask pattern. Accordingly, the present invention can prevent corner rounding of the active region with a tapered shape on the substrate. COPYRIGHT KIPO 2017 ...

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Номер записи: 4
24-03-2023 дата публикации

집적 회로 및 집적 회로의 설계 방법

Номер: KR102514044B1
Автор: 김하영, 송태중, 조성위
Принадлежит: 삼성전자주식회사

... 본 개시에 따른 집적 회로를 설계하기 위한 컴퓨터 구현 방법은, 복수의 로우들에 대응하는 멀티 하이트 셀인 제1 셀의 일 레이어에 해당하는 패턴들에 MPT를 적용하도록, 패턴들에 대해 복수의 컬러들을 할당하고, 제1 셀에 대하여, 로우 별로 패턴들에 대한 컬러 리맵핑이 수행된 복수의 쉬프트 셀들을 생성하며, 제1 셀 및 복수의 쉬프트 셀들을 포함하는 셀 세트를 표준 셀 라이브러리에 저장한다.

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Номер записи: 5
03-03-2016 дата публикации

STANDARD CELL LIBRARY, METHOD FOR USING SAME, AND METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT

Номер: KR1020160023535A
Автор: OH, SANG KYU, BAEK, SANG HOON, LEE, SEUNG YOUNG, SONG, TAE JOONG
Принадлежит:

The present invention relates to a standard cell library, a method for using the same, and a method for designing a semiconductor integrated circuit (IC). The method for designing the semiconductor integrated circuit comprises the following steps: preparing the standard cell library which includes characteristic information on a plurality of standard cells; detecting a characteristic change region which includes at least one of the plurality of standard cells, by comparing characteristics of the standard cells to be placed adjacent to the characteristic change region, based on the standard cell library; changing the characteristic of the standard cell included in the detected characteristic change region to one of the characteristics of the standard cells to be placed nearby; and placing a plurality of standard cells. According to the present invention, the standard cell library can prevent characteristic degradation of a semiconductor device in accordance with a semiconductor production ...

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Номер записи: 6
03-02-2016 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Номер: KR1020160012883A
Автор: DO, JUNG HO, BAEK, SANG HOON, OH, SANG KYU, CHUN, KWAN YOUNG, PARK, SUN YOUNG, SONG, TAE JOONG
Принадлежит:

The present invention relates to a method for manufacturing a semiconductor device comprising a field effect transistor, specifically comprising the following steps: defining a PMOSFET area and an NMOSFET area in a substrate; forming first and second gate electrodes; forming an interlayer insulation film having the first and second gate electrodes crossing the PMOSFET area and the NMOSFET area, while being extended in parallel, and covering the first and second gate electrodes; forming a first sub contact hole on the first gate electrode by patterning the interlayer insulation film; and forming a first gate contact hole exposing the upper surface of the second gate electrode by patterning the interlayer insulation film, while the first sub contact hole is located between the PMOSFET and NMOSFET areas in a planar aspect. Here, the first sub contact hole and the first gate contact hole are connected to form a single communicating hole. The subject of the present invention is providing the ...

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Номер записи: 7
11-05-2018 дата публикации

NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF

Номер: KR1020180049416A
Автор: PYO, SUK SOO, JUNG, HYUN TAEK, SONG, TAE JOONG, SEO, BO YOUNG
Принадлежит:

A method of operating a nonvolatile memory device according to the present invention may include a step of setting different data in first and second reference cells connected to a word line, a step of checking the first and second reference cells if the different data is stored, and a step of swapping the first and second reference cells if the different data is not stored. The nonvolatile memory device of the present invention can improve read reliability by swapping target data according to the characteristic of a reference cell when setting the reference cell. COPYRIGHT KIPO 2018 ...

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Номер записи: 8
29-05-2015 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: KR1020150058597A
Автор: BAEK, KANG HYUN, PARK, SUNG HYUN, BAEK, SANG HOON, SONG, TAE JOONG
Принадлежит:

Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: an active pin enlarged in a first direction with a shape protruding from an active layer, and arranged; a gate structure enlarged in a second direction crossing the first direction, and arranged on the active pin; and a spacer arranged on at least one side of the gate structure, wherein the active pin comprises a first area and a second area which is adjacent in the first direction on the first area, and the second direction width of the first area is different with the second direction width of the second area. COPYRIGHT KIPO 2015 ...

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Номер записи: 9
09-08-2017 дата публикации

SEMICONDUCTOR DEVICE TO SELECTIVELY PERFORM INSULATION AND LAYOUT METHOD THEREOF

Номер: KR1020170091487A
Автор: BAECK, SANG YEOP, KIM, TAE HYUNG, MOON, DAE YOUNG, SEO, DONG WOOK, LEE, IN HAK, CHOI, HYUN SU, SONG, TAE JOONG, CHOI, JAE SEUNG, KANG, JUNG MYUNG, KIM, HOON, YU, JI SU, JANG, SUN YUNG
Принадлежит:

The present invention is to provide a layout of a semiconductor device, which operates selectively as an insulation circuit or a driving circuit. A system on chip of the present invention may comprise a first semiconductor device and a second semiconductor device. According to the present invention, the first semiconductor device may comprise: an active area formed on a substrate to extend in a first direction; and a first gate electrode and a second gate electrode to extend in a second direction, which is vertical to the first direction, and to be arranged in the first direction on the active area. The second semiconductor device may comprise: a third gate electrode and a fourth gate electrode to extend in the second direction and to be arranged in the first direction on the active area. A first transistor formed by the first gate electrode and a third transistor formed by the third gate electrode may operate as a normal transistor. A second transistor formed by the second gate electrode ...

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Номер записи: 10
12-08-2015 дата публикации

LAYOUT DESIGN SYSTEM, SEMICONDUCTOR DEVICE FABRICATED BY USING SAME, AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

Номер: KR1020150091661A
Автор: BAEK, KANG HYUN, NOH, JIN HYUN, SONG, TAE JOONG, YANG, GI YOUNG, OH, SANG KYU
Принадлежит:

Provided are a layout design system, a semiconductor device fabricated by using the same, and a method for fabricating the semiconductor device. The layout design system includes a processor, a storage module which stores an intermediate design, and a correction module which corrects the intermediate design by using the processor. The intermediate design includes an active region and a plurality of dummy designs which are arranged on the active region. Each dummy design includes a dummy structure and dummy spacers which are arranged on both sides of the dummy structure. The correction module corrects the width of a partial region of the dummy designs. COPYRIGHT KIPO 2015 ...

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Номер записи: 11
09-02-2017 дата публикации

METHOD FOR DESIGNING LAYOUT OF SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING SAME

Номер: KR1020170015835A
Автор: SONG, TAE JOONG, BAEK, SANG HOON, CHO, SUNG WE, DO, JUNG HO, YANG, GI YOUNG, LIM, JIN YOUNG
Принадлежит:

The present invention relates to a method for designing a layout of a semiconductor device. More particularly, the present invention includes the steps of: configuring a standard cell layout including a step of placing a preliminary pin pattern in at least one wiring layout; performing routing with upper wiring layouts on the preliminary pin pattern; and forming a pin pattern in the wiring layout according to heating information obtained after performing the routing. The pin pattern is relatively smaller than the preliminary pin pattern. Accordingly, the present invention can optimize the pin patterns in the wiring layout of the standard cell layout. COPYRIGHT KIPO 2017 ...

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Номер записи: 12
10-07-2017 дата публикации

INTEGRATED CIRCUIT INCLUDING EMBEDDED MEMORY DEVICE CAPABLE OF PERFORMING DUAL-TRANSIENT WORD LINE ASSIST BY USING TRIPLE POWER SOURCE, AND APPARATUS INCLUDING SAME

Номер: KR1020170080403A
Автор: RIM, WOO JIN, SONG, TAE JOONG, KIM, YONG HO, PARK, SUNG HYUN
Принадлежит:

Disclosed is an integrated circuit. The integrated circuit comprises: an embedded memory device including a word line, a bit line pair, and a storage cell connected to the word line and the bit line pair; a timing control circuit generating switch signals in response to an operation control signal; and a switch circuit receiving a first voltage, a second voltage, and a third voltage having different levels, and supplying any one among the first voltage, the second voltage, and the third voltage to the word line in response to the switch signals. COPYRIGHT KIPO 2017 ...

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Номер записи: 13
20-02-2017 дата публикации

반도체 소자

Номер: KR0101707465B1
Автор: 송태중, 박재호, 백상훈, 김진태, 양기용, 원효식
Принадлежит: 삼성전자주식회사

... 본 발명은 전계 효과 트랜지스터를 포함하는 반도체 소자 및 이의 제조 방법에 관한 것으로, 전계 효과 트랜지스터에 있어서 전력 노드와 연결되는 제1 변형 콘택의 면적을 넓힘으로써 전압 강하(IR-DROP)를 줄일 수 있다. 나아가, 출력 노드와 연결되는 제2 변형 콘택의 이격 거리를 넓히고 제2 변형 콘택의 면적을 줄임으로써 기생 캐패시턴스를 감소시킬 수 있다. 이로써 소자의 전기적 특성이 향상될 수 있다.

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Номер записи: 14
29-05-2015 дата публикации

LAYOUT DESIGN SYSTEM, LAYOUT DESIGN METHOD, AND SEMICONDUCTOR DEVICE FABRICATED THEREBY

Номер: KR1020150058598A
Автор: BAEK, SANG HOON, OH, SANG KYU, HA, NA YA, PAEK, SEUNG WEON, SONG, TAE JOONG
Принадлежит:

Provided are a layout design system and a semiconductor device fabricated thereby. The layout design system includes a processor, a storage unit which stores a first unit design with a first cross section without arranging a termination on the edge thereof, and a design module which generates a second unit design with a second cross section which is larger than the first cross section by arranging the termination on the edge of at least one first unit design by using the processor. COPYRIGHT KIPO 2015 ...

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Номер записи: 15
24-03-2023 дата публикации

반도체 장치

Номер: KR20230041385A
Автор: 당호영, 심창수, 이어진, 김태형, 송태중
Принадлежит:

... 반도체 장치가 제공된다. 반도체 장치는, 제1 방향으로 연장되어 배치되는 구동 전압 메탈 라인, 제1 방향으로 연장되고, 구동 전압 메탈 라인으로부터 제1 방향과 교차하는 제2 방향으로 이격되는 비트 메탈 라인, 제1 방향으로 연장되고, 비트 메탈 라인으로부터 제2 방향으로 이격되는 접지 전압 메탈 라인, 및 구동 전압 메탈 라인과, 비트 메탈 라인과 접지 전압 메탈 라인 하부에 배치된 SRAM 셀을 포함하되, SRAM 셀은, 제1 스토리지 노드를 풀업(pull up)하는 제1 풀업 트랜지스터와, 제2 스토리지 노드를 풀업하는 제2 풀업 트랜지스터와, 제1 스토리지 노드를 비트 메탈 라인에 연결시키는 제1 패스 게이트(pass gate) 트랜지스터와, 제2 스토리지 노드를 비트 메탈 라인에 연결시키는 제2 패스 게이트 트랜지스터와, 제1 스토리지 노드를 풀다운(pull down)하는 제1 풀다운 트랜지스터와, 제2 스토리지 노드를 풀다운하는 제2 풀다운 트랜지스터를 포함하고, 비트 메탈 라인의 제2 방향 폭과 구동 전압 메탈 라인의 제2 방향 폭과, 접지 전압 메탈 라인의 제2 방향 폭은 서로 다르다.

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Номер записи: 16
08-03-2016 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Номер: KR1020160025435A
Автор: PARK, JAE HO, SONG, TAE JOONG, BAEK, SANG HOON, KIM, JIN TAE, YANG, GI YOUNG, WON, HYO SIG
Принадлежит:

The present invention relates to a semiconductor device having a field-effect transistor and a method for manufacturing the same. In the field-effect transistor, by widening an area of the first modified contact connected to a power node, a voltage drop (IR-DROP) can be reduced. In addition, by widening a spacing between a second modified contact connected to an output node and reducing an area of the second modified contact, parasitic capacitance can be reduced. As a result, electrical characteristics of the semiconductor device can be improved. COPYRIGHT KIPO 2016 ...

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Номер записи: 17
19-10-2018 дата публикации

STANDARD CELL AND INTEGRATED CIRCUIT INCLUDING SAME

Номер: KR1020180114812A
Автор: LEE, JAE BOONG, DO, JUNG HO, SONG, TAE JOONG, LEE, SEUNG YOUNG, JUNG, JONG HOON, YU, JI SU
Принадлежит:

According to an exemplary embodiment of the present disclosure, an integrated circuit including a plurality of standard cells to provide high degree of freedom of design may comprise: a power rail formed by using a plurality of conductive layers at the boundaries of the standard cells for providing power to the standard cells and extending in a first horizontal direction; and at least one signal line passing the power rail in a second horizontal direction orthogonal to the first horizontal direction to transfer an input signal or an output signal of the standard cells and formed at one of the conductive layers. The power rail may include a conductive line formed at the conductive layer in which at least one signal line is formed and extending in the first horizontal direction insulated with at least one signal line. COPYRIGHT KIPO 2018 ...

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Номер записи: 18
30-05-2017 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: KR1020170059371A
Автор: DO, JUNG HO, LEE, SEUNG YOUNG, JUNG, JONG HOON, LIM, JIN YOUNG, YANG, GI YOUNG, BAEK, SANG HOON, SONG, TAE JOONG
Принадлежит:

The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, the semiconductor device includes; a substrate including an active pattern; gate electrodes passing through the active pattern; impurity areas arranged in the active pattern between the gate electrodes; an active contact unit which is electrically connected to one or more of the impurity areas; a gate contact unit electrically connected to one or more of the gate electrodes; and a conductive structure electrically connected to one or more of the impurity areas and gate electrodes. The upper surfaces of the active contact unit, gate contact unit, and conductive structure coincide. The floor surface of a first part of the conductive structure is higher than the floor surfaces of the gate contact unit and the active contact unit. COPYRIGHT KIPO 2017 ...

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Номер записи: 19
29-03-2016 дата публикации

SEMICONDUCTOR DEVICE HAVING CROSS COUPLED CONSTRUCTURE AND LAYOUT VERIFICATION METHOD THEREOF

Номер: KR1020160034167A
Автор: SONG, TAE JOONG, DO, JUNG HO, HAN, CHANG HO
Принадлежит:

According to an embodiment of the present invention, a layout verification method of a semiconductor device having a cross coupled constructure comprises the following steps of: forming a plurality of standard cells having first and second type cross coupled constructures on a substrate of the semiconductor device; forming a plurality of first inverters in which the first type cross coupled constructure is activated in the plurality of standard cells and a plurality of second inverters in which the second type cross coupled constructure is activated in the plurality of standard cells; and estimating an electrical characteristic of the first type cross coupled constructure or the second type cross coupled constructure by measuring a magnitude of a signal delay of the plurality of first inverters or the plurality of second inverters. COPYRIGHT KIPO 2016 ...

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Номер записи: 20
21-03-2018 дата публикации

MEMORY DEVICE HAVING REDUNDANCY COLUMN AND REDUNDANCY PERIPHERAL LOGIC

Номер: KR1020180029832A
Автор: KIM, HOON KI, KIM, YONG HO, PARK, CHANG NAM, SONG, TAE JOONG, RIM, WOO JIN, JUNG, JONG HOON
Принадлежит:

A memory device is disclosed. According to an embodiment of the present disclosure, the memory device comprises: a memory cell array including a plurality of memory cells arranged in a plurality of columns including a normal column and a redundancy column for repairing the normal column; a plurality of peripheral logics including a normal peripheral logic and a redundancy peripheral logic for repairing the normal peripheral logic; and a first path selection logic forming first paths between the plurality of columns and the plurality of peripheral logics based on at least one defect from a defect of at least one column among the plurality of columns and a defect of at least one peripheral logic among the plurality of peripheral logics. COPYRIGHT KIPO 2018 ...

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Номер записи: 21
03-03-2016 дата публикации

METHOD OF DESIGNING LAYOUT OF INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT

Номер: KR1020160023542A
Автор: BAEK, SANG HOON, SONG, TAE JOONG, OH, SANG KYU, LEE, SEUNG YOUNG
Принадлежит:

A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced. COPYRIGHT KIPO 2016 (AA) Start (BB) End (CC) Yes (DD) No (S110) Providing a standard cell library (S130) Designing a first layout by disposing and wiring standard cells (S210) The number of masks >= / >= threshold value ? (S230) Generating a second layout by changing the first layout (S250) Forming an integrated circuit based on the second layout (S270) Forming an integrated circuit based on the first layout ...

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Номер записи: 22
17-10-2017 дата публикации

STANDARD CELL HAVING STRUCTURE FOR REMOVING ROUTING INTERFERENCE BETWEEN ADJACENT PINS AND DEVICE INCLUDING SAME

Номер: KR1020170115243A
Автор: SEO, JAE WOO, KIM, JIN TAE, SONG, TAE JOONG, OH, HYOUNG SUK, LEE, KEUN HO, LEE, DAL HEE, CHO, SUNG WE
Принадлежит:

An integrated circuit is disclosed. The integrated circuit includes a standard cell comprising only first unloaded transistors. The standard cell comprises a first metal, a second metal, and a third metal which are disposed in parallel in a first direction in a first layer; a fourth metal and a fifth metal which are separated from each other and are disposed in a second direction in a second layer; a first via connected between the first metal and the fourth metal; and a second via connected between the third metal and the fifth metal. The first via center-to-via center spacing between a first via and a second via is more than twice as large as the first minimum metal center-to-metal center pitch between the first metal and the second metal. The first minimum metal center-to-metal center pitch is equal to or less than 80 nanometers (nm). The first and second directions are perpendicular to each other. COPYRIGHT KIPO 2017 (AA) Y direction (BB) X direction ...

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Номер записи: 23
27-07-2015 дата публикации

SENSE AMPLIFIER AND MEMORY DEVICE INCLUDING SAME

Номер: KR1020150085903A
Автор: SONG, TAE JOONG, PARK, SUNG HYUN, RIM, WOO JIN, YANG, GI YOUNG
Принадлежит:

A sense amplifier includes: a switching NMOS transistor, a first sensing unit, a second sensing unit, and a latch unit. The switching NMOS transistor applies a ground voltage to a ground node in response to a sense enable signal. The first sensing unit is connected between the ground node and a first sensing node and provides a first sensing signal for the first sensing node based on a mode signal and a bit line voltage. The second sensing unit is connected between the ground node and a second sensing node and provides a second sensing signal for the second sensing node based on a complementary bit line voltage. The latch unit is connected between the power supply voltage, first sensing node, and second sensing node and outputs a first amplifying signal and a second amplifying signal respectively through a latch node and an inverted latch node signal based on the first and second sensing signals. COPYRIGHT KIPO 2015 ...

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Номер записи: 24
06-09-2016 дата публикации

SYSTEM-ON-CHIP AND LAYOUT DESIGN METHOD THEREOF

Номер: KR1020160105263A
Автор: BAEK, SANG HOON, DO, JUNG HO, SONG, TAE JOONG, YANG, GI YOUNG, LEE, SEUNG YOUNG, LIM, JIN YOUNG
Принадлежит:

The present invention relates to a system-on-chip and a layout design method thereof. More specifically, the system-on-chip comprises: a substrate which includes an active pattern thereon; a gate electrode which crosses the active pattern, and extends in a first direction parallel to the upper surface of the substrate; and a first metal layer which is electrically connected to the active pattern and the gate electrode. The metal layer includes a first metal wire which extends in the first direction, and a second metal wire which is separated from the first metal wire in the first direction, and extends in a second direction intersecting with the first direction, the first metal wire includes a first side wall in the second direction, the second metal wire includes a second side wall in the second direction, the first side wall and the second side wall are opposed, and the length of the first side wall is double or triple the minimum line width. COPYRIGHT KIPO 2016 ...

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Номер записи: 25
13-04-2018 дата публикации

INTEGRATED CIRCUIT INCLUDING MODIFIED CELL AND METHOD OF DESIGNING SAME

Номер: KR1020180037819A
Автор: KIM, JIN TAE, DO, JUNG HO, SONG, TAE JOONG, CHO, DOO HEE, LEE, SEUNG YOUNG
Принадлежит:

A method of designing an integrated circuit includes a step of receiving input data defining an integrated circuit, a step of providing a standard cell library including a plurality of standard cells, a step of providing a modified cell library including at least one modified cell having the same function as a corresponding standard cell among standard cells and having improved routing efficiency over the corresponding standard cell; and a step of performing placement and routing based on the input data, the standard cell library, and the modified cell library to generate output data defining the integrated circuit. The area of the integrated circuit can be reduced by using the modified cell having the routing efficiency higher than that of the standard cell. COPYRIGHT KIPO 2018 (AA) Start (BB) End (S100) Receiving input data defining an integrated circuit (S200) Providing a standard cell library including a plurality of standard cells (S300) Providing a modified cell library including ...

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Номер записи: 26
03-02-2016 дата публикации

METHOD OF DESIGNING LAYOUT OF INTEGRATED CIRCUIT AND COMPUTER SYSTEM PERFORMING SAME

Номер: KR1020160012864A
Автор: SONG, TAE JOONG, PARK, JAE HO, BAEK, SANG HOON, YANG, GI YOUNG, OH, SANG KYU, WON, HYO SIG
Принадлежит:

A method of designing the layout of a semiconductor integrated circuit includes a step of configuring a layout pattern for forming the semiconductor integrated circuit, a step of providing a biasing marker to the gate line of the layout pattern, a step of selecting at least one specific transistor among transistors included in the semiconductor integrated circuit, and a step of removing the biasing marker of the gate line of the selected transistor. COPYRIGHT KIPO 2016 ...

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Номер записи: 27
25-06-2018 дата публикации

INTEGRATED CIRCUIT INCLUDING VERTICAL TRANSISTOR AND SEMICONDUCTOR DEVICE INCLUDING SAME

Номер: KR1020180069465A
Автор: DO, JUNG HO, BAEK, SANG HOON, SONG, TAE JOONG, LEE, SEUNG YOUNG, JUNG, JONG HOON
Принадлежит:

An integrated circuit including a vertical transistor according to an exemplary embodiment of the present disclosure includes first to fourth gate lines which are extended in a first direction and are successively arranged in parallel to each other, a first upper active region which is arranged on the first to third gate lines, forms the first and third gate lines and first and third transistors, respectively, and is insulated from the second gate line, and a second upper active region which is arranged on the second to fourth gate lines, forms the second and fourth gate lines and second and fourth transistors, respectively, and is insulated from the third gate line. Accordingly, the present invention can reduce the area of the integrated circuit. COPYRIGHT KIPO 2018 ...

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Номер записи: 28
15-10-2018 дата публикации

INTEGRATED CIRCUIT INCLUDING INTERCONNECTION FOR MITIGATING ELECTROMIGRATION AND METHOD FOR FABRICATING SAME

Номер: KR1020180113137A
Автор: KIM, HA YOUNG, KIM, CHANG BEOM, ROH, HYUN JEONG, SONG, TAE JOONG, LEE, DAL HEE, CHO, SUNG WE
Принадлежит:

According to one aspect of a technical idea of the present invention, an integrated circuit capable of providing enhanced durability may comprise: a first conductive pattern formed at a first conductive layer; a second conductive pattern formatted at a second conductive layer on the first conductive layer; and a via which is electrically coupled to the first and second conductive patterns and in which a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern respectively pass through the via at different times. The via may be disposed on the first conductive pattern so that a path of the first current and a path of the second current do not overlap each other in the first conductive pattern. COPYRIGHT KIPO 2018 ...

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Номер записи: 29
08-03-2016 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME

Номер: KR1020160025436A
Автор: BAEK, SANG HOON, PARK, JAE HO, YANG, SEOL UN, SONG, TAE JOONG, OH, SANG KYU
Принадлежит:

The present invention relates to a method of fabricating a semiconductor device, comprising: providing a substrate including a first region, a second region, and a third region between the first and second regions; forming first and second preliminary active patterns protruding from the substrate on the first and second regions, respectively; forming mask patterns exposing the third region on the substrate; performing a first etching process using the mask patterns as an etch mask to form first and second active patterns from the first and second preliminary active patterns, respectively; and forming gate structures on the substrate. COPYRIGHT KIPO 2016 ...

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Номер записи: 30
28-02-2017 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: KR1020170021524A
Автор: JEONG, HAN WOOL, RIM, WOO JIN, SONG, TAE JOONG, JUNG, SEONG OOK, KIM, GYU HONG
Принадлежит:

A semiconductor memory device is provided. The semiconductor memory device includes a static random access memory (SRAM) cell, a sensing circuit connected to the SRAM cell through a first bit line and a second bit line different from the first bit line and sensing data stored in the SRAM cell, and a bit line voltage regulating circuit which is connected to the SRAM cell through the first and second bit lines and precharges the first bit line with a first voltage lower than a supply voltage, and precharges the second bit line with a different second voltage. So, read operation speed can be improved. COPYRIGHT KIPO 2017 ...

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Номер записи: 31
18-01-2017 дата публикации

집적 회로의 레이아웃 설계 방법 및 상기 집적 회로의 제조 방법

Номер: KR0101697343B1
Автор: 백상훈, 송태중, 오상규, 이승영
Принадлежит: 삼성전자주식회사

... 본 개시는 집적 회로의 레이아웃 설계 방법으로서, 집적 회로를 정의하는 복수의 표준 셀들을 배치 및 배선함으로써 제1 레이아웃을 설계하고, 제1 레이아웃에 대한 마스크 데이터 준비 과정에서, 제1 레이아웃을 변경함으로써 제2 레이아웃을 생성하며, 이때, 제1 레이아웃의 제1 레이어에 해당하는 제1 레이어 패턴들의 형성에 필요한 마스크들의 개수가 감소되도록 제1 레이어 패턴들 중 제1 및 제2 패턴들을 서로 연결함으로써 제2 레이아웃을 생성한다.

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Номер записи: 32
03-03-2016 дата публикации

STANDARD CELL LIBRARY AND METHOD FOR USING SAME

Номер: KR1020160023521A
Автор: BAEK, SANG HOON, SONG, TAE JOONG, PARK, JAE HO, YANG, GI YOUNG, KIM, JIN TAE, WON, HYO SIG
Принадлежит:

The present invention discloses a standard cell library and a method of using a standard cell library. According to one embodiment of the present invention, the standard cell library may include information regarding a plurality of standard cells. The standard cell library may include a pin through which an input signal or an output signal of at least one standard cell passes and including first and second regions. When a via is disposed in the pin later on, the second region can provide a resistance value of the via smaller than that of the first region. The standard cell library may include marker information corresponding to the second region. COPYRIGHT KIPO 2016 ...

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Номер записи: 33
26-06-2018 дата публикации

INTEGRATED CIRCUIT FOR MULTIPLE PATTERNING LITHOGRAPHY, COMPUTING SYSTEM AND COMPUTER IMPLEMENTING METHOD FOR DESIGNING INTEGRATED CIRCUIT

Номер: KR1020180070322A
Автор: DO, JUNG HO, JUNG, JONG HOON, LEE, SEUNG YOUNG, SONG, TAE JOONG
Принадлежит:

The present invention provides an integrated circuit capable of increasing a routing track resource in the integrated circuit to which multiple patterning lithography (MPL) is applied, a computer implementing method and a computing system for designing an integrated circuit. According to an embodiment of the present invention, the integrated circuit comprises: a lower layer including first and second lower patterns extending in a first direction; first and second vias located on the first and second lower patterns, respectively; and an upper layer which is individually located on the first and second vias, in which first and second colors are individually assigned, and which includes first and second upper patterns adjacent to each other along a second direction perpendicular to the first direction. A width of the first lower pattern is larger than a width of the first via, and the first via is located in an edge region of the first lower pattern which is far from the second lower pattern ...

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Номер записи: 34
22-02-2016 дата публикации

MEMORY DEVICE INCLUDING REFERENCE VOLTAGE GENERATOR

Номер: KR1020160019595A
Автор: RIM, WOO JIN, SONG, TAE JOONG, KIM, GYU HONG, PARK, JONG SUN, CHOI, WOONG
Принадлежит:

According to the present invention, a static random access memory device comprises: a first memory cell array including memory cells of a single bit line structure; a second memory cell array including memory cells of a single bit line structure; a reference voltage generation unit which outputs a bit line voltage of one of the first and the second memory cell arrays selected according to an array selection signal as a sensing voltage, and outputs a bit line voltage of an unselected memory cell array as a reference voltage; and a differential sense amplifier which amplifies and outputs a difference between the sensing voltage and the reference voltage. Logic states of the sensing voltage and the reference voltage are complementary to each other. COPYRIGHT KIPO 2016 ...

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Номер записи: 35
10-10-2017 дата публикации

INTEGRATED CIRCUIT AND METHOD FOR DESIGNING INTEGRATED CIRCUIT

Номер: KR1020170109863A
Автор: KIM, HA YOUNG, SONG, TAE JOONG, CHO, SUNG WE
Принадлежит:

A computer implemented method for designing an integrated circuit according to the present disclosure includes allocating a plurality of colors to patterns to apply an MPT to patterns corresponding to one layer of a first cell that is a multi-height cell corresponding to a plurality of rows; generating, for the first cell, a plurality of shift cells in which color remapping is performed on the patterns for each row; and storing a set of cells including the first cell and a plurality of shift cells in a standard cell library. It is possible to improve the efficiency of color remapping operation for the cells. COPYRIGHT KIPO 2017 (AA) Start (BB) End (S210) Allocating a plurality of colors to patterns corresponding to the same layer of a first cell (S220) Generating, for the first cell, shift cells in which color remapping is performed on the patterns for each row (S230) Storing a set of cells including the first and shift cells in a standard cell library ...

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Номер записи: 36
30-05-2017 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: KR1020170059364A
Автор: DO, JUNG HO, JUNG, JONG HOON, BAEK, SANG HOON, LEE, SEUNG YOUNG, SONG, TAE JOONG, LIM, JIN YOUNG, YANG, GI YONG
Принадлежит:

The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, the semiconductor device includes; a substrate including an active pattern; gate electrodes passing through the active pattern; impurity areas arranged in the active pattern between the gate electrodes; an active contact unit, which is electrically connected to one or more of the impurity areas; a gate contact unit electrically connected to one or more of the gate electrodes; and a conductive structure electrically connected to one or more of the impurity areas and gate electrodes. The upper surfaces of the active contact unit, gate contact unit, and conductive structure coincide. The floor surface of a first part of the conductive structure is higher than the floor surfaces of the gate contact unit and the active contact unit. COPYRIGHT KIPO 2017 ...

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Номер записи: 37
16-05-2016 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT AND FABRICATING METHOD THEREOF

Номер: KR1020160054379A
Автор: SONG, TAE JOONG, KIM, JUNG HAN
Принадлежит:

The present invention is to provide a semiconductor integrated circuit including a clock latch circuit realized in a small area. The semiconductor integrated circuit includes: first and second active areas; first to fourth gate structures; and first to fourth contacts. The first and second active areas are defined by a device isolation layer formed on a substrate, are individually extended in a first direction, are separated from each other in a second direction substantially perpendicular to the first direction, and are doped with different conductive impurities. The first and third gate structures are separated from each other in the first direction, are individually extended in the second direction, and are formed on the first active area and on a first section of the device isolation layer between the first and second active areas, respectively. The second and fourth gate structures are separated from each other in the first direction, are individually extended in the second direction ...

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Номер записи: 38
25-01-2018 дата публикации

FLIP-FLOP INCLUDING THREE-PHASE INVERTER

Номер: KR1020180009036A
Автор: KIM, HA YOUNG, LEE, DAL HEE, OH, HYOUNG SUK, LEE, KEUN HO, SONG, TAE JOONG, CHO, SUNG WE
Принадлежит:

The present invention relates to a flip-flop which prevents degradation in characteristics and yield reduction. According to the present invention, the flip-flop comprises: an input unit to receive a signal, and synchronize the received signal with a clock to output the signal; a first latch including a first and a second inverter, and synchronizing the signal outputted from the input unit with the clock to store the signal; a third inverter to synchronize a signal stored in a master latch with the clock to output the signal; and a second latch including a fourth and a fifth inverter, and synchronizing the signal outputted from the third inverter with the clock to store the signal. The third inverter and the fifth inverter include: first-type first transistors formed between a first power contact and a second power contact to which a power voltage is supplied, on first-type fins; and second-type second transistors formed between a first ground contact and a second ground contact to which ...

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Номер записи: 39
21-02-2019 дата публикации

불휘발성 메모리 장치 및 불휘발성 메모리 장치의 동작 방법

Номер: KR1020190018116A
Автор: 표석수, 정현택, 송태중
Принадлежит:

... 본 발명의 실시 예에 따른 불휘발성 메모리 장치는, 메모리 셀들 및 더미 셀들을 포함하는 메모리 셀 어레이, 워드 라인들을 통해 메모리 셀들에 연결되는 행 디코더, 더미 워드 라인들을 통해 더미 셀들에 연결되는 더미 워드 라인 바이어스 회로, 비트 라인들을 통해 메모리 셀들에 연결되는 쓰기 드라이버 및 감지 증폭기 회로, 그리고 더미 비트 라인을 통해 더미 셀들에 연결되는 더미 비트 라인 바이어스 회로를 포함한다.

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Номер записи: 40
24-12-2018 дата публикации

INTEGRATED CIRCUIT INCLUDING STANDARD CELLS OVERLAPPING EACH OTHER AND METHOD FOR GENERATING LAYOUT THEREOF

Номер: KR1020180136355A
Автор: DO, JUNG HO, JUNG, JONG HOON, YU, JI SU, LEE, SEUNG YOUNG, SONG, TAE JOONG, LEE, JAE BOONG
Принадлежит:

According to an exemplary embodiment of the present disclosure, in an integrated circuit including a plurality of standard cells, each of the standard cells may include a front end of line (FEOL) region including at least one gate line extending in a horizontal direction and a back end of line (BEOL) region of the FEOL region. The BEOL region of a first standard cell as one of the standard cells may not include an eaves portion not overlapping with the FEOL region of the first standard cell in a vertical direction and protruded in a second horizontal direction perpendicular to the first horizontal direction. COPYRIGHT KIPO 2019 ...

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Номер записи: 41
17-08-2018 дата публикации

INTEGRATED CIRCUIT HAVING CONTACT JUMPER

Номер: KR1020180092253A
Автор: DO, JUNG HO, SONG, TAE JOONG, LEE, SEUNG YOUNG, JUNG, JONG HOON
Принадлежит:

According to a technical idea of the present disclosure, an integrated circuit, which includes an ultra-high density standard cell with a reduced height, comprises first and second active regions extending in a first direction; a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions; and a first contact jumper including a first conductive pattern crossing the first gate line at the top of the first active region and a second conductive pattern extending in the second direction at the top of the first gate line and connected to the first conductive pattern. COPYRIGHT KIPO 2018 ...

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Номер записи: 42
16-08-2018 дата публикации

INTEGRATED CIRCUIT INCLUDING STANDARD CELL

Номер: KR1020180091687A
Автор: KIM, IN GYUM, KIM, HA YOUNG, SONG, TAE JOONG, JUNG, JONG HOON, YANG, GI YOUNG, LIM, JIN YOUNG
Принадлежит:

An integrated circuit with improved performance includes a plurality of standard cells according to an exemplary embodiment of the present disclosure. At least one standard cell among a plurality of standard cells comprises a power rail supplying power to at least one standard cell and extending in a first direction; a cell region including at least one transistor for determining a function of at least one standard cell; first and second dummy regions respectively adjacent to both sides of the cell region in the first direction; and an active region extending in the first direction crossing the cell region, the first dummy region, and the second dummy region. A region included in the first dummy region or the second dummy region of the active region may be electrically connected to the power rail. COPYRIGHT KIPO 2018 ...

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Номер записи: 43
04-03-2016 дата публикации

SEMICONDUCTOR DEVICES AND METHOD FOR FORMING SAME

Номер: KR1020160024341A
Автор: DO, JUNG HO, BAEK, SANG HOON, PARK, SUN YOUNG, BAE, MOO GYU, SONG, TAE JOONG
Принадлежит:

According to the present invention, a semiconductor device comprises: first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a third gate structure extending in the first direction and provided between the first and second gate structures; a first contact connected to the first gate structure and having a first width in the second direction; a second contact connected to the second gate structure and having a second width in the second direction; and a third contact connected to the third gate structure and having a third width in the second direction. The first, second, and third contacts can be aligned with each other in the second direction to constitute one row. The first and second widths can be greater than the third width. COPYRIGHT KIPO 2016 ...

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Номер записи: 44