METHOD OF DESIGNING LAYOUT OF INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT

Hereinafter, based on a text content of the drawing reference to. as further described focuses of the present invention embodiment. Where a new file does not exist per relate of the present invention embodiment of the chair are a mean water level in user with the present invention to illustrate the an entire surface is to be provided for. Modification of the present invention refers to various variety of forms that can apply may have a low bar, specific in the embodiment are rapidly and to reduce a memory and illustrated drawing.. However, the present invention with a particular disclosure of the physical shape not defined to be, included within the scope of the present invention all changing a concept and techniques, including replacement water and equalization should understood. Each drawing while describes similar references in a similar. to use components. In drawing with an, the dimensions of the structures a elcellent distinctions of the present invention are provided to magnify or reduce the than measured by the. the.

The present application only a term use in a particular embodiment used to describe the thereby, the cold air flows are added, is not intending to be defining the present invention. Contextually representation a plurality of differently it is apparent that without the carelessly, includes multiple representations. In the present application, "comprising" or "having." a set of terms, such as a specification to the features, number, step, operation, components, discrete parts or a combination of these is designates the feature to which is present does, number to execute another aspect of one or more, step, operation, components, or a combination of these discrete parts existence of a without excluding the possibility or additionally pre should understood.

Furthermore, number 1, a set of terms, such as number 2 describes various elements which may be used; however, said components are said terms is don't is defined by. Components of one said terms are distinguished from other components can be used with the object. For example, without range rights of the present invention, number 1 number 2 component can be designated components, similarly number 2 number 1 component elements can be designated.

Other is not defined, technical or scientific for a term including to the all terms are person with skill in the art in the present invention is in the field of the upwardly urged by equivalent to those that would have been understood photopolymerization initiator represented by chemical. Generally are defined as the dictionary used for, such as terms are contextually purpose: coincide semantics and having having the meanings must be interpreted to, the present application, become manifest in a do not define, excessively or is ideal for the widest sense of the formal does not interpreted.

Integrated circuit a plurality of cells can be defined as, specifically, of a plurality of cells and the attribute information includes a including cell libraries were utilized to can be designed. Wherein, scramble the cell name, dimension, gate width, pin (pin), delay (delay) characteristics, leakage current, threshold voltage, .can be defined, and a function. General scramble set (set) the AND, OR, NOR, (basic cell) basic cell such as switching portion, such as AOI (AND/OR/INVERTER) and OAI (OR/AND/INVERTER) composite cell (complex cell), and a simple master-slave flip flop (master-slaver flip-flop) and latch (latch) such as storage element may comprise an (storage element).

A refers to in in of the present invention in the embodiment hereinafter, scramble a standard scramble can be. The standard cell system, block logic circuit having various functions (or cell) and preparing a, a latch is connected between relates to the specification of user or the customer to input the in any combination according to, comprising a dedicated large-scale integrated circuit (LSI) .for designing. Verification is design and predetermined cell is registered with computer taken, with computer-aided design (Computer Aided Design, CAD) design using logic the maintain cell, disposed, wiring is given.

Specifically, when/manufacturing large scale for designing IC, which scale standardized logic circuit blocks, (or cell) is already library stored and if, the current design logic circuit on the retrieved from the block, same plurality of on the chip and as cell column, wiring between the cell cell the wiring length is shortest a space an optimum value which made the whole circuit without interconnection is formed in the. positioned in. The library though the rich types of cell design flexibility in them and, herein, the gears of the 2000 or the availability of optimum-designed chip.

Configuration information on file base to implement standard and an integrated circuit having as Microfuse integrated of the inventive circuit assembly, is designed pre to stored standard library standard cell and cell between them to minimize wiring is implemented by placing the cells. Therefore, compared to specific integrated circuit complete and supports file can be window in the.

Also according to one embodiment of the present invention Figure 1 shows a manufacturing method of IC is the flow indicating.

With a 1 also, the present embodiment according to design of the integrated circuit manufacturing method of IC (S100) and with integrated circuit fabrication processes. may be divided into (S200). (S100) has design of integrated circuit includes steps S130 and S110, integrated circuit is superposed on the layout designing wherein a tool for for designing IC, be in. The, a tool for for designing IC, performed in a processor plurality of instructions one at including can be program. While, with integrated circuit fabrication processes (S200) includes step S210 to S270, based on layout designed as a step in the production of integrated circuits, semiconductor process be module. In hereinafter, design of integrated circuit with integrated circuit fabrication processes and (S100) (S200) included in each step a to is disclosed.

In step S110, provides standard cell library. Wherein, a library of standard cell a plurality of standard cell excluding information may include, computer-readable storage medium may be stored in. A library of standard cell a standard controlled oscillator automatically information and timing information may include a. Standard cell content the second time control 2 also in the hereinafter by referring to more rapidly and to reduce a memory to a.

In step S130, a library of standard cell using standard cell and wiring (place and routing, & R P) by. is designed so that the layout number 1. Standard cell and wiring by a design layout number 1 in the embodiment for hereinafter by referring to 7d also to 7a also in more rapidly and to reduce a memory to a.

Specifically, first, an input data defining integrated circuit: this recorder receives. Wherein, operation of the integrated circuit input data (behavior) to abstraction form, e.g. RTL (Register Transfer Level) defined in standard cell from the data (synthesis) synthetic libraries were utilized to generated by data can be. For example, input data such as VHDL (VHSIC Hardware Description Language) and is defined as Verilog HDL (Hardware Description Language) integrated circuit is synthesized by the produced bit-stream (bitstream) or netlist (netlist) can be.

Furthermore, a library of standard cell to access and a storage medium storing for the, standard cell library stored plurality of standard cells selected according to input data and wiring a standard cell. Wherein, selected acids to epoxygenated fatty acids therein and wiring disposed standard cell the, connected to standard cell disposed circulation promoted. the task of. By is completed and wiring disposed, original or layout (initial) initial integrated circuit layout can be created which (original), same in hereinafter, referred to a layout number 1.

Integrated circuit design of the aforementioned steps S110 and S130 (S100) may include a. However, the present invention refers to and not limited to, generation of a library of standard cell, standard cell parameter, layout verification, such as simulation post integrated circuit generally design of various method according to may further include any steps.

In step S210, layout of number 1 number 1 layer in a pattern corresponding to the mask pattern as a mask to formation of a number of. to determine whether to critical value. Specifically, step S210 the number 1 (mask data preparation) preparing mask data layout be during the course of. Wherein, mask data preparing process of the integrated circuit design process (S100) designated in a number 1 layout collecting data overall the OPC (Optical Proximity Correction). having a selected preparing performance. Judgment result, number 1 layer in a pattern corresponding to the mask pattern as a mask to formation of a if the flow is greater than the threshold value disposed at the base of the housing performs step S230, otherwise step performs S270.

In step S230, by changing the layout number 1 number 2 generates layout. Specifically, step S210 with step S230, number 1 during the course of preparing mask data layout be. As such, in preparing mask data by changing the layout number 1 number 2 layout polishing data metric generator can be, referred (data polishing). Data polishing hereinafter a case that many destination 13 also to 8 also in reference to more rapidly and to reduce a memory to a.

In step S250, based on layout number 2 to form a integrated circuit. Specifically, first, the OPC based on layout number 2 number 2. to the change of coupling. Wherein, the OPC according to the error optical proximity effect travel motor is operated according to the layout number 2 circulation promoted. process. If layout number 2 for preparing and mask by using a speed of n times, produced by use of the mask in the of a photolithography processes, other forms of by optical proximity effect on the may be. Therefore, the error according to optical proximity effect, by changing a layout number 2, number 2 modified based on the layout mask printed onto the product, thus resulting photolithography by conducting the process, such as layout number 2 can be layer is wet-etched to form.

Furthermore, OPC result changed according to and to fabricate a mask according to a layout number 2, manufacturing a semiconductor layer to form a by an electrochemical reaction. The, OPC layout reflect data distributed, e.g., OPC reflected graphic design system (Graphic Design System: GDS) using a mask for making and, produced by use of the mask in the photolithography process for fabricating integrated circuit on the wafer using a can be.

In step S270, based on layout number 1 to form a integrated circuit. Step S270 step S250 that are substantially similar to a subsequent heat treatment is performed after. I.e., based on layout number 1 the OPC by changing a layout number 1, OPC result changed according to and to fabricate a mask according to a layout number 1, manufacturing a semiconductor layer to form a by an electrochemical reaction.

Figure 2 standard cell one example is a layout representing (SC).

Also refers to surface 2, standard cell (SC) a cell boundary (cell boundary, C_BD) is delimited by, plurality of fins (FIN), number 1 and number 2 active (active) regions (AR1, AR2), plurality of conductive lines (conductive lines) (CL) and a plurality of number 1 contacts (contacts) (CA) may include a. (C_BD) Internet dialpad the standard cell (SC) (outline) in defining a out lines, Internet dialpad tool and wiring disposed (C_BD) (SC) standard cell using. to be made aware of. Internet dialpad four (C_BD) for cell boundary lines consists of to (cell boundary lines).

The plurality of fins (FIN) number 1 direction (for example, X direction) extends, number 1 number 2 direction, are perpendicular to the direction (for example, Y direction) along the can be disposed parallel to each other. Number 1 and number 2 active region (AR1) active region (AR2) they are parallel to each other which is aligned on the reticle stage, a photoresist pattern can take the. In the present in the embodiment, number 1 and number 2 active regions (AR1, AR2) each integrator prevents a saturation using an integrator pins 3 (FIN) .can be arranged. However, the present invention refers to and not limited to, number 1 and number 2 active regions (AR1, AR2) is disposed in each (FIN) various the number of pins can be easily changed.

The, number 1 and number 2 active regions (AR1, AR2) a plurality of fins (FIN) can be an active pin admit, referring to. An active pin but occur shown in Figure 2, which the present invention refers to not limited to, standard cell (SC) a cell boundary (C_BD) and a (AR1) active region number 1, number 1 and number 2 active regions (AR1, AR2) a region between, or number 2 active region (AR2) Internet dialpad and a dummy arranged in the region of between (C_BD) (dummy) may further include any pins.

The plurality of conductive lines (CL) number 2 direction (for example, Y direction) can be extending, number 1 direction (for example, X direction) along the can be disposed parallel to each other. The, conductive lines any material having an electrically conductive (CL) may be formed into, for example, polysilicon, metal, such as the blackening layer may include a metal.

In one in the embodiment, conductive lines (CL) have gate electrodes can be corresponding to. However, the present invention refers to which not limited to, conductive lines (CL) having a conductivity of any combination of the conductor trace (trace).. Furthermore, the standard cell (SC) in Figure 2 three of conductive lines are shown but including a (CL), man is only the aspect the one embodiment, standard cell (SC) running in the direction the number 2 number 1 direction a and arrayed in parallel to each other wherein at least two conductor lines 4 may include a.

Plurality of number 1 the number 1 and number 2 active regions (CA) contacts (AR1, AR2) on which can be arranged on the, number 1 and number 2 active regions (AR1, AR2) electrically may be connected to. In one in the embodiment, the source/drain (source/drain) plurality of number 1 contacts (CA) can [...], in other in the embodiment, plurality of number 1 contacts (CA) may [...] the power (power). Although not shown, standard cell (SC) a plurality of conductive lines is arranged on (CL), plurality of conductive lines (CL) that are electrically coupled to the at may further include any contact number 2.

Figure 3 shows a layout semiconductor device having is one example of representing a perspective view of Figure 2. Figure 4 shows a III-III ' line is according to cross-sectional drawing of Figure 2.

Also 3 and 4 refers to surface, semiconductor device (100a) the bulk (bulk type) can be height and the width of the fin. Semiconductor device (100a) the substrate (SUB), (IL1) insulating layer number 1, number 2 (IL2) insulating layer, number 1 to number 3 pins (FIN) and conductive lines (hereinafter 'gate electrode', referred the) may include a (CL).

Substrate which may be the substrate a semiconductor (SUB), for example, semiconductor substrate is silicon, silicon-on-insulator, silicon-on-sapphire, germanium, silicon-germanium and a gallium arsenic either may comprise an. Wherein, the P type substrate (SUB) may be the substrate and, number 1 ID:2, seq ID : (AR1) active region.

Number 1 to number 3 (SUB) a substrate (FIN) pins can easily be arranged connected to. In one in the embodiment, number 1 to number 3 (SUB) in a substrate (FIN) pins are substituted for the vertical sections with a p or n can be active region.

Number 1 and number 2 insulating layers (IL1, IL2) of an insulating material which may include, for example, insulator material has oxide film, a nitride layer or a oxynitride may comprise an either. Number 1 (IL1) insulating layer the number 1 to number 3 pins can be disposed on (FIN). Number 1 (IL1) insulating layer the number 1 to number 3 pins (FIN) by (CL) and a gate electrode is arranged between, can be used by gate insulating layer. Number 2 (IL2) insulating layer the number 1 to number 3 (FIN) pins made of the same material with the predetermined spaces between the can be arranged to. Number 2 (IL2) insulating layer the number 1 to number 3 by is arranged between (FIN) pins, can be used by isolation layer.

The number 1 and number 2 insulating layers (CL) gate electrode (IL1, IL2) can be placed on top of. Thereby, gate electrode (CL) (FIN) pins the number 1 to number 3, and number 2 (IL2) number 1 (IL1) insulating layer surrounding the insulating layer material may have a structure. In other words, , number 1 to number 3 pins (FIN) a (CL) the gate electrode material may have a structure. Gate electrode (CL) the W, Ta, such a metal material, their nitride, their silicide, such as doped polysilicon can include a, process using can be formed.

Figure 5 shows a layout in another example of a semiconductor device having is representing a perspective view of Figure 2. Figure 6 shows a V-V ' line is according to cross-sectional drawing of Figure 2.

Also 5 and 6 with a, semiconductor device (100b) the SOI fin-type transistor can be. Semiconductor device (100b) the substrate (SUB '), insulating layer (IL1') number 1, number 2 insulating layer (IL2 '), number 1 to number 3 pins (FIN') and conductive lines (hereinafter in 'gate electrode' the referred to as the) (CL ') may include a. The present embodiment: a semiconductor device (100b) has door 3 and 4 shown in semiconductor device (100a) deformation of since in the embodiment, in hereinafter, semiconductor device (100a) which is disposed in about difference with, redundant portion a description dispensed to a.

Number 1 insulating layer (IL1 ') a substrate (SUB') can be disposed on. Number 2 insulating layer (IL2 ') the number 1 to number 3 pins (FIN') and a gate electrode by is arranged between (CL '), can be used by gate insulating layer. Number 1 to number 3 pins (FIN ') a semiconductor material, for example, can be silicon or doped silicon.

Gate electrode (CL ') the number 2 insulating layer (IL2') can be placed on top of. Thereby, gate electrode (CL ') the number 1 to number 2 and number 3 pins (FIN') surrounding the insulating layer (IL2 ') material may have a structure. In other words, , number 1 and number 2 pins (FIN ') the gate electrode (CL') a structure material may have a.

The 7d also to 7a also printed anode placed adjacent to the two standard cells integrated part of a circuit including exemplary number 1 layouts (10a to 10d) is.

The 7d also to 7a also step S130 exemplary in the embodiment as of Figure 1, number 2 and number 1 by means of a tool and wiring disposed standard cells (SC1, SC2) is number 2 direction (for example, Y direction) lie adjacent to each other along a can easily be arranged. Specifically, disposed and wiring using tools, selected number 1 and number 2 standard cells (SC1, SC2) to position the, then, number 1 and number 2 disposed interconnecting standard cells (SC1, SC2) also to 7a also by number 1 layouts shown in 7d (10a to 10d) can be the design. Also to 7a also for the sake of convenience number 1 layouts of 7d (10a to 10d) the pins of Figure 2 is shown that (FIN) did not.

Also refers to surface 7a, number 1 layout (10a) the number 2 direction situated adjacently to each other (SC1) standard cell number 1 and number 2 standard cell may include a (SC2). In the present in the embodiment, (SC1) standard cell number 1 number 1 of the number 1 and number 2 power contact patterns contact (CA) (CA_P1, CA_P2) can include a, standard cell (SC2) of number 1 number 2 number 1 and number 2 power contact patterns also contact (CA) (CA_P1, CA_P2) may include a.

Number 2 and number 1 by means of a tool and wiring disposed standard cells (SC1, SC2) number 1 a in each power contact patterns can be (CA_P1) are connected to each other, similarly, number 1 and number 2 standard cells (SC1, SC2) number 2 a in each power contact patterns may be connected to one (CA_P2). Therefore, layout number 1 (10a) one number 1 power resultant structure (CA_P1) and one number 2 power resultant structure may include a (CA_P2).

Number 1 layout (10a) one number 1 power resultant structure (CA_P1) and one number 2 power resultant structure the (CA_P2) can construct (CA) contact number 1. In consequence of its miniaturization of semiconductor process number 1 and number 2 power contact patterns (D0) has distance between (CA_P1, CA_P2) may be the pattern of the material layer resolution limit (patterning resolution limit) hereinafter, the, number 1 and number 2 power contact patterns (CA_P1, CA_P2) can be formed into a single mask, with the't. Therefore, number 1 and number 2 power contact patterns (CA) (CA_P1, CA_P2) for forming a contact including number 1 of double. are required to masks.

Also refers to surface 7b, number 1 layout (10b) the number 2 direction situated adjacently to each other (SC1) standard cell number 1 and number 2 standard cell may include a (SC2). In the present in the embodiment, (SC1) standard cell number 1 number 1 of the number 1 number 1 (CA_P1) and contact (CA) power resultant structure source/drain resultant structure can include a (CA_SD1), established standard cell number 2 number 1 (SC2) of number 1 and number 2 power contact patterns (CA_P1, CA_P2) may include a.

Number 2 and number 1 by means of a tool and wiring disposed standard cells (SC1, SC2) number 1 a in each power contact patterns (CA_P1) may be connected to each other. However, standard cell number 1 (SC1) included in source/drain number 1 (CA_SD1) resultant structure (SC2) standard cell number 2 and number 2 power resultant structure included in different (CA_P2) the multiplexer provides a path for applying the voltage are connected to each other and cannot. Therefore, layout number 1 (10b) (CA_P1) one number 1 power resultant structure, (CA_SD1) resultant structure source/drain number 1 and number 2 power resultant structure may include a (CA_P2).

Number 1 layout (10b) (CA_P1) one number 1 power resultant structure, source/drain number 1 and number 2 power resultant structure the resultant structure (CA_P2) (CA_SD1) can construct (CA) contact number 1. In consequence of its miniaturization of semiconductor process number 1 and number 2 power contact patterns (D0) (CA_P1, CA_P2) distance between the patterning resolution limit can be hereinafter, the, number 1 and number 2 power contact patterns (CA_P1, CA_P2) can be formed into a single mask, with the't.

Furthermore, resultant structure source/drain number 1 number 2 power resultant structure distance between (CA_P2) (CA_SD1) and (D1) has the pattern of the material layer resolution limit can be hereinafter, the, resultant structure source/drain number 1 number 2 power resultant structure (CA_SD1) and can be formed into a single mask, with the (CA_P2)'t. Therefore, (CA_P1) resultant structure power number 1, number 2 and number 1 (CA_SD1) source/drain resultant structure including number 1 contact (CA) is formed (CA_P2) for power resultant structure in order. are required to masks cell.

Also refers to surface 7c, number 1 layout (10c) the number 2 direction situated adjacently to each other (SC1) standard cell number 1 and number 2 standard cell may include a (SC2). The present in the embodiment in, standard cell number 1 (SC1) of the number 1 and number 2 number 1 contact (CA) source/drain contact patterns (CA_SD1, CA_SD2) can include a, standard cell number 2 number 3 and number 4 (CA) contact number 1 (SC2) of the source/drain contact patterns (CA_SD3, CA_SD4) may include a.

Number 1 standard cell number 1 and number 2 (SC1) included in source/drain contact patterns (CA_SD1, CA_SD2) (SC2) standard cell number 2 and number 3 and number 4 included in source/drain contact patterns (CA_SD3, CA_SD4) to which a voltage can be applied different and cannot are connected to each other since. Therefore, layout number 1 (10c) the number 1 to number 4 source/drain contact patterns (CA_SD4 to CA_SD1) may comprise an.

Number 1 layout (10c) in source/drain contact patterns number 1 to number 4 (CA_SD4 to CA_SD1) the number 1 contact (CA) can construct. In consequence of its miniaturization of semiconductor process number 1 and number 2 source/drain contact patterns (D0) (CA_SD1, CA_SD2) distance between the patterning resolution limit can be hereinafter, the, source/drain contact patterns number 1 and number 2 (CA_SD1, CA_SD2) can be formed into a single mask, with the't. Similarly, source/drain contact patterns number 3 and number 4 (CA_SD3, CA_SD4) (D0) has distance between the pattern of the material layer resolution limit can be hereinafter, the, number 3 and number 4 source/drain contact patterns (CA_SD3, CA_SD4) can be formed into a single mask, with the't.

Furthermore, source/drain number 1 and number 4 (CA_SD1) resultant structure (CA_SD4) distance between source/drain resultant structure (D2) has the pattern of the material layer resolution limit can be hereinafter, the, resultant structure source/drain number 1 and number 4 (CA_SD1) source/drain resultant structure can be formed into a single mask, with the (CA_SD4)'t. While, (CA_SD1) resultant structure source/drain number 1 and number 3 (CA_SD3) distance between source/drain resultant structure (D3) has the pattern of the material layer resolution limit least, the, resultant structure source/drain number 1 and number 3 (CA_SD1) (CA_SD3) a single mask, with the source/drain resultant structure can be formed into. Therefore, source/drain contact patterns number 1 to number 4 (CA_SD4 to CA_SD1) of forming a contact including number 1 of order. are required to masks cell.

Also refers to surface 7d, number 1 layout (10d) the number 2 direction situated adjacently to each other (SC1) standard cell number 1 and number 2 standard cell may include a (SC2). The present in the embodiment in, standard cell number 1 (SC1) of the number 1 and number 2 number 1 contact (CA) source/drain contact patterns (CA_SD1, CA_SD2) can include a, standard cell number 2 number 1 (SC2) of the number 1 and number 2 power contact patterns contact (CA) (CA_P1, CA_P2) may include a.

Number 1 standard cell number 1 and number 2 (SC1) included in source/drain contact patterns (CA_SD1, CA_SD2) (SC2) standard cell number 2 and number 3 and number 4 included in source/drain contact patterns (CA_SD3, CA_SD4) to which a voltage can be applied different and cannot are connected to each other since. Therefore, layout number 1 (10d) source/drain contact patterns the number 1 and number 2 (CA_SD1, CA_SD2) and number 1 and number 2 power contact patterns (CA_P1, CA_P2) may include a.

Number 1 layout (10d) in source/drain contact patterns number 1 and number 2 (CA_SD1, CA_SD2) and number 1 and number 2 power contact patterns the number 1 (CA_P1, CA_P2) contact (CA) can construct. In consequence of its miniaturization of semiconductor process number 1 and number 2 source/drain contact patterns (D0) (CA_SD1, CA_SD2) distance between the patterning resolution limit can be hereinafter, the, source/drain contact patterns number 1 and number 2 (CA_SD1, CA_SD2) can be formed into a single mask, with the't. Similarly, power contact patterns number 1 and number 1 (CA_P1, CA_P2) (D0) has distance between the pattern of the material layer resolution limit can be hereinafter, the, number 1 and number 2 power contact patterns (CA_P1, CA_P2) can be formed into a single mask, with the't.

Furthermore, resultant structure source/drain number 1 number 2 power resultant structure distance between (CA_P2) (CA_SD1) and (D1) has the pattern of the material layer resolution limit can be hereinafter, the, resultant structure source/drain number 1 number 2 power resultant structure (CA_SD1) and can be formed into a single mask, with the (CA_P2)'t. Furthermore, resultant structure source/drain number 1 number 1 power resultant structure (CA_SD1) and distance between (CA_P1) (D4) has the pattern of the material layer resolution limit can be hereinafter, the, resultant structure source/drain number 1 number 1 (CA_SD1) and power resultant structure can be formed into a single mask, with the (CA_P1)'t. Therefore, source/drain contact patterns number 1 and number 2 (CA_SD1, CA_SD2) and number 1 and number 2 power contact patterns including number 1 (CA_P1, CA_P2) contact (CA) is formed in order for you. are required to masks.

As described above, also 7a of layout number 1 (10a) of the number 1 contact patterns 2 (CA_P1, CA_P2) installed by using, two mask. in need. Also 7b of layout number 1 (10b) of the number 1 contact patterns 3 (CA_P1, CA_P2, CA_SD1) installed by using, three mask. in need. Also 7c of layout number 1 (10c) of the 4 number 1 contact patterns, which include but (CA_SD2 to CA_SD1), resultant structure source/drain number 1 and number 3 source/drain resultant structure (CA_SD1) (CA_SD3) distance between a patterned (D3) is over resolution limits, three mask. in need. However, also number 1 layout of 7d (10d) of the number 1 contact patterns 4 (CA_P1, CA_P2, CA_SD1, CA_SD2) includes, the distance between each resultant structure since the patterning resolution limits hereinafter, four mask. in need.

Number 1 a mask for forming a contact (CA) of time increases with an increasing number of the integrated circuit, in accordance with of a production cost thereof is are. However, integrated circuit a design step of, specifically, a library of standard cell steps requiring adjacent (of Figure 1 S110) in standard easily be arranged. unpredictable cell. Therefore, mask number reflect each standard controlled oscillator automatically for designing. it is not possible.

Also by referring to also to 7a 7d as described above, an integrated circuit designed in included in one layer, for example, contact number 1 a plurality respect to a predetermined reference axis (CA), for example, number 1 and number 2 power contact patterns (CA_P1, CA_P2) or source/drain contact patterns number 1 and number 2 (CA_SD1, CA_SD2) may include a. The, included in an integrated circuit designed in one layer a plurality of patterns corresponding to plurality of mask using patterning can be formed comprises isopropyl alcohol vapor and nitrogen gas. Plurality of mask step, the BSD the patterning layer in the case of using, integrated circuit a design step of, specifically, standard controlled oscillator automatically design step, color decompressor position (color decomposition) to each of the plurality of mask a plurality of colors respectively corresponding to the plurality of patterns so that it is possible to design.

Also number 1 layout of 7d (10d) included in the four patterns of contact number 1 (CA) (CA_SD1, CA_SD2, CA_P1, CA_P2) installed by using, to the typical four mask are required to, in this case three mask into the patterning a fourth loops, different color design to begin with, the four patterns (CA_SD1, CA_SD2, CA_P1, CA_P2) between is the development of color violation (color violation). Standard cell defining a integrated circuit chip selection signal is enabled arrangement of violation color the same routing phase and the colour (same color violation) can be problems are caused by the conflict (color conflict).

According to the present embodiment, an input/output buffer circuit is a plurality of layers a number 1 layer, for example, contact number 1 (CA) a mask for forming a threshold value disposed at the base of the housing (for example, two 4) a length different from each, mask data steps requiring the ones for reducing the number of mask in a layout number 1 number 2 layout, in is operated can be polishing. Therefore, also number 1 layout of 7d (10d) to design in steps requiring data mask relative to can be polishing. 13 also to 8 is hereinafter reference to specific polish data in the embodiment to illustrate the wheel driving shaft maintain an further enhance the to time as large as that of.

Figure 8 of the present invention according to one embodiment data surface of a altered from layout number 1 number 2 one example of layout (20a) is.

Also 8 with a, number 1 in steps requiring mask data layout (10d) of number 1 and number 2 power contact patterns (CA_P1, CA_P2) submerged together by (merge) number 2 layout (20a) for can be produced. The, number 1 and number 2 power contact patterns (CA_P1, CA_ 2) to which a voltage can be applied the same since, number 1 and number 2 power contact patterns (CA_P1, CA_ 2). be able to connect.

Specifically, layout number 1 (10d) designed different color number 1 and number 2 power contact patterns (CA_P1, CA_P2) the, number 2 layout (20a) designed the same color (CA_P) resultant structure one power. may be varied. The, number 2 layout (20a) in producing a integrated circuit based on, source/drain contact patterns number 1 and number 2 (CA_SD1, CA_SD2) and power resultant structure patterns of three (CA_P) is capable of three mask using contact number 1. capable of patterning (CA).

Number 2 layout (20a) included in the number 1 direction (CA_P) power resultant structure (for example, X direction) in width (W) has number 1, number 2 direction (for example, Y direction) number 1 in material may have a height (H). Number 2 layout (20a) the, number 1 layout (10d) as well as, power contact patterns (CA_P) the upper surfaces of the vias (V) .can be arranged.

The, number 1 the number 1 layout width (W) (10d) in number 1 and number 2 power contact patterns (CA_P1, CA_P2) each width and number 1 and number 2 power contact patterns (CA_P1, CA_P2) and the sum of the distance between can be substantially the same. However, the present invention refers to and not limited to, the (W) width number 1 number 1 layout (10d) in number 1 and number 2 power contact patterns (CA_P1, CA_P2) each width and number 1 and number 2 power contact patterns sum of the distance between (CA_P1, CA_P2) than may be small or large.

While, the 1 layout number 1 height (H) (10d) in number 1 and number 2 power contact patterns (CA_P1, CA_P2) is substantially equal to the height of each of the can be. However, the present invention refers to and not limited to, the number 1 layout number 1 height (H) (10d) in number 1 and number 2 power contact patterns (CA_P1, CA_P2) than the height of each of the may be small or large.

Therefore, according to the present embodiment, number 2 layout (20a) the number 1 layout (10d) compared to (CA) contact number 1 number of mask pattern as a mask to forming an a m number of third. In other words, , number 2 layout (20a) for integrated circuit fabrication which is an when forming the elongated mask, with the contact number 1. capable of forming a (CA).

Also the 9b and 9a IX-IX layout of of Figure 8 number 2' line. are examples of according to cross-sectional drawing.

Also refers to surface 9a, semiconductor device (200a) the substrate (SUB), conductive lines (CL), contact plug contact and power (CP) may include a (CA_Pa). A low cost is not shown, power contact (CA_Pa), for example, on the top of, power supply voltage or a ground voltage is supplied, and a metal line of a (metal line), and metal line and power contact (CA_Pa) (via) the direction of the interconnection can be arranged further and the like.

Substrate which may be the substrate a semiconductor (SUB), for example, semiconductor substrate is silicon, silicon-on-insulator (SOI), silicon-on-sapphire, germanium, silicon-germanium and a gallium arsenic either may comprise an. For example, substrate (SUB) can be the P-type substrate. Furthermore, although not shown, impurities doped active region (SUB) substrate may include a.

Conductive lines (SUB) a substrate (CL) can be disposed on. In one in the embodiment, conductive lines (CL) that can be used with the gate electrode, in this case, conductive lines (CL) and the substrate (SUB) second substrate active region in the aperture rate of the LCD can be arranged.

In one in the embodiment, conductive lines can be dummy conductive lines (CL). As such, when the conductive lines this dummy (CL) conductive lines, layout of Figure 8 number 1 (10d) in (CA_P1) number 1 and number 2 power resultant structure power resultant structure (CA_P2) the cell fortune compared to Riga can be present to be. The, resultant structure power number 1 number 2 power resultant structure (CA_P1) and the other (CA_P2) comprised in cells different standards can be if.

Contact plug (CP) on the substrate (SUB) which can be arranged on the, conductive lines (CL) and substantially the same height, may be formed as. Thereby, power contact (CA_Pa) (CL) and the conductive lines may be connected to. Contact plug disposed onto a part of the region of the substrate (CP) (SUB) power contact (CA_Pa) and the substrate (SUB) can be an electric wire electrically connecting to the.

The contact plug power contact (CA_Pa) which can be arranged on the on (CP), (CP) contact plug is electrically connected to the bump may be connected to. Thereby, power contact (CA_Pa) active region in a substrate (SUB) example to, power supply voltage or a ground voltage by using the mask pattern..

Also refers to surface 9b, semiconductor device (200b) the substrate (SUB), conductive lines (CL), contact plug (CP ') and power contact (CA_Pb) may include a. A low cost is not shown, power contact (CA_Pb), for example, on the top of, power supply voltage or a ground voltage is supplied, and a metal line of a, and connecting (CA_Pb) contact and power metal line, such as a via, is further can be arranged.

Substrate which may be the substrate a semiconductor (SUB), for example, semiconductor substrate is silicon, silicon-on-insulator (SOI), silicon-on-sapphire, germanium, silicon-germanium and a gallium arsenic either may comprise an. For example, substrate (SUB) can be the P-type substrate. Furthermore, although not shown, impurities doped active region (SUB) substrate may include a.

Conductive lines (SUB) a substrate (CL) can be disposed on. In one in the embodiment, conductive lines (CL) that can be used with the gate electrode, in this case, conductive lines (CL) and the substrate (SUB) second substrate active region in the aperture rate of the LCD can be arranged. In one in the embodiment, an active (CL) conductive lines can be conductive lines.

Contact plug (CP ') on the substrate (SUB) which can be arranged on the, conductive lines can be formed higher than (CL). Thereby, power contact (CA_Pb) the conductive lines may be not in communications with the (CL). Contact plug (CP ') the substrate (SUB) power disposed onto a part of the region of contact (CA_Pb) and the substrate (SUB) can be an electric wire electrically connecting to the.

Power contact (CA_Pb) on the contact plug (CP ') which can be arranged on the, contact plug is electrically connected to the bump (CP) may be connected to. Thereby, power contact (CA_Pb) active region in a substrate (SUB) example to, power supply voltage or a ground voltage by using the mask pattern..

Figure 10 of the present invention according to one embodiment data surface of a altered from layout number 1 number 2 in another example of a layout (20b) is.

Also with a 10, in steps requiring mask data layout number 1 (10d) of number 1 and number 2 power contact patterns (CA_P1, CA_P2) between the bridge (bridge) (BR) pattern layout number 2 by adding (20b) for can be produced. The, number 1 and number 2 power contact patterns (CA_P1, CA_P2) to which a voltage can be applied the same since, number 1 and number 2 power contact patterns (CA_P1, CA_P2). be able to connect.

Specifically, layout number 1 (10d) designed different color number 1 and number 2 power contact patterns (CA_P1, CA_P2) the, number 2 layout (20b) designed the same color (CA_P ') one power resultant structure. may be varied. The, number 2 layout (20b) in producing a integrated circuit based on, source/drain contact patterns number 1 and number 2 (CA_SD1, CA_SD2) and power resultant structure patterns of three (CA_P ') is capable of three mask using contact number 1. capable of patterning (CA).

Number 2 layout (20b) included in power resultant structure (CA_P ') the number 1 and number 2 power contact patterns (CA_P1, CA_P2) and bridge pattern can include a (BR), one mask may be formed as. Thereby, layout number 2 (20b) the H-shaped power contact (CA_P ') may include a. Number 2 layout (20b) the, number 1 layout (10d) as well as, number 1 and number 2 power contact patterns (CA_P1, CA_P2) (V) vias on. can be arranged. As such, power contact patterns number 1 and number 2 (CA_P1, CA_P2) and bridge pattern (BR) for including power contact (CA_P ') connectable mask, with the can be.

Therefore, according to the present embodiment, number 2 layout (20b) the number 1 layout (10d) compared to mask necessary to form a contact number 1 a number of m number of third. In other words, , number 2 layout (20b) for integrated circuit fabrication which is an when forming the elongated mask, with the number 1 can be of forming a contact.

Figure 11 of the present invention according to one embodiment data surface of a altered from layout number 1 number 2 in another example of a layout (20c) is.

Also 11 with a, number 1 in steps requiring mask data layout (10d) of number 1 and number 2 power contact patterns of (CA_P1, CA_P2) according to direction to reduce its height the number 2, number 1 and number 2 power contact patterns (CA_P1, CAP_ 2) which is connected to contact (CB1) is at least one selected from the layout number 2 number 2 (20c) for can be produced. The, number 1 and number 2 power contact patterns (CA_P1, CA_P2) to which a voltage can be applied the same since, number 1 and number 2 power contact patterns (CA_P1, CA_P2). be able to connect.

Specifically, layout number 1 (10d) designed different color number 1 and number 2 power contact patterns (CA_P1, CA_P2) the, number 2 layout (20c) the same color number 1 and number 2 power contact patterns designed (CA_P1 ', CA_P2') .may be varied. The, number 2 layout (20c) in producing a integrated circuit based on, source/drain contact patterns number 1 and number 2 (CA_SD1, CA_SD2) which correspond respectively to two masks and number 1 and number 2 power contact patterns (CA_P1 ', CA_P2') corresponding to single mask, with the contact number 1. capable of patterning (CA).

Number 2 layout (20c) number 2 the height (H2) having insert number 2 number 1 and number 2 power contact patterns (CA_P1 ', CA_P2') and number 2 contact (CB1) may include a. The, number 2 layout (20c) included in power contact patterns number 1 and number 2 (CA_P1 ', CA_P2') connectable mask, with the can be formed. Number 2 layout (20c) in number 1 and number 2 power contact patterns (CA_P1 ', CA_P2') on the number 1 and number 2 power contact patterns (CA_P1 ', CA_P2') aperture which is arranged on the second common to number 2 contact (CB1) and can be arranged, the upper surfaces of the vias (CB1) contact number 2 (V) .can be arranged.

Therefore, according to the present embodiment, number 2 layout (20c) the number 1 layout (10d) compared to mask necessary to form a contact number 1 a number of m number of third. In other words, , number 2 layout (20c) for integrated circuit fabrication which is an when forming the elongated mask, with the number 1 can be of forming a contact.

XII-XII layout of Figure 12 shows a number 2' line. an example of according to cross-sectional drawing of Figure 11.

Also refers to surface 12, semiconductor device (200c) the substrate (SUB), conductive lines (CL), number 1 and number 2 power contact patterns contact number 2 (CA_P1 ', CA_P2') and may include a (CB). A low cost is not shown, number 2, for example, on the top of contact (CB1), power supply voltage or a ground voltage is supplied, and a metal line of a, and connecting (CB1) contact number 2 and metal line, such as a via, is further can be arranged.

Substrate which may be the substrate a semiconductor (SUB), for example, semiconductor substrate is silicon, silicon-on-insulator (SOI), silicon-on-sapphire, germanium, silicon-germanium and a gallium arsenic either may comprise an. For example, substrate (SUB) can be the P-type substrate. Furthermore, although not shown, impurities doped active region (SUB) substrate may include a.

Conductive lines (SUB) a substrate (CL) can be disposed on. In one in the embodiment, conductive lines (CL) that can be used with the gate electrode, in this case, conductive lines (CL) and the substrate (SUB) second substrate active region in the aperture rate of the LCD can be arranged.

In one in the embodiment, conductive lines can be dummy conductive lines (CL). As such, when the conductive lines this dummy (CL) conductive lines, layout of Figure 11 number 1 (10d) in (CA_P1) number 1 and number 2 power resultant structure power resultant structure (CA_P2) the cell fortune compared to Riga can be present to be. The, resultant structure power number 1 number 2 power resultant structure (CA_P1) and the other (CA_P2) comprised in cells different standards can be if.

Number 1 and number 2 power contacts (CA_P1 ', CA_P2') on the substrate (SUB) which can be arranged on the, conductive lines (CL) and substantially the same height, may be formed as. Thereby, the conductive lines (CB1) contact number 2 (CL) and may be connected to. Number 1 and number 2 power contacts (CA_P1 ', CA_P2') a substrate (SUB) a part of the region of the, specifically, active region number 2 can be disposed (AR2).

Number 2 contact (CB1) the number 1 and number 2 power contacts (CA_P1 ', CA_P2') is arranged on, number 1 and number 2 power contacts (CA_P1 ', CA_P2') may be connected to P well region surrounded by n +. Thereby, contact number 2 number 2 (SUB) in a substrate (CB1) example to active region (AR2), power supply voltage or a ground voltage by using the mask pattern..

Figure 13 of the present invention according to one embodiment data surface of a altered from layout number 1 number 2 in another example of a layout (10d) is.

Also 13 with a, number 1 in steps requiring mask data layout (10d) of number 1 number 2 of power contact (CA_P1) according to direction and to the side surface, number 1 and number 2 power contact patterns (CA_P1, CA_P2) which is connected to contact number 2 number 2 (CB2) is at least one selected from the layout (20d) for can be produced. The, number 1 and number 2 power contact patterns (CA_P1, CA_P2) to which a voltage can be applied the same since, number 1 and number 2 power contact patterns (CA_P1, CA_P2). be able to connect.

Specifically, layout number 1 (10d) in the (CA_P1) resultant structure power number 1 number 1 source/drain resultant structure but designed color different directions (CA_SD1), number 2 layout (20d) in the (CA_P1) resultant structure power number 1 number 1 (CA_SD1) source/drain resultant structure having the same color, such that to change from an. The, number 2 layout (20d) in producing a integrated circuit based on, (CA_P1) number 1 and number 1 power resultant structure source/drain resultant structure by using a first mask (CA_SD1) .may be patterned. Therefore, layout number 2 (20d) in producing a integrated circuit based on, three mask using contact number 1. capable of patterning (CA).

Number 2 layout (20d) insert number 2 number 2 the height (H2) having power contact (CA_P1 ') number 1, number 2 and number 2 power contact (CA_P2) may include a contact (CB2). The, number 1 and number 1 source/drain contact (CA_SD1) distance between power contact (CA_P1 ') (D4') has the pattern of the material layer resolution limit least, the, source/drain contact (CA_SD1) and number 1 number 1 power contact (CA_P1 ') one mask, with the can be.

Number 2 layout (20d) in number 1 and number 2 power contact patterns (CA_P1 ', CA_P2) on bridge and a lamp cover, number 1 and number 2 power contact patterns (CA_P', CA_P2) which is connected to. can be arranged (CB2) contact number 2. Number 2 layout (20d) in power contact (CA_P1 ') number 1 the height is reduced, the number 2 power contact (CA_P2) via (V) can be arranged only on.

Therefore, according to the present embodiment, number 2 layout (20d) the number 1 layout (10d) compared to mask necessary to form a contact number 1 a number of m number of third. In other words, , number 2 layout (20d) for integrated circuit fabrication which is an when forming the elongated mask, with the number 1 can be of forming a contact.

According to one embodiment of the present invention also Figure 14 shows a layout design of IC is the flow indicating method.

Also refers to surface 14, the present embodiment according to the method 1 of IC layout design of integrated circuit illustrated also compared to manufacturing method of an integrated circuit containing as forming step, step S110 to step S230 according to the present content can be applied even in the embodiment. Therefore, reference to 13 also to 2 also is disclosed is an can be applied even in the embodiment.

In step S310, integrated circuit defining a plurality of standard cell and wiring by. is designed so that the layout number 1.

In step S320, in preparing mask data layout number 1, number 2 by changing the layout said number 1 generates layout. Specifically, corresponding to layer number 1 layout of number 1 number 1 layer mask pattern as a mask to formation of a pattern reduces the number of patterns in layer number 1 number 2 number 1 and number 2 by to each other pattern layout can be produced.

In one in the embodiment, number 1 layer, active integrated circuit in electrical connection with and contact to be formed on the active region (for example, number 1 contact (CA)) can be. In one in the embodiment, number 1 and number 2 number 1 direction patterns are and placed parallel to each other, substantially perpendicular to direction number 1 number 2 can be extending. For example, number 1 and number 2 7d also patterns are a number 1 illustrated layout (10d) of number 1 and number 2 power contact patterns can be (CA_P1, CA_P2). In one in the embodiment, number 3 patterns are layer number 1 may further include any pattern. For example, a number 1 number 3 illustrated 7d also pattern layout (10d) of source/drain resultant structure can be (CA_SD1) number 1.

In one in the embodiment, number 1 and number 2 power contact patterns (CA_P1, CA_P2) in the merged (merge) by number 1 and number 2 power contact patterns (CA_P1, CA_P2) according to direction a widened larger than a lower width of each number 1 number 1 has a width (W1), to define, and solubility, and can be pattern layout including number 2 for (CA_P) (for example, of Figure 8 20a) for can be produced.

In other in the embodiment, number 1 and number 2 power contact patterns (CA_P1, CA_P2) and number 1 and number 2 power contact patterns (CA_P1, CA_P2) including H of a bridge pattern (BR) performed on the front surface, to define, and solubility, and can be pattern including number 2 (CA_P ') of a layout (for example, of Figure 10 20b) can be produced.

In other in the embodiment, number 1 and number 2 power contact patterns (CA_P1, CA_P2) compared to number 2 according to direction and height is reduced, to define, and solubility, and can be number 1 and number 2 power contact patterns (CA_P1 ', CA_P2'), and novel number 1 and number 2 power contact patterns (CA_P1 ', CA_P2') aperture which is arranged on the second common to layout including number 2 number 2 layer (for example, of Figure 11 20c) for can be produced. The, number 2 layer, and at least one of plurality of conductive lines (CL) novel number 1 and number 2 power contact patterns (CA_P1 ', CA_P2') to be formed on the number 2 contact (CB1) can be.

In other in the embodiment, number 3 pattern, for example, distance between an (CA_SD1) resultant structure source/drain number 1 threshold distance such that a terminal portion of number 1 and number 2 power contact patterns (CA_P1, CA_P2) compared to number 2 according to direction and height is reduced, number 1 (CA_SD1) and source/drain resultant structure, and solubility, and can be formed the same mask (CA_P1 ') number 1 power resultant structure, and, novel number 1 power resultant structure (CA_P1') and said number 2 power contact pattern are connected to each other by bridge type number 2 layer layout including number 2 (for example, of Figure 13 20d) for can be produced. The, number 2 layer, at least one plurality of conductive lines (CL), novel power resultant structure (CA_P1 ') number 1 and number 2 power resultant structure to be formed on the contact number 2 (CA_P2) can be (CB2).

In one in the embodiment, number 1 number 1 and number 2 power contact patterns are standard cell included in the board, patterns in layer number 1 number 1 and number 2 power resultant structure beyond standard cell number 1 number 2 patterns are printed anode placed adjacent to the direction can be includes cell standard number 2.

In other in the embodiment, the resultant structure power said number 1 number 1 standard cell included in the board, standard cell number 1 number 1 number 2 power contact pattern printed anode placed adjacent to the direction being both contained cell standard number 2, number 1 number 1 and number 2 power resultant structure layer patterns patterns are beyond standard number 2 number 1 and number 2 to one of cells is placed adjacent a direction can be includes cell standard number 3.

Figure 15 shows a disclosure of a are also a storage medium according to embodiment (500) is block representing a.

Also refers to surface 15, storage medium (500) a computer-readable storage as the medium, computer instructions and/or data which is used to provide computer during which can be read by whether any of the stored biometric data may comprise an medium. For example, computer-readable storage medium (500) the disk, tape, CD-ROM, DVD-ROM, CD-R, CD-RW, DVD-R, such as magnetic or optical carrier DVD-RW, RAM, ROM, flash memory, such as volatile or non-volatile memory, accessible by means of an interface USB non-volatile memory, MEMS (microelectromechanical systems) and such as may include a. A storage medium computer-readable inserted into the or, or are integrated within the computer, networks and/or wireless link via an a processor related to a mobile is engagable with the computer.

Also as shown in 15, computer-readable storage medium (500) comprises a switchable polarizer and wiring program (510), library (520), analysis program (530), data structure (540) may comprise an. Disposed and wiring program (510): an embodiment exemplary of the present invention the standard cell library method for designing integrated circuit using to perform plurality of instructions may include a. For example, computer-readable storage medium (500) has a predecessor drawing standard depicted at one or more standard cell libraries were utilized to including cell for designing IC, including any instructions disposed and wiring program (510). capable of storing. Library (520) has an integrated an input/output buffer circuit is a standard unit information cell may comprise an.

Analysis program (530) defining integrated circuit integrated-circuit basis of the data analyzing a plurality of performing method may include instructions. For example, computer-readable storage medium (500) has an integrated circuit defining a standard cell and wiring designed and manufactured by a number 1 layout of needed to construct a multipanel layer number 1 number of the mask with radiation at least threshold value of instructions one at any to determine whether to including analysis program (530). capable of storing. Data structure (540) the library (520) included in a pigmented or a library of standard cell, library (520) from a library of standard cell generally included in specific information or extracting, or analysis program (530), is measured, and recorded/of an integrated circuit by produced during the a reservoir for storing managing data may include a spaces or the like.

According to embodiment of Figure 16 shows a a are also disclosure including an integrated circuit is block representing a memory card.

With a 16 also, memory card (1000) a controller (1100) with a memory (1200) electrical signal can be arranged to exchange the. For example, controller (1100) based network in, memory (1200) has can be transmitting data.

Controller (1100) and memory (1200) by technical idea of the present invention the in the embodiment according to may comprise an integrated circuit. Specifically, controller (1100) and memory (1200) a plurality of semiconductor device of at least one of transistors semiconductor substrate includes a projection portion, in preparing mask data, designed by means of a tool and wiring disposed number 1 number 2 a altered from layout based layout may be formed as. The, layer number 1 number 2 layout is needed to construct a multipanel the ones for reducing the number of the mask with radiation, corresponding to layer number 1 number 1 layout of patterns in layer number 1 number 1 and number 2 by connecting patterns can be produced.

Memory card (1000) different types of cards, for example memory stick card (memory stick card), smart media card (smart media card: SM), and a secure digital card (secure digital card: SD), mini-and a secure digital card (mini-secure digital card: mini SD), and multimedia card (multimedia card: MMC) various etc. and can construct a memory card.

According to the disclosure are also Figure 17 shows a embodiment of an integrated circuit is block that indicates computing including.

Also 17 with a, computing system (2000) a processor (2100), memory device (2200), storage device (2300), power supply (2400) and input/output device (2500) may comprise an. While, also not shown but the 17, computing system (2000) the video card, sound card, memory card, or and USB device, or other electronic device can communicate with a large a port may include further (port).

As such, computing system (2000) a processor included in an (2100), memory device (2200), storage device (2300), power supply (2400) and input/output device (2500) the, by technical idea of the present invention in the embodiment according to may comprise an integrated circuit. Specifically, processor (2100), memory device (2200), storage device (2300), power supply (2400) and input/output device (2500) a plurality of at least one of semiconductor device in semiconductor devices, semiconductor component or a semiconductor-substrate includes a projection portion in preparing mask data transistors, designed by means of a tool and wiring disposed number 1 number 2 a altered from layout based layout may be formed as. The, layer number 1 number 2 layout is needed to construct a multipanel the ones for reducing the number of the mask with radiation, corresponding to layer number 1 number 1 layout of patterns in layer number 1 number 1 and number 2 by connecting patterns can be produced.

Processor (2100) detects the special calculations or. capable of performing task (task). According to embodiment, processor (2100) has a microprocessor (micro-processor), central processing device can be (Central Processing Unit; CPU). Processor (2100) an address bus (address bus), control bus (control bus) and data bus such as bus (data bus) (2600) a memory via a device (2200), storage device (2300) and input/output device (2500) and a communication can be. According to embodiment, processor (2100) communicates with the ambient components interconnected (Peripheral Component Interconnect; PCI) such as a bus expansion bus in a even may be connected to.

Memory device (2200) the computing system (2000) required for operation of can be operative to store data. For example, memory device (2200) the dram (DRAM), mobile dram, SRAM (SRAM), blood RAM (PRAM), selective tungsten nitride (FRAM), the RAM which will know (RRAM) and/or. the system may be implemented in a MRAM (MRAM). Storage device (2300) has solid state drive (solid state drive), hard disk drive (hard disk drive), such as CD-ROM (CD-ROM) may include a.

Input/output device (2500) the keyboard, keypad, mouse such as input printer and means, the output means such as display or the like may include a. Power device (2400) the computing system (2000) required for operation of a can be provide an operating voltage to the processor.

An integrated circuit to the above-mentioned of the present invention in the embodiment between various types of package may be embodied in. For example, PoP (Package on Package) configurations of least a part of the integrated circuit, Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP) packages such as may be mounted using.

Thereby, the cold air flows embodiment shown in the present invention refers to drawing and a slant described with reference to an exemplary which purpose: to avoid a, knowledge usual the art various modifications therefrom grow with other and equalization embodiment styles are discussed that will understand. Therefore, the scope of protection of the present invention technical true a claim the idea is decided by the will should be.