THREE-DIMENSIONAL GRAPHENE SWITCHING DEVICE

A switching device includes a semiconductor layer, a graphene layer, a gate insulation layer, and a gate formed in a three-dimensional stacking structure between a first electrode and a second electrode formed on a substrate. 1. A three-dimensional graphene switching device , comprising:first and second electrodes spaced apart from each other on a substrate;a semiconductor layer and a graphene layer between the first electrode and the second electrode, the graphene layer surrounding an end portion of the semiconductor layer;a gate insulation layer surrounding the graphene layer; anda gate surrounding the gate insulation layer.2. The three-dimensional graphene switching device of claim 1 , wherein a first end portion of the semiconductor layer contacts a portion of the first electrode claim 1 , a second end portion of the semiconductor layer is connected to a first end portion of the graphene layer claim 1 , and a second end portion of the graphene layer contacts a portion of the second electrode.3. The three-dimensional graphene switching device of claim 2 , wherein the first end portion of the graphene layer is on an upper side and on lateral sides of the semiconductor layer.4. The three-dimensional graphene switching device of claim 2 , wherein the gate insulation layer is on an upper side and on lateral sides of the graphene layer.5. The three-dimensional graphene switching device of claim 4 , wherein the gate surrounds an upper side and lateral sides of the gate insulation layer on the second end portion of the semiconductor layer and the first end portion of the graphene layer.6. The three-dimensional graphene switching device of claim 1 , wherein the first electrode and the second electrode include one of metal claim 1 , conductive metal oxide claim 1 , conductive metal nitride claim 1 , and polysilicon.7. The three-dimensional graphene switching device of claim 1 , wherein the semiconductor layer includes one of silicon claim 1 , germanium claim 1 , silicon- ...

FIELD EFFECT TRANSISTOR USING GRAPHENE

According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode. 1. A field effect transistor comprising:a substrate; 'the graphene channel layer defining a slit;', 'a graphene channel layer on the substrate,'} 'the source electrode and the drain electrode being configured to apply voltages to the graphene channel layer;', 'a source electrode and a drain electrode spaced apart from each other,'}a gate electrode on the graphene channel layer; anda gate insulation layer between the graphene channel layer and the gate electrode.2. The field effect transistor of claim 1 , further comprising:a potential barrier material filling the slit of the graphene channel layer,wherein the potential barrier material is configured to induce Fowler-Nordheim (F-N) tunneling through the graphene channel layer when a gate voltage is applied to the gate electrode.3. The field effect transistor of claim 2 , wherein the potential barrier material includes undoped silicon (Si).4. The field effect transistor of claim 2 , wherein the potential barrier material and the gate insulation layer are a same material.5. The field effect transistor of claim 1 , wherein a width of the slit allows F-N tunneling through the graphene channel layer when a gate voltage is applied to the gate electrode.6. The field effect transistor of claim 1 , wherein the graphene channel layer defines a plurality of the slits.7. The field effect transistor of claim 1 , wherein the gate electrode is closer to the slit of the graphene channel layer than at least one of the source electrode and the drain electrode.8. The field effect transistor of claim 1 , wherein the source electrode is closer to the slit of the graphene ...

PRESSURE SENSOR AND PRESSURE SENSING METHOD

A pressure sensor and a pressure sensing method are provided. The pressure sensor includes a substrate; a sensor thin film transistor (TFT) disposed on the substrate and including a gate insulating layer, wherein the gate insulating layer includes an organic matrix in which piezoelectric inorganic nano-particles are dispersed; a power unit configured to apply an alternating current (AC) signal to a gate of the sensor TFT; and a pressure sensing unit configured to obtain a remnant polarization value based on a drain current which is generated in response to the AC signal and detected by the sensor TFT, and to sense a pressure based on the remnant polarization value. 1. A pressure sensor comprising:a substrate;a sensor thin film transistor (TFT) disposed on the substrate and comprising a gate insulating layer, wherein the gate insulating layer comprises an organic matrix in which piezoelectric inorganic nano-particles are dispersed;a power unit configured to apply an alternating current (AC) signal to a gate of the sensor TFT; anda pressure sensing unit configured to obtain a remnant polarization value based on a drain current which is generated in response to the AC signal and detected by the sensor TFT, and to sense pressure based on the remnant polarization value.3. The pressure sensor of claim 1 , wherein the AC signal has a frequency ranging from about 0.001 Hz to about 1 GHz.4. The pressure sensor of claim 1 , wherein a voltage amplitude of the AC signal ranges from 0.01 V to 100 V.5. The pressure sensor of claim 1 , wherein the organic matrix comprises a piezoelectric organic material.6. The pressure sensor of claim 5 , wherein the piezoelectric organic material is selected from P(VDF-TrFE) claim 5 , P(VDF-TrFE-CFE) claim 5 , and P(VDF-TrFE-CtFE).7. The pressure sensor of claim 5 , wherein the organic matrix has a crystalline structure.8. The pressure sensor of claim 5 , wherein the piezoelectric inorganic nano-particles are selected from the group consisting ...

TUNNELING FIELD-EFFECT TRANSISTOR INCLUDING GRAPHENE CHANNEL

According to example embodiments, a tunneling field-effect transistor (TFET) includes a first electrode on a substrate, a semiconductor layer on a portion of the first electrode, a graphene channel on the semiconductor layer, a second electrode on the graphene channel, a gate insulating layer on the graphene channel, and a gate electrode on the gate insulating layer. The first electrode may include a portion that is adjacent to the first area of the substrate. The semiconductor layer may be between the graphene channel and the portion of the first electrode. The graphene channel may extend beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate. 1. A tunneling field-effect transistor (TFET) comprising:a substrate; 'the first electrode including a portion that is adjacent to a first area of the substrate;', 'a first electrode on the substrate,'}a semiconductor layer on the portion of the first electrode; the semiconductor layer being between the graphene channel and the portion of the first electrode,', 'the graphene channel extending beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate;, 'a graphene channel on the semiconductor layer,'} 'the second electrode being over the first area of the substrate;', 'a second electrode on the graphene channel,'}a gate insulating layer on the graphene channel; anda gate electrode on the gate insulating layer.2. The TFET of the claim 1 , further comprising:a first insulating layer between the graphene channel and the first area of the substrate.3. The TFET of claim 1 , whereinthe first electrode comprises a body portion and an extension portion,the extension portion extends from the body portion toward the first area, andthe portion of the first electrode is the extension portion.4. The TFET of claim 3 , wherein a thickness of the extension portion is less than a ...

MEMORY DEVICES INCLUDING GRAPHENE SWITCHING DEVICES

A memory device includes a graphene switching device having a source electrode, a drain electrode and a gate electrode. The graphene switching device includes a Schottky barrier formed between the drain electrode and a channel in a direction from the source electrode toward the drain electrode. The memory device need not include additional storage element. 1. A memory device comprising:a graphene switching device having a source electrode, a drain electrode, and a gate electrode, and the graphene switching device including a Schottky barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode.2. The memory device of claim 1 , further comprising:a plurality of graphene switching devices arranged in a plurality of rows and a plurality of columns, each of the plurality of graphene switching devices having a source electrode, a drain electrode, and a gate electrode, and each of the plurality of graphene switching devices including a Schottky barrier between the drain electrode and a channel in a direction from the source electrode toward the drain electrode.3. The memory device of claim 2 , further comprising:a plurality of word lines, each of the plurality of word lines being connected to gate electrodes of graphene switching devices on a corresponding column;a plurality of bit lines, each of the plurality of bit lines being connected to drain electrodes of graphene switching devices on a corresponding row; anda plurality of source lines, each of the plurality of source lines being connected to source electrodes of graphene switching devices on a corresponding column,4. The memory device of claim 1 , wherein the graphene switching device further comprises: 'the drain electrode is on a first region of the substrate, and an insulating layer is on a second region of the substrate, the first and second regions being spaced apart from each other;', 'a conductive semiconductor substrate, wherein'} 'the source ...

METHOD OF FORMING TRANSITION METAL DICHALCOGENIDE THIN FILM

A method of forming a transition metal dichalcogenide thin film on a substrate includes treating the substrate with a metal organic material and providing a transition metal precursor and a chalcogen precursor around the substrate to synthesize transition metal dichalcogenide on the substrate. The transition metal precursor may include a transition metal element and the chalcogen precursor may include a chalcogen element. 1. A method of forming a transition metal dichalcogenide thin film on a substrate , the method comprising:treating the substrate with a metal organic material; andproviding a transition metal precursor and a chalcogen precursor around the substrate to synthesize a transition metal dichalcogenide on the substrate, the transition metal precursor including a transition metal element and the chalcogen precursor including a chalcogen element.2. The method of claim 1 , whereinthe metal organic material includes a metal for inducing adsorption of the transition metal precursor and the chalcogen precursor onto the substrate.3. The method of claim 1 , whereinthe metal organic material includes at least one of Al, Ti, and Ni.4. The method of claim 3 , whereinthe metal organic material includes at least one of trimethylaluminum, tris(demethylamido)aluminum, triisbutylaluminum, titanium isopropoxide, tetrakis(dimethylamido)titanium, bis(cyclopentadinenyl)nickel, and bis(ethylcyclopentadienyl)nickel.5. The method of claim 1 , wherein {'br': None, 'sub': 1-a', 'a', '2(1-b)', '2b, 'MM′XX′\u2003\u2003'}, 'the transition metal dichalcogenide is represented by Formula 1 belowwherein, in Formula 1,M and M′ are different transition metal elements from each other, [{'br': None, 'i': 'a<', '0≤1, and'}, {'br': None, 'i': 'b<', '0≤1.'}], 'X and X′ are different chalcogen elements from each other,'}6. The method of claim 1 , whereinthe transition metal element includes at least one of Ti, Zr, Hf, V, Nb, Ta, Mo, W, Tc, Re, Co, Rh, Ir, Ni, Pd, Pt, Zn, and Sn, ...

TRIBOELECTRIC DEVICE

Example embodiments relate to a triboelectric device including first and second electrodes that are spaced apart from each other, a charging layer provided on the first electrode, a display layer, which is provided between the first and second electrodes, configured to implement an image according to a change in an electric field between the first and second electrodes, and a charging member charged with an opposite polarity to the polarity of the charging layer by contacting the charging layer, wherein the triboelectric device is configured to implement the image according to the change in the electric field between the first and second electrodes in a contact area of the charging member and the charging layer. 1. A triboelectric device comprising:a first electrode and a second electrode spaced apart from each other;a charging layer on the first electrode;a display layer between the first and second electrodes, the display layer being configured to implement an image according to a change in an electric field between the first and second electrodes; anda charging member configured to be charged with an opposite polarity to a polarity of the charging layer when contacting the charging layer, whereinthe triboelectric device is configured to implement the image according to the change in the electric field between the first and second electrodes in a contact area of the charging member and the charging layer.2. The triboelectric device of claim 1 , whereinthe display layer includes a plurality of micro capsules between the first and second electrodes, and each of the micro capsules includes a plurality of first and second particles, wherein one of the first and second particles has a charge of opposite polarity to a polarity of another one of the first and second particles.3. The triboelectric device of claim 2 , whereinthe first and second particles are configured to move according to the change in the electric field between the first and second electrodes in the ...

GRAPHENE SWITCHING DEVICE HAVING TUNABLE BARRIER

According to example embodiments, a graphene switching devices having a tunable barrier includes a semiconductor substrate that includes a first well doped with an impurity, a first electrode on a first area of the semiconductor substrate, an insulation layer on a second area of the semiconductor substrate, a graphene layer on the insulation layer and extending onto the semiconductor substrate toward the first electrode, a second electrode on the graphene layer and insulation layer, a gate insulation layer on the graphene layer, and a gate electrode on the gate insulation layer. The first area and the second area of the semiconductor substrate may be spaced apart from each other. The graphene layer is spaced apart from the first electrode. A lower portion of the graphene layer may contact the first well. The first well is configured to form an energy barrier between the graphene layer and the first electrode. 1. A graphene switching device having a tunable barrier , the graphene switching device comprising: 'the semiconductor substrate including a first well doped with an impurity;', 'a semiconductor substrate,'}a first electrode on a first area of the semiconductor substrate; 'the first area and the second area being spaced apart from each other;', 'an insulation layer on a second area of the semiconductor substrate,'} the graphene layer extending onto the semiconductor substrate toward the first electrode,', 'the graphene layer being spaced apart from the first electrode,', 'the graphene layer including a lower portion that contacts the first well of the semiconductor substrate,', 'the first well being configured to form an energy barrier between the graphene layer and the first electrode;, 'a graphene layer on the insulation layer,'}a second electrode on the graphene layer and the insulation layer;a gate insulation layer on the graphene layer; anda gate electrode on the gate insulation layer.2. The graphene switching device of claim 1 , wherein a lower portion of ...

METHOD OF DIRECTLY GROWING CARBON MATERIAL ON SUBSTRATE

Provided are methods of directly growing a carbon material. The method may include a first operation and a second operation. The first operation may include adsorbing carbons onto a substrate by supplying the carbons to the substrate. The second operation may include removing unreacted carbon residues from the substrate after suspending the supplying the carbons of the first operation. The two operations may be repeated until a desired graphene is formed on the substrate. The substrate may be maintained at a temperature less than 700° C. In another embodiment, the method may include forming a carbon layer on a substrate, removing carbons that are not directly adsorbed to the substrate on the carbon layer, and repeating the two operations until desired graphene is formed on the substrate. The forming of the carbon layer includes supplying individual carbons onto the substrate by preparing the individual carbons. 1. A method of directly growing a carbon material , the method comprising:performing a first operation that includes adsorbing carbons onto a substrate by supplying the carbons to the substrate; andperforming a second operation that includes removing unreacted carbon residues from the substrate after suspending the supplying the carbons of the first operation.2. The method of claim 1 , whereinthe first operation and the second operation are repeated until a desired graphene is formed on the substrate, andan amount of carbons supplied in the repeated first operation and second operation is equal to or different from the amount of carbons supplied in the first operation.3. The method of claim 1 , wherein the adsorbing the carbons onto the substrate during the performing the first operation includes:maintaining the substrate at a temperature less than 700° C.;preparing a carbon source; andsupplying the carbons onto the substrate by separating the carbons included in the carbon source.4. The method of claim 3 , wherein the maintaining the substrate includes ...

Interconnect structure and electronic device employing the same

An interconnect structure and an electronic device including the interconnect structure are disclosed. The interconnect structure may include a metal interconnect having a bottom surface and two opposite side surfaces surrounded by a dielectric layer, a graphene layer on the metal interconnect, and a metal bonding layer providing interface adhesion between the metal interconnect and the graphene layer. The metal bonding layer includes a metal material.

INTERCONNECT STRUCTURE HAVING NANOCRYSTALLINE GRAPHENE CAP LAYER AND ELECTRONIC DEVICE INCLUDING THE INTERCONNECT STRUCTURE

Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals. 1. An interconnect structure comprising:a dielectric layer including at least one trench;a conductive wiring filling an inside of the at least one trench; anda cap layer on at least one surface of the conductive wiring, the cap layer including nanocrystalline graphene, the nanocrystalline graphene including nano-sized crystals.2. The interconnect structure of claim 1 , wherein the nano-sized crystals have a size of about 0.5 nm to about 100 nm.3. The interconnect structure of claim 1 , wherein a ratio of carbon having an spbonding structure to total carbon in the nanocrystalline graphene is in a range from about 50% to about 99%.4. The interconnect structure of claim 1 , wherein the nanocrystalline graphene comprises hydrogen of 1 at % to 20 at %.5. The interconnect structure of claim 1 , wherein density of the nanocrystalline graphene is 1.6 g/cc to 2.1 g/cc.6. The interconnect structure of claim 1 , further comprising:a substrate, whereinthe dielectric layer is on the substrate.7. The interconnect structure of claim 6 , wherein the at least one trench in the dielectric layer includes at least one of:a first trench in the dielectric layer that does not reach the substrate, ora second trench in the dielectric layer that reaches the substrate.8. The interconnect structure of claim 1 , wherein the conductive wiring includes one of a metal claim 1 , a metal alloy claim 1 , or a combination thereof.9. The interconnect structure of claim 1 , further comprising:a barrier layer, whereinthe barrier layer covers the conductive wiring in the at least one trench.10. ...

METHOD OF FORMING NANOCRYSTALLINE GRAPHENE, AND DEVICE INCLUDING NANOCRYSTALLINE GRAPHENE

A method of forming nanocrystalline graphene by a plasma-enhanced chemical vapor deposition process is provided. The method of forming nanocrystalline graphene includes arranging a protective layer on a substrate and growing nanocrystalline graphene directly on the protective layer by using a plasma of a reaction gas. The reaction gas may include a mixed gas of a carbon source gas, an inert gas, and hydrogen gas. 1. A method of forming nanocrystalline graphene , the method comprising:arranging a substrate in a reaction chamber, the substrate including a material having a certain permittivity or lower;forming a protective layer on the substrate;injecting into the reaction chamber a reaction gas that includes a mixture of a carbon source gas, an inert gas, and hydrogen gas;generating a plasma of the reaction gas in the reaction chamber; and,growing a nanocrystalline graphene directly on a surface of the protective layer using the plasma of the reaction gas at a temperature of 700° C. or lower.2. The method of claim 1 , wherein{'sub': '2', 'the protective layer includes one selected from a self-assembled monolayer, graphene quantum dots (GQDs), boron nitride (h-BN), and MX, wherein M is a transition metal and X is a chalcogen element of a transition metal dichalcogenide monolayer (TMDC), the self-assembled monolayer includes one of an amorphous carbon layer, hexamethyldisilazane (HMDS), chlorotrimethylsilane (TMCS), or trichloromethylsilane (TCMS).'}3. The method of claim 1 , wherein{'sub': 2', '2, 'the substrate includes at least one of silicon dioxide (SiO), carbon-doped SiO, silsesquioxane, hydrogen silsesquioxane (HSQ), or methyl silsesquioxane (MSQ).'}4. The method of claim 1 , whereinthe plasma of the reaction gas includes radio frequency (RF) plasma or microwave (MW) plasma.5. The method of claim 1 , whereina power for generating the plasma of the reaction gas is in a range of about 10 W to about 4000 W.6. The method of claim 1 , whereina volume ratio of the ...

Method of forming interconnect structure

Provided is a method of forming an interconnect structure. The method includes preparing a substrate including a first metal layer and a first insulating layer, selectively forming a carbon layer having an sp 2 bonding structure on the first metal layer, selectively forming a second insulating layer on the first insulating layer, forming a third insulating layer to cover the second insulating layer, and forming a second metal layer electrically connected to the first metal layer.

TRIBOELECTRIC GENERATOR USING SURFACE PLASMON RESONANCE

Disclosed are triboelectric generators using surface plasmon resonance. A triboelectric generator includes first and second electrodes spaced apart from each other, first and second electrification layers provided on the first and second electrodes, respectively, and a light source provided to irradiate light onto the second electrification layer. Herein, the second electrification layer includes a metallic material configured to generate surface plasmon resonance due to light of a desired wavelength, and the light source irradiates the light of the desired wavelength configured to generate the surface plasmon resonance, onto the second electrification layer. 1. A triboelectric generator comprising:first and second electrodes spaced apart from each other;a first electrification layer on a surface of the first electrode facing the second electrode, and including a dielectric material;a second electrification layer on a surface of the second electrode facing the first electrode, electrified with charges of an opposite polarity with respect to the first electrification layer due to contact with the first electrification layer, the second electrification layer including a metallic material configured to generate surface plasmon resonance due to light of a desired wavelength; anda light source configured to irradiate the light onto the second electrification layer.2. The triboelectric generator of claim 1 , wherein the first and second electrification layers are in contact with each other due to pressing claim 1 , sliding claim 1 , or rotating.3. The triboelectric generator of claim 1 , wherein the first and second electrodes comprise at least one of graphene claim 1 , carbon nanotubes (CNT) claim 1 , indium tin oxide (ITO) claim 1 , metal claim 1 , and conductive polymer.4. The triboelectric generator of claim 1 , wherein at least one of the first and second electrodes comprises a material configured to transmit the light.5. The triboelectric generator of claim 1 , ...

METHODS OF PREPARING GRAPHENE AND DEVICE INCLUDING GRAPHENE

A method of preparing graphene includes forming a silicon carbide thin film on a substrate, forming a metal thin film on the silicon carbide thin film, and forming a metal composite layer and graphene on the substrate by heating the silicon carbide thin film and the metal thin film. 1. A method of preparing graphene comprising:forming a silicon carbide thin film on a substrate;forming a metal thin film on the silicon carbide thin film; andforming a metal composite layer and graphene on the substrate by heating the silicon carbide thin film and the metal thin film.2. The method according to claim 1 , wherein the forming graphene forms the graphene between the substrate and the metal composite layer.3. The method according to claim 1 , wherein the forming a metal composite layer and graphene includes heating the silicon carbide thin film and the metal thin film at a temperature in a range of about 1000° C. to about 1100° C.4. The method according to claim 1 , wherein the forming a metal composite layer and graphene includes heating the silicon carbide thin film and the metal thin film for about 0.5 hour to about 2 hours.5. The method according to claim 1 , wherein the forming a metal thin film forms at least one of palladium (Pd) claim 1 , copper (Cu) claim 1 , iron (Fe) and manganese (Mn).6. The method according to claim 1 , wherein the forming a silicon carbide thin film forms one of a polycrystalline silicon carbide thin film and an amorphous silicon carbide thin film.7. The method according to claim 1 , wherein the substrate is formed of an insulation material.8. The method according to claim 1 , wherein the substrate is formed of an oxide.9. The method according to claim 1 , wherein the substrate includes at least one of sapphire (AlO) claim 1 , lanthanum aluminate (LaAlO) and strontium titanium oxide (SrTiO).10. The method according to claim 1 , wherein the forming graphene includes forming the graphene having a D-peak claim 1 , a G-peak and a 2D-peak.11. The ...

WIRING STRUCTURES, METHODS OF FORMING THE SAME, AND SEMICONDUCTOR DEVICES INCLUDING THE SAME

A wiring structure includes a first conductive pattern including doped polysilicon on a substrate, an ohmic contact pattern including a metal silicide on the first conductive pattern, an oxidation prevention pattern including a metal silicon nitride on the ohmic contact pattern, a diffusion barrier including graphene on the oxidation prevention pattern, and a second conductive pattern including a metal on the diffusion barrier. 1. A wiring structure , comprising:a first conductive pattern on a substrate, the first conductive pattern including doped polysilicon;an ohmic contact pattern on the first conductive pattern, the ohmic contact pattern including a metal silicide;an oxidation prevention pattern on the ohmic contact pattern, the oxidation prevention pattern including a metal silicon nitride;a diffusion barrier on the oxidation prevention pattern, the diffusion barrier including graphene; anda second conductive pattern on the diffusion barrier, the second conductive pattern including a metal,wherein the first conductive pattern, the ohmic contact pattern, the oxidation prevention pattern, the diffusion barrier, and the second conductive pattern are sequentially stacked in the stated order on the substrate.2. The wiring structure as claimed in claim 1 , wherein:the ohmic contact pattern includes titanium silicide, andthe oxidation prevention pattern includes titanium silicon nitride.3. The wiring structure as claimed in claim 1 , wherein:the ohmic contact pattern includes tantalum silicide or tungsten silicide, andthe oxidation prevention pattern includes tantalum silicon nitride or tungsten silicon nitride.4. The wiring structure as claimed in claim 1 , further comprising a metal oxide layer between the first conductive pattern and the oxidation prevention pattern.5. The wiring structure as claimed in claim 4 , wherein the metal oxide layer is formed only on a portion of an upper surface of the first conductive pattern.6. The wiring structure as claimed in claim ...

METHOD OF FORMING TRANSITION METAL DICHALCOGENIDETHIN FILM AND METHOD OF MANUFACTURING ELECTRONIC DEVICE INCLUDING THE SAME

Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: depositing a transition metal dichalcogenide thin film on a substrate; and heat-treating the deposited transition metal dichalcogenide thin film. 1. A method of forming a thin film of transition metal dichalcogenide , the method comprising:providing a substrate in a reaction chamber; 'the precursor including a transition metal and a chalcogen; and', 'depositing a transition metal dichalcogenide thin film on the substrate using a sputtering process that uses a precursor and is performed at a first temperature,'}heat-treating the transition metal dichalcogenide thin film on the substrate at a second temperature under a chalcogen atmosphere, the second temperature being higher than the first temperature.2. The method of claim 1 , wherein the transition metal dichalcogenide thin film includes at least one of an amorphous material and a polycrystalline material.3. The method of claim 1 , wherein the transition metal dichalcogenide thin film includes a composition represented by Formula 1 below:{'br': None, 'sub': (2-a)', 'a, 'MXY\u2003\u2003 [Formula 1]'}wherein, in Formula 1 above, M is a transition metal element, X is a chalcogen element, Y is an element other than the transition metal and the chalcogen element, and 0≤a<2 is satisfied.4. The method of claim 1 , wherein the depositing the transition metal dichalcogenide thin film is performed at a temperature of about 500° C. to about 800° C.5. The method of claim 1 , whereinthe heat-treating the transition metal dichalcogenide thin film is performed at a temperature of about 800° C. to about 1200° C.6. The method of claim 1 , wherein the heat-treating the transition metal dichalcogenide thin film includes forming the chalcogen atmosphere by providing a chalcogen-containing gas.7. The method of claim 1 , ...

ELECTRONIC DEVICE INCLUDING GRAPHENE

According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 10cm, and a depletion width of less than or equal to 3 nm. 1. An electronic device comprising: the semiconductor layer includes a constant doping density in overall, or', [{'sup': 19', '−3, 'a doping density that is less than or equal to 10cm, and'}, 'a depletion width of less than or equal to 3 nm;, 'the area includes at least one of'}], 'a semiconductor layer including an area, wherein'}a graphene directly contacting the area of the semiconductor layer; anda metal layer on the graphene.2. The electronic device of claim 1 , wherein the area of the semiconductor layer includes one of the constant doping density and the doping density that is less than or equal to 10cm.3. The electronic device of claim 1 , wherein the area of the semiconductor layer includes the depletion width of less than or equal to 3 nm.4. The electronic device of claim 3 , wherein the semiconductor layer is a semiconductor substrate.5. The electronic device of claim 3 , wherein the semiconductor layer includes at least one of silicon claim 3 , germanium claim 3 , silicon-germanium claim 3 , a II-VI group semiconductor claim 3 , and a III-V group semiconductor.6. The electronic device of claim 5 , wherein the semiconductor layer is weakly doped.7. A field effect transistor (FET) comprising: the source and drain areas being separated from each other,', a doping density in the source and drain areas that is equal to a doping density in the channel area, and', {'sup': 19', '−3, 'at least one of a doping density in the source and drain areas that is less than or equal to 10cm, and a depletion width that ...

SEMICONDUCTOR DEVICE INCLUDING SURFACE-TREATED SEMICONDUCTOR LAYER

Disclosed is a semiconductor device including a surface-treated semiconductor layer. The semiconductor device includes a metal layer, a semiconductor layer electrically contacting the metal layer and having a surface treated with an element having an electron affinity of about 4 eV or greater, and a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure.

Interconnect structure to reduce contact resistance, electronic device including the same, and method of manufacturing the interconnect structure

An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of a peripheral region of the semiconductor layer, a metal layer facing the semiconductor layer, a graphene layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the graphene layer and the semiconductor and covering the first region.

SEMICONDUCTOR MEMORY DEVICE AND APPARATUS INCLUDING THE SAME

A semiconductor memory device and a device including the same are provided. The semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate; bit line structures extending across the word lines in a second direction crossing the first direction; contact pad structures between the word lines and between the bit line structures; and spacers between the bit line structures and the contact pad structures. The spacers include a boron nitride layer. 1. A semiconductor memory device comprising:a semiconductor substrate;word lines extending in a first direction on the semiconductor substrate;bit line structures extending across the word lines, the bit line structures extending in a second direction crossing the first direction;contact pad structures between the word lines and between the bit line structures; andspacers between the bit line structures and the contact pad structures, the spacers comprising a boron nitride layer.2. The semiconductor memory device of claim 1 , wherein the spacers extend in the second direction along one sidewall of the bit line structures.3. The semiconductor memory device of claim 1 , wherein the spacers are surround at least a part of the contact pad structures.4. The semiconductor memory device of claim 3 , wherein the spacers are in direct contact with at least a portion of the contact pad structures.5. The semiconductor memory device of claim 1 , wherein the bit line structures comprise a polysilicon pattern claim 1 , a barrier/liner pattern claim 1 , a metal pattern claim 1 , and a hard mask pattern claim 1 , which are sequentially stacked on the semiconductor substrate claim 1 , andthe spacers overlap the polysilicon pattern, the barrier/liner pattern, and the metal pattern with respect to the first direction.6. The semiconductor memory device of claim 5 , wherein the spacers are in direct contact with at least one of the polysilicon pattern claim 5 , the barrier/liner pattern claim 5 , and ...

METHOD OF FORMING GRAPHENE

Provided is a method of forming graphene. The method of forming graphene includes treating a surface of a substrate placed in a reaction chamber with plasma while applying a bias to the substrate, and growing graphene on the surface of the substrate by plasma enhanced chemical vapor deposition (PECVD). 1. A method of forming graphene , the method comprising:treating a surface of a substrate placed in a reaction chamber with plasma while applying a bias to the substrate; andgrowing graphene on the surface of the substrate by plasma enhanced chemical vapor deposition (PECVD).2. The method of claim 1 , whereinthe treating the surface of the substrate including forming at least one of charges and activation sites inducing adsorption of activated carbon on the surface of the substrate.3. The method of claim 2 , wherein the activation sites includes at least one of roughness and defects.4. The method of claim 1 , wherein the treating the surface of the substrate includes:injecting a pretreatment gas into the reaction chamber;applying the bias to the substrate; andgenerating the plasma in the reaction chamber while applying the bias to the substrate.5. The method of claim 4 , wherein the pretreatment gas includes at least one of an inert gas claim 4 , hydrogen claim 4 , oxygen claim 4 , ammonia claim 4 , chlorine claim 4 , bromine claim 4 , fluorine claim 4 , and fluorocarbon.6. The method of claim 4 , whereinthe applying the bias to the substrate includes supplying a bias power to the substrate, andthe bias power ranges from about 1 W to about 100 W.7. The method of claim 1 , wherein the growing of the graphene includes:injecting a reaction gas including a carbon source into the reaction chamber; anddirectly growing the graphene on the surface of the substrate by generating plasma in the reaction chamber.8. The method of claim 7 , wherein the reaction gas further includes at least one of an inert gas and hydrogen gas.9. The method of claim 7 , wherein the treating the ...

GRAPHENE DEVICE INCLUDING SEPARATED JUNCTION CONTACTS AND METHOD OF MANUFACTURING THE SAME

A graphene device including separated junction contacts and a method of manufacturing the same are disclosed. The graphene device is a field effect transistor (FET) in which graphene is used as a channel. A source electrode and a drain electrode do not directly contact the graphene channel, and junction contacts formed by doping semiconductor are separately disposed between the graphene channel and the source electrode and between the graphene channel and the drain electrode. Therefore, in an off state where a voltage is not applied to a gate electrode, due to a barrier between the graphene channel and the junction contacts, carriers may not move. As a result, the graphene device may have low current in the off state. 1. A graphene device , comprising:a graphene channel layer;a gate electrode configured to apply an electric field to the graphene channel layer; andfirst and second junction contact layers contacting at least portions of the graphene channel layer,wherein the first and second junction contact layers are electrically separated from each other.2. The graphene device of claim 1 , further comprising a substrate claim 1 ,wherein the first and second junction contact layers are adjacently disposed on at least a portion of a top surface of the substrate.3. The graphene device of claim 2 ,wherein the first and second junction contact layers are doped to have a same conduction type, andwherein the substrate is doped to have an electrically opposite conduction type to the conduction type of the first and second junction contact layers.4. The graphene device of claim 2 , wherein the substrate comprises an insulating material.5. The graphene device of claim 2 , further comprising a separation film between the first junction contact layer and the second junction contact layer claim 2 , the separation film electrically separating the first junction contact layer from the second junction contact layer.6. The graphene device of claim 5 , wherein the separation film ...

GRAPHENE DEVICE AND ELECTRONIC APPARATUS

A graphene device and an electronic apparatus including the same are provided. According to example embodiments, the graphene device includes a transistor including a source, a gate, and a drain, an active layer through which carriers move, and a graphene layer between the gate and the active layer. The graphene layer may be configured to function both as an electrode of the active layer and a channel layer of the transistor. 1. A graphene device comprising:an active layer;a graphene layer contacting the active layer, the graphene layer and the active layer configured to provide a pathway for current flow; anda first electrode spaced apart from the graphene layer, the first electrode configured to control a work function of the graphene layer based on a voltage applied to the first electrode.2. The graphene device of claim 1 , further comprising:a second electrode contacting the active layer.3. The graphene device of claim 2 , further comprising:a third electrode contacting the graphene layer.4. The graphene device of claim 3 , wherein the third electrode is one of a source electrode of the transistor and a drain electrode of the transistor.5. The graphene device of claim 1 , whereinthe graphene layer is a channel of a transistor, andthe first electrode is a gate of the transistor.6. The graphene device of claim 1 , further comprising:a second electrode contacting the active layer, wherein a polarity of carriers moving from the active layer to the graphene layer is opposite to a polarity of carriers moving from the active layer to the second electrode.7. The graphene device of claim 6 , wherein the polarity of the carriers moving in the graphene layer changes according to a polarity of a voltage applied to the first electrode.8. The graphene device of claim 7 , whereinif the voltage applied to the first electrode is positive, the carriers moving in the graphene layer are electrons, and,if the voltage applied to the first electrode is negative, the carriers moving in ...

MEMORY DEVICE USING GRAPHENE AS CHARGE-TRAP LAYER AND METHOD OF OPERATING THE SAME

A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges. 1. A graphene memory comprising:a conductive semiconductor substrate;a source and a drain spaced apart from each other on the conductive semiconductor substrate;a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain; anda gate electrode on the graphene layer,wherein a Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges.2. The graphene memory of claim 1 , wherein the conductive semiconductor substrate includes one of silicon claim 1 , germanium claim 1 , silicon-germanium claim 1 , and a Group III-V semiconductor.3. The graphene memory of claim 1 , wherein the graphene layer includes one to four layers of graphene.4. The graphene memory of claim 1 , wherein the graphene layer includes at least one of a hole and a slit.5. The graphene memory of claim 1 , further comprising:a conductive layer contacting the graphene layer and facing the conductive semiconductor substrate with respect to the graphene layer.6. The graphene memory of claim 5 , wherein the conductive layer includes one of metal and polysilicon.7. The graphene memory of claim 5 , wherein each of the graphene layer and the conductive layer includes one of holes and slits.8. The graphene memory of claim 7 , wherein the one of the holes and the slits of the graphene layer are connected to the one of the holes and the slits of the conductive layer.9. The ...

METHOD OF FORMING GRAPHENE

A method of growing graphene includes forming a carbon monolayer on a substrate by injecting a first reaction gas into a reaction chamber, wherein the first reaction gas includes a first source including a component that is a carbon source and belongs to an electron withdrawing group, and injecting a second reaction gas including a second source into the reaction chamber, wherein the second source includes a functional group that forms a volatile structure by reacting with a component that belongs to an electron withdrawing group. Graphene may be directly grown on a surface of the substrate by repeatedly injecting the first reaction gas and the second reaction gas. 1. A method of forming graphene , the method comprising:forming a carbon monolayer on a substrate by injecting a first reaction gas into a reaction chamber, wherein the first reaction gas comprises a first source being a carbon source and including a component that belongs to an electron withdrawing group; andinjecting a second reaction gas including a second source into the reaction chamber, wherein the second source includes a functional group that forms a volatile structure by reacting with the component that belongs to an electron withdrawing group,wherein graphene is directly grown on a surface of the substrate by repeatedly injecting the first reaction gas and the second reaction gas.2. The method of claim 1 , wherein the first source comprises a component that belongs to an electron withdrawing group in which an electronegativity difference between a carbon atom and a functional group is greater than that of between carbon and hydrogen.3. The method of claim 2 , wherein the component that belongs to an electron withdrawing group of the first source comprises at least one functional group selected from the group consisting of amine claim 2 , thiol claim 2 , alcohol claim 2 , carboxyl claim 2 , carbonyl claim 2 , amide claim 2 , and halogen.4. The method of claim 1 , wherein the second source ...

METHOD OF GROWING GRAPHENE SELECTIVELY

Provided is a method of selectively growing graphene. The method includes forming an ion implantation region and an ion non-implantation region by implanting ions locally into a substrate; and selectively growing graphene in the ion implantation region or the ion non-implantation region. 1. A method of growing graphene selectively , the method comprising:forming an ion implantation region and an ion non-implantation region in a substrate by implanting ions locally into the substrate; andselectively growing graphene in the ion implantation region or the ion non-implantation region.2. The method of claim 1 , wherein the ions comprise at least one of As claim 1 , P claim 1 , B claim 1 , BCl claim 1 , In claim 1 , Sb claim 1 , Ge claim 1 , N claim 1 , H claim 1 , He claim 1 , and C.3. The method of claim 1 , wherein the ions are implanted in a range of 10at/cmto 10at/cm.4. The method of claim 1 , wherein the forming the ion implantation region is performed with an energy in a range of about 0.1 keV to about 10 claim 1 ,000 keV during the implanting ions locally into the substrate.5. The method of claim 1 , wherein the ions are configured to promote growth of graphene.6. The method of claim 1 , wherein the ions are configured to inhibit growth of graphene.7. The method of claim 1 , further comprising:doping a dopant into the substrate, whereinthe dopant is configured to inhibit growth of graphene on the substrate.8. The method of claim 1 , further comprising:doping boron (B) into the substrate; anddoping phosphorus (P) into the ion implantation region.9. The method of claim 1 , further comprising:forming a diffusion barrier between the ion implantation region and a portion of the substrate adjacent thereto.10. The method of claim 9 , wherein the diffusion barrier comprises TiN claim 9 , TaN claim 9 , graphene claim 9 , or h-BN.11. The method of claim 1 , wherein the substrate comprises a semiconductor claim 1 , a conductor claim 1 , or an insulator.12. The method of ...

GRAPHENE DEVICES AND METHODS OF FABRICATING THE SAME

A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable Schottky barrier formed by junction of the first electrode, the graphene layer, and the semiconductor substrate. 1. A graphene device comprising:a semiconductor substrate having a first region and a second region;a graphene layer on the first region, but not on the second region of the semiconductor substrate;a first electrode on a first portion of the graphene layer;a second electrode on a second portion of the graphene layer;an insulating layer between the graphene layer and the second electrode; and 'the semiconductor substrate has a tunable Schottky barrier formed by junction of the first electrode, the graphene layer, and the semiconductor substrate.', 'a third electrode on the second region of the semiconductor substrate; wherein'}2. The graphene device of claim 1 , wherein the graphene layer directly contacts the semiconductor substrate.3. The graphene device of claim 1 , wherein the first electrode directly contacts the graphene layer.4. The graphene device of claim 1 , wherein a surface of the first region of the semiconductor substrate is flat.5. The graphene device of claim 1 , wherein the first electrode is a source electrode claim 1 , the second electrode is a gate electrode claim 1 , and the third electrode is a drain electrode.6. The graphene device of claim 1 , wherein the semiconductor substrate has a carrier concentration of between about 10and about 10cm claim 1 , inclusive.7. The graphene device of claim 1 , further comprising:a high-concentration ...

Field effect transistor using graphene

According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.

METHODS OF FORMING GRAPHENE AND GRAPHENE MANUFACTURING APPARATUSES

A graphene manufacturing apparatus includes a reaction chamber a substrate supporter configured to structurally support a substrate inside the reaction chamber; a plasma generator configured to generate a plasma inside the reaction chamber; a first gas supply configured to supply an inert gas into the reaction chamber at a first height from an upper surface of the substrate supporter in a height direction of the reaction chamber; a second gas supply configured to supply a carbon source into the reaction chamber at a second height from the upper surface of the substrate supporter in the height direction of the reaction chamber; and a third gas supply configured to supply a reducing gas into the reaction chamber, wherein the first to third gas supply units are disposed at different heights at a third height from the upper surface of the substrate supporter in the height direction of the reaction chamber. 1. A graphene manufacturing apparatus , comprising:a reaction chamber;a substrate supporter inside the reaction chamber, the substrate supporter configured to structurally support a substrate inside the reaction chamber;a plasma generator configured to generate a plasma inside the reaction chamber;a first gas supply configured to supply an inert gas into the reaction chamber at a first height from an upper surface of the substrate supporter in a height direction of the reaction chamber;a second gas supply configured to supply a carbon source into the reaction chamber at a second height from the upper surface of the substrate supporter in the height direction of the reaction chamber; anda third gas supply configured to supply a reducing gas into the reaction chamber at a third height from the upper surface of the substrate supporter in the height direction of the reaction chamber,wherein the first height is greater than the second height, and the second height is greater than the third height.2. The graphene manufacturing apparatus of claim 1 , wherein a ratio of the ...

METHOD OF PRE-TREATING SUBSTRATE AND METHOD OF DIRECTLY FORMING GRAPHENE USING THE SAME

Provided are a method of pre-treating a substrate and a method of directly forming graphene by using the method of pre-treating the substrate. In the method of pre-treating the substrate in the method of directly forming graphene, according to an embodiment, the substrate is pre-treated by using a pre-treatment gas including at least a carbon source and hydrogen. The method of directly forming graphene includes a process of pre-treating a substrate and a process of directly growing graphene on the substrate that is pre-treated. The process of pre-treating the substrate is performed according to the method of pre-treating the substrate. 1. A method of pre-treating a substrate on which graphene is directly formed , the method comprising:pre-treating the substrate using a pre-treatment gas including at least a carbon source and hydrogen.2. The method of claim 1 , wherein the pre-treatment gas further includes N claim 1 , a noble gas claim 1 , or both Nand a noble gas.3. The method of claim 2 , wherein the pre-treating the substrate includes discontinuously suppling the at least one of the carbon source and the hydrogen of the pre-treatment gas to the substrate.4. The method of claim 2 , wherein the pre-treating the substrate includes preparing a mixed pre-treatment gas claim 2 , based on mixing the carbon source and the hydrogen outside a chamber before the graphene is directly formed on the substrate claim 2 , and supplying the mixed pre-treatment gas to the chamber while the substrate is placed in the chamber.5. The method of claim 2 ,the pre-treating the substrate includes supplying the carbon source and the hydrogen individually supplied to a chamber where the substrate is placed, andthe carbon source and the hydrogen are mixed in the chamber during the pre-treating the substrate.6. The method of claim 1 , wherein{'sub': x', 'y, 'the carbon source is represented by the formula CH,'}x is in a range from 1 to 12, andy is in a range from 2 to 26.7. The method of claim ...

Interconnect structure having nanocrystalline graphene cap layer and electronic device including the interconnect structure

Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

TRIBOELECTRIC GENERATOR

Example embodiments relate to triboelectric generators that include a first electrode and a triboelectric material layer facing first electrode, and a self-assembled monolayer that is combined with a surface of the first electrode or a surface of the triboelectric material layer between the first electrode and the triboelectric material layer. The self-assembled monolayer is formed of or include a material that includes a silane group, a silanol group, or a thiol group according to a material to be combined. 1. A triboelectric generator comprising:a first electrode and a triboelectric material layer facing the first electrode; anda self-assembled monolayer that is combined with one of a surface of the first electrode and a surface of the triboelectric material layer between the first electrode and the triboelectric material layer.2. The triboelectric generator of claim 1 , wherein the first electrode comprises a metal claim 1 , and the self-assembled monolayer includes a thiol group combined with the surface of the first electrode.3. The triboelectric generator of claim 1 , wherein the first electrode comprises a metal oxide claim 1 , and the self-assembled monolayer includes a silane group or a silanol group combined with the surface of the first electrode.4. The triboelectric generator of claim 1 , wherein the self-assembled monolayer has a thickness in a range from about 0.2 nm to about 5 nm.5. The triboelectric generator of claim 1 , wherein the triboelectric material layer comprises a polymer that has a greater amount of negative charges than the first electrode when there is a friction between the triboelectric material layer and the first electrode.6. The triboelectric generator of claim 1 , wherein the self-assembled monolayer comprises a first self-assembled monolayer on the surface of the first electrode facing the triboelectric material layer and a second self-assembled monolayer on the surface of the triboelectric material layer facing the first self- ...

METAL CHALCOGENIDE FILM AND METHOD AND DEVICE FOR MANUFACTURING THE SAME

Provided are a metal chalcogenide thin film and a method and device for manufacturing the same. The metal chalcogenide thin film includes a transition metal element and a chalcogen element, and at least one of the transition metal element and the chalcogen element having a composition gradient along the surface of the metal chalcogenide thin film, the composition gradient being an in-plane composition gradient. The metal chalcogenide thin film may be prepared by using a manufacturing method including providing a transition metal precursor and a chalcogen precursor on a substrate by using a confined reaction space in such a manner that at least one of the transition metal precursor and the chalcogen precursor forms a concentration gradient according to a position on the surface of the substrate; and heat-treating the substrate. 1. A metal chalcogenide thin film comprising:a transition metal element; anda chalcogen element, wherein at least one of the transition metal element and the chalcogen element has a composition gradient along a surface of the metal chalcogenide thin film, the composition gradient being an in-plane composition gradient.2. The metal chalcogenide thin film of claim 1 , whereinthe in-plane composition gradient refers to a condition in which a composition changes continuously from an element-rich region to an element-deficient region.3. The metal chalcogenide thin film of claim 2 , whereinthe element-rich region is thicker than the element-deficient region, and the thickness of the metal chalcogenide thin film continuously decreases from the element-rich region to the element-deficient region.4. The metal chalcogenide thin film of claim 1 , wherein {'br': None, 'sub': 1-x', 'x', '2(1-y)', '2y, 'MM′XX′\u2003\u2003[Formula 1]'}, 'the metal chalcogenide thin film includes a composition represented by Formula 1wherein M and M′ are different transition metal elements, X and X′ are different chalcogen elements, 0≤x<1, and 0≤y<1, and at least one of x and ...

GRAPHENE STRUCTURE AND METHOD OF FORMING GRAPHENE STRUCTURE

Provided are a graphene structure and a method of forming the graphene structure. The graphene structure includes a substrate and graphene on a surface of the substrate. Here, a bonding region in which a material of the substrate and carbon of the graphene are covalently bonded is formed between the surface of the substrate and the graphene. 1. A graphene structure comprising:a substrate;graphene on a surface of the substrate; anda bonding region, where a material of the substrate and carbon of the graphene are covalently bonded, between the surface of the substrate and the graphene.2. The graphene structure of claim 1 , whereinthe bonding region covers a part or all of the surface of the substrate.3. The graphene structure of claim 1 , whereinthe substrate includes silicon (Si), andthe bonding region includes a silicon-carbon (Si—C) bond.4. The graphene structure of claim 1 , whereinthe graphene has a thickness of 1 nm to 2 nm.5. The graphene structure of claim 1 , whereinthe surface of the substrate has nano-sized roughness.6. A method of forming a graphene structure claim 1 , the method comprising:forming a bonding site inducing a covalent bond with carbon on a surface of a substrate, the forming the bonding site including treating the surface of the substrate using a plasma having power equal to or greater than 600 W; anddirectly growing a graphene on the surface of the substrate via a plasma enhanced chemical vapor deposition (PECVD) process,the directly growing the graphene including forming a bonding region, in which a material of the substrate and carbon of the graphene are covalently bonded, between the surface of the substrate and the graphene.7. The method of claim 6 , whereinthe directly growing the graphene includes forming the bonding region to cover a part or all of the surface of the substrate.8. The method of claim 6 , whereinthe substrate includes silicon (Si), andthe bonding region includes a silicon-carbon (Si—C) bond.9. The method of claim 6 , ...

Methods and apparatuses for forming graphene

A method of forming graphene includes providing, in a reaction chamber, a non-catalyst substrate at least partially including a material that does not catalyze growth of graphene, and directly growing graphene on a surface of the non-catalyst substrate based on injecting a reaction gas into the reaction chamber. The reaction gas includes a carbon source having an ionization energy equal to or less than about 10.6 eV in a plasma-enhanced chemical vapor deposition (PECVD) process.

SEMICONDUCTOR MEMORY DEVICE AND APPARATUS INCLUDING THE SAME

A semiconductor memory device and a device including the same are provided. The semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate; bit line structures extending across the word lines in a second direction crossing the first direction; contact pad structures between the word lines and between the bit line structures; and spacers between the bit line structures and the contact pad structures. The spacers include a boron nitride layer. 1. A semiconductor memory device comprising:a semiconductor substrate;word lines extending in a first direction on the semiconductor substrate;bit line structures extending across the word lines, the bit line structures extending in a second direction crossing the first direction;contact pad structures between the word lines and between the bit line structures; andspacers between the bit line structures and the contact pad structures, the spacers comprising a boron nitride layer comprising at least one of at least one of amorphous material and nanocrystalline material,whereinthe bit line structures comprise a polysilicon pattern, a barrier/liner pattern, a metal pattern, and a hard mask pattern, which are sequentially stacked on the semiconductor substrate, andthe spacers overlap the polysilicon pattern, the barrier/liner pattern, and the metal pattern with respect to the first direction.2. The semiconductor memory device of claim 1 , wherein the spacers extend in the second direction along one sidewall of the bit line structures.3. The semiconductor memory device of claim 1 , wherein the spacers surround at least a part of the contact pad structures.4. The semiconductor memory device of claim 3 , wherein the spacers are in direct contact with at least a portion of the contact pad structures.5. The semiconductor memory device of claim 1 , wherein the spacers are in direct contact with at least one of the polysilicon pattern claim 1 , the barrier/liner pattern claim 1 , and the ...

Interconnect structure and electronic device including the same

Provided are an interconnect structure and an electronic device including the same. The interconnect structure may include a conductive wiring having a certain pattern, a dielectric layer on side surfaces of the conductive wiring, a capping layer on the conductive wiring, and a graphene layer on the dielectric layer. The graphene layer may include a graphene material. A ratio of carbons having sp 3 bonds to carbons having sp 2 bonds in the graphene material is 1 or less.

Method of directly growing carbon material on substrate

Provided are methods of directly growing a carbon material. The method may include a first operation and a second operation. The first operation may include adsorbing carbons onto a substrate by supplying the carbons to the substrate. The second operation may include removing unreacted carbon residues from the substrate after suspending the supplying the carbons of the first operation. The two operations may be repeated until a desired graphene is formed on the substrate. The substrate may be maintained at a temperature less than 700° C. In another embodiment, the method may include forming a carbon layer on a substrate, removing carbons that are not directly adsorbed to the substrate on the carbon layer, and repeating the two operations until desired graphene is formed on the substrate. The forming of the carbon layer includes supplying individual carbons onto the substrate by preparing the individual carbons.

Memory device using graphene as charge-trap layer and method of operating the same

Semiconductor memory device and apparatus including the same

A semiconductor memory device and a device including the same are provided. The semiconductor memory device includes word lines (WL) extending in a first direction on a semiconductor substrate; bit line structures (BL) extending across the word lines in a second direction crossing the first direction; contact pad structures (CPS) between the word lines and between the bit line structures; and spacers (131) between the bit line structures and the contact pad structures. The spacers (131) include a boron nitride layer.

Semiconductor memory device and apparatus including the same

A semiconductor memory device and a device including the same are provided. The semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate; bit line structures extending across the word lines in a second direction crossing the first direction; contact pad structures between the word lines and between the bit line structures; and spacers between the bit line structures and the contact pad structures. The spacers include a boron nitride layer.

Graphene device and electronic apparatus

A graphene device and an electronic apparatus including the same are provided. According to example embodiments, the graphene device includes a transistor including a source, a gate, and a drain, an active layer through which carriers move, and a graphene layer between the gate and the active layer. The graphene layer may be configured to function both as an electrode of the active layer and a channel layer of the transistor.

Transistor

A transistor includes an oxide semiconductor layer, a source electrode and a drain electrode disposed spaced apart from each other on the oxide semiconductor layer, a gate electrode spaced apart from the oxide semiconductor layer, a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode, and a graphene layer disposed between the gate electrode and the gate insulating layer and doped with a metal.

Wiring including graphene layer and method of manufacturing the same

Provided are a wiring including a graphene layer and a method of manufacturing the wiring. The method may include growing a graphene layer on a substrate and doping the graphene layer with a metal. The graphene layer may be grown using a plasma of a hydrocarbon at a temperature of about 200° C. to about 600° C. by plasma enhanced chemical vapor deposition (PECVD).

Method of forming transition metal dichalcogenidethin film and method of manufacturing electronic device including the same

Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: depositing a transition metal dichalcogenide thin film on a substrate; and heat-treating the deposited transition metal dichalcogenide thin film.

Interconnect structure to reduce contact resistance, electronic device including the same, and method of manufacturing the interconnect structure

An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of the rest region of the semiconductor layer, a metal layer facing the semiconductor layer, a semi-metal layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the semi-metal layer and the semiconductor and covering the first region.

Semiconductor device including metal-2 dimensional material-semiconductor junction

A semiconductor device may include a first semiconductor layer including a first semiconductor material; a metal layer facing the first semiconductor layer and having conductivity; a 2D material layer between the first semiconductor layer and the metal layer; and a second semiconductor layer between the first semiconductor layer and the 2D material layer. The second semiconductor layer may include a second semiconductor material different from the first semiconductor material. The second semiconductor layer and the 2D material layer may be in direct contact with each other. The second semiconductor material may include germanium.

Method of forming transition metal dichalcogenide thin film

Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: providing a substrate in a reaction chamber; depositing a transition metal dichalcogenide thin film on the substrate using a sputtering process that uses a transition metal precursor and a chalcogen precursor and is performed at a first temperature; and injecting the chalcogen precursor in a gas state and heat-treating the transition metal dichalcogenide thin film at a second temperature that is higher than the first temperature. The substrate may include a sapphire substrate, a silicon oxide (SiO2) substrate, a nanocrystalline graphene substrate, or a molybdenum disulfide (MoS2) substrate.

Nanocrystalline graphene and method of forming nanocrystalline graphene

Provided are nanocrystalline graphene and a method of forming the same. The nanocrystalline graphene may include a plurality of grains formed by stacking a plurality of graphene sheets and has a grain density of about 500 ea/μm 2 or higher and a root-mean-square (RMS) roughness in a range of about 0.1 or more to about 1.0 or less. When the nanocrystalline graphene has a grain density and a RMS roughness with these ranges, nanocrystalline graphene capable of covering the entirety of a large area on a substrate as a thin layer may be provided.

Method of forming transition metal dichalcogenide thin film

Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: providing a substrate in a reaction chamber; depositing a transition metal dichalcogenide thin film on the substrate using a sputtering process that uses a transition metal precursor and a chalcogen precursor and is performed at a first temperature; and injecting the chalcogen precursor in a gas state and heat-treating the transition metal dichalcogenide thin film at a second temperature that is higher than the first temperature. The substrate may include a sapphire substrate, a silicon oxide (SiO 2 ) substrate, a nanocrystalline graphene substrate, or a molybdenum disulfide (MoS 2 ) substrate.

Method of forming transition metal dichalcogenide thin film

A method of forming a transition metal dichalcogenide thin film on a substrate includes treating the substrate with a metal organic material and providing a transition metal precursor and a chalcogen precursor around the substrate to synthesize transition metal dichalcogenide on the substrate. The transition metal precursor may include a transition metal element and the chalcogen precursor may include a chalcogen element.

Metal chalcogenide film and method and device for manufacturing the same

Provided are a metal chalcogenide thin film and a method and device for manufacturing the same. The metal chalcogenide thin film includes a transition metal element and a chalcogen element, and at least one of the transition metal element and the chalcogen element having a composition gradient along the surface of the metal chalcogenide thin film, the composition gradient being an in-plane composition gradient. The metal chalcogenide thin film may be prepared by using a manufacturing method including providing a transition metal precursor and a chalcogen precursor on a substrate by using a confined reaction space in such a manner that at least one of the transition metal precursor and the chalcogen precursor forms a concentration gradient according to a position on the surface of the substrate; and heat-treating the substrate.

Interconnect structure and electronic device employing the same

An interconnect structure and an electronic device including the interconnect structure are disclosed. The interconnect structure may include a metal interconnect having a bottom surface and two opposite side surfaces surrounded by a dielectric layer, a graphene layer on the metal interconnect, and a metal bonding layer providing interface adhesion between the metal interconnect and the graphene layer. The metal bonding layer includes a metal material.

Method of growing graphene selectively

A method of selectively growing graphene includes forming an ion implantation region and an ion non-implantation region by implanting ions locally into a substrate; and selectively growing graphene in the ion implantation region or the ion non-implantation region.

Vertical nonvolatile memory device including memory cell strings

A vertical nonvolatile memory device may include a channel layer extending in a first direction; a plurality of gate electrodes and a plurality of spacers each extending in a second direction crossing the first direction, the plurality of gate electrodes and the plurality of spacers being alternately arranged with each other in the first direction; and a gate insulating layer extending in the first direction between the channel layer and the plurality of gate electrodes. Each of the plurality of gate electrodes may include a metal-doped graphene.

Thin film structure and electronic device including two-dimensional material

Provided is a thin film structure (100) including a substrate (110), a metal layer (170) on the substrate and spaced apart from the substrate, and a two-dimensional material layer between the substrate and the metal layer. The two-dimensional material layer may be configured to limit and/or block an electron transfer between the substrate and the metal layer. A resistivity of a metal layer on the two-dimensional material layer may be lowered by the two-dimensional material layer.

Complex of heterogeneous two-dimensional materials and method of manufacturing the same

Provided are a complex of heterogeneous two-dimensional materials and a method of manufacturing the same. The complex of heterogeneous two-dimensional materials may include a substrate; a first two-dimensional material layer on the substrate and having a two-dimensional crystal structure; and a second two-dimensional material layer between the substrate and the first two-dimensional material layer. The second two-dimensional material layer have a two-dimensional crystal structure in which a plurality of phosphorus atoms are covalently bonded to each other.

Semiconductor device including graphene

A semiconductor device may include a substrate including a source region and a drain region in a trench, a gate insulating layer in the trench, and a gate electrode in the trench. The gate electrode may include a lower filling portion and an upper filling portion surrounded by the gate insulating layer. The lower filling portion may include a first conductive layer surrounded by the gate insulating layer and may fill a lower region of the trench. The upper filling portion may include a second conductive layer surrounded by the gate insulating layer and may fill an upper region of the trench. The first conductive layer may include graphene doped with metal.

Semiconductor device including two-dimensional material and method of fabricating the same

A semiconductor device may include a first two-dimensional (2D) material layer, a second 2D material layer, a first electrode, a second electrode, a third electrode, a first gate electrode. and a second gate electrode. A Fermi-level may be pinned on an interfacial surface between the first 2D material layer and the first electrode. The Fermi-level may be depinned on an interfacial surface between the second 2D material layer and the first electrode.

Semiconductor device including metal-2 dimensional material-semiconductor junction

A semiconductor device may include a first semiconductor layer including a first semiconductor material; a metal layer facing the first semiconductor layer and having conductivity; a 2D material layer between the first semiconductor layer and the metal layer; and a second semiconductor layer between the first semiconductor layer and the 2D material layer. The second semiconductor layer may include a second semiconductor material different from the first semiconductor material. The second semiconductor layer and the 2D material layer may be in direct contact with each other. The second semiconductor material may include germanium.

Methods of forming graphene and graphene manufacturing apparatuses

A graphene manufacturing apparatus includes a reaction chamber a substrate supporter configured to structurally support a substrate inside the reaction chamber; a plasma generator configured to generate a plasma inside the reaction chamber; a first gas supply configured to supply an inert gas into the reaction chamber at a first height from an upper surface of the substrate supporter in a height direction of the reaction chamber; a second gas supply configured to supply a carbon source into the reaction chamber at a second height from the upper surface of the substrate supporter in the height direction of the reaction chamber; and a third gas supply configured to supply a reducing gas into the reaction chamber, wherein the first to third gas supply units are disposed at different heights at a third height from the upper surface of the substrate supporter in the height direction of the reaction chamber.

Method of calculating thickness of graphene layer by using xps

Semiconductor element, electronic system including the semiconductor element, and method of fabricating the semiconductor element

A semiconductor element may include a substrate including source and drain regions formed in the substrate apart from each other by a trench, a gate insulating layer covering a bottom surface and a sidewall of the trench, a gate electrode including lower and upper buried portions. The lower buried portion may be in the trench with the gate insulating layer therearound and fill a lower region of the trench. The upper buried portion may be on the lower buried portion with the gate insulating layer therearound and fill an upper region of the trench. The upper buried portion may include a two-dimensional material layer in the trench on an upper surface of the first conductive layer and an upper region of the sidewall of the gate insulating layer, and a second conductive layer in the upper region of the trench and surrounded by the two-dimensional material layer.

Method of calculating thickness of graphene layer and method of measuring content of silicon carbide by using XPS

A method of calculating a thickness of a graphene layer and a method of measuring a content of silicon carbide, by using X-ray photoelectron spectroscopy (XPS), are provided. The method of calculating the thickness of the graphene layer, which is directly grown on a silicon substrate, includes measuring the thickness of the graphene layer directly grown on the silicon substrate, by using a ratio between a signal intensity of a photoelectron beam emitted from the graphene layer and a signal intensity of a photoelectron beam emitted from the silicon substrate.

Conductive structure and method of controlling work function of metal

Provided are a conductive structure and a method of controlling a work function of metal. The conductive structure includes a conductive material layer including metal and a work function control layer for controlling a work function of the conductive structure by being bonded to the conductive material layer. The work function control layer includes a two-dimensional material with a defect.

Nanocrystalline graphene and method of forming nanocrystalline graphene

Provided are nanocrystalline graphene and a method of forming the same. The nanocrystalline graphene may include a plurality of grains formed by stacking a plurality of graphene sheets and has a grain density of about 500 ea/µm² or higher and a root-mean-square (RMS) roughness in a range of about 0.1 or more to about 1.0 or less. When the nanocrystalline graphene has a grain density and a RMS roughness with these ranges, nanocrystalline graphene capable of covering the entirety of a large area on a substrate as a thin layer may be provided.

Layer structure including metal layer and carbon layer, method of manufacturing the layer structure, electronic device including the layer structure, and electronic apparatus including the electronic device

Disclosed are a layer structure including a metal layer and a carbon layer, a manufacturing method the layer structure, an electronic device including the layer structure, and an electronic apparatus including the electronic device. The layer structure according to an embodiment includes an insulating layer on one surface of a semiconductor layer, a first metal layer facing the semiconductor layer with the insulating layer therebetween, a conductive first carbon layer arranged between the insulating layer and the first metal layer, the conductive first carbon layer being in contact with a first surface of the first metal layer. The first metal layer may be provided above or below the semiconductor layer. The first carbon layer may include a graphene layer. The first carbon layer may extend to another surface of the first metal layer.

Graphene structure and method of forming graphene structure

Provided are a graphene structure and a method of forming the graphene structure. The graphene structure includes a substrate and graphene on a surface of the substrate. Here, a bonding region in which a material of the substrate and carbon of the graphene are covalently bonded is formed between the surface of the substrate and the graphene.

グラフェンの形成方法

【課題】グラフェンの形成方法を提供する。【解決手段】本発明は、グラフェンの形成方法に関し、該グラフェンの形成方法は、反応チャンバ内に設けられた基板にバイアスを印加した状態で、プラズマを利用し、基板の表面を処理する段階と、基板の表面に、プラズマ化学気相蒸着（ＰＥＣＶＤ）工程により、グラフェンを成長させて形成する段階と、を含む。【選択図】図３

Layer structures including two-dimensional channel layer, methods of manufacturing the same, electronic devices including 2d channel layer, and electronic apparatuses including electronic device

A layer structure including a two-dimensional (2D) channel layer, a method of manufacturing a two-dimensional (2D) channel layer, an electronic device including the layer structure, and an electronic apparatus including the layer structure are disclosed. The layer structure may include a first substrate, a second substrate surrounded by the first substrate, and a 2D channel layer on the second substrate. An interfacial energy of the second substrate may be less than an interfacial energy of the first substrate. The method of manufacturing a 2D channel layer may include forming a second substrate to be surrounded by a first substrate, forming a precursor layer for forming a 2D channel on any one of the first and second substrates, and transforming the precursor layer into a liquid precursor layer. The interfacial energy of the second substrate may be less than the interfacial energy of the first substrate.

摩擦電気発電機

【課題】摩擦電気発電機を提供する。【解決手段】摺動によって互いに断続的に接触する第１帯電体及び第２帯電体を含む摩擦電気発電機であり、該摩擦電気発電機は、電荷保存所と第２帯電体とを断続的に連結する接地ユニットを含み、該接地ユニットは、第２帯電体の電位を変更させることにより、摩擦電気発電機の電極間に流れる電流の量を増幅させる。【選択図】図１

Complex of heterogeneous two-dimensional materials and method of manufacturing the same

Provided are a complex of heterogeneous two-dimensional materials and a method of manufacturing the same. The complex of heterogeneous two-dimensional materials may include a substrate; a first two-dimensional material layer on the substrate and having a two-dimensional crystal structure; and a second two-dimensional material layer between the substrate and the first two-dimensional material layer. The second two-dimensional material layer have a two-dimensional crystal structure in which a plurality of phosphorus atoms are covalently bonded to each other.

Interconnect structure, electronic device including the same, and method of manufacturing interconnect structure

Disclosed are an interconnect structure, an electronic device including the same, and a method of manufacturing the interconnect structure. The interconnect structure includes a dielectric layer; a conductive interconnect on the dielectric layer; and a graphene cap layer on the conductive interconnect. The graphene cap layer contains graphene quantum dots, has a carbon content of 80 at % or more, and has an oxygen content of 15 at % or less.

Semiconductor device including two-dimensional material and electronic device including the semiconductor device

Provided are a semiconductor device including a two-dimensional (2D) material and an electronic device including the semiconductor device. The semiconductor device may include a channel layer including a two-dimensional (2D) semiconductor material, a channel portion, and an extension portion on both sides of the channel portion, a source electrode and a drain electrode respectively on both sides of the channel layer, a gate electrode surrounding the channel portion, a first insulating layer between the channel portion of the channel layer and the gate electrode, and a second insulating layer on the extension portion of the channel layer. The second insulating layer may include a different material than a material of the first insulating layer. The second insulating layer may include a n-type dopant or p-type dopant. A dopant in the extension portion may be the same as a dopant in the second insulating layer.

Method of calculating thickness of graphene layer and method of measuring content of silicon carbide by using xps

A method of calculating a thickness of a graphene layer (120) and a method of measuring a content of silicon carbide, by using X-ray photoelectron spectroscopy (XPS), are provided. The method of calculating the thickness of the graphene layer (120), which is directly grown on a silicon substrate (110), includes measuring the thickness of the graphene layer (120) directly grown on the silicon substrate (110), by using a ratio between a signal intensity of a photoelectron beam emitted from the graphene layer (120) and a signal intensity of a photoelectron beam emitted from the silicon substrate (110).

Method of calculating thickness of graphene layer and method of measuring content of silicon carbide by using xps

A method of calculating a thickness of a graphene layer and a method of measuring a content of silicon carbide, by using X-ray photoelectron spectroscopy (XPS), are provided. The method of calculating the thickness of the graphene layer, which is directly grown on a silicon substrate, includes measuring the thickness of the graphene layer directly grown on the silicon substrate, by using a ratio between a signal intensity of a photoelectron beam emitted from the graphene layer and a signal intensity of a photoelectron beam emitted from the silicon substrate.

Ｘ線光電子分光法を利用した、グラフェン層の厚さの測定方法及びシリコンカーバイドの含量の測定方法

【課題】Ｘ線光電子分光法を利用した、グラフェン層の厚さの測定方法及びシリコンカーバイドの含量の測定方法を提供する。【解決手段】シリコン基板に直接成長したグラフェン層の厚さを測定する方法において、グラフェン層から放出された光電子ビームの信号強度と、シリコン基板から放出された光電子ビームの信号強度との割合を利用して、シリコン基板に直接成長したグラフェン層の厚さを測定する。【選択図】図４Ａ

Tunneling field-effect transistor including graphene channel

Semiconductor device including two-dimensional (2d) material

A semiconductor device may include a two-dimensional (2D) material layer having semiconductor characteristics, and a source electrode, a drain electrode, and a gate electrode spaced apart from one another on the 2D material layer. At least one of the source electrode and the drain electrode may be in contact with the 2D material layer and may include an alloy layer that may be amorphous.

Stacked structure including two-dimensional material and method of fabricating the stacked structure

A stacked structure may include a first material layer, a two-dimensional material layer on the first material layer, and a second material layer on the two-dimensional material layer. The two-dimensional material layer may include a plurality of holes that each expose a portion of the first material layer. The second material layer may be coupled to the first material layer through the plurality of holes.

Transistor, method of manufacturing the transistor, electronic device including transistor, and electronic apparatus including the transistor

Provided are a field effect transistor, a method of manufacturing the field effect transistor, and an electronic device and an electronic apparatus each including the field effect transistor. The field effect transistor includes a channel layer disposed on a substrate, a high-k gate insulating layer disposed on the channel layer, a first composite electrode layer connected to a first side of the channel layer, a second composite electrode layer connected to a second side of the channel layer, and a gate electrode layer disposed on the gate insulating layer. At least one of the first and second composite electrode layers includes a contact resistance reducing layer in contact with the channel layer and a conductive layer in contact with the contact resistance reducing layer. The conductive layer is spaced apart from the channel layer.

Semiconductor device and method of manufacturing the same

Disclosed are a semiconductor device, a method of manufacturing the same, and an electronic element and an electronic apparatus each including the semiconductor device. The semiconductor device may include a substrate, a channel layer on the substrate, a first electrode and a second electrode on two opposite ends of the channel layer, respectively, and spaced apart from each other, a gate electrode on the channel layer and spaced apart from the first electrode and the second electrode, a gate dielectric material provided between the channel layer and the gate electrode, and a chalcogen compound layer being at least one of between the gate dielectric material and the channel layer, between the first electrode and the channel layer, and between the second electrode and the channel layer.

Electronic device including two-dimensional material and method of fabricating the same

Disclosed are an electronic device including a two-dimensional material, and a method of fabricating the electronic device. The electronic device may include a first metal layer including a transition metal, a second metal layer on the first metal layer and including gold (Au), and a two-dimensional material layer between the first metal layer and the second metal layer. The two-dimensional material layer may include a transition metal dichalcogenide (TMD). The two-dimensional material layer may be formed as a chalcogen element diffuses into the second metal layer and reacts with the transition metal of the first metal layer adjacent to the second metal layer.

Graphene devices and methods of fabricating the same

Semiconductor device comprising two-dimensional material and method of manufacturing the semiconductor device

A semiconductor device including a two-dimensional material and a method of manufacturing the same are provided. The semiconductor device may include a first two-dimensional material layer including a first two-dimensional semiconductor material; a plurality of second two-dimensional material layers connected to the first two-dimensional material layer, each having a thickness greater than that of the first two-dimensional material layer, and including a doped two-dimensional semiconductor material; and a plurality of electrodes on the plurality of second two-dimensional material layers.

Semiconductor device including multi-layer gate insulating layer and electronic device including the same

A semiconductor device may include a multi-layer gate dielectric layer and an electronic apparatus including the semiconductor device. The semiconductor device may include a channel layer including a two-dimensional semiconductor material, a gate dielectric layer on a first area of the channel layer, a gate electrode on the gate dielectric layer, and source and drain electrodes in a second area of the channel layer. The gate dielectric layer may include a high-k dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer may be between the high-k dielectric layer and the channel layer. A dielectric constant of the intermediate dielectric layer may be less than a dielectric constant of the high-k dielectric layer.

Semiconductor device including two-dimensional material and electronic apparatus including the semiconductor device

A semiconductor device may include a channel layer including a two-dimensional (2D) semiconductor material, a gate insulating layer on the channel layer, a gate electrode on the gate insulating layer, and a first conductive layer and a second conductive layer respectively on opposite sides of the channel layer. Each of the first and second conductive layers may include metal boride.

Semiconductor device and method of manufacturing the same

Disclosed are a semiconductor device, a method of manufacturing the same, and an electronic element and an electronic apparatus each including the semiconductor device. The semiconductor device may include a substrate, a channel layer on the substrate, a first electrode and a second electrode on two opposite ends of the channel layer, respectively, and spaced apart from each other, a gate electrode on the channel layer and spaced apart from the first electrode and the second electrode, a gate dielectric material provided between the channel layer and the gate electrode, and a chalcogen compound layer being at least one of between the gate dielectric material and the channel layer, between the first electrode and the channel layer, and between the second electrode and the channel layer.

Semiconductor device including two-dimensional material and method of manufacturing the same

A semiconductor device may include a two-dimensional (2D) material layer, a source electrode and a drain electrode spaced apart from each other on the 2D material layer, a gate insulating layer and a gate electrode on the 2D material layer between the source electrode and the drain electrode, and graphene layers on both sides of the gate insulating layer. The 2D material layer may include a 2D semiconductor material having a polycrystalline structure. The 2D material layer may include a sheet member and a protrusion. The sheet member may extend along one plane. The protrusion may extend in one direction perpendicular to the one plane. The graphene layer may cover a part of the sheet member and the protrusion.

Semiconductor device including two-dimensional material and method of manufacturing the same

A semiconductor device may include a two-dimensional material layer, one or more metal islands on the two-dimensional material layer, and a metal layer covering the metal islands on the two-dimensional material layer. The semiconductor device may be manufactured by a method including forming metal islands on a two-dimensional material layer using a redox method and forming a metal layer covering the metal islands on the two-dimensional material layer.

Semiconductor device including two-dimensional material and electronic apparatus including the semiconductor device

A semiconductor device may include a channel layer including a two-dimensional (2D) semiconductor material, a gate insulating layer on a center portion of the channel layer, a gate electrode on the gate insulating layer, and a first conductive layer and a second conductive layer respectively contacting opposite sides of the channel layer. Each of the first and second conductive layers may include metal boride.

Interconnect structure and electronic device including the same

An interconnect structure may include a dielectric layer including a trench, a conductive wiring including graphene filling an inside of the trench, and a liner layer in contact with at least one surface of the conductive wiring and including a metal.

Layer structures including carbon-based material, methods of manufacturing the layer structures, electronic devices including the layer structures, and electronic apparatuses including the electronic devices

Provided are a layer structure including a carbon-based material, a method of manufacturing the layer structure, an electronic device including the layer structure, and an electronic apparatus including the electronic device. The layer structure may include a lower layer, an ion implantation layer in the lower layer, and a carbon-based material layer on the ion implantation layer, wherein the ion implantation layer includes carbon. The ion implantation layer may include a trench, and the carbon-based material layer may be provided in the trench. The carbon-based material layer may be formed to coat an inner surface of the trench. The carbon-based material layer may fill at least a portion of the trench. The ion implantation concentration of the ion implantation layer may be uniform as a whole. The ion implantation layer may have an ion implantation concentration gradient in a given direction.

Transistor

A transistor includes an oxide semiconductor layer, a source electrode and a drain electrode disposed spaced apart from each other on the oxide semiconductor layer, a gate electrode spaced apart from the oxide semiconductor layer, a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode, and a graphene layer disposed between the gate electrode and the gate insulating layer and doped with a metal.

Transistor

A transistor includes an oxide semiconductor layer, a source electrode and a drain electrode disposed spaced apart from each other on the oxide semiconductor layer, a gate electrode spaced apart from the oxide semiconductor layer, a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode, and a graphene layer disposed between the gate electrode and the gate insulating layer and doped with a metal.

Interconnect structure and electronic device including the same

An interconnect structure may include a first dielectric layer including a trench, a first conductive layer in the trench and including a plurality of first graphene layers stacked in a direction from an inner surface of the trench toward a center of the trench, a second dielectric layer on the first dielectric layer and including a through hole extending to the trench, and a second conductive layer in the through hole.