DIGITALLY CONTROLLED OSCILLATOR

Methods and systems for a digitally controlled oscillator may comprise, for example, an all-digital all digital phase locked loop (ADPLL) for generating an output clock signal from a reference clock signal, the ADPLL comprising a thermometer pulse coder comprising a plurality of frequency control word signal lines. the thermometer pulse coder may be configured to generate a frequency control word from a binary encoded frequency control word, where the frequency control word may comprise hermometer coded signals and a pulse modulated dither signal, and may select a frequency control word signal line over which to transmit the pulse modulated dither signal and may transmit the thermometer coded signals over another of frequency control word signal lines. A digitally controlled oscillator may be configured to receive a frequency control word and generate an output clock signal at a frequency determined using at least the frequency control word. 1. An all-digital phase locked loop (ADPLL) for generating an output clock signal from a reference clock signal , the ADPLL comprising: generate a frequency control word from a binary encoded frequency control word, where the frequency control word comprises a plurality of thermometer coded signals and a pulse modulated dither signal; and', 'select one of the plurality of frequency control word signal lines and transmit the pulse modulated dither signal over the selected frequency control word signal line, and transmit the thermometer coded signals over another of the frequency control word signal lines;, 'a thermometer pulse coder comprising a plurality of frequency control word signal lines, where the thermometer pulse coder is configured toa digitally controlled oscillator configured to receive a frequency control word comprising a combined thermometer and pulse modulated signal via the plurality of frequency control word signal lines and generate an output clock signal at a frequency determined using at least the frequency ...

Digitally controlled oscillator

Methods and systems for a digitally controlled oscillator may comprise, for example, an all-digital all digital phase locked loop (ADPLL) for generating an output clock signal from a reference clock signal, the ADPLL comprising a thermometer pulse coder comprising a plurality of frequency control word signal lines. the thermometer pulse coder may be configured to generate a frequency control word from a binary encoded frequency control word, where the frequency control word may comprise hermometer coded signals and a pulse modulated dither signal, and may select a frequency control word signal line over which to transmit the pulse modulated dither signal and may transmit the thermometer coded signals over another of frequency control word signal lines. A digitally controlled oscillator may be configured to receive a frequency control word and generate an output clock signal at a frequency determined using at least the frequency control word.

PHASE INTERPOLATOR BASED TRANSMISSION CLOCK CONTROL

A system and method is provided for phase interpolator based transmission clock control. The system includes a transmitter having a phase interpolator coupled to a master timing generator and a transmission module. The phase interpolator is also coupled to a receiver interpolator control module and/or an external interpolator control module. When the system is operating in repeat mode, the transmitter phase interpolator receives a control signal from a receiver interpolator control module. The transmitter phase interpolator uses the signal to synchronize the transmission clock to the sampling clock. When the system is operating in test mode, a user defines a transmission data profile in an external interpolator control module. The external interpolator control module generates a control signal based on the profile. The transmitter phase interpolator uses the signal to generate a transmission clock that is used by the transmission module to generate a data stream having the desired profile. 1. A communication system comprising: a sampling module configured to generate a sampled data stream based on a received data stream;', 'an interpolator control module configured to determine an offset between an optimal clock signal and a sampling signal used to generate the sampled data stream, and to generate an interpolator control signal based on the offset; and, 'at least one receiver including,'}a receiver phase interpolator configured to adjust the sampling signal based on the interpolator control signal and a set of reference signals generated by a master timing generator.2. The communication system of claim 1 , further comprising: 'a transmitter phase interpolator configured to generate a transmission clock signal based on the interpolator control signal and the set of reference signals, wherein', 'at least one transmitter including,'}the receiver phase interpolator adjusts the sampling signal to be synchronized to the transmission clock signal.3. The communication ...

Programmable Management IO Pads for an Integrated Circuit

A method for performing Iddq testing including receiving an Iddq message and executing the Iddq message to measure current leakage. 1. A method for performing Iddq testing , comprising:receiving, at a logic circuit coupled to a programmable pad, an Iddq message;receiving, at a controller, the Iddq message, the controller being one of an input controller and an output controller; andexecuting, at the logic circuit, the Iddq message to measure current leakage.2. A system for performing Iddq testing , comprising:a programmable pad;a logic circuit coupled to the programmable pad and configured to receive an Iddq message and to execute the Iddq message to measure current leakage; anda controller configured to receive the Iddq message, the controller being one of an input controller and an output controller. This application is a divisional of U.S. application Ser. No. 12/416,641, filed Apr. 1, 2009, which is a divisional of U.S. application Ser. No. 10/694,730, filed Oct. 29, 2003, which claims the benefit of U.S. Provisional Application No. 60/421,780, filed Oct. 29, 2002, the contents of all of which are herein incorporated by reference in their entireties.1. Field of the InventionThe present invention generally relates to serializer/deserializer integrated circuits with multiple high-speed data ports, and more particularly to a serializer and deserializer chip that includes the functionality to switch between multiple high-speed data ports.2. Related ArtHigh-speed data links transmit data from one location to another over transmission lines. These data links can include serializer data links (i.e., SERDES) that receive data in a parallel format and convert the data to a serial format for high-speed transmission, and deserializer data links (i.e., SERDES) that receive data in a serial format and convert the data to a parallel format. SERDES data links can be used for communicating data through a backplane in a communications system (e.g., Tyco Backplane 16 or 30-inch ...

Methods and Systems for Adaptive Receiver Equalization

Methods and systems for adaptively equalizing an analog information signal for a signal path, including sampling the analog information signal, thereby generating analog samples, and performing an equalizing process on the analog samples, wherein the equalizing includes processing an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples to produce equalized analog samples. 1. A method for adaptively equalizing an analog information signal for a signal path , comprising:sampling the analog information signal to provide analog samples; andperforming an equalizing process on the analog samples, wherein the equalizing includes processing an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples to produce equalized analog samples.2. The method according to claim 1 , further comprising:quantizing the equalized analog samples of the analog information signal.3. The method according to claim 2 , wherein the performing the equalizing process comprises:comparing a multi-level representation of the equalized samples with the quantized equalized samples;performing a least-means-squared operation on results of the comparison;adjusting an equalization coefficient with a result of the least-means-squared operation; andrepeating the comparing the multi-level representation, the performing the least-means-squared operation, and the adjusting the equalizing coefficient.4. The method according to claim 3 , wherein the comparing the multi-level representation claim 3 , the performing the least-means-squared operation claim 3 , and the adjusting the equalizing coefficient are performed at a sub-sample rate relative to a sampling associated with the sampling the analog information signal.5. The method according to claim 3 , wherein the comparing the multi-level representation claim 3 , the performing the least-means-squared operation claim 3 , and the adjusting the ...

High-Speed Serial Data Transceiver and Related Methods

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Methods and Systems for Adaptive Receiver Equalization

Methods and systems adaptively equalizing an analog information signal, the method including sampling the analog information signal to provide analog samples including post-transition samples and steady-state samples, and equalizing the analog samples to produce equalized analog samples. The equalizing includes determining a difference between an average post-transition amplitude associated with at least one of the post-transition samples and an average steady-state amplitude associated with at least one of the steady-state samples, and adjusting an equalization coefficient to adjust the difference between the average post-transition amplitude and the average steady-state amplitude. 1. A method for adaptively equalizing an analog information signal , the method comprising:sampling the analog information signal to provide analog samples including post-transition samples and steady-state samples; and determining a difference between an average post-transition amplitude associated with at least one of the post-transition samples and an average steady-state amplitude associated with at least one of the steady-state samples; and', 'adjusting an equalization coefficient to adjust the difference between the average post-transition amplitude and the average steady-state amplitude., 'equalizing the analog samples to produce equalized analog samples, the equalizing including,'}2. The method of claim 1 , further comprising:integrating the post-transition samples, the average post-transition amplitude being associated with integrated post-transition samples; andintegrating the steady-state samples, the average steady-state amplitude being associated with integrated steady-state samples.3. The method of claim 1 , further comprising:accumulating the post-transition samples, the average post-transition amplitude being associated with accumulated post-transition samples; andaccumulating the steady-state samples, the average steady-state amplitude being associated with accumulated ...

Digitally Controlled Oscillator with Thermometer Sigma Delta Encoded Frequency Control Word

Systems and methods for generating a thermometer sigma delta encoded frequency control word for controlling a digitally controlled oscillator in accordance with embodiments of the invention are disclosed. In one embodiment, an all digital phase locked loop for generating an output clock signal includes a thermometer pulse coder configured to generate a frequency control word (FCW) that includes thermometer coded signals and a pulse modulated dither signal, and transmit the pulse modulated dither signal over a selected FCW signal line and transmit the thermometer coded signals over other FCW signal lines, and a digitally controlled oscillator to receive a FCW comprising a combined thermometer and pulse modulated signal and generate an output clock signal. 1. An all digital phase locked loop (ADPLL) for generating an output clock signal from a reference clock signal , the ADPLL comprising:a thermometer pulse coder including a plurality of frequency control word signal lines, where the thermometer pulse coder is configured to:generate a frequency control word from a binary encoded frequency control word, where the frequency control word includes a plurality of thermometer coded signals and a pulse modulated dither signal; andselect one of the plurality of frequency control word signal lines and transmit the pulse modulated dither signal over the selected frequency control word signal line and transmit the thermometer coded signals over a plurality of the other frequency control word signal lines;a digitally controlled oscillator configured to receive a frequency control word comprising a combined thermometer and pulse modulated signal via the plurality of frequency control world signal lines and generate an output clock signal at a frequency determined using at least the frequency control word;a feedback divider configured to receive the output clock signal from the digitally controlled oscillator and generate a feedback signal; anda phase detector configured to ...

Multi-rate mac to phy interface

A method and system for a multi-rate Media Access Control layer (MAC) to Physical layer (PHY) interface is provided. The method to provide a multi-rate Media Access Control layer (MAC) interface comprises receiving a first set of signals, sampling the first set of signals to determine a type of interface to be used to transmit or receive the first set of signals or a subset of the first set of signals, generating a select signal indicating type of interface to be used based on the sampling step and transmitting the first set of signals or a subset of the first set of signals using the interface indicated by the select signal. The method to provide a multi-rate Physical layer (PHY) interface comprises receiving a select signal from a Physical layer (PHY) layer indicating data rate of a first set of signals, selecting a first interface and turning off the second interface if the select signal indicates the first interface is to be used, selecting the second interface and turning off the first interface if the select signal indicates the second interface is to be used and transmitting the first set of signals using the second interface or a subset of the first set of signals using the first interface based on the select signal.

Phase interpolator device and method

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

SENDING AND RECEIVING SYSTEMS AND RELATED METHODS FOR SERIAL HIGH-SPEED DATA

Programmable management IO pads for an integrated circuit

A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.

Programmable Management IO Pads for an Integrated Circuit

A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.