Randomized value generation

A data processing apparatus is provided for producing a randomized value. A cell in the data processing apparatus comprises a dielectric oxide layer and stress voltage circuitry is configured to apply a stress voltage across the dielectric oxide layer of the cell to cause an oxide breakdown process to occur. Oxide breakdown detection circuitry is configured to determine a current extent of the oxide breakdown process by measuring a response of the dielectric oxide layer to the stress voltage and randomized value determination circuitry is configured to determine a randomized value in dependence on the current extent of the oxide breakdown process. 1. A data processing apparatus comprising:a cell comprising a dielectric oxide layer;stress voltage circuitry configured to apply a stress voltage across said dielectric oxide layer of said cell to cause an oxide breakdown process to occur;oxide breakdown detection circuitry configured to determine a current extent of said oxide breakdown process by measuring a response of said dielectric oxide layer to said stress voltage; andrandomized value determination circuitry configured to determine a randomized value in dependence on said current extent of said oxide breakdown process.2. The data processing apparatus as claimed in claim 1 , wherein said randomized value determination circuitry is configured to determine said randomized value in dependence on a time period measurement of a time period between application of said stress voltage and determination by said oxide breakdown detection circuitry of occurrence of an oxide breakdown event claim 1 , said oxide breakdown event corresponding to a predetermined extent of said oxide breakdown process.3. The data processing apparatus as claimed in claim 2 , wherein said randomized value determination circuitry is configured to determine said randomized value in dependence on a transformed version of said time period measurement.4. The data processing apparatus as claimed in claim ...

FLOATING-GATE TRANSISTOR ARRAY FOR PERFORMING WEIGHTED SUM COMPUTATION

A weighted sum is a key computation for many neural networks and other machine learning algorithms. Integrated circuit designs that perform a weighted sum are presented. Weights are stored as threshold voltages in an array of flash transistors. By putting the circuits into a well-defined voltage state, the transistors that hold one set of weights will pass current equal to the desired sum. The current flowing through a given transistor is unaffected by operation of remaining transistors in the circuit. 1. A weighted sum system , comprising:a plurality of floating-gate transistors interconnected and arranged into subsets of transistors, wherein, for each subset of transistors, one of a source terminal or a drain terminal for each floating-gate transistor in a subset of transistors is electrically connected together at a select node and the other of the source terminal and the drain terminal for each floating-gate transistor in a subset of transistors is electrically connected to one of a plurality of output nodes, wherein the threshold voltage of the floating-gate transistors varies amongst the plurality of floating-gate transistors and each floating-gate transistor in the plurality of floating-gate transistors passes a current having a value that is a function of its gate voltage, its threshold voltage, and a voltage between its source terminal and its drain terminal such that current flowing through a given floating-gate transistor is unaffected by operation of remainder of the floating-gate transistors in the plurality of floating-gate transistors;a control circuit electrically connected to the select node for each subset of transistors and operates to selectively activate a given subset of floating-gate transistors in the plurality of floating-gate transistors;an input circuit electrically connected to each floating-gate transistor and operates to activate one or more floating-gate transistors in the given subset of floating-gate transistors; andan output circuit ...

INTRAOCULAR PRESSURE SENSOR

An intraocular pressure sensor is presented that achieve very low power consumption. The intraocular pressure sensor takes the form of an implantable assembly configured to be implanted in an eye of a subject. Specifically, the implantable assembly is comprised of a capsular tension ring attached to a flexible printed circuit board. The flexible printed circuit board includes a cutout that is sized to encircle the pupil of the eye and is C shaped. One or more electrical components are also mounted onto the flexible printed circuit board. One such component is a voltage reference generator that is implemented by a circuit which provides inherently low process variation and low power consumption. 1. An intraocular pressure sensor , comprising:an implantable assembly configured to be implanted in an eye of a subject;a pressure sensing element attached to the implantable assembly and operable to output a measureable value, wherein the measureable value changes in response to pressure applied to the pressure sensing element;a controller interfaced with the pressure sensing element and configured to receive the output from the pressure sensing element;a voltage reference generator attached to the implantable assembly and operable to generate a voltage that drives the controller, wherein the voltage reference generator includes a first metal-oxide semiconductor field-effect transistor (MOSFET) and a second MOSFET in a stacked arrangement, such that a body terminal of the first MOSFET is biased with a voltage that is different than voltage at a source terminal of the first MOSFET and voltage at a drain terminal of the first MOSFET; anda voltage regulator attached to the implantable assembly and interconnected between the voltage reference generator and the controller.2. The intraocular pressure sensor of wherein an implantable assembly includes a capsular tension ring attached to a flexible printed circuit board.3. The intraocular pressure sensor of wherein the pressure ...

ENVIRONMENTAL SENSOR

An environmental sensor implementing a sleep mode timer with an oscillator circuit suitable for low power applications is presented. The oscillator circuit includes a plurality of timer stages cascaded in series with each other. Each timer circuit includes a plurality of transistors and operates to output two voltages with opposite polarities, such that the polarities of the two voltages oscillate periodically based on leakage current in the plurality of transistors. Each timer circuit further includes one or more tuning transistors that operate to adjust a frequency at which the polarities of the voltages oscillate. A complementary-to-absolute temperature (“CTAT”) voltage generator is configured to receive a regulated voltage and supply a bias voltage to the one or more tuning transistors in each of the plurality of timer circuits, where the CTAT voltage generator adjusts the bias voltage linearly and inversely with changes in temperature. 1. An oscillator circuit , comprising:a plurality of timer circuits cascaded in series with each other, wherein each timer circuit is comprised of a plurality of transistors and operates to output two voltages with opposite polarities, such that the polarities of the two voltages oscillate periodically based on leakage current in the plurality of transistors;wherein each timer circuit further includes one or more tuning transistors that operate to adjust a frequency at which the polarities of the two voltages oscillate; anda complementary-to-absolute temperature (“CTAT”) voltage generator configured to receive a regulated voltage and supply a bias voltage to the one or more tuning transistors in each of the plurality of timer circuits, where the CTAT voltage generator adjusts the bias voltage linearly and inversely with changes in temperature.2. The oscillator circuit of wherein each timer circuit includes a pair of inverters cross-coupled to each other.3. The oscillator circuit of wherein each timer circuit further includes a ...

LOW-POWER, LONG-RANGE RF LOCALIZATION SYSTEM AND METHOD

A system is presented for non-line-of-sight localization between RF enabled devices. A transmitting node is configured to transmit an RF ranging signal at a first carrier frequency, where the RF ranging signal is modulated with a symbol. The reflecting node is configured to receive the RF ranging signal and further operates to convert the RF ranging signal to a second carrier frequency and retransmit the converted ranging signal while simultaneously receiving the RF ranging signal. The localizing node is configured to receive the converted ranging signal from the reflecting node. The localizing node operates to identify, in frequency domain, the symbol in the converted ranging signal and compute a distance between the reflecting node and the localizing node based in part on the identified symbol in the converted ranging signal. The transmitting node and the localizing node may be on the same or different devices. 1. A system for non-line-of-sight localization between RF enabled devices , comprising:a transmitting node configured to transmit an RF ranging signal at a first carrier frequency across a wireless medium, where the RF ranging signal is modulated with a symbol;a reflecting node having a wireless transceiver and configured to receive the RF ranging signal from the transmitting node, wherein the reflecting node operates to convert the RF ranging signal to a second carrier frequency and retransmit the converted ranging signal across the wireless medium while simultaneously receiving the RF ranging signal, such that the second carrier frequency differs from the first carrier frequency; anda localizing node configured to receive the converted ranging signal from the reflecting node, wherein the localizing node operates to identify, in frequency domain, the symbol in the converted ranging signal and compute a distance between the reflecting node and the localizing node based in part on the identified symbol in the converted ranging signal.2. The system of wherein ...

Self-oscillating switched-capacitor dc-dc converter

A self-oscillating DC-DC converter structure is proposed in which an oscillator is completely internalized within the switched-capacitor network. This eliminates power overhead of clock generation and level shifting and enables higher efficiency at lower power levels. Voltage doublers are cascaded to form a complete energy harvester with a wide load range from 5 nW to 5 μW and self-starting operation down to 140 mV. Because each doubler is self-oscillating, the frequency of each stage can be independently modulated, thereby optimizing the overall conversion efficiency.

PULSE INJECTION CRYSTAL OSCILLATOR

An improved oscillation driver circuit for use in an integrated circuit in combination with an oscillation element. An amplification element is adapted to receive an oscillator output, and to generate an amplified oscillator output. A pulse generator receives the amplified oscillator output and generates positive and negative pulsed outputs substantially in phase with the oscillator output. A driver element is adapted to drive the oscillator input in response to the pulsed outputs. 1. A driver circuit for an oscillation element having an oscillator input and an oscillator output , the driver circuit comprising: an amplification input adapted to be coupled to the oscillator output; and', 'an amplification output; and, 'an amplification element having a driver input coupled to the amplification output; and', 'a driver output adapted to be coupled to the oscillator input., 'a driver element having2. The driver circuit of wherein:the driver element generates a driver output signal on the driver output in a first voltage domain; andthe amplification element generates an amplification output signal on the amplification output in a second voltage domain higher than the first voltage domain.3. The driver circuit of wherein the amplification element receives the oscillator output in a first voltage domain and generates the amplification output in a second voltage domain higher than the first voltage domain.4. The driver circuit of wherein: an input comprising the amplification input;', 'a first pulsed output; and', 'a second pulsed output; and, 'the amplification element is further characterized as comprising a pulse generator having a first driver input coupled to the first pulsed output; and', 'a second driver input coupled to the second pulsed output., 'the driver element is further characterized as having5. The driver circuit of wherein the amplification element receives the oscillator output in a first voltage domain and generates the first and second pulsed outputs in ...

Wireless Neural Recording Devices And System With Two Stage RF And NIR Power Delivery And Programming

A mote includes an optical receiver that wirelessly receives a power and data signal in form of NIR light energy within a patient and converts the NIR light energy to an electrical signal having a supply voltage. A control module supplies the supply voltage to power devices of the mote. A clock generation circuit locks onto a target clock frequency based on the power and data signal and generates clock signals. A data recovery circuit sets parameters of one of the devices based on the power and data signal and a first clock signal. An amplifier amplifies a neuron signal detected via an electrode inserted in tissue of the patient. A chip identifier module, based on a second clock signal, generates a recorded data signal based on a mote chip identifier and the neuron signal. A driver transmits the recorded data signal via a LED or a RF transmitter.

Low Power High Gain Radio Frequency Amplifier For Sensor Apparatus

A wireless communication device is presented for use with a sensor. The wireless communication device includes: an antenna, a driver circuit and a bias circuit. The driver circuit is electrically coupled to the antenna and includes at least one pair of cross-coupled transistors. The bias circuit is electrically coupled to the driver circuit. In a transmit mode, the bias circuit biases the driver circuit with a first bias current. In response to the first bias current, the driver circuit oscillates the antenna. In a receive mode, the bias circuit biases the driver circuit with a second bias current, such that the first bias current differs from the second bias current. In response to the second bias current, the bias circuit amplifies a signal received by the antenna. 1. A wireless communication device for a sensor apparatus , comprising:an antenna;a driver circuit electrically coupled to the antenna and includes at least one pair of cross-coupled transistors; anda bias circuit electrically coupled to the driver circuit, wherein the bias circuit operates, in a transmit mode, to bias the driver circuit with a first bias current, and operates, in a receive mode, to bias the driver circuit with a second bias current, such that the first bias current differs from the second bias current,wherein the driver circuit, in response to the first bias current, oscillates the antenna and, in response to the second bias current, amplifies a signal received by the antenna.2. The wireless communication device of wherein the antenna is further defined as a loop antenna.3. The wireless communication device of wherein the driver circuit is further defined as a pair of NMOS field effect transistors cross-coupled to each other and coupled in parallel with the antenna.4. The wireless communication device of wherein the driver circuit is further defined as a Colpitts oscillator.5. The wireless communication device of wherein the driver circuit is further defined as a first pair of NMOS ...

Pruning Pair-HMM Algorithm And Hardware Architecture

A method is presented for aligning a read with a haplotype. The method includes: constructing an overall matrix for computing alignment probabilities between a given read and a given haplotype, calculating, during a first pass, an alignment probability for each cell in the overall matrix using Pair-HMM method, where the alignment probabilities are calculated using fixed-point arithmetic; pruning cells from the overall matrix to derive a subset of unpruned cells; and calculating, during a second pass, an alignment probability for each cell in the subset of unpruned cells using the Pair-HMM method, where the alignment probabilities are calculated using floating-point arithmetic.

Evaluating Optimality Of A Trace Generated During Sequence Alignment

A method is presented for aligning a read with a reference substring of a genome sequence. The method includes: receiving a banded portion of a matrix from a sequence alignment algorithm; calculating a score threshold for the banded portion of the matrix, where value of the score threshold is calculated as a function of a scoring method used by the sequence alignment algorithm; identifying a high score amongst the cells in the banded portion of the matrix; and comparing the high score to the score threshold. Performing variant calling using the banded portion of the matrix when the high score is greater than to the score threshold. Computing alignment scores for a larger portion of the matrix using the sequence alignment algorithm when the high score is less than or equal to the score threshold.

ULTRA LOW POWER TEMPERATURE INSENSITIVE CURRENT SOURCE WITH LINE AND LOAD REGULATION

A temperature insensitive sub-nA current reference is presented with pA-range power overhead. The main concept is to linearly reduce the gate voltage of a sub-threshold-biased MOSFET as temperature increases, in order to compensate for exponential dependence of drain current on temperature. For example, a MOSFET-only, 20 pA, 780 ppm/° C. current reference that consumes 23 pW is disclosed, marking the lowest reported power among current references. The circuit exploits sub-threshold-biased MOSFETs and a complementary-to-absolute temperature (CTAT) gate voltage to compensate for temperature dependency. The design shows high immunity to supply voltage of 0.58%/V and a load sensitivity of 0.25%/V. 1. A current reference circuit , comprising:a voltage regulator configured to receive a supply voltage and output a constant regulated voltage, the voltage regulator comprised of transistors operating only in the subthreshold region;an output stage having an output transistor, wherein the output transistor has a drain terminal configured to produce a reference current and is operating only in a subthreshold region; anda complementary-to-absolute temperature (CTAT) voltage generator configured to receive the regulated voltage from the voltage regulator and supply a gate voltage to a gate terminal of the output transistor, where the CTAT voltage generator is comprised of transistors operating only in the subthreshold region and the CTAT voltage generator adjusts the gate voltage linearly and inversely with changes in temperature.2. The current source of wherein the CTAT voltage generator is implemented by a stack of diode-connected transistors.3. The current source of wherein a transistor at top of the stack of diode-connected transistors has a different doping type than remainder of the transistors in the stack of diode-connected transistors.4. The current source of wherein one or more transistors on bottom of the stack of diode-connected transistors have a larger threshold ...

LOW POWER OSCILLATOR WITH CHARGE SUBTRACTION SCHEME

An ultra-low power oscillator is designed for wake-up timers that can be used in compact wireless sensors, for example. A constant charge subtraction scheme removes continuous comparator delay from the oscillation period, which is the source of temperature dependence in conventional RC relaxation oscillators. This relaxes comparator design constraints, enabling low power operation. In 0.18 μm CMOS, the oscillator consumes 5.8 nW at room temperature with temperature stability of 45 ppm/° C. (−10° C. to 90° C.) and 1%/V line sensitivity. 1. A low power oscillator , comprising:an integrating capacitor;a current source configured to charge the integrating capacitor;a subtraction circuit electrically coupled to the integrating capacitor and operable to subtract a fixed amount of charge from the integrating capacitor in response to a trigger signal; anda first comparator configured to receive voltage across the integrating capacitor and compare the capacitor voltage to a first reference voltage, wherein the first comparator provides a trigger signal to the subtraction circuit when the integrating capacitor voltage exceeds the first reference voltage.2. The low power oscillator of further comprises:a control circuit counts occurrences of the trigger signal generated by the first comparator and generates an activation signal when the number of occurrences equals a predefined number of cycles; anda second comparator configured to receive voltage across the integrating capacitor and, in response to the activation signal, compares the capacitor voltage to a second reference voltage and outputs a pulse when the capacitor voltage exceeds the second reference voltage.3. The low power oscillator of wherein the output from the second comparator forms a periodic oscillating signal having a frequency based on the predefined number of cycles.4. The low power oscillator of wherein the current source continues to charge the integrating capacitor while the subtraction circuit subtracts ...

Efficient Seeding For Read Alignment

Read alignment is a time-consuming step in genome sequencing analysis. The most widely used software for read alignment, BWA-MEM and BWA-MEM2 are based on the seed-and-extend paradigm for read alignment. The seeding step of read alignment is a major bottleneck contributing ˜38% of the overall execution time in BWA-MEM2 when aligning whole human genome. This is because BWA-MEM2 uses a compressed index structure called the FMD-Index, which results in high bandwidth requirements, primarily due to its character-by-character processing of reads. To address these challenges, a novel seeding data structure is presented along with a custom accelerator architecture for seeding.

Current-Mode Matched Filter Architecture For Signal Acquisition

A matched filter is provided for signal processing applications such as GNSS and RADAR. The filter includes a plurality of correlator cells configured to receive a digital signal and are arranged so that values of the digital signal can be shifted amongst the plurality of correlator cells. Each correlator cell includes a correlator circuit, a data source and a current source. The correlator circuit is configured to receive a value from the digital signal and operates to correlate the value with a value of the known pattern stored in the data store. The current source is interfaced with the correlator circuit and selectively sources current based on the correlation operation performed by the correlator circuit; and an output circuit is coupled to each of the plurality of correlator cell and operates to generate an output which is correlated to current that is being source collectively by the current sources. 1. A matched filter , comprising:a plurality of correlator cells are configured to receive a digital signal and are arranged so that values of the digital signal can be shifted amongst the plurality of correlator cells, the plurality of correlator cells are interconnected by a common wire, each correlator cell includes a data store, a correlator circuit, and a current source,wherein the data store stores one value of a known pattern,wherein the correlator circuit is configured to receive a value from the digital signal and operates to correlate the value of the digital signal with the value of the known pattern,wherein the current source is configured to selectively source current to the common wire based on the correlation operation performed by the correlator circuit, andan output circuit coupled at a common node to each of the plurality of correlator cell and operates to generate an output which is correlated to current that is being sourced collectively by the current sources.2. The matched filter of wherein the data store is implemented with a register claim ...

Variation-Tolerant Voltage Reference

A sub-nW voltage reference is presented that provides inherently low process variation and enables trim-free operation for low-dropout regulators and other applications in nW microsystems. Sixty chips from three different wafers in 180 nm CMOS are measured, showing an untrimmed within-wafer σ/μ of 0.26% and wafer-to-wafer σ/μ of 1.9%. Measurement results also show a temperature coefficient of 48-124 ppm/° C. from −40° C. to 85° C. Outputting a 0.986V reference voltage, the reference operates down to 1.2V and consumes 114 pW at 25° C.

Logic gate size optimization process for an integrated circuit whereby circuit speed is improved while circuit area is optimized

An integrated circuit, when designed, must adhere to timing constraints while attempting to minimize circuit area. In order to adhere to timing specifications while arriving at a near-optimal circuit surface area, an iterative process is used which selectively increases logic gates sizes by accessing logic gates from a memory stored logic gate library. A circuit representation is read along with timing constraints for circuit paths. Each circuit path in the circuit is processed to find it's actual circuit path delay. A most out-of-specification circuit path (in terms of speed) is chosen in the circuit and a sensitivity calculation is performed for each logic gate in the most out-of-specification circuit path. The logic gate in the circuit path with the maximized sensitivity (sensitivity=Δspeed/Δarea) is increased in size by accessing a larger gate in the library in order to improve speed at the expense of area. The above process continues iteratively until no out-of-specification circuit paths are found.

Low-power, long-range RF localization system and method

A system is presented for non-line-of-sight localization between RF enabled devices. A transmitting node is configured to transmit an RF ranging signal at a first carrier frequency, where the RF ranging signal is modulated with a symbol. The reflecting node is configured to receive the RF ranging signal and further operates to convert the RF ranging signal to a second carrier frequency and retransmit the converted ranging signal while simultaneously receiving the RF ranging signal. The localizing node is configured to receive the converted ranging signal from the reflecting node. The localizing node operates to identify, in frequency domain, the symbol in the converted ranging signal and compute a distance between the reflecting node and the localizing node based in part on the identified symbol in the converted ranging signal. The transmitting node and the localizing node may be on the same or different devices.

Millimeter-scale bluetooth low energy transmitter with dual purpose loop antenna

A millimeter-scale Bluetooth low energy wireless transmitter is presented with a dual purpose loop antenna. The oscillator employs a high quality factor resonator formed by a printed 3.5×3.5 mm 2 inductive loop antenna (simulated Q˜110) and an on-chip digitally-switched capacitor array (simulated Q˜283). The oscillator replaces the traditional voltage controlled oscillator plus power amplifier, achieving lower power consumption while maintaining phase noise of −118.5 dBc/Hz at 1 MHz offset that results in low FSK modulation error (2.1%) and low frequency drift during BLE packet transmission.

In-transit message detection for global virtual time calculation in parrallel time warp simulation

System and method for calculating global virtual time for use in memory management, termination detection, snapshots, crash recovery, input and output handling, and so forth, and in parallel simulation of digital circuits. Processes executing on parallel processors communicate messages through channels having output trail buffers on each process communicating to the channel, and one input trail buffer for all processes receiving messages from the channel. A channel is the union of all wires or communication paths connecting two processors. Input trail buffers store the time stamp of the most recently received message, and output trail buffers store valley messages. Global virtual time is calculated with reference to the least time stamp of the output trail buffers, where the least time stamp is calculated with respect to the time stamp of the input trail buffer.

Pulse injection crystal oscillator

An improved oscillation driver circuit for use in an integrated circuit in combination with an oscillation element. An amplification element is adapted to receive an oscillator output, and to generate an amplified oscillator output. A pulse generator receives the amplified oscillator output and generates positive and negative pulsed outputs substantially in phase with the oscillator output. A driver element is adapted to drive the oscillator input in response to the pulsed outputs.

Carrier And Sampling Frequency Offset Estimation For RF Communication With Crystal-Less Nodes

When the ultra-low power mm-scale sensor node does not have a crystal oscillator and phase-lock loop, it inevitably exhibits significant carrier frequency offset (CFO) and sampling frequency offset (SFO) with respect to the reference frequencies in the gateway. This disclosure enables efficient real-time calculation of accurate SFO and CFO at the gateway, thus the ultra-low power mm-scale sensor node can be realized without a costly and bulky clock reference crystal and also power-hungry phase lock loop. In the proposed system, the crystal-less sensor starts transmission with repetitive RF pulses with a constant interval, followed by the data payload using pulse-position modulation (PPM). A proposed algorithm uses a two-dimensional (2D) fast Fourier transform (FFT) based process that identifies the SFO and CFO at the same time to establish successful wireless communication between the gateway and crystal-less sensor nodes.

Environmental sensor

An environmental sensor implementing a sleep mode timer with an oscillator circuit suitable for low power applications is presented. The oscillator circuit includes a plurality of timer stages cascaded in series with each other. Each timer circuit includes a plurality of transistors and operates to output two voltages with opposite polarities, such that the polarities of the two voltages oscillate periodically based on leakage current in the plurality of transistors. Each timer circuit further includes one or more tuning transistors that operate to adjust a frequency at which the polarities of the voltages oscillate. A complementary-to-absolute temperature (“CTAT”) voltage generator is configured to receive a regulated voltage and supply a bias voltage to the one or more tuning transistors in each of the plurality of timer circuits, where the CTAT voltage generator adjusts the bias voltage linearly and inversely with changes in temperature.

Wireless neural recording devices and system with two stage RF and NIR power delivery and programming

A mote includes an optical receiver that wirelessly receives a power and data signal in form of NIR light energy within a patient and converts the NIR light energy to an electrical signal having a supply voltage. A control module supplies the supply voltage to power devices of the mote. A clock generation circuit locks onto a target clock frequency based on the power and data signal and generates clock signals. A data recovery circuit sets parameters of one of the devices based on the power and data signal and a first clock signal. An amplifier amplifies a neuron signal detected via an electrode inserted in tissue of the patient. A chip identifier module, based on a second clock signal, generates a recorded data signal based on a mote chip identifier and the neuron signal. A driver transmits the recorded data signal via a LED or a RF transmitter.

Amplifier with sample and average common mode feedback resistor

An amplifier is presented with a sample and average common mode feedback resistor. The amplifier circuit includes a feedback capacitor and a feedback resistor in parallel with the feedback capacitor, where the feedback capacitor and the feedback resistor form part of the negative feedback path for the amplifier. Of note, the feedback resistor is comprised of a low pass filter in series with a switched capacitor resistor, such that the low pass filter is electrically coupled to the output of the amplifier circuit and the switched capacitor resistor is electrically coupled to the inverting input of the amplifier circuit. The amplifier circuit further includes a control circuit interfaced with switches of the switched capacitor resistor. The high pass corner of the switched capacitor resistor is preferably lower than corner of the low pass filter.

Analog-to-digital conversion circuit and image sensor including the same

An analog-to-digital converter (ADC) circuit is present, which is particularly suitable for use in an image sensor. The ADC circuit includes a comparator and a digital-to-analog converter (DAC) circuit. The DAC circuit includes two or more charge paths electrically coupled to the output node. Each charge path is formed by one or more charge-injection cells electrically coupled via a gain capacitor to the output node, and a charge conversion capacitor electrically coupled in parallel with the one or more charge-injection cells. Each charge-injection cell is configured to transfer a fixed amount of charge from a charge source to an associated charge path and includes at least one switch configured to isolate the charge source from the output node.

Floating-gate transistor array for performing weighted sum computation

A weighted sum is a key computation for many neural networks and other machine learning algorithms. Integrated circuit designs that perform a weighted sum are presented. Weights are stored as threshold voltages in an array of flash transistors. By putting the circuits into a well-defined voltage state, the transistors that hold one set of weights will pass current equal to the desired sum. The current flowing through a given transistor is unaffected by operation of remaining transistors in the circuit.

Randomized value generation

Self-oscillating switched-capacitor DC-DC converter

A self-oscillating DC-DC converter structure is proposed in which an oscillator is completely internalized within the switched-capacitor network. This eliminates power overhead of clock generation and level shifting and enables higher efficiency at lower power levels. Voltage doublers are cascaded to form a complete energy harvester with a wide load range from 5 nW to 5 μW and self-starting operation down to 140 mV. Because each doubler is self-oscillating, the frequency of each stage can be independently modulated, thereby optimizing the overall conversion efficiency.

Floating-gate transistor array for performing weighted sum computation

A weighted sum is a key computation for many neural networks and other machine learning algorithms. Integrated circuit designs that perform a weighted sum are presented. Weights are stored as threshold voltages in an array of flash transistors. By putting the circuits into a well-defined voltage state, the transistors that hold one set of weights will pass current equal to the desired sum. The current flowing through a given transistor is unaffected by operation of remaining transistors in the circuit.

Ultra low power temperature insensitive current source with line and load regulation

A temperature insensitive sub-nA current reference is presented with pA-range power overhead. The main concept is to linearly reduce the gate voltage of a sub-threshold-biased MOSFET as temperature increases, in order to compensate for exponential dependence of drain current on temperature. For example, a MOSFET-only, 20 pA, 780 ppm/° C. current reference that consumes 23 pW is disclosed, marking the lowest reported power among current references. The circuit exploits sub-threshold-biased MOSFETs and a complementary-to-absolute temperature (CTAT) gate voltage to compensate for temperature dependency. The design shows high immunity to supply voltage of 0.58%/V and a load sensitivity of 0.25%/V.