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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 38. Отображено 38.
30-12-2021 дата публикации

PROXIMITY CORRECTION METHODS FOR SEMICONDUCTOR MANUFACTURING PROCESSES

Номер: US20210405521A1
Автор: Taehoon Kim, Jaeho Jeong, Jeonghoon Ko, Jongwon Kim, Yejin Jeong, Changwook Jeong
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A proximity correction method for a semiconductor manufacturing process includes: generating a plurality of pieces of original image data from a plurality of sample regions, with the sample regions selected from layout data used in the semiconductor manufacturing process; removing some pieces of original image data that overlap with each other from the plurality of pieces of original image data, resulting in a plurality of pieces of input image data; inputting the plurality of pieces of input image data to a machine learning model; obtaining a prediction value of critical dimensions of target patterns included in the plurality of pieces of input image data from the machine learning model; measuring a result value for critical dimensions of actual patterns corresponding to the target patterns on a semiconductor substrate on which the semiconductor manufacturing process is performed; and performing learning of the machine learning model using the prediction value and the result value.

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Номер записи: 1
10-02-2022 дата публикации

SIMULATION METHOD FOR SEMICONDUCTOR FABRICATION PROCESS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20220043405A1
Автор: Jinwoo Kim, Sanghoon Myung, Wonik Jang, Yongwoo Jeon, Kanghyun Baek, Jisu Ryu, Changwook Jeong
Принадлежит: SAMSUNG ELECTRONICS CO LTD

According to an aspect of the present inventive concept, a simulation method for a semiconductor fabrication process includes obtaining, as input data, process parameters for controlling a semiconductor process of manufacturing semiconductor devices, or design parameters representing a structure of the semiconductor devices, or both the process parameters and the design parameters; generating predictive data for electrical characteristics of the semiconductor devices using a machine learning model based on the input data; generating reference data for the electrical characteristics of the semiconductor devices using a simulation tool based on the input data; and training the machine learning model using the predictive data and the reference data.

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Номер записи: 2
30-01-2024 дата публикации

Simulation system for semiconductor process and simulation method thereof

Номер: US0011886783B2
Автор: Sanghoon Myung, Hyunjae Jang, In Huh, Hyeon Kyun Noh, Min-Chul Park, Changwook Jeong
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

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Номер записи: 3
17-11-2020 дата публикации

High optical transparent two-dimensional electronic conducting system and process for generating same

Номер: US0010839974B2
Автор: Muhammad Ashraful Alam, Ruiyi Chen, Suprem R. Das, David B. Janes, Changwook Jeong, Mark Lundstrom, ALAM MUHAMMAD ASHRAFUL, CHEN RUIYI, DAS SUPREM R, JANES DAVID B, JEONG CHANGWOOK, LUNDSTROM MARK, Alam, Muhammad Ashraful, Chen, Ruiyi, Das, Suprem R., Janes, David B., Jeong, Changwook, Lundstrom, Mark
Принадлежит: PURDUE RESEARCH FOUNDATION

Hybrid transparent conducting materials are disclosed with combine a polycrystalline film and conductive nanostructures, in which the polycrystalline film is “percolation doped” with the conductive nanostructures. The polycrystalline film preferably is a single atomic layer thickness of polycrystalline graphene, and conductive nanostructures preferably are silver nanowires.

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Номер записи: 4
08-08-2013 дата публикации

Hybrid Transparent Conducting Materials

Номер: US20130200421A1
Автор: Changwook Jeong, Mark Lundstrom, Muhammad Ashraful Alam
Принадлежит:

Illustrative embodiments of hybrid transparent conducting materials and applications thereof are disclosed. In one illustrative embodiment, a hybrid transparent conducting material may include a polycrystalline film and a plurality of conductive nanostructures randomly dispersed in the polycrystalline film. In another illustrative embodiment, a photovoltaic cell may include a transparent electrode comprising polycrystalline graphene that is percolation doped with metallic nanowires, where the metallic nanowires do not form a percolation network for charge carriers across the transparent electrode. 1. A hybrid transparent conducting material (TCM) comprising:a polycrystalline film; anda plurality of conductive nanostructures randomly dispersed in the polycrystalline film.2. The hybrid TCM of claim 1 , wherein the polycrystalline film comprises a polycrystalline graphene film.3. The hybrid TCM of claim 1 , wherein the plurality of conductive nanostructures comprise a plurality of metallic nanowires.4. The hybrid TCM of claim 3 , wherein the plurality of metallic nanowires comprise silver nanowires.5. The hybrid TCM of claim 1 , wherein the plurality of conductive nanostructures each have a length greater than 1 μm and a cross-sectional dimension of less than 1 μm.6. The hybrid TCM of claim 1 , wherein a density of the plurality of conductive nanostructures randomly dispersed in the polycrystalline film is below a percolation threshold.7. The hybrid TCM of claim 6 , wherein the density of the plurality of conductive nanostructures randomly dispersed in the polycrystalline film is at most sixty percent of the percolation threshold.8. The hybrid TCM of claim 1 , wherein an average length of the plurality of conductive nanostructures is greater than an average grain diameter of the polycrystalline film.9. The hybrid TCM of claim 8 , wherein an average distance between each of the plurality of conductive nanostructures is greater than the average length of the plurality of ...

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Номер записи: 5
06-06-2023 дата публикации

Electronic devices generating verification vector for verifying semiconductor circuit and methods of operating the same

Номер: US0011669773B2
Автор: Seungju Kim, Hyojin Choi, In Huh, Jeonghoon Ko, Changwook Jeong, Younsik Park, Joonwan Chai
Принадлежит: Samsung Electronics Co., Ltd.

An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.

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Номер записи: 6
07-02-2023 дата публикации

Simulation system for semiconductor process and simulation method thereof

Номер: US0011574095B2
Автор: Sanghoon Myung, Hyunjae Jang, In Huh, Hyeon Kyun Noh, Min-Chul Park, Changwook Jeong
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

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Номер записи: 7
11-05-2023 дата публикации

SIMULATION SYSTEM FOR SEMICONDUCTOR PROCESS AND SIMULATION METHOD THEREOF

Номер: US20230142367A1
Автор: Sanghoon MYUNG, Hyunjae Jang, In Huh, Hyeon Kyun Noh, Min-Chul Park, Changwook Jeong
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

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Номер записи: 8
14-03-2024 дата публикации

SYSTEM AND METHOD FOR MODELING A SEMICONDUCTOR FABRICATION PROCESS

Номер: US20240086599A1
Автор: Hyunjoong Kim, Jaepil Shin, Moonhyun Cha, Changwook Jeong
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A system for modeling a semiconductor fabrication process includes at least one first processor and at least one second processor. The at least one first processor is configured to provide at least one machine learning (ML) model, which is trained by using a plurality of pairs of images of a design pattern sample and a physical pattern sample. The physical pattern sample is formed from the design pattern sample by using the semiconductor fabrication process. The at least one second processor is configured to provide an input image representing a shape of a design pattern and/or a physical pattern to the at least one first processor and to generate output data defining the physical pattern and/or the design pattern based on an output image received from the at least one first processor.

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Номер записи: 9
22-08-2023 дата публикации

Proximity correction methods for semiconductor manufacturing processes

Номер: US0011733603B2
Автор: Taehoon Kim, Jaeho Jeong, Jeonghoon Ko, Jongwon Kim, Yejin Jeong, Changwook Jeong
Принадлежит: Samsung Electronics Co., Ltd.

A proximity correction method for a semiconductor manufacturing process includes: generating a plurality of pieces of original image data from a plurality of sample regions, with the sample regions selected from layout data used in the semiconductor manufacturing process; removing some pieces of original image data that overlap with each other from the plurality of pieces of original image data, resulting in a plurality of pieces of input image data; inputting the plurality of pieces of input image data to a machine learning model; obtaining a prediction value of critical dimensions of target patterns included in the plurality of pieces of input image data from the machine learning model; measuring a result value for critical dimensions of actual patterns corresponding to the target patterns on a semiconductor substrate on which the semiconductor manufacturing process is performed; and performing learning of the machine learning model using the prediction value and the result value.

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Номер записи: 10
03-10-2023 дата публикации

Non-transitory computer-readable medium storing program code generating wafer map based on generative adversarial networks and computing device including the same

Номер: US0011775840B2
Автор: Wonik Jang, Sanghoon Myung, Changwook Jeong, Sunghee Lee
Принадлежит: Samsung Electronics Co., Ltd.

A non-transitory computer-readable medium storing a program code including an image generation model, which when executed, causes a processor to input input data including sampling data of some of a plurality of semiconductor dies of a wafer to a generator network of the image generation model and output a wafer map indicating the plurality of semiconductor dies, and to input the wafer map output from the generator network to a discriminator network of the image generation model and discriminate the wafer map.

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Номер записи: 11
29-11-2022 дата публикации

High optical transparent two-dimensional electronic conducting system and process for generating same

Номер: US0011515057B2
Автор: Muhammad Ashraful Alam, Ruiyi Chen, Suprem R. Das, David B. Janes, Changwook Jeong, Mark Lundstrom
Принадлежит: Purdue Research Foundation

Hybrid transparent conducting materials are disclosed which combine a polycrystalline film and conductive nanostructures, in which the polycrystalline film is “percolation doped” with the conductive nanostructures. The polycrystalline film preferably is a single atomic layer thickness of polycrystalline graphene, and the conductive nanostructures preferably are silver nanowires.

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Номер записи: 12
22-04-2021 дата публикации

ELECTRONIC DEVICES GENERATING VERIFICATION VECTOR FOR VERIFYING SEMICONDUCTOR CIRCUIT AND METHODS OF OPERATING THE SAME

Номер: US20210117193A1
Автор: Seungju Kim, Hyojin Choi, In Huh, Jeonghoon Ko, Changwook Jeong, Younsik Park, Joonwan Chai, KIM SEUNGJU, CHOI HYOJIN, HUH IN, KO JEONGHOON, JEONG CHANGWOOK, PARK YOUNSIK, CHAI JOONWAN, Kim, Seungju, Choi, Hyojin, Huh, In, Ko, Jeonghoon, Jeong, Changwook, Park, Younsik, Chai, Joonwan
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.

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Номер записи: 13
30-06-2022 дата публикации

METHOD OF PREDICTING SEMICONDUCTOR MATERIAL PROPERTIES AND METHOD OF TESTING SEMICONDUCTOR DEVICE USING THE SAME

Номер: US20220207393A1
Автор: Naoto Umezawa, Changwook Jeong, Jisu Ryu, Kyu Hyun Lee, Jinyoung Lim, Wonik Jang, In Huh
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Disclosed are methods of predicting semiconductor material properties and methods of testing semiconductor devices using the same. The prediction method comprises preparing a machine learning model that is trained with a training system and using the machine learning model to predict material properties of a target system. The machine learning model is represented as a function of material properties with respect to a descriptor. The descriptor is calculated from unrelaxed charge density (UCD) that is represented by summation of atomic charge density (ACD) of single atoms.

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Номер записи: 14
05-11-2019 дата публикации

High optical transparent two-dimensional electronic conducting system and process for generating same

Номер: US0010468151B2
Автор: Muhammad Ashraful Alam, Ruiyi Chen, Suprem R. Das, David B. Janes, Changwook Jeong, Mark Lundstrom, ALAM MUHAMMAD ASHRAFUL, CHEN RUIYI, DAS SUPREM R, JANES DAVID B, JEONG CHANGWOOK, LUNDSTROM MARK, Alam, Muhammad Ashraful, Chen, Ruiyi, Das, Suprem R., Janes, David B., Jeong, Changwook, Lundstrom, Mark
Принадлежит: PURDUE RESEARCH FOUNDATION

Hybrid transparent conducting materials are disclosed with combine a polycrystalline film and conductive nanostructures, in which the polycrystalline film is “percolation doped” with the conductive nanostructures. The polycrystalline film preferably is a single atomic layer thickness of polycrystalline graphene, and conductive nanostructures preferably are silver nanowires.

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Номер записи: 15
14-05-2024 дата публикации

Simulation method for semiconductor fabrication process and method for manufacturing semiconductor device

Номер: US0011982980B2
Автор: Jinwoo Kim, Sanghoon Myung, Wonik Jang, Yongwoo Jeon, Kanghyun Baek, Jisu Ryu, Changwook Jeong
Принадлежит: SAMSUNG ELECTRONICS CO., LTD., Samsung Electronics Co., Ltd.

According to an aspect of the present inventive concept, a simulation method for a semiconductor fabrication process includes obtaining, as input data, process parameters for controlling a semiconductor process of manufacturing semiconductor devices, or design parameters representing a structure of the semiconductor devices, or both the process parameters and the design parameters; generating predictive data for electrical characteristics of the semiconductor devices using a machine learning model based on the input data; generating reference data for the electrical characteristics of the semiconductor devices using a simulation tool based on the input data; and training the machine learning model using the predictive data and the reference data.

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Номер записи: 16
24-03-2022 дата публикации

SYSTEM AND METHOD FOR MODELING A SEMICONDUCTOR FABRICATION PROCESS

Номер: US20220092239A1
Автор: Hyunjoong Kim, Jaepil Shin, Moonhyun Cha, Changwook Jeong
Принадлежит:

A system for modeling a semiconductor fabrication process includes at least one first processor and at least one second processor. The at least one first processor is configured to provide at least one machine learning (ML) model, which is trained by using a plurality of pairs of images of a design pattern sample and a physical pattern sample. The physical pattern sample is formed from the design pattern sample by using the semiconductor fabrication process. The at least one second processor is configured to provide an input image representing a shape of a design pattern and/or a physical pattern to the at least one first processor and to generate output data defining the physical pattern and/or the design pattern based on an output image received from the at least one first processor. 1. A system for modeling a semiconductor fabrication process , the system comprising:at least one first processor configured to provide at least one machine learning model, the at least one machine learning model being trained by using a plurality of pairs of images of a design pattern sample and a physical pattern sample, the physical pattern sample being formed from the design pattern sample by using the semiconductor fabrication process; andat least one second processor configured to provide an input image representing a shape of a design pattern and/or a physical pattern to the at least one first processor and to generate output data defining the physical pattern and/or the design pattern based on an output image received from the at least one first processor.2. The system of claim 1 , wherein the at least one machine learning model comprises a generative adversarial network comprising a generator and a discriminator claim 1 , which are trained by using the plurality of pairs of images claim 1 ,wherein the at least one second processor is configured to provide the input image to the generator and to generate the output data based on an output image received from the generator.3. ...

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Номер записи: 17
29-08-2023 дата публикации

Semiconductor wafer fault analysis system and operation method thereof

Номер: US0011741596B2
Автор: Min-Chul Park, Ami Ma, Jisu Ryu, Changwook Jeong
Принадлежит: Samsung Electronics Co., Ltd., SAMSUNG ELECTRONICS CO., LTD.

A semiconductor wafer fault analysis system includes: a database to store a first reference map, which is classified as a first fault type, and a second reference map, which is classified as a second fault type; a first auto-encoder/decoder to remove a noise corresponding to the first fault type from the first reference map to generate a first pre-processed reference map; a second auto-encoder/decoder to remove a noise corresponding to the second fault type from the second reference map to generate a second pre-processed reference map; and a fault type analyzer. The database is updated based on the first and second pre-processed reference maps, and the fault type analyzer is to classify a fault type of a target map based on the updated database. The target map is generated by measuring a target wafer.

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Номер записи: 18
21-04-2022 дата публикации

METHODS OF GENERATING CIRCUIT MODELS AND MANUFACTURING INTEGRATED CIRCUITS USING THE SAME

Номер: US20220121800A1
Автор: Yohan Kim, Changwook Jeong, Jisu Ryu
Принадлежит:

A method of generating a circuit model used to simulate an integrated circuit may include generating first feature element data and second feature element data by classifying feature data of a target semiconductor device according to measurement conditions, generating first target data and second target data by preprocessing the first feature element data and the second feature element data, respectively, generating a first machine learning model using the first target data and extracting a second machine learning model using the second target data, and generating the circuit model used to simulate the integrated circuit using the first machine learning model and the second machine learning model.

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Номер записи: 19
27-06-2024 дата публикации

ELECTRIFICATION OF HEAT SUPPLY TO FLUIDIZED REGENERATION SYSTEM

Номер: US20240207801A1
Автор: Rian Reyneke, Matthew James Griffiths, Changwook Jeong, Manoj Nagvekar, Kyung Taek Han, Michael J. Tallman
Принадлежит: KELLOGG BROWN & ROOT LLC

A system for reactivating a catalyst having a predetermined heat content includes a reactor, a regenerator, and an electrically energized heater. The reactor is configured to generate a spent catalyst. The regenerator is configured to receive the spent catalyst from the reactor. The electrically energized heater has a plurality of energy emitting members at least partially immersed in the spent catalyst. The heater is configured to provide a supplemental heat content to obtain the predetermined heat content.

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Номер записи: 20
20-12-2016 дата публикации

Hybrid transparent conducting materials

Номер: US0009524806B2
Автор: Changwook Jeong, Mark Lundstrom, Muhammad Ashraful Alam, JEONG CHANGWOOK, LUNDSTROM MARK, ALAM MUHAMMAD ASHRAFUL, Jeong Changwook, Lundstrom Mark, Alam Muhammad Ashraful
Принадлежит: PURDUE RESEARCH FOUNDATION, JEONG CHANGWOOK, LUNDSTROM MARK, ALAM MUHAMMAD ASHRAFUL, Jeong Changwook, Lundstrom Mark, Alam Muhammad Ashraful

Illustrative embodiments of hybrid transparent conducting materials and applications thereof are disclosed. In one illustrative embodiment, a hybrid transparent conducting material may include a polycrystalline film and a plurality of conductive nanostructures randomly dispersed in the polycrystalline film. In another illustrative embodiment, a photovoltaic cell may include a transparent electrode comprising polycrystalline graphene that is percolation doped with metallic nanowires, where the metallic nanowires do not form a percolation network for charge carriers across the transparent electrode.

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Номер записи: 21
26-12-2023 дата публикации

System and method for modeling a semiconductor fabrication process

Номер: US0011853660B2
Автор: Hyunjoong Kim, Jaepil Shin, Moonhyun Cha, Changwook Jeong
Принадлежит: SAMSUNG ELECTRONICS CO., LTD., Samsung Electronics Co., Ltd.

A system for modeling a semiconductor fabrication process includes at least one first processor and at least one second processor. The at least one first processor is configured to provide at least one machine learning (ML) model, which is trained by using a plurality of pairs of images of a design pattern sample and a physical pattern sample. The physical pattern sample is formed from the design pattern sample by using the semiconductor fabrication process. The at least one second processor is configured to provide an input image representing a shape of a design pattern and/or a physical pattern to the at least one first processor and to generate output data defining the physical pattern and/or the design pattern based on an output image received from the at least one first processor.

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Номер записи: 22
12-05-2020 дата публикации

Semiconductor fault analysis device and fault analysis method thereof

Номер: US0010650910B2
Автор: Changwook Jeong, Sanghoon Myung, Min-Chul Park, Jeonghoon Ko, Jisu Ryu, Hyunjae Jang, Hyungtae Kim, Yunrong Li, Min Chul Jeon, JEONG CHANGWOOK, MYUNG SANGHOON, PARK MIN-CHUL, KO JEONGHOON, RYU JISU, JANG HYUNJAE, KIM HYUNGTAE, LI YUNRONG, JEON MIN CHUL, Jeong, Changwook, Myung, Sanghoon, Park, Min-Chul, Ko, Jeonghoon, Ryu, Jisu, Jang, Hyunjae, Kim, Hyungtae, Li, Yunrong, Jeon, Min Chul
Принадлежит: SAMSUNG ELECTRONICS CO., LTD., SAMSUNG ELECTRONICS CO LTD

A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.

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Номер записи: 23
27-05-2021 дата публикации

SIMULATION SYSTEM FOR SEMICONDUCTOR PROCESS AND SIMULATION METHOD THEREOF

Номер: US20210158152A1
Автор: Sanghoon MYUNG, Hyunjae Jang, In Huh, Hyeon Kyun Noh, Min-chul Park, Changwook Jeong, MYUNG SANGHOON, JANG HYUNJAE, HUH IN, NOH HYEON KYUN, PARK MIN-CHUL, JEONG CHANGWOOK, MYUNG, Sanghoon, Jang, Hyunjae, Huh, In, Noh, Hyeon Kyun, Park, Min-chul, Jeong, Changwook
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

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Номер записи: 24
16-01-2014 дата публикации

HIGH OPTICAL TRANSPARENT TWO-DIMENSIONAL ELECTRONIC CONDUCTING SYSTEM AND PROCESS FOR GENERATING SAME

Номер: US20140014171A1
Автор: ALAM Muhammad Ashraful, CHEN Ruiyi, DAS Suprem R., JANES David B., JEONG Changwook
Принадлежит: PURDUE RESEARCH FOUNDATION

Hybrid transparent conducting materials are disclosed with combine a polycrystalline film and conductive nanostructures, in which the polycrystalline film is “percolation doped” with the conductive nanostructures. The polycrystalline film preferably is a single atomic layer thickness of polycrystalline graphene, and conductive nanostructures preferably are silver nanowires. 1. A hybrid transparent conducting material (TCM) comprising:a granular polycrystalline film anda layer, on the granular polycrystalline film, comprising a plurality of randomly dispersed conductive nanostructures.2. The hybrid TCM of claim 1 , wherein the granular polycrystalline film is an atomic monolayer.3. The hybrid TCM of claim 1 , wherein the granular polycrystalline film is a polycrystalline graphene film.4. The hybrid TCM of claim 1 , wherein the conductive nanostructures are metallic nanowires.5. The hybrid TCM of claim 4 , wherein the metallic nanowires are silver nanowires.6. The hybrid TCM of claim 1 , wherein each of the conductive nanostructures has a length greater than 1 μm and a cross-sectional dimension of less than 1 μm.7. The hybrid TCM of claim 1 , wherein density of the plurality of conductive nanostructures randomly dispersed in the granular polycrystalline film is below a percolation threshold.8. The hybrid TCM of claim 1 , wherein density of the plurality of conductive nanostructures randomly dispersed on the polycrystalline film is at most sixty percent of the percolation threshold.9. The hybrid TCM of claim 1 , wherein average length of the conductive nanostructures is greater than average grain diameter in the granular polycrystalline film.10. The hybrid TCM of claim 1 , wherein average distance between the conductive nanostructures is greater than average length of the conductive nanostructures.11. The hybrid TCM of claim 1 , wherein the granular polycrystalline film and the nanowire layer separately each have a sheet resistance of 20 ohms per square or greater.12. ...

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Номер записи: 25
25-02-2021 дата публикации

METHOD AND SYSTEM FOR HYBRID MODEL INCLUDING MACHINE LEARNING MODEL AND RULE-BASED MODEL

Номер: US20210056425A1
Автор: HUH IN, Jang Hyunjae, JEONG Changwook, Myung Sanghoon, Noh Hyeonkyun, Park Minchul
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A method for a hybrid model that includes a machine learning model and a rule-based model, includes obtaining a first output from the rule-based model by providing a first input to the rule-based model, and obtaining a second output from the machine learning model by providing the first input, a second input, and the obtained first output to the machine learning model. The method further includes training the machine learning model, based on errors of the obtained second output. 1. A method for a hybrid model that comprises a machine learning model and a rule-based model , the method comprising:obtaining a first output from the rule-based model by providing a first input to the rule-based model;obtaining a second output from the machine learning model by providing the first input, a second input, and the obtained first output to the machine learning model; andtraining the machine learning model, based on errors of the obtained second output.2. The method of claim 1 , wherein the first input is required for the rule-based model claim 1 , andthe second input affects the second output and is not required for the rule-based model.3. The method of claim 1 , wherein the rule-based model comprises a plurality of parameters used to obtain the first output from the first input claim 1 , andeach of the plurality of parameters is a constant.4. The method of claim 1 , wherein the rule-based model comprises a plurality of parameters used to obtain the first output from the first input claim 1 , andthe method further comprises adjusting the plurality of parameters, based on the errors of the obtained second output.5. The method of claim 4 , wherein the training of the machine learning model comprises:obtaining a value of a loss function, based on the errors of the obtained second output; andtraining the machine learning model to reduce the value of the obtained loss function, andwherein the value of the obtained loss function increases as errors between the plurality of ...

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Номер записи: 26
06-04-2017 дата публикации

HIGH OPTICAL TRANSPARENT TWO-DIMENSIONAL ELECTRONIC CONDUCTING SYSTEM AND PROCESS FOR GENERATING SAME

Номер: US20170098486A1
Автор: ALAM Muhammad Ashraful, CHEN Ruiyi, DAS Suprem R., JANES David B., JEONG Changwook
Принадлежит:

Hybrid transparent conducting materials are disclosed with combine a polycrystalline film and conductive nanostructures, in which the polycrystalline film is “percolation doped” with the conductive nanostructures. The polycrystalline film preferably is a single atomic layer thickness of polycrystalline graphene, and conductive nanostructures preferably are silver nanowires. 1. A hybrid transparent conducting material (TCM) comprising:a granular polycrystalline film anda layer, on the granular polycrystalline film, comprising a plurality of randomly dispersed conductive nanostructures.2. The hybrid TCM of claim 1 , wherein the granular polycrystalline film is an atomic monolayer.3. The hybrid TCM of claim 1 , wherein the granular polycrystalline film is a polycrystalline graphene film.4. The hybrid TCM of claim 1 , wherein the conductive nanostructures are metallic nanowires.5. The hybrid TCM of claim 4 , wherein the metallic nanowires are silver nanowires.6. The hybrid TCM of claim 1 , wherein each of the conductive nanostructures has a length greater than 1 μm and a cross-sectional dimension of less than 1 μm.7. The hybrid TCM of claim 1 , wherein density of the plurality of conductive nanostructures randomly dispersed in the granular polycrystalline film is below a percolation threshold.8. The hybrid TCM of claim 1 , wherein density of the plurality of conductive nanostructures randomly dispersed on the polycrystalline film is at most sixty percent of the percolation threshold.9. The hybrid TCM of claim 1 , wherein average length of the conductive nanostructures is greater than average grain diameter in the granular polycrystalline film.10. The hybrid TCM of claim 1 , wherein average distance between the conductive nanostructures is greater than average length of the conductive nanostructures.11. The hybrid TCM of claim 1 , wherein the granular polycrystalline film and the nanowire layer separately each have a sheet resistance of 20 ohms per square or greater.12. ...

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Номер записи: 27
02-04-2020 дата публикации

HIGH OPTICAL TRANSPARENT TWO-DIMENSIONAL ELECTRONIC CONDUCTING SYSTEM AND PROCESS FOR GENERATING SAME

Номер: US20200105434A1
Автор: ALAM Muhammad Ashraful, CHEN Ruiyi, DAS Suprem R., JANES David B., JEONG Changwook, LUNDSTROM Mark
Принадлежит:

Hybrid transparent conducting materials are disclosed with combine a polycrystalline film and conductive nanostructures, in which the polycrystalline film is “percolation doped” with the conductive nanostructures. The polycrystalline film preferably is a single atomic layer thickness of polycrystalline graphene, and conductive nanostructures preferably are silver nanowires. 1. A photovoltaic cell comprising:a transparent electrode comprising a polycrystalline graphene film that is percolation doped with randomly dispersed metallic nanowires, wherein the metallic nanowires do not form a percolation network for charge carriers across the transparent electrode.2. The photovoltaic cell of claim 1 , wherein the transparent electrode comprises a plurality of stacked layers claim 1 , each of the plurality of stacked layers comprising a polycrystalline graphene film that is percolation doped with randomly dispersed metallic nanowires.3. The photovoltaic cell of claim 1 , wherein the transparent electrode has a sheet resistance below twenty ohms per square and a transmittance above ninety percent for solar radiation.4. The photovoltaic cell of claim 1 , wherein an average distance between the conductive nanowires is greater than an average length of the conductive nanowires.5. The photovoltaic cell of claim 1 , wherein an average length of the conductive nanowires is greater than an average grain diameter in the polycrystalline graphene film.6. The photovoltaic cell of claim 1 , wherein the number of conductive nanowires is less than one half a number of grains in the polycrystalline graphene film.7. The photovoltaic cell of claim 1 , wherein the polycrystalline graphene film is an atomic monolayer.8. The photovoltaic cell of claim 1 , wherein the conductive nanowires are silver nanowires.9. The photovoltaic cell of claim 1 , wherein each of the conductive nanowires has a length greater than 1 μm and a cross-sectional dimension of less than 1 μm.10. The photovoltaic cell of ...

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Номер записи: 28
27-05-2021 дата публикации

NON-TRANSITORY COMPUTER-READABLE MEDIUM STORING PROGRAM CODE GENERATING WAFER MAP BASED ON GENERATIVE ADVERSARIAL NETWORKS AND COMPUTING DEVICE INCLUDING THE SAME

Номер: US20210158173A1
Автор: Jang Wonik, JEONG Changwook, LEE Sunghee, Myung Sanghoon
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A non-transitory computer-readable medium storing a program code including an image generation model, which when executed, causes a processor to input input data including sampling data of some of a plurality of semiconductor dies of a wafer to a generator network of the image generation model and output a wafer map indicating the plurality of semiconductor dies, and to input the wafer map output from the generator network to a discriminator network of the image generation model and discriminate the wafer map. 1. A non-transitory computer-readable medium storing a program code including an image generation model , which when executed , causes a processor to:input input data including sampling data of some of a plurality of semiconductor dies of a wafer to a generator network of the image generation model and output a wafer map indicating the plurality of semiconductor dies; andinput the wafer map output from the generator network to a discriminator network of the image generation model and discriminate the wafer map.2. The non-transitory computer-readable medium of claim 1 , wherein the image generation model claim 1 , which when executed claim 1 , causes the processor to:arrange the sampling data on the input data depending on locations of the some semiconductor dies of the wafer.3. The non-transitory computer-readable medium of claim 1 , wherein the image generation model claim 1 , which when executed claim 1 , causes the processor to:generate the input data including the sampling data and at least one of a first value determined in advance and a second value based on the sampling data.4. The non-transitory computer-readable medium of claim 3 , wherein the image generation model claim 3 , which when executed claim 3 , causes the processor to:dispose a sampling value of the sampling data on the input data depending on a location of a first semiconductor die of the some semiconductor dies; anddispose the at least one of the first value and the second value on the ...

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Номер записи: 29
10-06-2021 дата публикации

COMPUTING DEVICE, OPERATING METHOD OF COMPUTING DEVICE, AND STORAGE MEDIUM

Номер: US20210174201A1
Автор: HUH IN, Jang Wonik, JEONG Changwook, Myung Sanghoon
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A computing device includes memory storing computer-executable instructions; and processing circuitry configured to execute the computer-executable instructions such that the processing circuitry is configured to operate as a machine learning generator configured to receive semiconductor process parameters, to generate semiconductor process result information from the semiconductor process parameters, and to output the generated semiconductor process result information; and operate as a machine learning discriminator configured to receive the generated semiconductor process result information from the machine learning generator and to discriminate whether the generated semiconductor process result information is true. 1. A computing device comprising:memory storing computer-executable instructions; and operate as a machine learning generator configured to receive semiconductor process parameters, to generate semiconductor process result information from the semiconductor process parameters, and to output the generated semiconductor process result information; and', 'operate as a machine learning discriminator configured to receive the generated semiconductor process result information from the machine learning generator and to generate a discrimination result by discriminating whether the generated semiconductor process result information is true., 'processing circuitry configured to execute the computer-executable instructions such that the processing circuitry is configured to'}2. The computing device of claim 1 , wherein the processing circuitry is further configured to execute the computer-executable instructions such that at least one of the machine learning generator and the machine learning discriminator is further configured to perform learning to update an algorithm based on the discrimination result.3. The computing device of claim 1 , wherein the processing circuitry is further configured to execute the computer-executable instructions such that the ...

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Номер записи: 30
04-06-2020 дата публикации

SEMICONDUCTOR WAFER FAULT ANALYSIS SYSTEM AND OPERATION METHOD THEREOF

Номер: US20200175665A1
Автор: JEONG Changwook, MA Ami, PARK Min-chul, Ryu Jisu
Принадлежит:

A semiconductor wafer fault analysis system includes: a database to store a first reference map, which is classified as a first fault type, and a second reference map, which is classified as a second fault type; a first auto-encoder/decoder to remove a noise corresponding to the first fault type from the first reference map to generate a first pre-processed reference map; a second auto-encoder/decoder to remove a noise corresponding to the second fault type from the second reference map to generate a second pre-processed reference map; and a fault type analyzer. The database is updated based on the first and second pre-processed reference maps, and the fault type analyzer is to classify a fault type of a target map based on the updated database. The target map is generated by measuring a target wafer. 1. A semiconductor wafer fault analysis system comprising:a database to store a first reference map, which is classified as a first fault type, and a second reference map, which is classified as a second fault type;a first auto-encoder/decoder to remove a noise corresponding to the first fault type from the first reference map to generate a first pre-processed reference map;a second auto-encoder/decoder to remove a noise corresponding to the second fault type from the second reference map to generate a second pre-processed reference map; anda fault type analyzer, wherein:the database is updated based on the first and second pre-processed reference maps, andthe fault type analyzer is to classify a fault type of a target map based on the updated database, the target map being generated by measuring a target wafer.2. The semiconductor wafer fault analysis system as claimed in claim 1 , further comprising:a first thresholder to perform a thresholding operation on the first pre-processed reference map based on information of the first fault type to generate a first thresholding reference map; anda second thresholder to perform a thresholding operation on the second pre- ...

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Номер записи: 31
19-11-2020 дата публикации

METHOD AND APPARATUS WITH SYSTEM VERIFICATION BASED ON REINFORCEMENT LEARNING

Номер: US20200364314A1
Автор: CHOI Hyojin, HUH IN, JEONG Changwook, KIM Seungju, LEE Jaecheol, Lee Jun Haeng, Lee Yongwoo, OH Youngmin, PARK Hyun Sun, PARK Younsik
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A system verification method includes generating a first verification vector as a result of a first action of an agent, the first verification vector referring to an observation corresponding to at least one state already covered, from among states of elements of a target system, identifying a first coverage corresponding to at least one state covered by the first verification vector, from among the states of the elements, updating the observation by reflecting the first coverage in the observation, and generating a second verification vector through a second action of the agent, the second verification vector referring to the updated observation. 1. A system verification method , comprising:generating a first verification vector as a result of a first action of an agent, the first verification vector referring to an observation corresponding to at least one state already covered, from among states of elements of a target system;identifying a first coverage corresponding to at least one state covered by the first verification vector, from among the states of the elements;updating the observation by reflecting the first coverage in the observation; andgenerating a second verification vector through a second action of the agent, the second verification vector referring to the updated observation.2. The system verification method of claim 1 , further comprising training the agent based on the second verification vector.3. The system verification method of claim 1 , wherein the generating of the first verification vector comprises generating the first verification vector using a template corresponding to a combination of commands used in the target system.4. The system verification method of claim 1 , further comprising:adding first action information related to the first action to an action pool, in response to the first action information being absent from the action pool.5. The system verification method of claim 4 , further comprising:generating a training data set ...

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Номер записи: 32
19-12-2019 дата публикации

SEMICONDUCTOR FAULT ANALYSIS DEVICE AND FAULT ANALYSIS METHOD THEREOF

Номер: US20190385695A1
Автор: Jang Hyunjae, JEON Min Chul, JEONG Changwook, Kim Hyungtae, KO JEONGHOON, LI Yunrong, Myung Sanghoon, PARK Min-chul, Ryu Jisu
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type. 1. A fault analysis method of a semiconductor fault analysis device , the fault analysis method comprising:receiving measurement data measured from a semiconductor device included in a semiconductor wafer;generating double sampling data based on the measurement data and reference data;performing a fault analysis operation with respect to the double sampling data;classifying a fault type of the semiconductor device based on a result of the fault analysis operation; andoutputting information about the fault type.2. The fault analysis method of claim 1 , wherein the reference data are data associated with at least one normal current-voltage curve corresponding to a normal state of the semiconductor device claim 1 , andwherein the measurement data are data associated with at least one measured current-voltage curve measured from the semiconductor device.3. The fault analysis method of claim 1 , wherein the double sampling data correspond to a difference between the measurement data and the reference data.4. The fault analysis method of claim 1 , wherein the fault analysis operation is based on a deep neural network algorithm claim 1 , andthe fault analysis method further comprises:generating training data based on the reference data and fault data associated with each of a plurality of fault types of the semiconductor device; andperforming pre-training based on the training data to generate a training model for the deep neural network algorithm.5. The fault analysis method ...

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Номер записи: 33
04-05-2023 дата публикации

Method and system for three-dimensional modeling

Номер: US20230136021A1
Автор: Changwook Jeong, Jaemyung Choe, Sanghoon MYUNG, Wonik JANG
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A three-dimensional (3D) modeling method includes obtaining geometric data representing a 3D structure and input parameters including factors determining an attribute of the 3D structure, generating grid data from the geometric data, sequentially generating at least one piece of down-sampled data from the grid data, pre-processing the input parameters to generate a 3D feature map, and generating attribute profile data, representing a profile of the attribute in the 3D structure, from the at least one piece of down-sampled grid data and the 3D feature map based on at least one machine learning model respectively corresponding to at least one stage.

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Номер записи: 34
01-06-2023 дата публикации

Computing device and method generating optimal input data

Номер: US20230169240A1
Автор: Byoungseon Choi, Changwook Jeong, Jaemyung Choe, Jaesik An, Jinwoo Kim, Jisu Ryu, Sanghoon MYUNG, Yunjun Nam
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of generating optimal input data for a design simulator providing output data related to output parameters in response to input data related to input parameters. The method includes; generating training data including sample input data and sample output data, selecting at least one essential input parameter affecting a plurality of output parameters from among the input parameters in accordance with an estimation model trained using the training data, and generating the optimal input data in accordance with essential input data corresponding to the at least one essential input parameter and the sample output data.

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Номер записи: 35
18-05-2023 дата публикации

Learning method and system for object tracking based on hybrid neural network

Номер: US20230153624A1
Автор: Bo Hyung Han, Changwook Jeong, Daeyoung Park, Il Chae Jung, Moon Hyun Cha
Принадлежит: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

An object tracking learning system includes a first neural network module that expresses and learns a first parameter for an input image from a first type to a second type and outputs the learned result as a first learning result, a second neural network module that removes and learns a connection of a part of a second parameter for the input image and outputs the learned result as a second learning result, a prediction module that generates a prediction value for an object of the input image from a summation result obtained by summing the first learning result and the second learning result, and an optimization module that updates the first parameter and the second parameter based on the prediction value.

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Номер записи: 36
24-11-2022 дата публикации

Data processing method of detecting and recovering missing values, outliers and patterns in tensor stream data

Номер: US20220374498A1
Автор: Changwook Jeong, Dongjin Lee, Kijung Shin
Принадлежит: Korea Advanced Institute of Science and Technology KAIST, SAMSUNG ELECTRONICS CO LTD

A tensor data processing method is provided. The method comprises receiving an input tensor including at least one of an outlier and a missing value, the input tensor being input during a time interval between a first time point and a second time point, factorizing the input tensor into a low rank tensor to extract a temporal factor matrix, calculating trend and periodic pattern from the extracted temporal factor matrix, detecting the outlier which is out of the calculated trend and periodic pattern, updating the temporal factor matrix except the detected outlier, combining the updated temporal factor matrix and a non-temporal factor matrix of the input tensor to calculate the real tensor and recovering the input tensor by setting data corresponding to a position of the outlier or a position of the missing value of the input tensor from the data of the real tensor as an estimated value.

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Номер записи: 37
27-06-2024 дата публикации

Electrification of heat supply to fluidized regeneration system

Номер: WO2024137859A1
Автор: Changwook Jeong, Kyung Taek Han, Manoj NAGVEKAR, Matthew James Griffiths, Michael J. Tallman, Rian Reyneke
Принадлежит: Kellogg Brown & Root LLC

A system for reactivating a catalyst having a predetermined heat content includes a reactor, a regenerator, and an electrically energized heater. The reactor is configured to generate a spent catalyst. The regenerator is configured to receive the spent catalyst from the reactor. The electrically energized heater has a plurality of energy emitting members at least partially immersed in the spent catalyst. The heater is configured to provide a supplemental heat content to obtain the predetermined heat content.

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Номер записи: 38