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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 31. Отображено 27.
20-03-2018 дата публикации

Array of optoelectronic structures and fabrication thereof

Номер: US0009923022B2
Автор: Mattias B. Borg, Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara, Heike E. Riel, Heinz Schmid, BORG MATTIAS B, CZORNOMAZ LUKAS, DESHPANDE VEERESH V, DJARA VLADIMIR, RIEL HEIKE E, SCHMID HEINZ, Borg Mattias B., Czornomaz Lukas, Deshpande Veeresh V., Djara Vladimir, Riel Heike E., Schmid Heinz
Принадлежит: International Business Machines Corporation, IBM

A method of fabrication of an array of optoelectronic structures. The method first provides a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells comprises an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portionsthat coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.

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Номер записи: 1
20-09-2016 дата публикации

Dual pulse driven extreme ultraviolet (EUV) radiation source method

Номер: US0009451684B2
Автор: Daniel A. Corliss, Sadanand V. Deshpande, Veeresh V. Deshpande, Oleg Gluschenkov, Sivarama Krishnan, CORLISS DANIEL A, DESHPANDE SADANAND V, DESHPANDE VEERESH V, GLUSCHENKOV OLEG, KRISHNAN SIVARAMA, Corliss Daniel A., Deshpande Sadanand V., Deshpande Veeresh V., Gluschenkov Oleg, Krishnan Sivarama
Принадлежит: International Business Machines Corporation, IBM

An extreme ultraviolet (EUV) radiation source pellet includes at least one metal particle embedded within a heavy noble gas cluster contained within a noble gas shell cluster. The EUV radiation source assembly can be activated by a sequential irradiation of at least one first laser pulse and at least one second laser pulse. Each first laser pulse generates plasma by detaching outer orbital electrons from the at least one metal particle and releasing the electrons into the heavy noble gas cluster. Each second laser pulse amplifies the plasma embedded in the heavy noble gas cluster triggering a laser-driven self-amplifying process. The amplified plasma induces inter-orbital electron transitions in heavy noble gas and other constitute atoms leading to emission of EUV radiation. The laser pulsing units can be combined with a source pellet generation unit to form an integrated EUV source system.

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Номер записи: 2
27-04-2017 дата публикации

OPTICAL SYNAPSE FOR NEUROMORPHIC NETWORKS

Номер: US20170116514A1
Автор: Stefan Abel, Lukas Czomomaz, Veeresh V. Deshpande, Jean Fompeyrine, ABEL STEFAN, CZOMOMAZ LUKAS, DESHPANDE VEERESH V, FOMPEYRINE JEAN, Abel Stefan, Czomomaz Lukas, Deshpande Veeresh V., Fompeyrine Jean
Принадлежит:

A neuromorphic network includes a first node configured to transmit a first optical signal and a second node configured to transmit a second optical signal. A waveguide optically connects the first node to the second node. An integrated optical synapse is located on the waveguide between the first node and the second node, the optical synapse configured to change an optical property based on the first optical signal and the second optical signal such that if a correlation between the first optical signal and the second optical signal is strong, the optical connection between the first node and the second node is increased and if the correlation between the first optical signal and the second optical signal is weak, the optical connection between the first node and the second node is decreased. 1. A neuromorphic network , comprising:a first node configured to transmit a first optical signal;a second node configured to transmit a second optical signal;a waveguide optically connecting the first node to the second node; andan integrated optical synapse located on the waveguide between the first node and the second node, the optical synapse comprising an optical property that is configured to change a strength of an optical connection between the first node and the second node based on a correlation between the first optical signal and the second optical signal,wherein based on a determination that the correlation is strong, the strength of the optical connection between the first node and the second node is increased and based on a determination that the correlation is weak, the strength of the optical connection between the first node and the second node is decreased.2. The neuromorphic network of claim 1 , further comprising a first detector configured to receive a portion of the first optical signal and a second detector configured to receive a portion of the second optical signal claim 1 , wherein the first detector and the second detector are configured to transmit ...

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Номер записи: 3
13-03-2018 дата публикации

Fabricating raised source drain contacts of a CMOS structure

Номер: US0009917164B1
Автор: Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara, CZORNOMAZ LUKAS, DESHPANDE VEERESH V, DJARA VLADIMIR, Czornomaz Lukas, Deshpande Veeresh V., Djara Vladimir
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.

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Номер записи: 4
14-02-2017 дата публикации

Resistive memory device

Номер: US9570169B1
Автор: CZORNOMAZ LUKAS, DESHPANDE VEERESH V, JONNALAGADDA VARA SUDANANDA PRASAD, KOELMANS WABE, SEBASTIAN ABU, Czornomaz Lukas, Deshpande Veeresh V., Jonnalagadda Vara Sudananda Prasad, Koelmans Wabe, Sebastian Abu
Принадлежит: IBM, International Business Machines Corporation

A memory device includes a plurality of memory cells and a control unit. The memory cells include a first segment including a resistive memory material for storing information in a plurality of resistance states, a second segment including a non-insulating material, a first terminal, a second terminal, and a third terminal. The first segment and the second segment are arranged in parallel between the first terminal and the second terminal. The control unit is configured to apply in a write mode a write voltage to the first and the second terminal for writing the resistance state, and to apply in a read mode a read voltage to the first and the second terminal for reading the resistance state, and to apply a control signal to the third terminal for adjusting the electrical resistance of the second segment. A related method and control unit are also disclosed.

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Номер записи: 5
20-04-2017 дата публикации

MODIFYING DESIGN LAYER OF INTEGRATED CIRCUIT (IC)

Номер: US20170108769A1
Автор: Veeresh V. Deshpande, Howard S. Landis, Arun Sankar Mampazhy, Neelima Mandloi, DESHPANDE VEERESH V, LANDIS HOWARD S, MAMPAZHY ARUN SANKAR, MANDLOI NEELIMA, Deshpande Veeresh V., Landis Howard S., Mampazhy Arun Sankar, Mandloi Neelima
Принадлежит: International Business Machines Corp

Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.

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Номер записи: 6
27-04-2017 дата публикации

TUNABLE OPTICAL NEUROMORPHIC NETWORK

Номер: US20170116515A1
Автор: Stefan Abel, Lukas Czomomaz, Veeresh V. Deshpande, Jean Fompeyrine, ABEL STEFAN, CZOMOMAZ LUKAS, DESHPANDE VEERESH V, FOMPEYRINE JEAN, Abel Stefan, Czomomaz Lukas, Deshpande Veeresh V., Fompeyrine Jean
Принадлежит:

A reservoir computing neuromorphic network includes an input layer comprising one or more input nodes, a reservoir layer comprising a plurality of reservoir nodes, and an output layer comprising one or more output nodes. A portion of at least one of the input layer, the reservoir layer, and the output layer includes an optically tunable material. 1. A reservoir computing neuromorphic network , comprising:an input layer comprising one or more input nodes;a reservoir layer comprising a plurality of reservoir nodes; andan output layer comprising one or more output nodes,wherein a portion of at least one of the input layer, the reservoir layer, and the output layer includes an optically tunable material.2. The reservoir computing neuromorphic network of claim 1 , wherein the input layer claim 1 , the reservoir layer claim 1 , and the output layer form a first block claim 1 , the reservoir computing neuromorphic network further comprising:a second block having a second input layer comprising one or more second input nodes, a second reservoir layer comprising a plurality of second reservoir nodes, and a second output layer comprising one or more second output nodes, wherein at least one of the second input layer, the second reservoir layer, and the second output layer is formed from an optically tunable material, andwherein an input to the second block is an output of the first block.3. The reservoir computing neuromorphic network of claim 1 , wherein each of the input layer claim 1 , the output layer claim 1 , and the reservoir layer includes an optically tunable material.4. The reservoir computing neuromorphic network of claim 1 , wherein the optically tunable material is a III-V semiconductor material claim 1 , a photorefractive material claim 1 , an optically nonlinear material claim 1 , a phase change material claim 1 , or a magneto-optical material.5. The reservoir computing neuromorphic network of claim 1 , wherein the input layer is formed from photonic crystals.6 ...

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Номер записи: 7
04-01-2018 дата публикации

Array of optoelectronic structures and fabrication thereof

Номер: US20180006069A1
Автор: Heike E. Riel, Heinz Schmid, Lukas Czornomaz, Mattias B. Borg, Veeresh V. Deshpande, Vladimir DJARA
Принадлежит: International Business Machines Corp

A method of fabrication of an array of optoelectronic structures. The method first provides a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells comprises an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portions that coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.

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Номер записи: 8
02-01-2020 дата публикации

Buried electrode geometry for lowering surface losses in superconducting microwave circuits

Номер: US20200006619A1
Автор: Andreas Fuhrer, Andreas Kuhlmann, Marc Ganzhorn, Stefan FILIPP, Ute Drechsler, Veeresh V. Deshpande
Принадлежит: International Business Machines Corp

Embodiments are directed to a superconducting microwave circuit. The circuit includes a substrate and two electrodes. The latter form an electrode pair dimensioned so as to support an electromagnetic field, which allows the circuit to be operated in the microwave domain. The substrate exhibits a raised portion, which includes a top surface and two lateral surfaces. The top surface connects the two lateral surfaces, which show respective undercuts (on the lateral sides of the raised portions). Each of the electrodes includes a structure that includes a potentially superconducting material. Two protruding structures are accordingly formed, which are shaped complementarily to the respective undercuts. This way, the shaped structure of each of the electrodes protrudes toward the other one of the electrodes of the pair.

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Номер записи: 9
17-03-2016 дата публикации

Dual pulse driven extreme ultraviolet (euv) radiation source utilizing a droplet comprising a metal core with dual concentric shells of buffer gas

Номер: US20160081174A1
Автор: Daniel A. Corliss, Oleg Gluschenkov, Sadanand V. Deshpande, Sivarama Krishnan, Veeresh V. Deshpande
Принадлежит: International Business Machines Corp

An extreme ultraviolet (EUV) radiation source pellet includes at least one metal particle embedded within a heavy noble gas cluster contained within a noble gas shell cluster. The EUV radiation source assembly can be activated by a sequential irradiation of at least one first laser pulse and at least one second laser pulse. Each first laser pulse generates plasma by detaching outer orbital electrons from the at least one metal particle and releasing the electrons into the heavy noble gas cluster. Each second laser pulse amplifies the plasma embedded in the heavy noble gas cluster triggering a laser-driven self-amplifying process. The amplified plasma induces inter-orbital electron transitions in heavy noble gas and other constitute atoms leading to emission of EUV radiation. The laser pulsing units can be combined with a source pellet generation unit to form an integrated EUV source system.

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Номер записи: 10
28-06-2018 дата публикации

MODIFYING DESIGN LAYER OF INTEGRATED CIRCUIT (IC)

Номер: US20180180989A1
Автор: Deshpande Veeresh V., Landis Howard S., Mampazhy Arun Sankar, Mandloi Neelima
Принадлежит:

Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer. 1. A computer program product comprising program code stored on a computer readable storage medium , which when executed by at least one computing device , causes the at least one computing device to modify a design layer of an integrated circuit (IC) by perform actions including:identifying at least one empty region in the design layer used to form the IC;determining whether the at least one empty region requires a fill object;identifying a first area of the design layer requiring a nested fill object and a second area of the input design layer requiring a non-nested fill object in response to determining the at least one empty region requires the fill object;placing the nested fill object in the first area and the non-nested fill object in the second area;performing one of a simplified optical proximity correction (OPC) or no OPC on the nested fill object, and a complete OPC on the non-nested fill object and the design layer; andgenerating a modified design layer including a corrected version of the design layer and modified nested fill objects and non-nested fill objects after the performing of the simplified OPC or no OPC on ...

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Номер записи: 11
05-07-2018 дата публикации

Array of optoelectronic structures and fabrication thereof

Номер: US20180190693A1
Автор: Heike E. Riel, Heinz Schmid, Lukas Czornomaz, Mattias B. Borg, Veeresh V. Deshpande, Vladimir DJARA
Принадлежит: International Business Machines Corp

A method of fabrication of an array of optoelectronic structures includes first providing a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells includes an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portions that coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.

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Номер записи: 12
14-07-2016 дата публикации

DUAL PULSE DRIVEN EXTREME ULTRAVIOLET (EUV) RADIATION SOURCE

Номер: US20160205757A1
Автор: Corliss Daniel A., Deshpande Sadanand V., Deshpande Veeresh V., Gluschenkov Oleg, Krishnan Sivarama
Принадлежит:

An extreme ultraviolet (EUV) radiation source pellet includes at least one metal particle embedded within a heavy noble gas cluster contained within a noble gas shell cluster. The EUV radiation source assembly can be activated by a sequential irradiation of at least one first laser pulse and at least one second laser pulse. Each first laser pulse generates plasma by detaching outer orbital electrons from the at least one metal particle and releasing the electrons into the heavy noble gas cluster. Each second laser pulse amplifies the plasma embedded in the heavy noble gas cluster triggering a laser-driven self-amplifying process. The amplified plasma induces inter-orbital electron transitions in heavy noble gas and other constitute atoms leading to emission of EUV radiation. The laser pulsing units can be combined with a source pellet generation unit to form an integrated EUV source system. 1. A method for generating an extreme ultraviolet (EUV) radiation , said method comprising: at least one metallic particle;', 'a heavy noble gas cluster embedding said at least one metallic particle; and', 'a noble gas shell cluster embedding said heavy noble gas cluster and containing a cluster of a light noble gas selected from He, Ne, and Ar; and, 'forming a plurality of extreme ultraviolet (EUV) radiation pellets within an EUV source pellet generator, said plurality of EUV radiation pellets comprisingirradiating said plurality of EUV radiation pellets with at least one irradiation source, wherein each of said at least one irradiation source is configured to irradiate a laser beam toward a path of said EUV radiation pellets.2. The method of claim 1 , wherein said at least one irradiation source comprises:a first laser source configured to irradiate a first laser beam at a first point in said path of said plurality of EUV radiation pellets; anda second laser source configured to irradiate a second laser beam at a second point in said path of said plurality of EUV radiation ...

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Номер записи: 13
11-10-2018 дата публикации

FABRICATING CONTACTS OF A CMOS STRUCTURE

Номер: US20180294193A1
Автор: Czornomaz Lukas, Deshpande Veeresh V., DJARA Vladimir, Hashemi Pouya
Принадлежит:

The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product. 1. A semiconductor device comprising:a substrate with a channel layer;a gate stack structure disposed on the channel layer;a raised source and a raised drain disposed on the channel layer;an oxide layer disposed on one or more portions of the semiconductor device; anda self-aligned contact disposed on the raised source and the raised drain.2. A semiconductor device as claimed in claim 1 , wherein the gate stack structure comprises:a gate dielectric layer;a gate metal layer;a gate cap layer deposited on the gate metal layer; andsidewall spacers.3. A semiconductor device as claimed in claim 1 , further comprising:a first dummy gate stack structure adjacent to the raised source and a second dummy gate stack structure adjacent to the raised drain.4. A semiconductor device as claimed in claim 1 , further comprising:a liner on one or more portions of the semiconductor device, the gate stack structure, the raised source and the raised drain.5. A semiconductor device as claimed in claim 4 , wherein the liner comprises a material selected from the group consisting of: AlO claim 4 , HfO claim 4 , ZrO claim 4 , AlON claim 4 , SiO ...

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Номер записи: 14
11-10-2018 дата публикации

FABRICATING RAISED SOURCE DRAIN CONTACTS OF A CMOS STRUCTURE

Номер: US20180294338A1
Автор: Czornomaz Lukas, Deshpande Veeresh V., DJARA Vladimir
Принадлежит:

The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product. 1. A method for forming a field effect transistor , the method comprising:providing a substrate with a channel layer;forming a gate stack structure on the channel layer;forming first sidewall spacers;forming a raised source and a raised drain on the channel layer;forming second sidewall spacers above the raised source and the raised drain;depositing an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers;planarization of the insulating dielectric layer;selectively etching the second sidewall spacers, thereby creating contact cavities above the raised source and the raised drain; and depositing a metal layer; and', 'planarization of the metal layer., 'forming a source contact and a drain contact by filling the contact cavities, wherein forming the source contact and the drain contact comprises2. (canceled)3. A method as claimed in claim 1 , wherein depositing the metal layer is performed by chemical vapor deposition claim 1 , physical vapor deposition claim 1 , atomic layer deposition claim 1 , plasma enhanced atomic layer ...

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Номер записи: 15
17-10-2019 дата публикации

OPTICAL SYNAPSE

Номер: US20190318233A1
Автор: Abel Stefan, Deshpande Veeresh V., Fompeyrine Jean
Принадлежит:

An integrated optical circuit for an optical neural network is provided. The integrated optical circuit is configured to process a phase-encoded optical input signal and to provide a phase-encoded output signal depending on the phase-encoded optical input signal. The phase-encoded output signal emulates a synapse functionality with respect to the phase-encoded optical input signal. A related method and a related design structure are further provided. 1. An integrated optical circuit for an optical neural network , the optical circuit being configured:to process a phase-encoded optical input signal; andto provide a phase-encoded optical output signal depending on the phase-encoded optical input signal, the phase-encoded optical output signal emulating a synapse functionality with respect to the phase-encoded optical input signal.2. The integrated optical circuit according to claim 1 , wherein the integrated optical circuit is configured:to convert the phase-encoded optical input signal into an amplitude-encoded signal;to perform a weighting of the amplitude-encoded signal; andto convert the weighted amplitude-encoded signal into the phase-encoded optical output signal.3. The integrated optical circuit according to claim 1 , further comprising:a reference waveguide configured to carry an optical reference signal;an input waveguide configured to receive the phase-encoded optical input signal, wherein a phase difference between the optical reference signal and the optical input signal represents the phase of the phase encoded optical input signal;an output waveguide;an optical interferometer configured to convert the optical reference signal and the optical input signal into an interference signal by superimposition;a tunable attenuator configured to perform a weighting of the interference signal into a weighted interference signal; anda phase-shifting device configured to convert the weighted interference signal into the phase-encoded optical output signal by inducing ...

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Номер записи: 16
17-10-2019 дата публикации

Optical neuron

Номер: US20190318234A1
Автор: Jean Fompeyrine, Stefan Abel, Veeresh V. Deshpande
Принадлежит: International Business Machines Corp

An integrated optical circuit for an optical neural network is provided. The optical circuit is configured to process a plurality of phase-encoded optical input signals and to provide a phase-encoded optical output signal depending on the phase-encoded optical input signals. The phase-encoded optical output signal emulates a neuron functionality with respect to the plurality of phase-encoded optical input signals. Such an embodied optical circuit uses the phase to encode information in the optical domain. A related method and a related design structure are further provided.

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Номер записи: 17
06-12-2018 дата публикации

FABRICATING RAISED SOURCE DRAIN CONTACTS OF A CMOS STRUCTURE

Номер: US20180350925A1
Автор: Czornomaz Lukas, Deshpande Veeresh V., DJARA Vladimir
Принадлежит:

The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product. 1. A method for forming a field effect transistor , the method comprising:providing a substrate with a channel layer;forming a gate stack structure on the channel layer;forming first sidewall spacers;forming a raised source and a raised drain on the channel layer;depositing in a conformal way a liner on the gate stack structure, the raised source and the raised drain;forming second sidewall spacers above the raised source and the raised drain;depositing an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers;planarization of the insulating dielectric layer;selectively etching the second sidewall spacers, thereby creating contact cavities above the raised source and the raised drain; andforming a source contact and a drain contact by filling the contact cavities.2. A method as claimed in claim 1 , wherein forming the source contact and the drain contact comprises:depositing a metal layer; andplanarization of the metal layer.3. A method as claimed in claim 2 , wherein depositing the metal layer is performed by chemical vapor ...

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Номер записи: 18
21-12-2017 дата публикации

DESIGN/TECHNOLOGY CO-OPTIMIZATION PLATFORM FOR HIGH-MOBILITY CHANNELS CMOS TECHNOLOGY

Номер: US20170364623A1
Автор: Caimi Daniele, Czornomaz Lukas, Deshpande Veeresh V., DJARA Vladimir, Fompeyrine Jean
Принадлежит:

Embodiments of the present invention may provide the capability to design SRAM cells may be designed that is compatible with the requirements of InGaAs integration by selective epitaxy in SiOcavities without sacrificing density and area scaling. In an embodiment of the present invention, a computer-implemented method for designing a hybrid integrated circuit may comprise receiving data representing a layout of a static random-access memory cell array, identifying areas between active channel regions that do not overlap with transistor gates of static random-access memory cells of the static random-access memory cell array, selecting from among the identified areas at least one area, expanding the selected areas to determine whether the expanded area intersects with a p-doped active Si semiconductor or p-channel semiconductor area, and marking as Si seed locations the identified expanded areas that do not intersect on both sides with a channel active transistor region. 1. A computer-implemented method for designing a hybrid integrated circuit comprising:receiving data representing a layout of a static random-access memory cell array;identifying areas between active channel regions that do not overlap with transistor gates of static random-access memory cells of the static random-access memory cell array;selecting from among the identified areas at least one area;expanding the selected areas to determine whether the expanded area intersects with a p-doped active Si semiconductor or p-channel semiconductor area; andmarking as Si seed locations the identified expanded areas that do not intersect on both sides with a channel active transistor region.2. The method of claim 1 , wherein each selected area is expanded length-wise claim 1 , width-wise claim 1 , or both claim 1 , to a maximum area or by a pre-determined amount.3. The method of claim 1 , wherein the hybrid integrated circuit comprises Si or SiGe static random-access memory circuits and a III-V semiconductor ...

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Номер записи: 19
17-10-2019 дата публикации

Optical neuron

Номер: WO2019197134A1
Автор: Jean Fompeyrine, Stefan Abel, Veeresh V. Deshpande
Принадлежит: IBM Deutschland GmbH, INTERNATIONAL BUSINESS MACHINES CORPORATION

An integrated optical circuit for an optical neural network is provided. The optical circuit is configured to process a plurality of phase-encoded optical input signals and to provide a phase-encoded optical output signal depending on the phase-encoded optical input signals. The phase-encoded optical output signal emulates a neuron functionality with respect to the plurality of phase-encoded optical input signals. Such an embodied optical circuit uses the phase to encode information in the optical domain. A related method and a related design structure are further provided.

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Номер записи: 20
24-02-2021 дата публикации

Optical neuron

Номер: EP3782086A1
Автор: Jean Fompeyrine, Stefan Abel, Veeresh V. Deshpande
Принадлежит: International Business Machines Corp

An integrated optical circuit for an optical neural network is provided. The optical circuit is configured to process a plurality of phase-encoded optical input signals and to provide a phase-encoded optical output signal depending on the phase-encoded optical input signals. The phase-encoded optical output signal emulates a neuron functionality with respect to the plurality of phase-encoded optical input signals. Such an embodied optical circuit uses the phase to encode information in the optical domain. A related method and a related design structure are further provided.

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Номер записи: 21
24-02-2021 дата публикации

Optical synapse

Номер: EP3782085A1
Автор: Jean Fompeyrine, Stefan Abel, Veeresh V. Deshpande
Принадлежит: International Business Machines Corp

An integrated optical circuit for an optical neural network is provided. The integrated optical circuit is configured to process a phase-encoded optical input signal and to provide a phase-encoded output signal depending on the phase-encoded optical input signal. The phase-encoded output signal emulates a synapse functionality with respect to the phase-encoded optical input signal. A related method and a related design structure are further provided.

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Номер записи: 22
17-10-2019 дата публикации

Optical synapse

Номер: WO2019197135A1
Автор: Jean Fompeyrine, Stefan Abel, Veeresh V. Deshpande
Принадлежит: IBM Deutschland GmbH, INTERNATIONAL BUSINESS MACHINES CORPORATION

An integrated optical circuit for an optical neural network is provided. The integrated optical circuit is configured to process a phase-encoded optical input signal and to provide a phase-encoded output signal depending on the phase-encoded optical input signal. The phase-encoded output signal emulates a synapse functionality with respect to the phase-encoded optical input signal. A related method and a related design structure are further provided.

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Номер записи: 23
12-06-2018 дата публикации

Fabricating contacts of a CMOS structure

Номер: US09997409B1
Автор: Lukas Czornomaz, Pouya Hashemi, Veeresh V. Deshpande, Vladimir DJARA
Принадлежит: International Business Machines Corp

The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.

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Номер записи: 24
29-05-2018 дата публикации

Fabricating contacts of a CMOS structure

Номер: US09984929B1
Автор: Lukas Czornomaz, Pouya Hashemi, Veeresh V. Deshpande, Vladimir DJARA
Принадлежит: International Business Machines Corp

The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.

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Номер записи: 25
22-05-2018 дата публикации

Modifying design layer of integrated circuit (IC)

Номер: US09977325B2
Автор: Arun Sankar Mampazhy, Howard S. Landis, Neelima Mandloi, Veeresh V. Deshpande
Принадлежит: International Business Machines Corp

Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.

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Номер записи: 26
24-04-2018 дата публикации

Design/technology co-optimization platform for high-mobility channels CMOS technology

Номер: US09953125B2
Автор: Daniele Caimi, Jean Fompeyrine, Lukas Czornomaz, Veeresh V. Deshpande, Vladimir DJARA
Принадлежит: International Business Machines Corp

Embodiments of the present invention may provide the capability to design SRAM cells may be designed that is compatible with the requirements of InGaAs integration by selective epitaxy in SiO 2 cavities without sacrificing density and area scaling. In an embodiment of the present invention, a computer-implemented method for designing a hybrid integrated circuit may comprise receiving data representing a layout of a static random-access memory cell array, identifying areas between active channel regions that do not overlap with transistor gates of static random-access memory cells of the static random-access memory cell array, selecting from among the identified areas at least one area, expanding the selected areas to determine whether the expanded area intersects with a p-doped active Si semiconductor or p-channel semiconductor area, and marking as Si seed locations the identified expanded areas that do not intersect on both sides with a channel active transistor region.

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Номер записи: 27