Sealing electronic packages containing bumped hybrids

A method of packaging hybrid wafers or die that are interconnected using soft metal bumps, such as indium, in a sealed ceramic package. The present invention passivates the hybrid die that are to be interconnected by way of the bumps, so that the metal in the bumps (indium) does not wet the surface of the hybrid die when the ceramic package is sealed at high temperature. Vias are formed in the passivated surfaces to expose underlying contact areas. Bumps are then formed on the contact areas, and the bumped and passivated hybrid die are electrically interconnected. The ceramic package containing the electrically interconnected hybrid die is processed at a temperature above the melting temperature of the bumps to attach a ceramic cover to the ceramic package. The method is performed at a temperature well in excess of the melting temperature of the bumps (∼155° Celsius for indium), typically on the order of 325° Celsius. The surface tension of the indium maintains the bump structure and electrical ...

Non-destructive read ferroelectric memory cell utilizing the ramer-drab effect

A memory cell is constructed using a ferroelectric capacitor having an insulator formed of a ferroelectric material that has a zero field capacitance which is controllably dependent upon the electrical charging path by which the zero field capacitance is reached. Preferably, the material is characterized by a first zero field capacitance following saturation of the polarization by a first applied voltage applied in a first polarization direction, and a second zero field capacitance following saturation of the polarization by the first applied voltage applied in the first polarization direction followed by partial depolarization by a second voltage applied in a direction opposite to the first polarization direction. A second ferroelectric capacitor or a linear capacitor may be placed in parallel with the ferroelectric capacitor to form a two-capacitor memory cell. Data may be read to or from the capacitor cell without impairing the state of the stored data.

Bismuth layered structure pyroelectric detectors

This invention teaches a method for fabricating an array (1) of pyroelectric detectors (10), and further teaches an array (1) of pyroelectric detectors (10) that include a bismuth layered compound. The array has a substrate (12) and a plurality of pyroelectric detector sites disposed over a surface of the substrate. Each of the pyroelectric detector sites is constructed to have a first electrode (16); a second electrode (20); and a thin layer (18) containing a bismuth layered compound that is interposed between and electrically coupled to the first and second electrodes. In one embodiment the thin layer is comprised of Y1 material (SrBi2 Ta2 O9), while in another embodiment the layer is comprised instead of YZ material (SrBi2 Nb2-x Tax O9).

Nondestructive readout memory utilizing ferroelectric capacitors isolated from bitlines by buffer amplifiers

A memory includes a bitline data signal input (24), at least one memory unit (20), a writing circuit (128) which writes a polarization state into each memory unit (20) responsive to the bitline data signal input, and a sensing circuit (130) that senses a polarization state of each memory unit (20). Each memory unit (20) includes a ferroelectric capacitor (22) and a buffer amplifier (26) in electrical series relationship with the ferroelectric capacitor (22) and the bitline data signal input (24). The buffer amplifier (26) capacitively isolates the ferroelectric capacitor (22) from the bitline data signal input (24) so that the ferroelectric capacitor (22) may be made smaller in size than would otherwise be the case.

Ferroelectric interruptible read memory

A memory includes a first ferroelectric capacitor and a second ferroelectric capacitor electrically connected in a parallel arrangement, and writing circuitry that writes controllably different polarization states into the two ferroelectric capacitors using a single input signal. Read circuitry senses the difference in stored polarizations in the first ferroelectric capacitor and the second ferroelectric capacitor. This sensing circuit causes only a partial switching of the polarization state of the first ferroelectric capacitor and does not disturb the polarization state of the second ferroelectric capacitor. There is a restoration circuit to restore the original ferroelectric polarization of the ferroelectric capacitors following reading.

Non-toxic solvent soluble group IV and V metal acid salt complexes using polyether acid anhydrides

Novel metal acid salt complexes are provided comprising (1) a metal selected from Group IV and Group V metals and (2) a polyether acid, along with a process for making the salt complexes. The process comprises: (a) preparing a polyether acid anhydride from the corresponding polyether acid; and (b) combining a metal alkoxide containing the Group IV or Group V metal with the polyether acid anhydride to form the metal acid salt complex. The resulting Group IV and Group V metal acid salt complexes enable the production of improved thin film, thick film, and bulk ceramic metal oxides and mixed metal oxides for a number of applications, including ferroelectric, electrooptic, paraelectric, and piezoelectric devices, using liquid soluble precursors which are soluble in far less toxic solvents than in the prior art. The soluble ceramic precursors may also be used as reactive binders and shape-forming aids in conventional ceramic processing.

Pin diode structure having surface charge suppression

A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes.

DIRECT BOND METHOD PROVIDING THERMAL EXPANSION MATCHED DEVICES

A method of transferring an integrated circuit (IC) onto an alternative substrate is provided at a wafer level to enable coefficient of thermal expansion (CTE) matching for a circuit layer to a different material. The method is executable relative to a wafer with a circuit layer, a first major surface, a second major surface opposite the first major surface, and a substrate affixed to the first major surface. The method includes temporarily bonding a handle to the second major surface, removing a majority of the substrate to expose the first major surface and bonding a second substrate to the first major surface with deposited bonding material. 1. A wafer level integrated circuit (IC) transfer enabling structure , comprising:a circuit layer having a first major surface and a second major surface opposite the first major surface;a substrate remainder, which is substantially thinner than the circuit layer, affixed to the first major surface;a handle temporarily bonded to the second major surface; anda Sapphire substrate bonded to the first major surface and the substrate remainder with a deposited and polished bonding oxide.2. The structure according to claim 1 , wherein a thermoplastic adhesive temporarily bonds the handle to the second major surface.3. The structure according to claim 1 , wherein the circuit layer is approximately 10 μm thick.4. The structure according to claim 1 , wherein the circuit layer is approximately 10 μm thick and the Sapphire substrate is approximately 1500 μm thick. This application is a divisional of U.S. application Ser. No. 15/331,149 titled “DIRECT BOND METHOD PROVIDING THERMAL EXPANSION MATCHED DEVICES”, which was filed Oct. 21, 2016. The entire contents of U.S. application Ser. No. 15/331,149 are incorporated by reference herein.The present disclosure relates to a direct bond method and to a direct bond method that provides for thermal expansion matched devices for true heterogeneous three-dimensional integration.Many currently used ...

Pin diode structure having surface charge suppression

A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes.

DIRECT BOND METHOD PROVIDING THERMAL EXPANSION MATCHED DEVICES

A method of transferring an integrated circuit (IC) onto an alternative substrate is provided at a wafer level to enable coefficient of thermal expansion (CTE) matching for a circuit layer to a different material. The method is executable relative to a wafer with a circuit layer, a first major surface, a second major surface opposite the first major surface, and a substrate affixed to the first major surface. The method includes temporarily bonding a handle to the second major surface, removing a majority of the substrate to expose the first major surface and bonding a second substrate to the first major surface with deposited bonding material. 1. A method of transferring an integrated circuit (IC) onto an alternative substrate at a wafer level to enable coefficient of thermal expansion (CTE) matching for a circuit layer to a different material ,the method being executable relative to a wafer with a circuit layer, a first major surface, a second major surface opposite the first major surface, and a substrate affixed to the first major surface,the method comprising:temporarily bonding a handle to the second major surface;removing a majority of the substrate to expose the first major surface; andbonding a second substrate to the first major surface with deposited bonding material.2. The method according to claim 1 , wherein the wafer comprises a complementary-metal-oxide-semiconductor (CMOS) wafer.3. The method according to claim 1 , wherein temporarily bonding a handle to the second major surface comprises applying thermoplastic adhesive.4. The method according to claim 1 , wherein removing a substantial portion of the substrate comprises at least one or more of grinding and polishing.5. The method according to claim 1 , wherein removing a substantial portion of the substrate leaves a substrate remainder that is thinner than the circuit layer.6. The method according to claim 1 , wherein the circuit layer is approximately 10 μm thick and removing a substantial portion ...

TILE FOR AN ACTIVE ELECTRONICALLY SCANNED ARRAY (AESA)

In one aspect, an active electronically scanned array (AESA) tile includes a radiator structure and oxide-bonded semiconductor wafers attached to the radiator structure and comprising a radio frequency (RF) manifold and a beam former. An RF signal path through the oxide-bonded wafers comprises a first portion that propagates toward the beam former and a second portion that propagates parallel to the beam former. 1. An active electronically scanned array (AESA) tile comprising:a radiator structure; andoxide-bonded semiconductor wafers attached to the radiator structure and comprising a radio frequency (RF) manifold and a beam former; andwherein an RF signal path through the oxide-bonded wafers comprises a first portion that propagates toward the beam former and a second portion that propagates parallel to the beam former.2. The AESA tile of claim 1 , wherein the RF signal path through the oxide-bonded wafers further comprises a third portion that propagates away from the beam former.3. The AESA tile of claim 1 , wherein the RF signal path further comprises a third path that extends into the beam former and out of the beam former.4. The AESA tile of claim 1 , wherein the oxide-bonded wafers are fused silica.5. The AESA tile of claim 1 , wherein the oxide-bonded wafers comprise metal posts claim 1 , andwherein a metal post from one wafer is connected to a metal post of another wafer.6. The AESA tile of claim 1 , wherein the beam former comprises at least one of a phase shifter claim 1 , an amplifier or an application-specific integrated circuit (ASIC).7. The AESA tile of claim 1 , wherein the beam former is fabricated on silicon germanium (SiGe) wafer.8. The AESA tile of claim 1 , wherein the radiator structure provides radiation shielding for the beam former.9. The AESA tile of claim 1 , wherein the RF manifold propagates RF signals and no DC signals.10. The AESA tile of claim 1 , wherein the beam former includes a redistribution layer to allow for surface mounting to ...

Hybrid sensor chip assembly and method for reducing radiative transfer between a detector and read-out integrated circuit

Aspects and examples described herein provide a hybrid imaging sensor chip assembly for reducing undesired radiative transfer between a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC) and an optical detector, and methods of manufacturing a hybrid imaging sensor chip assembly. In one example, a hybrid imaging sensor chip assembly includes an optical detector configured to collect electromagnetic radiation incident thereon, a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC), and a radiation-shielding wafer interposed between the optical detector and the CMOS ROIC, the radiation-shielding wafer including a plurality of through wafer vias (TWVs) electrically coupled to the optical detector and the CMOS ROIC, the radiation-shielding wafer being positioned to prevent radiative transfer between the CMOS ROIC and the optical detector.

DIE ENCAPSULATION IN OXIDE BONDED WAFER STACK

Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above. 117-. (canceled)18. A method of encapsulating a die into a semiconductor wafer assembly , the method comprising:etching a cavity into an oxide bonded semiconductor wafer stack;positioning a semiconductor die in the cavity;mechanically and electrically mounting the semiconductor die to the wafer stack; andencapsulating the semiconductor die within the cavity by bonding a lid wafer to the wafer stack.19. The method of claim 18 , wherein mechanically and electrically mounting the semiconductor die comprises a process selected from bump bonding claim 18 , wire interconnecting claim 18 , ultrasonic bonding claim 18 , and oxide bonding.20. The method of claim 18 , wherein bonding the lid wafer to the wafer stack further comprises:creating an oxide layer a first surface of the wafer stack;creating an oxide layer on a first surface of the lid wafer; andbonding the oxide layer of the first surface of the wafer stack to the oxide layer of the first surface of the lid wafer to create a wafer assembly and to form a hermetic seal around the cavity.21. The method of claim 18 , further comprising forming a conduit from the exterior of the wafer assembly through the lid wafer to the cavity.22. The method of claim 21 , further comprising delivering a sufficient amount of a ...

Cu3Sn VIA METALLIZATION IN ELECTRICAL DEVICES FOR LOW-TEMPERATURE 3D-INTEGRATION

A CuSn electrical interconnect and method of making same in an electrical device, such as for hybrid bond 3D-integration of the electrical device with one or more other electrical devices. The method of forming the CuSn electrical interconnect includes: depositing a Sn layer in the via hole; depositing a Cu layer atop and in contact with the Sn layer; and heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a CuSn interconnect in the via hole. During the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer as initially deposited, such that any remaining Cu layer or any voids formed during the diffusion are at an upper region of the formed CuSn interconnect in the via hole, thereby allowing such voids or remaining material to be easily removed. 1. A method of forming an electrical interconnect in a via hole of an electrical device , the method comprising:depositing a Sn layer in the via hole;depositing a Cu layer atop and in contact with the Sn layer; and{'sub': '3', 'heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a CuSn interconnect in the via hole;'}wherein during the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer initially deposited.2. The method according to claim 1 , wherein the heating causes solid state diffusion between the Sn and Cu layers.3. The method according to claim 1 ,{'sub': '3', 'wherein the heating causes Cu atoms in the Cu layer to diffuse across the diffusion front into the Sn layer to form the CuSn interconnect;'}{'sub': '3', 'wherein the heating causes vacancy diffusion and the formation of Kirkendall voids at an interface between the formed CuSn interconnect and remaining Cu layer; and'}wherein the method is carried out such that the Kirkendall voids are at an upper portion of the via hole or above an upper surface of a layer in which the via hole is formed.4. The ...

FOUNDRY-AGNOSTIC POST-PROCESSING METHOD FOR A WAFER

A foundry-agnostic post-processing method for a wafer is provided. The wafer includes an active surface, a substrate and an intermediate layer interposed between the active surface and the substrate. The method includes removing the wafer from an output yield of a wafer processing foundry, thinning the substrate to the intermediate layer or within microns of the intermediate layer to expose a new surface and bonding the new surface to an alternate material substrate which provides for enhanced device performance as compared to the substrate. 1. A foundry-agnostic post-processing method , comprising:removing a wafer from an output yield at a foundry, the wafer comprising an intermediate layer with a via between an active surface and a substrate;removing other wafers similar to the wafer from output yields of other foundries; andcompiling the wafer and the other wafers into a wafer set in a post-processing facility,wherein, for each wafer and other wafer of the wafer set, the method further comprises:thinning the substrate to the intermediate layer at locations remote from the via to expose a new surface;avoiding the thinning at a location of the via to form a bump; andbonding the new surface to an alternate material substrate while absorbing the bump such that the alternate material substrate is flat at a location corresponding to the location of the via.2. The foundry-agnostic post-processing method according to claim 1 , wherein at least one of the active surface and the substrate comprises at least one of silicon (Si) and silicon germanium (SiGe) and wherein the alternate material substrate comprises a high resistivity material.3. The foundry-agnostic post-processing method according to claim 1 , wherein the alternate material substrate comprises at least one of glass and fused silica.4. The foundry-agnostic post-processing method according to claim 1 , wherein the bonding comprises oxide bonding.5. The foundry-agnostic post-processing method according to claim 1 ...

BARRIER LAYER FOR INTERCONNECTS IN 3D INTEGRATED DEVICE

An electronic device integration method and integrated electronic device. The integration method may include the steps of preparing a first electronic device by forming an electrically conductive trace overlying a substrate, forming a barrier layer overlying the electrically conductive trace, forming one or more electrically conductive interconnects on the barrier layer, and forming a bonding layer overlying the trace and/or at least partially surrounding the one or more interconnects. The barrier layer is configured to prevent formation of an intermetallic compound between the trace and interconnect structures, while still enabling electrical communication between the trace and interconnect. The integration method may further include the steps of direct bonding the first electronic device to a second electronic device, direct bonding a third electronic device to the second electronic device, and so on. A high-temperature treatment and functional testing of the vertically integrated electronic device may be conducted after each stack sequence. 1. An electronic device comprising:a substrate;a plurality of electrically conductive traces disposed on at least a portion of the substrate;a plurality of barrier layers, each respective barrier layer of the plurality of barrier layers completely overlying each respective electrically conductive trace of the plurality of electrically conductive traces;a plurality of electrically conductive interconnects, each respective electrically conductive interconnect of the plurality of electrically conductive interconnects at least partially overlying each respective barrier layer of the plurality of barrier layers; anda bonding layer at least partially surrounding the plurality of electrically conductive interconnects,wherein each respective barrier layer of the plurality of barrier layers is interposed between each respective electrically conductive trace of the plurality of electrically conductive traces and each respective ...

BARRIER LAYER FOR INTERCONNECTS IN 3D INTEGRATED DEVICE

An electronic device integration method and integrated electronic device. The integration method may include the steps of preparing a first electronic device by forming an electrically conductive trace overlying a substrate, forming a barrier layer overlying the electrically conductive trace, forming one or more electrically conductive interconnects on the barrier layer, and forming a bonding layer overlying the trace and/or at least partially surrounding the one or more interconnects. The barrier layer is configured to prevent formation of an intermetallic compound between the trace and interconnect structures, while still enabling electrical communication between the trace and interconnect. The integration method may further include the steps of direct bonding the first electronic device to a second electronic device, direct bonding a third electronic device to the second electronic device, and so on. A high-temperature treatment and functional testing of the vertically integrated electronic device may be conducted after each stack sequence. 1. An integration method for an electronic device comprising: forming a first electrically conductive trace overlying at least a portion of the first substrate,', 'forming a first barrier layer overlying at least a portion of the first electrically conductive trace,', 'forming one or more first electrically conductive interconnects in contact with the first barrier layer, and', 'forming a first bonding layer overlying at least a portion of the first electrically conductive trace and at least partially surrounding the one or more first interconnects;, 'preparing a first electronic device having a first substrate, includingpreparing a second electronic device having a second substrate, one or more second electrically conductive interconnects, and a second bonding layer;contacting the one or more first interconnects with the one or more second interconnects; andcontacting the first bonding layer with the second bonding layer.2. ...

DIE ENCAPSULATION IN OXIDE BONDED WAFER STACK

Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above. 1. A semiconductor wafer assembly , comprising:a first wafer including a first surface and an integrated circuit;a second wafer having a first surface and a second surface, the first surface is bonded to the first wafer, wherein the first wafer and the second wafer define a cavity;a semiconductor die within the cavity mechanically and electrically connected to the first wafer; anda third wafer including an integrated circuit, and having a first surface that is bonded to the second surface of the second wafer, thereby encapsulating the semiconductor die within the cavity,wherein the wafer assembly is configured to produce one or more stacked integrated circuits, each including one or more encapsulated semiconductor dies, when the wafer assembly is diced, and the second wafer includes an active integrated circuit interconnected to the integrated circuits of the first wafer and third wafer.2. The semiconductor wafer assembly of claim 1 , wherein the semiconductor die is mechanically and electrically connected to the first wafer by at least one of a bump bond claim 1 , a wire interconnection claim 1 , an ultrasonic bond claim 1 , and an oxide bond.3. The semiconductor wafer assembly of claim 1 , wherein the cavity is hermetically sealed to encapsulate the ...

Foundry-agnostic post-processing method for a wafer

A foundry-agnostic post-processing method for a wafer is provided. The wafer includes an active surface, a substrate and an intermediate layer interposed between the active surface and the substrate. The method includes removing the wafer from an output yield of a wafer processing foundry, thinning the substrate to the intermediate layer or within microns of the intermediate layer to expose a new surface and bonding the new surface to an alternate material substrate which provides for enhanced device performance as compared to the substrate.

Fixed frequency regulation circuit employing a voltage variable dielectric capacitor

Frequency regulating apparatus (30) comprising a high power, voltage variable dielectric varactor (16) or capacitor (31) (or ferroelectric voltage variable dielectric capacitor (31)) for use as a control element in the regulation circuit that actively tunes a resonant network (11) to modulate power delivered to a load. The voltage variable dielectric capacitor comprises a substrate (32) having a bottom electrode (33) formed thereon. A dielectric material (34) is disposed on the substrate is a crystallized ceramic material that preferably comprises a barium, strontium, and titanium mixture. A top electrode (35) is disposed on top of the crystallized ceramic material. Methods (20) of fabricating the voltage variable dielectric varactor (capacitor) are also disclosed.

Coaxial connector feed-through for multi-level interconnected semiconductor wafers

A semiconductor, silicon-on-oxide (SOI) structure having a silicon layer disposed on a bottom oxide (BOX) insulating layer. A deep trench isolation (DTI) material passes vertically through the silicon layer to the bottom oxide insulating layer. The deep trench isolation material has a lower permittivity than the permittivity of the silicon. A coaxial transmission line having an inner electrical conductor and an outer electrically conductive shield structure disposed around the inner electrical conductor passing vertically through the deep trench isolation material to electrically connect electrical conductors disposed over the bottom oxide insulating layer to electrical conductors disposed under the contacts bottom oxide insulating layer.

Tile for an active electronically scanned array (AESA)

In one aspect, an active electronically scanned array (AESA) tile includes a radiator structure and oxide-bonded semiconductor wafers attached to the radiator structure and comprising a radio frequency (RF) manifold and a beam former. An RF signal path through the oxide-bonded wafers comprises a first portion that propagates toward the beam former and a second portion that propagates parallel to the beam former.

Direct bond method providing thermal expansion matched devices

A method of transferring an integrated circuit (IC) onto an alternative substrate is provided at a wafer level to enable coefficient of thermal expansion (CTE) matching for a circuit layer to a different material. The method is executable relative to a wafer with a circuit layer, a first major surface, a second major surface opposite the first major surface, and a substrate affixed to the first major surface. The method includes temporarily bonding a handle to the second major surface, removing a majority of the substrate to expose the first major surface and bonding a second substrate to the first major surface with deposited bonding material.

Barrier layer for interconnects in 3d integrated device

An electronic device integration method and integrated electronic device. The integration method may include the steps of preparing a first electronic device by forming an electrically conductive trace overlying a substrate, forming a barrier layer overlying the electrically conductive trace, forming one or more electrically conductive interconnects on the barrier layer, and forming a bonding layer overlying the trace and/or at least partially surrounding the one or more interconnects. The barrier layer is configured to prevent formation of an intermetallic compound between the trace and interconnect structures, while still enabling electrical communication between the trace and interconnect. The integration method may further include the steps of direct bonding the first electronic device to a second electronic device, direct bonding a third electronic device to the second electronic device, and so on. A high-temperature treatment and functional testing of the vertically integrated electronic device may be conducted after each stack sequence.

Electrode for thin film capacitor devices

A method of forming a conductor on a substrate including steps of depositing tantalum on a glass layer of the substrate; oxidizing the tantalum; and depositing a noble metal on the oxidized tantalum to form the conductor. The method can be used to form a ferroelectric capacitor or other thin film ferroelectric device. The device can include a substrate comprising a glass layer; and an electrode connected to the glass layer. The electrode comprising can include a noble metal connected to the glass layer by an adhesion layer comprising Ta 2 O 5 .

Temperature-compensated ferroelectric capacitor device, and its fabrication

A temperature-compensated capacitor device (20) has ferroelectric properties and includes a ferroelectric capacitor (22) using a ferroelectric material such as a metal oxide ferroelectric material, a negative-temperature-variable capacitor (24) using a negative-temperature-coefficient-of-capacitance material such as a metal oxide paraelectric material, and an electrical series connection (26) between the negative-temperature-variable capacitor (24) and the ferroelectric capacitor (22). The temperature-compensated capacitor device (20) may be formed as an integrated layered structure, or as separate capacitors with a discrete electrical connection therebetween.

Die encapsulation in oxide bonded wafer stack

Structures and methods of fabricating semiconductor water assemblies (100) that encapsulate at least one die (108, 202, 402) in a cavity (110, 204, 404) etched into an oxide bonded semiconductor wafer stack (102+104, 206+208, 406+408). The methods generally include the steps of position-ing the die (108, 202, 402) in the cavity (110, 204, 404), mechanically and electrically mounting the die (108, 202, 402) to the wafer stack (102+104, 206+208, 406+408), and encapsulating the die (108, 202, 402) within the cavity (110, 204, 404) by bonding a lid wafer (106, 210, 410) to the wafer stack (102+104, 206+208, 406+408) in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above. The cavity (110, 404) may be hermetically sealed to encapsulate the semiconductor die (108, 402). The wafer assembly (100) may be diced to produce one or more semiconductor chips, each semiconductor chip including one or more encapsulated semiconductor die (108, 202, 402). A thermal interface (164, 170, 412) may be comprised between the semiconductor die (108, 402) and one or more of the wafers (102, 104, 106, 406, 408, 410). The wafer stack (102+104, 406+408) and the lid wafer (106, 410) may be oxide bonded together. Alternatively, the wafer stack (206+208) and the lid wafer (210) may be bump (214) bonded so as to define an air gap (224) providing thermal isolation from the cavity (204). One of the wafers (102, 104, 106) may define a conduit (168) to the cavity (110) from the exterior of the wafer assembly (100), wherein the conduit (168) and the cavity (110) are at least partially filled with a thermally conductive material, are evacuated and sealed providing a vacuum package or are evacuated and backfilled with a liquid or gas ...

Tile for an active electronically scanned array (aesa)

Transfer method providing thermal expansion matched devices

A method of transferring an integrated circuit (IC) onto an alternative substrate is provided at a wafer level to enable coefficient of thermal expansion (CTE) matching for a circuit layer to a different material. The method is executable relative to a wafer (11) with a circuit layer (12), a first major surface (121), a second major surface (122) opposite the first major surface, and a substrate (13) affixed to the first major surface. The method includes temporarily bonding a handle (14) to the second major surface, removing a majority of the substrate to expose the first major surface and bonding a second substrate (16) to the first major surface with deposited bonding material (15).

Die encapsulation in oxide bonded wafer stack

Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.

Pin diode structure having surface charge suppression

A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes.

Foundry-agnostic post-processing method for a wafer

Oxide liner stress buffer

A through-wafer via substrate includes a substrate having an intermediate layer and a bonding layer formed on a surface of the intermediate layer. A via cavity extends through the bonding layer and into the intermediate layer, and a stress buffer liner is deposited directly on inner sidewalls and a base of the via cavity. An electrically conductive through-wafer via is disposed in the via cavity such that the stress buffer liner is interposed completely between the intermediate layer and the through-wafer via.

Cu3Sn via metallization in electrical devices for low-temperature 3D-integration

A Cu 3 Sn electrical interconnect and method of making same in an electrical device, such as for hybrid bond 3D-integration of the electrical device with one or more other electrical devices. The method of forming the Cu 3 Sn electrical interconnect includes: depositing a Sn layer in the via hole; depositing a Cu layer atop and in contact with the Sn layer; and heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a Cu 3 Sn interconnect in the via hole. During the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer as initially deposited, such that any remaining Cu layer or any voids formed during the diffusion are at an upper region of the formed Cu 3 Sn interconnect in the via hole, thereby allowing such voids or remaining material to be easily removed.

PiN DIODE STRUCTURE HAVING SURFACE CHARGE SUPPRESSION

A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes.

PiN DIODE STRUCTURE HAVING SURFACE CHARGE SUPPRESSION

A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes.

Hybrid sensor chip assembly and method for reducing radiative transfer between a detector and read-out integrated circuit

Aspects and examples described herein provide a hybrid imaging sensor chip assembly for reducing undesired radiative transfer between a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC) and an optical detector, and methods of manufacturing a hybrid imaging sensor chip assembly. In one example, a hybrid imaging sensor chip assembly includes an optical detector configured to collect electromagnetic radiation incident thereon, a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC), and a radiation-shielding wafer interposed between the optical detector and the CMOS ROIC, the radiation-shielding wafer including a plurality of through wafer vias (TWVs) electrically coupled to the optical detector and the CMOS ROIC, the radiation-shielding wafer being positioned to prevent radiative transfer between the CMOS ROIC and the optical detector.

Oxide liner stress buffer

A through-wafer via substrate includes a substrate having an intermediate layer and a bonding layer formed on a surface of the intermediate layer. A via cavity extends through the bonding layer and into the intermediate layer, and a stress buffer liner is deposited directly on inner sidewalls and a base of the via cavity. An electrically conductive through-wafer via is disposed in the via cavity such that the stress buffer liner is interposed completely between the intermediate layer and the through-wafer via.

PiN diode structure having surface charge suppression

A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes.

Cu3Sn VIA METALLIZATION IN ELECTRICAL DEVICES FOR LOW-TEMPERATURE 3D-INTEGRATION

A Cu3Sn electrical interconnect and method of making same in an electrical device, such as for hybrid bond 3D-integration of the electrical device with one or more other electrical devices. The method of forming the Cu3Sn electrical interconnect includes: depositing a Sn layer in the via hole; depositing a Cu layer atop and in contact with the Sn layer; and heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a Cu3Sn interconnect in the via hole. During the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer as initially deposited, such that any remaining Cu layer or any voids formed during the diffusion are at an upper region of the formed Cu3Sn interconnect in the via hole, thereby allowing such voids or remaining material to be easily removed.

Three-dimensional wafer-stacked optical and radio frequency phased array transceiver system

A communication system includes an antenna assembly. The antenna assembly includes an optical communication layer including a plurality of electro-optical (EO) antennas for communicating via an EO signal and a radio-frequency communication layer including a plurality of radio frequency (RF) antennas for communicating via an RF signal. A processor operates the antenna assembly to communicate via one or both of the EO signal and the RF signal.

Coaxial connector feed-through for multi-level interconnected semiconductor wafers

A semiconductor, silicon-on-oxide (SOI) structure having a silicon layer disposed on a bottom oxide (BOX) insulating layer. A deep trench isolation (DTI) material passes vertically through the silicon layer to the bottom oxide insulating layer. The deep trench isolation material has a lower permittivity than the permittivity of the silicon. A coaxial transmission line having an inner electrical conductor and an outer electrically conductive shield structure disposed around the inner electrical conductor passing vertically through the deep trench isolation material to electrically connect electrical conductors disposed over the bottom oxide insulating layer to electrical conductors disposed under the contacts bottom oxide insulating layer.