Data storage method used for Memory cell

This invention relates to a kind of data memory method which is used to the memorizer cell and its memorizer cell. It includes the following steps: firstly, divides the memorizer cell into many small memorizer groups; then, defines the critical pressure distributing area of each small memorizer groups; thirdly, defines multi read-in validate critical pressure and multi reference determination value of each small memorizer groups according to the critical pressure distributing area of each small memorizer groups; at last, uses these small memorizer groups to save the data.

Process for preparing self-aligning mask-type ROM

The ivnention method for manufacturing the self-aligning mask ROM is as following. The grid stack including the grid dielectric layer, the grid conductor layer and grid top cover layer is formed on the substrate. Multiple source/drain areas, which are not adjacent to the grid stack, are formed on the substrate between the stacks. Then, the first dielectric layer and the patterned photoresistive layer with multiple openings are formed on the substrate in sequence. With the photoresistive layer being as the mask, the part of the first dielectric layer is removed and the ion implantation processis carried out so as to form multiple coded the ion implantation areas self-aligned. With the photoresistive layer being removed, the eatback process is carried out again in order to expose the grid conductive layer so as to form the character line.

Hood curtain type read-only storage capable of storing multi order information

A mask ROM able to store multiple bit information is composed of a substrate, the first deeper channel and second shallow channel in the substrate, a conformal dielectric layer on the side walls and bottoms of both channels, a conducting layer filled in both channels, a first doped region under the first channel, a second doped region under the second channel, and a third doped region in the surface of substrate between two channels.

MROM capable of storing multiple byte information

Internal storage structure and its controller

The present invention relates to an internal memory structure and its used controller. The internal storage range in the internal memory structure which can be fetched once is called total internal memory capacity, and said internal memory structure includes first internal memory whose capacity is first internal memory capacity and second internal memory whose capacity is second internal memory capacity, and when the internal memory capacity of first internal memory is a specific fixed capacity, its actual used pin position memory capacity of second internal memory is fixed capacity, its actual used pin position number is pin position of second application pin position number in which first application pin position number is greater than second application pin position number.

Memory cell and data storage method used for the same

This invention relates to a kind of data memory method which is used to the memorizer cell and its memorizer cell. It includes the following steps: firstly, divides the memorizer cell into many small memorizer groups; then, defines the critical pressure distributing area of each small memorizer groups; thirdly, defines multi read-in validate critical pressure and multi reference determination value of each small memorizer groups according to the critical pressure distributing area of each small memorizer groups; at last, uses these small memorizer groups to save the data.

High-density integrated circuit with memory array

The invention discloses the high density IC with storage array, the shared select transistor and the distributed drives of XDEC. The shared select transistor is utilized to read the two adjacent unit areas of the storage so as to reduce the overhead. The distributed drives of XDEC are positioned on the two sides of the storage array in order to drive the unit area of the storage. Thus, the traditional transition area, which wastes the area, is reduced.

High-density mask type non-volatility memory array structure with flat zone-block selected transistor

The present invention is mainly aimed at providing a read-only memory array with flat-type structure. It includes at least two memory banks, said two memory banks have several memory cells, at least two inter-bank selective transistors are connected to two memory banks and shared by two memory banks, every inter-bank selective transistor can select memory cell of two memory banks, and at least one contact can be connected to two memory banks by means of two inter-bank selective transistors.