NITRIDATION ON HDP OXIDE BEFORE HIGH-K DEPOSITION TO PREVENT OXYGEN INGRESS

A method of reducing a migration of oxygen into a high-k dielectric layer of a semiconducting device is disclosed. An oxide layer of the semiconducting device is deposited on a substrate. A chemical composition of a top portion of the oxide layer is altered. The high-k dielectric layer is deposited on the top portion of the oxide layer to form the semiconducting device. The altered chemical composition of the top portion of the oxide layer reduces migration of oxygen into the high-k dielectric layer. 1forming a substrate;forming dummy gates on the substrate, the dummy gates separated by at least one first gap;depositing a flowable oxide into the at least one first gap to form an oxide layer of the semiconducting device on the substrate;. A method of reducing a migration of oxygen into a high-k dielectric layer of a semiconducting device, comprising: The present application is a continuation application of U.S. patent application Ser. No. 14/609,782 filed on Jan. 30, 2015, the contents of which are incorporated by reference herein.The present invention relates generally to methods of manufacturing a transistor, and more specifically, to a method of reducing oxygen migration into a high-k dielectric layer of a transistor during manufacture of the transistor.In various high-k metal gate (HKMG) transistors, a source and a drain are built into a substrate and a gate structure is built on top of the substrate. The gate structure includes gate material in a gap between flowable oxide materials built on top of the substrate. The gap is generally lined with a high-k dielectric material. However, since the high-k dielectric material is in contact with the top surfaces of the flowable oxide material during a manufacturing stage, oxygen molecules can migrate from the flowable oxide material into the high-k dielectric material. Once inside the high-k dielectric material, the oxygen can affect the performance of the resulting HKMG transistor. Therefore, there is a desire to ...

PARTIALLY DIELECTRIC ISOLATED FIN-SHAPED FIELD EFFECT TRANSISTOR (FINFET)

One embodiment provides a method comprising etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin, and laterally etching the reduced fin to form a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall. The method further comprises forming a first thin dielectric tunnel and a second thin dielectric tunnel on the first fin channel sidewall and the second fin channel sidewall, respectively. Each thin dielectric tunnel prevents lateral epitaxial crystal growth on the fin channel. The method further comprises etching an insulator layer disposed between the fin channel and a substrate of the FinFET to expose portions of a substrate surface of the substrate. A source epitaxy and a drain epitaxy are formed from vertical epitaxial crystal growth on the exposed portions of the substrate surface after epitaxial deposition.

Gate structure cut after formation of epitaxial active regions

A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

NITRIDATION ON HDP OXIDE BEFORE HIGH-K DEPOSITION TO PREVENT OXYGEN INGRESS

A method of reducing a migration of oxygen into a high-k dielectric layer of a semiconducting device is disclosed. An oxide layer of the semiconducting device is deposited on a substrate. A chemical composition of a top portion of the oxide layer is altered. The high-k dielectric layer is deposited on the top portion of the oxide layer to form the semiconducting device. The altered chemical composition of the top portion of the oxide layer reduces migration of oxygen into the high-k dielectric layer. 1. A method of reducing a migration of oxygen into a high-k dielectric layer of a semiconducting device , comprising:forming a first dummy gate and a second dummy gate to define a first gap;depositing an oxide layer of the semiconducting device on a substrate in the first gap;altering a chemical composition of a top portion of the oxide layer;removing the first dummy gate and the second dummy gate to define a second gap;depositing the high-k dielectric layer on the top portion of the oxide layer and in the second gap, wherein the altered chemical composition of the top portion of the oxide layer reduces migration of oxygen into the high-k dielectric layer;annealing the semiconducting device, wherein the top portion of the oxide layer prevents migration of oxygen from the oxide layer into the high-k dielectric layer during the annealing; andremoving a first segment of the high-k dielectric layer from the top portion of the oxide layer after the annealing of the semi-conducting device to dissociate the high-k dielectric layer from the oxide layer, wherein a second segment of the high-k dielectric layer lines the second gap to define a gate lining.2. The method of claim 1 , wherein altering the chemical composition of the top portion of the oxide layer further comprises diffusing nitrogen into the top portion of the oxide layer.3. The method of claim 2 , further comprising diffusing the nitrogen into the top portion by performing at least one of: nitrogen implantation; ...

Nitridation on HDP oxide before high-k deposition to prevent oxygen ingress

A method of reducing a migration of oxygen into a high-k dielectric layer of a semiconducting device is disclosed. An oxide layer of the semiconducting device is deposited on a substrate. A chemical composition of a top portion of the oxide layer is altered. The high-k dielectric layer is deposited on the top portion of the oxide layer to form the semiconducting device. The altered chemical composition of the top portion of the oxide layer reduces migration of oxygen into the high-k dielectric layer.

High-K layer chamfering to prevent oxygen ingress in replacement metal gate (RMG) process

A semiconductor structure includes a semiconductor substrate having an outer surface; a plurality of oxide regions, located outward of the outer surface, and defining a plurality of metal-gate-stack-receiving cavities; and a liner interspersed between the plurality of oxide regions and the semiconductor substrate and between the plurality of oxide regions and the plurality of metal-gate-stack-receiving cavities. A layer of high-K material is deposited over the semiconductor structure, including on outer surfaces of the plurality of oxide regions, outer edges of the liner, on walls of the plurality of metal-gate-stack-receiving cavities, and on the outer surface of the semiconductor substrate within the plurality of metal-gate-stack-receiving cavities. The layer of high-K material is chamfered to remove same from the outer surfaces of the plurality of oxide regions, the outer edges of the liner, and partially down the walls of the plurality of metal-gate-stack-receiving cavities.

GATE STRUCTURE CUT AFTER FORMATION OF EPITAXIAL ACTIVE REGIONS

A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

HIGH-K LAYER CHAMFERING TO PREVENT OXYGEN INGRESS IN REPLACEMENT METAL GATE (RMG) PROCESS

A semiconductor structure includes a semiconductor substrate having an outer surface; a plurality of oxide regions, located outward of the outer surface, and defining a plurality of metal-gate-stack-receiving cavities; and a liner interspersed between the plurality of oxide regions and the semiconductor substrate and between the plurality of oxide regions and the plurality of metal-gate-stack-receiving cavities. A layer of high-K material is deposited over the semiconductor structure, including on outer surfaces of the plurality of oxide regions, outer edges of the liner, on walls of the plurality of metal-gate-stack-receiving cavities, and on the outer surface of the semiconductor substrate within the plurality of metal-gate-stack-receiving cavities. The layer of high-K material is chamfered to remove same from the outer surfaces of the plurality of oxide regions, the outer edges of the liner, and partially down the walls of the plurality of metal-gate-stack-receiving cavities. 1. (canceled)2. A semiconductor structure comprising:a semiconductor substrate having an outer surface;a plurality of metal gate stacks located outward of said outer surface of said semiconductor substrate;a plurality of oxide regions, located outward of said outer surface of said semiconductor substrate, and interspersed between said plurality of metal gate stacks;a liner interspersed between said plurality of oxide regions and said semiconductor substrate and between said plurality of oxide regions and said plurality of metal gate stacks; anda plurality of high-K layers separating said plurality of metal gate stacks from said semiconductor substrate and separating said plurality of metal gate stacks from said plurality of oxide regions;wherein:said plurality of oxide regions and said plurality of metal gate stacks extend outwardly a first height from said semiconductor substrate; andsaid plurality of high-K layers extend outwardly a second height from said semiconductor substrate, said ...

Replacement metal gate stack for diffusion prevention

A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.

Partially dielectric isolated fin-shaped field effect transistor (FinFET)

One embodiment provides a method comprising etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin, and laterally etching the reduced fin to form a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall. The method further comprises forming a first thin dielectric tunnel and a second thin dielectric tunnel on the first fin channel sidewall and the second fin channel sidewall, respectively. Each thin dielectric tunnel prevents lateral epitaxial crystal growth on the fin channel. The method further comprises etching an insulator layer disposed between the fin channel and a substrate of the FinFET to expose portions of a substrate surface of the substrate. A source epitaxy and a drain epitaxy are formed from vertical epitaxial crystal growth on the exposed portions of the substrate surface after epitaxial deposition.

Gate structure cut after formation of epitaxial active regions

A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

Partially dielectric isolated fin-shaped field effect transistor (FinFET)

One embodiment provides a method comprising etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin, and laterally etching the reduced fin to form a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall. The method further comprises forming a first thin dielectric tunnel and a second thin dielectric tunnel on the first fin channel sidewall and the second fin channel sidewall, respectively. Each thin dielectric tunnel prevents lateral epitaxial crystal growth on the fin channel. The method further comprises etching an insulator layer disposed between the fin channel and a substrate of the FinFET to expose portions of a substrate surface of the substrate. A source epitaxy and a drain epitaxy are formed from vertical epitaxial crystal growth on the exposed portions of the substrate surface after epitaxial deposition.

Nitridation on HDP oxide before high-k deposition to prevent oxygen ingress

A method of reducing a migration of oxygen into a high-k dielectric layer of a semiconducting device is disclosed. An oxide layer of the semiconducting device is deposited on a substrate. A chemical composition of a top portion of the oxide layer is altered. The high-k dielectric layer is deposited on the top portion of the oxide layer to form the semiconducting device. The altered chemical composition of the top portion of the oxide layer reduces migration of oxygen into the high-k dielectric layer.

Device structure, layout and fabrication method for uniaxially strained transistors

A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.

Spacer as hard mask scheme for in-situ doping in cmos finfets

A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.

Finfet spacer formation by oriented implantation

A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack.

Highly scalable trench capacitor

An improved trench structure, and method for its fabrication are disclosed. Embodiments of the present invention provide a trench in which the collar portion has an air gap instead of a solid oxide collar. The air gap provides a lower dielectric constant. Embodiments of the present invention can therefore be used to make higher-performance devices (due to reduced parasitic leakage), or smaller devices, due to the ability to use a thinner collar to achieve the same performance as a thicker collar comprised only of oxide (with no air gap). Alternatively, a design choice can be made to achieve a combination of improved performance and reduced size, depending on the application.

Gate structure cut after formation of epitaxial active regions

A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

Handler wafer removal by use of sacrificial inert layer

The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to the temporary bonding of a semiconductor wafer to handler wafer during processing. The semiconductor wafer may be temporarily bonded to the handler wafer by forming a sacrificial layer on a surface of a handler wafer, forming a first dielectric layer on a surface of the sacrificial layer, forming a second dielectric layer on a surface of a semiconductor wafer, and directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer. After the semiconductor wafer is processed, it may be removed from the handler wafer along with the bonding layer by degrading the sacrificial layer with infrared radiation transmitted through the handler wafer.

FINFET SPACER FORMATION BY ORIENTED IMPLANTATION

A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack. 125.-. (canceled)26. A finFET formed by a method comprising steps offorming at least one fin of semiconductor material on a substrate,forming a gate stack across said fin,conformally depositing sidewall spacer material on surfaces of said fin, gate stack and said substrate,etching said sidewall spacer material to form sidewall spacers,performing angled ion impurity implants into said sidewall spacer material on both sides of said fin in a direction substantially parallel to sides of said gate stack,etching said sidewall spacer material to remove said sidewall spacer material from said fin selectively to said sidewall spacer material on said gate stack, said etching being subsequent to said angled ion impurity implant and sufficient to obtain a substantially uniform shape of spacer material remaining as sidewall spacers on said gate stack and to remove substantially all of said sidewall spacer material from portions of said fin beyond said sidewall spacers on said gate stack, andperforming epitaxial growth on said sides of ends of said fin.27. The FinFET as recited in claim 26 , wherein said etching step to remove said sidewall spacer material from said fin comprisesetching said spacer material deposited in said step of conformally depositing said spacer material using hydrofluoric acid or an etchant which is slightly anisotropic or selective to nitride caps on said fin and said gate stack.28. The ...

UNIFORM FINFET GATE HEIGHT

A method including providing fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the fins and the nitride layer, removing a portion of the fins to form an opening, forming a dielectric spacer on a sidewall of the opening, and filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer. The method may further include forming a deep trench capacitor in-line with one of the fins, removing the nitride layer to form a gap between the fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the fins and the fill material to widen. 1. A method comprising:providing a plurality of fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the plurality of fins and the nitride layer;removing a portion of the plurality of fins to form an opening;forming a dielectric spacer on a sidewall of the opening;filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer;forming a deep trench capacitor in-line with one of the plurality of fins;removing the nitride layer to form a gap between the plurality of fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap; andremoving the re-entrant geometry and causing the gap between the plurality of fins and the fill material to widen.2. The method of claim 1 , further comprising:removing the oxide layer; andrecessing the fill material such that the top surface of the fill material is substantially flush with a top surface of the fins.3. The method of claim 2 , further comprising:forming a gate above and between the plurality of fins and the fill material.4. The method ...

REPLACEMENT METAL GATE STACK FOR DIFFUSION PREVENTION

A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer. 1. A semiconductor structure comprising:a gate structure formed above a substrate, the gate structure comprising:a metal gate above a conductive barrier, anda gate dielectric layer below the conductive barrier; anda capping layer above the gate structure, wherein the conductive barrier separates the capping layer from the gate dielectric layer.2. The semiconductor structure of claim 1 , wherein the gate structure comprises a length less than 20 nm.3. The semiconductor structure of claim 1 , wherein the conductive barrier comprises an n-type workfunction metal.4. The semiconductor structure of claim 1 , wherein the gate dielectric layer comprises a high-k dielectric material.5. The semiconductor structure of claim 1 , wherein the gate dielectric layer has a vertical portion and a horizontal portion claim 1 , the vertical portion of the gate dielectric layer having a height less than a height of the metal gate measured from a top surface of the substrate.6. The semiconductor structure of claim 5 , wherein the height of the vertical portion of the gate dielectric layer is within a range from 1 nm to ...

HIGH-K LAYER CHAMFERING TO PREVENT OXYGEN INGRESS IN REPLACEMENT METAL GATE (RMG) PROCESS

A semiconductor structure includes a semiconductor substrate having an outer surface; a plurality of oxide regions, located outward of the outer surface, and defining a plurality of metal-gate-stack-receiving cavities; and a liner interspersed between the plurality of oxide regions and the semiconductor substrate and between the plurality of oxide regions and the plurality of metal-gate-stack-receiving cavities. A layer of high-K material is deposited over the semiconductor structure, including on outer surfaces of the plurality of oxide regions, outer edges of the liner, on walls of the plurality of metal-gate-stack-receiving cavities, and on the outer surface of the semiconductor substrate within the plurality of metal-gate-stack-receiving cavities. The layer of high-K material is chamfered to remove same from the outer surfaces of the plurality of oxide regions, the outer edges of the liner, and partially down the walls of the plurality of metal-gate-stack-receiving cavities. 1. A method comprising: a semiconductor substrate having an outer surface;', 'a plurality of oxide regions, located outward of said outer surface of said semiconductor substrate, and defining a plurality of metal-gate-stack-receiving cavities; and', 'a liner interspersed between said plurality of oxide regions and said semiconductor substrate and between said plurality of oxide regions and said plurality of metal-gate-stack-receiving cavities;, 'providing a semiconductor structure comprisingdepositing a layer of high-K material over said semiconductor structure, including on outer surfaces of said plurality of oxide regions, outer edges of said liner, on walls of said plurality of metal-gate-stack-receiving cavities, and on said outer surface of said semiconductor substrate within said plurality of metal-gate-stack-receiving cavities; andchamfering said layer of high-K material to remove same from said outer surfaces of said plurality of oxide regions, said outer edges of said liner, and ...

Replacement metal gate stack for diffusion prevention

A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.

GATE STRUCTURE CUT AFTER FORMATION OF EPITAXIAL ACTIVE REGIONS

A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed. 1. A semiconductor structure comprising:a semiconductor material portion located on a substrate and extending along a lengthwise direction;a gate structure overlying a portion of said semiconductor material portion;a pair of gate spacer portions contacting widthwise sidewalls of said gate structure and laterally spaced from each other by said gate structure along said lengthwise direction; anda dielectric liner contacting lengthwise sidewalls of said gate spacer portions and lengthwise sidewalls of said gate structure and laterally surrounding said semiconductor material portion.2. The semiconductor structure of claim 1 , wherein two of said lengthwise sidewalls of said pair of gate spacer portions and one of said lengthwise sidewalls of said gate structure are within a vertical plane.3. The semiconductor structure of claim 2 , further comprising a pair of epitaxial active regions located on said semiconductor material portion claim 2 , wherein sidewall surfaces of said pair of epitaxial active regions are within said vertical plane.4. The semiconductor ...

Semiconductor structure having buried conductive elements

Embodiments for the present invention provide a semiconductor device and methods for fabrication. In an embodiment of the present invention, a semiconductor structure comprises a first conductor horizontally formed on a semiconductor substrate. A second conductor is vertically formed in a semiconductor stack that includes the semiconductor substrate. An oxidized region is formed proximate to the first conductor. The second conductor is formed in a manner to be in electrical communication with the first conductor. The first conductor is formed in a manner to be laterally connected to the second conductor. The first conductor is formed in a manner to not traverse beneath the oxidized region. The first conductor is formed in a manner to have a reduced link-up resistance with adjacent epitaxial material included in the semiconductor structure.

REPLACEMENT METAL GATE STACK FOR DIFFUSION PREVENTION

A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer. 1. A method of forming a semiconductor structure , the method comprising:depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate, a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess;depositing a protective layer above the gate dielectric layer, the protective layer substantially filling the recess;recessing the protective layer selectively to the gate dielectric layer, wherein a top surface of the protective layer is below of the recess;recessing the first portion of the gate dielectric layer until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer, wherein the protective layer protects the second portion of the gate dielectric layer while recessing the first portion of the gate dielectric layer;removing the protective layer;depositing a conductive barrier above the recessed first portion of the gate dielectric layer;depositing a metal gate above the conductive barrier; andforming ...

SEMICONDUCTOR STRUCTURE HAVING BURIED CONDUCTIVE ELEMENTS

Embodiments for the present invention provide a semiconductor device and methods for fabrication. In an embodiment of the present invention, a semiconductor structure comprises a first conductor horizontally formed on a semiconductor substrate. A second conductor is vertically formed in a semiconductor stack that includes the semiconductor substrate. An oxidized region is formed proximate to the first conductor. The second conductor is formed in a manner to be in electrical communication with the first conductor. The first conductor is formed in a manner to be laterally connected to the second conductor. The first conductor is formed in a manner to not traverse beneath the oxidized region. The first conductor is formed in a manner to have a reduced link-up resistance with adjacent epitaxial material included in the semiconductor structure. 110-. (canceled)11. A method comprising: 'forming a second conductor in a semiconductor stack that includes the semiconductor substrate;', 'forming a first conductor horizontally on a semiconductor substrate;'}forming an oxidized region proximate to the first conductor;wherein the second conductor is formed in a manner to be in electrical communication with the first conductor;wherein the first conductor structure is formed in a manner to be laterally connected to the second conductor;wherein the first conductor is formed in a manner to not traverse beneath the oxidized region; andwherein the first conductor is formed in a manner to have a reduced link-up resistance with adjacent epitaxial material included in the semiconductor stack.12. The method of claim 11 , wherein the first conductor includes epitaxially grown conducting material.13. The method of claim 12 , wherein the epitaxially grown conducting material includes an n-type or p-type dopant.14. The method of claim 11 , wherein the first conductor is in electrical communication with a common backside plate.15. The method of claim 11 , wherein the second conductor is a ...

Stress enhanced transistor devices and methods of making

A transistor device includes a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.

Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor

Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.

Device with stressed channel

An FET device is disclosed which contains a source and a drain that are each provided with an extension. The source and the drain, and their extensions, are composed of epitaxial materials containing Ge or C. The epitaxial materials and the Si substrate have differing lattice constants, consequently the source and the drain and their extensions are imparting a state of stress onto the channel. For a PFET device the epitaxial material may be SiGe, or Ge, and the channel may be in a compressive state of stress. For an NFET device the epitaxial material may be SiC and the channel may be in a tensile state of stress. A method for fabricating an FET device is also disclosed. One may form a first recession in the Si substrate to a first depth on opposing sides of the gate. The first recession is filled epitaxially with a first epitaxial material. Then, a second recession may be formed in the Si substrate to a second depth, which is greater than the first depth. Next, one may fill the second recession with a second epitaxial material, which is the same kind of material as the first epitaxial material. The epitaxial materials are selected to have a different lattice constant than the Si substrate, and consequently a state of stress is being imparted onto the channel.

Dram having deep trench capacitors with lightly doped buried plates

By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.

Smooth and vertical semiconductor fin structure

A method for processing a semiconductor fin structure is disclosed. The method includes thermal annealing a fin structure in an ambient containing an isotope of hydrogen. Following the thermal annealing step, the fin structure is etched in a crystal-orientation dependent, self-limiting, manner. The crystal-orientation dependent etch may be selected to be an aqueous solution containing ammonium hydroxide (NH 4 OH). The completed fin structure has smooth sidewalls and a uniform thickness profile. The fin structure sidewalls are {110} planes.

Process for fabricating a uniform gate oxide of a vertical transistor

A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a <100> crystal plane and a <110> crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the <110> crystal plane of the trench side wall, but not into the <100> crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

High-K/metal gate CMOS finFET with improved pFET threshold voltage

A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.

Device structure, layout and fabrication method for uniaxially strained transistors

A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.

Providing isolation for wordline passing over deep trench capacitor

A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.

Source/drain junction for high performance mosfet formed by selective epi process

In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly be formed by etching an epitaxial silicon layer, then filling with another epitaxial layer. Source and Drain, and extensions, and halo, which are normally formed by diffusion, may be formed as discrete elements by etching and filling (epi-Si). This may provide a shallow, highly activated, abrupt S/D extension, an optimally formed halo and deep S/D diffusion doping, and maximized improvement of channel mobility from the compressive or tensile stress from e-SiGe or e-SiC.

STI formation in semiconductor device including SOI and bulk silicon regions

ビット線コンタクトおよびその形成方法

(57)【要約】 【課題】 ビット線コンタクト・マスクを用いてバーチ カルＤＲＡＭアレイのためのビット線コンタクトを形成 する方法およびビット線コンタクトを提供する。 【解決手段】 この方法において、ゲート導体線が形成 される。酸化物層３５がゲート導体線の上に付着され、 ビット線コンタクト・マスク４０が、酸化物層３５の一 部の上に形成される。ビット線コンタクト・マスク４０ がエッチングされ、シリコン層４５が基板５上に付着さ れる。ビット線層５０がシリコン層４５の上に付着され る。マスキングおよびエッチング工程がビット線層５０ に対して実行される。Ｍ０金属６０がシリコン層４５の 上とビット線（Ｍ０）層５０の非エッチング部分の両側 とに付着され、左右のビット線を形成する。

Structure and method of forming bitline contacts for a vertical dram array using a line bitline contact mask

Self-aligned contact

A method of forming contacts for semiconductor devices, the method including depositing an inter-level dielectric (ILD) over a plurality of gate stacks, in which the divots within the inter-level dielectric layer are defined by the spaces between the gate stacks, filling the divots with an initial fill material, depositing a masking material on the dielectric over the gate stacks, and selectively etching the fill material to form contact vias. The fill material may be a self-assembly material such as a multi-block copolymer in which the blocks self organize vertically within the divots, so that a selective etch of the block material will remove the vertically organized blocks from the divot, but leave at least one block over the gate regions. In another embodiment, the fill material may be a metal, and the masking material may be a parylene based polymer.

Oxidation of silicon nitride films in semiconductor devices