DIELECTRIC BARRIER AT NON-VOLATILE MEMORY TILE EDGE

An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles. 1. A non-volatile memory die comprising:multiple tiles of memory cells, each of the multiple tiles including a plurality of non-volatile memory cells, each of the non-volatile memory cells including a stack of materials including chalcogenide material;an oxidation barrier on a side wall of a trench between adjacent memory tiles; anda dielectric fill in the trench and over the oxidation barrier.2. The non-volatile memory die of claim 1 , wherein:the oxidation barrier comprises a silicon nitride film.3. The non-volatile memory die of claim 2 , wherein:the silicon nitride film has a density that is greater than 2.6 g/cm3.4. The non-volatile memory die of claim 1 , wherein:the oxidation barrier has a thickness in a range between 15-500 Angstroms.5. The non-volatile memory die of claim 1 , wherein:the oxidation barrier comprises multiple nitride films.6. The non-volatile memory die of claim 5 , wherein:the multiple nitride films include:a first nitride film and one or more second nitride films over the first nitride film, wherein the first nitride film is thicker than the one or more second nitride films.7. The non-volatile memory die of claim 1 , wherein:the trench between adjacent memory tiles includes tapered side walls.8. The non-volatile memory die of claim 7 , wherein:the oxidation barrier comprises a conformal layer over the tapered side walls of the trench.9. The non-volatile memory die of claim 1 , wherein:the oxidation barrier is further disposed on a bottom of the trench.10. The non-volatile memory die of claim 1 , wherein:the trench comprises a ...

Non-contact electron beam probing techniques and related structures

Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.

Non-contact measurement of memory cell threshold voltage

Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.

NON-CONTACT MEASUREMENT OF MEMORY CELL THRESHOLD VOLTAGE

Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell. 1. (canceled)2. An apparatus , comprising:a first access line coupled with a ground reference;a plurality of second access lines; and isolate the respective second access line from the first access line when a voltage associated with the respective second access line is below a threshold voltage of the respective chalcogenide component; and', 'couple the respective second access line with the first access line when the voltage associated with the respective second access line exceeds the threshold voltage of the respective chalcogenide component., 'a plurality of memory cells each coupled with the first access line and a respective second access line of the plurality of second access lines, wherein each memory cell of the plurality of memory cells comprises a respective chalcogenide component and is configured to3. The apparatus of claim 2 , wherein:the first access line is at a first level of the apparatus; andeach of the plurality of second access lines is at a second level of the apparatus above the first level.4. The apparatus of claim 3 , further comprising:a third access line at a third level of the apparatus above the second level; and isolate the third access line from the first access line when a voltage associated with the third access line is ...

Non-contact electron beam probing techniques and related structures

Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.

Dielectric barrier at non-volatile memory tile edge

An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles.

Dielectric barrier at non-volatile memory tile edge

An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles.

Non-contact electron beam probing techniques and related structures

Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.

Non-contact measurement of memory cell threshold voltage

Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.

Semiconductor structure including barrier layer between electrode layer and underlying substrate

A semiconductor structure, system and method. The semiconductor structure comprises: a substrate including circuitry therein; and a semiconductor stack on the substrate, the semiconductor stack including: a first electrically conductive layer including a metal and electrically coupled to the circuitry of the substrate; and a second electrically conductive layer between the substrate and the first electrically conductive layer, the second electrically conductive layer including one of a refractory metal, or a combination including silicon, carbon and nitride. The second electrically conductive layer may serve as a barrier layer between the first electrically conductive layer and the material of the underlying substrate, in this manner avoiding the formation of an intermixing region between the metal of the first electrically conductive layer and the material of the substrate during deposition of the metal.

Dielectric barrier at non-volatile memory tile edge