METHODS AND MATERIALS FOR PRODUCING 7-CARBON MONOMERS

This document describes biochemical pathways for producing 7-aminoheptanoic acid using a β-ketoacyl synthase or a β-ketothiolase to form an N-acetyl-5-amino-3-oxopentanoyl-CoA intermediate. 7-aminoheptanoic acid can be enzymatically converted to pimelic acid, 7-hydroxyheptanoic acid, heptamethylenediamine or 1,7-heptanediol or corresponding salts thereof. This document also describes recombinant microorganisms producing 7-aminoheptanoic acid as well as pimelic acid, 7-hydroxyheptanoic acid, heptamethylenediamine and 1,7-heptanediol or corresponding salts thereof.

METHODS AND MATERIALS FOR PRODUCING 7-CARBON MONOMERS

This document describes biochemical pathways for producing 7-aminoheptanoic acid using a β-ketoacyl synthase or a β-ketothiolase to form either a 5-amino-3-oxopentanoyl-[ACP] or 5-amino-3-oxopentanoyl-CoA intermediate. 7-aminoheptanoic acid can be enzymatically converted to pimelic acid, 7-hydroxyheptanoic acid, heptamethylenediamine or 1,7-heptanediol or the corresponding salts thereof. This document also describes recombinant microorganisms producing 7-aminoheptanoic acid as well as pimelic acid, 7-hydroxyheptanoic acid, heptamethylenediamine and 1,7-heptanediol or the corresponding salts thereof. 1. A method of producing 5-amino-3-oxopentanoyl-[ACP] or 5-amino-3-oxopentanoyl-CoA or corresponding salts thereof , said method comprising enzymatically converting β-alanyl-[ACP] or β-alanyl-CoA respectively to 5-amino-3-oxopentanoyl-[ACP] or 5-amino-3-oxopentanoyl-CoA or corresponding salts thereof , using a polypeptide having the activity of a β-ketoacyl synthase or a β-ketothiolase classified under EC. 2.3.1.- and/or a CoA transferase classified under EC 2.8.3-.2. The method of claim 1 , wherein said polypeptide having the activity of a β-ketoacyl synthase is classified under EC 2.3.1.41 claim 1 , EC 2.3.1.179 or EC 2.3.1.180 and wherein said polypeptide having the activity of a β-ketothiolase is classified under EC 2.3.1.16 or EC 2.3.1.174.3. The method of claim 1 , wherein said polypeptide having the activity of a β-ketothiolase has at least 70% sequence identity to the amino acid sequence set forth in SEQ ID NOs: 1 or 13 and said polypeptide having the activity of a β-ketoacyl synthase has at least 70% sequence identity to the amino acid sequence set forth in SEQ ID NO: 14 and said polypeptide having the activity of a CoA transferase has at least 70% sequence identity to the amino acid sequence set forth in SEQ ID NO: 19.4. The method of claim 3 , wherein said polypeptide having the activity of a β-ketothiolase has at least 70% sequence identity to the amino acid ...

SIMULTANEOUS ACCOMMODATION OF A LOW POWER SIGNAL AND AN INTERFERING SIGNAL IN A RADIO FREQUENCY (RF) RECEIVER

A method includes providing a highly linear front end in a Radio Frequency (RF) receiver, implementing a high Effective Number of Bits (ENOB) Analog to Digital Converter (ADC) circuit in the RF receiver, and sampling, through the high ENOB ADC circuit, at a frequency having harmonics that do not coincide with a desired signal component of an input signal of the RF receiver to eliminate spurs within a data bandwidth of the RF receiver. The input signal includes the desired signal component and an interference signal component. The interference signal component has a higher power level than the desired signal component. The method also includes simultaneously accommodating the desired signal component and the interference signal component in the RF receiver based on an increased dynamic range of the RF receiver and the high ENOB ADC circuit provided through the highly linear front end and the high ENOB ADC circuit. 1. A method comprising:providing a highly linear front end in a Radio Frequency (RF) receiver;implementing a high Effective Number of Bits (ENOB) Analog to Digital Converter (ADC) circuit in the RF receiver;sampling, through the high ENOB ADC circuit, at a frequency having harmonics that do not coincide with a desired signal component of an input signal of the RF receiver to eliminate spurs within a data bandwidth of the RF receiver, the input signal including the desired signal component and an interference signal component, and the interference signal component having a power level higher than that of the desired signal component; andsimultaneously accommodating the desired signal component and the interference signal component in the RF receiver based on an increased dynamic range of the RF receiver and the high ENOB ADC circuit provided through the highly linear front end and the high ENOB ADC circuit.2. The method of claim 1 ,wherein the RF receiver includes an RF mixer and an image reject mixer in a double superheterodyne configuration thereof, ...

GRAPHICS MEMORY EXTENDED WITH NONVOLATILE MEMORY

An embodiment of an electronic processing system may include an application processor, system memory communicatively coupled to the application processor, a graphics processor communicatively coupled to the application processor, graphics memory communicatively coupled to the graphics processor, and persistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media. The persistent storage media may include a low latency, high capacity, and byte-addressable nonvolatile memory. The one or more graphics assets may include one or more of a mega-texture and terrain data. Other embodiments are disclosed and claimed. 1. (canceled)2. A computing system comprising:a persistent storage media;a graphics processor;a central processing unit; anda memory including a set of instructions, which when executed by one or more of the graphics processor or the central processing unit, cause the computing system to:partition the persistent storage media into a first portion accessible by the graphics processor, and a second portion accessible by the central processing unit; andmap assets in the first portion for access by the graphics processor.3. The system of claim 2 , wherein the persistent storage media comprises a low latency claim 2 , high capacity claim 2 , and byte-addressable nonvolatile memory.4. The system of claim 2 , wherein the assets include one or more of a mega-texture or terrain data.5. The system of claim 2 , wherein graphics processor is to directly access the first portion.6. The system of claim 5 , wherein the graphics processor is to directly access the first portion so as to one or more of bypass a storage device driver stack associated with the persistent storage media or a file system stack.7. The system of claim 2 , wherein the instructions claim 2 , when executed claim 2 ...

Materials and methods utilizing biotin producing mutant hosts for the production of 7-carbon chemicals

Disclosed are methods for regulating biosynthesis of at least one of pimelic acid, 7-aminoheptanoic acid, 7-hydroxyheptanoic acid, heptamethylenediamine, 7-aminohelptanol and 1,7-heptanediol (C7 building blocks) using a pathway having a pimeloyl-ACP intermediate, the method including the step of downregulating the activity of BioF. Also disclosed are recombinant hosts by fermentation in which the above methods are performed. Further disclosed are recombinant hosts for producing pimeloyl-ACP, the recombinant host including a deletion of a bioF gene.

METHODS AND MATERIALS FOR BIOSYNTHESIZING MULTIFUNCTIONAL, MULTIVARIATE MOLECULES VIA CARBON CHAIN MODIFICATION

This document describes biochemical pathways for producing a difunctional product having an odd number of carbon atoms in vitro or in a recombinant host, or salts or derivatives thereof, by forming two terminal functional groups selected from carboxyl, amine, formyl, and hydroxyl groups in an aliphatic carbon chain backbone having an odd number of carbon atoms synthesized from (i) acetyl-CoA and propanedioyl-CoA via one or more cycles of methyl ester shielded carbon chain elongation or (ii) propanedioyl-[acp] via one or more cycles of methyl ester shielded carbon chain elongation. The biochemical pathways and metabolic engineering and cultivation strategies described herein rely on enzymes or homologs accepting methyl ester shielded aliphatic carbon chain backbones and maintaining the methyl ester shield for at least one further enzymatic step following one or more cycles of methyl ester shielded carbon chain elongation. 1. A method for biosynthesizing a difunctional product having an odd number of carbon atoms in vitro or in a recombinant host , said method comprising:enzymatically synthesizing an aliphatic carbon chain backbone having an odd number of carbon atoms from (i) acetyl-CoA and propanedioyl-CoA via one or more cycles of methyl ester shielded carbon chain elongation or (ii) propanedioyl-[acp] via one or more cycles of methyl ester shielded carbon chain elongation;enzymatically forming a first terminal functional group selected from carboxyl, amine, formyl, and hydroxyl groups in said backbone while maintaining said methyl ester shield for at least one further enzymatic step; andenzymatically forming a second terminal functional group selected from carboxyl, amine, formyl, and hydroxyl groups in said backbone, thereby forming said difunctional product.2. The method of claim 1 , wherein each of said one or more cycles of carbon chain elongation comprises using (i) a polypeptide having the activity of a β-ketoacyl-[acp] synthase or a β-ketothiolase claim 1 , ...

MATERIALS AND METHODS FOR DIRECTING CARBON FLUX AND INCREASED PRODUCTION OF CARBON BASED CHEMICALS

This disclosure relates to genome-scale attenuation or knockout strategies for directing carbon flux to certain carbon based building blocks within the 7-aminoheptanoic acid (7-AHA) and 6-aminohexanoic acid (6-AHA) biosynthesis pathways, for example, to achieve reduced flux to unwanted side products while achieving increased production of desired intermediates and end products. This disclosure also relates to non-naturally occurring mutant bacterial strains comprising one or more gene disruptions in aldehyde reductase and/or aldehyde dehydrogenase genes that are generated to direct carbon flux to certain carbon based building blocks. This disclosure further relates to a method for enhancing production of carbon based building blocks by generating non-naturally occurring mutant bacterial strains, culturing said mutant bacterial strains in the presence of suitable substrates or under desired growth conditions, and substantially purifying the desired end product. 1. A method for enhancing biosynthesis of 7-aminoheptanoic acid or 6-aminohexanoic acid comprising:a) generating a recombinant host comprising one or more gene disruptions in aldehyde reductase and/or aldehyde dehydrogenase genes, wherein said gene disruptions reduce aldehyde reductase and/or aldehyde dehydrogenase activity of polypeptides encoded by said genes, and wherein said recombinant host produces an increased level of 7-aminoheptanoic acid or 6-aminohexanoic acid converted from pimelic acid or pimelic acid derivatives or adipic acid or adipic acid derivatives as compared to a wild-type recombinant host;b) culturing said recombinant host in the presence of a suitable substrate or metabolic intermediate and under conditions suitable for the conversion of pimelic acid or pimelic acid derivatives to 7-aminoheptanoic acid or adipic acid or adipic acid derivatives to 6-aminohexanoic acid; andc) obtaining the 7-aminoheptanoic acid or 6-aminohexanoic acid.2. The method of claim 1 , wherein said pimelic acid ...

INTERCONNECT FABRIC LINK WIDTH REDUCTION TO REDUCE INSTANTANEOUS POWER CONSUMPTION

Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on the instantaneous throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on throughput demand from the client. 1. A parallel processor comprising:a first processing cluster including a first interface node, the first interface node having dynamically configurable ingress and egress bus widths; andan interconnect fabric coupled with the first interface node of the first processing cluster, the interconnect fabric including a dynamic bus module to dynamically configure active bus widths for connections to the first interface node, wherein the dynamic bus module is to dynamically configure a first active bus width for an ingress connection to the first interface node based on a first rate of data transfer requests through the first interface node and dynamically configure a second active bus width for an egress connection to the first interface node based on a second rate of data transfer requests through the first interface node, the first active bus width different from the second active bus width.2. The parallel processor as in claim 1 , the dynamic bus module to configure a bus frequency for the first interface node based on the first rate of data transfer requests or the second rate of data transfer requests.3. The parallel processor as in claim 1 , additionally comprising a second processing cluster including a second interface node claim 1 , the second interface node having a second ingress module and a second egress module claim 1 , wherein the dynamic bus module is to dynamically configure a third active bus width for an ingress connection to the second interface node based on a third rate of data ...

FIELD RECOVERY OF GRAPHICS ON-DIE MEMORY

Systems, apparatuses and methods may provide for technology that identifies a redundant portion of a packaged on-die memory and detects, during a field test of the packaged on-die memory, one or more failed cells in the packaged on-die memory. Additionally, one or more memory cells in the redundant portion may be substituted for the one or more failed memory cells. 1. (canceled)2. A system comprising:a power supply to provide power to the system; anda semiconductor package apparatus including a substrate, an on-die memory coupled to the substrate, and logic coupled to the substrate, wherein the on-die memory is to include a redundant portion, wherein the logic is implemented in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the substrate to:identify the redundant portion of the on-die memory,execute a field test on the on-die memory, wherein the field test is to include a program of a functional pattern into the on-die memory and a read of the on-die memory to determine whether the on-die memory was programmed correctly with the functional pattern, anddetect, during the field test of the on-die memory, one or more failed memory cells in the on-die memory.3. The system of claim 2 , wherein the logic coupled to the substrate is to reduce a size of the on-die memory in response to detection of the one or more failed memory cells.4. The system of claim 2 , wherein the logic coupled to the substrate is to conduct a fuse override to substitute one or more remaining memory cells in the redundant portion for the one or more failed memory cells.5. The system of claim 2 , wherein the logic coupled to the substrate is to execute the field test in response to one or more of each power down condition associated with the on-die memory claim 2 , each power up condition associated with the on-die memory claim 2 , an idleness condition associated with the on-die memory claim 2 , or an expiration of a periodic timer.6. The system of ...

CLOUD BASED DISTRIBUTED SINGLE GAME CALCULATION OF SHARED COMPUTATIONAL WORK FOR MULTIPLE CLOUD GAMING CLIENT DEVICES

Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices. 124-. (canceled)25. A graphics processing system , comprising: identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client devices of a plurality of users by analyzing the graphics data to detect view-independent graphics calculations, and', 'generate, in response to the identified redundant graphics calculations, a single calculation for common frame characteristics relating to the one or more graphical scenes to be shared by the client devices., 'a cloud computing server including a graphics processor having logic to26. The graphics processing system of claim 25 , wherein the graphics processor is to send the calculation of the common frame characteristics to the client devices to be visually presented as rendered visual content in a 3D virtual space.27. The graphics processing system of claim 25 , wherein the common frame characteristics comprises frame geometry.28. The graphics processing system of claim 25 , wherein the common frame characteristics comprises frame lighting.29. A graphics processing system claim 25 , comprising: identify, from graphics data in the graphics application, redundant texture maps relating to common frame characteristics of one or more graphical scenes to be shared between ...

METHODS AND MATERIALS FOR PRODUCING 7-CARBON MONOMERS

This document describes biochemical pathways for producing 7-aminoheptanoic acid using a β-ketoacyl synthase or a β-ketothiolase to form an N-acetyl-5-amino-3-oxopentanoyl-CoA intermediate. 7-aminoheptanoic acid can be enzymatically converted to pimelic acid, 7-hydroxyheptanoic acid, heptamethylenediamine or 1,7-heptanediol or corresponding salts thereof. This document also describes recombinant microorganisms producing 7-aminoheptanoic acid as well as pimelic acid, 7-hydroxyheptanoic acid, heptamethylenediamine and 1,7-heptanediol or corresponding salts thereof. 1. A method of producing N-acetyl-5-amino-3-oxopentanoyl-CoA or a salt thereof , said method comprising enzymatically converting N-acetyl-3-aminopropanoyl-CoA to N-acetyl-5-amino-3-oxopentanoyl-CoA or a salt thereof using a polypeptide having the activity of a β-ketoacyl synthase or a β-ketothiolase classified under EC. 2.3.1.- and/or a CoA transferase classified under EC 2.8.3.-.2. The method of claim 1 , wherein said polypeptide having the activity of a β-ketoacyl synthase is classified under EC 2.3.1.41 claim 1 , EC 2.3.1.179 or EC 2.3.1.180 and wherein said polypeptide having the activity of a β-ketothiolase is classified under EC 2.3.1.16 or EC 2.3.1.174.3. The method of any one of claim 1 , wherein said polypeptide having the activity of a β-ketothiolase has at least 70% sequence identity to the amino acid sequence set forth in SEQ ID NOs: 1 or 13 and said polypeptide having the activity of a β-ketoacyl synthase has at least 70% sequence identity to the amino acid sequence set forth in SEQ ID NO: 14 and said polypeptide having the activity of a CoA transferase has at least 70% sequence identity to the amino acid sequence set forth in SEQ ID NO: 19.4. The method of claim 3 , wherein said polypeptide having the activity of a β-ketothiolase has at least 70% sequence identity to the amino acid sequence set forth in SEQ ID NOs: 1 or 13 and is capable of converting N-acetyl-3-aminopropanoyl-CoA to N-acetyl- ...

Multi-resolution image plane rendering within an improved graphics processor microarchitecture

A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.

Controlling coarse pixel size from a stencil buffer

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

ENHANCED PROCESSES AND REAGENTS FOR HOST ENGINEERING

Nonnaturally occurring host cells altered to increase their ability to transfer genetic molecules into the host cells as compared to an unaltered host cell are provided. Also provided are methods for identifying endogenous loci of a host cell which inhibit transformation efficiency and/or electroporation of genetic molecules into the cell as well as methods for producing nonnaturally occurring host cells with enhanced transformation efficiency and/or the modified ability to allow for genomic integration of an exogenous DNA sequence via electroporation. Methods for producing biochemicals and products produced with the nonnaturally occurring host cells are also provided. 1. A nonnaturally occurring organism having at least one hereditary alteration which increases the ability to transfer genetic molecules into the organism as compared to an unaltered organism.2. The nonnaturally occurring organism of wherein the alteration increases transformation efficiency.3. The nonnaturally occurring organism of wherein the alteration allows for genomic integration of an exogenous DNA sequence via electroporation into the organism.4. The nonnaturally occurring organism of wherein the alteration increases transformation efficiency and allows for genomic integration of an exogenous DNA sequence via electroporation into the organism.5. The nonnaturally occurring organism of wherein the alteration comprises a genetic alteration.6. The nonnaturally occurring organism of wherein the alteration comprises deletion of an endogenous target locus.7. The nonnaturally occurring organism of wherein the alteration is deletion of an endogenous endonuclease locus.8Cupriavidus necator.. The nonnaturally occurring organism of which is a strain of9. The nonnaturally occurring organism of wherein the alteration is deletion of an endogenous target locus H16_A0006-9.10. The nonnaturally occurring organism of wherein the genetic molecule comprises an antibiotic resistance gene claim 1 , a Km-based claim ...

BEAM SCANNING IMAGE PROCESSING WITHIN AN IMPROVED GRAPHICS PROCESSOR MICROARCHITECTURE

Systems and methods may provide for determining a start time for an output image scanner to begin scanning an output image to a display device, determining a processing start time for each row of blocks of image pixel data within a rasterizer to ensure its completion before each row of blocks of image pixel data within the output image begin to be scanned out, and scheduling the start of processing of each row of blocks of image pixel data. In one example, the start time for the rasterizer to process a row of blocks of image pixel data uses the number of graphical objects to rendered into the output image and the processing times required by prior images. 1. (canceled)2. A computing system comprising:a data interface including one or more of a network controller, a memory controller or a bus, the data interface to obtain an output image comprising a plurality of pixel values stored within an image buffer memory and one or more graphical objects to be rendered within an output image associated with a three dimensional (3D) scene;an output image scanner to retrieve contents of the image buffer memory and output pixel values to a display device based on graphical objects; and a rasterizer to generate the output image containing the graphical objects;', 'an image block retriever coupled to the image buffer memory and the rasterizer, the image block retriever to retrieve a row of pixel data from a row of image pixel tiles having one or more rows of pixel data, for use by the rasterizer; and', determine a start time for the output image scanner to begin scanning the output image to the display device,', 'determine a processing start time for each row of tiles of image pixel data within the rasterizer to ensure a completion of the rasterizer before the row of tiles of image pixel data within the output image begin to be scanned out, and', 'schedule a start of processing of rows of tiles of image pixel data,', 'wherein the image block processing scheduler is to schedule a ...

MOTION BIASED FOVEATED RENDERER

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed. 1an application processor;persistent storage media communicatively coupled to the application processor;a graphics subsystem communicatively coupled to the application processor;a sense engine communicatively coupled to the graphics subsystem to provide sensed information;a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information;a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information; anda motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, and the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information.. An electronic processing system, comprising: The present application claims the benefit of priority to U.S. Non-Provisional patent application Ser. No. 15/477,019 filed on Apr. 1, 2017.Embodiments generally relate to data processing and to graphics processing via a graphics ...

BIOSYNTHETIC ORGANISMS WITH ENHANCED CARBON UTILIZATION

Nonnaturally occurring organisms exhibiting improved carbon utilization and methods for production and use of these nonnaturally occurring organisms in chemical production from carbon containing feedstocks are provided. 1. A nonnaturally occurring organism which exhibits increased carbon utilization , said nonnaturally occurring organism comprising a disruption in a cbbX gene leading to increased carbon utilization as compared to an organism without the disruption.2C. necator. The nonnaturally occurring organism of wherein the nonnaturally occurring organism is a mutant species or an organism with properties similar thereto.3. The nonnaturally occurring organism of which exhibits increased polyol utilization.4. The nonnaturally occurring organism of which exhibits increased glycerol utilization.5. A method for production of a nonnaturally occurring organism which exhibits increased carbon utilization claim 1 , said method comprising introducing a disruption into a cbbX gene of the organism leading to improved carbon utilization as compared to an organism without disruption.6C. necator. The method of wherein the nonnaturally occurring organism is a mutant species or an organism with properties similar thereto.7. The method of wherein the nonnaturally occurring organism exhibits increased polyol utilization.8. The method of wherein the nonnaturally occurring organism exhibits increased glycerol utilization.9. A method for producing a chemical from a carbon containing feedstock claim 1 , said method comprising contacting the feedstock with the nonnaturally occurring organism of .10. The method of wherein the produced chemical is selected from a polyhydroxyalkanoates (PHA) claim 9 , a nylon intermediate claim 9 , a butanediol claim 9 , a butanol claim 9 , succinic acid claim 9 , butadiene claim 9 , isoprene claim 9 , and 3-hydroxypropanoic acid.11. A bio-derived claim 1 , bio-based claim 1 , or fermentation-derived product produced using the nonnaturally occurring ...

Extending beamforming capability of a coupled voltage controlled oscillator (vco) array during local oscillator (lo) signal generation through a circular configuration thereof

A method includes separating phase of Local Oscillator (LO) signals generated by individual Voltage Controlled Oscillators (VCOs) of a coupled VCO array through varying voltage levels of voltage control inputs thereto. The method also includes coupling the individual VCOs of the coupled VCO array to one another in a closed, circular configuration to increase phase difference between the phase separated LO signals generated by the individual VCOs compared to a linear configuration of the coupled VCO array. Further, the method includes mixing outputs of the individual VCOs of the circular coupled VCO array with signals from antenna elements of an antenna array to introduce differential phase shifts in signal paths coupled to the antenna elements during performing beamforming with the antenna array.

PHASE SHIFT BASED IMPROVED REFERENCE INPUT FREQUENCY SIGNAL INJECTION INTO A COUPLED VOLTAGE CONTROLLED OSCILLATOR (VCO) ARRAY DURING LOCAL OSCILLATOR (LO) SIGNAL GENERATION TO REDUCE A PHASE-STEERING REQUIREMENT DURING BEAMFORMING

A method includes injecting a reference input signal into each Voltage Controlled Oscillator (VCO) of a number of VCOs forming a coupled VCO array to reduce a level of injection energy required therefor. The reference input signal is configured to control operating frequency of the coupled VCO array. The method also includes utilizing a phase shift circuit: between individual VCOs of the coupled VCO array and/or in a path of injection of the reference input signal into one or more VCO(s) of the individual VCOs, and mixing outputs of the number of VCOs with signals from antenna elements of an antenna array to introduce differential phase shifts in signal paths coupled to the antenna elements during performing beamforming with the antenna array. Further, the method includes reducing a phase-steering requirement of the coupled VCO array during the beamforming based on the utilization of the phase shift circuit. 1. A method comprising:injecting a reference input signal into each Voltage Controlled Oscillator (VCO) of a plurality of VCOs forming a coupled VCO array to reduce a level of injection energy required therefor compared to injecting the reference input signal at an end of the coupled VCO array, the reference input signal being configured to control operating frequency of the coupled VCO array;utilizing a phase shift circuit at least one of: between individual VCOs of the coupled VCO array and in a path of injection of the reference input signal into at least one VCO of the individual VCOs;mixing outputs of the plurality of VCOs of the coupled VCO array with signals from antenna elements of an antenna array to introduce differential phase shifts in signal paths coupled to the antenna elements during performing beamforming with the antenna array; andreducing a phase-steering requirement of the coupled VCO array during the beamforming based on the utilization of the phase shift circuit.2. The method of claim 1 , further comprising injection locking two or more VCOs ...

Methods and materials for the biosynthesis of compounds of fatty acid metabolism and related compounds

Methods and materials for the production of compounds involved in fatty acid metabolism, and/or derivatives thereof and/or compounds related thereto are provided. Also provided are products produced in accordance with the methods and materials of the present invention.

Augmented reality virtual reality ray tracing sensory enhancement system, apparatus and method

Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

Methods and materials for producing 7-carbon monomers

This document describes biochemical pathways for producing 7-aminoheptanoic acid using a β-ketoacyl synthase or a β-ketothiolase to form either a 5-amino-3-oxopentanoyl-[ACP] or 5-amino-3-oxopentanoyl-CoA intermediate. 7-aminoheptanoic acid can be enzymatically converted to pimelic acid, 7-hydroxyheptanoic acid, heptamethylenediamine or 1,7-heptanediol or the corresponding salts thereof. This document also describes recombinant microorganisms producing 7-aminoheptanoic acid as well as pimelic acid, 7-hydroxyheptanoic acid, heptamethylenediamine and 1,7-heptanediol or the corresponding salts thereof.

Augmented reality virtual reality ray tracing sensory enhancement system, apparatus and method

Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

PROCESSOR POWER MANAGEMENT

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed. 118-. (canceled)19. An apparatus comprising:one or more processors including a graphical processing unit (GPU), the GPU including a graphics processing pipeline, the graphics processing pipeline including a plurality of stages; anda memory to store data, including graphics data processed by the graphics processing pipeline; collect one or more performance metrics associated with operation of each stage of the plurality of stages of the graphics processing pipeline, and', 'adjust at least one of an operating voltage or an operating frequency for one or more stages of the plurality of stages based at least in part on the one or more performance metrics for each stage., 'wherein the apparatus is to20. The apparatus of claim 19 , wherein adjusting at least one of the operating voltage or the operating frequency for the one or more stages includes the apparatus to:determining a level of activity for each stage the plurality of stages utilizing at least the one or more performance metrics; andadjust at least one of an operating voltage or an operating frequency for the one or more stages based at least in part on the determined level of activity for each stage of the plurality of stages.21. The apparatus of claim 20 , wherein the apparatus is to perform one or more of:increase the operating voltage or operating frequency for a first stage that is determined to have a higher level of activity in the plurality of stages; ordecrease the operating voltage or operating frequency for a second stage that is ...

Processor power management

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Motion biased foveated renderer

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

Multi-resolution image plane rendering within an improved graphics processor microarchitecture

A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.

Enhanced processes and reagents for host engineering

Nonnaturally occurring host cells altered to increase their ability to transfer genetic molecules into the host cells as compared to an unaltered host cell are provided. Also provided are methods for identifying endogenous loci of a host cell which inhibit transformation efficiency and/or electroporation of genetic molecules into the cell as well as methods for producing nonnaturally occurring host cells with enhanced transformation efficiency and/or the modified ability to allow for genomic integration of an exogenous DNA sequence via electroporation. Methods for producing biochemicals and products produced with the nonnaturally occurring host cells are also provided. In particular, a host Cupriavidus necator cell is provided in which a chromosomal gene encoding a restriction endonuclease has been disrupted, leading to an increase in transformation efficiency.

GRAPHICS MEMORY EXTENDED WITH NONVOLATILE MEMORY

An embodiment of an electronic processing system may include an application processor, system memory communicatively coupled to the application processor, a graphics processor communicatively coupled to the application processor, graphics memory communicatively coupled to the graphics processor, and persistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media. The persistent storage media may include a low latency, high capacity, and byte-addressable nonvolatile memory. The one or more graphics assets may include one or more of a mega-texture and terrain data. Other embodiments are disclosed and claimed. 1. An electronic processing system , comprising:an application processor;system memory communicatively coupled to the application processor;a graphics processor communicatively coupled to the application processor;graphics memory communicatively coupled to the graphics processor; andpersistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media.2. The system of claim 1 , wherein the persistent storage media comprises a low latency claim 1 , high capacity claim 1 , and byte-addressable nonvolatile memory.3. The system of claim 1 , wherein the one or more graphics assets include one or more of a mega-texture and terrain data.4. A graphics memory apparatus claim 1 , comprising:persistent storage media to store one or more graphics assets; anda memory mapper to map a physical location of the one or more graphics assets to a memory location accessible by a graphics application.5. The apparatus of claim 4 , wherein the persistent storage media comprises a byte-addressable persistent ...

Controlling coarse pixel size from a stencil buffer

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

BEAM SCANNING IMAGE PROCESSING WITHIN AN IMPROVED GRAPHICS PROCESSOR MICROARCHITECTURE

Systems and methods may provide for determining a start time for an output image scanner to begin scanning an output image to a display device, determining a processing start time for each row of blocks of image pixel data within a rasterizer to ensure its completion before each row of blocks of image pixel data within the output image begin to be scanned out, and scheduling the start of processing of each row of blocks of image pixel data. In one example, the start time for the rasterizer to process a row of blocks of image pixel data uses the number of graphical objects to rendered into the output image and the processing times required by prior images. 1. A computing system comprising:a data interface including one or more of a network controller, a memory controller or a bus, the data interface to obtain an output image comprising a plurality of pixel values stored within an image buffer memory and one or more graphical objects to be rendered within an output image associated with a three dimensional (3D) scene;an output image scanner to retrieve the contents of the image buffer memory and out pixel values to a display device based on graphical objects; and a rasterizer to generate the output image containing the graphical objects;', 'a image block retriever coupled to the image buffer memory and the rasterizer, the image block retriever to retrieve a row of pixel data from a row of image pixel tiles having one or more rows of pixel data, for use by the rasterizer; and', determines a start time for the output image scanner to begin scanning the output image to the display device,', 'determines the processing start time for each row of tiles of image pixel data within the rasterizer to ensure a completion of the rasterizer before the row of tiles of image pixel data within the output image begin to be scanned out, and', 'schedules a start of processing of rows of tiles of image pixel data., 'an image block processing scheduler to schedule the start of processing ...

Augmented reality and virtual reality feedback enhancement system, apparatus and method

Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.

CLOUD BASED DISTRIBUTED SINGLE GAME CALCULATION OF SHARED COMPUTATIONAL WORK FOR MULTIPLE CLOUD GAMING CLIENT DEVICES

Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices. 1. A computing system , comprising:a memory to store a set of instructions; and a substrate,', 'a host processor operatively coupled to the substrate, wherein when executed by the host processor, the set of instructions cause the host processor to execute a graphics application, and', 'a graphics processor operatively coupled to the substrate, wherein the graphics processor includes logic to:', 'identify, from graphics data in the graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users;', 'calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes; and', 'send, over a computer network, the calculation of the frame characteristics to the client game devices;, 'a cloud computing server coupled to the memory, the cloud server includinga display, operatively coupled to the cloud computing server, to visually present rendered visual content in a 3D virtual space.2. The system of claim 1 , wherein the graphics processor includes logic to detect claim 1 , prior to identifying redundant graphics calculations claim 1 , an initiation of a game session.3. The system of claim 1 , wherein the frame characteristics comprises frame ...

ORDER INDEPENDENT ASYNCHRONOUS COMPUTE AND STREAMING FOR GRAPHICS

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed. 1. An electronic processing system , comprising:an application processor;persistent storage media communicatively coupled to the application processor;a graphics subsystem communicatively coupled to the application processor;a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls;a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode;a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage; andan order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage.2. The system of claim 1 , wherein the draw call re-orderer includes:an order dependency analyzer to determine an order dependency between the two or more draw calls, wherein the draw call re-orderer is further to re-order the ...

AUGMENTED REALITY AND VIRTUAL REALITY FEEDBACK ENHANCEMENT SYSTEM, APPARATUS AND METHOD

Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment. 1. A system comprising:a power source to supply power to the system;a memory comprising n-dimensional environment information, the memory coupled to a processor; and an observer monitor to monitor one or more actions of an observer observing the n-dimensional environment information, the environment information including feedback information;', 'a feedback manager to detect feedback information, wherein feedback information includes a priority relationship to the observer, wherein the priority relationship identifies one or more of observer directed feedback information directed to the observer or undirected feedback information;', 'a ray tracing engine to normalize the environment information, including normalize the feedback information, to a location of the observer, wherein the graphics pipeline apparatus renders the normalized feedback information based on one or more of the actions of the observer or the priority relationship of the feedback information to the observer., 'a graphics pipeline apparatus comprising2. The system of claim 1 , wherein the feedback manager attenuates one or more feedback devices based on one or more operating parameters claim 1 , wherein the feedback devices are coupled to the graphics pipeline apparatus claim 1 , wherein the feedback manager identifies the feedback information as known feedback information or unknown feedback information claim 1 , wherein the feedback manager requests unknown feedback identifier training claim 1 , when the unknown feedback information ...

Interconnect fabric link width reduction to reduce instantaneous power consumption

Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on the instantaneous throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on throughput demand from the client.

GRAPHICS CONTROL FLOW MECHANISM

An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels. 1. An apparatus to facilitate control flow in a graphics processing system comprising: a plurality of execution units to execute single instruction, multiple data (SIMD); and', 'flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels., 'a graphics processor, including2. The apparatus of claim 1 , wherein the flow control logic detects SIMD channels that are active and identifies a code region impacted by the diverging control flow.3. The apparatus of claim 2 , wherein the logic to detect the active SIMD channels detects whether the number of active SIMD channels is below a predetermined threshold percentage of the plurality of SIMD channels.4. The apparatus of claim 3 , wherein the flow control logic comprises packs input to the active SIMD channels into a subset of the SIMD channels upon a determination that the number of active SIMD channels is below the predetermined threshold percentage.5. The apparatus of claim 4 , wherein the logic to detect the active SIMD channels detects whether the active SIMD channels are spread over multiple SIMD sections.6. The apparatus of claim 5 , wherein the flow control logic prevents packing input to the active SIMD channels into a subset of the SIMD channels upon detecting that the active SIMD channels are not spread over multiple SIMD sections.7. The apparatus of claim 2 , wherein the logic to identify the code region duplicates the identified code region within the subset of the SIMD channels.8. The apparatus of claim 7 , wherein the subset of the SIMD channels ...

DYNAMIC DISTRIBUTED TRAINING OF MACHINE LEARNING MODELS

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed. 1. An apparatus comprising:a plurality of compute engines comprising logic, at least partially including hardware logic, to train a neural network; anda hardware engine to accelerate a weight update process for training the neural network.2. The apparatus of claim 1 , wherein:the hardware engine implements fast operations to average weights from a plurality of nodes in the neural network.3. The apparatus of claim 2 , wherein:the neural network comprises a plurality of sub-neural networks; andeach sub-neural network is trained separately.4. The apparatus of claim 3 , further comprising logic claim 3 , wherein:the plurality of sub-neural networks operate according to a priority.5. The apparatus of claim 4 , wherein:the output of a first sub-neural network may be provided as an input to a second sub-neural network.6. The apparatus of claim 1 , wherein:a decision making routine of the neural network executes on at least two different compute engines.7. The apparatus of claim 6 , further comprising logic claim 6 , at least partially including hardware logic claim 6 , to:compare results of the decision making routine executed on the at least two different compute engines.8. The apparatus of claim 7 , further comprising a driver comprising logic claim 7 , at least partially including hardware logic claim 7 , to:continue processing if the results of the decision making routine executed on the at least two different compute engines match.9. The apparatus of claim 8 , further comprising a thread scheduler comprising logic claim 8 , at least partially including hardware logic claim 8 , to: ...

POSITIONAL ONLY SHADING PIPELINE (POSH) GEOMETRY DATA PROCESSING WITH COARSE Z BUFFER

The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones. 1. A system comprising:a power source to supply power to the system; position geometry data, the geometry data including surface triangles for a digital representation of a scene;', 'perform a screen space transformation; and', 'cull at least one of the surface triangles; and, 'a positional only shading pipeline to, 'a graphics pipeline apparatus comprisinga render pipe to render the surface triangles remaining following the culling.2. The system of claim 1 , wherein the positional only shading pipeline identifies the at least one of the surface triangles culled as exclusion triangles and the surface triangles remaining following the culling as non-exclusion triangles claim 1 , wherein the surface triangles identified as exclusion triangles include at least a portion of the surface triangles in one or more exclusion zones claim 1 , and wherein the surface triangles identified as non-exclusion triangles include the surface triangles in one or more non-exclusion zones.3. The system of claim 2 , wherein the non-exclusion zones and non-exclusion zones are sized based on culling parameters claim 2 , and wherein the culling parameters include one or more of lens parameters for depth perception of near plans and far plans claim 2 , performance parameters claim 2 , head mounted display parameters or other device parameters.4. The system of claim 3 , wherein the graphics pipeline apparatus exposes the surface triangles to a vertex shader claim 3 , ...

FIELD RECOVERY OF GRAPHICS ON-DIE MEMORY

Systems, apparatuses and methods may provide for technology that identifies a redundant portion of a packaged on-die memory and detects, during a field test of the packaged on-die memory, one or more failed cells in the packaged on-die memory. Additionally, one or more memory cells in the redundant portion may be substituted for the one or more failed memory cells. 1. A system comprising:a display;a power supply to provide power to the system; anda semiconductor package apparatus including a substrate, an on-die memory coupled to the substrate, the on-die memory including a redundant portion, and logic coupled to the substrate, wherein the logic is implemented in one or more of configurable logic or fixed-functionality hardware logic, the logic to:identify the redundant portion of the on-die memory,detect, during a field test of the on-die memory, one or more failed memory cells in the on-die memory, andsubstitute one or more memory cells in the redundant portion for the one or more failed memory cells.2. The system of claim 1 , wherein the logic is to program a fuse override to a permanent data structure to substitute the one or memory cells in the redundant portion for the one or more failed memory cells.3. The system of claim 1 , wherein the field test is to include a built-in self-test process.4. The system of claim 1 , wherein the logic is to execute the field test in response to one or more of a periodic timer expiration claim 1 , a power down condition claim 1 , a power up condition or an idleness condition.5. The system of claim 1 , wherein redundant portion includes one or more of redundant rows or redundant columns.6. The system of claim 1 , wherein the on-die memory includes one or more of a graphics cache or a graphics register file.7. An apparatus comprising:a substrate;an on-die memory coupled to the substrate, the on-die memory including a redundant portion; andlogic coupled to the substrate, wherein the logic is implemented in one or more of ...

GAAS/SIGE-BICMOS-Based Transceiver System-in-Package for E-Band Frequency Applications

An e-band transceiver includes a transmitter circuit and a receiver circuit. The transmitter circuit includes a surface mounted technology (SMT) module on which is mounted a silicon-germanium (SiGe) bipolar plus CMOS (BiCMOS) converter, a gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (pHEMT) output amplifier coupled to the SiGe BiCMOS converter, and a microstrip/waveguide interface coupled to the GaAs pHEMT output amplifer. The receiver circuit of the e-band transceiver includes a receiver-side SMT module on which is mounted a receiver-side SiGe BiCMOS converter, a GaAs pHEMT low noise amplifier coupled to the receiver-side SiGe BiCMOS converter, and a receiver-side microstrip/waveguide interface coupled to the receiver-side GaAs pHEMT low noise amplifier. 1. An e-band transceiver comprising a transmitter circuit and a receiver circuit , wherein the transmitter circuit comprises: a silicon-germanium (SiGe) bipolar plus CMOS (BiCMOS) converter,', 'a gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (pHEMT) output amplifier coupled to the SiGe BiCMOS converter, and', 'a microstrip/waveguide interface coupled to the GaAs pHEMT output amplifer., 'a surface mounted technology (SMT) module including2. The e-band transceiver of claim 1 , wherein the SiGe BiCMOS converter further comprises a digital interface.3. The e-band transceiver of claim 2 , wherein the digital interface is configured as a digital control interface for controlling one of bias claim 2 , type of channel filters and output power levels of the SMT module.4. The e-band transceiver of claim 3 , wherein the digital control interface is configured as one of an IC or SPI interface.5. The e-band transceiver of claim 2 , wherein the digital interface is coupled to a non-volatile memory.6. The e-band transceiver of claim 5 , wherein the non-volatile memory is configured to store calibration data.7. The e-band transceiver of claim 1 , wherein the SMT module is a ...

AUGMENTED REALITY VIRTUAL REALITY RAY TRACING SENSORY ENHANCEMENT SYSTEM, APPARATUS AND METHOD

Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience. 1. A system comprising:a power source to supply power to the system;a memory comprising environment information, the memory coupled to a processor; and normalize the environment information to a position of an observer to generate normalized environment information for the observer;', 'calculate, for the observer, the sound sources or sensed events vector paths;', 'generate a number of ray bundles for the sounds, the ray bundles including a number of frequency bands based on acoustic properties of one or more of the sound sources, wherein the environment information is further to include one or more objects or surfaces in the path of one or more of the vector paths, and wherein the ray bundles are to be based on one or more of the acoustic properties of the sound, the objects, or the surfaces;', 'apply an absorption filter, an attenuation filter, and a reflective filter to the normalized environment information, based on the vector path attributes of the sound or the sensed events; and', 'play back the normalized environment information to the observer based on the vector paths., 'a ray tracing engine to, 'a graphics pipeline apparatus comprising2. The system of claim 1 , wherein the vector paths include vector path attributes including one more of positional information or directional information claim 1 , wherein the environment information is captured by one or more capture devices ...

POSITIONAL ONLY SHADING PIPELINE (POSH) GEOMETRY DATA PROCESSING WITH COARSE Z BUFFER

The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones. 1. (canceled)2. A graphics processing unit comprising: compute a position of geometry data, the geometry data including surface triangles for a digital representation of a scene;', 'cull at least one of the surface triangles;', 'identify the at least one of the surface triangles culled as exclusion triangles and the surface triangles remaining following the culling as non-exclusion triangles, wherein the surface triangles identified as exclusion triangles include at least a portion of the surface triangles in one or more exclusion zones, and wherein the surface triangles identified as non-exclusion triangles include the surface triangles in one or more non-exclusion zones;', 'adjust a granularity setting for the exclusion zones or the non-exclusion zones based on a position of one or more of the surface triangles, lens parameters for depth perception, or attributes of stream out data, wherein the attributes of the stream out data include one or more of granularity of the stream out data, motion or direction of one or more objects or a gaze of a user; and', 'based on the adjustment of the granularity setting for the exclusion zones or the non-exclusion zones, expose the stream out data to a vertex shader., 'a processor to3. The graphics processing unit of claim 2 , wherein the processor is further to:create a coarse Z buffer while processing the geometry data, andstore one or more of the surface triangles in a coarse Z order as coarse Z ...

MATERIALS AND METHODS FOR DIFFERENTIAL BIOSYNTHESIS IN SPECIES OF THE GENERA RALSTONIA AND CUPRIAVIDUS AND ORGANISMS RELATED THERETO

Methods for increasing carbon-based chemical product yield in an organism by increasing carbon uptake and/or altering a pathway to or from an overflow metabolite in the organism, nonnaturally occurring organisms having increased carbon-based chemical product yield with increased carbon uptake and/or an altered pathway to or from an overflow metabolite, and methods for producing a carbon-based chemical product with these organisms are provided. 1CupriavidusRalstonia. A method for increasing carbon-based chemical product yield in an organism , said method comprising modifying an organism selected from a species of or with diminished polyhydroxybutyrate synthesis or an organism with properties similar thereto by modulating activity of one or more polypeptides or functional fragments thereof functioning to increase carbon uptake and/or in a pathway to or from an overflow metabolite , thereby increasing carbon-based chemical product yield in the organism as compared to an organism without said modulated polypeptide activity.2. The method of wherein said one or more polypeptides or functional fragments thereof functioning to increase carbon uptake comprise one or more carbon transporter proteins selected from TctA claim 1 , TctB or TctC or a functional fragment thereof.3. The method of wherein said one or more polypeptides or functional fragments thereof functioning in a pathway to or from an overflow metabolite is selected from Table 2.4. The method of wherein said one or more polypeptides or functional fragments thereof functioning in a pathway to or from an overflow metabolite is selected from any one of lactate claim 3 , hydroxybutyrate claim 3 , acetate and/or 2 claim 3 ,3 butandiol.5. The method of claim 1 , wherein modulating the activity of one or more polypeptides comprises overexpressing or mutating an endogenous or exogenous nucleic acid sequence in the organism.6. The method of claim 1 , wherein modulating the activity of one or more polypeptides or functional ...

Materials and methods for controlling regulation in biosynthesis in species of the genera ralstonia or cupriavidus and organisms related thereto

Methods for increasing carbon-based chemical product yield in an organism by genetically modifying one or more genes involved in a stringent response and/or in a regulatory network, nonnaturally occurring organisms having increased carbon-based chemical product yield, and methods for use in production of carbon-based chemical products are provided.

CLOUD BASED DISTRIBUTED SINGLE GAME CALCULATION OF SHARED COMPUTATIONAL WORK FOR MULTIPLE CLOUD GAMING CLIENT DEVICES

Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices. 1. (canceled)2. An apparatus , comprising:a graphics processor of a cloud server, the graphics processor to identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users participating in a gaming session by analyzing the graphics data to detect view-independent graphics calculations.3. The apparatus of claim 2 , wherein the graphics processor is to perform claim 2 , in response to the identified redundant graphics calculations claim 2 , a calculation for common frame characteristics relating to the one or more graphical scenes to be shared by the client devices during the gaming session.4. The apparatus of claim 3 , wherein the graphics processor is to send the calculation of the common frame characteristics to the client game devices to be visually presented as rendered visual content in a 3D virtual space.5. The apparatus of claim 2 , wherein the graphics processor is to detect claim 2 , prior to identifying redundant graphics calculations claim 2 , an initiation of the gaming session.6. The apparatus of claim 2 , wherein the common frame characteristics comprises frame geometry.7. The apparatus of claim 2 , wherein the common frame characteristics comprises frame ...

FIELD RECOVERY OF GRAPHICS ON-DIE MEMORY

Systems, apparatuses and methods may provide for technology that identifies a redundant portion of a packaged on-die memory and detects, during a field test of the packaged on-die memory, one or more failed cells in the packaged on-die memory. Additionally, one or more memory cells in the redundant portion may be substituted for the one or more failed memory cells. 1. (canceled)2. A system comprising:a display;a power supply to provide power to the system; anda semiconductor package apparatus including a substrate, an on-die memory coupled to the substrate, the on-die memory including a redundant portion, and logic coupled to the substrate, wherein the logic is implemented in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the substrate to:identify the redundant portion of the on-die memory,adjust a periodic timer in accordance with a likelihood of failure of the on-die memory,execute a field test on the on-die memory in response to one or more of an expiration of the periodic timer, each power down condition associated with the on-die memory, each power up condition associated with the on-die memory or an idleness condition associated with the on-die memory,detect, during the field test of the on-die memory, one or more failed memory cells in the on-die memory, andsubstitute one or more remaining memory cells in the redundant portion for the one or more failed memory cells.3. The system of claim 2 , wherein the logic coupled to the substrate is to execute the field test in response to the expiration of the periodic timer.4. The system of claim 2 , wherein the logic coupled to the substrate is to execute the field test in response to each power down condition associated with the on-die memory.5. The system of claim 2 , wherein the logic coupled to the substrate is to execute the field test in response to each power up condition associated with the on-die memory.6. The system of claim 2 , wherein the logic coupled to the ...

MATERIALS AND METHODS FOR BIOSYNTHETIC MANUFACTURE OF CARBON-BASED CHEMICALS

This disclosure relates to strategies for in vivo production of certain carbon-based products, for example, aminated aliphatic compounds having a carbon chain length of C5-C19. 1. A method for improved biosynthesis of an aminated aliphatic compound , the method comprising:a) providing a recombinant organism capable of biosynthesizing an aminated aliphatic compound; wherein the recombinant organism has been engineered to comprise one or more exogenous, modified, or overexpressed polypeptides; wherein each of the one or more polypeptides independently encodes at least one enzyme of an aminated aliphatic compound biosynthesis or export pathway; and wherein at least one of the one or more polypeptides encodes an ω-transaminase having at least 70% identity to SEQ ID NO: 1, or a functional fragment thereof; andb) culturing the recombinant organism under conditions suitable for the recombinant organism to produce the aminated aliphatic compound or a salt thereof2. The method of claim 1 , wherein the recombinant organism has been engineered to comprise two or more exogenous claim 1 , modified claim 1 , or overexpressed polypeptides; and wherein the two or more polypeptides each independently encode at least one enzyme selected from the group consisting of an ω-transaminase claim 1 , a thioesterase claim 1 , a carboxylate reductase claim 1 , an acetyl-CoA synthetase claim 1 , a β-alanine CoA transferase claim 1 , a 6-phosphogluconate dehydrogenase claim 1 , a transketolase claim 1 , a puridine nucleotide transhydrogenase claim 1 , a glyceraldehyde-3P-dehydrogenase claim 1 , a malic enzyme claim 1 , a glucose-6-phosphate dehydrogenase claim 1 , a glucose dehydrogenase claim 1 , a fructose 1 claim 1 ,6 diphosphatase claim 1 , an L-alanine dehydrogenase claim 1 , a L-glutamate dehydrogenase claim 1 , a formate dehydrogenase claim 1 , an L-glutamine synthetase claim 1 , a diamine transporter claim 1 , a dicarboxylate transporter claim 1 , an amino acid transporter claim 1 , and ...

MATERIALS AND METHODS FOR BIOSYNTHETIC MANUFACTURE AND UTILIZATION OF SYNTHETIC POLYPEPTIDES, AND PRODUCTS THEREFROM

Provided herein are novel, synthetic polypeptides having, for example, acyl-acyl carrier protein (ACP) thioesterase (TE) activity, including polypeptides that convert pimeloyl-ACP to pimelic acid. In some aspects, the synthetic polypeptides have advantageous enzymatic activity and/or improved substrate specificity relative to a wild type acyl-ACP TE. 1. A polypeptide having an acyl-acyl carrier protein (ACP) thioesterase (TE) activity , wherein the polypeptide having acyl-ACP TE activity comprises one or more amino acid substitution(s) relative to a wild-type acyl-ACP TE , wherein the one or more amino acid substitution(s) are at amino acid(s) that occupy position(s) corresponding to position(s) 5 , 32 , 33 , 35 , 36 , 38 , 40 , 45 , 59 , 64 , 90 , 111 , 128 , 175 , and 241 of SEQ ID NO: 1 , or a functional fragment thereof.2. The polypeptide of claim 1 , wherein the wild-type acyl-ACP TE is an acyl-ACP TE classified under EC 3.1.2.-.3. The polypeptide of claim 1 , wherein the amino acid corresponding to position 5 is substituted with tyrosine (Y) or an equivalent amino acid.4. The polypeptide of claim 1 , wherein the amino acid at position 35 is substituted with serine (S) or an equivalent amino acid.5. The polypeptide of claim 1 , wherein the amino acid at position 38 is substituted with glutamine (Q) or an equivalent amino acid.6. The polypeptide of claim 1 , wherein the amino acid at position 64 is substituted with valine (V) or an equivalent amino acid.7. The polypeptide of claim 1 , wherein the amino acid at position 241 is substituted with glutamic acid (E) or an equivalent amino acid.8. The polypeptide of claim 1 , wherein the amino acid at position 45 is substituted with methionine or isoleucine (I) or an equivalent amino acid.9. The polypeptide of claim 1 , wherein the amino acid at position 128 is substituted with tyrosine (Y) or an equivalent amino acid.10. The polypeptide of claim 1 , wherein the amino acid at position 175 is substituted with serine (S) ...

ORDER INDEPENDENT ASYNCHRONOUS COMPUTE AND STREAMING FOR GRAPHICS

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed. 1. (canceled)2. A computing system for graphics data processing , the computing system comprising:one or more processors; and determine an order dependency between two or more draw calls;', 're-order the two or more draw calls based on the determined order dependency;', 're-order two or more work items in an order independent mode, wherein the order independent mode is made in response to a guarantee of memory dependency, when the guarantee is made for a particular phase of rendering in a first mode of operation and for an entire application in a different second mode of operation;', 'define a producer stage and a consumer stage; and', 'provide tile-based order independent execution of a compute stage., 'a memory coupled to the one or more processors, the memory including executable program instructions, which when executed by the host processor, cause the computing system to3. The system of claim 2 , wherein the re-order of two or more work items includes operations to:determine a work split for the two or more work items, and re-order the two ...

GAAS/SIGE-BICMOS-BASED TRANSCEIVER SYSTEM-IN-PACKAGE FOR E-BAND FREQUENCY APPLICATIONS

An e-band transceiver includes a transmitter circuit and a receiver circuit. The transmitter circuit includes a surface mounted technology (SMT) module on which is mounted a silicon-germanium (SiGe) bipolar plus CMOS (BiCMOS) converter, a gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (pHEMT) output amplifier coupled to the SiGe BiCMOS converter, and a microstrip/waveguide interface coupled to the GaAs pHEMT output amplifer. The receiver circuit of the e-band transceiver includes a receiver-side SMT module on which is mounted a receiver-side SiGe BiCMOS converter, a GaAs pHEMT low noise amplifier coupled to the receiver-side SiGe BiCMOS converter, and a receiver-side microstrip/waveguide interface coupled to the receiver-side GaAs pHEMT low noise amplifier. 1. An apparatus comprising:a package having an interface;an up-converter (i) implemented in a bipolar-plus-CMOS technology, (ii) disposed in said package and (iii) configured to generate a transmit signal, wherein said transmit signal has a frequency in a millimeter wave frequency range;a power amplifier (i) implemented in a pseudomorphic high-electron-mobility transistor technology, (ii) disposed in said package, and (iii) configured to amplify said transmit signal;a transmit waveguide configured to carry said transmit signal from said power amplifier to said interface; anda memory configured to store calibration data that allows a chip-by-chip calibration.2. The apparatus according to claim 1 , wherein said frequency of said transmit signal is between approximately 40 gigahertz and approximately 86 gigahertz.3. The apparatus according to claim 1 , wherein said frequency of said transmit signal is in an E-band.4. The apparatus according to claim 1 , wherein said calibration data avoids a calibration rejection procedure.5. The apparatus according to claim 1 , wherein (i) said a bipolar-plus-CMOS technology comprises a Silicon-Germanium bipolar-plus-CMOS technology and (ii) said ...

Controlling coarse pixel size from a stencil buffer

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Method of producing antihypercholesterolemic agents

A method of increasing the production of lovastatin or monacolin J in a lovastatin-producing or non-lovastatin-producing organism is disclosed. In o ne embodiment, the method comprises the steps of transforming an organism with the A. terreus D4B segment, wherein the segment is translated and where an increase in lovastatin production occurs.

Method of producing antihypercholesterolemic agents

A method of increasing the production of lovastatin or monacolin J in a lovastatin-producing or non-lovastatin-producing organism is disclosed. In one embodiment, the method comprises the steps of transforming an organism with the A. terreus D4B segment, wherein the segment is translated and where an increase in lovastatin production occurs.

Method and apparatus for compressing digital image data

A method for compressing digital image data with greyscale values comprises making at least three predictions of the greyscale value of each pixel and comparing the predicted values with the actual value of the pixel. The difference values between the respective predicted values and the actual value of each pixel is computed, and the median difference value of the three difference values is selected for bit coding. Bit coding is carried out by using variable length bit codes, the shortest length bit code being assigned to the most frequently occurring median difference value. The coded values of the median differences are bit packed, and in the case of a pixel where the absolute median difference value exceeds a predetermined value, the actual pixel value is bit packed.

Device for detecting and determining, in situ, spectral properties of an underwater radiation field

Order independent asynchronous compute and streaming for graphics

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

Materials and methods for biosynthetic manufacture and utilization of synthetic polypeptides, and products therefrom

Provided herein are novel, synthetic polypeptides having, for example, acyl-acyl carrier protein (ACP) thioesterase (TE) activity, including polypeptides that convert pimeloyl-ACP to pimelic acid. In some aspects, the synthetic polypeptides have advantageous enzymatic activity and/or improved substrate specificity relative to a wild type acyl-ACP TE.

Materials and methods for controlling regulation in biosynthesis in species of the genera Ralstonia or Cupriavidus and organisms related thereto

Methods for increasing carbon-based chemical product yield in an organism by genetically modifying one or more genes involved in a stringent response and/or in a regulatory network, nonnaturally occurring organisms having increased carbon-based chemical product yield, and methods for use in production of carbon-based chemical products are provided.

Order independent asynchronous compute and streaming for graphics

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

Multistage modulation architecture and method in a radio

In a multiple stage transmitter, and analog signal is modulated and mixed to produce a radio frequency output. A separate mixing frequency signal is provided to each stage. A single frequency synthesizer is used rather than a plurality of frequency synthesizers. In a two-stage system, first and second dividers each receive the output of the frequency synthesizer and deliver a mixing signal to the first and second stages respectively. The modulus of each divider may be selected to minimize spurious signals.

A method and apparatus for compressing digital image data

Processor power management

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

A method and apparatus for compressing digital image data

A method for compressing digital image data with greyscale values comprises making at least three predictions of the greyscale value of each pixel and comparing the predicted values with the actual value of the pixel. The difference values between the respective predicted values and the actual value of each pixel is computed, and the median difference value of the three difference values is selected for bit coding. Bit coding is carried out by using variable length bit codes, the shortest length bit code being assigned to the most frequently occurring median difference value. The coded values of the median differences are bit packed, and in the case of a pixel where the absolute median difference value exceeds a predetermined value, the actual pixel value is bit packed.

Materials and methods utilizing biotin producing mutant hosts for the production of 7-carbon chemicals

Disclosed are methods for regulating biosynthesis of at least one of pimelic acid, 7-aminoheptanoic acid, 7-hydroxyheptanoic acid, heptamethylenediamine, 7-arninoheiptanol and 1,7-heptanediol (C7 building blocks) using a pathway having a pimeloyl-ACP intermediate, the method including the step of downregulating the activity of BioF. Also disclosed are recombinant hosts by fermentation in which the above methods are performed. Further disclosed are recombinant hosts for producing pimeloyl-ACP, the recombinant host including a deletion of a bioF gene.

Multi-resolution image plane rendering within an improved graphics processor microarchitecture

A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.

Renderowanie płaszczyzny obrazu w wielu rozdzielczościach w ulepszonej mikroarchitekturze procesora graficznego

Representación de plano de imagen multirresolución dentro de una microarquitectura de procesador gráfico mejorada

Un sistema informático que comprende: una interfaz de datos (902) que incluye uno o más de un controlador de red, un controlador de memoria o un bus, la interfaz de datos (902) para obtener una imagen de salida (801, 901) que comprende una pluralidad de valores de píxel almacenados dentro de una memoria intermedia de imágenes y uno o más objetos gráficos que hay que representar dentro de dicha imagen de salida (801, 901) asociada con una escena tridimensional (3D); un escáner de imagen de salida para recuperar los contenidos de la memoria intermedia de imágenes y emitir valores de píxel a un dispositivo de visualización (903); y un módulo de representación multiplano para generar la imagen de salida para un dispositivo de visualización de usuario (903), incluyendo el módulo de representación multiplano: un representador (912) recibe una pluralidad de objetos gráficos para generar uno o más planos de imagen (601- 604) de datos de objeto, el representador (912): recibe uno de los objetos gráficos que tienen un valor de ubicación a lo largo de un eje z de la escena 3D; determina en cuál de una pluralidad de planos de imagen (601-604) se ubican los objetos gráficos recibidos usando la ubicación de eje z para el objeto gráfico recibido, cada uno de la pluralidad de planos (601-604) posee una correspondiente resolución de imagen; y representa el objeto gráfico recibido en el plano de imagen determinado (601-604) con la resolución de imagen que corresponde al plano de imagen determinado (601-604); un remuestreador (913) eleva planos de imagen de menor resolución (601-604) a una mayor resolución usada por la imagen de salida (801; 901); y un rasterizador (914) combina valores de píxel de cada ubicación en la pluralidad de planos de imagen (601- 604) después de que cada plano de imagen (601-604) se sobremuestrea a la mayor resolución la imagen de salida (801, 901) que contiene los objetos gráficos.

Multi-resolution image plane rendering within an improved graphics processor microarchitecture

Processor power management

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Processor power management

Dynamic distributed training of machine learning models

Described herein is a graphics processor comprising a memory device and a graphics processing cluster coupled with the memory device. The graphics processing cluster includes a plurality of graphics multiprocessors interconnected via a data interconnect. A graphics multiprocessor includes circuitry configured to load a modular neural network including a plurality of subnetworks, each of the plurality of subnetworks trained to perform a computer vision operation on a separate subject.

Controlling coarse pixel size from a stencil buffer

Controlling coarse pixel size from a stencil buffer

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Augmented reality virtual reality ray tracing sensory enhancement system, apparatus and method

The present disclosure provides a method, an apparatus and at least one non-transitory computer readable storage medium comprising a set of instructions, which when executed, cause a computing device to perform, by a ray tracing engine, path-tracing of a sound from a sound source of an augmented reality, AR, environment or a virtual reality, VR, environment, apply, by the ray tracing engine, one or more filters to the sound from the sound source to form a filtered sound based on: one or more of positional information or directional information, or attributes of objects and surfaces associated with acoustic properties of material of the surfaces within the augmented reality, AR, environment or the virtual reality, VR, environment; and cause, playback of the filtered sound to an observer as an AR sensory enhancement or a VR sensory enhancement.

Augmented reality virtual reality ray tracing sensory enhancement system, apparatus and method

Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

Motion biased foveated renderer

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

Materials and methods for directing carbon flux and increased production of carbon based chemicals

This disclosure relates to genome-scale attenuation or knockout strategies for directing carbon flux to certain carbon based building blocks within the 7-aminoheptanoic acid (7-AHA) and 6-aminohexanoic acid (6-AHA) biosynthesis pathways, for example, to achieve reduced flux to unwanted side products while achieving increased production of desired intermediates and end products. This disclosure also relates to non-naturally occurring mutant bacterial strains comprising one or more gene disruptions in aldehyde reductase and/or aldehyde dehydrogenase genes that are generated to direct carbon flux to certain carbon based building blocks. This disclosure further relates to a method for enhancing production of carbon based building blocks by generating non-naturally occurring mutant bacterial strains, culturing said mutant bacterial strains in the presence of suitable substrates or under desired growth conditions, and substantially purifying the desired end product.

Controlling coarse pixel size from a stencil buffer

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Controlling coarse pixel size from a stencil buffer

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Dynamic distributed training of machine learning models

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

Enhanced processes and reagents for host engineering

Nonnaturally occurring host cells altered to increase their ability to transfer genetic molecules into the host cells as compared to an unaltered host cell are provided. Also provided are methods for identifying endogenous loci of a host cell which inhibit transformation efficiency and/or electroporation of genetic molecules into the cell as well as methods for producing nonnaturally occurring host cells with enhanced transformation efficiency and/or the modified ability to allow for genomic integration of an exogenous DNA sequence via electroporation. Methods for producing biochemicals and products produced with the nonnaturally occurring host cells are also provided.

Augmented reality virtual reality ray tracing sensory enhancement system, apparatus and method

Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

Processor power management

An apparatus is disclosed with one or more processors including a graphics processing unit, the graphics processing unit including a graphics processing pipeline, and a memory to store data, including graphics data processed by the graphics processing pipeline, wherein the graphics processing unit is to conduct a training session with an application, the training session including a plurality of executions of the application utilizing the graphics processing pipeline, wherein the plurality of executions of the application includes executing the application under a plurality of different operating parameters, a plurality of different hardware configurations, or both, collect performance data for the application during the plurality of executions of the application, generate a performance profile for the application as processed in the graphics processing pipeline based on the collected performance data, train a neural network to configure the graphics processing pipeline based on performance profile data from the performance profile for the application, and utilize the trained neural network to configure the graphics processing pipeline to execute an instance of the application. Furthermore, a method and one or more computer-readable media are disclosed.

Methods and materials for producing 7-carbon monomers

This document describes biochemical pathways for producing 7-aminoheptanoic acid using a β-ketoacyl synthase or a β-keioihiolase to form an N-acetyl-5-amino-3- oxopentanoyl-CoA intermediate. 7-aminoheptanoic acid can be enzymatieally converted to pimelic acid, 7-hydroxyheptanoic acid, heptamethylenediamine or 1,7-heptanediol or corresponding salts thereof. This document also describes recombinant microorganisms producing 7-aminoheptanoic acid as well as pimelic acid, 7-hydroxyheptanoic acid, heptamethylenediamine and 1,7-heptanediol or corresponding salts thereof.

Controlling coarse pixel size from a stencil buffer

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Methods and materials for producing 7-carbon monomers

This document describes biochemical pathways for producing 7-aminoheptanoic acid using a β-ketoacyl synthase or a β-ketothiolase to form an N-acetyl-5-amino-3-oxopentanoyl-CoA intermediate. 7-aminoheptanoic acid can be enzymatically converted to pimelic acid, 7-hydroxyheptanoic acid, heptamethylenediamine or 1,7-heptanediol or corresponding salts thereof. This document also describes recombinant microorganisms producing 7-aminoheptanoic acid as well as pimelic acid, 7-hydroxyheptanoic acid, heptamethylenediamine and 1,7-heptanediol or corresponding salts thereof.

Biosynthetic organisms with enhanced carbon utilization

Nonnaturally occurring organisms exhibiting improved carbon utilization and methods for production and use of these nonnaturally occurring organisms in chemical production from carbon containing feedstocks are provided.