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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 237. Отображено 107.
08-11-2016 дата публикации

Techniques for spatially sorting graphics information

Номер: US0009489771B2
Автор: John G. Gierach, Travis T. Schluessler, GIERACH JOHN G, SCHLUESSLER TRAVIS T, Gierach John G., Schluessler Travis T.
Принадлежит: INTEL CORPORATION, INTEL CORP, Intel Corporation

Various embodiments are generally directed to an apparatus, method and other techniques for separating a group of polygons from a viewpoint of a scene into a dependent subgroup of polygons or a non-dependent subgroup of polygon and spatially sorting the non-dependent subgroup of polygons and the dependent group of polygons separately to form a sorted group of polygons.

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Номер записи: 1
07-02-2017 дата публикации

Techniques for power saving on graphics-related workloads

Номер: US0009563253B2
Автор: Selvakumar Panneer, Tion A. Thomas, Travis T. Schluessler, Adam Z. Leibel, PANNEER SELVAKUMAR, THOMAS TION A, SCHLUESSLER TRAVIS T, LEIBEL ADAM Z, Panneer Selvakumar, Thomas Tion A., Schluessler Travis T., Leibel Adam Z.
Принадлежит: INTEL CORPORATION, INTEL CORP, Intel Corporation

Various embodiments are generally directed to an apparatus, method and other techniques for monitoring a task of a graphics processing unit (GPU) by a graphics driver, determining if the task is complete, determining an average task completion time for the task if the task is not complete and enabling a sleep state for a processing circuit for a sleep state time if the average task completion time is greater than the sleep state time.

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Номер записи: 2
21-09-2017 дата публикации

FAST ACCESS AND USE OF COMMON DATA VALUES RELATING TO APPLICATIONS IN PARALLEL COMPUTING ENVIRONMENTS

Номер: US20170269914A1
Автор: Daniel H. Walsh, Travis T. Schluessler, Larry E. Wickstrom, WALSH DANIEL H, SCHLUESSLER TRAVIS T, WICKSTROM LARRY E, Walsh Daniel H., Schluessler Travis T., Wickstrom Larry E.
Принадлежит:

A mechanism is described for facilitating fast access and use of common data values relating to applications in parallel computing environments. A method of embodiments, as described herein, includes detecting a software application being hosted by a computing device, where the software application is further detected as accessing common data values. The method may further include determining whether access to the common data values is slow, and accessing an existing compiled program specific to the common data values at a database, if the access to the common data values is slow. The method may further include loading the existing compiled program to be executed by a processor at the computing device, where the existing compiled program to replace an originally compiled program.

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Номер записи: 3
23-01-2018 дата публикации

Reducing network latency during low power operation

Номер: US0009876720B2
Автор: Steen K. Larsen, Bryan E. Veal, Daniel S. Lake, Travis T. Schluessler, Mazhar I. Memon, LARSEN STEEN K, VEAL BRYAN E, LAKE DANIEL S, SCHLUESSLER TRAVIS T, MEMON MAZHAR I, Larsen Steen K., Veal Bryan E., Lake Daniel S., Schluessler Travis T., Memon Mazhar I.
Принадлежит: Intel Corporation, INTEL CORP

In an embodiment, a method includes identifying a core of a multicore processor to which an incoming packet that is received in a packet buffer is to be directed, and if the core is powered down, transmitting a first message to cause the core to be powered up prior to arrival of the incoming packet at a head of the packet buffer. Other embodiments are described and claimed.

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Номер записи: 4
11-07-2017 дата публикации

Method, apparatus, and system for energy efficiency and energy conservation including power and performance balancing between multiple processing elements and/or a communication bus

Номер: US0009703352B2
Автор: Travis T. Schluessler, Russell J. Fenger, SCHLUESSLER TRAVIS T, FENGER RUSSELL J, Schluessler Travis T., Fenger Russell J.
Принадлежит: Intel Corporation, INTEL CORP

An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

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Номер записи: 5
10-04-2018 дата публикации

Techniques for determining an adjustment for a visual output

Номер: US0009940904B2
Автор: Jacky Romano, Travis T. Schluessler, Guy Zadicario, Stas Gurtovoy, Liran Bachar, ROMANO JACKY, SCHLUESSLER TRAVIS T, ZADICARIO GUY, GURTOVOY STAS, BACHAR LIRAN, Romano Jacky, Schluessler Travis T., Zadicario Guy, Gurtovoy Stas, Bachar Liran
Принадлежит: INTEL CORPORATION, INTEL CORP

Various embodiments are generally directed to an apparatus, method and other techniques for receiving image information for a current frame, determining an amount of change between the current frame and a previous based on the image information for the current frame and image information for a previous frame and determining an adjustment of a frame time based on the amount of change between the current frame and the previous frame.

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Номер записи: 6
05-10-2017 дата публикации

Per-Sample MSAA Rendering Using Comprehension Data

Номер: US20170287209A1
Автор: John G. Gierach, Travis T. Schluessler, GIERACH JOHN G, SCHLUESSLER TRAVIS T, Gierach John G., Schluessler Travis T.
Принадлежит:

By determining if there is redundancy between sub-samples in a multi-sampled anti-aliasing shader, determining which of at least two optimization techniques to use to reduce redundancy and eliminating a redundant shader thread using the selected technique, performance can be improved and power consumption may be reduced when sampling at the sample frequency in multi-sampled anti-aliasing. 1. A method comprising:determining whether a shader is to be run at sample frequency; andif the shader is to be run at sample frequency, determining whether there is a redundancy between two or more sub-samples.2. The method of including:determining if there is redundancy between the sub-samples in a sample frequency shader;determining which of at least two optimization techniques to use to reduce redundancy; andeliminating a redundant shader thread using the selected technique.3. The method of including determining during compilation if there is a redundancy.4. The method of including identifying sub-samples that have non-redundant data and only dispatching threads for samples with non-redundant data.5. The method of including compiling a shader executed at pixel frequency.6. The method of including storing information about whether one or more sub-samples within a pixel have the same color values.7. The method of including if two sub-samples are the same value then storing color information for one sub-sample and only indicating that the other sub-sample has the same information without storing the same information twice.8. The method of including identifying cases where there are redundancies in both the source and destination for blended pixels claim 1 , and using compressed input and output pixel data claim 1 , reducing unnecessary blend work and memory bandwidth claim 1 , and maintaining a maximally compressed state.9. The method of including recompression blended pixels of identical values to save bandwidth.10. One or more non-transitory computer readable media storing ...

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Номер записи: 7
28-09-2017 дата публикации

SYSTEM CHARACTERIZATION AND CONFIGURATION DISTRIBUTION FOR FACILITATING IMPROVED PERFORMANCE AT COMPUTING DEVICES

Номер: US20170279677A1
Автор: Devan Burke, Robert B. Taylor, Travis T. Schluessler, BURKE DEVAN, TAYLOR ROBERT B, SCHLUESSLER TRAVIS T, Burke Devan, Taylor Robert B., Schluessler Travis T.
Принадлежит:

A mechanism is described for facilitating system characterization and configuration distribution for promoting improved performance at computing devices. A method of embodiments, as described herein, includes selecting a computing device from a plurality of computing devices to perform a test relating to a default configuration corresponding to the computing device, where the computing device is selected based on at least one of a workload being initiated at the computing device or overall performance of the computing device. The method may further include evaluating feedback data resulting from the test to decide whether a change is necessitated for the default configuration, and computing a new configuration to replace the default configuration at the computing device, if the change is necessitated for the default configuration. 1. An apparatus comprising:testing logic to select a computing device from a plurality of computing devices to perform a test relating to a default configuration corresponding to the computing device, wherein the computing device is selected based on at least one of a workload being initiated at the computing device or overall performance of the computing device;evaluation logic to evaluate feedback data resulting from the test to decide whether a change is necessitated for the default configuration; andcomputation logic to compute a new configuration to replace the default configuration at the computing device, if the change is necessitated for the default configuration.2. The apparatus of claim 1 , wherein the evaluation logic to allow the default configuration to be maintained unchanged at the computing device claim 1 , if the change is not necessitated for the default configuration.3. The apparatus of claim 1 , further comprising detection/reception logic to detect the computing device in a machine class prior to the selection of the computing device claim 1 , wherein the plurality of computing devices are clustered into a plurality of ...

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Номер записи: 8
20-12-2016 дата публикации

Compression techniques for dynamically-generated graphics resources

Номер: US0009524536B2
Автор: Robert B. Taylor, Travis T. Schluessler, TAYLOR ROBERT B, SCHLUESSLER TRAVIS T, Taylor Robert B., Schluessler Travis T.
Принадлежит: INTEL CORPORATION, INTEL CORP

Compression techniques for dynamically-generated graphics resources are described. In one embodiment, for example, an apparatus may comprise logic, at least a portion of which is in hardware, the logic to determine one or more usage characteristics of a dynamically-generated graphics resource, determine whether to compress the dynamically-generated graphics resource based on the one or more usage characteristics, and in response to a determination to compress the dynamically-generated graphics resource, select a compression procedure based on a graphics quality threshold for the dynamically-generated graphics resource. Other embodiments are described and claimed.

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Номер записи: 9
28-03-2017 дата публикации

System and method for high performance secure access to a trusted platform module on a hardware virtualization platform

Номер: US0009608821B2
Автор: Ravi L. Sahita, Travis T. Schluessler, SAHITA RAVI L, SCHLUESSLER TRAVIS T, Sahita Ravi L., Schluessler Travis T.
Принадлежит: Intel Corporation, INTEL CORP

A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. The virtualization platform including Virtual Machine Monitor (VMM) managed components coupled to the VMM. One of the VMM managed components is a TPM (Trusted Platform Module). The virtualization platform also includes a plurality of Virtual Machines (VMs). Each of the virtual machines includes a guest Operating System (OS), a TPM device driver (TDD), and at least one security application. The VMM creates an intra-partition in memory for each TDD such that other code and information at a same or higher privilege level in the VM cannot access the memory contents of the TDD. The VMM also maps access only from the TDD to a TPM register space specifically designated for the VM requesting access. Contents of the TPM requested by the TDD are stored in an exclusively VMM-managed protected page table that provides hardware-based memory isolation for the TDD.

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Номер записи: 10
26-04-2012 дата публикации

PROVIDING PROTECTED ACCESS TO CRITICAL MEMORY REGIONS

Номер: US20120102285A1
Автор: Durham David, Khosravi Hormuzd, Nagabhushan Gayathri, Sahita Ravi, Savagaonkar Uday, Schluessler Travis T.
Принадлежит:

In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing hardware of a virtualized processor based system detecting a specified type of memory access to an identified region of memory and in response to the detecting generating an interrupt for a virtual machine monitor (VMM) of the virtualized processor based system. 110-. (canceled)11. In a smart mobile phone device having a memory and a processor therein , a method comprising:executing a virtual machine monitor to service one or more virtual machines, wherein the virtual machine monitor operates in a first part of the memory that is not accessible to any of the one or more virtual machines that are serviced by the virtual machine monitor;loading a protected program for one of the virtual machines into a second part of the memory; and (a) specifying in one or more registers of the processor, the range of memory locations or regions to be protected, and', '(b) selectively blocking a memory access attempt to the range of memory locations or regions to be protected based on an access type for the memory access attempt and based further on the memory access attempt having a location within the range of memory locations or regions to be protected., 'protecting the protected program based on a range of memory locations or regions occupied by the protected program, wherein protecting the protected program comprises12. The method of claim 11 , wherein specifying in the one or more registers of the processor claim 11 , the range of memory locations or regions to be protected comprises:configuring Memory Type Range Registers (MTRRs) or Memory Protection Range Registers (MPRRs) of the processor.13. The method of claim 11 , wherein specifying in the one or more registers of the processor claim 11 , the range of memory locations or regions to be protected comprises:specifying the range of memory locations or regions to be protected and an access mode for each memory range ...

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Номер записи: 11
20-12-2012 дата публикации

METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING POWER AND PERFORMANCE BALANCING BETWEEN MULTIPLE PROCESSING ELEMENTS

Номер: US20120324248A1
Автор: Fenger Russell J., Schluessler Travis T.
Принадлежит:

An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit. 1. An apparatus for efficient energy consumption comprising: an integrated circuit including ,a first core and a second core, the first and second cores being asymmetric cores;a workload monitor adapted to dynamically determine a first workload for the first core and a second workload for the second core; anda balancing module adapted to dynamically tune frequency allocation between the first core and the second core based on a power limit for the integrated circuit and at least the second workload.2. The apparatus of claim 1 , wherein the first core includes a host processing core and the second core includes a graphics processing core.3. The apparatus of claim 1 , wherein a workload monitor adapted to dynamically determine a first workload for the first core and a second workload for the second core includes first hardware to track a first number of cycles the first core is active during a period of time and second hardware to track a second number of cycles the second core is active during the period of time.4. The apparatus of claim 1 , wherein a workload monitor adapted to dynamically determine a first workload for the first core and a second workload for the second core includes a microcontroller configured to execute code held on a non- ...

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Номер записи: 12
20-06-2013 дата публикации

Method, Apparatus, and System for Energy Efficiency and Energy Conservation Including Power and Performance Balancing Between Multiple Processing Elements and/or a Communication Bus

Номер: US20130159741A1
Автор: Fenger Russell J., Schluessler Travis T.
Принадлежит:

An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit. 1. An apparatus for efficient energy consumption comprising: an integrated circuit including ,a first core;a communication bus coupled to the first core;a core workload monitor configured to determine a core workload for the first core;a bus workload monitor configured to determine a bus workload for the communication bus; andbalancing control adapted to dynamically tune power allocation between the first core and the communication bus based on a power limit for the integrated circuit and at least the bus workload.2. The apparatus of claim 1 , further comprising a second core and a second core workload monitor configured to determine a second core workload for the second core claim 1 , wherein the first core includes a host processing core claim 1 , the second core includes a graphics processing core claim 1 , and the communication bus includes a ring interconnect claim 1 , and wherein the balancing control is further adapted to dynamically tune power allocation between the first core claim 1 , the second core claim 1 , and the communication bus based on a power limit for the integrated circuit and at least the bus workload claim 1 , the core workload claim 1 , and the second core workload.3. The apparatus of claim 1 , wherein a core workload ...

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Номер записи: 13
06-02-2014 дата публикации

SINGLE INSTRUCTION PROCESSING OF NETWORK PACKETS

Номер: US20140036909A1
Автор: Schluessler Travis T., Veal Bryan E.
Принадлежит:

Executing a single instruction/multiple data (SIMD) instruction of a program to process a vector of data wherein each element of the packet vector corresponds to a different received packet. 1. A method comprising:executing a single instruction/multiple data (SIMD) instruction of a program to process a vector of data wherein each element of the packet vector corresponds to a different received packet.2. The method of claim 1 ,wherein each element of the vector corresponds to a same strict subset of packet header fields.3. The method of claim 1 , further comprising:accessing a second vector, wherein each element of the second vector identifies occupancy of a corresponding element in the packet vector;accessing a third vector, wherein each element of the third vector comprises flow state data for a flow of an associated packet in the packet vector;modifying elements in the third vector.4. The method of claim 3 , further comprising:determining a packet should not be processed by the SIMD instructions.5. The method of claim 1 , wherein the SIMD instruction comprises at least a portion of the program to perform at least one of the following:determine protocols of the packets;validate the packets;compute header values for the packets; anddetermine an execution unit to handle the packets.6. A method comprising:receiving packets transmitted over a communications medium;arranging data of the packets into a vector, wherein each element of the vector corresponds to a different packet, for single instruction/multiple data (SIMD) processing of the vector.7. The method of claim 6 ,wherein the arranging data of the packets into a vector comprises arranging data of the packets into a vector where each element of the vector corresponds to a same strict subset of packet header fields.8. The method ofwherein the arranging comprises performing a Direct Memory Access of the strict subset of packet header fields data from a contiguously stored packet header.9. The method of claim 6 , ...

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Номер записи: 14
20-03-2014 дата публикации

Distributing Power To Heterogeneous Compute Elements Of A Processor

Номер: US20140082378A1
Автор: Romano Yaakov, Schluessler Travis T., Wells Ryan D.
Принадлежит:

In one embodiment, the present invention includes a processor having a first domain with a first compute engine and a second domain with a second compute engine, where each of these domains can operate at an independent voltage and frequency. A first logic may be present to update a power bias value used to control dynamic allocation of power between the first and second domains based at least in part on a busyness of the second domain. In turn, a second logic may dynamically allocate at least a portion of a power budget for the processor between the domains based at least in part on this power bias value. Other embodiments are described and claimed. 1. A processor comprising:a first domain having a first compute engine;a second domain having a second compute engine, the first and second compute engines asymmetrical, each of the first and second domains to operate at an independent voltage and frequency;a first logic to update a power bias value used to control dynamic allocation of power between the first and second domains based at least in part on a busyness of the second domain; anda second logic to dynamically allocate at least a portion of a power budget for the multi-domain processor between the first and second domains based at least in part on the power bias value.2. The processor of claim 1 , wherein the second domain is a consumer domain and the first domain is a producer domain claim 1 , the first compute engine is a core and the second compute engine is a graphics engine.3. The processor of claim 1 , wherein the first logic includes a first domain counter and a second domain counter claim 1 , wherein the first logic is to update one of the first and second domain counters based on whether a frequency of the first domain is substantially around a target frequency for the first domain.4. The processor of claim 3 , wherein the first logic is to determine the target frequency based on the busyness of the second domain.5. The processor of claim 4 , wherein ...

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Номер записи: 15
20-03-2014 дата публикации

Distributing Power To Heterogeneous Compute Elements Of A Processor

Номер: US20140082380A1
Автор: Romano Yaakov, Schluessler Travis T., Wells Ryan D.
Принадлежит:

In one embodiment, the present invention includes a processor having a first domain with a first compute engine and a second domain with a second compute engine, where each of these domains can operate at an independent voltage and frequency. A first logic may be present to update a power bias value used to control dynamic allocation of power between the first and second domains based at least in part on a busyness of the second domain. In turn, a second logic may dynamically allocate at least a portion of a power budget for the processor between the domains based at least in part on this power bias value. Other embodiments are described and claimed. 1. A processor comprising:a first domain having a first compute engine;a second domain having a second compute engine, the first and second compute engines asymmetrical, each of the first and second domains to operate at an independent voltage and frequency;a power bias logic to update a power bias value used to control dynamic allocation of power between the first and second domains based at least in part on a busyness of the second domain; anda power controller to dynamically allocate at least a portion of a power budget for the processor between the first and second domains based at least in part on the power bias value.2. The processor of claim 1 , wherein the second domain is a consumer domain and the first domain is a producer domain claim 1 , the first compute engine is a core claim 1 , the core including a decode unit to decode instructions claim 1 , at least one execution unit to execute decoded instructions claim 1 , and a retirement unit to retire executed instructions; andthe second compute engine is a graphics engine.3. The processor of claim 1 , wherein the power bias logic includes a first domain counter and a second domain counter claim 1 , wherein the power bias logic is to update one of the first and second domain counters based on whether a frequency of the first domain is substantially around a ...

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Номер записи: 16
27-03-2014 дата публикации

TECHNIQUES FOR DYNAMIC PHYSICAL MEMORY PARTITIONING

Номер: US20140089626A1
Автор: Schluessler Travis T., TAYLOR ROBERT B.
Принадлежит:

Various embodiments are presented herein that reallocate partitions of a shared physical memory between processing units. An apparatus and a computer-implemented method may determine an amount of memory space in the physical memory allocated to a first processing unit during system initialization. The determined amount of the memory space may be consolidated. The consolidated memory space may be allocated to the second processing unit during runtime. Other embodiments are described and claimed. 1. A computer-implemented method , comprising:determining an amount of a memory space in a physical memory allocated to a first processing unit during system initialization;consolidating the determined amount of the memory space; andreallocating the consolidated memory space to a second processing unit during runtime.2. The computer-implemented method of claim 1 , comprising:receiving a request to allocate memory space to the second processing unit.3. The computer-implemented method of claim 1 , comprising:determining whether the physical memory includes unallocated memory space.4. The computer-implemented method of claim 1 , comprising:determining whether the first processing unit includes available memory space.5. The computer-implemented method of claim 1 , comprising:determining whether the memory space allocated to the first processing unit exceeds a threshold.6. The computer-implemented method of claim 1 , comprising:remapping physical pages from the determined amount of the memory space.7. The computer-implemented method of claim 1 , comprising:copying memory resources into a non-volatile long term storage to make available memory space within the first processing unit.8. The computer-implemented method of claim 1 , comprising:copying memory resources within the determined amount of the memory space into available memory space allocated to the first processing unit.9. The computer-implemented method of claim 1 , comprising:receiving a request to reallocate the physical ...

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Номер записи: 17
14-01-2021 дата публикации

GRAPHICS MEMORY EXTENDED WITH NONVOLATILE MEMORY

Номер: US20210011853A1
Автор: Appu Abhishek R., Ferreira Cristiano J., Gandiga Shivakumar Deepak, Guttridge Brandt M., KENNEDY Jonathan, Koker Altug, Nandyal Lakshman Ajit Krisshna, Pallister Kim, Qiu Bo, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., Soqui Frank J., Srivatsa Anand, TALPALLIKAR Nikhil, Zhu Jianfang
Принадлежит:

An embodiment of an electronic processing system may include an application processor, system memory communicatively coupled to the application processor, a graphics processor communicatively coupled to the application processor, graphics memory communicatively coupled to the graphics processor, and persistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media. The persistent storage media may include a low latency, high capacity, and byte-addressable nonvolatile memory. The one or more graphics assets may include one or more of a mega-texture and terrain data. Other embodiments are disclosed and claimed. 1. (canceled)2. A computing system comprising:a persistent storage media;a graphics processor;a central processing unit; anda memory including a set of instructions, which when executed by one or more of the graphics processor or the central processing unit, cause the computing system to:partition the persistent storage media into a first portion accessible by the graphics processor, and a second portion accessible by the central processing unit; andmap assets in the first portion for access by the graphics processor.3. The system of claim 2 , wherein the persistent storage media comprises a low latency claim 2 , high capacity claim 2 , and byte-addressable nonvolatile memory.4. The system of claim 2 , wherein the assets include one or more of a mega-texture or terrain data.5. The system of claim 2 , wherein graphics processor is to directly access the first portion.6. The system of claim 5 , wherein the graphics processor is to directly access the first portion so as to one or more of bypass a storage device driver stack associated with the persistent storage media or a file system stack.7. The system of claim 2 , wherein the instructions claim 2 , when executed claim 2 ...

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Номер записи: 18
15-01-2015 дата публикации

Techniques for spatially sorting graphics information

Номер: US20150015575A1
Автор: John G. Gierach, Travis T. Schluessler
Принадлежит: Intel Corp

Various embodiments are generally directed to an apparatus, method and other techniques for separating a group of polygons from a viewpoint of a scene into a dependent subgroup of polygons or a non-dependent subgroup of polygon and spatially sorting the non-dependent subgroup of polygons and the dependent group of polygons separately to form a sorted group of polygons.

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Номер записи: 19
11-01-2018 дата публикации

REDUCING NETWORK LATENCY DURING LOW POWER OPERATION

Номер: US20180013676A1
Автор: Lake Daniel S., Larsen Steen K., Memon Mazhar I., Schluessler Travis T., Veal Bryan E.
Принадлежит:

In an embodiment, a method includes identifying a core of a multicore processor to which an incoming packet that is received in a packet buffer is to be directed, and if the core is powered down, transmitting a first message to cause the core to be powered up prior to arrival of the incoming packet at a head of the packet buffer. Other embodiments are described and claimed. 1. A system comprising:a processor including a plurality of first cores and a plurality of second, lower power cores; and perform a look-up in a table for task requests from at least one buffer for the plurality of first cores and the plurality of second, lower power cores, wherein the table comprises data indicating which of the plurality of first cores and which of the plurality of second, lower power cores are to be in an active power state based on task requests from the at least one buffer, and', 'cause each of the plurality of first cores and the plurality of second, lower power cores to be in a respective power state indicated by the data from the look-up in the table., 'a non-transitory machine-accessible storage medium including instructions that when executed cause the system to2. The system of claim 1 , wherein the non-transitory machine-accessible storage medium includes instructions that when executed cause the system to utilize the plurality of second claim 1 , lower power cores to handle processing tasks at reduced power consumption.3. The system of claim 1 , wherein the table includes data indicating which of the plurality of first cores and which of the plurality of second claim 1 , lower power cores are to be in an active power state based on at least eight task requests from the at least one buffer.4. The system of claim 1 , wherein the non-transitory machine-accessible storage medium includes instructions that when executed cause the system to cause each of the plurality of first cores and the plurality of second claim 1 , lower power cores to be in a respective power state ...

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Номер записи: 20
14-01-2021 дата публикации

SYNERGISTIC TEMPORAL ANTI-ALIASING AND COARSE PIXEL SHADING TECHNOLOGY

Номер: US20210014450A1
Автор: Apodaca Michael, Feit John H., Kaburlasos Nikos, Kwiatkowski Jacek, Ramadoss Murali, Ray Joydeep, Schluessler Travis T., Surti Prasoonkumar, Vaidyanathan Karthik, Venkatesh Abhishek
Принадлежит:

Systems, apparatuses and methods may provide for technology that determines a frame rate of video content, sets a blend amount parameter based on the frame rate, and temporally anti-aliases the video content based on the blend amount parameter. Additionally, the technology may detect a coarse pixel (CP) shading condition with respect to one or more frames in the video content and select, in response to the CP shading condition, a per frame jitter pattern that jitters across pixels, wherein the video content is temporally anti-aliased based on the per frame jitter pattern. The CP shading condition may also cause the technology to apply a gradient to a plurality of color planes on a per color plane basis and discard pixel level samples associated with a CP if all mip data corresponding to the CP is transparent or shadowed out. 1. (canceled)2. A computing system comprising:a processor; and detect a coarse pixel shading condition with respect to one or more frames in video content;', 'detect if all mip data corresponding to the course pixel is shadowed out;', 'if all the mip data corresponding to the course pixel is not shadowed out, detect if all the mip data corresponding to the course pixel is transparent; and', 'discard one or more pixel level samples associated with a coarse pixel if all mip data corresponding to the coarse pixel is transparent or shadowed out., 'memory coupled to the processor, the memory including instructions which, when executed by the processor, cause the computing system to3. The system of claim 2 , wherein the instructions claim 2 , when executed claim 2 , further cause the computing system to process the one or more pixel level samples if all mip data corresponding to the coarse pixel is not transparent or shadowed out.4. The system of claim 2 , wherein the instructions claim 2 , when executed claim 2 , further cause the computing system to:in response to the coarse pixel shading condition, define at least a plurality of color planes for ...

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Номер записи: 21
18-01-2018 дата публикации

SYSTEM AND METHOD FOR HIGH PERFORMANCE SECURE ACCESS TO A TRUSTED PLATFORM MODULE ON A HARDWARE VIRTUALIZATION PLATFORM

Номер: US20180019875A1
Автор: Sahita Ravi L., Schluessler Travis T.
Принадлежит:

A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. The virtualization platform including Virtual Machine Monitor (VMM) managed components coupled to the VMM. One of the VMM managed components is a TPM (Trusted Platform Module). The virtualization platform also includes a plurality of Virtual Machines (VMs). Each of the virtual machines includes a guest Operating System (OS), a TPM device driver (TDD), and at least one security application. The VMM creates an intra-partition in memory for each TDD such that other code and information at a same or higher privilege level in the VM cannot access the memory contents of the TDD. The VMM also maps access only from the TDD to a TPM register space specifically designated for the VM requesting access. Contents of the TPM requested by the TDD are stored in an exclusively VMM-managed protected page table that provides hardware-based memory isolation for the TDD. 1Virtual Machine Monitor (VMM) managed components coupled to a VMM, wherein one of the VMM managed components comprises a Trusted Platform Module (TPM); anda plurality of Virtual Machines (VMs), each of the virtual machines including a guest operating system (OS), a TPM device driver (TDD), and at least one security application,wherein the VMM to create an intra-partition in memory for the TDD such that other code and information at a same or higher privilege level within the VM cannot access the memory contents of the TDD and to map accesses from only the TDD to a TPM register space specifically designated for the VM requesting access.. A virtual platform comprising: This application is a continuation of U.S. application Ser. No. 14/510,534, entitled “System and Method for High Performance Secure Access to a Trusted Platform Module on a Hardware Virtualization Platform,” which was filed on Oct. 9, 2014, and which is a divisional application of U.S. application Ser. No. 13/305,902, entitled “System ...

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Номер записи: 22
22-01-2015 дата публикации

SYSTEM AND METHOD FOR HIGH PERFORMANCE SECURE ACCESS TO A TRUSTED PLATFORM MODULE ON A HARDWARE VIRTUALIZATION PLATFORM

Номер: US20150026426A1
Автор: Sahita Ravi L., Schluessler Travis T.
Принадлежит:

A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. The virtualization platform including Virtual Machine Monitor (VMM) managed components coupled to the VMM. One of the VMM managed components is a TPM (Trusted Platform Module). The virtualization platform also includes a plurality of Virtual Machines (VMs). Each of the virtual machines includes a guest Operating System (OS), a TPM device driver (TDD), and at least one security application. The VMM creates an intra-partition in memory for each TDD such that other code and information at a same or higher privilege level in the VM cannot access the memory contents of the TDD. The VMM also maps access only from the TDD to a TPM register space specifically designated for the VM requesting access. Contents of the TPM requested by the TDD are stored in an exclusively VMM-managed protected page table that provides hardware-based memory isolation for the TDD. 120-. (canceled)21. One or more machine-readable storage media comprising a plurality of instructions stored thereon that , in response to execution by a computing device , cause the computing device to:issue a call, by a requesting entity of the computing device, for a hardware cryptographic device to perform an operation;determine whether the call is an initial request by the requesting entity to the hardware cryptographic device;verify authentication information provided with a first access associated with the initial request in response to a determination that the call is not the initial request;enable access to a subset of hardware registers of the hardware cryptographic device based on an identification of a virtual machine of the requesting entity;perform, by the hardware cryptographic device, the requested operation; andstore, by the hardware cryptographic device, results of the performed operation in a protected page table accessible from outside the hardware cryptographic device by only ...

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Номер записи: 23
28-01-2016 дата публикации

Compression techniques for dynamically-generated graphics resources

Номер: US20160027145A1
Автор: Robert B. Taylor, Travis T. Schluessler
Принадлежит: Intel Corp

Compression techniques for dynamically-generated graphics resources are described. In one embodiment, for example, an apparatus may comprise logic, at least a portion of which is in hardware, the logic to determine one or more usage characteristics of a dynamically-generated graphics resource, determine whether to compress the dynamically-generated graphics resource based on the one or more usage characteristics, and in response to a determination to compress the dynamically-generated graphics resource, select a compression procedure based on a graphics quality threshold for the dynamically-generated graphics resource. Other embodiments are described and claimed.

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Номер записи: 24
23-01-2020 дата публикации

HIERARCHICAL GENERAL REGISTER FILE (GRF) FOR EXECUTION BLOCK

Номер: US20200026514A1
Автор: Appu Abhishek R., Hoekstra Eric J., HURD LINDA L., Koker Altug, Lueh Guei-yuan, Maiyuran Subramaniam, Pal Supratim, Puffer David, Ray Joydeep, Schluessler Travis T., Sinha Kamal, Surti Prasoonkumar, Veernapu Kiran C.
Принадлежит: Intel Corporation

In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed. 1. (canceled)2. A general purpose graphics processor , comprising:a general-purpose graphics processing compute block comprising a plurality of processing resources to execute compute instructions, wherein each of the plurality of processing resources comprises a local general register file (GRF) which operates at a first speed;a shared general register file (GRF) communicatively coupled to the plurality of processing resources, wherein the shared GRF operates at a second speed, slower than the first speed.3. The general purpose graphics processor of claim 2 , wherein each of the plurality of processing resources is to retrieve data from the shared GRF when the data is unavailable in the local GRF.4. The general purpose graphics processor of claim 2 , wherein:the local GRF operates at a first power level; andthe shared GRF operates at a second power level, lower than the first power level.5. The general purpose graphics processor of claim 2 , wherein:the local GRF and the shared GRF are separate memory structures.6. The general purpose graphics processor of claim 2 , wherein:the local GRF and the shared GRF are embodied in a single memory structure.7. The general purpose graphics processor of claim 2 , wherein:the shared GRF comprises a virtualized address space.8. The general purpose graphics processor of claim 2 , wherein:each of the plurality of processing resources is to detect a data context switch between two or more of the plurality of processing resources, and in response to the data context switch, to redirect a data inquiry from the local GRF to a remote memory device9. The general purpose graphics processor of claim 2 , further comprising:a shared cache memory ...

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Номер записи: 25
28-01-2021 дата публикации

THREAD SERIALIZATION, DISTRIBUTED PARALLEL PROGRAMMING, AND RUNTIME EXTENSIONS OF PARALLEL COMPUTING PLATFORM

Номер: US20210027416A1
Автор: AMSTUTZ Jefferson, Appu Abhishek R., GUENTHER Johannes, Koker Altug, Kwiatkowski Jacek, Liktor Gabor, Ould-Ahmed-Vall Elmoustapha, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., WALD INGO
Принадлежит:

Systems, apparatuses, and methods may provide for technology to process graphical data, and to modify a runtime environment in a parallel computing platform for a graphic environment. 1. (canceled)2. A semiconductor package apparatus , comprising:a substrate; and detect, in a runtime environment, a graphic application for use in a parallel computing platform; and', 'modify, during runtime and in response to detecting the graphic application, the source code in connection with the parallel computing platform by adding at least one source code extension., 'logic coupled to the substrate, wherein the logic is at least partially implemented in one or more of configurable logic or fixed-functionality hardware logic, the logic to3. The semiconductor package apparatus of claim 2 , wherein detecting the graphic application comprises detecting active execution lanes of the graphic application.4. The semiconductor package apparatus of claim 3 , wherein:detecting active execution lanes comprises applying a predetermine value;for each loop iteration, execution lanes whose value matches the predetermine value are active; andfor each loop iteration, execution lanes whose value does not match the predetermine value are inactive.5. The semiconductor package apparatus of claim 4 , wherein the at least one source code extension is to execute a loop body once for each predetermined value that different threads in a warp hold in that variable.6. The semiconductor package apparatus of claim 4 , wherein modifying the source code comprises executing a loop body once for each detected active execution lane.7. A graphics processing system claim 4 , comprising:a memory; and detect, in a runtime environment, a graphic application for use in a parallel computing platform; and', 'modify, during runtime and in response to detecting the graphic application, the source code in connection with the parallel computing platform by adding at least one source code extension., 'a semiconductor package ...

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Номер записи: 26
24-04-2014 дата публикации

Mechanism for Detecting Human Presence Using Authenticated Input Activity Timestamps

Номер: US20140115662A1
Автор: CHHABRA Jasmeet, Goglin Stephen D., Johnson Erik J., Orrin Steve, Schluessler Travis T.
Принадлежит:

When a service request associated with an initiated online service transaction is received, an attestation identifying a human-input activity is requested. Upon receiving a signature attesting the human-input activity, the previously initiated service transaction is authenticated based at least in part on the signature. 120-. (canceled)21. At least one computer-readable medium comprising instructions that when executed on a processor configure the processor to:receive one or more user input events having one or more associated timestamps; anddetermine that a human generated the one or more user input events, wherein the determination is based at least in part on the one or more timestamps.22. The at least one computer-readable medium of claim 21 , wherein the one or more user input events comprises a keyboard input claim 21 , a mouse click claim 21 , or a mouse movement.23. The at least one computer-readable medium of claim 21 , wherein the one or more user input events comprises a key press claim 21 , a key release claim 21 , a mouse button press claim 21 , or a mouse button release.24. The at least one computer-readable medium of claim 21 , whereina first user input event is associated with initiation of a service request, the first user input event being associated with a first timestamp;a second user input event comprises a keyboard input, a mouse click, or a mouse movement, the second user input event being associated with a second timestamp; andwherein the instructions further configure the processor to:temporally correlate a difference between the first timestamp and the second timestamp to a threshold.25. The at least one computer-readable medium of claim 24 , whereinthe initiation of the service request comprises a request to generate a form to receive user input.26. An apparatus comprising:a processor; and receive one or more user input events having one or more associated timestamps; and', 'determine that a human generated the one or more user input ...

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Номер записи: 27
17-02-2022 дата публикации

ADJUSTING GRAPHICS RENDERING BASED ON FACIAL EXPRESSION

Номер: US20220050520A1
Автор: AMSTUTZ Jefferson, Appu Abhishek R., BROWNLEE Carson, Feit John H., Kaburlasos Nikos, Kwiatkowski Jacek, Lahiri Sayan, Mastronarde Josh B., Ould-Ahmed-Vall Elmoustapha, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., Tiwari Vivek, Vembar Deepak S., Vembu Balaji, Xiao Kai
Принадлежит: Intel Corporation

An embodiment of a graphics apparatus may include a facial expression detector to detect a facial expression of a user, and a parameter adjuster communicatively coupled to the facial expression detector to adjust a graphics parameter based on the detected facial expression of the user. The detected facial expression may include one or more of a squinting, blinking, winking, and facial muscle tension of the user. The graphics parameter may include one or more of a frame resolution, a screen contrast, a screen brightness, and a shading rate. Other embodiments are disclosed and claimed. 1. (canceled)2. A computing system comprising:a graphics processor;a central processing unit; anda memory including a set of instructions, which when executed by one or more of the graphics processor or the central processing unit, cause the computing system to:detect a first facial expression of a user;detect a secondary input from the user that is associated with the first facial expression; andtrigger an associated action based on the first facial expression and the secondary input.3. The system of claim 2 , wherein the associated action is one or more of a zoom or a pan.4. The system of claim 2 , wherein the secondary input from the user is one or more of a pulse of the user claim 2 , a heart rate of the user or a gesture of the user.5. The system of claim 2 , wherein the secondary input is a second facial expression of the user that is different from the first facial expression.6. The system of claim 2 , wherein the instructions claim 2 , when executed claim 2 , cause the computing system to:detect a focal point associated with the user;detect a focus area based on the focal point; andadjust the associated action based on the focus area.7. The system of claim 6 , wherein the instructions claim 6 , when executed claim 6 , cause the computing system to:determine a depth of focus of the user during a calibration process;determine a focus distance of the user that is associated with ...

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Номер записи: 28
30-01-2020 дата публикации

COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS

Номер: US20200034946A1
Автор: Akhbari Farshad, Appu Abhishek R., Ashbaugh Ben J., BAGHSORKHI Sara S., Barik Rajkishore, Boles Jeffery S., Burke Devan, Chen Feng, Feit John H., Fu Wenyin, Galoppo von Borries Nicolas C., Gottschlich Justin E., HURD LINDA L., Kim Dukhwan, Koker Altug, Lake Adam T., Lin Tsung-Han, Maiyuran Subramaniam, Mastronarde Josh B., Nurvitadhi Eriko, Ray Joydeep, Satish Nadathur Rajagopalan, Schluessler Travis T., Sinha Kamal, Srinivasa Narayan, Surti Prasoonkumar, Vaidyanathan Karthik, Vembu Balaji
Принадлежит: Intel Corporation

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels. 119-. (canceled)20. An apparatus , comprising: one or more processing units to process data, including the one or more processing units to run a first shader application,', 'a scheduler to schedule shader threads for processing, and', 'a programmable integrated circuit (IC) device,, 'one or more processors including a graphics processor, the one or more processors includingwherein, upon the programmable IC device being configured to operate as a second shader application, each of one or more shader threads is to be processed at either the first shader application or the second shader application based on one or more requirements for each shader thread.21. The apparatus of claim 20 , wherein the one or more requirements include a speed of operation for a shader thread.22. The apparatus of claim 21 , wherein a first shader thread requiring a first speed of operation is to be processed at the first shader application and a second shader thread requiring a second speed of operation claim 21 , the first speed of operation being greater than the second speed of operation claim 21 , is to be processed at the second shader application.23. The apparatus of claim 20 , wherein the first shader application and the second shader application are different versions of a same shader.24. The apparatus of claim 20 , wherein the programmable IC device is a field-programmable gate array (FPGA).25. The apparatus of claim 20 , wherein the scheduler is to determine whether a shader thread is to be processed by the first shader application or the second shader application.26. The apparatus of claim 20 , wherein the programmable IC device is triggered to perform as a shader stage in ...

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Номер записи: 29
04-02-2021 дата публикации

INTERCONNECT FABRIC LINK WIDTH REDUCTION TO REDUCE INSTANTANEOUS POWER CONSUMPTION

Номер: US20210034135A1
Автор: Appu Abhishek R., KENNEDY Jonathan, Koker Altug, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., Tameem Mohammed, Veernapu Kiran C.
Принадлежит: Intel Corporation

Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on the instantaneous throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on throughput demand from the client. 1. A parallel processor comprising:a first processing cluster including a first interface node, the first interface node having dynamically configurable ingress and egress bus widths; andan interconnect fabric coupled with the first interface node of the first processing cluster, the interconnect fabric including a dynamic bus module to dynamically configure active bus widths for connections to the first interface node, wherein the dynamic bus module is to dynamically configure a first active bus width for an ingress connection to the first interface node based on a first rate of data transfer requests through the first interface node and dynamically configure a second active bus width for an egress connection to the first interface node based on a second rate of data transfer requests through the first interface node, the first active bus width different from the second active bus width.2. The parallel processor as in claim 1 , the dynamic bus module to configure a bus frequency for the first interface node based on the first rate of data transfer requests or the second rate of data transfer requests.3. The parallel processor as in claim 1 , additionally comprising a second processing cluster including a second interface node claim 1 , the second interface node having a second ingress module and a second egress module claim 1 , wherein the dynamic bus module is to dynamically configure a third active bus width for an ingress connection to the second interface node based on a third rate of data ...

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Номер записи: 30
04-02-2021 дата публикации

Frequent Data Value Compression for Graphics Processing Units

Номер: US20210035257A1
Автор: Anantaraman Aravindh V., Appu Abhishek R., Borole Bhushan M., Fu Wenyin, Hoekstra Eric J., HURD LINDA L., K. Pattabhiraman P., Koker Altug, Ranganathan Vasanth, Ray Joydeep, Schluessler Travis T., Sharma Saurabh, Sinha Kamal, Surti Prasoonkumar, Venkatesh Abhishek
Принадлежит:

A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline. 1. (canceled)2. A graphics processor comprising:a plurality of execution units; and when the data are all zeros, the write back unit is to write a first encoding to a control surface in the memory; and', 'when the data are all ones, the write back unit is to write a second encoding to the control surface in the memory., 'a write back unit coupled to the plurality of execution units, the write back unit to receive data from a first execution unit of the plurality of execution units and perform a write to a memory, wherein3. The graphics processor of claim 2 , wherein when the data is not the all zeros or the all ones claim 2 , the write back unit is to write at least some of the data to another surface in the memory.4. The graphics processor of claim 2 , wherein the write back unit is to receive a cacheline comprising the data.5. The graphics processor of claim 4 , wherein the data of the cacheline comprises one or more pixels.6. The graphics processor of claim 4 , wherein the write back unit is to receive the cacheline comprising a victimized cacheline.7. The graphics processor of claim 2 , further comprising a read unit coupled to the plurality of execution units.8. The graphics processor of claim 7 , wherein in response to a read request claim 7 , the read unit is to read information from the control surface in the memory.9. The graphics processor of claim 8 , wherein when the information from the control surface in the memory is a first value claim 8 , the read unit is to read stored data from the memory.10. The graphics processor of claim 9 , wherein when the information from the ...

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Номер записи: 31
12-02-2015 дата публикации

TECHNIQUES TO AUTOMATICALLY ADJUST 3D GRAPHICS APPLICATION SETTINGS

Номер: US20150042641A1
Автор: INSKO BRENT E., Schluessler Travis T.
Принадлежит:

Techniques for automatically adjusting three-dimensional (3D) graphics application settings are described. In one embodiment, for example, an apparatus may comprise a processor circuit to execute a 3D graphics application based on one or more feature control settings and a 3D graphics management module to determine a performance metric during execution of the 3D graphics application, compare the performance metric to a performance threshold, and when the performance metric is less than the performance threshold, determine a set of one or more setting adjustments based on feature control information to increase a performance of the 3D graphics application. Other embodiments are described and claimed. 1. At least one machine-readable medium storing a set of instructions that , in response to being executed on a computing device , cause the computing device to:execute a three-dimensional (3D) graphics application based on one or more feature control settings;determine a performance metric during execution of the 3D graphics application;compare the performance metric to a performance threshold; andwhen the performance metric is less than the performance threshold, determine a set of one or more setting adjustments based on feature control information to increase a performance of the 3D graphics application.2. The at least one machine-readable medium of claim 1 , storing instructions that claim 1 , in response to being executed on the computing device claim 1 , cause the computing device to:compare the performance metric to a second performance threshold; andwhen the performance metric is greater than the second performance threshold, determine a second set of one or more setting adjustments based on the feature control information to increase a quality of 3D graphics information generated by the 3D graphics application.3. The at least one machine-readable medium of claim 1 , the performance metric comprising a frame rate of video generated by the 3D graphics application ...

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Номер записи: 32
12-02-2015 дата публикации

Method, Apparatus, And System For Energy Efficiency And Energy Conservation Including Power And Performance Balancing Between Multiple Processing Elements And/Or A Communication Bus

Номер: US20150046730A1
Автор: Fenger Russell J., Schluessler Travis T.
Принадлежит:

An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit. 1. A processor comprising: a first core;', 'a cache memory;', 'a communication bus coupled to the first core, the communication bus to couple the first core and the cache memory;', 'a graphics processor;', 'a core workload monitor to determine a core workload for the first core;', 'a bus workload monitor to determine a bus workload for the communication bus; and', 'a power control unit including logic to receive the bus workload and to dynamically balance power between the first core and the communication bus based on a power limit for the processor and a comparison between the bus workload and a bus workload threshold, the power limit corresponding to a maximum thermal dissipation capacity for the processor, wherein a power consumption of one of the first core and the communication bus is to be reduced if a thermal value of the processor exceeds the power limit., 'a first semiconductor die including2. The processor of claim 1 , further comprising a second core and a second core workload monitor to determine a second core workload for the second core claim 1 , wherein the first core includes a host processing core claim 1 , the second core includes a graphics processing core claim 1 , and the communication bus includes a ring interconnect claim 1 ...

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Номер записи: 33
18-02-2021 дата публикации

FIELD RECOVERY OF GRAPHICS ON-DIE MEMORY

Номер: US20210050070A1
Автор: Appu Abhishek R., KENNEDY Jonathan, Koker Altug, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N.
Принадлежит:

Systems, apparatuses and methods may provide for technology that identifies a redundant portion of a packaged on-die memory and detects, during a field test of the packaged on-die memory, one or more failed cells in the packaged on-die memory. Additionally, one or more memory cells in the redundant portion may be substituted for the one or more failed memory cells. 1. (canceled)2. A system comprising:a power supply to provide power to the system; anda semiconductor package apparatus including a substrate, an on-die memory coupled to the substrate, and logic coupled to the substrate, wherein the on-die memory is to include a redundant portion, wherein the logic is implemented in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the substrate to:identify the redundant portion of the on-die memory,execute a field test on the on-die memory, wherein the field test is to include a program of a functional pattern into the on-die memory and a read of the on-die memory to determine whether the on-die memory was programmed correctly with the functional pattern, anddetect, during the field test of the on-die memory, one or more failed memory cells in the on-die memory.3. The system of claim 2 , wherein the logic coupled to the substrate is to reduce a size of the on-die memory in response to detection of the one or more failed memory cells.4. The system of claim 2 , wherein the logic coupled to the substrate is to conduct a fuse override to substitute one or more remaining memory cells in the redundant portion for the one or more failed memory cells.5. The system of claim 2 , wherein the logic coupled to the substrate is to execute the field test in response to one or more of each power down condition associated with the on-die memory claim 2 , each power up condition associated with the on-die memory claim 2 , an idleness condition associated with the on-die memory claim 2 , or an expiration of a periodic timer.6. The system of ...

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Номер записи: 34
03-03-2022 дата публикации

Regional Adjustment of Render Rate

Номер: US20220066726A1
Автор: Abhishek R. Appu, Altug Koker, Balaji Vembu, Devan BURKE, Elmoustapha Ould-Ahmed-Vall, Eric J. ASPERHEIM, Jacek Kwiatkowski, John H. Feit, Joydeep Ray, Kamal SINHA, Kiran C. Veernapu, Nikos Kaburlasos, Peter L. Doyle, Philip R. Laws, Sanjeev S. Jahagirdar, Subramaniam M. Maiyuran, Travis T. Schluessler
Принадлежит: Intel Corp

In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

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Номер записи: 35
13-02-2020 дата публикации

GRAPHICS WITH ADAPTIVE TEMPORAL ADJUSTMENTS

Номер: US20200051524A1
Автор: Appu Abhishek R., Burke Devan, Cimini David M., Feit John H., Feng Louis, Janczak Tomasz, Kaburlasos Nikos, Koker Altug, Kwiatkowski Jacek, Lauritzen Andrew T., Laws Philip R., Ould-Ahmed-Vall Elmoustapha, Ray Joydeep, Schluessler Travis T.
Принадлежит:

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed. 1. At least one computer readable storage medium comprising a set of instructions , which when executed by a computing system , cause the computing system to:assign a first rate to a first region of a frame; andassign a second rate to a second region of the frame, wherein the second rate indicates a greater number of pixels to share a pixel shader result than the first rate, wherein the first rate and the second rate are associated with temporal anti-aliasing data, and wherein the second region corresponds to higher motion content than the first region.2. The at least one computer readable storage medium of claim 1 , wherein the instructions claim 1 , when executed claim 1 , further cause the computing system to assign a third rate to a third region of the frame claim 1 , wherein the third rate indicates a greater number of pixels to share a pixel shader result than the second rate claim 1 , and wherein the third rate is associated with temporal anti-aliasing data.3. The at least one computer readable storage medium of claim 2 , wherein the third corresponds to higher motion content than the second region.4. The at least one computer readable storage medium of claim 1 , wherein the second region corresponds to higher motion content than the first region.5. The at least one computer readable storage medium of claim 1 , wherein the first rate and the second rate are associated with ...

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Номер записи: 36
10-03-2022 дата публикации

Low power foveated rendering to save power on gpu and/or display

Номер: US20220076467A1
Автор: Jacek Kwiatkowski, John H. Feit, Joydeep Ray, Nikos Kaburlasos, Prasoonkumar Surti, Travis T. Schluessler, Wenyin Fu
Принадлежит: Intel Corp

Methods and apparatus relating to techniques for provision of low power foveated rendering to save power on GPU (Graphics Processing Unit) and/or display are described. In various embodiment, brightness/contrast, color intensity, and/or compression ratio applied to pixels in a fovea region are different than those applied in regions surrounding the fovea region. Other embodiments are also disclosed and claimed.

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Номер записи: 37
10-03-2022 дата публикации

CLOUD BASED DISTRIBUTED SINGLE GAME CALCULATION OF SHARED COMPUTATIONAL WORK FOR MULTIPLE CLOUD GAMING CLIENT DEVICES

Номер: US20220076480A1
Автор: Appu Abhishek R., Boles Jeffery S., GRAJEWSKI SLAWOMIR, KENNEDY Jonathan, Koker Altug, Kwiatkowski Jacek, Liktor Gabor, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., Vembu Balaji
Принадлежит:

Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices. 124-. (canceled)25. A graphics processing system , comprising: identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client devices of a plurality of users by analyzing the graphics data to detect view-independent graphics calculations, and', 'generate, in response to the identified redundant graphics calculations, a single calculation for common frame characteristics relating to the one or more graphical scenes to be shared by the client devices., 'a cloud computing server including a graphics processor having logic to26. The graphics processing system of claim 25 , wherein the graphics processor is to send the calculation of the common frame characteristics to the client devices to be visually presented as rendered visual content in a 3D virtual space.27. The graphics processing system of claim 25 , wherein the common frame characteristics comprises frame geometry.28. The graphics processing system of claim 25 , wherein the common frame characteristics comprises frame lighting.29. A graphics processing system claim 25 , comprising: identify, from graphics data in the graphics application, redundant texture maps relating to common frame characteristics of one or more graphical scenes to be shared between ...

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Номер записи: 38
28-02-2019 дата публикации

Specialized code paths in gpu processing

Номер: US20190066256A1
Автор: Abhishek Venkatesh, Jon Hasselgren, Rahul P. Sathe, Saurabh Sharma, Thomas F. Raoux, Travis T. Schluessler
Принадлежит: Intel Corp

Techniques to improve graphics processing unit (GPU) performance by introducing specialized code paths to process frequent common values are described. A shader compiler can determine instruction that, during operation, may output a common value and can introduce an enhanced shader instruction branch to process the common value to reduce overall computational requirements to execute the shader.

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Номер записи: 39
28-02-2019 дата публикации

METHOD AND APPARATUS FOR PROFILE-GUIDED GRAPHICS PROCESSING OPTIMIZATIONS

Номер: US20190066355A1
Автор: Apodaca Michael, DAVIDSON William B., Guo Peng, Lueh Guei-yuan, Schluessler Travis T.
Принадлежит:

An apparatus and method for collecting and using profile data during graphics processing. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics commands responsive to execution of an application; and profile storage to store graphics execution profile data associated with one or more graphics workloads; and a profile manager to read the profile data upon detecting one of the graphics workloads during execution of the application and to configure the graphics processor in accordance with the profile data. 1. An apparatus comprising:a graphics processor to process graphics commands responsive to execution of an application; andprofile storage to store graphics execution profile data associated with one or more graphics workloads; anda profile manager to read the profile data upon detecting one of the graphics workloads during execution of the application and to configure the graphics processor in accordance with the profile data.2. The apparatus as in wherein the profile data comprises both hardware and software configuration settings for the graphics processor.3. The apparatus as in wherein the profile data indicates a number of SIMD lanes to be allocated for processing the graphics workload.4. The apparatus as in wherein the profile manager is to generate the profile data by monitoring execution of the workload using different hardware and/or software configuration settings.5. The apparatus as in wherein the profile manager is to select the hardware and/or software configuration settings resulting in the most efficient execution of the graphics workload that fits within a specified power budget.6. The apparatus as in further comprising:an application-level profile requestor to instruct the profile manager to generate and subsequently use the profile data.7. The apparatus as in further comprising:an application programming interface (API) extension to an existing 3D API to establish communication between the application-level ...

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Номер записи: 40
28-02-2019 дата публикации

APPARATUS AND METHOD FOR A PROGRAMMABLE DEPTH STENCIL GRAPHICS PIPELINE STAGE

Номер: US20190066356A1
Автор: GIERACH JOHN C., PALKE DARREL K., Schluessler Travis T., Surti Prasoonkumar
Принадлежит:

An apparatus and method for programmable depth stencil pipeline stage and shading. For example, one embodiment of a graphics processing apparatus comprises: a rasterizer to generate a plurality of pixel blocks, one or more of which overlap one or more primitives; programmable depth stencil circuitry to perform depth stencil tests on the pixels which overlap the one or more primitives to identify pixels which pass the depth stencil tests; and thread dispatch circuitry to dispatch pixel shader threads to perform pixel shading operations on those pixels which pass the depth stencil tests, the thread dispatch circuitry including thread dispatch recombine logic to combine pixels which have passed the depth stencil test from multiple pixel blocks into a set of pixel shader threads to be executed concurrently on single instruction multiple data (SIMD) hardware. 1. A graphics processing apparatus comprising:a rasterizer to generate a plurality of pixel blocks, one or more of which overlap one or more primitives;programmable depth stencil circuitry to perform depth stencil tests on the pixels which overlap the one or more primitives to identify pixels which pass the depth stencil tests; andthread dispatch circuitry to dispatch pixel shader threads to perform pixel shading operations on those pixels which pass the depth stencil tests, the thread dispatch circuitry including thread dispatch recombine logic to combine pixels which have passed the depth stencil test from multiple pixel blocks into a set of pixel shader threads to be executed concurrently on thread execution hardware.2. The graphics processing apparatus as in wherein the programmable depth stencil circuitry is to implement a programmable depth stencil shader to perform the depth stencil tests.3. The graphics processing apparatus as in wherein the thread execution hardware comprises single instruction multiple data (SIMD) hardware claim 1 , the thread dispatch recombine logic to pack each pixel which passes the ...

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Номер записи: 41
05-03-2020 дата публикации

Memory-based dependency tracking and cache pre-fetch hardware for multi-resolution shading

Номер: US20200073810A1
Автор: Abhishek R. Appu, Altug Koker, Andrew T. Lauritzen, Balaji Vembu, Gabor Liktor, Hugues Labbe, Jacek Kwiatkowski, John G. Gierach, John H. Feit, Joydeep Ray, Nikos Kaburlasos, Tomer Bar-On, Travis T. Schluessler
Принадлежит: Intel Corp

Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.

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Номер записи: 42
12-03-2020 дата публикации

CONTEXTUAL CONFIGURATION ADJUSTER FOR GRAPHICS

Номер: US20200082494A1
Автор: Appu Abhishek R., HURD LINDA L., Kuwahara Atsuo, Mastronarde Josh B., Ould-Ahmed-Vall Elmoustapha, Ranganathan Vasanth, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., Vembar Deepak S.
Принадлежит:

An embodiment of a graphics apparatus may include a context engine to determine contextual information, a recommendation engine communicatively coupled to the context engine to determine a recommendation based on the contextual information, and a configuration engine communicatively coupled to the recommendation engine to adjust a configuration of a graphics operation based on the recommendation. Other embodiments are disclosed and claimed. 1. (canceled)2. A graphics apparatus , comprising:a substrate; andlogic coupled to the substrate, wherein the logic is implemented, at least partly, in one or more of configurable logic or fixed-functionality hardware logic, the logic to:determine contextual information;develop a recommendation using machine learning based on the contextual information;adjust a configuration of a graphics operation based on the recommendation;monitor a condition including one or more of an action of a user or a response of the user following the adjustment of the configuration of the graphics operation;determine a future configuration adjustment based on the condition.3. The apparatus according to claim 2 , wherein the contextual information is to include one or more oflocation data, biometric data, time data, temperature data, power data, environmental data, schedule data, habit data, or configuration settings for a prior frame.4. The apparatus according to claim 2 , wherein the contextual information is determined based on contextual data claim 2 , thecontextual data is to include one or more of brightness of an environment, a temperature of the environment, movement information of the user, biometric information of the user, gesture information of the user, or facial information of the user. This application claims benefit to U.S. patent application Ser. No. 15/483,623 filed Apr. 10, 2017.Embodiments generally relate to data processing and to graphics processing. More particularly, embodiments relate to a contextual configuration adjuster for ...

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Номер записи: 43
21-03-2019 дата публикации

METHOD AND APPARATUS FOR EFFICIENT PROCESSING OF DERIVED UNIFORM VALUES IN A GRAPHICS PROCESSOR

Номер: US20190087998A1
Автор: Lueh Guei-yuan, NEYMAN Aleksander, Raoux Thomas F., Schluessler Travis T., SPITZBARTH Bartosz
Принадлежит:

Various embodiments enable low frequency calculation of derived uniform values. A compiler can identify one or more portions of a shader that calculate a derived value based on an input value. For example, this portion may include instructions that use constant values, or the results of prior functions that used constant values. The constant values may include hardcoded values provided by the program (e.g., immediates) and/or other constant values. This portion of the shader can be extracted by the compiler and compiled into a first program. The compiler can compile the remainder of the shader into a second program that receives the derived uniform values from the first program. By extracting the portion(s) of the program that calculates a derived value into a separate program, the derived uniform value or values can be calculated at a lower frequency than if they were calculated for each pixel. 1. A system comprising:a central processing unit to execute an application;a graphics processor to process graphics commands responsive to execution of the application; and receive a shader from the application;', 'analyze the shader to identify a portion of the shader including derived uniform calculations;', 'generate a program to execute the portion of the shader using the derived uniform calculations; and', 'generate a compiled shader configured to receive an output of the program., 'a compiler to2. The system as in wherein the program is executable by the central processing unit.3. The system as in further comprising: receive a draw call from the application, the draw call including at least one input value;', 'execute the program to perform the derived uniform calculations using the at least one input value to generate at least one output value; and', 'send the at least one output value from the program to the compiled shader to perform the draw call., 'a device driver to4. The system as in wherein the program is a compute shader executable by the graphics processor.5. ...

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Номер записи: 44
05-05-2022 дата публикации

GRAPHICS WITH ADAPTIVE TEMPORAL ADJUSTMENTS

Номер: US20220139351A1
Автор: Appu Abhishek R., Burke Devan, Cimini David M., Feit John H., Feng Louis, Janczak Tomasz, Kaburlasos Nikos, Koker Altug, Kwiatkowski Jacek, Lauritzen Andrew T., Laws Philip R., Ould-Ahmed-Vall Elmoustapha, Ray Joydeep, Schluessler Travis T.
Принадлежит: Intel Corporation

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.

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Номер записи: 45
23-04-2015 дата публикации

TECHNIQUES FOR DETERMINING AN ADJUSTMENT FOR A VISUAL OUTPUT

Номер: US20150109326A1
Автор: BACHAR LIRAN, GURTOVOY STAS, ROMANO JACKY, Schluessler Travis T., ZADICARIO GUY
Принадлежит:

Various embodiments are generally directed to an apparatus, method and other techniques for receiving image information for a current frame, determining an amount of change between the current frame and a previous based on the image information for the current frame and image information for a previous frame and determining an adjustment of a frame time based on the amount of change between the current frame and the previous frame. 1. An apparatus , comprising:processing circuitry;a visual quality metric module for execution on the processing circuitry to receive image information for a current frame and determine an amount of change between the current frame and a previous frame based on the image information for the current frame and image information for the previous frame; anda visual quality adjustment module for execution on the processing circuitry to determine an adjustment of a frame time based on the amount of change between the current frame and the previous frame.2. The apparatus of claim 1 , the adjustment comprising:a decrease in the frame time when the amount of change based on the image information for the current frame and the image information for the previous frame is greater than a perceived quality threshold;an increase in the frame time when the amount of change based on the image information for the current frame and the image information for the previous frame is less than to the perceived quality threshold; andno change in the frame time when there is no change based on the image information for the current frame and the image information for the previous frame.3. The apparatus of claim 1 , the visual quality metric module to determine the amount of change based on a comparison between pixels of the current frame with pixels of the previous frame claim 1 , wherein the pixels of the current frame are at corresponding locations of the pixels of the previous frame.4. The apparatus of claim 3 , the image information comprising pixel color ...

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Номер записи: 46
17-07-2014 дата публикации

A METHOD AND DEVICE TO AUGMENT VOLATILE MEMORY IN A GRAPHICS SUBSYSTEM WITH NON-VOLATILE MEMORY

Номер: US20140198116A1
Автор: Ramadoss Murali, Schluessler Travis T., Veal Bryan E., Vembu Balaji
Принадлежит:

Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command. 1. A method comprising:storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM), the NVRAM being directly accessible by a graphics processor using at least memory store and load commands;a graphics processor executing a graphics application, wherein the graphics processor at least sends a request using a memory load command for an address corresponding to at least one of the one or more static or near-static graphics resources stored in the NVRAM;in response to the memory load command, directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor.2. The method of claim 1 , further comprising:storing a graphics processor memory management unit address map in a volatile memory location accessible to a graphics memory manager logic component;the graphics memory manager logic component managing a logical address to physical address map for each of a plurality of graphics resources related to the graphics application, wherein the one or more static or near-static graphics resources are part of the plurality of graphics resources related to the graphics application; andthe graphics memory manager logic ...

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Номер записи: 47
09-06-2022 дата публикации

Synergistic temporal anti-aliasing and coarse pixel shading technology

Номер: US20220182575A1
Автор: Abhishek Venkatesh, Jacek Kwiatkowski, John H. Feit, Joydeep Ray, Karthik Vaidyanathan, Michael Apodaca, Murali Ramadoss, Nikos Kaburlasos, Prasoonkumar Surti, Travis T. Schluessler
Принадлежит: Intel Corp

Systems, apparatuses and methods may provide for technology that determines a frame rate of video content, sets a blend amount parameter based on the frame rate, and temporally anti-aliases the video content based on the blend amount parameter. Additionally, the technology may detect a coarse pixel (CP) shading condition with respect to one or more frames in the video content and select, in response to the CP shading condition, a per frame jitter pattern that jitters across pixels, wherein the video content is temporally anti-aliased based on the per frame jitter pattern. The CP shading condition may also cause the technology to apply a gradient to a plurality of color planes on a per color plane basis and discard pixel level samples associated with a CP if all mip data corresponding to the CP is transparent or shadowed out.

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Номер записи: 48
09-05-2019 дата публикации

DISPLAY ENGINE SURFACE BLENDING AND ADAPTIVE TEXEL TO PIXEL RATIO SAMPLE RATE SYSTEM, APPARATUS AND METHOD

Номер: US20190139192A1
Автор: Appu Abhishek R., Feit John H., Kaburlasos Nikos, Kwiatkowski Jacek, Ray Joydeep, Schluessler Travis T., Surti Prasoonkumar, Vembu Balaji
Принадлежит:

Systems, apparatuses and methods may provide away to blend two or more of the scene surfaces based on the focus area and an offload threshold. More particularly, systems, apparatuses and methods may provide a way to blend, by a display engine, two or more of the focus area scene surfaces and blended non-focus area scene surfaces. The systems, apparatuses and methods may include a graphics engine to render the focus area surfaces at a higher sample rate than the non-focus area scene surfaces. 1a power source to supply power to the system;a memory comprising a scene, the memory coupled to a processor; [ monitor a gaze of a user viewing the scene, and', 'identify a focus area in the scene based on the gaze of the user; and, 'a gaze monitor to, 'a display engine to blend two or more of the scene surfaces based on the focus area and an offload threshold., 'a graphics pipeline apparatus to receive the scene, the scene including scene surfaces, the graphics pipeline apparatus comprising. A system comprising: The present application claims the benefit of priority to U.S. Non-Provisional patent application Ser. No. 15/494,709 filed on Apr. 24, 2017.Embodiments generally relate to rendering a scene, and more particularly to blending focus area scene surfaces and blended non-focus area scene surfaces, and rendering the focus area surfaces at a higher sample rate than the non-focus area scene surfaces.Currently, rendering systems may upscale pixels from render resolution to display resolution for foveated rendering or multi-resolution rendering, inefficiently consuming power and GPU bandwidth. In addition, traditional systems may use a fixed sample rate for texel to pixel ratio, and therefore not adaptable to Improved performance and power efficiency.In the following description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to one of skill in the art that the present invention may be ...

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Номер записи: 49
16-05-2019 дата публикации

MOTION BIASED FOVEATED RENDERER

Номер: US20190147640A1
Автор: Appu Abhishek R., Bar-On Tomer, Benthin Carsten, Feit John H., Kaburlasos Nikos, KENNEDY Jonathan, Kp Sameer, Kuwahara Atsuo, Kwiatkowski Jacek, Labbe Hugues, Lake Adam T., Ranganathan Vasanth, Ray Joydeep, Schluessler Travis T., Surti Prasoonkumar, Vaidyanathan Karthik
Принадлежит:

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed. 1an application processor;persistent storage media communicatively coupled to the application processor;a graphics subsystem communicatively coupled to the application processor;a sense engine communicatively coupled to the graphics subsystem to provide sensed information;a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information;a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information; anda motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, and the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information.. An electronic processing system, comprising: The present application claims the benefit of priority to U.S. Non-Provisional patent application Ser. No. 15/477,019 filed on Apr. 1, 2017.Embodiments generally relate to data processing and to graphics processing via a graphics ...

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Номер записи: 50
11-06-2015 дата публикации

Reducing Network Latency During Low Power Operation

Номер: US20150163143A1
Автор: Lake Daniel S., Larsen Steen K., Memon Mazhar I., Schluessler Travis T., Veal Bryan E.
Принадлежит:

In an embodiment, a method includes identifying a core of a multicore processor to which an incoming packet that is received in a packet buffer is to be directed, and if the core is powered down, transmitting a first message to cause the core to be powered up prior to arrival of the incoming packet at a head of the packet buffer. Other embodiments are described and claimed. 1. A method comprising:identifying a core of a multicore processor to which an incoming packet that is received in a packet buffer is to be directed; andif the core is powered down, transmitting a first message to cause the core to be powered up prior to arrival of the incoming packet at a head of the packet buffer.2. The method of claim 1 , further comprising sending the incoming packet to the core after the incoming packet arrives at the head of the packet buffer.3. The method of claim 1 , further comprising prior to receipt of the incoming packet in the packet buffer claim 1 , determining a level of network traffic of a network coupled to the multicore processor and responsive to a determination that the level of activity is less than a threshold level claim 1 , transmitting an initial message to cause the core to be powered down.4. The method of claim 1 , wherein the incoming packet includes an incoming packet flow identifier claim 1 , and wherein identifying the core to which the incoming packet is to be directed comprises accessing a mapping table that maps each flow identifier to a corresponding core identifier.5. The method of claim 4 , further comprising accessing the mapping table using a content addressable memory.6. The method of claim 1 , further comprising transmitting a second message to a component associated with the core to cause the component to be powered up if the core is powered down.7. The method of claim 1 , further comprising claim 1 , prior to transmitting the first message claim 1 , powering down a plurality of cores of the multicore processor responsive to determining ...

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Номер записи: 51
24-06-2021 дата публикации

SYSTEM AND METHOD FOR HIGH PERFORMANCE SECURE ACCESS TO A TRUSTED PLATFORM MODULE ON A HARDWARE VIRTUALIZATION PLATFORM

Номер: US20210194696A1
Автор: Sahita Ravi L., Schluessler Travis T.
Принадлежит:

A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. Example instructions partition resources of the host system to allocate (a) first resources of the host system for a first virtual machine and (b) second resources of the host system for a second virtual machine, wherein the resources of the host system include memory resources and a trusted platform module, the first virtual machine to run a first guest operating system and the second virtual machine to run a second guest operating system, wherein the first guest operating system is to run in a first isolated environment, the second guest operating system is to run in a second isolated environment; implement a virtual trusted platform module to support encryption for the first virtual machine; and protect the first resources and the second resources from unauthorized access. 1. At least one storage device comprising instructions that when executed by one or more processors cause the one or more processors of a host system to at least: partition resources of the host system to allocate (a) first resources of the host system for a first virtual machine and (b) second resources of the host system for a second virtual machine, wherein the resources of the host system include memory resources and a trusted platform module, the first virtual machine to run a first guest operating system and the second virtual machine to run a second guest operating system, wherein the first guest operating system is to run in a first isolated environment, the second guest operating system is to run in a second isolated environment, the first isolated environment to be isolated from the second isolated environment;', 'implement a virtual trusted platform module to support encryption for the first virtual machine; and', 'protect the first resources and the second resources from unauthorized access., 'execute a hypervisor to2. The at least one storage device of claim 1 ...

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Номер записи: 52
22-06-2017 дата публикации

SPECIALIZED CODE PATHS IN GPU PROCESSING

Номер: US20170178277A1
Автор: HASSELGREN Jon, Raoux Thomas F., Sathe Rahul P., Schluessler Travis T., Sharma Saurabh, Venkatesh Abhishek
Принадлежит:

Techniques to improve graphics processing unit (GPU) performance by introducing specialized code paths to process frequent common values are described. A shader compiler can determine instruction that, during operation, may output a common value and can introduce an enhanced shader instruction branch to process the common value to reduce overall computational requirements to execute the shader. 1. An apparatus to compile a shader comprising: determine whether a shader instruction can output a predetermined value; and', 'compile the shader instruction to include an enhanced sub-sequence based on a determination that the shader instruction can output the predetermined value., 'logic, at least a portion of which is implemented in hardware, the logic to2. The apparatus of claim 1 , the logic to compile the shader instruction omitting the enhanced sub-sequence based on a determination that the shader instruction cannot output the predetermined value.3. The apparatus of claim 1 , the logic to:evaluate at least one coordinate; anddetermine whether the shader instruction can output the predetermined value based on the at least one coordinate.4. The apparatus of claim 1 , wherein the shader instruction comprises a sample_c instruction claim 1 , a mul_sat instruction claim 1 , an add_sat instruction claim 1 , a ld instruction claim 1 , a sample instruction claim 1 , an AND instruction claim 1 , a greater than instruction claim 1 , an equal to instruction claim 1 , or a less than instruction.5. The apparatus of claim 4 , wherein the common value comprises one claim 4 , zero claim 4 , 1.0 f claim 4 , 0.0 f claim 4 , or the like.6. The apparatus of claim 1 , the logic to generate an enhanced shader based in part on compiling the shader instructions claim 1 , the enhanced shader to:determine whether the output of the shader instruction equals the predetermined value; andexecute a first sequence based on a determination that the output of the shader instruction equals the ...

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Номер записи: 53
18-09-2014 дата публикации

TECHNIQUES FOR POWER SAVING ON GRAPHICS-RELATED WORKLOADS

Номер: US20140281615A1
Автор: LEIBEL Adam Z., Panneer Selvakumar, Schluessler Travis T., THOMAS TION A.
Принадлежит:

Various embodiments are generally directed to an apparatus, method and other techniques for monitoring a task of a graphics processing unit (GPU) by a graphics driver, determining if the task is complete, determining an average task completion time for the task if the task is not complete and enabling a sleep state for a processing circuit for a sleep state time if the average task completion time is greater than the sleep state time. 1. An apparatus , comprising:a memory;a processing circuit coupled to the memory;a graphics processing unit (GPU) coupled to the processing circuit and the memory to process graphics-related tasks; anda graphics driver module to monitor a task of the GPU, determine when the task is complete, determine an average task completion time for the task when the task is not complete, and enable a sleep state for the processing circuit for a sleep state time when the average task completion time is greater than the sleep state time.2. The apparatus of claim 1 , the graphics driver module to disable the sleep state for the processing circuit upon expiration of the sleep state time or upon completion of the task.3. The apparatus of claim 1 , the graphics driver module to store a task start time when the task is not complete.4. The apparatus of claim 3 , the graphics driver module to determine a task completion time for the task based on the task start time when the task is complete.5. The apparatus of claim 1 , the graphics driver module to determine an average task completion based upon an average of one or more task completion times for one or more tasks.6. The apparatus of claim 1 , the graphics driver module to receive a request from an application for a completion status of the task and send a response to the application indicating whether the task is complete or not complete based upon the completion status.7. The apparatus of claim 1 , the graphics driver module to generate an event notification for the task claim 1 , receive the event ...

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Номер записи: 54
04-07-2019 дата публикации

COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS

Номер: US20190205736A1
Автор: Abidi Huma, Bar-On Tomer, Bleiweiss Amit, Burke Devan, Elibol Oguz, Gierach John, Keskin Gokce, Menon Jaikrishnan, Nurvitadhi Eriko, Patel Nishant, Schluessler Travis T., Srivastava Dhawal, Thomas Anil, Thorehosur Appajigowda Pruthvi Gowda, Venkatesh Abhishek
Принадлежит: Intel Corporation

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations. 1. An apparatus to facilitate compute optimization , comprising:at least one processor to perform operations to implement a neural network; andcompute logic to accelerate neural network computations.2. The apparatus of claim 1 , wherein the compute logic comprises:a local memory to store one or more graph representations; andgraph processing unit (GrPU) to accelerate computations of the graph representation.3. The apparatus of claim 2 , wherein the GrPU supports multiple function pointers and threads to accelerate traversing the one or more graph representations.4. The apparatus of claim 2 , wherein the compute logic further comprises a compilation unit (CU) to compile shader kernels.5. The apparatus of claim 4 , wherein the CU and the GrPU are implemented to compute an optimized shader operation.6. The apparatus of claim 1 , wherein the compute logic performs non-uniform quantization for the neural network.7. The apparatus of claim 6 , wherein performing the non-uniform quantization comprises providing a lower error percentage to weight values that have a significant impact for accuracy of the neural network.8. The apparatus of claim 7 , wherein discrete points are selected to have lower error percentage for large absolute value numbers claim 7 , and selected to have higher error percentage for small absolute value numbers.9. The apparatus of claim 1 , wherein the compute logic comprises an Computing Language (OpenCL) to accelerate workloads on the neural network.10. The apparatus of claim 9 , wherein the OpenCL shares weights across hidden layers of the neural network.11. The apparatus of claim 10 , wherein the neural network is a Recurrent neural network (RNN).12. The apparatus of claim 10 , wherein the neural network is a long short-term ...

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Номер записи: 55
05-08-2021 дата публикации

COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS

Номер: US20210241417A1
Автор: Akhbari Farshad, Appu Abhishek R., Ashbaugh Ben J., BAGHSORKHI Sara S., Barik Rajkishore, Boles Jeffery S., Burke Devan, Chen Feng, Feit John H., Fu Wenyin, Galoppo von Borries Nicolas C., Gottschlich Justin E., HURD LINDA L., Kim Dukhwan, Koker Altug, Lake Adam T., Lin Tsung-Han, Maiyuran Subramaniam, Mastronarde Josh B., Nurvitadhi Eriko, Ray Joydeep, Satish Nadathur Rajagopalan, Schluessler Travis T., Sinha Kamal, Srinivasa Narayan, Surti Prasoonkumar, Vaidyanathan Karthik, Vembu Balaji
Принадлежит: Intel Corporation

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type. 1. A graphics processing unit comprising one or more multiprocessors , at least one of the one or more multiprocessors including:a register file to store operands for a plurality of different types of operands; anda plurality of processing cores, including:a first set of processing cores of a first type to perform multi-dimensional matrix math operations on a first set of operands in a first set of registers of the register file; anda second set of processing cores of a second type, the second set of processing cores being different from the first set of processing cores, the second set of processing cores to perform general purpose graphics processing unit (GPGPU) operations on a second set of operands in a second set of registers of the register file.2. The graphics processing unit as in claim 1 , wherein the first set of processing cores of the first type includes a first set of floating point units (FPUs) to execute instructions to perform matrix operations on the first set of operands in the first set of registers of the register file.3. The graphics processing unit as in claim 2 , wherein matrix operations performed on the first set of operands include 64-bit floating (FP64) operations.4. The graphics processing unit as in claim 2 , wherein the second set of processing cores comprises:a set of integer units to execute instructions to perform integer operations; anda second set of FPUs to execute instructions to perform floating point operations, the set of FPUs comprising a first subset of FPUs to perform 32-bit floating point (FP32) operations and a second subset of FPUs to FP64 operations.5. The graphics processing unit as in claim 1 , wherein the first set of processing cores of the first type is configured to ...

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Номер записи: 56
02-07-2020 дата публикации

HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS

Номер: US20200210238A1
Автор: Appu Abhishek R, Asperheim Eric J., Borole Bhushan M., Fu Wenyin, GRAJEWSKI SLAWOMIR, HURD LINDA L., Jahagirdar Sanjeev S., Janczak Tomasz, Kaburlasos Nikos, Koker Altug, Lueh Guei-yuan, Maiyuran Subramaniam, Mastronarde Josh B., Puffer David, Ray Joydeep, Schluessler Travis T., Sinha Kamal, Surti Prasoonkumar, Veernapu Kiran C., Vembu Balaji, Venkatesh Abhishek, Xiao Kai
Принадлежит: Intel Corporation

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed. 120-. (canceled)21. A general-purpose graphics processor , comprising:a low-performance processing resource;a high-performance processing resource;a cache memory structure communicatively coupled to the low-performance processing resource and the high-performance processing resource; and receive a workload resource requirement data set for a workload to be executed by the general purpose graphics processor;', 'define a set of work group boundaries within the workload;', 'initiate execution of the workload on one of the low-performance processing resource or the high-performance processing resource based at least in part on the workload requirement data set;', 'save a workload context when execution of the workload reaches a work group boundary in the set of work group boundaries; and', 'assign the workload to a different processing resource based at least in part on a physical proximity to resources associated with a related workload., 'a thread scheduler to22. The general-purpose graphics processor of claim 21 , the thread scheduler to:parse the workload requirement data set.23. The general-purpose graphics processor of claim 21 , wherein the low-performance processing resource and the high-performance processing resource reside on a common processor.24. The general-purpose graphics processor of claim 21 , wherein the low-performance processing resource and the high-performance processing resource are separate processing structures.25. The general-purpose graphics processor of claim 21 , the thread scheduler to:determine an execution resource requirement from the one or more ...

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Номер записи: 57
09-07-2020 дата публикации

ADAPTIVE MULTI-RESOLUTION FOR GRAPHICS

Номер: US20200218330A1
Автор: AMSTUTZ Jefferson, Appu Abhishek R., BROWNLEE Carson, Feit John H., Holland James M., K. Pattabhiraman, Kaburlasos Nikos, Kwiatkowski Jacek, Lahiri Sayan, Ould-Ahmed-Vall Elmoustapha, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., Sinha Kamal, Tiwari Vivek, Vembar Deepak S., VENKATARAMAN RADHAKRISHNAN, Xiao Kai
Принадлежит:

An embodiment may include an application processor, persistent storage media coupled to the application processor, and a graphics subsystem coupled to the application processor. The system may further include any of a performance analyzer to analyze a performance of the graphics subsystem to provide performance analysis information, a content-based depth analyzer to analyze content to provide content-based depth analysis information, a focus analyzer to analyze a focus area to provide focus analysis information, an edge analyzer to provide edge analysis information, a frame analyzer to provide frame analysis information, and/or a variance analyzer to analyze respective amounts of variance for the frame. The system may further include a workload adjuster to adjust a workload of the graphics subsystem based on the analysis information. Other embodiments are disclosed and claimed. 1. At least one non-transitory computer readable storage medium comprising a set of application programming instructions , which when executed by a computing device , cause the computing device to:identify one or more values that are to be accessed during frame generation; andassign a first shading rate to a current region of a current frame based on the one or more values,wherein the current region is to share a temporal and spatial association with a previous region of a previous frame that was previously shaded at a second shading rate higher than the first shading rate, wherein the previous region is identified as being shadeable at a lower shading rate than the second shading rate based on having a color coherence throughout the previous region, and wherein the current region has the color coherence.2. The at least one non-transitory computer readable storage medium of claim 1 , wherein the color coherence comprises the current region and the previous region being a same color.3. The at least one non-transitory computer readable storage medium of claim 1 , wherein the color coherence is ...

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Номер записи: 58
23-09-2021 дата публикации

Augmented reality virtual reality ray tracing sensory enhancement system, apparatus and method

Номер: US20210297801A1
Автор: Abhishek R. Appu, Archie Sharma, Atsuo Kuwahara, Barnan Das, Gokcen Cilingir, Jacek Kwiatkowski, James M. Holland, Jeffery S. BOLES, John H. Feit, Jonathan Kennedy, Joydeep Ray, Louis Feng, Mayuresh M. Varerkar, Narayan Biswal, Nikos Kaburlasos, Nilesh V. Shah, Prasoonkumar Surti, Stanley J. Baran, Travis T. Schluessler
Принадлежит: Intel Corp

Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

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Номер записи: 59
15-08-2019 дата публикации

Frequent Data Value Compression for Graphics Processing Units

Номер: US20190251655A1
Автор: Anantaraman Aravindh V., Appu Abhishek R., Borole Bhushan M., Fu Wenyin, Hoekstra Eric J., HURD LINDA L., K. Pattabhiraman P., Koker Altug, Ranganathan Vasanth, Ray Joydeep, Schluessler Travis T., Sharma Saurabh, Sinha Kamal, Surti Prasoonkumar, Venkatesh Abhishek
Принадлежит:

A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline. 1. A method comprising:providing a first unique code to indicate at least one common data pattern for an entire cacheline, where a common data pattern is made up of repeating identical single data values;providing a second unique code to indicate at least one repeating data pattern for less than an entire cacheline, where a repeating data pattern is made up of a sequence of more than one data value, said sequence repeating within less than an entire cacheline;in response to detecting a common data pattern, writing a first unique code, instead of writing the common data pattern;upon identifying said first unique code during a cacheline read, substituting for the first unique code, the common data pattern represented by the first unique code;in response to detecting a repeating data pattern, writing a second unique code, instead of writing the common data pattern, wherein the first and second unique codes are different codes; andupon identifying the second unique code during a cacheline read, substituting for the second unique code, the repeating data pattern represented by the second unique code.2. The method of wherein the common data pattern is repeated zeros or repeated ones.3. The method of providing a first or second unique code only if a cacheline is entirely composed of a single common data pattern or a single repeating data pattern.4. The method of including encoding the first unique code and the second unique code each including only two bits.5. The method of including using one of the two bits to indicate that whether the code represents a common data pattern or a repeating data ...

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Номер записи: 60
22-08-2019 дата публикации

GRAPHICS PROCESSOR WITH TILED COMPUTE KERNELS

Номер: US20190259128A1
Автор: Burke Devan, Feng Louis, GRAJEWSKI SLAWOMIR, Janczak Tomasz, Schluessler Travis T., Surti Prasoonkumar, Venkatesh Abhishek, Xiao Kai
Принадлежит:

An embodiment of a graphics apparatus may include a tile candidate identifier to determine if a compute kernel is a tile candidate, and a compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate. Other embodiments are disclosed and claimed. 1an application processor;persistent storage media communicatively coupled to the application processor; and determine if a compute kernel is a tile candidate; and', 'tile the compute kernel if the compute kernel is determined to be a tile candidate., 'a graphics processor communicatively coupled to the application processor, the graphics processor to. An electronic processing system, comprising: Embodiments generally relate to data processing and to graphics processing. More particularly, embodiments relate to a graphics processor with tiled compute kernels.Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors used fixed function computational units to process graphics data; however, more recently, portions of graphics processors have been made programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data. Some systems may support tile-based processing.In the following description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to one of skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention.System Overviewis a block diagram illustrating a computing system configured to implement one or more aspects ...

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Номер записи: 61
22-08-2019 дата публикации

AUGMENTED REALITY VIRTUAL REALITY RAY TRACING SENSORY ENHANCEMENT SYSTEM, APPARATUS AND METHOD

Номер: US20190261122A1
Автор: Appu Abhishek R., Baran Stanley J., Biswal Narayan, Boles Jeffery S., Cilingir Gokcen, DAS BARNAN, Feit John H., Feng Louis, Holland James M., Kaburlasos Nikos, KENNEDY Jonathan, Kuwahara Atsuo, Kwiatkowski Jacek, Ray Joydeep, Schluessler Travis T., Shah Nilesh V., SHARMA ARCHIE, Surti Prasoonkumar, Varerkar Mayuresh M.
Принадлежит:

Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience. 1. (canceled)2. A system comprising:a power source to supply power to the system;a memory comprising environment information, the memory coupled to a processor; and normalize the environment information to a position of an observer to generate normalized environment information for the observer;', 'calculate, for the observer, sound sources or sensed events vector paths;', 'apply two or more of an absorption filter, an attenuation filter, and a reflective filter to the normalized environment information to form filtered normalized environment information, based on attributes of the sound sources or sensed events vector paths; and', 'play back the filtered normalized environment information to the observer based on the vector paths., 'a ray tracing engine to, 'a graphics pipeline apparatus comprising3. The system of claim 2 , the ray tracing engine further to:generate a number of ray bundles for the sounds, the ray bundles including a number of frequency bands based on acoustic properties of one or more of the sound sources, wherein the environment information is further to include one or more objects or surfaces in the path of one or more of the vector paths, and wherein the ray bundles are to be based on one or more of the acoustic properties of the sound, the objects, or the surfaces;wherein the vector paths include vector path attributes including one more of positional information ...

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Номер записи: 62
11-11-2021 дата публикации

COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS

Номер: US20210350499A1
Автор: Akhbari Farshad, Appu Abhishek R., Ashbaugh Ben J., BAGHSORKHI Sara S., Barik Rajkishore, Boles Jeffery S., Burke Devan, Chen Feng, Feit John H., Fu Wenyin, Galoppo von Borries Nicolas C., Gottschlich Justin E., HURD LINDA L., Kim Dukhwan, Koker Altug, Lake Adam T., Lin Tsung-Han, Maiyuran Subramaniam, Mastronarde Josh B., Nurvitadhi Eriko, Ray Joydeep, Satish Nadathur Rajagopalan, Schluessler Travis T., Sinha Kamal, Srinivasa Narayan, Surti Prasoonkumar, Vaidyanathan Karthik, Vembu Balaji
Принадлежит: Intel Corporation

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of processing cores of a first type and a second type. A first set of processing cores of a first type perform multi-dimensional matrix operations and a second set of processing cores of a second type perform general purpose graphics processing unit (GPGPU) operations. 1. A graphics processing unit comprising one or more multiprocessors , at least one of the one or more multiprocessors including:a register file to store a plurality of different types of operands; anda plurality of processing cores, including:a first set of processing cores of a first type to perform multi-dimensional matrix operations on a first set of operands in a first set of registers of the register file, wherein the first set of processing cores of the first type includes circuitry to execute instructions to perform matrix operations on the first set of operands in the first set of registers of the register file, the first set of operands including one or more 64-bit operands; anda second set of processing cores of a second type, the second set of processing cores being different from the first set of processing cores, the second set of processing cores to perform general purpose graphics processing unit (GPGPU) operations on a second set of operands in a second set of registers of the register file.2. The graphics processing unit as in claim 1 , wherein the second set of processing cores comprises:a set of floating point units (FPUs) to execute instructions to perform floating point operations, the set of FPUs to perform 32-bit floating point (FP32) operations and 16-bit floating point (FP16) operations; anda set of integer units to execute instructions to perform integer operations.3. The graphics processing unit as in claim 2 , wherein the set of FPUs includes first FPUs to perform 32-bit floating point (FP32) operations and second FPUs to perform ...

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Номер записи: 63
29-09-2016 дата публикации

METHOD AND APPARATUS FOR INTELLIGENT CLOUD-BASED GRAPHICS UPDATES

Номер: US20160284041A1
Автор: Schluessler Travis T., TAYLOR ROBERT B., Venkatesh Abhishek, WALSH DANIEL H.
Принадлежит:

An apparatus and method are described for cloud-based graphics updates. For example, one embodiment of an apparatus comprises a system optimization agent to detect a graphics application installed on the apparatus, the system optimization agent to responsively transmit, over a network, information related to the graphics application including a new graphics application or a new version of an existing graphics application. The apparatus may further comprise the system optimization agent to receive, over the network, optimized program code comprising one or more optimizations to specified portions of a graphics driver, where the one or more optimizations relate to the graphics application. The apparatus may further comprise the system optimization agent to install and enable only those specified portions of the graphics driver for which optimizations have been received, where the installation and enablement triggers at least one of increased user experience and increased performance relating to the graphics application. 1. An apparatus comprising:a system optimization agent to detect a graphics application installed on the apparatus, the system optimization agent to responsively transmit, over a network, information related to the graphics application including a new graphics application or a new version of an existing graphics application;the system optimization agent to receive, over the network, optimized program code comprising one or more optimizations to specified portions of a graphics driver, wherein the one or more optimizations relate to the graphics application; andthe system optimization agent to install and enable only those specified portions of the graphics driver for which optimizations have been received, wherein the installation and enablement triggers at least one of increased user experience and increased performance relating to the graphics application.2. The apparatus as in wherein the system optimization agent is to further transmit claim 1 , ...

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Номер записи: 64
05-09-2019 дата публикации

Frequent Data Value Compression for Graphics Processing Units

Номер: US20190272613A1
Автор: Anantaraman Aravindh V., Appu Abhishek R., Borole Bhushan M., Fu Wenyin, Hoekstra Eric J., HURD LINDA L., K. Pattabhiraman P., Koker Altug, Ranganathan Vasanth, Ray Joydeep, Schluessler Travis T., Sharma Saurabh, Sinha Kamal, Surti Prasoonkumar, Venkatesh Abhishek
Принадлежит:

A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline. 1. A method comprising:using a first code for a first type of recurring data value in a cacheline of a graphics processor;using a second code different from first code for a second type of recurring data value of the graphics processor, wherein the first and second types have different lengths;in response to detecting the first type of recurring data value, writing the first code instead of writing said first type of recurring data value; andin response to detecting the second type of recurring data value, writing the second code instead of writing said second type of recurring data value.2. The method of wherein said first type has a length equal to a cacheline length and the second type has a length of less than a cacheline.3. The method of wherein encoding includes encoding repeated zeros or repeated ones.4. The method of wherein encoding is only performed if a cacheline is entirely composed of a single frequently recurring data value.5. The method of including encoding the frequently recurring data value using only two bits.6. The method of including using one of the two bits to indicate that at least one frequently recurring data value exists and using the other bit to differentiate two frequently recurring data values.7. The method of including using preprogrammed frequently recurring data values.8. The method of including identifying the frequently recurring data value during compile time.9. The method of including identifying the frequently recurring data value during run time.10. The method of including monitoring streams for a plurality of frequently recurring data values claim 1 ...

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Номер записи: 65
27-08-2020 дата публикации

PROCESSOR POWER MANAGEMENT

Номер: US20200272215A1
Автор: Appu Abhishek R., Borole Bhushan M., Fu Wenyin, Hoekstra Eric J., Kaburlasos Nikos, KENNEDY Jonathan, Koker Altug, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., Sinha Kamal, Surti Prasoonkumar, Veernapu Kiran C., Vembu Balaji
Принадлежит: Intel Corporation

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed. 118-. (canceled)19. An apparatus comprising:one or more processors including a graphical processing unit (GPU), the GPU including a graphics processing pipeline, the graphics processing pipeline including a plurality of stages; anda memory to store data, including graphics data processed by the graphics processing pipeline; collect one or more performance metrics associated with operation of each stage of the plurality of stages of the graphics processing pipeline, and', 'adjust at least one of an operating voltage or an operating frequency for one or more stages of the plurality of stages based at least in part on the one or more performance metrics for each stage., 'wherein the apparatus is to20. The apparatus of claim 19 , wherein adjusting at least one of the operating voltage or the operating frequency for the one or more stages includes the apparatus to:determining a level of activity for each stage the plurality of stages utilizing at least the one or more performance metrics; andadjust at least one of an operating voltage or an operating frequency for the one or more stages based at least in part on the determined level of activity for each stage of the plurality of stages.21. The apparatus of claim 20 , wherein the apparatus is to perform one or more of:increase the operating voltage or operating frequency for a first stage that is determined to have a higher level of activity in the plurality of stages; ordecrease the operating voltage or operating frequency for a second stage that is ...

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Номер записи: 66
04-10-2018 дата публикации

Processor power management

Номер: US20180284868A1
Автор: Abhishek R. Appu, Altug Koker, Ankur N. Shah, Balaji Vembu, Bhushan M. Borole, Eric J. Hoekstra, Jonathan Kennedy, Joydeep Ray, Kamal SINHA, Kiran C. Veernapu, Nikos Kaburlasos, Prasoonkumar Surti, Travis T. Schluessler, Wenyin Fu
Принадлежит: Intel Corp

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

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Номер записи: 67
04-10-2018 дата публикации

ADAPTIVE MULTI-RESOLUTION FOR GRAPHICS

Номер: US20180284872A1
Автор: AMSTUTZ Jefferson, Appu Abhishek R., BROWNLEE Carson, Feit John H., Holland James M., K. Pattabhiraman, Kaburlasos Nikos, Kwiatkowski Jacek, Lahiri Sayan, Ould-Ahmed-Vall Elmoustapha, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., Sinha Kamal, Tiwari Vivek, Vembar Deepak S., VENKATARAMAN RADHAKRISHNAN, Xiao Kai
Принадлежит:

An embodiment may include an application processor, persistent storage media coupled to the application processor, and a graphics subsystem coupled to the application processor. The system may further include any of a performance analyzer to analyze a performance of the graphics subsystem to provide performance analysis information, a content-based depth analyzer to analyze content to provide content-based depth analysis information, a focus analyzer to analyze a focus area to provide focus analysis information, an edge analyzer to provide edge analysis information, a frame analyzer to provide frame analysis information, and/or a variance analyzer to analyze respective amounts of variance for the frame. The system may further include a workload adjuster to adjust a workload of the graphics subsystem based on the analysis information. Other embodiments are disclosed and claimed. 1. An electronic processing system , comprising:an application processor;persistent storage media communicatively coupled to the application processor;a graphics subsystem communicatively coupled to the application processor;a performance analyzer communicatively coupled to the graphics subsystem to analyze a performance of the graphics subsystem to provide performance analysis information; anda workload adjuster communicatively coupled to the graphics subsystem and the performance analyzer to adjust a workload of the graphics subsystem based on the performance analysis information.2. The system of claim 1 , further comprising:a content-based depth analyzer communicatively coupled to the graphics subsystem and the workload adjuster to analyze content to provide content-based depth analysis information, wherein the workload adjuster is further to adjust the workload of the graphics subsystem based on the content-based depth analysis information.3. The system of claim 1 , further comprising:a focus analyzer communicatively coupled to the graphics subsystem and the workload adjuster to analyze a ...

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Номер записи: 68
04-10-2018 дата публикации

HIERARCHICAL GENERAL REGISTER FILE (GRF) FOR EXECUTION BLOCK

Номер: US20180285106A1
Автор: Appu Abhishek R., Hoekstra Eric J., HURD LINDA L., Koker Altug, Lueh Guei-yuan, Maiyuran Subramaniam, Pal Supratim, Puffer David, Ray Joydeep, Schluessler Travis T., Sinha Kamal, Surti Prasoonkumar, Veernapu Kiran C.
Принадлежит:

In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed. 1. An apparatus comprising:a plurality of execution units; anda first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units.2. The apparatus of claim 1 , further comprising:a second GRF communicatively coupled to the plurality of execution units.3. The apparatus of claim 2 , wherein:the first GRF is a low-powered GRF; andthe second GRF is a high-powered GRF.4. The apparatus of claim 2 , further comprising logic claim 2 , wherein:the first GRF and the second GRF are separate memory structures.5. The apparatus of claim 2 , wherein:the first GRF and the second GRF are embodied in a single memory structure.6. The apparatus of claim 1 , wherein:each of the plurality of execution units comprises a local GRF.7. The apparatus of claim 6 , wherein:the first GRF is a slow GRF; andthe local GRF coupled to each of the execution units is a fast GRF.8. The apparatus of claim 6 , further comprising logic claim 6 , at least partially including hardware logic claim 6 , to:detect a data context switch between two or more of the plurality of execution units, and in response to the data context switch, to redirect a data inquiry from the first general register file to a remote memory device.9. The apparatus of claim 8 , wherein the remote memory device comprises a L3 cache.10. The apparatus of claim 1 , wherein the plurality of execution units and the first GRF are on a single integrated circuit.11. An electronic device claim 1 , comprising:a processor having a plurality of execution units; anda first general register file (GRF) communicatively couple to the plurality of execution units, wherein the ...

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Номер записи: 69
04-10-2018 дата публикации

HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS

Номер: US20180285158A1
Автор: Appu Abhishek R., Asperheim Eric J., Borole Bhushan M., Fu Wenyin, GRAJEWSKI SLAWOMIR, HURD LINDA L., Jahagirdar Sanjeev S., Janczak Tomasz, Kaburlasos Nikos, Koker Altug, Lueh Guei-yuan, Maiyuran Subramaniam, Mastronarde Josh B., Puffer David, Ray Joydeep, Schluessler Travis T., Sinha Kamal, Surti Prasoonkumar, Veernapu Kiran C., Vembu Balaji, Venkatesh Abhishek, Xiao Kai
Принадлежит:

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed. 1. An apparatus comprising:a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit; and analyze a workload; and', 'assign the workload to one of the first type of execution unit or the second type of execution unit., 'logic, at least partially including hardware logic, to2. The apparatus of claim 1 , wherein:the first type of execution unit is a low-performance execution unit; andthe second type of execution unit is a high-performance execution unit.3. The apparatus of claim 2 , wherein:the first type of execution unit and the second type of execution unit reside on a common processor.4. The apparatus of claim 2 , further comprising logic claim 2 , wherein:the first GRF and the second GRF are separate processing structures.5. The apparatus of claim 2 , wherein:the first GRF and the second GRF are communicatively coupled to a common memory structure.6. The apparatus of claim 1 , further comprising an application programming interface which allows a programmer to pass hints about one or more characteristics of the workload to the logic.7. The apparatus of claim 6 , further comprising a compiler comprising logic claim 6 , at least partially including hardware logic claim 6 , to:determine an execution resource requirement from the one or more characteristics of the workload.8. The apparatus of claim 7 , further comprising a driver comprising logic claim 7 , at least partially including hardware logic claim 7 , to:store the execution resource requirement as kernel thread meta-data.9. The apparatus of claim 8 , further comprising ...

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Номер записи: 70
04-10-2018 дата публикации

Reference voltage control based on error detection

Номер: US20180285191A1
Автор: Abhishek R. Appu, Altug Koker, Ankur N. Shah, Eric C. Samson, Eric J. ASPERHEIM, Jacek Kwiatkowski, Joydeep Ray, Kiran C. Veernapu, Sanjeev S. Jahagirdar, SUBRAMANIAM MAIYURAN, Travis T. Schluessler
Принадлежит: Intel Corp

Methods and apparatus relating to techniques for reference voltage control based on error detection are described. In an embodiment, modification to a reference voltage (to be supplied to one or more components of a processor) is based at least in part on error detection to be detected for a reference circuit. In another embodiment, modification is made to a power characteristic of a processor in response to a determination that the processor is to execute a safety critical application. The modification may include adjustment to an operating frequency and/or an operating voltage of the processor. Other embodiments are also disclosed and claimed.

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Номер записи: 71
04-10-2018 дата публикации

MULTI-RESOLUTION SMOOTHING

Номер: US20180286024A1
Автор: Feit John H., Kaburlasos Nikos, Kwiatkowski Jacek, Ray Joydeep, Schluessler Travis T.
Принадлежит: Intel Corporation

Systems, apparatuses, and methods may provide for technology to process multi-resolution images by identifying pixels at a boundary between pixels of different resolutions, and selectively smoothing the identified pixels. 1. A computing system , comprising:a display to present visual content;a memory to store a set of instructions; and a substrate,', 'a host processor coupled to the substrate, wherein when executed by the host processor, the set of instructions cause the host processor to generate an object description associated with the visual content, and', 'a graphics processor coupled to the substrate, wherein the graphics processor includes logic to:', 'receive image data of visual content to be rendered at different resolutions at different regions of a frame;', 'identify boundary pixels; and', 'selectively smooth the identified boundary pixels., 'a semiconductor package apparatus coupled to the display and the memory, the semiconductor package apparatus including2. The system of claim 1 , wherein the visual content is to be rendered:at a first resolution at a first region of a frame via a first plurality of pixels; andat a second resolution which is different than the first resolution, at a second region of the frame via a second plurality of pixels.3. The system of claim 1 , wherein the logic is to generate a pixel map containing pixel data.4. The system of claim 3 , wherein the boundary pixels are identified using the pixel data.5. The system of claim 1 , wherein the boundary pixels are identified based on changes in pixel characteristics.6. A semiconductor package apparatus claim 1 , comprising:a substrate; and receive image data of visual content to be rendered at different resolutions at different regions of a frame;', 'identify boundary pixels; and', 'selectively smooth the identified pixels., 'logic coupled to the substrate, wherein the logic is at least partially implemented in one or more of configurable logic or fixed-functionality hardware logic, ...

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Номер записи: 72
04-10-2018 дата публикации

Motion biased foveated renderer

Номер: US20180286105A1
Автор: Abhishek R. Appu, Adam T. Lake, Atsuo Kuwahara, Carsten BENTHIN, Hugues Labbe, Jacek Kwiatkowski, John H. Feit, Jonathan Kennedy, Joydeep Ray, Karthik Vaidyanathan, Nikos Kaburlasos, Prasoonkumar Surti, Sameer Kp, Tomer Bar-On, Travis T. Schluessler, Vasanth Ranganathan
Принадлежит: Intel Corp

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

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Номер записи: 73
12-09-2019 дата публикации

MULTI-SAMPLE STEREO RENDERER

Номер: US20190279413A1
Автор: Feit John H., Kaburlasos Nikos, Kwiatkowski Jacek, Laws Philip R., Ray Joydeep, Schluessler Travis T.
Принадлежит:

An embodiment of a parallel processor apparatus may include a sample pattern selector to select a sample pattern for a pixel, and a sample pattern subset selector communicatively coupled to the sample pattern selector to select a first subset of the sample pattern for the pixel corresponding to a left eye display frame and to select a second subset of the sample pattern for the pixel corresponding to a right eye display frame, wherein the second subset is different from the first subset. Other embodiments are disclosed and claimed. 1. (canceled)2. A parallel processor apparatus , comprising:a sample pattern selector to select a sample pattern for a pixel; anda sample pattern subset selector communicatively coupled to the sample pattern selector to select a first subset of the sample pattern for the pixel corresponding to a left eye display frame and to select a second subset of the sample pattern for the pixel corresponding to a right eye display frame,wherein the second subset is different from the first subset, andwherein the sample pattern subset selector is further to select a different subset of the sample pattern for the first subset for a current left eye display frame as compared to the first subset for a previous left eye display frame.3. The apparatus of claim 2 , wherein the first subset for the current left eye display frame is one of rotated claim 2 , shifted claim 2 , and swapped as compared to the first subset for the previous left eye display frame.4. The apparatus of claim 2 , wherein the sample pattern comprises one of a 1× claim 2 , 2× claim 2 , 4× claim 2 , 8× claim 2 , and 16× multi-sample anti-aliasing pattern.5. A method of processing a pixel claim 2 , comprising:selecting a sample pattern for a pixel;selecting a first subset of the sample pattern for the pixel corresponding to a left eye display frame;selecting a second subset of the sample pattern for the pixel corresponding to a right eye display frame, wherein the second subset is ...

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Номер записи: 74
04-10-2018 дата публикации

TECHNIQUES FOR DETERMINING AN ADJUSTMENT FOR A VISUAL OUTPUT

Номер: US20180286353A1
Автор: BACHAR LIRAN, GURTOVOY STAS, ROMANO JACKY, Schluessler Travis T., ZADICARIO GUY
Принадлежит: Intel Corporation

Various embodiments are generally directed to an apparatus, method and other techniques for receiving image information for a current frame, determining an amount of change between the current frame and a previous based on the image information for the current frame and image information for a previous frame and determining an adjustment of a frame time based on the amount of change between the current frame and the previous frame. 125.-. (canceled)26. An apparatus , comprising:memory; andprocessing circuitry coupled with the memory, the processing circuitry to determine an amount of change between a current frame and a previous frame based on image information for the current frame and image information for the previous frame; compare the amount of change to a perceived quality threshold to adjust a hysteresis value; compare the hysteresis value to a hysteresis threshold to determine an adjustment of a frame time, wherein the frame time is an amount of time to process one frame; and adjust the frame time based on the adjustment, in response to the hysteresis value exceeding the hysteresis threshold.271. The apparatus of claim , the adjustment comprising:a decrease in the frame time in response to a first hysteresis value exceeding a first threshold andan increase in the frame time in response to a second hysteresis value exceeding a second threshold, wherein the hysteresis value comprises the first hysteresis value and second hysteresis value and wherein the hysteresis threshold comprises the first hysteresis threshold and second hysteresis threshold, the first hysteresis value and second hysteresis value to be reset in response to the adjustment of the frame time.281. The apparatus of claim , the processing circuitry to determine the amount of change based on a comparison between pixels of the current frame with pixels of the previous frame , wherein the pixels of the current frame are at corresponding locations of the pixels of the previous frame.29. The ...

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Номер записи: 75
11-10-2018 дата публикации

Adjusting graphics rendering based on facial expression

Номер: US20180292895A1
Автор: Abhishek R. Appu, Ankur N. Shah, Balaji Vembu, Carson Brownlee, Deepak S. Vembar, Elmoustapha Ould-Ahmed-Vall, Jacek Kwiatkowski, Jefferson Amstutz, John H. Feit, Josh B. Mastronarde, Joydeep Ray, Kai Xiao, Nikos Kaburlasos, Sayan Lahiri, Travis T. Schluessler, Vivek Tiwari
Принадлежит: Intel Corp

An embodiment of a graphics apparatus may include a facial expression detector to detect a facial expression of a user, and a parameter adjuster communicatively coupled to the facial expression detector to adjust a graphics parameter based on the detected facial expression of the user. The detected facial expression may include one or more of a squinting, blinking, winking, and facial muscle tension of the user. The graphics parameter may include one or more of a frame resolution, a screen contrast, a screen brightness, and a shading rate. Other embodiments are disclosed and claimed.

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Номер записи: 76
11-10-2018 дата публикации

POWER MANAGEMENT OF MEMORY CHIPS BASED ON WORKING SET SIZE

Номер: US20180293011A1
Автор: Anantaraman Aravindh V., Appu Abhishek R., Koker Altug, Ray Joydeep, Schluessler Travis T., Surti Prasoonkumar, Vembu Balaji
Принадлежит: Intel Corporation

Briefly, in accordance with one or more embodiments, an apparatus comprises a memory comprising one or more physical memory chips, and a processor to implement a working set monitor to monitor a working set resident in the one or more physical memory chips. The working set monitor is to adjust a number of the physical memory chips that are powered on based on a size of the working set. 1. An apparatus , comprising:a memory comprising one or more physical memory chips; anda processor to implement a working set monitor to monitor a working set resident in the one or more physical memory chips;wherein, the working set monitor is to adjust a number of the physical memory chips that are powered on based on a size of the working set.2. The apparatus of claim 1 , wherein the working set monitor is to power down one or more of the physical memory chips if the size of the working set may be reduced to a smaller number of the physical memory chips.3. The apparatus of claim 2 , wherein the working set monitor is to copy contents from a physical memory chip to be powered down to a physical memory chip to remain powered after reduction of the size of the working set.4. The apparatus of claim 1 , wherein the working set monitor is to power up one or more of the physical memory chips if the size of the working set is to be increased to a larger number of the physical memory chips.5. The apparatus of claim 1 , wherein the working set monitor is to evaluate memory usage of the application when the application starts up.6. The apparatus of claim 1 , wherein the working set monitor is to evaluate the memory usage of the application during a profiling pass.7. The apparatus of claim 1 , wherein the working set monitor is to reevaluate memory usage of the application periodically.8. The apparatus of claim 1 , wherein the working set monitor is to put one or more of the physical memory chips that are not needed for the working set into self-refresh mode.9. The apparatus of claim 1 , ...

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Номер записи: 77
11-10-2018 дата публикации

GRAPHICS MEMORY EXTENDED WITH NONVOLATILE MEMORY

Номер: US20180293173A1
Автор: Appu Abhishek R., Ferreira Cristiano J., Gandiga Shivakumar Deepak, Guttridge Brandt M., KENNEDY Jonathan, Koker Altug, Nandyal Lakshman Ajit Krisshna, Pallister Kim, Qiu Bo, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., Soqui Frank J., Srivatsa Anand, TALPALLIKAR Nikhil, Zhu Jianfang
Принадлежит:

An embodiment of an electronic processing system may include an application processor, system memory communicatively coupled to the application processor, a graphics processor communicatively coupled to the application processor, graphics memory communicatively coupled to the graphics processor, and persistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media. The persistent storage media may include a low latency, high capacity, and byte-addressable nonvolatile memory. The one or more graphics assets may include one or more of a mega-texture and terrain data. Other embodiments are disclosed and claimed. 1. An electronic processing system , comprising:an application processor;system memory communicatively coupled to the application processor;a graphics processor communicatively coupled to the application processor;graphics memory communicatively coupled to the graphics processor; andpersistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media.2. The system of claim 1 , wherein the persistent storage media comprises a low latency claim 1 , high capacity claim 1 , and byte-addressable nonvolatile memory.3. The system of claim 1 , wherein the one or more graphics assets include one or more of a mega-texture and terrain data.4. A graphics memory apparatus claim 1 , comprising:persistent storage media to store one or more graphics assets; anda memory mapper to map a physical location of the one or more graphics assets to a memory location accessible by a graphics application.5. The apparatus of claim 4 , wherein the persistent storage media comprises a byte-addressable persistent ...

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Номер записи: 78
11-10-2018 дата публикации

Frequent Data Value Compression for Graphics Processing Units

Номер: US20180293695A1
Автор: Abhishek R. Appu, Abhishek Venkatesh, Altug Koker, Aravindh V. Anantaraman, Bhushan M. Borole, Eric J. Hoekstra, Joydeep Ray, Kamal SINHA, Linda L. Hurd, Pattabhiraman P. K., Prasoonkumar Surti, Saurabh Sharma, Travis T. Schluessler, Vasanth Ranganathan, Wenyin Fu
Принадлежит: Intel Corp

A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

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Номер записи: 79
11-10-2018 дата публикации

CONTEXTUAL CONFIGURATION ADJUSTER FOR GRAPHICS

Номер: US20180293697A1
Автор: Appu Abhishek R., HURD LINDA L., Kuwahara Atsuo, Mastronarde Josh B., Ould-Ahmed-Vall Elmoustapha, Ranganathan Vasanth, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., Vembar Deepak S.
Принадлежит:

An embodiment of a graphics apparatus may include a context engine to determine contextual information, a recommendation engine communicatively coupled to the context engine to determine a recommendation based on the contextual information, and a configuration engine communicatively coupled to the recommendation engine to adjust a configuration of a graphics operation based on the recommendation. Other embodiments are disclosed and claimed. 1. An electronic processing system , comprising:a graphics subsystem;persistent storage media communicatively coupled to the graphics subsystem;memory communicatively coupled to the graphics subsystem;a display communicatively coupled to the graphics subsystem; anda contextual configuration adjuster communicatively coupled to the graphics subsystem to adjust a configuration of the graphics subsystem based on contextual information.2. The system of claim 1 , wherein the contextual configuration adjuster comprises a context engine to determine the contextual information.3. The system of claim 2 , further comprising:a recommendation engine communicatively coupled to the context engine to determine a recommendation based on the contextual information.4. The system of claim 3 , wherein the contextual configuration adjuster is further to adjust the configuration of the graphics subsystem based at least in part on the recommendation from the recommendation engine.5. The system of claim 1 , further comprising:a sense engine communicatively coupled to the contextual configuration adjuster to sense contextual data.6. The system of claim 1 , further comprising:a profiler to determine profile information for a graphics application; anda neural network trainer to train a neural network to develop a configuration decision network for the graphics application based on the profile information.7. The system of claim 6 , wherein the contextual configuration adjuster is further to adjust the configuration of the graphics subsystem based on the ...

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Номер записи: 80
11-10-2018 дата публикации

GRAPHICS PROCESSOR WITH TILED COMPUTE KERNELS

Номер: US20180293698A1
Автор: Burke Devan, Feng Louis, GRAJEWSKI SLAWOMIR, Janczak Tomasz, Schluessler Travis T., Surti Prasoonkumar, Venkatesh Abhishek, Xiao Kai
Принадлежит:

An embodiment of a graphics apparatus may include a tile candidate identifier to determine if a compute kernel is a tile candidate, and a compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate. Other embodiments are disclosed and claimed. 1. An electronic processing system , comprising:an application processor;persistent storage media communicatively coupled to the application processor; and determine if a compute kernel is a tile candidate; and', 'tile the compute kernel if the compute kernel is determined to be a tile candidate., 'a graphics processor communicatively coupled to the application processor, the graphics processor to2. The system of claim 1 , wherein the graphics processor is further to:determine if all thread groups for the compute kernel are localized; andidentify the compute kernel as a tile candidate if all thread groups for the compute kernel are determined to be localized.3. The system of claim 1 , wherein the graphics processor is further to:execute the tiled compute kernel in a same tile pass as a tiled render kernel.4. A graphics apparatus claim 1 , comprising:a tile candidate identifier to determine if a compute kernel is a tile candidate; anda compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate.5. The apparatus of claim 4 , wherein the tile candidate identifier is further to:determine if all data needed by the compute kernel comes from within a tile and if all output from the compute kernel is written to the tile; andidentify the compute kernel as a tile candidate if all data needed by the compute kernel is determined to come from within the tile and if all output from the compute kernel is determined to be written to the tile.6. The apparatus of claim 4 , wherein the tile candidate identifier is further to:determine if all ...

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Номер записи: 81
11-10-2018 дата публикации

Multi-sample stereo renderer

Номер: US20180293779A1
Автор: Jacek Kwiatkowski, John H. Feit, Joydeep Ray, Nikos Kaburlasos, Philip R. Laws, Travis T. Schluessler
Принадлежит: Intel Corp

An embodiment of a parallel processor apparatus may include a sample pattern selector to select a sample pattern for a pixel, and a sample pattern subset selector communicatively coupled to the sample pattern selector to select a first subset of the sample pattern for the pixel corresponding to a left eye display frame and to select a second subset of the sample pattern for the pixel corresponding to a right eye display frame, wherein the second subset is different from the first subset. Other embodiments are disclosed and claimed.

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Номер записи: 82
19-09-2019 дата публикации

AUGMENTED REALITY AND VIRTUAL REALITY FEEDBACK ENHANCEMENT SYSTEM, APPARATUS AND METHOD

Номер: US20190287290A1
Автор: Apodaca Michael, Baran Stanley J., Biswal Narayan, Boles Jeffery S., Cilingir Gokcen, DAS BARNAN, Feit John H., Feng Louis, Holland James M., Kaburlasos Nikos, KENNEDY Jonathan, Koker Altug, Kwiatkowski Jacek, Lake Adam T., Ray Joydeep, Sakthivel Chandrasekaran, Schluessler Travis T., Shah Nilesh V., SHARMA ARCHIE, Surti Prasoonkumar, Varerkar Mayuresh M., Xiao Kai
Принадлежит:

Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment. 1. (canceled)2. An apparatus comprising:a substrate; andlogic coupled to the substrate, wherein the logic is implemented in one or more of configurable logic or fixed-functionality hardware logic, and the logic is to:monitor one or more actions of an observer observing n-dimensional environment information, the environment information including feedback information;detect feedback information, wherein the feedback information includes a priority relationship to the observer, wherein the priority relationship identifies one or more of observer directed feedback information directed to the observer or undirected feedback information; andnormalize the environment information and the feedback information, the normalized feedback information being based on the one or more actions of the observer or the priority relationship of the feedback information to the observer,wherein the feedback information is identified as known feedback information or unknown feedback information, andwherein unknown feedback identifier training is requested when the unknown feedback information is detected.3. The apparatus of claim 2 , wherein the apparatus attenuates one or more feedback devices based on one or more operating parameters claim 2 , the feedback devices being coupled to the apparatus.4. The apparatus of claim 3 ,wherein one or more of a gaze direction, a focus area, non-focus area or the location of the observer are monitored,wherein the environment information includes one more of virtual reality information or ...

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Номер записи: 83
18-10-2018 дата публикации

Regional Adjustment of Render Rate

Номер: US20180300096A1
Автор: Appu Abhishek R., Asperheim Eric J., Burke Devan, DOYLE PETER L., Feit John H., Jahagirdar Sanjeev S., Kaburlasos Nikos, Koker Altug, Kwiatkowski Jacek, Laws Philip R., Maiyuran Subramaniam M., Ould-Ahmed-Vall Elmoustapha, Ray Joydeep, Schluessler Travis T., Sinha Kamal, Veernapu Kiran C., Vembu Balaji
Принадлежит:

In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments. 1. A method comprising:identifying two different screen regions of one screen display; andrendering the two regions of the one screen display at different rendering rates.2. The method of including identifying a screen region the user is currently looking at.3. The method of including predicting a screen region that a user will look at next.4. The method of including predicting based on a historical viewing pattern.5. The method of including predicting based on what will be displayed in the future.6. The method of including detecting a user's viewing pattern and using that detected pattern to predict a region that will be viewed in the future.7. The method of including defining more than two screen regions.8. The method of including implementing more than two render rates on the same display.9. The method of including rendering a region the user is not currently looking at with temporal anti-aliasing and rendering another region with multi-sampled anti-aliasing.10. The method of including tracking a moving screen object to predict which region will be viewed by the user in the future.11. The method of further comprising:selecting assigning cores of different precision to each of at least two distinct screen regions; andrendering each of said region with a core of different precision.12. The method of wherein said cores are part of a common processing unit.13 ...

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Номер записи: 84
18-10-2018 дата публикации

MEMORY-BASED DEPENDENCY TRACKING AND CACHE PRE-FETCH HARDWARE FOR MULTI-RESOLUTION SHADING

Номер: US20180300145A1
Автор: Appu Abhishek R., Bar-On Tomer, Feit John H., Gierach John G., Kaburlasos Nikos, Koker Altug, Kwiatkowski Jacek, Labbe Hugues, Lauritzen Andrew T., Liktor Gabor, Ray Joydeep, Schluessler Travis T., Vembu Balaji
Принадлежит:

Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space. 1. A system comprising:a power source to supply power to the system;a memory comprising one or more blocks of pixel samples for one or more regions of a screen space, the memory coupled to a processor; 'a dependency tracker to track one or more operation dependencies between two or more pipeline operations for one or more of the blocks of pixel samples, wherein the dependency tracker stalls one or more of the pipeline operations based on the one or more operation dependencies.', 'a graphics pipeline apparatus comprising2. The system of claim 1 , further comprising:a dependency tracker buffer to track one or more cache lines accessed by the two or more pipeline operations, assigns sequence numbers to each of the pipeline operations based on one or more operation dependencies between two or more of the pipeline operations, wherein the operation dependencies identify a dependent operation, an in-process operation, or an independent operation, wherein the dependent operation is executed upon completion of the in-process operation,', 'tracks the pipeline operations and access requests to one or more of the cache lines requested by the operations, wherein the access requests include two or more of a dependent operation request, an in-process operation request, ...

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Номер записи: 85
18-10-2018 дата публикации

ADAPTIVE CACHE SIZING PER WORKLOAD

Номер: US20180300238A1
Автор: Appu Abhishek R., Asperheim Eric J., Borole Bhushan M., Fu Wenyin, Hoekstra Eric J., HURD LINDA L., Jahagirdar Sanjeev S., K PATTABHIRAMAN, Kaburlasos Nikos, Koker Altug, Maiyuran Subramaniam, Mastronarde Josh B., Ray Joydeep, Schluessler Travis T., Sinha Kamal, Surti Prasoonkumar, Veernapu Kiran C., Vembu Balaji
Принадлежит:

Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to monitor cache utilization of an application during execution of the application for a workload; and a memory to store cache utilization statistics responsive to the monitored cache utilization. The processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application. 1. An apparatus , comprising:a processor to monitor cache utilization of an application during execution of the application for a workload; anda memory to store cache utilization statistics responsive to the monitored cache utilization;wherein the processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application.2. The apparatus of claim 1 , wherein the cache utilization statistics comprise per frame cache statistics.3. The apparatus of claim 1 , wherein the optimal cache configuration is stored in the memory as a per workload profile for the application claim 1 , and the smallest amount of cache to be turned on for subsequent executions of the workload is based at least in part on the per workload profile.4. The apparatus of claim 1 , wherein the processor is to store parameters for the optimal cache configuration in a context image in the memory.5. The apparatus of claim 1 , wherein the processor is to power on one or more banks of caches based at least in part on the optimal cache configuration.6. The apparatus of claim 1 , wherein the processor is to power off claim 1 , or leave powered off claim 1 , one or more banks of caches based at least in part on the optimal cache configuration.7. The apparatus of claim 1 , wherein ...

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Номер записи: 86
18-10-2018 дата публикации

DISPLAY LINK COMPRESSION BY RENDER ENGINE

Номер: US20180300840A1
Автор: Appu Abhishek R., Hoekstra Eric J., HURD LINDA L., Ray Joydeep, Schluessler Travis T., Surti Prasoonkumar
Принадлежит:

Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to render data from an application to be displayed on a display panel, and a memory to store the compressed final display surface writes. The processor is to compress final display surface writes of the data to be displayed on the display panel in a format to be displayed on the display to allow a display engine coupled to the display to stream the compressed final display surface writes to the display. 1. An apparatus , comprising:a processor to render from an application to be displayed on a display panel; anda memory to store compressed final display surface writes;wherein the processor is to compress final display surface writes of the data to be displayed on the display panel in a format to be displayed on the display to allow a display engine coupled to the display to stream the compressed final display surface writes to the display;wherein the final display surface writes of data stored in the memory include meta-data to indicate to the display engine whether the final display surface writes of the data are compressed in a Display Link format.2. The apparatus of claim 1 , wherein the final display surface writes are compressed in a Display Link format.3. The apparatus of claim 1 , wherein the final display surface writes are compressed in a format that does not require the display engine to uncompress or compress the final display surface writes.4. (canceled)5. The apparatus of claim 1 , wherein the processor includes a register bank to store display settings for the data to be provided to the display panel.6. The apparatus of claim 5 , wherein the display settings comprise display resolution claim 5 , pixel format claim 5 , an indication of whether Display Link compression is enabled claim 5 , or parameters for Display Link compression claim 5 , or a combination thereof.7. The apparatus of claim 5 , wherein a display driver is to send display settings to the register bank ...

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Номер записи: 87
18-10-2018 дата публикации

THREAD SERIALIZATION, DISTRIBUTED PARALLEL PROGRAMMING, AND RUNTIME EXTENSIONS OF PARALLEL COMPUTING PLATFORM

Номер: US20180300841A1
Автор: AMSTUTZ Jefferson, Appu Abhishek R., GUENTHER Johannes, Koker Altug, Kwiatkowski Jacek, Liktor Gabor, Ould-Ahmed-Vall Elmoustapha, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., WALD INGO
Принадлежит:

Systems, apparatuses, and methods may provide for technology to process graphical data, and to modify a runtime environment in a parallel computing platform for a graphic environment. 1. A graphics processing system , comprising:a display to visually present a rendering graphical image;a memory to store a set of instructions; and a substrate,', 'a host processor operatively coupled to the memory and the substrate, wherein when executed by the host processor, the set of instructions cause the host processor to execute a multi-threaded graphics platform, and', detect, in parallel to executing a plurality of threads of the multi-threaded graphics platform, a presence of one or more external graphics processors on a shared computer network; and', 'dynamically enable, in response to detecting the presence, parallel execution of a portion of the threads by the one or more remote graphics processors., 'a host graphics processor operatively coupled to the substrate, wherein the host graphics processor includes logic to], 'a semiconductor package apparatus operatively coupled to the memory and the display, the semiconductor package apparatus including2. The graphics processing system of claim 1 , wherein permitting parallel execution comprises dynamically distributing claim 1 , via the shared computer network claim 1 , a portion of the plurality of threads to the one or more remote graphics processors for parallel execution thereof.3. The graphics processing system of claim 1 , wherein permitting parallel execution of comprises permitting access claim 1 , by the one or more remote graphics processors via the shared computer network claim 1 , to a portion of the plurality of threads for parallel execution of a portion thereof.4. The graphics processing system of claim 1 , wherein the host graphics processor includes logic to:receive, via the shared computer network, computational work from the one or more remote graphics processors; andaggregate, in response to receiving the ...

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Номер записи: 88
18-10-2018 дата публикации

STEREOSCOPIC RENDERING WITH COMPRESSION

Номер: US20180300903A1
Автор: Appu Abhishek R., Bar-On Tomer, Burke Devan, DOYLE PETER L., Gierach John G., Koker Altug, Labbe Hugues, Lake Adam T., Laws Philip R., Ould-Ahmed-Vall Elmoustapha, Schluessler Travis T., SHAH ANKUR N., Xiao Kai
Принадлежит:

Systems, apparatuses, and methods may provide for technology to render and compress stereoscopic graphical data. In one example, the technology identifies, from graphical data associated with a stereoscopic image defined by a first perspective view and a second perspective view, a background region and a foreground region of a graphical scene in the stereoscopic image, renders graphical data of the identified background region for the first perspective view, and compresses the rendered graphical data. 1. A system , comprising:a display to visually present a rendered stereoscopic image defined by a first perspective view and a second perspective view;a memory to store a set of instructions; and a substrate,', 'a host processor coupled to the substrate, wherein when executed by the host processor, the set of instructions cause the host processor to generate a graphical scene associated with the stereoscopic image, and', identify, from graphical data, a background region and a foreground region of the graphical scene; and', 'render graphical data of the identified background region for the first perspective view, and compress the rendered graphical data., 'a graphics processor coupled to the substrate, wherein the graphics processor includes logic to], 'a semiconductor package apparatus coupled to the display and the memory, the semiconductor package apparatus including2. The system of claim 1 , wherein the graphics processor includes logic to render claim 1 , in parallel claim 1 , graphical data of the identified foreground region for the first perspective view and the second perspective view.3. The system of claim 1 , wherein the graphics processor includes logic to broadcast claim 1 , in response to rendering graphical data of the identified background region for the first perspective view claim 1 , the compressed graphical data to the second perspective view.4. The system of claim 3 , wherein broadcasting the rendered and compressed graphical data to the second ...

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Номер записи: 89
18-10-2018 дата публикации

CLOUD BASED DISTRIBUTED SINGLE GAME CALCULATION OF SHARED COMPUTATIONAL WORK FOR MULTIPLE CLOUD GAMING CLIENT DEVICES

Номер: US20180300930A1
Автор: Appu Abhishek R., Boles Jeffery S., GRAJEWSKI SLAWOMIR, KENNEDY Jonathan, Koker Altug, Kwiatkowski Jacek, Liktor Gabor, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., Vembu Balaji
Принадлежит:

Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices. 1. A computing system , comprising:a memory to store a set of instructions; and a substrate,', 'a host processor operatively coupled to the substrate, wherein when executed by the host processor, the set of instructions cause the host processor to execute a graphics application, and', 'a graphics processor operatively coupled to the substrate, wherein the graphics processor includes logic to:', 'identify, from graphics data in the graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users;', 'calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes; and', 'send, over a computer network, the calculation of the frame characteristics to the client game devices;, 'a cloud computing server coupled to the memory, the cloud server includinga display, operatively coupled to the cloud computing server, to visually present rendered visual content in a 3D virtual space.2. The system of claim 1 , wherein the graphics processor includes logic to detect claim 1 , prior to identifying redundant graphics calculations claim 1 , an initiation of a game session.3. The system of claim 1 , wherein the frame characteristics comprises frame ...

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Номер записи: 90
18-10-2018 дата публикации

AUGMENTED REALITY AND VIRTUAL REALITY FEEDBACK ENHANCEMENT SYSTEM, APPARATUS AND METHOD

Номер: US20180300940A1
Автор: Apodaca Michael, Baran Stanley J., Biswal Narayan, Boles Jeffery S., Cilingir Gokcen, DAS BARNAN, Feit John H., Feng Louis, Holland James M., Kaburlasos Nikos, KENNEDY Jonathan, Koker Altug, Kwiatkowski Jacek, Lake Adam T., Ray Joydeep, Sakthivel Chandrasekaran, Schluessler Travis T., Shah Nilesh V., SHARMA ARCHIE, Surti Prasoonkumar, Varerkar Mayuresh M., Xiao Kai
Принадлежит:

Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment. 1. A system comprising:a power source to supply power to the system;a memory comprising n-dimensional environment information, the memory coupled to a processor; and an observer monitor to monitor one or more actions of an observer observing the n-dimensional environment information, the environment information including feedback information;', 'a feedback manager to detect feedback information, wherein feedback information includes a priority relationship to the observer, wherein the priority relationship identifies one or more of observer directed feedback information directed to the observer or undirected feedback information;', 'a ray tracing engine to normalize the environment information, including normalize the feedback information, to a location of the observer, wherein the graphics pipeline apparatus renders the normalized feedback information based on one or more of the actions of the observer or the priority relationship of the feedback information to the observer., 'a graphics pipeline apparatus comprising2. The system of claim 1 , wherein the feedback manager attenuates one or more feedback devices based on one or more operating parameters claim 1 , wherein the feedback devices are coupled to the graphics pipeline apparatus claim 1 , wherein the feedback manager identifies the feedback information as known feedback information or unknown feedback information claim 1 , wherein the feedback manager requests unknown feedback identifier training claim 1 , when the unknown feedback information ...

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Номер записи: 91
18-10-2018 дата публикации

Adaptive tessellation for foveated rendering

Номер: US20180300951A1
Автор: Jacek Kwiatkowski, John H. Feit, Joydeep Ray, Nikos Kaburlasos, Prasoonkumar Surti, Travis T. Schluessler, Wenyin Fu
Принадлежит: Intel Corp

Methods and apparatus relating to techniques for adaptive tessellation for foveated rendering are described. In one embodiment, a first tessellation operation in a fovea region is performed in accordance with a first tessellation factor and a second tessellation operation in one or more regions surrounding the fovea region in accordance with a second tessellation factor. The first tessellation factor results in a finer tessellation than the second tessellation factor. Other embodiments are also disclosed and claimed.

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Номер записи: 92
18-10-2018 дата публикации

GRAPHICS WITH ADAPTIVE TEMPORAL ADJUSTMENTS

Номер: US20180301110A1
Автор: Appu Abhishek R., Burke Devan, Cimini David M., Feit John H., Feng Louis, Janczak Tomasz, Kaburlasos Nikos, Koker Altug, Kwiatkowski Jacek, Lauritzen Andrew T., Laws Philip R., Ould-Ahmed-Vall Elmoustapha, Ray Joydeep, Schluessler Travis T.
Принадлежит:

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed. 1. An electronic processing system , comprising:an application processor;persistent storage media communicatively coupled to the application processor;a graphics subsystem communicatively coupled to the application processor;an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter; anda sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition.2. The system of claim 1 , wherein the object space adjuster is further to adjust the object space parameter based on a detected screen space shading rate.3. The system of claim 1 , wherein the sample adjuster is further to adjust a sample rate based on a detected amount of motion.4. The system of claim 1 , wherein the sample adjuster is further to adjust a sample rate for a subsequent frame based on a detected sample rate hit information for one or more prior frames.5. The system of claim 1 , wherein the sample adjuster is further to adjust a sample pattern for a detected static object.6. A graphics apparatus claim 1 , comprising:a screen space condition detector to detect a screen space condition; andan object space adjuster communicatively coupled to the screen space condition detector to adjust an object space parameter based on the detected screen space condition.7. ...

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Номер записи: 93
25-10-2018 дата публикации

INTERCONNECT FABRIC LINK WIDTH REDUCTION TO REDUCE INSTANTANEOUS POWER CONSUMPTION

Номер: US20180307295A1
Автор: Appu Abhishek R., KENNEDY Jonathan, Koker Altug, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., Tameem Mohammed, Veernapu Kiran C.
Принадлежит: Intel Corporation

Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on the instantaneous throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on throughput demand from the client. 1. A parallel processor comprising:an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on a rate of data transfer requests associated with the client, the interconnect fabric including an ingress connection from the client and egress connection to the client.2. The parallel processor as in claim 1 , the dynamic bus module to configure a bus frequency for the client based on the rate of data transfer requests for the ingress connection to the client.3. The parallel processor as in claim 1 , the dynamic bus module to configure the bus width for the client based on the rate of data transfer requests for the ingress connection to the client.4. The parallel processor as in claim 1 , the dynamic bus module to configure the bus width for the client or the bus frequency for the client based on the rate of data transfer requests for the egress connection to the client.5. The parallel processor as in claim 1 , wherein each of the ingress connection and the egress connection include multiple connection links.6. The parallel processor as in claim 5 , wherein each of the multiple connection links include multiple connection lanes.7. The parallel processor as in claim 6 , wherein the bus width of each of the multiple connection links is an aggregate of the multiple connection lanes.8. The parallel processor as in claim 7 , wherein active bus width of each of the multiple connection links is an aggregate of active connection lanes.9. The ...

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Номер записи: 94
25-10-2018 дата публикации

GRAPHICS CONTROL FLOW MECHANISM

Номер: US20180307487A1
Автор: Appu Abhishek R., Burke Devan, Chandra Joy, Chen Gang, KENNEDY Jonathan, Koker Altug, Kommaraju Ananda V., Liao Hong Bin, Lueh Guei-yuan, Maiyuran Subramaniam M., Pal Supratim, Puffer David, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., Surti Prasoonkumar
Принадлежит:

An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels. 1. An apparatus to facilitate control flow in a graphics processing system comprising: a plurality of execution units to execute single instruction, multiple data (SIMD); and', 'flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels., 'a graphics processor, including2. The apparatus of claim 1 , wherein the flow control logic detects SIMD channels that are active and identifies a code region impacted by the diverging control flow.3. The apparatus of claim 2 , wherein the logic to detect the active SIMD channels detects whether the number of active SIMD channels is below a predetermined threshold percentage of the plurality of SIMD channels.4. The apparatus of claim 3 , wherein the flow control logic comprises packs input to the active SIMD channels into a subset of the SIMD channels upon a determination that the number of active SIMD channels is below the predetermined threshold percentage.5. The apparatus of claim 4 , wherein the logic to detect the active SIMD channels detects whether the active SIMD channels are spread over multiple SIMD sections.6. The apparatus of claim 5 , wherein the flow control logic prevents packing input to the active SIMD channels into a subset of the SIMD channels upon detecting that the active SIMD channels are not spread over multiple SIMD sections.7. The apparatus of claim 2 , wherein the logic to identify the code region duplicates the identified code region within the subset of the SIMD channels.8. The apparatus of claim 7 , wherein the subset of the SIMD channels ...

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Номер записи: 95
25-10-2018 дата публикации

DYNAMIC DISTRIBUTED TRAINING OF MACHINE LEARNING MODELS

Номер: US20180307984A1
Автор: Akhbari Farshad, Appu Abhishek R., BAGHSORKHI Sara S., Bottleson Jeremy, Chen Xiaoming, Gottschlich Justin E., Jahagirdar Sanjeev, KENNEDY Jonathan, Koker Altug, MA Liwei, Nealis Kevin, Nurvitadhi Eriko, Ould-Ahmed-Vall Elmoustapha, Ranganathan Vasanth, Ray Joydeep, Sakthivel Chandrasekaran, Satish Nadathur Rajagopalan, Schluessler Travis T., SHAH ANKUR N., Sinha Kamal, Surti Prasoonkumar, Vembu Balaji, Weast John C., Yao Anbang
Принадлежит: Intel Corporation

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed. 1. An apparatus comprising:a plurality of compute engines comprising logic, at least partially including hardware logic, to train a neural network; anda hardware engine to accelerate a weight update process for training the neural network.2. The apparatus of claim 1 , wherein:the hardware engine implements fast operations to average weights from a plurality of nodes in the neural network.3. The apparatus of claim 2 , wherein:the neural network comprises a plurality of sub-neural networks; andeach sub-neural network is trained separately.4. The apparatus of claim 3 , further comprising logic claim 3 , wherein:the plurality of sub-neural networks operate according to a priority.5. The apparatus of claim 4 , wherein:the output of a first sub-neural network may be provided as an input to a second sub-neural network.6. The apparatus of claim 1 , wherein:a decision making routine of the neural network executes on at least two different compute engines.7. The apparatus of claim 6 , further comprising logic claim 6 , at least partially including hardware logic claim 6 , to:compare results of the decision making routine executed on the at least two different compute engines.8. The apparatus of claim 7 , further comprising a driver comprising logic claim 7 , at least partially including hardware logic claim 7 , to:continue processing if the results of the decision making routine executed on the at least two different compute engines match.9. The apparatus of claim 8 , further comprising a thread scheduler comprising logic claim 8 , at least partially including hardware logic claim 8 , to: ...

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Номер записи: 96
25-10-2018 дата публикации

COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS

Номер: US20180308200A1
Автор: Akhbari Farshad, Appu Abhishek R., Ashbaugh Ben J., BAGHSORKHI Sara S., Barik Rajkishore, Boles Jeffery S., Burke Devan, Chen Feng, Feit John H., Fu Wenyin, Galoppo von Borries Nicolas C., Gottschlich Justin E., HURD LINDA L., Kim Dukhwan, Koker Altug, Lake Adam T., Lin Tsung-Han, Maiyuran Subramaniam, Mastronarde Josh B., Nurvitadhi Eriko, Ray Joydeep, Satish Nadathur Rajagopalan, Schluessler Travis T., Sinha Kamal, Srinivasa Narayan, Surti Prasoonkumar, Vaidyanathan Karthik, Vembu Balaji
Принадлежит:

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type 1. An apparatus to facilitate compute optimization , comprising:a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type.2. The apparatus of claim 1 , wherein the plurality of processing units comprise:a first processing unit including a plurality of EUs of the first type; anda second processing unit including a plurality of EUs of the second type.3. The apparatus of claim 1 , wherein the plurality of processing units comprise: a first set of EUs of the first type; and', 'a second set of EUs of the second type; and, 'a first processing unit including a third set of EUs of the first type; and', 'a fourth set of EUs of the second type., 'a second processing unit including4. The apparatus of claim 1 , further comprising compute logic to select the EUs that are to be implemented to execute a workload.5. The apparatus of claim 4 , wherein the compute logic selects the EUs of the first type to process a first type of application workload and selects the EUs of the second type to process a second type of application workload.6. The apparatus of claim 1 , further comprising a memory claim 1 , wherein the plurality of processing units are included in the memory.7. The apparatus of claim 6 , wherein the memory comprises a high bandwidth memory (HBM).8. The apparatus of claim 7 , wherein the HBM comprises:a first memory channel; anda first processing unit included in the first memory channel.9. The apparatus of claim 1 , further comprising a register file implemented to perform matrix-vector transformations.10. The apparatus of claim 1 , further comprising a shared local memory (SLM) implemented to perform matrix-vector ...

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Номер записи: 97
25-10-2018 дата публикации

COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS

Номер: US20180308206A1
Автор: Akhbari Farshad, Appu Abhishek R., Ashbaugh Ben J., BAGHSORKHI Sara S., Barik Rajkishore, Boles Jeffery S., Burke Devan, Chen Feng, Feit John H., Fu Wenyin, Galoppo von Borries Nicolas C., Gottschlich Justin E., HURD LINDA L., Kim Dukhwan, Koker Altug, Lake Adam T., Lin Tsung-Han, Maiyuran Subramaniam, Mastronarde Josh B., Nurvitadhi Eriko, Ray Joydeep, Satish Nadathur Rajagopalan, Schluessler Travis T., Sinha Kamal, Srinivasa Narayan, Surti Prasoonkumar, Vaidyanathan Karthik, Vembu Balaji
Принадлежит:

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels. 1. An apparatus to facilitate compute optimization , comprising: a first integrated circuit (IC) including a plurality of memory channels; and', 'a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels., 'a memory device including2. The apparatus of claim 1 , further comprising a plurality of high-speed interfaces coupled between each of the plurality of memory channels and the processing units.3. The apparatus of claim 2 , further comprising:a first memory channel;a first interface coupled to the first memory channel; anda first processing unit coupled to the first interface.4. The apparatus of claim 3 , further comprising a controller to facilitate access of the first memory channel by the first processing unit via the first interface to perform compute operations.5. The apparatus of claim 4 , wherein the controller further facilitates the storing of results of the compute operations to the first memory channel by the first processing unit.6. The apparatus of claim 5 , wherein the controller further facilitates the access of the compute operations results stored in the the first memory channel by a graphics processor.7. The apparatus of claim 2 , wherein the memory device comprises a high bandwidth memory (HBM).8. An integrated circuit (IC) package claim 2 , comprising:a first integrated circuit (IC) including a plurality of memory channels;a plurality of interfaces, each coupled to one of the plurality of memory channels anda second IC including a plurality of processing units, each coupled to one of the plurality of interfaces.9. The IC of claim 8 , further comprising a controller to ...

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Номер записи: 98
25-10-2018 дата публикации

COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS

Номер: US20180308208A1
Автор: Akhbari Farshad, Appu Abhishek R., Ashbaugh Ben J., BAGHSORKHI Sara S., Barik Rajkishore, Boles Jeffery S., Burke Devan, Chen Feng, Feit John H., Fu Wenyin, Galoppo von Borries Nicolas C., Gottschlich Justin E., HURD LINDA L., Kim Dukhwan, Koker Altug, Lake Adam T., Lin Tsung-Han, Maiyuran Subramaniam, Mastronarde Josh B., Nurvitadhi Eriko, Ray Joydeep, Satish Nadathur Rajagopalan, Schluessler Travis T., Sinha Kamal, Srinivasa Narayan, Surti Prasoonkumar, Vaidyanathan Karthik, Vembu Balaji
Принадлежит: Intel Corporation

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type 1. A graphics processing unit (GPU) comprising one or more multiprocessors , at least one of the one or more multiprocessors including:a register file to store operands;a first type of processing core to perform multi-dimensional matrix math operations on a first set of operands; anda second type of processing cores, different from the first type, to perform general purpose graphics processing unit (GPGPU) operations on a second set of operands.2. The GPU of claim 1 , wherein the at least one of the one or more multiprocessors further comprises a dispatch unit to dispatch first instructions for execution at the first type of processing core and to dispatch second instructions to the second type of processing cores.3. The GPU of claim 1 , wherein the second type of processing cores comprise:processing cores to execute operands to perform floating point operations; andprocessing cores to execute operands to perform integer operations.4. The GPU of claim 3 , wherein the processing cores to execute operands to perform floating point operations comprise:a first set of processing cores to execute 32-bit floating point (FP32) operands; anda second set of processing cores to execute 64-bit floating point (FP64) operands.5. The GPU of claim 4 , wherein the register file stores the first set of operands claim 4 , the operands to perform integer operation claim 4 , the FP32 operands and the FP64 operands.6. The GPU of claim 2 , wherein the at least one of the one or more multiprocessors further comprises an instruction cache to store the first instructions and the second instructions.7. The GPU of claim 1 , wherein the multi-dimensional matrix math operations comprise deep learning matrix operations.8. A method to facilitate the ...

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Номер записи: 99
25-10-2018 дата публикации

DISPLAY ENGINE SURFACE BLENDING AND ADAPTIVE TEXEL TO PIXEL RATIO SAMPLE RATE SYSTEM, APPARATUS AND METHOD

Номер: US20180308219A1
Автор: Appu Abhishek R., Feit John H., Kaburlasos Nikos, Kwiatkowski Jacek, Ray Joydeep, Schluessler Travis T., Surti Prasoonkumar, Vembu Balaji
Принадлежит:

Systems, apparatuses and methods may provide away to blend two or more of the scene surfaces based on the focus area and an offload threshold. More particularly, systems, apparatuses and methods may provide a way to blend, by a display engine, two or more of the focus area scene surfaces and blended non-focus area scene surfaces. The systems, apparatuses and methods may include a graphics engine to render the focus area surfaces at a higher sample rate than the non-focus area scene surfaces. 1. A system comprising:a power source to supply power to the system;a memory comprising a scene, the memory coupled to a processor; [ monitor a gaze of a user viewing the scene, and', 'identify a focus area in the scene based on the gaze of the user;, 'a gaze monitor to, 'a display engine to blend two or more of the scene surfaces based on the focus area; and, 'a graphics pipeline apparatus to receive the scene, the scene including scene surfaces, the graphics pipeline apparatus comprisinga graphics engine to offload computations by communicating to the display engine two or more of the scene surfaces when an offload threshold is satisfied, wherein the offload threshold is based at least in part on one or more performance factors.2. The system of claim 1 ,wherein the display engine converts the blended scene surfaces to a display resolution.3. The system of claim 2 , wherein a non-focus area identifies a portion of the scene outside the focus area claim 2 , wherein the scene surfaces include claim 2 , focus area scene surfaces and non-focus area scene surfaces claim 2 , wherein the focus area scene surfaces and non-focus area scene surfaces are displayed at different resolutions claim 2 , and wherein the display engine blends two or more of the non-focus area scene surfaces.4. The system of claim 3 , wherein the display engine blends two or more of the focus area scene surfaces and the blended non-focus area scene surfaces claim 3 , wherein the display engine renders the focus ...

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Номер записи: 100
25-10-2018 дата публикации

Low power foveated rendering to save power on gpu and/or display

Номер: US20180308266A1
Автор: Jacek Kwiatkowski, John H. Feit, Joydeep Ray, Nikos Kaburlasos, Prasoonkumar Surti, Travis T. Schluessler, Wenyin Fu
Принадлежит: Intel Corp

Methods and apparatus relating to techniques for provision of low power foveated rendering to save power on GPU (Graphics Processing Unit) and/or display are described. In various embodiment, brightness/contrast, color intensity, and/or compression ratio applied to pixels in a fovea region are different than those applied in regions surrounding the fovea region. Other embodiments are also disclosed and claimed.

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Номер записи: 101
25-10-2018 дата публикации

DEDICATED FIXED POINT BLENDING FOR ENERGY EFFICIENCY

Номер: US20180308272A1
Автор: Akiba Hiroshi, Appu Abhishek R., Dasgupta Subhajit, Hoekstra Eric J., HURD LINDA L., Mysore Srivallaba, Schluessler Travis T., Schmidt Daren J., Surti Prasoonkumar
Принадлежит:

Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API). The API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. The API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data. 1. An apparatus , comprising:a processor to receive an incoming data stream that includes alpha channel data; anda memory to store an application programming interface (API);wherein the API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data.2. The apparatus of claim 1 , wherein the API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data.3. The apparatus of claim 2 , wherein an output of the fixed point blending unit is combined with an output of the floating point blending unit.4. The apparatus of claim 2 , wherein the API is further to route the alpha channel data to the fixed point blending unit in a lower power mode claim 2 , and to route the alpha channel data to the floating point blending unit in a higher power mode.5. The apparatus of claim 1 , wherein the processor is to comprise one or more of: a Graphics Processing Unit (GPU) or a processor core claim 1 , or a combination thereof.6. The apparatus of claim 1 , wherein the fixed point blending unit comprises hardware claim 1 , software claim 1 , firmware claim 1 , or a combination thereof.7. A method claim 1 , comprising:receiving an incoming data stream that includes alpha channel data; androuting the alpha channel data to a fixed point blending unit ...

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Номер записи: 102
25-10-2018 дата публикации

POSITIONAL ONLY SHADING PIPELINE (POSH) GEOMETRY DATA PROCESSING WITH COARSE Z BUFFER

Номер: US20180308277A1
Автор: Apodaca Michael, Appu Abhishek R., Boles Jeffery S., Cimini David M., GRAJEWSKI SLAWOMIR, KENNEDY Jonathan, Koker Altug, Kp Sameer, Kuwahara Atsuo, Labbe Hugues, Lauritzen Andrew T., Liktor Gabor, Ramadoss Murali, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., Surti Prasoonkumar, Vaidyanathan Karthik, Vembu Balaji, Venkatesh Abhishek, Xiao Kai
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The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones. 1. A system comprising:a power source to supply power to the system; position geometry data, the geometry data including surface triangles for a digital representation of a scene;', 'perform a screen space transformation; and', 'cull at least one of the surface triangles; and, 'a positional only shading pipeline to, 'a graphics pipeline apparatus comprisinga render pipe to render the surface triangles remaining following the culling.2. The system of claim 1 , wherein the positional only shading pipeline identifies the at least one of the surface triangles culled as exclusion triangles and the surface triangles remaining following the culling as non-exclusion triangles claim 1 , wherein the surface triangles identified as exclusion triangles include at least a portion of the surface triangles in one or more exclusion zones claim 1 , and wherein the surface triangles identified as non-exclusion triangles include the surface triangles in one or more non-exclusion zones.3. The system of claim 2 , wherein the non-exclusion zones and non-exclusion zones are sized based on culling parameters claim 2 , and wherein the culling parameters include one or more of lens parameters for depth perception of near plans and far plans claim 2 , performance parameters claim 2 , head mounted display parameters or other device parameters.4. The system of claim 3 , wherein the graphics pipeline apparatus exposes the surface triangles to a vertex shader claim 3 , ...

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Номер записи: 103
25-10-2018 дата публикации

FIELD RECOVERY OF GRAPHICS ON-DIE MEMORY

Номер: US20180308561A1
Автор: Appu Abhishek R., KENNEDY Jonathan, Koker Altug, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N.
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Systems, apparatuses and methods may provide for technology that identifies a redundant portion of a packaged on-die memory and detects, during a field test of the packaged on-die memory, one or more failed cells in the packaged on-die memory. Additionally, one or more memory cells in the redundant portion may be substituted for the one or more failed memory cells. 1. A system comprising:a display;a power supply to provide power to the system; anda semiconductor package apparatus including a substrate, an on-die memory coupled to the substrate, the on-die memory including a redundant portion, and logic coupled to the substrate, wherein the logic is implemented in one or more of configurable logic or fixed-functionality hardware logic, the logic to:identify the redundant portion of the on-die memory,detect, during a field test of the on-die memory, one or more failed memory cells in the on-die memory, andsubstitute one or more memory cells in the redundant portion for the one or more failed memory cells.2. The system of claim 1 , wherein the logic is to program a fuse override to a permanent data structure to substitute the one or memory cells in the redundant portion for the one or more failed memory cells.3. The system of claim 1 , wherein the field test is to include a built-in self-test process.4. The system of claim 1 , wherein the logic is to execute the field test in response to one or more of a periodic timer expiration claim 1 , a power down condition claim 1 , a power up condition or an idleness condition.5. The system of claim 1 , wherein redundant portion includes one or more of redundant rows or redundant columns.6. The system of claim 1 , wherein the on-die memory includes one or more of a graphics cache or a graphics register file.7. An apparatus comprising:a substrate;an on-die memory coupled to the substrate, the on-die memory including a redundant portion; andlogic coupled to the substrate, wherein the logic is implemented in one or more of ...

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Номер записи: 104
25-10-2018 дата публикации

SYNERGISTIC TEMPORAL ANTI-ALIASING AND COARSE PIXEL SHADING TECHNOLOGY

Номер: US20180309969A1
Автор: Apodaca Michael, Feit John H., Kaburlasos Nikos, Kwiatkowski Jacek, Ramadoss Murali, Ray Joydeep, Schluessler Travis T., Surti Prasoonkumar, Vaidyanathan Karthik, Venkatesh Abhishek
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Systems, apparatuses and methods may provide for technology that determines a frame rate of video content, sets a blend amount parameter based on the frame rate, and temporally anti-aliases the video content based on the blend amount parameter. Additionally, the technology may detect a coarse pixel (CP) shading condition with respect to one or more frames in the video content and select, in response to the CP shading condition, a per frame jitter pattern that jitters across pixels, wherein the video content is temporally anti-aliased based on the per frame jitter pattern. The CP shading condition may also cause the technology to apply a gradient to a plurality of color planes on a per color plane basis and discard pixel level samples associated with a CP if all mip data corresponding to the CP is transparent or shadowed out. 1. A system comprising:a substrate; andlogic coupled to the substrate, wherein the logic is implemented in one or more of configurable logic or fixed-functionality hardware logic, the logic to:determine a frame rate of video content,set a blend amount parameter based on the frame rate, andtemporally anti-alias the video content based on the blend amount parameter.2. The system of claim 1 , wherein the logic is to:increase the blend amount parameter if the frame rate does not exceed a first threshold, anddecrease the blend amount parameter if the frame rate exceeds a second threshold, wherein the second threshold is greater than or equal to the first threshold.3. The system of claim 1 , wherein the logic is to:detect a coarse pixel shading condition with respect to one or more frames in the video content, andselect, in response to the coarse pixel shading condition, a per frame jitter pattern that jitters across pixels, wherein the video content is to be temporally anti-aliased based on the per frame jitter pattern.4. The system of claim 3 , wherein the logic is to:identify one or more viewports in the video content, andadd a one-pixel guard band ...

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Номер записи: 105
25-10-2018 дата публикации

AUGMENTED REALITY VIRTUAL REALITY RAY TRACING SENSORY ENHANCEMENT SYSTEM, APPARATUS AND METHOD

Номер: US20180310113A1
Автор: Appu Abhishek R., Baran Stanley J., Biswal Narayan, Boles Jeffery S., Cilingir Gokcen, DAS BARNAN, Feit John H., Feng Louis, Holland James M., Kaburlasos Nikos, KENNEDY Jonathan, Kuwahara Atsuo, Kwiatkowski Jacek, Ray Joydeep, Schluessler Travis T., Shah Nilesh V., SHARMA ARCHIE, Surti Prasoonkumar, Varerkar Mayuresh M.
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Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience. 1. A system comprising:a power source to supply power to the system;a memory comprising environment information, the memory coupled to a processor; and normalize the environment information to a position of an observer to generate normalized environment information for the observer;', 'calculate, for the observer, the sound sources or sensed events vector paths;', 'generate a number of ray bundles for the sounds, the ray bundles including a number of frequency bands based on acoustic properties of one or more of the sound sources, wherein the environment information is further to include one or more objects or surfaces in the path of one or more of the vector paths, and wherein the ray bundles are to be based on one or more of the acoustic properties of the sound, the objects, or the surfaces;', 'apply an absorption filter, an attenuation filter, and a reflective filter to the normalized environment information, based on the vector path attributes of the sound or the sensed events; and', 'play back the normalized environment information to the observer based on the vector paths., 'a ray tracing engine to, 'a graphics pipeline apparatus comprising2. The system of claim 1 , wherein the vector paths include vector path attributes including one more of positional information or directional information claim 1 , wherein the environment information is captured by one or more capture devices ...

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Номер записи: 106
22-10-2020 дата публикации

POSITIONAL ONLY SHADING PIPELINE (POSH) GEOMETRY DATA PROCESSING WITH COARSE Z BUFFER

Номер: US20200334896A1
Автор: Apodaca Michael, Appu Abhishek R., Boles Jeffery S., Cimini David M., GRAJEWSKI SLAWOMIR, KENNEDY Jonathan, Koker Altug, Kp Sameer, Kuwahara Atsuo, Labbe Hugues, Lauritzen Andrew T., Liktor Gabor, Ramadoss Murali, Ray Joydeep, Schluessler Travis T., SHAH ANKUR N., Surti Prasoonkumar, Vaidyanathan Karthik, Vembu Balaji, Venkatesh Abhishek, Xiao Kai
Принадлежит:

The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones. 1. (canceled)2. A graphics processing unit comprising: compute a position of geometry data, the geometry data including surface triangles for a digital representation of a scene;', 'cull at least one of the surface triangles;', 'identify the at least one of the surface triangles culled as exclusion triangles and the surface triangles remaining following the culling as non-exclusion triangles, wherein the surface triangles identified as exclusion triangles include at least a portion of the surface triangles in one or more exclusion zones, and wherein the surface triangles identified as non-exclusion triangles include the surface triangles in one or more non-exclusion zones;', 'adjust a granularity setting for the exclusion zones or the non-exclusion zones based on a position of one or more of the surface triangles, lens parameters for depth perception, or attributes of stream out data, wherein the attributes of the stream out data include one or more of granularity of the stream out data, motion or direction of one or more objects or a gaze of a user; and', 'based on the adjustment of the granularity setting for the exclusion zones or the non-exclusion zones, expose the stream out data to a vertex shader., 'a processor to3. The graphics processing unit of claim 2 , wherein the processor is further to:create a coarse Z buffer while processing the geometry data, andstore one or more of the surface triangles in a coarse Z order as coarse Z ...

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Номер записи: 107