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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 174. Отображено 104.
29-12-2016 дата публикации

OPTIMIZED WIRES FOR RESISTANCE OR ELECTROMIGRATION

Номер: US20160379877A1
Автор: Lawrence A. CLEVENGER, Baozhen LI, Kirk D. PETERSON, CLEVENGER LAWRENCE A, LI BAOZHEN, PETERSON KIRK D, CLEVENGER Lawrence A., LI Baozhen, PETERSON Kirk D.
Принадлежит:

Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes depositing metal material within openings and on a surface of dielectric material resulting in metal filled openings and a topography of recessed areas aligned with the metal filled openings. The method further includes depositing an alloying material over the metal material, including within the recessed areas. The method further includes planarizing the metal material, leaving the alloying material within the recessed areas. The method further includes diffusing the alloying material into the metal material forming alloyed regions self-aligned with the metal filled openings. 1. A method , comprising:determining whether metal lines are to need electromigration resistance;assigning a shape of the metal lines that require electromigration resistance;constructing a mask for the shape; anddetermining timing for the assigned shape of the metal lines.2. The method of claim 1 , wherein the shape of the metal line is provided by constructing a new mask for forming an opening in a capping layer.3. The method of claim 1 , wherein each metal line is analyzed for electromigration (EM) concerns for low resistance case.4. The method of claim 3 , wherein the analyzing is provided by a circuit analysis.5. The method of claim 4 , wherein the circuit analysis comprises supplying a current to each metal line and determining whether the current is less than an EM threshold.6. The method of claim 5 , wherein when the metal lines pass the circuit analysis claim 5 , the metal line will remain low resistance and the timing will be closed with this condition.7. The method of claim 6 , wherein when the metal lines fail the circuit analysis claim 6 , a new design shape is added to the metal lines to construct a mask.8. The method of claim 7 , further comprising controlling out diffusion of material into a copper line to adjust the alloying ...

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Номер записи: 1
02-02-2017 дата публикации

DETERMINISTIC CURRENT BASED FREQUENCY OPTIMIZATION OF PROCESSOR CHIP

Номер: US20170031415A1
Автор: Malcolm S. ALLEN-WARE, Michael S. FLOYD, Joshua D. FRIEDRICH, Charles R. LEFURGY, Kirk D. PETERSON, Karthick RAJAMANI, Srinivasan RAMANI, Todd J. ROSEDAHL, Gregory S. STILL, Brian W. THOMPTO, Victor ZYUBAN, ALLEN-WARE MALCOLM S, FLOYD MICHAEL S, FRIEDRICH JOSHUA D, LEFURGY CHARLES R, PETERSON KIRK D, RAJAMANI KARTHICK, RAMANI SRINIVASAN, ROSEDAHL TODD J, STILL GREGORY S, THOMPTO BRIAN W, ZYUBAN VICTOR, ALLEN-WARE Malcolm S., FLOYD Michael S., FRIEDRICH Joshua D., LEFURGY Charles R., PETERSON Kirk D., RAJAMANI Karthick, RAMANI Srinivasan, ROSEDAHL Todd J., STILL Gregory S., THOMPTO Brian W., ZYUBAN Victor
Принадлежит:

A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory, where the memory includes a program configured to adjust a frequency of a multi-core processor. The operations include determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The operations also include calculating a switching current by subtracting the leakage current from the total current and calculating an effective switching capacitance based at least in part on the switching current. The operations also include calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor. 18-. (canceled)9. A system , comprising:a processor; anda memory, wherein the memory includes a program configured to adjust a frequency of a multi-core processor, the operations comprising:determining a total current and a temperature of the multi-core processor;estimating a leakage current for the multi-core processor;calculating a switching current by subtracting the leakage current from the total current;calculating an effective switching capacitance based at least in part on the switching current;calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data; andenforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.10. The system of claim 9 , wherein estimating the leakage current comprises using vital product data to estimate the leakage current for a voltage and temperature condition.11. The system of claim 10 , wherein estimating the leakage current further comprises adjusting the leakage current for a number of active cores of the ...

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Номер записи: 2
17-01-2019 дата публикации

PHOTODIODE STRUCTURES

Номер: US20190019914A1
Автор: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON, ELLIS-MONAGHAN JOHN J, GAMBINO JEFFREY P, JAFFE MARK D, PETERSON KIRK D, ELLIS-MONAGHAN, John J., GAMBINO, Jeffrey P., JAFFE, Mark D., PETERSON, Kirk D.
Принадлежит:

Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material. 1. A method comprising forming an amorphous Ge material over a waveguide structure in a back end of line (BEOL) metal layer comprising depositing a metal layer on the amorphous Ge material through an opening of a via and crystallizing the amorphous Ge material through the annealing process to form the crystalline Ge structure aligned with the via.2. The method of claim 1 , wherein the amorphous Ge material is formed over an upper surface the waveguide structure in the BEOL metal layer.3. The method of claim 1 , wherein the annealing process is at about 350° C. to 420° C.4. The method of claim 1 , wherein the crystallizing the amorphous Ge material into the crystalline Ge structure is performed by the annealing process with a metal layer in contact with the Ge material.5. The method of claim 1 , wherein the forming of the amorphous Ge material is adjacent to the waveguide structure in the BEOL metal layer and comprises:depositing a barrier layer of nitride directly on the upper surface of the waveguide structure, followed by a patterning of the barrier layer;depositing the amorphous Ge material directly on the barrier layer, followed by a patterning of the amorphous Ge material;depositing the metal layer on the amorphous Ge material through the opening of the via; andcrystallizing of the amorphous Ge material through the annealing process to form the crystalline Ge structure aligned with the via.6. The method claim 5 , wherein the metal layer is a metal seed layer formed in direct contact with the amorphous Ge material ...

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Номер записи: 3
09-06-2016 дата публикации

OPTIMIZED WIRES FOR RESISTANCE OR ELECTROMIGRATION

Номер: US20160163651A1
Автор: Lawrence A. CLEVENGER, Baozhen LI, Kirk D. PETERSON, CLEVENGER LAWRENCE A, LI BAOZHEN, PETERSON KIRK D, CLEVENGER LAWRENCE A., PETERSON KIRK D.
Принадлежит:

Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes depositing metal material within openings and on a surface of dielectric material resulting in metal filled openings and a topography of recessed areas aligned with the metal filled openings. The method further includes depositing an alloying material over the metal material, including within the recessed areas. The method further includes planarizing the metal material, leaving the alloying material within the recessed areas. The method further includes diffusing the alloying material into the metal material forming alloyed regions self-aligned with the metal filled openings. 1. A method comprising:depositing metal material within openings and on a surface of dielectric material resulting in metal filled openings and a topography of recessed areas aligned with the metal filled openings;depositing an alloying material over the metal material, including within the recessed areas;planarizing the metal material, leaving the alloying material within the recessed areas; anddiffusing the alloying material into the metal material forming alloyed regions self-aligned with the metal filled openings.2. The method of claim 1 , wherein the openings in the dielectric material are formed by a dual damascene process.3. The method of claim 1 , wherein the metal filled openings are via interconnects and wiring structures.4. The method of claim 3 , wherein the depositing of the metal material is a an electroplating deposition.5. The method of claim 4 , wherein the deposition is a copper electroplating bath resulting in the openings being filled with copper material.6. The method of claim 5 , wherein the alloying material is a film of Mn.7. The method of claim 5 , wherein the alloying material is one of Mn claim 5 , Al claim 5 , Co claim 5 , Sn claim 5 , Pd claim 5 , C claim 5 , Ca claim 5 , Mg claim 5 , and Hf.8. The method of claim 1 ...

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Номер записи: 4
06-09-2018 дата публикации

PHOTODIODE STRUCTURES

Номер: US20180254374A1
Автор: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON, ELLIS-MONAGHAN JOHN J, GAMBINO JEFFREY P, JAFFE MARK D, PETERSON KIRK D, ELLIS-MONAGHAN, John J., GAMBINO, Jeffrey P., JAFFE, Mark D., PETERSON, Kirk D.
Принадлежит: International Business Machines Corp

Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

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Номер записи: 5
17-03-2016 дата публикации

PHOTODIODE STRUCTURES

Номер: US20160079451A1
Автор: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON
Принадлежит: International Business Machines Corp

Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

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Номер записи: 6
04-05-2017 дата публикации

PHOTODIODE STRUCTURES

Номер: US20170125626A1
Автор: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON, ELLIS-MONAGHAN JOHN J, GAMBINO JEFFREY P, JAFFE MARK D, PETERSON KIRK D, ELLIS-MONAGHAN John J., GAMBINO Jeffrey P., JAFFE Mark D., PETERSON Kirk D.
Принадлежит:

Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material. 1. A method , comprising:forming a waveguide structure in a dielectric layer;forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer; andcrystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.2. The method of claim 1 , wherein the low temperature annealing process is at about 350° C. to 420° C.3. The method claim 2 , wherein the metal layer is a metal seed layer formed in direct contact with the Ge material within a via formed to expose a surface of the Ge material claim 2 , the low temperature annealing is performed after deposition of the metal seed layer is formed in direct contact with the Ge material claim 2 , within the via of the dielectric layer.4. The method of claim 1 , wherein the metal layer is a metal seed layer of Ni in contact with the Ge material.5. The method of claim 1 , wherein the metal layer is a germanide or a eutectic.6. The method of claim 1 , wherein any unreacted metal layer is removed after the low temperature annealing process.7. The method of claim 1 , wherein the metal layer is a metal seed layer deposited in a via and on a surface of the Ge material.8. The method of claim 1 , wherein the metal layer is a metal seed layer deposited in two vias in a dielectric material composing BEOL wiring layers claim 1 , offset from a center of the Ge material.9. The method of claim 1 , wherein the metal layer is a metal seed layer deposited in one of at least ...

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Номер записи: 7
07-07-2022 дата публикации

PREDETERMINING SEPARATE THERMAL CONTROL POINTS FOR CHIPS OF A MULTI-CHIP MODULE

Номер: US20220214728A1
Автор: Eric MARZ, Kirk D. PETERSON, Greg ABRAMI, Howard V. MAHANEY, Jr., William James ANDERL, Eric Jason FLUHR, Todd Jon ROSEDAHL
Принадлежит:

Thermal control of a multi-chip module in an operating environment is facilitated by predetermining separate thermal control points for multiple chips of the multi-chip module, with a first chip and a second chip having different predetermined thermal control points, and saving the predetermined thermal control points for reference by a thermal control of the multi-chip module in an operating environment. The thermal control monitors an operating temperature of the first chip, and compares the operating temperature of the first chip to the predetermined thermal control point of that chip. The thermal control further initiates a control action to control temperature of the first chip based on comparing the operating temperature of the first chip to the predetermined thermal control point of the first chip.

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Номер записи: 8
07-04-2011 дата публикации

STRUCTURE AND METHOD TO CREATE A DAMASCENE LOCAL INTERCONNECT DURING METAL GATE DEPOSITION

Номер: US20110079827A1
Автор: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Kirk D. PETERSON, Jed H. RANKIN, Robert R. ROBISON
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method and structure to create damascene local interconnect during metal gate deposition. A method includes: forming a gate dielectric on an upper surface of a substrate; forming a mandrel on the gate dielectric; forming an interlevel dielectric (ILD) layer on a same level as the mandrel; forming a trench in the ILD layer; removing the mandrel; and forming a metal layer on the gate dielectric and in the trench.

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Номер записи: 9
15-03-2018 дата публикации

PHOTODIODE STRUCTURES

Номер: US20180076351A1
Автор: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON
Принадлежит:

Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material. 1. A structure , comprising:a waveguide structure in a dielectric material;a single crystalline Ge structure formed in proximity to the waveguide structure;an underlying metal layer; andan interconnect structure connecting the underlying metal layer to the single crystalline Ge structure.2. The structure of claim 1 , further comprising at least one metal filled via in electrical contact with Ge material of the single crystalline Ge structure.3. The structure of claim 1 , wherein at least one capping layer is between the at least one metal filled via and the Ge material.4. The structure of claim 1 , wherein the single crystalline Ge structure is adjacent to the waveguide structure.5. The structure of claim 1 , wherein the single crystalline Ge structure is a photodector.6. The structure of claim 1 , wherein the single crystalline Ge structure is a photodector above the waveguide structure.7. The structure of claim 1 , wherein the single crystalline Ge structure is a photodector adjacent to the waveguide structure.8. The structure of claim 1 , wherein further comprising a barrier layer between the single crystalline Ge structure and the waveguide structure.9. The structure of claim 8 , wherein the barrier layer is nitride.10. The structure of claim 1 , further comprising lined vias and trenches in the dielectric material claim 1 , over the single crystalline Ge structure.11. The structure of claim 10 , wherein the lined vias and trenches are a nickel seed layer.12. The structure of claim 10 , wherein the lined vias and ...

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Номер записи: 10
29-05-2014 дата публикации

LIGHT ACTIVATED TEST CONNECTIONS

Номер: US20140145747A1
Автор: Nathaniel R. CHADWICK, John B. DEFORGE, John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Ezra D. HALL, Marc D. KNOX, Kirk D. PETERSON, CHADWICK NATHANIEL R, DEFORGE JOHN B, ELLIS-MONAGHAN JOHN J, GAMBINO JEFFREY P, HALL EZRA D, KNOX MARC D, PETERSON KIRK D, CHADWICK NATHANIEL R., DEFORGE JOHN B., ELLIS-MONAGHAN JOHN J., GAMBINO JEFFREY P., HALL EZRA D., KNOX MARC D., PETERSON KIRK D.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A test circuit including a light activated test connection in a semiconductor device is provided. The light activated test connection is electrically conductive during a test of the semiconductor device and is electrically non-conductive after the test. 1. A semiconductor structure , comprising:a test circuit comprising a light activated test connection in a semiconductor device, wherein the light activated test connection is electrically conductive during a test of the semiconductor device and is electrically non-conductive after the test.2. The structure of claim 1 , wherein the light activated test connection is converted from a non-conductive state to a conductive state by applying light.3. The structure of claim 1 , wherein the test circuit is between two through silicon vias in the semiconductor device.4. The structure of claim 3 , wherein the light activated test connection is structured and arranged as a switch between the two through silicon vias.5. The structure of claim 1 , wherein the semiconductor device is a single chip of a three dimensional stacked chip system.6. The structure of claim 1 , wherein the light activated test connection is composed of a material having a bandgap substantially less than that of silicon.7. The structure of claim 1 , wherein the semiconductor device comprises:an integrated circuit device formed in silicon; andat least one of an opaque structure and an isolation structure between the integrated circuit device and the light activated test connection.8. A method of testing an integrated circuit chip claim 1 , comprising:closing a test circuit in the chip by applying light to a light activated test connection in the chip;applying a test signal to the test circuit while the test circuit is closed; andopening the test circuit by removing the light from the light activated test connection in the chip after the applying the test signal.9. The method of claim 8 , wherein:the chip is in a wafer that is connected to a handler wafer ...

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Номер записи: 11
02-02-2017 дата публикации

DETERMINISTIC CURRENT BASED FREQUENCY OPTIMIZATION OF PROCESSOR CHIP

Номер: US20170031417A1
Автор: Malcolm S. ALLEN-WARE, Michael S. FLOYD, Joshua D. FRIEDRICH, Charles R. LEFURGY, Kirk D. PETERSON, Karthick RAJAMANI, Srinivasan RAMANI, Todd J. ROSEDAHL, Gregory S. STILL, Brian W. THOMPTO, Victor ZYUBAN, ALLEN-WARE MALCOLM S, FLOYD MICHAEL S, FRIEDRICH JOSHUA D, LEFURGY CHARLES R, PETERSON KIRK D, RAJAMANI KARTHICK, RAMANI SRINIVASAN, ROSEDAHL TODD J, STILL GREGORY S, THOMPTO BRIAN W, ZYUBAN VICTOR, ALLEN-WARE Malcolm S., FLOYD Michael S., FRIEDRICH Joshua D., LEFURGY Charles R., PETERSON Kirk D., RAJAMANI Karthick, RAMANI Srinivasan, ROSEDAHL Todd J., STILL Gregory S., THOMPTO Brian W., ZYUBAN Victor
Принадлежит:

A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The method also includes calculating a switching current by subtracting the leakage current from the total current. The method also includes calculating an effective switching capacitance based at least in part on the switching current. The method also includes calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor. 1. A method for adjusting a frequency of a multi-core processor , comprising:determining a total current and a temperature of the multi-core processor;estimating a leakage current for the multi-core processor;calculating a switching current by subtracting the leakage current from the total current;calculating an effective switching capacitance based at least in part on the switching current;calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data; andenforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.2. The method of claim 1 , wherein estimating the leakage current comprises using vital product data to estimate the leakage current for a voltage and temperature condition.3. The method of claim 2 , wherein estimating the leakage current further comprises adjusting the leakage current for a number of active cores of the multi-core processor.4. The method of claim 1 , wherein calculating a switching current further comprises normalizing the switching current to a predetermined thermal design point switching current.5. The method of claim 1 , ...

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Номер записи: 12
09-07-2015 дата публикации

SHIELDING STRUCTURES BETWEEN OPTICAL WAVEGUIDES

Номер: US20150192735A1
Автор: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON, Jed H. RANKIN
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Methods and structures for shielding optical waveguides are provided. A method includes forming a first optical waveguide core and forming a second optical waveguide core adjacent to the first optical waveguide core. The method also includes forming an insulator layer over the first optical waveguide core and the second optical waveguide core. The method further includes forming a shielding structure in the insulator layer between the first optical waveguide core and the second optical waveguide core.

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Номер записи: 13
19-12-2019 дата публикации

PHOTODIODE STRUCTURES

Номер: US20190386168A1
Автор: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON, ELLIS-MONAGHAN JOHN J, GAMBINO JEFFREY P, JAFFE MARK D, PETERSON KIRK D, ELLIS-MONAGHAN, John J., GAMBINO, Jeffrey P., JAFFE, Mark D., PETERSON, Kirk D.
Принадлежит:

Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material. 1. A method of forming a semiconductor structure , comprising:forming a barrier layer in direct contact with both a single crystalline Ge structure and a waveguide structure, wherein the barrier layer is a different material than a dielectric material which covers the waveguide structure, the single crystalline Ge structure, an underlying metal layer, an interconnect structure and the barrier layer.2. The method of claim 1 , further comprising forming at least one metal filled via in electrical contact with Ge material of the single crystalline Ge structure.3. The method of claim 2 , wherein at least one capping layer is between the at least one metal filled via and the Ge material.4. The method of claim 1 , wherein the single crystalline Ge structure is adjacent to the waveguide structure.5. The method of claim 1 , wherein the single crystalline Ge structure is a photodetector.6. The method of claim 1 , wherein the single crystalline Ge structure is a photodetector above the waveguide structure.7. The method of claim 1 , wherein the single crystalline Ge structure is a photodetector adjacent to the waveguide structure.8. The method of claim 1 , wherein the interconnect structure connects the underlying metal layer to the single crystalline Ge structure.9. The method of claim 1 , wherein the barrier layer is nitride.10. The method of claim 1 , further comprising forming lined vias and trenches in the dielectric material claim 1 , over the single crystalline Ge structure.11. The method of claim 10 , wherein the lined vias ...

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Номер записи: 14
13-08-2015 дата публикации

STRESS BALANCING OF CIRCUITS

Номер: US20150228357A1
Автор: Igor ARSOVSKI, Nathaniel R. CHADWICK, John B. DEFORGE, Ezra D.B. HALL, Kirk D. PETERSON
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Methods, systems, and structures for stress balancing field effect transistors subject to bias temperature instability-caused threshold voltage shifts. A method includes characterizing fatigue of a location in a memory array by skewing a bit line voltage of the location. The method also includes determining that the location is unbalanced based on the characterizing. Further, the method includes inverting a logic state of the location. Additionally, the method includes changing a value of an inversion indicator corresponding to the location.

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Номер записи: 15
25-04-2019 дата публикации

SHIELDING STRUCTURES BETWEEN OPTICAL WAVEGUIDES

Номер: US20190121022A1
Автор: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON, Jed H. RANKIN, ELLIS-MONAGHAN JOHN J, GAMBINO JEFFREY P, JAFFE MARK D, PETERSON KIRK D, RANKIN JED H, ELLIS-MONAGHAN, John J., GAMBINO, Jeffrey P., JAFFE, Mark D., PETERSON, Kirk D., RANKIN, Jed H.
Принадлежит:

Methods and structures for shielding optical waveguides are provided. A method includes forming a first optical waveguide core and forming a second optical waveguide core adjacent to the first optical waveguide core. The method also includes forming an insulator layer over the first optical waveguide core and the second optical waveguide core. The method further includes forming a shielding structure in the insulator layer between the first optical waveguide core and the second optical waveguide core. 1. An optical waveguide device , comprising:a first optical waveguide core on an insulator layer;a second optical waveguide core adjacent to the first optical waveguide core;an upper insulator layer over the first optical waveguide core and the second optical waveguide core; anda shielding structure in the upper insulator layer between the first optical waveguide core and the second optical waveguide core, wherein the shielding structure comprises a reflective material in a trench in the upper insulator layer.2. The device of claim 1 , wherein the reflective material is a metal comprising one of. tungsten (W) claim 1 , Aluminum (Al) or Copper (Cu).3. The device of claim 1 , wherein the reflective material is a highly reflective material.4. The device of claim 3 , wherein the first optical waveguide core and the second optical waveguide core comprise silicon.5. The device of claim 4 , wherein the highly reflective material is a material having an optical reflectivity of at least 50% at a wavelength of light propagated in the first optical waveguide core and in the second optical waveguide core.6. The device of claim 1 , wherein the shielding structure extends into the insulator layer lower than bottom surfaces of the first optical waveguide core and the second optical waveguide core.7. An optical waveguide device claim 1 , comprising:a first optical waveguide core on an insulator layer;a second optical waveguide core adjacent to the first optical waveguide core;an upper ...

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Номер записи: 16
30-04-2015 дата публикации

ENCAPSULATED SENSORS

Номер: US20150115270A1
Автор: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, William J. MURPHY, Kirk D. PETERSON, Steven M. SHANK, ELLIS-MONAGHAN JOHN J, GAMBINO JEFFREY P, JAFFE MARK D, MURPHY WILLIAM J, PETERSON KIRK D, SHANK STEVEN M, ELLIS-MONAGHAN JOHN J., GAMBINO JEFFREY P., JAFFE MARK D., MURPHY WILLIAM J., PETERSON KIRK D., SHANK STEVEN M.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

An encapsulated sensors and methods of manufacture are disclosed herein. The method includes forming an amorphous or polycrystalline material in contact with a layer of seed material. The method further includes forming an expansion space for the amorphous or polycrystalline material. The method further includes forming an encapsulation structure about the amorphous or polycrystalline material. The method further includes crystallizing the amorphous or polycrystalline material by a thermal anneal process such that the amorphous or polycrystalline material expands within the expansion space. 1. A method , comprising:forming an amorphous or polycrystalline material in contact with a layer of seed material;forming an expansion space for the amorphous or polycrystalline material;forming an encapsulation structure about the amorphous or polycrystalline material; andcrystallizing the amorphous or polycrystalline material by a thermal anneal process such that the amorphous or polycrystalline material expands within the expansion space.2. The method of claim 1 , wherein the forming of the expansion space comprises forming voids between polysilicon structures formed on an underlying encapsulating layer of the encapsulation structure claim 1 , wherein: depositing polysilicon material on the underlying encapsulating layer; and', 'patterning the polysilicon material to have a minimal spacing therebetween; and, 'the forming of the polysilicon structures comprisesthe forming of the voids comprises depositing the amorphous or polycrystalline material over the polysilicon structures, which only partly fills the minimum spacing.3. The method of claim 1 , wherein the forming of the expansion space comprises forming voids within trenches formed in an underlying active silicon material claim 1 , wherein: exposing the underlying active silicon material by etching an opening in a first encapsulating layer which partly forms the encapsulation structure; and', 'etching the exposed ...

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Номер записи: 17
21-11-2019 дата публикации

PHOTODIODE STRUCTURES

Номер: US20190355865A1
Автор: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON
Принадлежит:

Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material. 1. A method , comprising:forming a waveguide structure in a dielectric material and which is located above metal wirings;forming a single crystalline Ge structure formed in the dielectric material and separated from the waveguide structure in the dielectric material by a barrier layer directly in contact with both the single crystalline Ge structure and the waveguide structure and completely separating the single crystalline Ge structure from the waveguide structure; andforming lined vias and trenches in the dielectric material, over the single crystalline Ge structure, wherein the lined vias and trenches includes a seed layer and filled with a metal material.2. The method of claim 1 , further comprising forming at least one metal filled via in electrical contact with the single crystalline Ge structure claim 1 , and at least one capping layer between the at least one metal filled via and the single crystalline Ge structure.3. The method of claim 1 , wherein the single crystalline Ge structure is adjacent to the waveguide structure.4. The method of claim 1 , wherein the single crystalline Ge structure is a photodetector above the waveguide structure.5. The method of claim 1 , wherein the single crystalline Ge structure is a photodetector adjacent the waveguide structure.6. The method of claim 1 , wherein the barrier layer is between the single crystalline Ge structure and the waveguide structure.7. The method of claim 6 , wherein the barrier layer is nitride.8. The method of claim 1 , wherein the single crystalline Ge ...

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Номер записи: 18
29-12-2016 дата публикации

OPTIMIZED WIRES FOR RESISTANCE OR ELECTROMIGRATION

Номер: US20160379927A1
Автор: Lawrence A. CLEVENGER, Baozhen LI, Kirk D. PETERSON, CLEVENGER LAWRENCE A, LI BAOZHEN, PETERSON KIRK D, CLEVENGER Lawrence A., LI Baozhen, PETERSON Kirk D.
Принадлежит:

Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes depositing metal material within openings and on a surface of dielectric material resulting in metal filled openings and a topography of recessed areas aligned with the metal filled openings. The method further includes depositing an alloying material over the metal material, including within the recessed areas. The method further includes planarizing the metal material, leaving the alloying material within the recessed areas. The method further includes diffusing the alloying material into the metal material forming alloyed regions self-aligned with the metal filled openings. 1. A structure comprising a plurality of via interconnects and wiring structures formed in a dielectric material , the plurality of via interconnects and wiring structures are copper lined structures having a planar surface covered by a capping layer and self-aligned alloying regions with the via interconnects and wiring structures under the capping layer which inhibit electromigration.2. The structure of claim 1 , wherein the self-aligned alloying regions comprise copper material diffused with one of Mn claim 1 , Al claim 1 , Co claim 1 , Sn claim 1 , Pd claim 1 , C claim 1 , Ca claim 1 , Mg claim 1 , and Hf.3. The structure of claim 1 , wherein the wiring structures include the alloying regions aligned with underlying copper interconnect structures.4. The structure of claim 1 , wherein the capping layer is silicon nitride5. The structure of claim 4 , wherein the capping layer has a planarized surface of metal material.6. The structure of claim 5 , wherein the self-aligned alloying regions includes alloying material within recessed areas.7. The structure of claim 6 , wherein the self-aligned alloying regions comprise a thin film formed on copper with a thickness of between about 0.1 to 200 nm.8. The structure of claim 7 , wherein the thin film ...

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Номер записи: 19
05-09-2013 дата публикации

SEMICONDUCTOR STRUCTURES USING REPLACEMENT GATE AND METHODS OF MANUFACTURE

Номер: US20130228835A1
Автор: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Kirk D. PETERSON, Jed H. RANKIN
Принадлежит: International Business Machines Corporation

An improved semiconductor device manufactured using, for example, replacement gate technologies. The method includes forming a dummy gate structure having a gate stack and spacers. The method further includes forming a dielectric material adjacent to the dummy gate structure. The method further includes removing the spacers to form gaps, and implanting a halo extension through the gaps and into an underlying diffusion region.

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Номер записи: 20
14-10-2021 дата публикации

MICROCHIP LEVEL SHARED ARRAY REPAIR

Номер: US20210319845A1
Автор: Timothy MEEHAN, Kirk D. PETERSON, John B. DEFORGE, William V. HUOTT, Uma SRINIVASAN, Hyong Uk KIM, Michelle E. Finnefrock, Daniel RODKO
Принадлежит:

A system may include an integrated circuit having repair select bits coupled with a central repair register. The repair register may be configured to determine how to broadcast multiple repair actions to a group of repairable circuits. Inclusion of the repair register may function to reduce the total number of latches used to hold repair information.

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Номер записи: 21
20-09-2018 дата публикации

PHOTODIODE STRUCTURES

Номер: US20180269348A1
Автор: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON, ELLIS-MONAGHAN JOHN J, GAMBINO JEFFREY P, JAFFE MARK D, PETERSON KIRK D, ELLIS-MONAGHAN, John J., GAMBINO, Jeffrey P., JAFFE, Mark D., PETERSON, Kirk D.
Принадлежит:

Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material. 1. A structure , comprising:a waveguide structure in a dielectric material;a single crystalline Ge structure formed in the dielectric material and-separated from the waveguide structure in the dielectric material; andlined vias and trenches in the dielectric material, over the single crystalline Ge structure, wherein the lined vias and trenches is a nickel seed layer.2. The structure of claim 1 , further comprising at least one metal filled via in electrical contact with the single crystalline Ge structure claim 1 , and at least one capping layer between the at least one metal filled via and the single crystalline Ge structure.3. The structure of claim 1 , wherein the single crystalline Ge structure is adjacent to the waveguide structure.4. The structure of claim 1 , wherein the single crystalline Ge structure is a photodetector above the waveguide structure.5. The structure of claim 1 , wherein the single crystalline Ge structure is a photodetector adjacent the waveguide structure.6. The structure of claim 1 , further comprising a barrier layer between the single crystalline Ge structure and the waveguide structure.7. The structure of claim 6 , wherein the barrier layer is nitride.8. The structure of claim 1 , wherein the single crystalline Ge structure includes nucleation sites.9. The structure of claim 8 , wherein the nucleation sites include a capping layer which is in direct contact with the single crystalline Ge structure.10. The structure of claim 1 , wherein the lined vias and trenches are filled with metal ...

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Номер записи: 22
04-05-2017 дата публикации

PHOTODIODE STRUCTURES

Номер: US20170125627A1
Автор: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON, ELLIS-MONAGHAN JOHN J, GAMBINO JEFFREY P, JAFFE MARK D, PETERSON KIRK D, ELLIS-MONAGHAN John J., GAMBINO Jeffrey P., JAFFE Mark D., PETERSON Kirk D.
Принадлежит:

Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material. 1. A structure , comprising:a waveguide structure and metal wiring layers in a dielectric material;a single crystalline Ge structure formed in proximity to the waveguide structure in the dielectric material; andat least one metal filled via in electrical contact with the Ge material.2. The structure of claim 1 , wherein at least one capping layer between the at least one metal filled via and the Ge material.3. The structure of claim 1 , wherein the single crystalline Ge structure is adjacent to the waveguide structure.4. The structure of claim 1 , wherein the single crystalline Ge structure is a photodector above the waveguide structure.5. The structure of claim 1 , wherein the single crystalline Ge structure is a photodector adjacent the waveguide structure.6. The structure of claim 1 , wherein further comprising a barrier layer between the single crystalline Ge structure and the waveguide structure.7. The structure of claim 6 , wherein the barrier layer is nitride.8. The structure of claim 1 , further comprising lined vias and trenches in the dielectric material claim 1 , over the single crystalline Ge structure.9. The structure of claim 8 , wherein the lined vias and trenches is a nickel seed layer.10. The structure of claim 8 , wherein the lined vias and trenches is germanides.11. The structure of claim 10 , wherein the single crystalline Ge structure includes nucleation sites.12. The structure of claim 11 , wherein the nucleation sites include a capping layer.13. The structure of claim 8 , wherein the lined vias and ...

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Номер записи: 23
17-11-2011 дата публикации

Semiconductor Structures Using Replacement Gate and Methods of Manufacture

Номер: US20110281409A1
Автор: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Kirk D. PETERSON, Jed H. RANKIN, ELLIS-MONAGHAN JOHN J, GAMBINO JEFFREY P, PETERSON KIRK D, RANKIN JED H, ELLIS-MONAGHAN JOHN J., GAMBINO JEFFREY P., PETERSON KIRK D., RANKIN JED H.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

An improved semiconductor device manufactured using, for example, replacement gate technologies. The method includes forming a dummy gate structure having a gate stack and spacers. The method further includes forming a dielectric material adjacent to the dummy gate structure. The method further includes removing the spacers to form gaps, and implanting a halo extension through the gaps and into an underlying diffusion region.

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Номер записи: 24
15-03-2012 дата публикации

METHOD OF DESIGNING AN INTEGRATED CIRCUIT BASED ON A COMBINATION OF MANUFACTURABILITY, TEST COVERAGE AND, OPTIONALLY, DIAGNOSTIC COVERAGE

Номер: US20120066657A1
Автор: Bernstein Kerry, Culp James A., Pastel Leah M.P., Peterson Kirk D., Rohrer Norman J.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection. 1. An integrated circuit design method comprising:generating, based on a description of an integrated circuit, a set of test patterns for testing said integrated circuit;identifying tested nodes in said integrated circuit covered by said test patterns and untested nodes in said integrated circuit not covered by said test patterns;converting said description of said integrated circuit to a layout of said integrated circuit; andmaking, based on a set of design-for-manufacturability (DFM) rules, modifications to said layout, said DFM rules specifying different application requirements for said untested nodes and said tested nodes.2. The integrated circuit design method of claim 1 , said DFM rules comprising a particular rule specifying mandatory application to all of said untested nodes and discretionary application to any of said tested nodes.3. The integrated circuit design method of claim 2 , said particular rule specifying one of mandatory formation of redundant vias ...

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Номер записи: 25
29-03-2012 дата публикации

USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES

Номер: US20120074502A1
Автор: Ellis-Monaghan John J., Gambino Jeffrey P., Peterson Kirk D., Rankin Jed H., Robison Robert R.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts. 1. A method of creating differential stress in a plurality of contacts in an integrated circuit (IC) chip , the method comprising:providing a substrate including a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET);etching at least one PFET contact trench to the PFET;depositing a first material at a first temperature in the at least one PFET contact trench to form a PFET contact;etching at least one NFET contact trench to the NFET;depositing a second material at a second temperature in the at least one NFET contact trench to form an NFET contact, wherein the first temperature is higher than the second temperature.2. The method of claim 1 , wherein the first material has a first coefficient of thermal expansion (CTE) and the second material has a second CTE claim 1 , and wherein the first CTE is higher than the than the second CTE.3. The method of claim 1 , wherein a rate at which the first material is deposited is faster than a rate at which the second material is deposited.4. The method of claim 1 , wherein the first material is selected from the group consisting of: a ...

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Номер записи: 26
04-04-2013 дата публикации

Fuse for three dimensional solid-state battery

Номер: US20130084476A1
Автор: Jed H. Rankin, Jeffrey P. Gambino, John J. Ellis-Monaghan, Kirk D. Peterson
Принадлежит: International Business Machines Corp

A solid-state battery structure having a plurality of battery cells formed in a substrate, method of manufacturing the same and design structure thereof are provided. The battery structure includes a patterned cathode electrode layer formed upon the substrate and structured to form a plurality of sub-arrays of the battery cells. The battery structure further includes a plurality of fuse wires structured to interconnect at least two adjacent sub-arrays. At least one of the plurality of fuse wires is structured to be blown to disconnect an interconnection having a defective sub-array. Advantageously, the plurality of fuse wires is an integral part of the battery structure.

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Номер записи: 27
30-05-2013 дата публикации

Dual power supply memory array having a control circuit that dyanmically selects a lower of two supply voltages for bitline pre-charge operations and an associated method

Номер: US20130135944A1
Автор: George M. Braceras, Harold Pilo, Kirk D. Peterson
Принадлежит: International Business Machines Corp

Disclosed is a memory array in which the lower of two supply voltages from two power supplies is dynamically selected for bitline pre-charge operations. In the memory array, a voltage comparator compares the first supply voltage on a first power supply rail to a second supply voltage on a second power supply rail and outputs a voltage difference signal. If the voltage difference signal has a first value indicating that the first supply voltage is equal to or less than the second supply voltage, than a control circuit ensures that the complementary bitlines connected to a memory cell are pre-charged to the first supply voltage. If the voltage difference signal has a second value indicating that the first supply voltage is greater than the second supply voltage, then the control circuit ensures that the complementary bitlines are pre-charged to the second supply voltage. Also disclosed is an associated method.

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Номер записи: 28
04-07-2013 дата публикации

MICROMIRRORS FOR COLOR ELECTRONIC PAPER AND DESIGN STRUCTURES FOR SAME

Номер: US20130170012A1
Автор: Ellis-Monaghan John J., Gambino Jeffrey P., Peterson Kirk D., Rankin Jed H.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Direct view color displays and design structures of direct view color displays. The direct view displays include micromirrors having un-tilted and tilted states and multiple color filters or color reflectors. 1. A direct view display , comprising:an array of micromirrors and first and second filters formed on a top surface of a substrate, each micromirror of said array of micromirrors having a top surface that reflects light, each micromirror of said array of micromirrors positioned between a respective first filter that absorbs white light and a respective second filter that transmits color light of selected wavelengths, each micromirror of said array of micromirrors (i) having a non-tilted first state that reflects incident light back toward the source of said incident light, (ii) tiltable to a second state to reflect incident light into said first filters and (iii) tiltable to a third state to reflect incident light through said second filters.2. The direct view display of claim 1 , wherein in said non-tilted states claim 1 , said top surfaces of said micromirrors are parallel to said top surface of said substrate.3. The direct view display of claim 1 , wherein said micromirrors are electrically conductive claim 1 , said substrate includes first electrodes positioned between a bottom surface of said micromirrors and proximate to first sides of said micromirrors and second electrodes positioned between said bottom surface of said micromirrors and proximate to second and opposite sides of said micromirrors claim 1 , said micromirrors tiltable to said second state when different polarity voltages are applied to said micromirrors and said first electrodes and tiltable to said third state when different polarity voltages are applied to said micromirrors and said second electrodes.4. The direct view display of claim 1 , further including:a transparent cover plate supported by said first and second filters, said micromirrors positioned between said cover plate and said ...

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Номер записи: 29
08-08-2013 дата публикации

USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES

Номер: US20130200434A1
Автор: Ellis-Monaghan John J., Gambino Jeffrey P., Peterson Kirk D., Rankin Jed H., Robison Robert R.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET. 1. An integrated circuit (IC) chip comprising:a substrate having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) thereon, the PFET and NFET each including a source/drain region;a PFET contact to a source/drain region of the PFET;an NFET contact to a source/drain region of the NFET; anda silicon germanium (SiGe) layer only under the PFET contact, wherein the SiGe layer extends into the source/drain region of the PFET.2. The IC chip of claim 1 , wherein the SiGe layer extends approximately 50 to approximately 3000 angstroms into the source/drain region of the PFET.3. The IC chip of claim 1 , wherein the PFET contact includes a pair of PFET contacts claim 1 , one PFET contact to a source region of the PFET and one PFET contact to a drain region of the PFET.4. The IC chip of claim 1 , wherein an upper surface of the SiGe layer is coplanar with an upper surface of the source/drain region of the PFET.5. The IC chip of claim 1 , wherein a percentage of germanium (Ge) in the SiGe layer is approximately 20 percent.6. An integrated circuit (IC) chip comprising:a substrate having a p-type field effect transistor (PFET) and a n-type field effect transistor (NFET) thereon, the PFET and NFET each including a source/drain region;a PFET contact to a source ...

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Номер записи: 30
08-08-2013 дата публикации

3-DIMENSIONAL INTEGRATED CIRCUIT TESTING USING MEMS SWITCHES WITH TUNGSTEN CONE CONTACTS

Номер: US20130200910A1
Автор: Ellis-Monaghan John J., Gambino Jeffrey P., Peterson Kirk D., Rankin Jed H.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A test system for testing a multilayer 3-dimensional integrated circuit (IC), where two separate layers of IC circuits are temporarily connected in order to achieve functionality, includes a chip under test with a first portion of the 3-dimensional IC, and a test probe chip with a second portion of the 3-dimensional IC and micro-electrical-mechanical system (MEMS) switches that selectively complete functional circuits between the first portion of the 3-dimensional IC in a first IC layer to circuits within the second portion of the 3-dimensional IC in a second IC layer. The MEMS switches include tungsten (W) cone contacts, which make the selective electrical contacts between circuits of the chip under test and the test probe chip and which are formed using a template of graded borophosphosilicate glass (BPSG). 1. A test probe chip , comprising:an integrated circuit (IC) layer that forms a portion of a 3-dimensional IC, said IC layer being formed above a base layer; a beam having an upper surface of a first end that contacts an extension of said first TSV beneath a lower surface of said base layer,', 'a tungsten (W) cone contact disposed on a lower surface at a second end of said beam, and', 'an actuator disposed on said lower surface of said base layer and separated from said upper surface of said second end of said beam by an air gap, when not actuated., 'a first through silicon via (TSV), said first TSV contacting said IC layer and extending through said base layer to contact a micro-electrical-mechanical systems (MEMS) switch, said MEMS switch comprising2. The test probe chip of claim 1 , each of said TSVs comprising a peripheral insulating layer of silicon dioxide (SiO) and a metallic core of copper (Cu).3. The test probe chip of claim 2 , said beam comprising a bilayer of an upper insulating layer and a lower metal layer claim 2 , said lower metal layer penetrating said upper insulating layer at said first end of said beam to contact said metallic core of said ...

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Номер записи: 31
15-08-2013 дата публикации

USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES

Номер: US20130210227A1
Автор: Ellis-Monaghan John J., Gambino Jeffrey P., Peterson Kirk D., Rankin Jed H., Robison Robert R.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET. 1. A method of creating differential stress in a plurality of contacts in an integrated circuit (IC) chip , the method comprising:providing a substrate including a p-type field effect transistor (PFET) and a n-type field effect transistor (NFET), the PFET and NFET each including a source/drain region;forming a silicide layer over the PFET and the NFET;depositing at least one nitride layer over the substrate;depositing a dielectric layer over the at least one nitride layer;etching a PFET contact trench through the dielectric layer down to the at least one nitride layer on the PFET;etching an NFET contact trench through the dielectric layer down to the at least one nitride layer on the NFET;opening the at least one nitride layer in a selected contact trench of a selected FET of the PFET and the NFET;etching the selected contact trench through the silicide layer into the source/drain region of the selected FET, and opening the at least one nitride layer on the FET that is not the selected FET;filling the PFET contact trench to form a PFET contact; andfilling the NFET contact trench to form an NFET contact,wherein in the case that the PFET is the selected FET, the PFET contact extends into the source/drain region of the PFET, and in the case that the NFET is the selected FET, the ...

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Номер записи: 32
29-08-2013 дата публикации

MICRO-ELECTRO-MECHANICAL SYSTEM TILTABLE LENS

Номер: US20130224896A1
Автор: Ellis-Monaghan John J., Gambino Jeffrey P., Peterson Kirk D., Rankin Jed H.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A tiltable micro-electro-mechanical (MEMS) system lens comprises a microscopic lens located on a front surface of a semiconductor-on-insulator (SOI) substrate and a semiconductor rim surrounding the periphery of the microscopic lens. Two horizontal semiconductor beams located at different heights are provided within a top semiconductor layer. The microscopic lens may be tilted by applying an electrical bias between the lens rim and one of the two semiconductor beams, thereby altering the path of an optical beam through the microscopic lens. An array of tiltable microscopic lenses may be employed to form a composite lens having a variable focal length may be formed. A design structure for such a tiltable MEMS lens is also provided. 1. A design structure embodied in a machine readable medium for designing , manufacturing , or testing a design for a semiconductor structure , said design structure comprising:a first data representing a semiconductor-on-insulator (SOI) substrate including a patterned top semiconductor layer, a buried insulator layer, and a handle substrate;a second data representing a microlens located on said patterned top semiconductor layer and comprising an optically transparent material and having a convex or concave surface;a third data representing a lens rim abutting a peripheral portion of said microlens and comprising a doped semiconductor material;a fourth data representing a first horizontal semiconductor beam included in said patterned top semiconductor layer and located in proximity to said lens rim, but not abutting said lens rim; anda fifth data representing a second horizontal semiconductor beam located in said patterned top semiconductor layer and located in proximity to said lens rim, but not abutting said lens rim, wherein said first and second horizontal semiconductor beams comprises a doped semiconductor material, and wherein said second horizontal semiconductor beam if vertically and laterally offset from said first horizontal ...

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Номер записи: 33
26-09-2013 дата публикации

CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE

Номер: US20130249052A1
Автор: Appleyard Jennifer E., Barth, DeForge John B., Ho Herbert L., JR. John E., Khan Babar A., Peterson Kirk D., Turner Andrew A.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications. 1. A method comprising:providing a first substrate;doping an upper part of the first substrate to form at least one buried plate in the first substrate;forming a plurality of trenches in each of the at least one buried plate; andfilling each of the plurality of trenches with a first conductor to form an inner electrode in each of the plurality of trenches.2. The method of claim 1 , further comprising:forming a recess in an upper surface of the first conductor in each of the plurality of trenches;depositing polysilicon over the upper surface of the first conductor and an upper surface of the first substrate; andremoving the polysilicon from the upper surface of the first substrate.3. The method of claim 1 , further comprising:before filling the plurality of trenches with the first conductor,forming an oxide liner in each of the plurality of trenches; andforming an oxide layer over the upper surface of the first substrate,wherein each of the plurality of inner electrodes extends vertically above an upper surface of the at least one buried plate.4. The method of claim 3 , further comprising:after forming an oxide liner in each of the plurality of trenches,forming a mask layer over some of the plurality of trenches in each of the at least one buried plate, wherein at least one of the plurality of trenches is not covered by the mask;etching the oxide liner from the exposed at least one of the plurality of trenches; andremoving ...

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Номер записи: 34
03-10-2013 дата публикации

SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING

Номер: US20130256830A1
Автор: Barth, Ho Herbert L., JR. John E., Khan Babar A., Peterson Kirk D.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer. 1. A method of forming a semiconductor-on-oxide structure , the method comprising:forming a first dielectric layer over a substrate;forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide;forming a second dielectric layer over the first conductive layer;bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer;cleaving the donor wafer to remove a portion of the donor semiconductor layer;forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; andforming a contact to the first conductive layer through the donor dielectric and the second dielectric layer.2. The method of claim 1 , wherein the contact includes at least one of tungsten claim 1 , copper or polysilicon claim 1 , and the semiconductor layer includes silicon.3. The method of claim 1 , wherein the forming of the at least one semiconductor isolation region includesetching the unremoved portion of the donor semiconductor layer; andforming an additional dielectric partially surrounding the etched unremoved portion of the donor ...

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Номер записи: 35
03-10-2013 дата публикации

THREE DIMENSIONAL SOLID-STATE BATTERY INTEGRATED WITH CMOS DEVICES

Номер: US20130260183A1
Автор: Ellis-Monaghan John, Gambino Jeffrey P., Peterson Kirk D., Rankin Jed Hickory
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A solid-state battery structure having a plurality of battery cells formed in a substrate. The plurality of battery cells includes a first current collector layer overlying a first insulating layer and a first electrode layer overlying the first current collector layer. The battery structure further includes a second current collector layer overlying a patterned second electrode layer. The patterned second electrode layer overlies the substrate and forms a plurality of sub-arrays of the battery cells. The battery structure further includes a second insulating layer overlying the second current collector layer. The second insulating layer substantially laterally surrounds first and second contact pads. The first pad is electrically connected to the first current collector layer and the second pad is electrically connected to the second current collector layer. The first and second contact pads are in electrical communication, through at least two electrical wires, with a circuit located upon the substrate. 1. A battery structure comprising:a substrate;a plurality of battery cells formed in the substrate, the plurality of battery cells comprising a first current collector layer overlying a first insulating layer and a first electrode layer overlying the first current collector layer;a second current collector layer overlying a patterned second electrode layer, the patterned second electrode layer overlies the substrate and forms a plurality of sub-arrays of the battery cells; anda second insulating layer overlying the second current collector layer, the second insulating layer substantially laterally surrounding first and second contact pads, the first contact pad electrically connected to the first current collector layer and the second contact pad electrically connected to the second current collector layer, the first contact pad and the second contact pad are in electrical communication, through at least two electrical wires, with a circuit located upon the ...

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Номер записи: 36
31-10-2013 дата публикации

METAL-INSULATOR-METAL (MIM) CAPACITOR WITH DEEP TRENCH (DT) STRUCTURE AND METHOD IN A SILICON-ON-INSULATOR (SOI)

Номер: US20130285193A1
Автор: Barth, Ho Herbert L., JR. John E., Khan Babar A., Peterson Kirk D.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor. 1. A structure forming a metal-insulator-metal (MIM) trench capacitor , comprising: a metal layer; and', 'at least one other layer;, 'a multi-layer substrate comprisinga trench in said substrate passing through said metal layer and at least partially into said at least one other layer;a metal material partially lining said trench, said metal material being in contact with said metal layer, said metal layer comprising a first node of a capacitor;a dielectric material lining said metal material; anda conductor filling said trench,said dielectric material separating said conductor from said metal layer,said dielectric material additionally separating said conductor from said metal material lining said trench, andsaid conductor comprising a second node of said capacitor.2. The structure of claim 1 , further comprising:a dielectric layer deposited on said metal layer; anda Silicon-on-insulator (SOI) layer bonded on said dielectric layer;said trench passing through said dielectric layer and said SOI layer, andsaid metal material lining said trench being insulated from said SOI layer.3. The structure of claim 2 , said conductor being in contact with said SOI layer.4. The structure of claim 1 , further comprising:a poly cap deposited on said conductor.5. The structure of claim 1 , said multi-layer ...

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Номер записи: 37
23-01-2014 дата публикации

CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE

Номер: US20140021585A1
Автор: Appleyard Jennifer E., Barth John E., DeForge John B., Ho Herbert L., Khan Babar A., Peterson Kirk D., Turner Andrew A.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications. 1. A structure comprising: 'a plurality of deep trench capacitors disposed about the at least one buried plate contact; and', 'a first substrate, the first substrate including at least one buried plate disposed in an upper part of the first substrate, wherein each of the at least one buried plate includesa first oxide layer disposed over the first substrate.2. The structure of claim 1 , further comprising an insulating liner disposed about each of the plurality of deep trench capacitors.3. The structure of claim 1 , wherein the first substrate comprises a P− substrate claim 1 , and buried plate comprises a N+ doped region of the first substrate.4. The structure of claim 1 , further comprising a polysilicon plug disposed on an upper surface of at least one of the plurality of deep trench capacitors and the at least one buried plate contact.5. The structure of claim 1 , further comprising:a second substrate disposed above the first oxide layer;at least one polyconductor gate disposed above the second substrate; anda second oxide layer disposed above the second substrate and the at least one polyconductor gate.6. The structure of claim 5 , further comprising:a plurality of conductive contacts, wherein each of the plurality of conductive contacts vertically extends from an upper surface of the second oxide layer to an upper surface of one of the at least one buried plate contacts, and one of the plurality of deep trench ...

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Номер записи: 38
27-03-2014 дата публикации

Semiconductor-on-insulator (soi) deep trench capacitor

Номер: US20140084411A1
Автор: Babar A. Khan, Herbert L. Ho, John E. Barth, Jr., Kirk D. Peterson
Принадлежит: International Business Machines Corp

Aspects of the present invention relate to a semiconductor-on-insulator (SOI) deep trench capacitor. One embodiment includes a method of forming a deep trench capacitor structure. The method includes: providing a SOI structure including a first and second trench opening in a semiconductor layer of the SOI structure, forming a doped semiconductor layer covering the semiconductor layer, forming a first dielectric layer covering the doped semiconductor layer, forming a node metal layer over the first dielectric layer, forming a second dielectric layer covering the node metal layer, filling a remaining portion of each trench opening with a metal layer to form an inner node in each of the trench openings, the metal layer including a plate coupling each of the inner nodes, and forming a node connection structure to conductively connect the node metal layer in the first trench opening with the node metal layer in the second trench opening.

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Номер записи: 39
03-01-2019 дата публикации

METALIZATION REPAIR IN SEMICONDUCTOR WAFERS

Номер: US20190006248A1
Автор: Clevenger Lawrence A., II John E., Li Baozhen, Peterson Kirk D., Sheets
Принадлежит:

Embodiments are directed to a method for repairing features of a host semiconductor wafer. The method includes forming a feature of the host semiconductor wafer, wherein the feature includes a first conductive material and a surface having a planar region and non-planar regions. The method further includes forming a metal conductive liner over the non-planar regions. The method further includes applying a second conductive material metal layer over said the conductive liner. The method further includes recessing the second conductive material to be substantially planar with the planar region. 1. A method for repairing features of a host semiconductor wafer , the method comprising:forming a feature of the host semiconductor wafer, wherein the feature comprises a first conductive material and a surface having a planar region and non-planar regions;determining a first defect level of the feature, wherein the first defect level corresponds to a characteristic of the non-planar regions;comparing the first defect level to a threshold;applying a first repair methodology to the feature if the defect level is below the threshold;applying a second repair methodology to the feature if the defect level is above the threshold;determining a second defect level of the feature, wherein the second defect level corresponds to a characteristic of the non-planar regions;applying the first repair methodology to the feature if the second defect level is below the threshold; andapplying the second repair methodology to the feature if the second defect level is above the threshold.2. The method of claim 1 , wherein the second repair methodology comprises:forming a conductive liner over at least the non-planar regions;applying a second conductive material over at least the conductive liner; andrecessing the second conductive material to be substantially planar with the planar region;wherein the first repair methodology comprises applying a current to the first conductive material to induce ...

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Номер записи: 40
10-01-2019 дата публикации

PROTECTIVE LINER BETWEEN A GATE DIELECTRIC AND A GATE CONTACT

Номер: US20190013238A1
Автор: Clevenger Lawrence A., Li Baozhen, Peterson Kirk D., Wang Junli
Принадлежит:

A method of forming a protective liner between a gate dielectric and a gate contact. The method may include; forming a finFET having a replacement metal gate (RMG) on one or more fins, the RMG includes a gate dielectric wrapped around a metal gate, an outer liner is on the sidewalls of the gate dielectric and on the fins; forming a gate contact trench by recessing the gate dielectric and the outer liner below a top surface of the metal gate in a gate contact region; forming a protective trench by further recessing the gate dielectric below a top surface of the outer liner; filling the protective trench with a protective liner; and forming a gate contact in the gate contact trench, where the protective liner is between the gate dielectric and the gate contact. 1. A semiconductor structure comprising:a gate comprising a gate dielectric disposed on opposite sidewalls of the gate;a gate contact above and in electrical contact with the gate;a protective liner separating the gate dielectric from the gate contact, wherein a lateral thickness of first portions of the protective liner is equal to a lateral thickness of a portion of the gate dielectric; anda gate contact liner separating the protective liner from the gate contact.2. The structure of claim 1 , wherein the top surface of the gate dielectric is below a top surface of the gate.3. The structure of claim 1 , further comprising:a dielectric liner separating portions of the gate dielectric and portions of the protective liner from an interlevel dielectric layer, wherein a top surface of the dielectric liner is below a top surface of the gate and above a top surface of the gate dielectric.4. The structure of claim 1 , wherein the gate contact is arranged perpendicular to the gate.5. The structure of claim 1 , wherein portions of the gate contact extend below an upper surface of the gate.6. The structure of claim 1 , wherein the gate dielectric separates the gate from a fin.7. A semiconductor structure comprising:a ...

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Номер записи: 41
09-01-2020 дата публикации

ENHANCEMENT OF ISO-VIA RELIABILITY

Номер: US20200013671A1
Автор: Clevenger Lawrence A., Li Baozhen, Liu Xiao H., Peterson Kirk D.
Принадлежит:

A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a multilayer cap layer and an ILD layer. A metal-filled via extends through the ILD layer and partially through the cap layer to make contact with the wiring line. There is a reliability enhancement material formed in one of the layers of the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer. 1. A semiconductor structure comprising:a semiconductor base comprising a plurality of semiconductor devices; a wiring line;', 'a multilayer cap layer on the wiring line comprising first, second and third layers of silicon carbide nitride (SiCN) such that the second layer is between the first and third layers and is richer in silicon content than the first and third layers and the second layer is oxidized to form a reliability enhancement material comprising silicon carbide nitride plus oxygen (SiOCN);', 'an interlayer dielectric (ILD) layer on the cap layer and the reliability enhancement material;', 'a via extending through the ILD, the first layer and the reliability enhancement material to communicate with the wiring line such that the third layer is between the via and the wiring line; and', 'a metal filling the via and in contact with the third layer and the wiring line;, 'a back end of the line wiring layer comprisingwherein the reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the third layer and the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the first and third layers of the cap ...

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Номер записи: 42
09-01-2020 дата публикации

LOW RESISTANCE CONTACT FOR TRANSISTORS

Номер: US20200013868A1
Автор: Clevenger Lawrence A., II John E., Li Baozhen, Peterson Kirk D., Sheets, Spooner Terry A., Wang Junli
Принадлежит:

According to an embodiment of the present invention, a method for forming contacts includes forming an oxide layer over and along a first liner layer. A first spacer layer is formed along the first liner layer opposing the oxide layer. A work function metal layer is formed along the first spacer layer opposing the first liner layer. A gate is formed on and along the work function metal opposing the first spacer. A second spacer layer is formed on the oxide layer. Portions of the oxide layer, the first liner layer, the first spacer, the work function metal layer and the second spacer layer are removed which forms a recess between the gate and the first spacer layer. A second liner layer is deposited in the recess. A low-resistance metal is deposited in the removed portions to form the first contact. 1. A semiconductor device comprising:a fin coupled to a source or a drain (S/D);a work function metal coupled to the fin and a gate;a liner coupled to the work function metal;a first contact coupled to the gate, wherein the liner provides a barrier between the first contact and the work function metal;a trench silicide region coupled to the fin; anda second contact coupled to the trench silicide region.2. The semiconductor device of claim 1 , wherein the first contact and the second contact are comprised as a low-resistance metal.3. The semiconductor device of claim 2 , wherein the low-resistance metal is copper.4. The semiconductor device of claim 1 , wherein the liner is comprised of silicon nitride.5. The semiconductor device of claim 1 , wherein the liner width is 2-15 nanometers.6. The semiconductor device of claim 1 , wherein the liner is 1-15 nanometers in height.7. The semiconductor device of claim 1 , wherein portions of the work function metal are etched to form a recess claim 1 , wherein the liner resides in the recess.8. The semiconductor device of further comprising a dielectric claim 1 , wherein the dielectric is associated with the work function metal.9. ...

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Номер записи: 43
22-01-2015 дата публикации

METAL-INSULATOR-METAL (MIM) CAPACITOR WITH DEEP TRENCH (DT) STRUCTURE AND METHOD IN A SILICON-ON-INSULATOR (SOI)

Номер: US20150021737A1
Автор: Barth, Ho Herbert L., JR. John E., Khan Babar A., Peterson Kirk D.
Принадлежит:

A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor. 1. A structure , comprising: a metal layer; and', 'at least one other layer;, 'a multi-layer substrate comprisinga trench in said substrate passing through said metal layer and at least partially into said at least one other layer;a metal material partially lining said trench, said metal material being in contact with said metal layer;a dielectric material lining said metal material; anda conductor filling said trench,said dielectric material separating said conductor from said metal layer, andsaid dielectric material additionally separating said conductor from said metal material lining said trench.2. The structure of claim 1 , said metal layer comprising a first node of a capacitor.3. The structure of claim 2 , said conductor comprising a second node of said capacitor.4. The structure of claim 1 , further comprising:a dielectric layer deposited on said metal layer; anda Silicon-on-insulator (SOI) layer bonded on said dielectric layer,said trench passing through said dielectric layer and said SOI layer, andsaid metal material lining said trench being insulated from said SOI layer.5. The structure of claim 4 , said conductor being in contact with said SOI layer.6. The structure of claim 1 , further comprising:a poly cap deposited on said conductor.7. The structure of claim 1 , said multi-layer ...

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Номер записи: 44
17-04-2014 дата публикации

METHODOLOGY OF GRADING RELIABILITY AND PERFORMANCE OF CHIPS ACROSS WAFER

Номер: US20140107822A1
Автор: Chadwick Nathaniel R., Di Sarro James P., Gauthier, JR. Robert J., Lee Tom C., Li Junjun, Mitra Souvick, Peterson Kirk D., Turner Andrew A.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A system and method sorts integrated circuit devices. Integrated circuit devices are manufactured on a wafer according to an integrated circuit design using manufacturing equipment. The design produces integrated circuit devices that are identically designed and perform differently based on manufacturing process variations. The integrated circuit devices are for use in a range of environmental conditions, when placed in service. Testing is performed on the integrated circuit devices. Environmental maximums are individually predicted for each device. The environmental maximums comprise ones of the environmental conditions that must not be exceeded for each device to perform above a given failure rate. Each integrated circuit device is assigned at least one of a plurality of grades based on the environmental maximums predicted for each device. The integrated circuit devices are provided to different forms of service having different ones of the environmental conditions based on the grades assigned to each device. 1. A method of sorting integrated circuit devices , said method comprising:manufacturing said integrated circuit devices on a wafer according to an integrated circuit design using manufacturing equipment, said integrated circuit design producing identically designed integrated circuit devices that perform differently based on manufacturing process variations, said identically designed integrated circuit devices being for use in a range of environmental conditions, when placed in service;performing testing on said identically designed integrated circuit devices using testing equipment to produce test results;individually predicting environmental maximums for each identically designed integrated circuit device of said identically designed integrated circuit devices using a computerized device operatively connected to said testing equipment, said environmental maximums comprising ones of said environmental conditions that must not be exceeded for each said ...

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Номер записи: 45
29-01-2015 дата публикации

Nanoparticles for making supercapacitor and diode structures

Номер: US20150028449A1
Автор: James W. Adkisson, Jed H. Rankin, Jeffrey P. Gambino, John J. Ellis-Monaghan, Kirk D. Peterson
Принадлежит: International Business Machines Corp

Structures and methods of making a supercapacitor may include a first electrode comprising a first conductive plate and a 3-dimensional (3D) aggregate of sintered nanoparticles electrically connected one to another and to the first conductive plate. The supercapacitor may also include a dielectric formed on surfaces of the 3D aggregate of sintered nanoparticles. The supercapacitor may further include a second electrode comprising a solid second conductor that fills interstices between surfaces of the dielectric and electrically connects to a second conductive plate of a solid second conductor, disposed above an outermost portion of the dielectric.

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Номер записи: 46
01-02-2018 дата публикации

SEMICONDUCTOR POWER AND PERFORMANCE OPTIMIZATION

Номер: US20180031630A1
Автор: Carey Sean M., Peterson Kirk D., Turner Andrew A.
Принадлежит:

Embodiments are directed to a method and system for testing and optimizing integrated circuit devices. Latches within an integrated circuit device that fail to operate properly are found using observed data from a test. Thereafter, a directed graph of the layout of the integrated circuit is used to find clock controllers that feed into the latches. The clock controllers that are the most likely to be at issue are ranked, then testing can be performed to confirm that a critical path can be found. The critical path can be excluded from further power optimization to maintain the performance of the integrated circuit device. Other embodiments are also disclosed. 1. A computer-implemented method comprising:examining, by a processor, fail data of an integrated circuit device to determine which latches of the integrated circuit device are underperforming;analyzing, by the processor, a directed graph of the integrated circuit device to find clock controllers that feed into the latches that are underperforming;creating, using the processor, a test plan to test the clock controllers; andperforming, using the processor, the test plan to find the clock controllers that are in a critical path.2. The computer-implemented method of further comprising:testing a proposed solution to the clock controllers in the critical path; andwriting the proposed solution to a vital product data (VPD).3. The computer-implemented method of wherein claim 2 , the proposed solution is a timing correction to the clock controllers in the critical path.4. The computer-implemented method of wherein claim 2 , the VPD comprises a set of operating parameters applied to the integrated circuit device prior to operation.5. The computer-implemented method of claim 1 , wherein the test plan to test the clock controllers tests the clock controllers in order of a likelihood of the clock controller being part of the critical path.6. The computer-implemented method of further comprising:using a performance screen ...

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Номер записи: 47
05-02-2015 дата публикации

HIGH DENSITY CAPACITOR INTEGRATED INTO FOCAL PLANE ARRAY PROCESSING FLOW

Номер: US20150035108A1
Автор: Jardine Daniel B., Krueger Eugene E., Ossenfort Cari A., Peterson Kirk D., Skidmore George D.
Принадлежит: DRS RSTA, INC.

Methods and structures of photodetectors are described. The structure may include a readout integrated circuit substrate having an internally integrated capacitor. The structure may additionally include an external capacitor overlying the readout integrated circuit substrate. The external capacitor may be coupled with the internally integrated capacitor of the readout integrated circuit substrate, and configured to operate in parallel with the internally integrated capacitor of the readout integrated circuit substrate. The structure may also include a detector overlying the external capacitor. 1. A photodetector structure comprising:a readout integrated circuit substrate having an internally integrated capacitor;an external capacitor overlying the readout integrated circuit substrate, wherein the external capacitor is coupled with the internally integrated capacitor of the readout integrated circuit substrate and configured to operate in parallel with the internally integrated capacitor of the readout integrated circuit substrate; anda detector overlying the external capacitor.2. The photodetector structure of claim 1 , further comprising a reflector material layer overlying the external capacitor claim 1 , and located below the detector.3. The photodetector structure of claim 2 , wherein the reflector material is configured to provide electrical coupling of an electrode of the external capacitor with the readout integrated circuit.4. The photodetector structure of claim 1 , wherein the detector comprises a photodiode.5. The photodetector structure of claim 1 , wherein the external capacitor further comprises:a first electrode overlying the readout integrated circuit substrate;a dielectric material overlying the first electrode; anda second electrode overlying the dielectric material.6. The photodetector structure of claim 5 , wherein each of the first electrode and second electrode include a first layer of electrode material and a second layer of electrode material ...

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Номер записи: 48
11-02-2016 дата публикации

REDUCING THE IMPACT OF CHARGED PARTICLE BEAMS IN CRITICAL DIMENSION ANALYSIS

Номер: US20160040986A1
Автор: Peterson Kirk D., Shao Dongbing
Принадлежит:

Measuring a feature on a wafer, the feature including at least two edges. Scanning the wafer with an electron beam over the length of a first scan interval that includes at least a portion of a first edge of the feature. Preventing the electron beam from illuminating the wafer while moving the scan position of the electron beam across a portion of the wafer to a second scan interval that includes at least a portion of a second edge of the feature. Scanning the wafer with an electron beam over the length of the second scan interval. Determining a distance between the first and second edges of the feature. 1. A method for measuring a feature on a wafer using , the feature including at least two edges , the method comprising:scanning the wafer with an electron beam over the length of a first scan interval that includes at least a portion of a first edge of the feature;preventing the electron beam from illuminating the wafer while moving the scan position of the electron beam across a portion of the wafer to a second scan interval that includes at least a portion of a second edge of the feature;scanning the wafer with the electron beam over the length of the second scan interval; anddetermining a distance between the first and second edges of the feature.2. A method in accordance with claim 1 , wherein determining a distance further comprises:receiving a signal representative of emissions from the feature and/or wafer caused by the interaction of the electron beam and the feature and/or wafer;analyzing the signal to determine most likely locations for the first and second edges of the feature; anddetermining a distance between the most likely locations for the first and second edges of the feature.3. A method in accordance with claim 1 , wherein scanning the wafer over the length of the first and/or second scan interval further comprises:aligning the electron beam to the start of the scan interval, wherein aligning includes one or more of: aligning the electron beam to ...

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Номер записи: 49
22-05-2014 дата публикации

HIGH DENSITY CAPACITOR INTEGRATED INTO FOCAL PLANE ARRAY PROCESSING FLOW

Номер: US20140138786A1
Автор: Jardine Daniel B., Krueger Eugene E., Ossenfort Cari A., Peterson Kirk D., Skidmore George D.
Принадлежит: DRS RSTA, INC.

Methods and structures of photodetectors are described. The structure may include a readout integrated circuit substrate having an internally integrated capacitor. The structure may additionally include an external capacitor overlying the readout integrated circuit substrate. The external capacitor may be coupled with the internally integrated capacitor of the readout integrated circuit substrate, and configured to operate in parallel with the internally integrated capacitor of the readout integrated circuit substrate. The structure may also include a detector overlying the external capacitor. 1. A photodetector structure comprising:a readout integrated circuit substrate having an internally integrated capacitor;an external capacitor overlying the readout integrated circuit substrate, wherein the external capacitor is coupled with the internally integrated capacitor of the readout integrated circuit substrate and configured to operate in parallel with the internally integrated capacitor of the readout integrated circuit substrate; anda detector overlying the external capacitor.2. The photodetector structure of claim 1 , further comprising a reflector material layer overlying the external capacitor claim 1 , and located below the detector.3. The photodetector structure of claim 2 , wherein the reflector material is configured to provide electrical coupling of an electrode of the external capacitor with the readout integrated circuit.4. The photodetector structure of claim 1 , wherein the detector comprises a photodiode.5. The photodetector structure of claim 1 , wherein the external capacitor further comprises:a first electrode overlying the readout integrated circuit substrate;a dielectric material overlying the first electrode; anda second electrode overlying the dielectric material.6. The photodetector structure of claim 5 , wherein each of the first electrode and second electrode include a first layer of electrode material and a second layer of electrode material ...

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Номер записи: 50
01-03-2018 дата публикации

SEMICONDUCTOR VIA STRUCTURE WITH LOWER ELECTRICAL RESISTANCE

Номер: US20180061707A1
Автор: Clevenger Lawrence A., Li Baozhen, Peterson Kirk D., Spooner Terry A., Wang Junli
Принадлежит:

A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via. 1. A semiconductive device comprising:a first conductive line including a first conductive material;a second conductive line including a second conductive material;a via connecting the first conductive line and the second conductive line, wherein the via includes a via material, wherein the via material includes a via material top surface, wherein the via material is in direct physical contact with the first conductive line, wherein the via material top surface is convex;a first liner material coating inner surfaces of the via side walls; anda second liner material coating the via material top surface.2. A semiconductive device comprising:a first conductive line including a first conductive material;a second conductive line including a second conductive material;a via connecting the first conductive line and the second conductive line, wherein the via includes a via material, wherein the via material includes a via material top surface;a first liner material coating inner surfaces of the via side walls; anda second liner material coating the via material top surface.3. The semiconductive device of claim 2 , wherein the via material is in direct physical contact with the first conductive line.4. The semiconductive device of claim 2 , wherein the second liner material physically isolates the via material from the second conductive line.5. The semiconductive device of claim 2 , wherein the via material top surface extends above a bottom surface of the second conductive line.6. ...

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Номер записи: 51
15-03-2018 дата публикации

PROTECTIVE LINER BETWEEN A GATE DIELECTRIC AND A GATE CONTACT

Номер: US20180076086A1
Автор: Clevenger Lawrence A., Li Baozhen, Peterson Kirk D., Wang Junli
Принадлежит:

A method of forming a protective liner between a gate dielectric and a gate contact. The method may include; forming a finFET having a replacement metal gate (RMG) on one or more fins, the RMG includes a gate dielectric wrapped around a metal gate, an outer liner is on the sidewalls of the gate dielectric and on the fins; forming a gate contact trench by recessing the gate dielectric and the outer liner below a top surface of the metal gate in a gate contact region; forming a protective trench by further recessing the gate dielectric below a top surface of the outer liner; filling the protective trench with a protective liner; and forming a gate contact in the gate contact trench, where the protective liner is between the gate dielectric and the gate contact. 1. A method comprising:forming a finFET structure including one or more dummy gates on one or more fins, a gate spacer on sidewalls of the dummy gate, an outer liner on the gate spacer and on the fins, and a first inter-layer dielectric (ILD) on the outer liner;removing the gate spacer from at least a gate contact region;replacing the dummy gate with a replacement metal gate (RMG), the RMG includes a metal gate and a gate dielectric, the gate dielectric is between the metal gate and the fins and between the metal gate and the outer liner;forming a first fin contact through the first ILD and the outer liner, the first fin contact is in direct connection with the fins;forming a gate contact trench by recessing the first ILD, the gate dielectric, and the outer liner in the gate contact region, the gate contact trench exposes the top surface of the metal gate;forming a protective trench in the gate contact trench by recessing the gate dielectric exposing a portion of the metal gate sidewalls;forming a protective liner in the protective trench; andforming a gate contact in the gate contact trench, the gate contact is directly on the metal gate, and the protective liner is between the metal gate and the gate ...

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Номер записи: 52
22-03-2018 дата публикации

ROBUST BUILT-IN SELF TEST CIRCUITRY

Номер: US20180080986A1
Автор: DeForge John B., Hook Terence B., Newton Theresa A., Peterson Kirk D.
Принадлежит:

Embodiments are directed to a semiconductor wafer having on-wafer circuitry. The on-wafer circuitry includes functional circuitry and first drive circuitry communicatively coupled to the functional circuitry. The on-wafer circuitry further includes test-only circuitry communicatively coupled to the functional circuitry, along with second drive circuitry communicatively coupled to the test-only circuitry. The control circuitry is communicatively coupled to the second drive circuitry and the test-only circuitry, wherein the first drive circuitry is configured to drive the functional circuitry in a first manner, and wherein the control circuitry is configured to control the second drive circuitry to drive the test-only circuitry in a second manner that is independent of the first manner. 1. A semiconductor wafer having on-wafer circuitry comprising:functional circuitry;first drive circuitry communicatively coupled to the functional circuitry;test-only circuitry communicatively coupled to the functional circuitry;second drive circuitry communicatively coupled to the test-only circuitry; andcontrol circuitry communicatively coupled to the second drive circuitry and the test-only circuitry;wherein the first drive circuitry is configured to drive the functional circuitry in a first manner;wherein the control circuitry is configured to control the second drive circuitry to drive the test-only circuitry in a second manner that is independent of the first manner.2. The semiconductor wafer of claim 1 , wherein the second manner comprises:receiving, at the control circuitry, control data from the test-only circuitry; generate modulated test-only drive signals; and', 'apply the modulated test-only drive signals to drive the test-only circuitry., 'based at least in part on the control data, controlling, using the control circuitry, the second test-only drive circuitry to3. The semiconductor wafer of claim 1 , wherein the second manner comprises:disabling the second drive ...

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Номер записи: 53
09-04-2015 дата публикации

Semiconductor device burn-in stress method and system

Номер: US20150100939A1
Автор: Esuasi K. Segbefia, Kirk D. Peterson, Mark D. Knox
Принадлежит: International Business Machines Corp

Burn-in (BI) stress using stress patterns with pin-specific power characteristics. A control device for each conductive pathway from BI board (BIB) contacts to device under test (DUT) connectors/contacts can adjust power delivered to a respective connector/contact responsive to a controller. The control devices can be included in the BIB or an interposer (IP) can be used with existing equipment. Each control device can include a regulator, such as a latchable array of field effect transistors that can regulate power delivered to a respective package connector.

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Номер записи: 54
05-04-2018 дата публикации

METALIZATION REPAIR IN SEMICONDUCTOR WAFERS

Номер: US20180096858A1
Автор: Clevenger Lawrence A., II John E., Li Baozhen, Peterson Kirk D., Sheets
Принадлежит:

Embodiments are directed to a method for repairing features of a host semiconductor wafer. The method includes forming a feature of the host semiconductor wafer, wherein the feature includes a first conductive material and a surface having a planar region and non-planar regions. The method further includes forming a metal conductive liner over the non-planar regions. The method further includes applying a second conductive material metal layer over said the conductive liner. The method further includes recessing the second conductive material to be substantially planar with the planar region. 1. A method for repairing features of a host semiconductor wafer , the method comprising:forming a feature of the host semiconductor wafer, wherein forming the feature comprises one or more operations configured to planarize an exposed surface of the feature, wherein implementing the one or more operations results in the feature comprising a first conductive material and the exposed surface, wherein the exposed surface formed by the one or more operations comprises a planar region and unintended defects comprising unintended non-planar regions;forming a conductive liner over at least the non-planar regions;applying a second conductive material over at least the conductive liner; andrecessing the second conductive material to be substantially planar with the planar region.2. The method of claim 1 , wherein the first conductive material comprises copper.3. The method of claim 1 , wherein the conductive liner comprises tantalum claim 1 , cobalt claim 1 , ruthenium claim 1 , or nitrides thereof.4. The method of claim 1 , wherein recessing the second conductive material comprises applying a chemical mechanical planarization (CMP) to the second conductive material.5. The method of claim 1 , wherein the conductive liner comprises a thickness dimension within a range from about 10 nanometers to about 300 nanometers.6. The method of claim 1 , wherein the second conductive material ...

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Номер записи: 55
05-04-2018 дата публикации

METALIZATION REPAIR IN SEMICONDUCTOR WAFERS

Номер: US20180096902A1
Автор: Clevenger Lawrence A., II John E., Li Baozhen, Peterson Kirk D., Sheets
Принадлежит:

Embodiments are directed to a method for repairing features of a host semiconductor wafer. The method includes forming a feature of the host semiconductor wafer, wherein the feature includes a first conductive material and a surface having a planar region and non-planar regions. The method further includes forming a metal conductive liner over the non-planar regions. The method further includes applying a second conductive material metal layer over said the conductive liner. The method further includes recessing the second conductive material to be substantially planar with the planar region. 1. A method for repairing features of a host semiconductor wafer , the method comprising:forming a feature of the host semiconductor wafer, wherein the feature comprises a first conductive material and a surface having a planar region and non-planar regions;determining a defect level of the feature, wherein the defect level corresponds to a characteristic of the non-planar regions;comparing the defect level to a threshold;applying a first repair methodology to the feature if the defect level is below the threshold; andapplying a second repair methodology to the feature if the defect level is above the threshold.2. The method of claim 1 , wherein the second repair methodology comprises:forming a conductive liner over at least the non-planar regions;applying a second conductive material over at least the conductive liner; andrecessing the second conductive material to be substantially planar with the planar region.3. The method of claim 2 , wherein the first conductive material comprises copper.4. The method of claim 2 , wherein the conductive liner comprises tantalum claim 2 , cobalt claim 2 , ruthenium claim 2 , or nitrides thereof.5. The method of claim 2 , wherein recessing the second conductive material comprises applying a chemical mechanical planarization (CMP) to the second conductive material.6. The method of claim 2 , wherein the conductive liner comprises a thickness ...

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Номер записи: 56
06-04-2017 дата публикации

METHOD OF OPTIMIZING WIRE RC FOR DEVICE PERFORMANCE AND RELIABILITY

Номер: US20170098577A1
Автор: Clevenger Lawrence A., II John E., Li Baozhen, Peterson Kirk D., Sheets, Spooner Terry A.
Принадлежит:

A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is analyzed. The analysis comprises calculating Vmax for vias and metal lines in the integrated circuit design over a range of sizes for the vias and the metal lines. Predicted use voltage for applications on the integrated circuit chip is determined. The size or the location of at least one of the vias and the metal lines is tailored based on performance parameters of the integrated circuit chip. 1. A method comprising:analyzing an integrated circuit design on an integrated circuit chip, said analyzing comprising calculating Vmax for vias and metal lines in said integrated circuit design over a range of sizes for said vias and said metal lines;determining predicted use voltage for applications on said integrated circuit chip; andtailoring one of the size and the location of at least one of said vias and said metal lines based on performance parameters of said integrated circuit chip.2. The method according to claim 1 , further comprising:comparing said predicted use voltage to said Vmax calculated for said vias and said metal lines.3. The method according to claim 1 , said tailoring comprising creating a modified circuit design based on performance parameters of said integrated circuit chip using selected sizes of said vias and said metal lines.4. The method according to claim 3 , further comprising:printing and etching said vias and said metal lines according to said modified circuit design.5. The method according to claim 1 , said determining said predicted use voltage comprising using test and inline data to predict the use voltage that said integrated circuit chip will actually experience in applications.6. The method according to claim 5 , said determining said predicted use voltage being done on lot claim 5 , wafer claim 5 , or chip basis.7. A method claim 5 , in a data processing system claim 5 , of ...

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Номер записи: 57
30-04-2015 дата публикации

SELF-CORRECTING POWER GRID FOR SEMICONDUCTOR STRUCTURES METHOD

Номер: US20150115400A1
Автор: Christiansen Cathryn J., Norfleet Andrew H., Peterson Kirk D., Turner Andrew A.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect. 1. A self-correcting power grid for a semiconductor structure , the power grid comprising: 'a plurality of metal lines, each of the plurality of metal lines positioned substantially parallel to one another and positioned substantially perpendicular to a plurality of distinct metal lines in an adjacent interconnect layer;', 'a plurality of interconnect layers, each of the plurality of interconnect layers includinga plurality of vias for electrically connecting each of the plurality of interconnect layers; anda plurality of fuses positioned substantially adjacent to each of the plurality of vias, the plurality of fuses formed within each of the plurality of metal lines of each of the plurality of interconnect layers,wherein at least one of the plurality of fuses positioned immediately adjacent to a defect included in at least one of the plurality of interconnect layers is configured to blow during a testing process to isolate the defect.2. The power grid of claim 1 , wherein the plurality of metal lines of the plurality of interconnect layers include:a plurality of voltage ...

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Номер записи: 58
30-04-2015 дата публикации

THERMAL ENERGY DISSIPATION USING BACKSIDE THERMOELECTRIC DEVICES

Номер: US20150115431A1
Автор: Chadwick Nathaniel R., Gambino Jeffrey P., Peterson Kirk D.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Embodiments of the present invention provide a semiconductor structure and method to dissipate heat generated by semiconductor devices by utilizing backside thermoelectric devices. In certain embodiments, the semiconductor structure comprises an electronic device formed on a first side of the semiconductor structure. The semiconductor structure also comprises a thermoelectric cooling device formed on a second side of the semiconductor structure in close proximity to a region of the semiconductor structure where heat dissipation is desired, wherein the thermoelectric cooling device includes a Peltier junction. In other embodiments, the method comprises forming an electronic device on a first side of a semiconductor structure. The method also comprises forming a thermoelectric cooling device on a second side of the semiconductor structure in close proximity to a region of the semiconductor structure where heat dissipation is desired, wherein the thermoelectric cooling device includes a Peltier junction. 1. A semiconductor structure comprising:an electronic device formed on a first side of the semiconductor structure; anda thermoelectric cooling device formed on a second side of the semiconductor structure in close proximity to a region of the semiconductor structure where heat dissipation is desired, wherein the thermoelectric cooling device includes a Peltier junction.2. The semiconductor structure of claim 1 , wherein the thermoelectric cooling device includes thermoelectric material.3. The semiconductor structure of claim 2 , wherein the thermoelectric cooling device includes two or more Peltier junctions that are connected by TiN/Al claim 2 , aluminum claim 2 , and/or Ti/Cu.4. The semiconductor structure of claim 1 , wherein the thermoelectric cooling device is configured to be energized using a through silicon via that extends from the thermoelectric cooling device to contacts on the first side of the semiconductor structure.5. The semiconductor structure of ...

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Номер записи: 59
10-07-2014 дата публикации

SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING

Номер: US20140191359A1
Автор: Barth, Ho Herbert L., JR. John E., Khan Babar A., Peterson Kirk D.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer. 1. A semiconductor-on-oxide wafer comprising:a substrate;a first dielectric layer over the substrate;a first conductive layer over the first dielectric layer;a second dielectric layer over the first dielectric layer;a second conductive layer over a portion of the second dielectric layer, the second conductive layer including a separation;a third dielectric layer over the second conductive layer; anda contact extending through the third dielectric layer and the separation in the second conductive layer contacting the first conductive layer.2. The wafer of claim 1 , wherein the contact includes at least one of tungsten claim 1 , copper or polysilicon.3. The wafer of claim 1 , wherein the second conductive layer includes an additional separation claim 1 , and the first conductive layer includes a separation aligned with the additional separation in the second conductive layer.4. The wafer of claim 3 , further comprising a second contact extending through the additional separation in the second conductive layer and the separation in the first conductive layer.5. The wafer of claim 4 , wherein the second contact contacts the substrate.6. The wafer of claim 5 , wherein the second ...

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Номер записи: 60
10-07-2014 дата публикации

ON CHIP ELECTROSTATIC DISCHARGE (ESD) EVENT MONITORING

Номер: US20140191778A1
Автор: DeForge John B., Li Junjun, Loiseau Alain F., Peterson Kirk D.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

An approach for monitoring electrostatic discharge (ESD) event of an integrated circuit. The approach includes a canary device for exhibiting an impedance shift when affected by an ESD pulse, wherein circuit drain of the canary device is connected to an input terminal of the circuit structure. The approach further includes circuit source and logic gates of the canary device, connected to a circuit drain of ESD transistor of the circuit structure, wherein circuit source of the ESD transistor is connected to an output terminal of the circuit structure. The approach further includes a logic gate of the ESD transistor, connected to an enable signal of the circuit structure, and wherein the enable signal is connected to the output terminal through a capacitor of the circuit structure. In addition, the enable signal is also connected to the input terminal through a resistor of the circuit structure. 1. A circuit structure for monitoring an electrostatic discharge (ESD) event in a manufacturing environment of an integrated circuit package , the circuit structure comprising: wherein circuit drain of the canary device is connected to an input terminal of the circuit structure; and', 'wherein circuit source and logic gates of the canary device are connected to a circuit drain of ESD transistor of the circuit structure, wherein circuit source of the ESD transistor is connected to an output terminal of the circuit structure, wherein logic gate of the ESD transistor is connected to an enable signal of the circuit structure, and wherein the enable signal is connected to the output terminal through a capacitor of the circuit structure, and wherein the enable signal is also connected to the input terminal through a resistor of the circuit structure., 'a canary device for exhibiting an impedance shift when affected by an ESD pulse of the ESD event,'}2. The circuit structure according to claim 1 , wherein the circuit structure comprises multiple canary devices for monitoring the ESD ...

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Номер записи: 61
04-05-2017 дата публикации

WAVEGUIDE SWITCH WITH TUNED PHOTONIC MICRORING

Номер: US20170123290A1
Автор: Ellis-Monaghan John J., Gambino Jeffrey P., Jaffe Mark D., Peterson Kirk D., Rankin Jed H.
Принадлежит:

Various particular embodiments include an optical structure, including: a photonic microring including an integral signal detector for detecting a level of an optical signal in the photonic microring; and a controller, coupled to the signal detector, for selectively adjusting a resonant frequency of the photonic microring based on the detected level of the optical signal in the photonic microring. 2. The optical structure according to claim 1 , wherein the microcontroller applies a voltage bias to the photonic microring to adjust the resonant frequency of the photonic microring.3. The optical structure according to claim 1 , further comprising at least one component for heating the photonic microring to adjust the resonant frequency of the photonic microring.4. The optical structure according to claim 3 , wherein the at least one component comprises a resistor claim 3 , and wherein the microcontroller applies a voltage bias to the resistor.5. The optical structure according to claim 1 , wherein the microcontroller adjusts the resonant frequency of the photonic microring such that is equal to a frequency of an optical signal in an adjacent structure to increase coupling between the photonic microring and the adjacent structure.6. The optical structure according to claim 1 , wherein the microcontroller adjusts the resonant frequency of the photonic microring such that is not equal to a frequency of an optical signal in an adjacent structure to decrease coupling between the photonic microring and the adjacent structure.7. The optical structure according to claim 1 , wherein the signal detector comprises a germanium (Ge) signal detector.9. The optical switch according to claim 8 , wherein the microcontroller applies a voltage bias to the photonic microring to adjust the resonant frequency of the photonic microring.10. The optical switch according to claim 8 , further comprising at least one component for heating the photonic microring to adjust the resonant frequency of ...

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Номер записи: 62
16-04-2020 дата публикации

STEP PYRAMID SHAPED STRUCTURE TO REDUCE DICING DEFECTS

Номер: US20200118942A1
Автор: LI SHIDONG, Peterson Kirk D., Pizzuti Nicolas, Shaw Thomas M., Wassick Thomas A.
Принадлежит:

A semiconductor device which includes a substrate having integrated circuits; and metallization layers on the substrate, the metallization layers having a peripheral region adjacent to a kerf region of the semiconductor device and containing a crack stop structure. The crack stop structure includes a bottom portion containing a plurality of the metallization layers connected by vias with each metallization layer decreasing in width in a step pyramid structure from a bottom of the bottom portion to a top of the bottom portion; and a top portion containing a top metallization layer of the metallization layers connected to the bottom portion, the top metallization layer being wider than a top-most metallization layer of the bottom portion and having a segment that extends toward the kerf region so as to create an overhang with respect to the bottom portion. 1. A semiconductor device comprising:a substrate having integrated circuits;metallization layers on the substrate, the metallization layers having a peripheral region adjacent to a kerf region of the semiconductor device and containing a crack stop structure comprising:a bottom portion containing a plurality of the metallization layers connected by vias with each metallization layer decreasing in width in a step pyramid structure from a bottom of the bottom portion to a top of the bottom portion; anda top portion containing a top metallization layer of the metallization layers connected to the bottom portion, the top metallization layer being wider than a top-most metallization layer of the bottom portion and having a segment that extends toward the kerf region so as to create an overhang with respect to the bottom portion;wherein the vias that connect each metallization layer to an adjacent metallization layer are spaced entirely across each metallization layer immediately above the vias.2. The semiconductor device of wherein the outermost via on each metallization layer of the bottom portion is aligned with an ...

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Номер записи: 63
25-05-2017 дата публикации

SEMICONDUCTOR VIA STRUCTURE WITH LOWER ELECTRICAL RESISTANCE

Номер: US20170148673A1
Автор: Clevenger Lawrence A., Li Baozhen, Peterson Kirk D., Spooner Terry A., Wang Junli
Принадлежит:

A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via. 120.- (canceled)21. A method for forming a device , the method comprising:forming a first liner material in a first insulator layer;depositing a first conductive material in the first insulator layer to form a first conductive line;depositing an insulator material on the first conductive line;forming a channel in the insulator material;removing a portion of the insulator material in channel to expose a portion of the first conductive line;depositing a second liner material in the channel and over the exposed portion of the first conductive line;removing a portion of the second liner material to expose a portion of the first conductive line;depositing a via material on the exposed portion of the first conductive line and in the channel;depositing a third liner material over the via material and the second liner material in the channel; anddepositing a second conductive material in the channel.22. The method of claim 21 , wherein the first liner material and the second liner material may be independently selected from the group consisting of titanium claim 21 , titanium nitride claim 21 , tungsten claim 21 , titanium tungsten claim 21 , tungsten nitride claim 21 , tantalum claim 21 , TaN claim 21 , TaN/Ta claim 21 , Ta/TaN claim 21 , Ta/TaN/Ta claim 21 , or combinations thereof.23. The method of claim 21 , wherein the via material includes a conductive material. The present invention relates to structures, and more specifically, to via structures preventing the creation of ...

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Номер записи: 64
16-05-2019 дата публикации

MANAGED INTEGRATED CIRCUIT POWER SUPPLY DISTRIBUTION

Номер: US20190148284A1
Автор: Aipperspach Anthony G., Brown Jeffrey D., II John E., Peterson Kirk D., Sheets
Принадлежит:

An integrated circuit (IC) can be configured to provide managed power distribution to circuits within a plurality of regions of the IC. Each region of the plurality of regions can include a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within the region. A global power distribution structure within the IC can be configured to be electrically interconnected to an off-chip voltage supply. The IC can also include a plurality of sets of vertical interconnects (VIs), each set of VIs electrically interconnected to a VPI within a corresponding region. Each set of VIs can also be connected to the global power distribution structure, and can be used to provide a specified, managed voltage, through a VPI, to a set of circuits within a corresponding region of the IC. 1. An integrated circuit (IC) configured to provide managed power distribution to circuits within a plurality of regions of the IC , the IC comprising:the plurality of regions of the IC, each region of the plurality of regions including a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within the each region;a global power distribution structure configured to be electrically interconnected to an off-chip voltage supply; anda plurality of sets of vertical interconnects (VIs), each set of VIs of the plurality of sets of VIs being electrically interconnected to a corresponding VPI within a corresponding region of the plurality of regions, each set of VIs of the plurality of sets of VIs also being connected to the global power distribution structure.2. The IC of claim 1 , wherein each set of VIs of the plurality of sets of VIs includes at least one via electrically interconnected to the global power distribution structure on a first wiring plane of the IC and to a VPI on a second wiring plane of the IC.3. The IC of claim 1 , further comprising at least one horizontal interconnect (HI) electrically ...

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Номер записи: 65
07-06-2018 дата публикации

METHOD OF OPTIMIZING WIRE RC FOR DEVICE PERFORMANCE AND RELIABILITY

Номер: US20180158731A1
Автор: Clevenger Lawrence A., II John E., Li Baozhen, Peterson Kirk D., Sheets, Spooner Terry A.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is analyzed. The analysis comprises calculating Vmax for vias and metal lines in the integrated circuit design over a range of sizes for the vias and the metal lines. Predicted use voltage for applications on the integrated circuit chip is determined. The size or the location of at least one of the vias and the metal lines is tailored based on performance parameters of the integrated circuit chip. 1. A computer program product for tailoring BEOL RC parametrics to improve chip performance in an integrated circuit design , said computer program product comprising a computer readable storage medium having program instructions embodied therewith , the program instructions being readable and executable by a computerized device to cause said computerized device to perform a method comprising:analyzing a circuit design for an integrated circuit chip, said analyzing comprising determining Vmax for vias and metal lines in said circuit design over a range of sizes for said vias and metal lines, Vmax defining spacing between features on the integrated circuit chip due to time dependent dielectric breakdown based on-device characteristics;determining predicted use voltage for applications on said integrated circuit chip;comparing said predicted use voltage to said Vmax determined for said vias and metal lines; andcreating a modified circuit design based on performance parameters of said integrated circuit chip, said modified circuit design using a lower voltage for Vmax.2. The computer program product according to claim 1 , said method further comprising:tailoring the size or the location of at least one of said vias and said metal lines based on performance parameters of said integrated circuit chip.3. The computer program product according to claim 1 , said method further comprising:providing printing and etching ...

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Номер записи: 66
29-09-2022 дата публикации

MULTICOMPONENT MODULE DESIGN AND FABRICATION

Номер: US20220308564A1
Автор: Allard Stephanie E, Bachand Jean-Francois, Blanchard Denis, Casey Jon Alfred, Chun Sungjun, Dreps Daniel M., Gagnon Pascale, Labonte Jean, Ostrander Steven Paul, Peterson Kirk D., Pharand Sylvain, Quinlan Brian W., Reynolds Charles L., Turnbull David Edward
Принадлежит:

Multicomponent module assembly by identifying a failed site on a laminate comprising a plurality of sites, adding a machine discernible mark associated with the failed site, placing an electrically good element at a successful site; and providing an MCM comprising the laminate, and the electrically good element. 1. A method for multicomponent module assembly , the method comprising:identifying, by one or more computer processors, a failed site on a laminate comprising a plurality of sites;adding, a machine discernible mark associated with the failed site;placing, an electrically good element at a successful site; andproviding, a multicomponent module (MCM) comprising the laminate, the failed site, and the electrically good element.2. The method according to claim 1 , further comprising:placing a mechanically good element at the failed site.3. The method according to claim 1 , further comprising:receiving, by the one or more computer processors, a definition for at least one region for at least one layer of the laminate;receiving, by the one or more computer processors, inspection criteria for the at least one region;inspecting the at least one region according to the inspection criteria; andidentifying a failed site according to the inspection.4. The method according to claim 1 , further comprising updating claim 1 , by the one or more computer processors claim 1 , a database entry associated with the laminate according to the failed site.5. The method according to claim 1 , further comprising receiving claim 1 , by the one or more computer processors claim 1 , an overall success criteria for the MCM; and accepting claim 1 , by the one or more computer processors claim 1 , the MCM according to the overall success criteria.6. A method for multicomponent module (MCM) assembly claim 1 , the method comprising:identifying, by one or more computer processors, a failed site on a laminate comprising a plurality of sites using an automated inspection;adding a machine ...

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Номер записи: 67
02-07-2015 дата публикации

Signal monitoring of through-wafer vias using a multi-layer inductor

Номер: US20150185273A1
Автор: Keith C. Stevens, Kirk D. Peterson, Mark A. DiRocco, Norman W. Robson
Принадлежит: International Business Machines Corp

According to a method herein, a multi-level inductor is created around a through-silicon-via (TSV) in a semiconductor substrate. A voltage induced in the multi-level inductor by current flowing in the TSV is sensed, using a computerized device. The voltage is compared to a reference voltage, using the computerized device. An electrical signature of the TSV is determined based on the comparing the voltage to the reference voltage, using the computerized device.

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Номер записи: 68
28-06-2018 дата публикации

Structure and method for fully depleted silicon on insulator structure for threshold voltage modification

Номер: US20180182778A1
Автор: John J. Ellis-Monaghan, Kirk D. Peterson, Terence B. Hook
Принадлежит: Globalfoundries Inc

A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.

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Номер записи: 69
20-06-2019 дата публикации

THREE-DIMENSIONAL STACKED MEMORY OPTIMIZATIONS FOR LATENCY AND POWER

Номер: US20190187915A1
Автор: Chinnakkonda Vidyapoornachary Diyanesh B., DeForge John B., Maule Warren E., Peterson Kirk D., Rangarajan Sridhar H., Sethuraman Saravanan
Принадлежит:

An aspect includes receiving a request to write data to a memory that includes a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). The write request is received by a hypervisor from an application executing on a virtual machine managed by the hypervisor. In response to receiving the request a latency requirement of accesses to the write data is determined. A physical location on a memory device in the stack of memory devices is assigned to the write data based at least in part on the latency requirement and a position of the memory device in the stack of memory devices. A write command that includes the physical location and the write data is sent to a memory controller. 1. A method comprising:receiving a request to write data to a memory, the memory comprising a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV), the request to write data received by a hypervisor from an application executing on a virtual machine managed by the hypervisor; and determining a latency requirement of accesses to the write data;', 'assigning a physical location on a memory device in the stack of memory devices to the write data, the assigning based at least in part on the latency requirement, a predicted power consumption of the write data, and a position of the memory device in the stack of memory devices; and', 'sending a write command to a memory controller, the write command including the physical location and the write data., 'in response to receiving the request2. The method of claim 1 , wherein the request includes a tag that specifies the latency requirement.3. The method of claim 1 , further comprising determining a predicted access frequency of the write data claim 1 , wherein the assigning is further based at least in part on the predicted access ...

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Номер записи: 70
20-06-2019 дата публикации

THREE-DIMENSIONAL STACKED MEMORY ACCESS OPTIMIZATION

Номер: US20190187930A1
Автор: Chinnakkonda Vidyapoornachary Diyanesh B., DeForge John B., Maule Warren E., Peterson Kirk D., Rangarajan Sridhar H., Sethuraman Saravanan
Принадлежит:

An aspect includes receiving a request to access one or more memory devices in a stack of memory devices in a memory. Each of the memory devices are communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). A current operating mode of the memory is determined in response to receiving the request. Based at least in part on the current operating mode of the memory being a first mode, a chip select switch is activated to provide access to exactly one of the memory devices in the stack of memory devices. Based at least in part on the current operating mode of the memory being a second mode, the chip select switch is activated to access all of the memory devices in the stack in parallel. The request is serviced using the activated chip select switch. 1. A method comprising:receiving a request to access one or more memory devices in a stack of memory devices in a memory, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV); and determining a current operating mode of the memory;', 'based at least in part on the current operating mode of the memory being a first mode, activating a chip select switch to provide access to exactly one of the memory devices in the stack of memory devices;', 'based at least in part on the current operating mode of the memory being a second mode, activating the chip select switch to access all of the memory devices in the stack in parallel; and', 'servicing the request using the activated chip select switch., 'in response to receiving the request2. The method of claim 1 , wherein the request includes a requested operating mode of the memory and the method further comprises claim 1 , based at least in part on the current operating mode of the memory not matching the requested operating mode of the memory claim 1 , changing the current operating mode of the memory to the requested operating mode of the ...

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Номер записи: 71
19-07-2018 дата публикации

METHOD AND STRUCTURES FOR PERSONALIZING LITHOGRAPHY

Номер: US20180203341A1
Автор: DeForge John B., Hamieh Bassem M., Hook Terence B., Newton Theresa A., Peterson Kirk D.
Принадлежит:

After printing common features from a primary mask into a photoresist layer located over a substrate, a functional feature which is suitable for changing functionalities or the configurations of the common features according to a chip design is selected from a library of additional functional features in a secondary mask. The selected functional feature from the secondary mask is printed into the photoresist layer to modify the common features that already exist in the photoresist layer. The selection and printing of functional feature processes can be repeated until a final image corresponding to the chip design is obtained in the photoresist layer. 1. A method for printing a pattern on a substrate comprising:providing a primary mask comprising common features of a chip at a given mask level;exposing a photoresist layer located on the substrate through the primary mask to print the common features in the photoresist layer;providing a secondary mask comprising a library of functional features for personalizing the common features in the photoresist layer at the given mask level according to a chip design;selecting a functional feature in the library of the functional features of the secondary mask to modify at least one common feature in the photoresist layer; andexposing the photoresist layer through the secondary mask to print the selected functional feature in the photoresist layer.2. The method of claim 1 , further comprising:selecting another functional feature in the library of the functional features of the secondary mask according to the chip design to modify at least one another common feature in the photoresist layer;exposing the photoresist layer through the secondary mask to print the selected another functional feature in the photoresist layer; andrepeating the above steps until personalized features according to the chip design are formed in the photoresist layer.3. The method of claim 2 , further comprising developing the photoresist layer after the ...

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Номер записи: 72
18-06-2020 дата публикации

CONTACTS HAVING A GEOMETRY TO REDUCE RESISTANCE

Номер: US20200194371A1
Автор: Clevenger Lawrence A., Li Baozhen, Peterson Kirk D., Spooner Terry A., Wang Junli
Принадлежит:

A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dielectric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region. 1. An electrical contact comprising:a first contact portion extending through an intralevel dielectric to a semiconductor device, wherein an upper surface of the first contact portion that is opposing a surface of the first contact portion that is in contact with the semiconductor device has a planar upper surface;a second contact portion having an exterior surface defined by a curvature and a width greater than the first contact portion, wherein the curvature of the second contact portion has a greater surface area than the planar upper surface of the first contact portion; anda third contact portion in direct contact with the second contact portion that encapsulates the second contact portion.2. The electrical contact of claim 1 , wherein the first contact portion is a stud having sidewalls with a length substantially perpendicular to an upper surface of source and drain portions of the semiconductor device.3. The electrical contact of claim 2 , wherein the first contact portion comprises tungsten (W) claim 2 , cobalt (Co) claim 2 , ruthenium (Ru) claim 2 , titanium (Ti) claim 2 , aluminum (Al) claim 2 , copper (Cu) and combinations thereof.4. The electrical contact of claim 1 , further comprising a liner of a metal nitride on external surfaces of the first contact portion that are not in direct contact with ...

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Номер записи: 73
18-07-2019 дата публикации

OPTIMIZING ERROR CORRECTING CODE IN THREE-DIMENSIONAL STACKED MEMORY

Номер: US20190220351A1
Автор: Chinnakkonda Vidyapoornachary Diyanesh B., DeForge John B., Peterson Kirk D., RANGARAJAN SRIDHAR, Sethuraman Saravanan
Принадлежит:

Optimizing error correcting code (ECC) in three-dimensional (3D) stacked memory including selecting, as an ECC memory chip, a memory chip of a plurality of memory chips in a 3D stacked memory structure, wherein the 3D stacked memory structure comprises the plurality of memory chips stacked vertically and coupled together using through-silicon vias; determining that an error has been detected in one of the plurality of memory chips in the 3D stacked memory structure; selecting, based on the detected error, an order of an ECC decoder of the ECC stored in the ECC memory chip; and correcting the detected error in the 3D stacked memory structure using the ECC stored in the ECC memory chip. 1. A method of optimizing error correcting code (ECC) in three-dimensional (3D) stacked memory , the method comprising:selecting, as an ECC memory chip, a memory chip of a plurality of memory chips in a 3D stacked memory structure, wherein the 3D stacked memory structure comprises the plurality of memory chips stacked vertically and coupled together using through-silicon vias;determining that an error has been detected in one of the plurality of memory chips in the 3D stacked memory structure;selecting, based on the detected error, an order of an ECC decoder of the ECC stored in the ECC memory chip; andcorrecting the detected error in the 3D stacked memory structure using the ECC stored in the ECC memory chip.2. The method of claim 1 , wherein selecting claim 1 , based on the detected error claim 1 , the order of the ECC decoder comprises one selected from a group consisting of selecting a high order ECC decoder and selecting a low order ECC decoder.3. The method of claim 1 , wherein the plurality of memory chips comprises at least two types of memory chips.4. The method of claim 1 , further comprising:in response to selecting, based on the detected error, the order of the ECC decoder of the ECC, allocating an unused portion of the ECC memory chip for mainline data storage.5. The ...

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Номер записи: 74
30-10-2014 дата публикации

Vertical bend waveguide coupler for photonics applications

Номер: US20140321801A1
Автор: Jed H. Rankin, Jeffrey P. Gambino, John J. Ellis-Monaghan, Kirk D. Peterson, Mark D. Jaffe
Принадлежит: International Business Machines Corp

An optical waveguide structure may include a dielectric layer having a top surface, an optical waveguide structure, and an optical coupler embedded within the dielectric layer. The optical coupler may have both a substantially vertical portion that couples to the top surface of the dielectric layer and a substantially horizontal portion that couples to the optical waveguide structure. The substantially vertical portion and the substantially horizontal portion are separated by a curved portion.

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Номер записи: 75
30-10-2014 дата публикации

VERTICALLY CURVED WAVEGUIDE

Номер: US20140321802A1
Автор: Ellis-Monaghan John J., Gambino Jeffrey P., Jaffe Mark D., Peterson Kirk D., Rankin Jed H.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

An optical waveguide structure may include an optical waveguide structure located within a semiconductor structure and an optical coupler. The optical coupler may include a metallic structure located within an electrical interconnection region of the semiconductor structure, whereby the metallic structure extends downward in a substantially curved shape from a top surface of the electrical interconnection region and couples to the optical waveguide structure. The optical coupler may further include an optical signal guiding region bounded within the metallic structure, whereby the optical coupler receives an optical signal from the top surface and couples the optical signal to the optical waveguide structure such that the optical signal propagation is substantially vertical at the top surface and substantially horizontal at the optical waveguide structure. 1. A waveguide structure comprising:an optical waveguide structure located within a semiconductor structure; and a metallic structure located within an electrical interconnection region of the semiconductor structure, the metallic structure extending downward in a substantially curved shape from a top surface of the electrical interconnection region and coupling to the optical waveguide structure, and', 'an optical signal guiding region bounded within the metallic structure,, 'an optical coupler includingwherein the optical coupler receives an optical signal from the top surface and couples the optical signal to the optical waveguide structure such that the optical signal propagation is substantially vertical at the top surface and substantially horizontal at the optical waveguide structure.2. The structure of claim 1 , wherein the optical coupler comprises a core region for guiding the optical signal.3. The structure of claim 2 , wherein metallic structure comprises a cladding region for the core region.4. The structure of claim 1 , wherein the metallic structure comprises:at least one metal structure having a ...

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Номер записи: 76
27-08-2015 дата публикации

METHOD OFSELF-CORRECTING A POWER GRID FOR SEMICONDUCTOR STRUCTURES

Номер: US20150243601A1
Автор: Christiansen Cathryn J., Norfleet Andrew H., Peterson Kirk D., Turner Andrew A.
Принадлежит:

Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect. 1. A method of self-correcting a power grid of a semiconductor structure , the method comprising: [ 'a plurality of metal lines, each of the plurality of metal lines positioned substantially parallel to one another and positioned substantially perpendicular to a plurality of distinct metal lines in an adjacent interconnect layer, and', 'a plurality of interconnect layers, each of the plurality of interconnect layers including, 'a plurality of fuses formed within each of the plurality of metal lines of each of the plurality of interconnect layers; and, 'providing the power grid of the semiconductor structure, the power grid including 'performing a stress-test on the semiconductor structure, the stress test including heating an ambient temperature of the semiconductor structure including the power grid above an operational ambient temperature of the semiconductor structure.', 'isolating a defect included in the power grid of the semiconductor structure by performing a testing process on the semiconductor structure including the power grid, the testing process blowing at least ...

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Номер записи: 77
10-09-2015 дата публикации

CIRCUIT DESIGN FOR BALANCED LOGIC STRESS

Номер: US20150253807A1
Автор: Chadwick Nathaniel R., Clougherty Frances S. M., Hovis William P., Peterson Kirk D., Riley Mack W.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

An electronic system is disclosed, which may include a phase pipeline, a data pipeline, an input phase selector, and an output phase selector. The phase pipeline may have latches clocked by a clock signal, and designed to propagate phase signals from a phase input to a phase output. The data pipeline may have latches clocked by the phase pipeline clock signal, and designed to propagate data from a data input to a data output. The input phase selector may be designed to provide an inverted or a non-inverted copy of data from a data input, in response to a value at the phase input, to the data pipeline data input. The output phase selector may be designed to provide an inverted or a non-inverted copy of data from the data pipeline output to an output phase selector data output, in response to a phase pipeline output value. 1. An electronic system comprising: a phase input;', 'a phase output; and', 'a plurality of series-connected latches designed to, in response to a clock signal, propagate phase signals from the phase input to the phase output;, 'a phase pipeline, having a data input;', 'a data output; and', 'a plurality of series-connected latches designed to, in response to the clock signal of the phase pipeline, propagate data from the data input to the data output;, 'a data pipeline, having in response to a first value at the phase input, non-inverted data from an input phase selector data input; and', 'in response to a second value at the phase input, an inverted copy of data from an input phase selector data input; and, 'an input phase selector, designed to provide to the data input of the data pipeline in response to the first value at the phase output of the phase pipeline, non-inverted data from the data output of the data pipeline; and', 'in response to the second value at the phase output of the phase pipeline, an inverted copy of data from the data output of the data pipeline., 'an output phase selector, designed to provide to an output phase selector ...

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Номер записи: 78
10-09-2015 дата публикации

CIRCUIT DESIGN FOR BALANCED LOGIC STRESS

Номер: US20150253808A1
Автор: Chadwick Nathaniel R., Clougherty Frances S. M., Hovis William P., Peterson Kirk D., Riley Mack W.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

An electronic system is disclosed, which may include a phase pipeline, a data pipeline, an input phase selector, and an output phase selector. The phase pipeline may have latches clocked by a clock signal, and designed to propagate phase signals from a phase input to a phase output. The data pipeline may have latches clocked by the phase pipeline clock signal, and designed to propagate data from a data input to a data output. The input phase selector may be designed to provide an inverted or a non-inverted copy of data from a data input, in response to a value at the phase input, to the data pipeline data input. The output phase selector may be designed to provide an inverted or a non-inverted copy of data from the data pipeline output to an output phase selector data output, in response to a phase pipeline output value. 1. A method to control field effect transistor (FET) stress in a device , the method comprising:setting a phase signal to a first logical value for a first time interval;clocking, in response to a first clock transition and to the first logical value of the phase signal, both a non-inverted data into a data pipeline and the first logical value into a phase pipeline;setting the phase signal to a second logical value for a second time interval;clocking, in response to a second clock transition and to the second logical value of the phase signal, both an inverted copy of the data into the data pipeline and the second logical value into the phase pipeline;clocking a data signal out of the data pipeline and a corresponding phase signal out of the phase pipeline;outputting, in response to a first logical value of the corresponding phase signal, a first phase of the data signal from the data pipeline; andoutputting, in response to a second logical value of the corresponding phase signal, a second phase of the data signal from the data pipeline.2. The method of claim 1 , wherein the device is a P-channel field-effect transistor (PFET) claim 1 , with a ...

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Номер записи: 79
10-09-2015 дата публикации

ENHANCEMENT OF ISO-VIA RELIABILITY

Номер: US20150255388A1
Автор: Clevenger Lawrence A., Li Baozhen, Liu Xiao H., Peterson Kirk D.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line and an ILD layer. A metal-filled via extends through the ILD layer to make contact with the wiring line. There is a reliability enhancement material that surrounds at least part of the via so as to render the via compressive where the via contacts the wiring line. The reliability enhancement material may be compressive as deposited or may be made compressive after deposition. 1. A semiconductor structure comprising:a semiconductor base comprising a plurality of semiconductor devices: a wiring line;', 'an interlayer dielectric (ILD) layer on the wiring line;', 'a via extending through the ILD to communicate with the wiring line;', 'a metal filling the via and in contact with the wiring line; and', 'a compressive reliability enhancement material surrounding at least part of the metal-filled via to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress., 'a back end of the line wiring layer comprising2. The semiconductor structure of wherein the reliability enhancement material surrounds the entire metal-filled via.3. The semiconductor structure of wherein the reliability enhancement material surrounds the metal-filled via in the cap and only in a portion of the ILD.4. The semiconductor structure of further comprising a cap layer between the wiring line and the ILD layer and wherein the reliability enhancement material surrounds the metal-filled via only in the cap layer.5. The semiconductor structure of wherein the reliability enhancement material surrounds the metal-filled via only in a portion of the ILD.6. The semiconductor structure of wherein the reliability enhancement material surrounds the metal-filled via only where the metal-filled via contacts the wiring line.7. The semiconductor structure of wherein the via has a via wall and further comprising a barrier layer on ...

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Номер записи: 80
09-09-2021 дата публикации

PERFORMANCE-SCREEN RING OSCILLATOR WITH SWITCHABLE FEATURES

Номер: US20210281248A1
Автор: DeForge John B., Hook Terence B., Newton Theresa, Peterson Kirk D., Turner Andrew
Принадлежит:

A method and performance-screen ring oscillator (PSRO) test structure for designing, testing, and manufacturing a VLSI device. The performance-screen ring oscillator (PSRO) test structure comprises a ring oscillator having a plurality of stages; one or more selectable loads, each selectable load being coupled to an output of a corresponding one of the stages of the ring oscillator; and one or more multiplexers, each multiplexer being coupled to at least one stage of the ring oscillator and being configured to select a configuration of the corresponding selectable load. 1. A performance-screen ring oscillator (PSRO) test structure , the performance-screen ring oscillator (PSRO) test structure comprising:a ring oscillator having a plurality of stages;two or more selectable loads, each selectable load configured to be selectively coupled to an output of a corresponding stage of the ring oscillator; andone or more multiplexers, an output of each multiplexer being coupled to an output of at least one stage of the ring oscillator and at least two inputs of each multiplexer being coupled to a corresponding one of the selectable loads, the multiplexer being configured to connect one of the selectable loads to the output of the corresponding stage of the ring oscillator.2. A performance-screen ring oscillator (PSRO) test structure , the performance-screen ring oscillator (PSRO) test structure comprising:a ring oscillator having a plurality of stages;one or more selectable loads, each selectable load being coupled to an output of a corresponding one of the stages of the ring oscillator; andone or more multiplexers, each multiplexer being coupled to an output of at least one stage of the ring oscillator and being configured to select a configuration of the corresponding selectable load, wherein the selectable load in a first mode is a 180 degree out-of-phase signal.3. The performance-screen ring oscillator test structure of claim 2 , wherein at least one multiplexer couples an ...

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Номер записи: 81
14-09-2017 дата публикации

CONTACTS HAVING A GEOMETRY TO REDUCE RESISTANCE

Номер: US20170263557A1
Автор: Clevenger Lawrence A., Li Baozhen, Peterson Kirk D., Spooner Terry A., Wang Junli
Принадлежит:

A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dieletric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region. 1. An electrical contact comprising:a first contact portion extending through an intralevel dielectric to a semiconductor device, wherein an upper surface of the first contact portion that is opposing a surface of the first contact portion that is in contact with the semiconductor device has a planar upper surface;a second contact portion having an exterior surface defined by a curvature and a width greater than the first contact portion, wherein the curvature of the second contact portion has a greater surface area than the planar upper surface of the first contact portion; anda third contact portion in direct contact with the second contact portion that encapsulates the second contact portion.2. The electrical contact of claim 1 , wherein the first contact portion is a stud having sidewalls with a length substantially perpendicular to an upper surface of source and drain portions of the semiconductor device.3. The electrical contact of claim 2 , wherein the first contact portion comprises tungsten (W) claim 2 , cobalt (Co) claim 2 , ruthenium (Ru) claim 2 , titanium (Ti) claim 2 , aluminum (Al) claim 2 , copper (Cu) and combinations thereof.4. The electrical contact of further comprising a liner of a metal nitride on external surfaces of the first contact portion that are not in direct contact with the second ...

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Номер записи: 82
13-09-2018 дата публикации

CONTACTS HAVING A GEOMETRY TO REDUCE RESISTANCE

Номер: US20180261543A1
Автор: Clevenger Lawrence A., Li Baozhen, Peterson Kirk D., Spooner Terry A., Wang Junli
Принадлежит:

A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dieletric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region. 1. An electrical contact comprising:a first contact portion extending through an intralevel dielectric to a semiconductor device, wherein an upper surface of the first contact portion that is opposing a surface of the first contact portion that is in contact with the semiconductor device has a planar upper surface;a second contact portion having an exterior surface defined by a curvature and a width greater than the first contact portion, wherein the curvature of the second contact portion has a greater surface area than the planar upper surface of the first contact portion; anda third contact portion in direct contact with the second contact portion that encapsulates the second contact portion.2. The electrical contact of claim 1 , wherein the first contact portion is a stud having sidewalls with a length substantially perpendicular to an upper surface of source and drain portions of the semiconductor device.3. The electrical contact of claim 2 , wherein the first contact portion comprises tungsten (W) claim 2 , cobalt (Co) claim 2 , ruthenium (Ru) claim 2 , titanium (Ti) claim 2 , aluminum (Al) claim 2 , copper (Cu) and combinations thereof.4. The electrical contact of claim 1 , further comprising a liner of a metal nitride on external surfaces of the first contact portion that are not in direct contact with ...

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Номер записи: 83
18-12-2014 дата публикации

Methods for testing integrated circuits of wafer and testing structures for integrated circuits

Номер: US20140367684A1
Автор: Jeffrey P. Gambino, Kirk D. Peterson, Mark A. DiRocco, Michael T. Coster
Принадлежит: International Business Machines Corp

Aspects of the present invention relate to methods of testing an integrated circuit of a wafer and testing structures for integrated circuits. The methods include depositing a sacrificial material over a first conductor material of the integrated circuit, and contacting a test probe to the deposited sacrificial material. The methods can also include testing the integrated circuit using the test probe contacting the sacrificial material. Finally, the methods can include removing the sacrificial material over the first conductor material of the integrated circuit subsequent to the testing of the integrated circuit.

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Номер записи: 84
26-10-2017 дата публикации

Testing mechanism for a proximity fail probability of defects across integrated chips

Номер: US20170307685A1
Автор: Alain G. Rwabukamba, Andrew A. Turner, Kirk D. Peterson
Принадлежит: International Business Machines Corp

According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.

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Номер записи: 85
02-11-2017 дата публикации

Enhancement of iso-via reliability

Номер: US20170316970A1
Автор: Baozhen Li, Kirk D. Peterson, Lawrence A. Clevenger, Xiao H. Liu
Принадлежит: International Business Machines Corp

A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a cap layer and an ILD layer. A metal-filled via extends through the ILD layer to make contact with the wiring line. There is a reliability enhancement material in the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer. The reliability enhancement material may be compressive as deposited or may be made compressive after deposition.

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Номер записи: 86
24-09-2020 дата публикации

PASSIVE METHODS OF LOOSE DIE IDENTIFICATION

Номер: US20200305274A1
Автор: Hassan Tassbieh, Marz Eric, Peterson Kirk D., Pizzuti Nicolas, Rex Nathaniel, Whiteside Christine
Принадлежит:

Embodiments of the invention are directed to a method and resulting structures for identifying an integrated circuit (IC) chip using optically-unique features. In a non-limiting embodiment of the invention, an imaging device generates an image of the chip. One or more optical features of the chip within the image can be determined and stored in a local or remote database. Metadata associated with the chip can be generated and linked with the one or more optical features of the chip and a unique identifier of the chip in the database. 1. A method for identifying an integrated circuit (IC) chip , the method comprising:generating, with an imaging device, an image of the chip;determining one or more optical features of the chip within the image;storing the one or more optical features of the chip;determining metadata associated with the chip; andlinking the one or more optical features of the chip with the metadata and a unique identifier of the chip.2. The method of claim 1 , wherein the imaging device is a camera and the image comprises a high-resolution image of a portion of the chip.3. The method of claim 1 , wherein the image comprises a top surface claim 1 , a backside claim 1 , or an edge of the chip.4. The method of claim 1 , wherein the one or more optical features comprise a scrape or scratch shape claim 1 , size claim 1 , location claim 1 , or color claim 1 , a laser groove or dicing channel shape or dimension claim 1 , a C4 bump location claim 1 , shape claim 1 , size claim 1 , or color claim 1 , or a surface roughness on a backside of the chip claim 1 , a top surface of the chip claim 1 , or an edge of the chip.5. The method of claim 1 , wherein storing the one or more optical features of the chip further comprises:generating a candidate unique optical feature; andin response to determining that a database does not include a previously stored optical feature that matches the candidate unique optical feature, storing the candidate unique optical feature in ...

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Номер записи: 87
10-11-2016 дата публикации

IMMUNITY TO INLINE CHARGING DAMAGE IN CIRCUIT DESIGNS

Номер: US20160328513A1
Автор: Henderson Zachary, HIBBELER Jason D., Hook Terence B., Palmer Nicholas, Peterson Kirk D.
Принадлежит:

Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device. 1. A method of checking a design of an integrated circuit using an antenna rule , comprising: determining, by a computer device, a resistance of a gate path of the respective transistor;', 'determining, by the computer device, a resistance of a source/drain path of the respective transistor;', 'determining, by the computer device, a resistance of a shunt path of the respective transistor;', 'determining, by the computer device, a figure of merit for the respective transistor based on the resistance of the shunt path, the resistance of the gate path, and the resistance of the source/drain path; and', 'comparing, by the computer device, the figure of merit for the respective transistor to a limit., 'checking a subset of a plurality of transistors of the design of the integrated circuit using the antenna rule, wherein the checking comprises for each respective transistor in the subset2. The method of claim 1 , wherein the subset includes only transistors in which the gate path and the source/drain path each end at respective metal shapes other than vias.3. The method of claim 1 , wherein the subset includes only transistors that include a shunt path between a gate and a source/drain.4. The method of claim 1 , wherein the subset includes only transistors that include a shunt path comprising a semiconductor material between ...

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Номер записи: 88
10-11-2016 дата публикации

IMMUNITY TO INLINE CHARGING DAMAGE IN CIRCUIT DESIGNS

Номер: US20160329317A1
Автор: Henderson Zachary, HIBBELER Jason D., Hook Terence B., Palmer Nicholas, Peterson Kirk D.
Принадлежит:

Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device. 1. A semiconductor structure , comprising:a transistor comprising a gate and a source/drain;at least one first electrically conductive element;at least one second electrically conductive element;a first electrically conductive path from the gate to the at least one first electrically conductive element;a second electrically conductive path from the source/drain to the at least one second electrically conductive element; anda third electrically conductive path from the gate to the source/drain; [{'br': None, 'i': Rsd', 'Rsd+Rg+Rs', 'Rg+Rs', 'X,, '/()*1/()<'}, Rsd is the resistance of the second path;', 'Rs is the resistance of the third path; and', 'X is a pre-defined limit value., 'where: Rg is the resistance of the first path;'}], 'wherein the transistor satisfies the expression2. The semiconductor structure of claim 1 , wherein the at least one first electrically conductive element and the at least one second electrically conductive element each comprise one of a wire claim 1 , via claim 1 , and interconnect that is exposed to plasma during a manufacturing step of the semiconductor structure.3. The semiconductor structure of claim 1 , wherein:the first path comprises plural circuit elements connected between the gate to the at least one first electrically conductive element; andRg is a series resistance of the plural ...

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Номер записи: 89
01-10-2020 дата публикации

COMPRESSIVE ZONE TO REDUCE DICING DEFECTS

Номер: US20200312788A1
Автор: Peterson Kirk D., Pizzuti Nicolas, Shaw Thomas M., Wassick Thomas A.
Принадлежит:

A semiconductor device that includes a substrate having integrated circuits; a plurality of metallization layers on the substrate, the plurality of metallization layers having a peripheral region adjacent to a kerf region of the semiconductor device and containing a crack stop structure extending through the plurality of metallization layers; a trench extending through the plurality of metallization layers and adjacent to the crack stop structure, the trench filled with a material that creates compressive stresses between the filled trench and the adjacent metallization layers to form a compressive zone adjacent to the crack stop structure. Also disclosed is a method for forming the semiconductor device. 1. A semiconductor device comprising:a substrate having integrated circuits;a plurality of metallization layers on the substrate, the plurality of metallization layers having a peripheral region adjacent to a kerf region of the semiconductor device and containing a crack stop structure extending through the plurality of metallization layers;a trench extending through the plurality of metallization layers and adjacent to the crack stop structure, the trench filled with a material that creates compressive stresses between the filled trench and the adjacent metallization layers to form a compressive zone adjacent to the crack stop structure.2. The semiconductor device of wherein the material is an ion exchangeable glass having potassium or sodium ions.3. The semiconductor device of wherein the material is an oxide of tantalum or tungsten.4. The semiconductor device of wherein the material is silicon nitride that is in compression.5. The semiconductor device of wherein the material is a high coefficient of thermal expansion oxide compared to the coefficient of thermal expansion of the metallization layers that creates a compressive stress between the trench and the adjacent metallization layers.6. The semiconductor device of wherein the material is a low coefficient of ...

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Номер записи: 90
17-12-2015 дата публикации

SIGNAL MONITORING OF THROUGH-WAFER VIAS USING A MULTI-LAYER INDUCTOR

Номер: US20150362534A1
Автор: DiRocco Mark A., Peterson Kirk D., Robson Norman W., Stevens Keith C.
Принадлежит:

According to a method herein, a multi-level inductor is created around a through-silicon-via (TSV) in a semiconductor substrate. A voltage induced in the multi-level inductor by current flowing in the TSV is sensed, using a computerized device. The voltage is compared to a reference voltage, using the computerized device. An electrical signature of the TSV is determined based on the comparing the voltage to the reference voltage, using the computerized device. 1. A structure , comprising:a wafer comprising a multilayer silicon substrate;an active device in a layer of said multilayer silicon substrate;a through-silicon-via (TSV) structure extending through multiple levels of said multilayer silicon substrate and operatively attached to said active device;an inductor in said multilayer silicon substrate, said inductor surrounding said TSV through multiple levels of said multilayer silicon substrate; anda comparator having multiple inputs, a reference voltage being applied to a first input of said comparator,said inductor being connected to ground at a first end and connected to a second input of said comparator at a second end.2. The structure according to claim 1 , said inductor being connected to sensing signal at said first end and connected to said second input of said comparator at said second end.3. The structure according to claim 1 , further comprising:an amplifier operatively connected between said inductor and said comparator.4. The structure according to claim 1 , further comprising:a multiplexer operatively connected between said inductor and said comparator.5. The structure according to claim 4 , said multiplexer having multiple TSVs connected as inputs to said multiplexer and a single output to said comparator.6. The structure according to claim 4 , said multiplexer having multiple TSVs connected as inputs to said multiplexer and multiple outputs to said comparator.7. The structure according to claim 6 , said reference voltage comprising one of:a voltage ...

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Номер записи: 91
17-12-2015 дата публикации

ENHANCEMENT OF ISO-VIA RELIABILITY

Номер: US20150364365A1
Автор: Clevenger Lawrence A., Li Baozhen, Liu Xiao H., Peterson Kirk D.
Принадлежит:

A process of making a semiconductor structure. The process includes forming a wiring line; forming a reliability enhancement material on the wiring line; forming an interlayer dielectric (ILD) layer on the wiring line; forming a via opening through the ILD layer and reliability enhancement material to expose a surface of the wiring line; and filling the via opening with a metal to form a metal-filled via in contact with the wiring line wherein the reliability enhancement material is in direct contact with the metal-filled via; wherein the reliability enhancement material causes a compressive stress on the metal-filled via where it contacts the wiring line. Another embodiment includes the metal-filled via being an iso-via so that there is only one metal-filled via per wiring line. 1. A process of making a semiconductor structure comprising:forming a wiring line;forming a recess in the wiring line;filling the recess with a reliability enhancement material;forming a cap layer over the wiring line and the recess;forming an interlayer dielectric (ILD) layer on the cap layer;forming a via opening through the ILD layer, cap layer and reliability enhancement material to expose a surface of the wiring line; andfilling the via opening with a metal to form a metal-filled via in contact with the wiring line;wherein the reliability enhancement material causes a compressive stress on the metal-filled via where it contacts the wiring line.2. The process of wherein the reliability enhancement material is deposited so as to be compressive.3. The process of further comprising after forming a reliability enhancement material claim 1 , treating the reliability enhancement material so as to be compressive.4. A process of making a semiconductor structure comprising:forming a wiring line;forming a reliability enhancement material on the wiring line;forming an interlayer dielectric (ILD) layer on the wiring line;forming a via opening through the ILD layer and reliability enhancement ...

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Номер записи: 92
14-11-2019 дата публикации

MANAGED INTEGRATED CIRCUIT POWER SUPPLY DISTRIBUTION

Номер: US20190348361A1
Автор: Aipperspach Anthony G., Brown Jeffrey D., II John E., Peterson Kirk D., Sheets
Принадлежит:

An integrated circuit (IC) can be configured to provide a managed power distribution to circuits within a plurality of regions of the IC. Each region of the plurality of regions can include a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within said each region. A global power distribution structure within the IC can be configured to be electrically interconnected to an off-chip voltage supply. The IC can also include a plurality of sets of vertical interconnects (VIs), each set of VIs electrically interconnected to a VPI within a corresponding region. Each set of VIs can also be connected to the global power distribution structure, and can be used to provide a specifically managed voltage through a VPI to a set of circuits within a corresponding region of the IC. 1. An integrated circuit (IC) configured to provide managed power distribution to circuits within a plurality of regions of the IC , the IC comprising:the plurality of regions of the IC, each region of the plurality of regions including a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within the each region;a global power distribution structure configured to be electrically interconnected to an off-chip voltage supply; anda plurality of sets of vertical interconnects (VIs), each set of VIs of the plurality of sets of VIs being electrically interconnected to a corresponding VPI within a corresponding region of the plurality of regions, each set of VIs of the plurality of sets of VIs also being connected to the global power distribution structure.2. The IC of claim 1 , wherein each set of VIs of the plurality of sets of VIs includes at least one via electrically interconnected to the global power distribution structure on a first wiring plane of the IC and to a VPI on a second wiring plane of the IC.3. The IC of claim 1 , further comprising at least one horizontal interconnect (HI) ...

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Номер записи: 93
13-12-2018 дата публикации

LATERAL NON-VOLATILE STORAGE CELL

Номер: US20180358366A1
Автор: DeForge John B., Ellis-Monaghan John J., Hook Terence B., Peterson Kirk D.
Принадлежит:

A method fabricates a lateral non-volatile storage cell. The lateral non-volatile storage cell includes a first transistor including a first transistor body formed on a dielectric layer. The first transistor includes a source region and drain region on opposite sides of the first transistor body. A second transistor is laterally adjacent to the first transistor and includes a second transistor body, parallel with the first transistor body, formed on the dielectric layer. A first layer of gate oxide of a first thickness is formed over the first transistor body, and a second layer of gate oxide of a second thickness is formed over a portion of the second transistor body. The first thickness and the second thickness are different. A floating gate is formed over the first layer of gate oxide, the second layer of gate oxide, and the dielectric layer. 1. A method of fabricating a lateral non-volatile storage cell , the method comprising:fabricating a first transistor including a first transistor body formed on a dielectric layer, wherein the first transistor includes a source region and drain region on opposite sides of the first transistor body;fabricating a second transistor laterally adjacent to the first transistor and including a second transistor body, parallel with the first transistor body, formed on the dielectric layer;forming a first layer of gate oxide of a first thickness over a portion of the first transistor body;forming a second layer of gate oxide of a second thickness over a portion of the second transistor body, wherein the first thickness and the second thickness are different; andforming a floating gate over the first layer of gate oxide, the second layer of gate oxide, and the dielectric layer, wherein each of the forming the first layer of gate oxide and the forming the second layer of gate oxide includes depositing an interlayer dielectric (ILD) and a high k dielectric, the depositing the high k dielectric of the first layer of gate oxide is at a ...

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Номер записи: 94
27-12-2018 дата публикации

TESTING MECHANISM FOR A PROXIMITY FAIL PROBABILITY OF DEFECTS ACROSS INTEGRATED CHIPS

Номер: US20180372799A1
Автор: Peterson Kirk D., RWABUKAMBA ALAIN G., Turner Andrew A.
Принадлежит:

According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area. 1. A method for determining a status of circuitry within a chip by a testing mechanism , comprising:collecting, by the testing mechanism, fail signatures from portions of the circuitry within the chip to determine the status of the circuitry within a chip, where the fail signatures evidence lack of operability for the portions of the circuitry within the chip;analyzing, by the testing mechanism, fail signatures on a by-level basis to identify a high probability defect area within the chip;determining, by the testing mechanism, whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip; anddetermining, by the testing mechanism, the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.2. The method of claim 1 , the analyzing of the fail signatures further comprising:determining the chip to be a bad chip with respect to whether the fail signatures indicate the status of the circuits to be bad.3. The method of claim 1 , the analyzing of the fail signatures further comprising:determining by-level fail probabilities and associated confidence scores.4. The method of claim 3 , wherein the determining of the by-level fail probabilities comprises statistically determining one or more by-level fail probabilities based on tracing diagnostics of the fail signatures.5. The method of claim 1 , wherein the high ...

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Номер записи: 95
05-12-2019 дата публикации

SEMICONDUCTOR VIA STRUCTURE WITH LOWER ELECTRICAL RESISTANCE

Номер: US20190371663A1
Автор: Clevenger Lawrence A., Li Baozhen, Peterson Kirk D., Spooner Terry A., Wang Junli
Принадлежит:

A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via. 1. A method of forming a device , comprising:providing a first conductive line including a first conductive material and a second conductive line, wherein the first conductive line and second conductive line are connected by a via, wherein the via includes two via side walls and a via bottom surface;depositing a first liner material along inner surfaces of the via side walls and the via bottom surface;removing the liner material from the via bottom surface;depositing a via material into the via forming a via material top surface; anddepositing a second liner material that covers the via material such that a top surface of the via material extends above a bottom surface of the second liner material.2. The method of claim 1 , wherein the via material top surface extends above a bottom surface of the second conductive line.3. The method of claim 1 , wherein the via material top surface is curved.4. The method of claim 1 , wherein the first liner material includes a semiconductor material or an insulator material.5. The method of claim 1 , wherein the second liner material includes a semiconductor material or an insulator material.6. The method of claim 1 , wherein the first liner material and the second liner material are the same.7. The method of claim 1 , wherein the first liner material and the second liner material may be independently selected from the group consisting of titanium claim 1 , titanium nitride claim 1 , tungsten claim 1 , titanium tungsten claim 1 , tungsten ...

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Номер записи: 96
18-10-2016 дата публикации

Stress balancing of circuits

Номер: US9472269B2
Автор: Ezra D. B. Hall, Igor Arsovski, John B. DeForge, Kirk D. Peterson, Nathaniel R. Chadwick
Принадлежит: Globalfoundries Inc

Methods, systems, and structures for stress balancing field effect transistors subject to bias temperature instability-caused threshold voltage shifts. A method includes characterizing fatigue of a location in a memory array by skewing a bit line voltage of the location. The method also includes determining that the location is unbalanced based on the characterizing. Further, the method includes inverting a logic state of the location. Additionally, the method includes changing a value of an inversion indicator corresponding to the location.

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Номер записи: 97
24-04-2001 дата публикации

Combined chemical mechanical polishing and reactive ion etching process

Номер: US6221775B1
Автор: Kirk D. Peterson, Mark P. Murray, Michael J. MacDonald, Thomas G. Ference, Walter E. Mlynko, William F. Landers
Принадлежит: International Business Machines Corp

A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemical mechanical planarizing (CMP) process step until all of the raised regions are at least partially removed from the layer. Finally, the surface of the polished substrate is etched with a reactive ion etching (RIE) process.

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Номер записи: 98
07-01-2020 дата публикации

Three-dimensional stacked memory access optimization

Номер: US10528288B2
Автор: Diyanesh B. Chinnakkonda Vidyapoornachary, John B. DeForge, Kirk D. Peterson, Saravanan Sethuraman, Sridhar H. Rangarajan, Warren E. Maule
Принадлежит: International Business Machines Corp

An aspect includes receiving a request to access one or more memory devices in a stack of memory devices in a memory. Each of the memory devices are communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). A current operating mode of the memory is determined in response to receiving the request. Based at least in part on the current operating mode of the memory being a first mode, a chip select switch is activated to provide access to exactly one of the memory devices in the stack of memory devices. Based at least in part on the current operating mode of the memory being a second mode, the chip select switch is activated to access all of the memory devices in the stack in parallel. The request is serviced using the activated chip select switch.

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Номер записи: 99
25-12-2012 дата публикации

Optimizing voltage on a power plane using a networked voltage regulation module array

Номер: US8341434B2
Автор: Alain Loiseau, Gilles Gervais, Kirk D. Peterson, Norman J. Rohrer
Принадлежит: International Business Machines Corp

A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.

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Номер записи: 100
17-02-2009 дата публикации

Adjusting voltage for a phase locked loop based on temperature

Номер: US7493229B2
Автор: David W. Boerstler, Eskinder Hailu, Jieming Qi, Kirk D. Peterson, Nathaniel R. Chadwick
Принадлежит: International Business Machines Corp

A mechanism for utilizing a single set of one or more thermal sensors, e.g., thermal diodes, provided on the integrated circuit device, chip, etc., to control the operation of the integrated circuit device, associated cooling system, and high-frequency PLLs is provided. By utilizing a single set of thermal sensors to provide multiple functions, e.g., controlling the operation of the integrated circuit device, the cooling system, and the PLLs, silicon real-estate usage is reduced through combining circuitry functionality. Moreover, the integrated circuit device yield is improved by reducing circuitry complexity and increasing PLL robustness to temperature. Furthermore, the PLL circuitry operating range is improved by compensating for temperature.

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Номер записи: 101
15-12-2015 дата публикации

Method of self-correcting power grid for semiconductor structures

Номер: US9214427B2
Автор: Andrew A. Turner, Andrew H. NORFLEET, Cathryn J. Christiansen, Kirk D. Peterson
Принадлежит: Globalfoundries Inc

Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect.

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Номер записи: 102
11-06-2013 дата публикации

Use of contacts to create differential stresses on devices

Номер: US8460981B2
Автор: Jed H. Rankin, Jeffrey P. Gambino, John J. Ellis-Monaghan, Kirk D. Peterson, Robert R. Robison
Принадлежит: International Business Machines Corp

Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.

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Номер записи: 103
19-11-2002 дата публикации

Double planar gated SOI MOSFET structure

Номер: US6483156B1
Автор: Effendi Leobandung, James W. Adkisson, Jed H. Rankin, Jerome B. Lasky, John A. Bracchitta, John J. Ellis-Monaghan, Kirk D. Peterson
Принадлежит: International Business Machines Corp

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.

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Номер записи: 104