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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 25. Отображено 20.
07-02-2017 дата публикации

Axiocentric scrubbing land grid array contacts and methods for fabrication

Номер: US0009565759B2
Автор: Gareth Hougham, Gerard McVicker, Xiaoxiong Gu, Sung K. Kang, Frank R. Libsch, Xiao H. Liu, HOUGHAM GARETH, MCVICKER GERARD, GU XIAOXIONG, KANG SUNG K, LIBSCH FRANK R, LIU XIAO H, Hougham Gareth, McVicker Gerard, Gu Xiaoxiong, Kang Sung K., Libsch Frank R., Liu Xiao H.
Принадлежит: GLOBALFOUNDRIES INC., GLOBALFOUNDRIES INC

A contact structure and assembly for a microelectronics device includes first and second electrically conductive contacts being helically shaped. A carrier element is attached to and positioned between the first and second contacts. The first and second contacts are in electrical communication with each other, and the first and second contacts are in a mirror image relationship with each other. A pair of insulating substrates each include electrically conductive members. A contact point on each of the first and second contacts is attached and electrically communicating to respective electrically conductive members such that the first and second electrically conductive contacts between the pair of insulating substrates form an electrically conductive package. A metal layer on the carrier element provides electrical conductivity through a first opening defined by the carrier element between the first and second portions of the helix shaped contact.

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Номер записи: 1
12-09-2017 дата публикации

Enhancement of iso-via reliability

Номер: US0009761482B2
Автор: Lawrence A. Clevenger, Baozhen Li, Xiao H. Liu, Kirk D. Peterson, CLEVENGER LAWRENCE A, LI BAOZHEN, LIU XIAO H, PETERSON KIRK D, Clevenger Lawrence A., Li Baozhen, Liu Xiao H., Peterson Kirk D.
Принадлежит: International Business Machines Corporation, IBM

A process of making a semiconductor structure. The process includes forming a wiring line; forming a reliability enhancement material on the wiring line; forming an interlayer dielectric (ILD) layer on the wiring line; forming a via opening through the ILD layer and reliability enhancement material to expose a surface of the wiring line; and filling the via opening with a metal to form a metal-filled via in contact with the wiring line wherein the reliability enhancement material is in direct contact with the metal-filled via; wherein the reliability enhancement material causes a compressive stress on the metal-filled via where it contacts the wiring line. Another embodiment includes the metal-filled via being an iso-via so that there is only one metal-filled via per wiring line.

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Номер записи: 2
03-01-2017 дата публикации

Structure with air gap crack stop

Номер: US0009536842B2
Автор: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Xiao H. Liu, Naftali E. Lustig, Andrew H. Simon, BAO JUNJING, BONILLA GRISELDA, CHOI SAMUEL S, FILIPPI RONALD G, LIU XIAO H, LUSTIG NAFTALI E, SIMON ANDREW H, Bao Junjing, Bonilla Griselda, Choi Samuel S., Filippi Ronald G., Liu Xiao H., Lustig Naftali E., Simon Andrew H.
Принадлежит: GlobalFoundries, Inc., GLOBALFOUNDRIES INC, GLOBALFOUNDRIES INC.

An method including forming multiple interconnect levels on top of one another, each level comprising a metal interconnect and a crack stop both embedded in a dielectric layer, and a dielectric capping layer directly on top of the dielectric layer and directly on top of the metal interconnect, the crack stop is an air gap which intersects an interface between the dielectric layer and the dielectric capping layer of each interconnect level, and forming a through substrate via through the multiple interconnect levels adjacent to, but not in direct contact with, the crack stop, the crack stop of each interconnect level is directly between the metal interconnect of each interconnect level and the through substrate via to prevent cracks caused during fabrication from propagating away from the through substrate via and damaging the metal interconnect.

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Номер записи: 3
11-10-2012 дата публикации

Thermal expansion control employing platelet fillers

Номер: US20120259072A1
Автор: Gareth G. Hougham, Xiao H. Liu
Принадлежит: International Business Machines Corp

Bilayer platelet fillers are employed to compensate for a positive coefficient of thermal expansion (CTE) of an embedding polymeric material, or even to provide a composite structure having a negative CTE to eliminate or alleviate thermomechanical stress and/or delamination during thermal cycling. A bilayer platelet includes two joined layers having different CTEs. The CTE mismatch induces bending of the bilayer platelets, thereby causing cavities at temperatures lower than the joining temperature at which the bilayers are joined. The decrease in the volume of the polymeric material and the bilayer platelets at low temperatures is compensated by an accompanying increase in the volume of the cavities so that the composite structure has a temperature independent volume, a low net CTE, or even a negative CTE.

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Номер записи: 4
27-12-2012 дата публикации

AXIOCENTRIC SCRUBBING LAND GRID ARRAY CONTACTS AND METHODS FOR FABRICATION

Номер: US20120325541A1
Автор: Gu Xiaoxiong, Hougham Gareth, Kang Sung K., Libsch Frank R., Liu Xiao H., McVicker Gerard
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A contact structure and assembly and a method for manufacturing the same for a microelectronics device includes first and second electrically conductive contacts being helically shaped. A carrier element is attached to and positioned between the first and second contacts. The first and second contacts are in electrical communication with each other, and the first and second contacts are in a mirror image relationship with each other. A pair of insulating substrates each include electrically conductive members. A contact point on each of the first and second contacts is attached and electrically communicating to respective electrically conductive members such that the first and second electrically conductive contacts between the pair of insulating substrates form an electrically conductive package. A metal layer on the carrier element provides electrical conductivity through a first opening defined by the carrier element between the first and second portions of the helix shaped contact. 1. A method for manufacturing a contact structure for microelectronics manufacturing , comprising:providing a carrier element defining a first opening therethrough;positioning a molded element on opposite sides of the carrier element by passing the molded element partially through the first opening;coating the molded element with an electrically conductive material;fabricating a helix shaped contact from the electrically conductive material on the opposite sides of the carrier element, the helix shaped contact being positioned over the molded element, the helix shaped contact having a first portion and a second portion on the opposing sides of the carrier element, respectively, and the first and second portions being in mirror image relationship to each other;heating the combined helix shaped contact and the molded element such that the molded element is ablated and the helix shaped contact substantially retains the shape of the molded element.2. The method of claim 1 , wherein the ...

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Номер записи: 5
07-02-2013 дата публикации

Thermal expansion control employing platelet fillers

Номер: US20130035411A1
Автор: Gareth G. Hougham, Xiao H. Liu
Принадлежит: International Business Machines Corp

Bilayer platelet fillers are employed to compensate for a positive coefficient of thermal expansion (CTE) of an embedding polymeric material, or even to provide a composite structure having a negative CTE to eliminate or alleviate thermomechanical stress and/or delamination during thermal cycling. A bilayer platelet includes two joined layers having different CTEs. The CTE mismatch induces bending of the bilayer platelets, thereby causing cavities at temperatures lower than the joining temperature at which the bilayers are joined. The decrease in the volume of the polymeric material and the bilayer platelets at low temperatures is compensated by an accompanying increase in the volume of the cavities so that the composite structure has a temperature independent volume, a low net CTE, or even a negative CTE.

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Номер записи: 6
11-07-2013 дата публикации

Thick On-Chip High-Performance Wiring Structures

Номер: US20130175073A1
Автор: Cooney, Gambino Jeffrey P., He Zhong-Xiang, III Edward C., Lee Tom C., Liu Xiao H.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire. 1. A method of fabricating a back-end-of-line wiring structure , the method comprising:forming a first wire in a first dielectric layer;annealing the first wire in an oxygen-free atmosphere;after annealing the first wire, forming a second wire in alignment with the first wire; andforming a final passivation layer comprised of an organic material that covers an entirety of a sidewall of the second wire.2. The method of wherein forming the first wire in the first dielectric layer comprises:depositing the first dielectric layer;etching a trench in the first dielectric layer; anddepositing a conductor layer that partially resides in the trench to define the first wire and that covers a top surface of the first dielectric layer.3. The method of wherein further comprising:after annealing, removing the conductor layer from the top surface of the first dielectric layer so that the top surface of the first wire is planarized relative to the top surface of the first dielectric layer.4. The method of wherein the conductor layer is removed from the top surface of the first dielectric layer by chemical-mechanical polishing.5. The method of wherein the oxygen-free atmosphere comprises nitrogen gas.6. The method of wherein the first wire is annealed at a temperature in a range of 250° C. to 425° C.7. The method of wherein the second wire is formed in direct contact with the first wire claim 1 , the first wire is formed by a damascene process claim 1 , ...

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Номер записи: 7
09-01-2020 дата публикации

Enhancement of iso-via reliability

Номер: US20200013671A1
Автор: Baozhen Li, Kirk D. Peterson, Lawrence A. Clevenger, Xiao H. Liu
Принадлежит: International Business Machines Corp

A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a multilayer cap layer and an ILD layer. A metal-filled via extends through the ILD layer and partially through the cap layer to make contact with the wiring line. There is a reliability enhancement material formed in one of the layers of the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer.

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Номер записи: 8
29-05-2014 дата публикации

Fixed curvature force loading of mechanically spalled films

Номер: US20140147988A1
Автор: Devendra K. Sadana, Keith E. Fogel, Paul A. Lauro, Stephen W. Bedell, Xiao H. Liu
Принадлежит: International Business Machines Corp

A spalling method is provided that includes depositing a stressor layer on surface of a base substrate, and contacting the stressor layer with a planar transfer. The planar transfer surface is then traversed along a plane that is parallel to and having a vertical offset from the upper surface of the base substrate. The planar transfer surface is traversed in a direction from a first edge of the base substrate to an opposing second edge of the base substrate to cleave the base substrate and transfer a spalled portion of the base substrate to the planar transfer surface. The vertical offset between the plane along which the planar transfer surface is traversed and the upper surface of the base substrate is a fixed distance. The fixed distance of the vertical offset provides a uniform spalling force. A spalling method is also provided that includes a transfer roller.

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Номер записи: 9
19-06-2014 дата публикации

Thick On-Chip High-Performance Wiring Structures

Номер: US20140167219A1
Автор: Edward C. Cooney, III, Jeffrey P. Gambino, Tom C. Lee, Xiao H. Liu, Zhong-Xiang He
Принадлежит: International Business Machines Corp

Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.

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Номер записи: 10
23-06-2016 дата публикации

DISCONTINUOUS AIR GAP CRACK STOP

Номер: US20160181208A1
Автор: Bao Junjing, Bonilla Griselda, Choi Samuel S., Filippi Ronald G., Liu Xiao H., Lustig Naftali E., Simon Andrew H.
Принадлежит:

An method including forming multiple interconnect levels on top of one another, each level comprising a metal interconnect and a crack stop both embedded in a dielectric layer, and a dielectric capping layer directly on top of the dielectric layer and directly on top of the metal interconnect, the crack stop is an air gap which intersects an interface between the dielectric layer and the dielectric capping layer of each interconnect level, and forming a through substrate via through the multiple interconnect levels adjacent to, but not in direct contact with, the crack stop, the crack stop of each interconnect level is directly between the metal interconnect of each interconnect level and the through substrate via to prevent cracks caused during fabrication from propagating away from the through substrate via and damaging the metal interconnect. 1. A method comprising:forming multiple interconnect levels on top of one another, each interconnect level comprising a metal interconnect embedded in a dielectric layer, an air gap partially embedded in the dielectric layer, and a dielectric capping layer directly on top of the dielectric layer and directly on top of the metal interconnect, the air gap intersects an interface between the dielectric layer and the dielectric capping layer of each interconnect level, and air gaps in adjacent interconnect levels do not physically contact one another; andforming a through substrate via through the multiple interconnect levels adjacent to, but not in direct contact with, the air gap, the air gap of each interconnect level is directly between the metal interconnect of each interconnect level and the through substrate via to prevent cracks caused during fabrication from propagating away from the through substrate via and damaging the metal interconnect.2. The method of claim 1 , wherein a height or depth of each air gap of each of the multiple interconnect levels is less than a height or thickness of each of the multiple ...

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Номер записи: 11
10-09-2015 дата публикации

ENHANCEMENT OF ISO-VIA RELIABILITY

Номер: US20150255388A1
Автор: Clevenger Lawrence A., Li Baozhen, Liu Xiao H., Peterson Kirk D.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line and an ILD layer. A metal-filled via extends through the ILD layer to make contact with the wiring line. There is a reliability enhancement material that surrounds at least part of the via so as to render the via compressive where the via contacts the wiring line. The reliability enhancement material may be compressive as deposited or may be made compressive after deposition. 1. A semiconductor structure comprising:a semiconductor base comprising a plurality of semiconductor devices: a wiring line;', 'an interlayer dielectric (ILD) layer on the wiring line;', 'a via extending through the ILD to communicate with the wiring line;', 'a metal filling the via and in contact with the wiring line; and', 'a compressive reliability enhancement material surrounding at least part of the metal-filled via to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress., 'a back end of the line wiring layer comprising2. The semiconductor structure of wherein the reliability enhancement material surrounds the entire metal-filled via.3. The semiconductor structure of wherein the reliability enhancement material surrounds the metal-filled via in the cap and only in a portion of the ILD.4. The semiconductor structure of further comprising a cap layer between the wiring line and the ILD layer and wherein the reliability enhancement material surrounds the metal-filled via only in the cap layer.5. The semiconductor structure of wherein the reliability enhancement material surrounds the metal-filled via only in a portion of the ILD.6. The semiconductor structure of wherein the reliability enhancement material surrounds the metal-filled via only where the metal-filled via contacts the wiring line.7. The semiconductor structure of wherein the via has a via wall and further comprising a barrier layer on ...

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Номер записи: 12
02-11-2017 дата публикации

Enhancement of iso-via reliability

Номер: US20170316970A1
Автор: Baozhen Li, Kirk D. Peterson, Lawrence A. Clevenger, Xiao H. Liu
Принадлежит: International Business Machines Corp

A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a cap layer and an ILD layer. A metal-filled via extends through the ILD layer to make contact with the wiring line. There is a reliability enhancement material in the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer. The reliability enhancement material may be compressive as deposited or may be made compressive after deposition.

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Номер записи: 13
19-11-2015 дата публикации

AXIOCENTRIC SCRUBBING LAND GRID ARRAY CONTACTS AND METHODS FOR FABRICATION

Номер: US20150334830A1
Автор: Gu Xiaoxiong, Hougham Gareth, Kang Sung K., Libsch Frank R., Liu Xiao H., McVicker Gerard
Принадлежит:

A contact structure and assembly for a microelectronics device includes first and second electrically conductive contacts being helically shaped. A carrier element is attached to and positioned between the first and second contacts. The first and second contacts are in electrical communication with each other, and the first and second contacts are in a mirror image relationship with each other. A pair of insulating substrates each include electrically conductive members. A contact point on each of the first and second contacts is attached and electrically communicating to respective electrically conductive members such that the first and second electrically conductive contacts between the pair of insulating substrates form an electrically conductive package. A metal layer on the carrier element provides electrical conductivity through a first opening defined by the carrier element between the first and second portions of the helix shaped contact.

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Номер записи: 14
17-12-2015 дата публикации

ENHANCEMENT OF ISO-VIA RELIABILITY

Номер: US20150364365A1
Автор: Clevenger Lawrence A., Li Baozhen, Liu Xiao H., Peterson Kirk D.
Принадлежит:

A process of making a semiconductor structure. The process includes forming a wiring line; forming a reliability enhancement material on the wiring line; forming an interlayer dielectric (ILD) layer on the wiring line; forming a via opening through the ILD layer and reliability enhancement material to expose a surface of the wiring line; and filling the via opening with a metal to form a metal-filled via in contact with the wiring line wherein the reliability enhancement material is in direct contact with the metal-filled via; wherein the reliability enhancement material causes a compressive stress on the metal-filled via where it contacts the wiring line. Another embodiment includes the metal-filled via being an iso-via so that there is only one metal-filled via per wiring line. 1. A process of making a semiconductor structure comprising:forming a wiring line;forming a recess in the wiring line;filling the recess with a reliability enhancement material;forming a cap layer over the wiring line and the recess;forming an interlayer dielectric (ILD) layer on the cap layer;forming a via opening through the ILD layer, cap layer and reliability enhancement material to expose a surface of the wiring line; andfilling the via opening with a metal to form a metal-filled via in contact with the wiring line;wherein the reliability enhancement material causes a compressive stress on the metal-filled via where it contacts the wiring line.2. The process of wherein the reliability enhancement material is deposited so as to be compressive.3. The process of further comprising after forming a reliability enhancement material claim 1 , treating the reliability enhancement material so as to be compressive.4. A process of making a semiconductor structure comprising:forming a wiring line;forming a reliability enhancement material on the wiring line;forming an interlayer dielectric (ILD) layer on the wiring line;forming a via opening through the ILD layer and reliability enhancement ...

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Номер записи: 15
31-08-2010 дата публикации

Apparatus and method for reducing contamination in immersion lithography

Номер: US7787101B2
Автор: Dario L. Goldfarb, Dmitriy Shneyder, Kafai Lai, Raschid J. Bezama, Xiao H. Liu
Принадлежит: International Business Machines Corp

An apparatus for reducing contamination in immersion lithography includes a wafer chuck assembly including a wafer chuck configured to hold a semiconductor wafer on a support surface thereof. An O-ring assembly has a deformable O-ring attached to movable support sections arranged in a generally circular configuration so as to surround the wafer.

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Номер записи: 16
08-03-2011 дата публикации

Semiconductor nanowire with built-in stress

Номер: US7902541B2
Автор: Dureseti Chidambarrao, Lidija Sekaric, Xiao H. Liu
Принадлежит: International Business Machines Corp

A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

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Номер записи: 17
24-11-2009 дата публикации

Test structures for electrically detecting back end of the line failures and methods of making and using the same

Номер: US7622737B2
Автор: Ian D. Melville, Mukta G. Farooq, Xiao H. Liu
Принадлежит: International Business Machines Corp

Test structures for electrically detecting BEOL failures are provided. In an embodiment, the structure comprises: an input/output connection disposed above a primary conductive pad which is embedded in an insulator; a dielectric layer disposed upon the insulator; a primary via extending through the dielectric layer down to the primary conductive pad for providing electrical connection between the input/output connection and the primary conductive pad; and a secondary via filled with a conductive material in electrical connection with the input/output connection, the secondary via extending through the dielectric layer down to a secondary interconnect in electrical connection with a secondary conductive pad that is insulated from the primary conductive pad.

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Номер записи: 18
29-09-2008 дата публикации

Beol interconnect structures with improved resistance to stress

Номер: SG145626A1
Автор: Christos D Dimitrakopoulos, Darryl D Restaino, Griselda Bonilla, Jae H Kim, Johnny Widodo, Michael W Lane, Son V Nguyen, Stephen M Gates, Thomas M Shaw, Xiao H Liu
Принадлежит: Chartered Semiconductor Mfg, Ibm, SAMSUNG ELECTRONICS CO LTD

BEOL INTERCONNECT STRUCTURES WITH IMPROVED RESISTANCE TO STRESS A chip is provided which includes a back-end-of-line ("BEOL") interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric ("ILD") layers which include a dielectric material curable by ultraviolet ("UV") radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.

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Номер записи: 19
05-02-2009 дата публикации

Strengthening of a structure by infiltration

Номер: US20090035480A1
Автор: David L. Questad, Elbert Huang, Eric G. Liniger, Michael Lane, Thomas M. Shaw, William F. Landers, Xiao H. Liu
Принадлежит: International Business Machines Corp

The present invention provides a method of strengthening a structure, to heal the imperfection of the structure, to reinforce the structure, and thus strengthening the dielectric without compromising the desirable low dielectric constant of the structure. The inventive method includes the steps of providing a semiconductor structure having at least one interconnect structure; dicing the interconnect structure; applying at least one infiltrant into the interconnect structure; and infiltrating the infiltrant to infiltrate into the interconnect structure.

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Номер записи: 20