INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT

A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.

TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME

Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.

Dielectric layers for metal lines in semiconductor chips

A semiconductor structure and methods for forming the same. The structure includes (a) a substrate; (b) a first device and a second device each being on the substrate; (c) a device cap dielectric layer on the first and second devices and the substrate, wherein the device cap dielectric layer comprises a device cap dielectric material; (d) a first dielectric layer on top of the device cap dielectric layer, wherein the first dielectric layer comprises a first dielectric material; (e) a second dielectric layer on top of the first dielectric layer; and (f) a first electrically conductive line and a second electrically conductive line each residing in the first and second dielectric layers. The first dielectric layer physically separates the first and second electrically conductive lines from the device cap dielectric layer. A dielectric constant of the first dielectric material is less than that of the device cap dielectric material.

Local wiring for a bipolar junction transistor including a self-aligned emitter region

Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.

LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES

A semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

INCREASED POWER LINE NOISE IMMUNITY IN IC USING CAPACITOR STRUCTURE IN FILL AREA

Increase power line noise immunity in an IC is provided by using decoupling capacitor structure in an area of the IC that is typically not used for routing, but filled with unconnected and non-functional metal squares (fills). In one embodiment, a method includes providing a circuit design layout; determining a density of a structure in an area of the circuit design layout; and in response to the density being less than a pre-determined density for the structure in the area, filling in a portion of the area with at least one capacitor structure until a combined density of the structure and the at least one capacitor structure in the area is about equal to the pre-determined density. Power line noise immunity is increased by increasing decoupling capacitance without enlarging the IC's total size by using a (fill) area that would normally be filled with unconnected and non-functional metal shapes.

Optoelectronic structures having multi-level optical waveguides and methods of forming the structures

Disclosed are structures with an optical waveguide having a first segment at a first level and a second segment extending between the first level and a higher second level and further extending along the second level. Specifically, the waveguide comprises a first segment between first and second dielectric layers. The second dielectric layer has a trench, which extends through to the first dielectric layer and which has one side positioned laterally adjacent to an end of the first segment. The waveguide also comprises a second segment extending from the bottom of the trench on the side adjacent to the first segment up to and along the top surface of the second dielectric layer on the opposite side of the trench. A third dielectric layer covers the second segment in the trench and on the top surface of the second dielectric layer. Also disclosed are methods of forming such optoelectronic structures.

Integrated BEOL thin film resistor

In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

METHOD AND SYSTEM FOR ASSESSING RELIABILITY OF INTEGRATED CIRCUIT

The present invention provides a method. The method includes operating a plurality of field-effect-transistors (FETs) under a first operation condition; reversing an operation direction for at least one of the plurality of FETs for a brief period of time; measuring a second operation condition of the one of the plurality of FETs during the brief period of time; computing a difference between the second operation condition and a reference operation condition; and providing a reliability indicator based upon the difference between the second and the reference operation conditions, wherein the plurality of FETs are employed in a single integrated circuit (IC).

Semiconductor structures having low resistance paths throughout a wafer

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

INTERDIGITATED CAPACITORS WITH A ZERO QUADRATIC VOLTAGE COEFFICIENT OF CAPACITANCE OR ZERO LINEAR TEMPERATURE COEFFICIENT OF CAPACITANCE

Disclosed are an interdigitated capacitor and an interdigitated vertical native capacitor, each having a relatively low (e.g., zero) net coefficient of capacitance with respect to a specific parameter. For example, the capacitors can have a zero net linear temperature coefficient of capacitance (T) to limit capacitance variation as a function of temperature or a zero net quadratic voltage coefficient of capacitance (V) to limit capacitance variation as a function of voltage. In any case, each capacitor can incorporate at least two different plate dielectrics having opposite polarity coefficients of capacitance with respect to the specific parameter due to the types of dielectric materials used and their respective thicknesses. As a result, the different dielectric plates will have opposite effects on the capacitance of the capacitor that cancel each other out such that the capacitor has a zero net coefficient of capacitance with respect to specific parameter. 1. A capacitor comprising: said first dielectric layer having a top surface and a first thickness, and', 'said first dielectric layer further having a first coefficient of capacitance with respect to a specific parameter;, 'a first dielectric layer comprising a first dielectric material,'} 'said first metal wires being interdigitated with said second metal wires, being physical separated from said second metal wires by spaces, and further being electrically isolated from said second metal wires by said first dielectric material in said spaces; and', 'first metal wires and second metal wires in said first dielectric layer at said top surface,'} said second dielectric layer comprising a second dielectric material different from said first dielectric material and having a second thickness that is different from said first thickness, and', 'said second dielectric layer further having a second coefficient of capacitance with respect to said specific parameter,, 'a second dielectric layer on said top surface and ...

Thick on-chip high-performance wiring structures

DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE

A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge structure comprises a first dielectric layer with more than one electrode formed therein. A second dielectric layer with more than one electrode formed therein is located above the first dielectric layer. At least one via connects the more than one electrode in the first dielectric layer with the more than one electrode in the second dielectric layer. A gap is formed through the first dielectric layer and the second dielectric layer, wherein the gap extends between two adjacent electrodes in both the first dielectric layer and the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer, wherein the third dielectric layer hermetically seals the gap to provide electro-static discharge protection on the integrated circuit.

METAL GATE INTEGRATION STRUCTURE AND METHOD INCLUDING METAL FUSE, ANTI-FUSE AND/OR RESISTOR

A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

INTEGRATED BEOL THIN FILM RESISTOR

In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

VERTICAL PARALLEL PLATE CAPACITOR STRUCTURES

Vertical parallel plate (VPP) capacitor structures that utilize different spacings between conductive plates in different levels of the capacitor stack. The non-even spacings of the conductive plates in the capacitor stack decrease the susceptibility of the capacitor stack of the VPP capacitor to ESD-promoted failures. The non-even spacings may be material specific in that, for example, the spacings between adjacent conductive plates in different levels of the capacitor stack may be chosen based upon material failure mechanisms for plates containing different materials.

Multiple layer structure for substrate noise isolation

A method of forming a semiconductor structure, comprising: providing a substrate having a buried insulative layer and a heavily doped layer; forming a first trench within the substrate around a protected area; filling the first trench with an insulative material, wherein the first trench filled with the insulative material and the buried insulative layer combine to form a high impedance noise isolation that surrounds the protected area on all sides except one side of the protected area to isolate noise from the protected area; forming a second trench within the substrate around the first trench; and filling the second trench with a conductive material, wherein the second trench filled with the conductive material and the heavily doped layer combine to form a low impedance ground path that surrounds the high impedance noise isolation on all sides except one side of the high impedance noise isolation to isolate noise from the protected area.

Semiconductor structures and methods of manufacture

Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.

Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure

Disclosed is a semiconductor chip having a dual damascene insulated wire and insulated through-substrate via (TSV) structure and methods of forming the chip. The methods incorporate a dual damascene technique wherein a trench and via opening are formed in dielectric layers above a substrate such that the trench is above a first via and the via opening is positioned adjacent to the first via and extends vertically from the trench and into the substrate. Dielectric spacers are formed on the sidewalls of the trench and via opening. A metal layer is deposited to form an insulated wire in the trench and an insulated TSV in the via opening. Thus, the insulated wire electrically connects the insulated TSV to the first via and, thereby to an on-chip device or lower metal level wire below. Subsequently, the substrate is thinned to expose the insulated TSV at the bottom surface of the substrate.

FABRICATING POLYSILICON MOS DEVICES AND PASSIVE ESD DEVICES

A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes. 1. A method for integrating fabrication of a metal oxide semiconductor (MOS) device and microelectromechanical system (MEMS) device into a back end of the line (BEOL) process , comprising the steps of:forming a first layer of electrically isolated substrate;forming a first electrode for a MEMS device from a first conductive layer;forming from a first semiconductor layer, a first semiconductor film for the MEMS device and a second semiconductor film for a MOS device;forming from a second conductive layer, a second electrode for the MEMS device and a third electrode for the MOS device;forming from a third conductive layer, a fourth electrode for the MEMS device, and a fifth electrode, sixth electrode and seventh electrode for the MOS device;forming from a second semiconductor layer, a third semiconductor film; andremoving the first semiconductor film and the third semiconductor film.2. The method of claim 1 , wherein the step of removing the first and third semiconductor film comprises removing the first and third semiconductor film through at least one venting hole.3. The method of claim 2 , further comprising the step ...

Structure and design structure for high-Q value inductor and method of manufacturing the same

Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.

STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING

A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.

Semiconductor structure with thin film resistor and terminal bond pad

Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.

Structure of very high insertion loss of the substrate noise decoupling

A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.

METAL-OXIDE-SEMICONDUCTOR (MOS) VARACTORS AND METHODS OF FORMING MOS VARACTORS

MOS varactor having an entire accumulation and depletion regime of its CV characteristic curve in one bias regime (negative or positive). The MOS varactor may comprise a gate electrode, a well region of semiconductor material having a first conductivity type (e.g., p-type), contact regions to the well region that comprise heavily doped semiconductor material of the first conductivity type (e.g., p+-type), and a Schottky junction formed between the gate and contact regions. The Schottky junction may be formed by spacing the contact regions away from the gate electrode and siliciding the substrate surface. The gate electrode may be formed from semiconductor material of a second conductivity type (e.g., n-type) opposite to the first conductivity type, thus changing the flat band voltage of the MOS varactor and shifting accumulation and depletion regime of the CV characteristic curve in one bias regime, such as the negative bias regime.

Structures including means for lateral current carrying capability improvement in semiconductor devices

A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

Low cost bonding pad and method of fabricating same

A structure and a method of forming the structure. The structure including: an integrated circuit chip having a set of wiring levels from a first wiring level to a last wiring level, each wiring level including one or more damascene, dual-damascene wires or damascene vias embedded in corresponding interlevel dielectric levels, a top surface of a last damascene or dual-damascene wire of the last wiring level substantially coplanar with a top surface of a corresponding last interlevel dielectric level; a capping layer in direct physical and electrical contact with a top surface of the last damascene or dual-damascene wire, the last damascene or dual-damascene wire comprising copper; a dielectric passivation layer formed on a top surface of the last interlevel dielectric level; and an aluminum pad in direct physical and electrical contact with the capping layer, a top surface of the aluminum pad not covered by the dielectric passivation layer.

Integrated circuit structure incorporating an inductor, an associated design method and an associated design system

Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M1). An inductor is formed in a second metal level (e.g., M5) above the first metal level and is aligned over and electrically connected in parallel to the ESD device by a single vertical via stack. The inductor is configured to nullify, for a given application frequency, the capacitance value of the ESD device. The quality factor of the inductor is optimized by providing, on a third metal level (e.g., M3) between the second metal level and the first metal level, a shield to minimize inductive coupling. An opening in the shield allows the via stack to pass through, trading off Q factor reduction for size-scaling and ESD robustness improvements.

Post last wiring level inductor using patterned plate process

A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above a top surface of the substrate; an insulative layer on and above a top surface of the capping layer; an inductor comprising a first portion in and above the insulative layer and a second portion only above the insulative layer; and a wire bond pad within the insulative layer, wherein the first portion the inductor has a height in a first direction greater than a height of the wire bond pad in the first direction, wherein the first direction is perpendicularly directed from the top surface of substrate toward the insulative layer.

Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric

A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by sidewall spacers.

METHOD AND STRUCTURE FOR SYMMETRIC CAPACITOR FORMATION

A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.

Isolated wire structures with reduced stress, methods of manufacturing and design structures

An integrated circuit (IC) including a set of isolated wire structures disposed within a layer of the IC, methods of manufacturing the same and design structures are disclosed. The method includes forming adjacent wiring structures on a same level, with a space therebetween. The method further includes forming a capping layer over the adjacent wiring structures on the same level, including on a surface of a material between the adjacent wiring structures. The method further includes forming a photosensitive material over the capping layer. The method further includes forming an opening in the photosensitive material between the adjacent wiring structures to expose the capping layer. The method further includes removing the exposed capping layer.

INTERLEVEL CONDUCTIVE LIGHT SHIELD

A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain. 1. A semiconductor structure comprising:at least one semiconductor device located on a top surface of a semiconductor substrate;at least one first-level metal line separated from a top surface of said semiconductor substrate;a first dielectric layer abutting a top surface of said at least one first-level metal line;a conductive light shield located over said at least one semiconductor device and abutting a top surface of said first dielectric layer; anda second dielectric layer located over said conductive light shield, wherein said first dielectric layer and said second dielectric layer encapsulate an entirety of said conductive light shield.2. The semiconductor structure of claim 1 , further comprising:a second level metal line embedded in said second dielectric layer; anda contact via abutting a bottom surface of said at least one second level metal line and a top surface of said at least one first level metal line.3. The semiconductor structure of claim 2 , wherein said contact via is of integral construction without any physically manifested interface therein.4. The semiconductor structure of claim 2 , further comprising:a metal plate having a same material composition and a same thickness as said conductive light shield and abutting said top surface of said first dielectric layer and disjoined from said conductive ...

Method of forming a metal silicide layer, devices incorporating metal silicide layers and design structures for the devices

Electronic devices and design structures of electronic devices containing metal silicide layers. The devices include: a thin silicide layer between two dielectric layers, at least one metal wire abutting a less than whole region of the silicide layer and in electrical contact with the silicide layer.

COMPLIMENTARY METAL-INSULATOR-METAL (MIM) CAPACITORS AND METHOD OF MANUFACTURE

A low capacitance density, high voltage MIM capacitor and the high density MIM capacitor and a method of manufacture are provided. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.

INTERLEVEL CONDUCTIVE LIGHT SHIELD

A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.

INTEGRATED CIRCUIT STRUCTURE INCORPORATING AN INDUCTOR, AN ASSOCIATED DESIGN METHOD AND AN ASSOCIATED DESIGN SYSTEM

Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M1). An inductor is formed in a second metal level (e.g., M5) above the first metal level and is aligned over and electrically connected in parallel to the ESD device by a single vertical via stack. The inductor is configured to nullify, for a given application frequency, the capacitance value of the ESD device. The quality factor of the inductor is optimized by providing, on a third metal level (e.g., M3) between the second metal level and the first metal level, a shield to minimize inductive coupling. An opening in the shield allows the via stack to pass through, trading off Q factor reduction for size-scaling and ESD robustness improvements.

POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS

A method of forming a semiconductor structure, and the semiconductor structure so formed, wherein a transmission line, such as an inductor, is formed on a planar level above the surface of a last metal wiring level.

Semiconductor structures having low resistance paths throughout a wafer

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

INTEGRATED CIRCUIT STRUCTURE WITH THROUGH-METAL THROUGH-SUBSTRATE INTERCONNECT AND METHOD

Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.

Method and structure for creation of a metal insulator metal capacitor

The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.

DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE

A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge device comprises a substrate and multiple metal level layers disposed on the substrate. Each metal level comprises more than one electrode formed therein and more than one via connecting with some of the electrodes in adjacent metal levels. The device further includes a gap formed about one of the metal level layers, wherein the gap is hermetically sealed to provide electro-static discharge protection for the integrated circuit.

Optimum padset for wire bonding RF technologies with high-Q inductors

An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF structure includes a dielectric layer having metal inductor wires of a first thickness and a metal bond pad having a major area of a second thickness located on a surface thereof, wherein the first thickness is greater than the second thickness. In the inventive RF structure, the majority of the metal bond pad is thinned for wire bonding, while maintaining the full metal wire thickness in the other areas of the structure for inductor performance requirements, such as, for example, low resistivity. Methods for fabricating the aforementioned RF structure are also provided.

ON-CHIP INDUCTOR WITH MAGNETIC CORE

An inductor formed on an integrated circuit chip including one or more inner layers (12) between two or more outer layers (14), inductor metal winding turns (16) included in one or more inner layers (12), and a magnetic material forming the two or more outer layers (14) and the one or more inner layers (12). In one embodiment, the magnetic material is a photoresist paste having magnetic particles. In another embodiment, the magnetic material is a series of magnetic metallic strips (32 and 36) disposed on each of the first and second portions (30 and 34, respectively) of the two or more outer layers (14) and on each of the one or more inner layers (12). The series of magnetic metallic strips on the first and second portions (30, 34) form a grid pattern. Other embodiments include an adjustable controlled compound deposit and control windings with adjustable electrical currents.

Integrated BEOL thin film resistor

In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

Semiconductor structure including a high performance fet and a high voltage fet on an SOI substrate

A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

FORMATION OF METAL-INSULATOR-METAL CAPACITOR SIMULTANEOUSLY WITH ALUMINUM METAL WIRING LEVEL USING A HARDMASK

Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

Method of forming a recessed polysilicon filled trench

A method of forming a recessed polysilicon contact is provided. The method includes: forming a trench in a substrate; overfilling the trench with polysilicon; removing the polysilicon outside of the trench to provide a substantially planar surface; oxidizing the surface of the polysilicon in the trench using plasma oxidation; and removing an upper portion of the polysilicon from the trench.

Segmented guard-ring and chip edge seals

The present disclosure relates to semiconductor structures and, more particularly, to segmented guard-ring and chip edge seals and methods of manufacture. The structure includes: a guard ring structure formed in a low-k dielectric material; and an edge seal structure formed through the low-k dielectric material to at least a substrate underneath the low-k dielectric material.

INTEGRATED CIRCUIT INCLUDING WIRE STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE

An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via. 1. An integrated circuit comprising:a substrate;a dielectric layer disposed on the substrate;a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component;a bond pad disposed on the first wire component, the bond pad including an exposed portion;a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; anda wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.2. The integrated circuit of claim 1 , further comprising a diffusion barrier disposed within the wire structure via between the second wire component and a thick wire in the wire structure.3. The integrated circuit of claim 2 , wherein the diffusion barrier is self-aligned and the wire structure is physically isolated from the bond pad.4. The integrated circuit of claim 2 , wherein the diffusion barrier includes at least one of Tantalum claim 2 , Titanium claim 2 , Titanium Nitride claim 2 , ...

Vertical LC tank device

An LC tank structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.

Capacitor using barrier layer metallurgy

A metal-insulator-metal (MIM) capacitor using barrier layer metallurgy and methods of manufacture are disclosed. The method includes forming a bottom plate of a metal-insulator-metal (MIM) capacitor and a bonding pad using a single masking process. The method further includes forming a MIM dielectric on the bottom plate. The method further includes forming a top plate of the MIM capacitor on the MIM dielectric. The method further includes forming a solder connection on the bonding pad.

INTEGRATED CIRCUIT INCLUDING WIRE STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE

Various aspects include an integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via. 1. An integrated circuit comprising:a substrate;a dielectric layer disposed on the substrate;a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component on a same level of the integrated circuit;a bond pad disposed on the same level as the first wire component, the bond pad including an exposed portion;a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; anda wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via, wherein the wire structure is located over the first wire component and the second wire component,wherein the bond pad is disposed laterally adjacent the wire structure via.2. The integrated circuit of claim 1 , further comprising a diffusion barrier disposed within the wire structure via between the second wire component and a thick wire in the wire structure.3. The integrated circuit of claim 2 , wherein the ...

METHODS FOR SELECTIVE REVERSE MASK PLANARIZATION AND INTERCONNECT STRUCTURES FORMED THEREBY

Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer. 1. An interconnect structure formed on a substrate , the interconnect structure comprising:a first dielectric layer on the substrate, the first dielectric layer having a top surface;a plurality of conductive features extending from the substrate to the top surface of the first dielectric layer, each of the conductive features having a top surface substantially coplanar with the top surface of the first dielectric layer;a second dielectric layer on the first dielectric layer and the conductive features; andan etch stop layer on the top surface of at least one of the conductive features, the etch stop layer disposed between the top surface of at least one of the conductive features and the second dielectric layer.2. The interconnect structure of wherein each of the conductive features has a height claim 2 , the first dielectric layer has a thickness approximately equal to the height of the conductive features claim 2 , and the second dielectric layer has a thickness smaller than the thickness of the first dielectric layer.3. The interconnect structure of wherein the thickness of the second ...

ON-CHIP TRANSMISSION LINE STRUCTURES WITH BALANCED PHASE DELAY

A transmission wiring structure, associated design structure and associated method for forming the same. A structure is disclosed having: a plurality of wiring levels formed on a semiconductor substrate; a pair of adjacent first and second signal lines located in the wiring levels, wherein the first signal line comprises a first portion formed on a first wiring level and a second portion formed on a second wiring level; a primary dielectric structure having a first dielectric constant located between the first portion and a ground shield; and a secondary dielectric structure having a second dielectric constant different than the first dielectric constant, the secondary dielectric structure located between the second portion and the ground shield, and the second dielectric layer extending co-planar with the second portion and having a length that is substantially the same as the second portion. 1. A structure comprising:a plurality of wiring levels formed on a semiconductor substrate;a pair of adjacent first and second signal lines located in the wiring levels, wherein the first signal line comprises a first portion formed on a first wiring level and a second portion formed on a second wiring level;a primary dielectric structure having a first dielectric constant located between the first portion and a ground shield; anda secondary dielectric structure having a second dielectric constant different than the first dielectric constant, the secondary dielectric structure located between the second portion and the ground shield, and the second dielectric layer extending co-planar with the second portion and having a length that is substantially the same as the second portion.2. The structure of claim 1 , wherein the first signal line has a length that is different than a length of the second signal line; and claim 1 , the second portion and the secondary dielectric structure are arranged to provide the same phase delay and same characteristic impedance for the first and ...

Increased power line noise immunity in IC using capacitor structure in fill area

Increase power line noise immunity in an IC is provided by using decoupling capacitor structure in an area of the IC that is typically not used for routing, but filled with unconnected and non-functional metal squares (fills). In one embodiment, a method includes providing a circuit design layout; determining a density of a structure in an area of the circuit design layout; and in response to the density being less than a pre-determined density for the structure in the area, filling in a portion of the area with at least one capacitor structure until a combined density of the structure and the at least one capacitor structure in the area is about equal to the pre-determined density. Power line noise immunity is increased by increasing decoupling capacitance without enlarging the IC's total size by using a (fill) area that would normally be filled with unconnected and non-functional metal shapes.

Post last wiring level inductor using patterned plate process

A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

Planar cavity MEMS and related structures, methods of manufacture and design structures

A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower wiring layer on a substrate. The method further includes forming a plurality of discrete wires from the lower wiring layer. The method further includes forming an electrode beam over the plurality of discrete wires. The at least one of the forming of the electrode beam and the plurality of discrete wires are formed with a layout which minimizes hillocks and triple points in subsequent silicon deposition.

ON-CHIP SIGNAL TRANSFORMER FOR GROUND NOISE ISOLATION

A mixed-signal chip having a signal transformer located between analog circuitry and digital circuitry. The signal transformer includes a primary winding electrically coupled to the analog circuitry and a secondary winding electrically coupled to the digital circuitry. The primary and secondary windings are magnetically coupled with one another via a magnetic core. The magnetic coupling between the primary and secondary windings inhibits the coupling of electrical noise between the analog and digital circuitries.

DESIGN STRUCTURE INCORPORATING VERTICAL PARALLEL PLATE CAPACITOR STRUCTURES

Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a vertical parallel plate capacitor structure with a first plurality of conductive plates and a second plurality of conductive plates having an overlying relationship with the first plurality of conductive plates. The first plurality of conductive plates are spaced apart by a first distance. The second plurality of conductive plates are spaced apart by a second distance different than the first distance

Passive Components in the Back End of Integrated Circuits

Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.

Semiconductor structures and methods of manufacture

Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.

Semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure

Disclosed is a semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure. The structure comprises a semiconductor device (e.g., a two-terminal device, such as a PN junction diode or Schottky diode, or a three-terminal device, such as a field effect transistor (FET), a bipolar junction transistor (BJT), etc.) and a dielectric layer that covers the semiconductor device. A contact extends vertically through the dielectric layer to a terminal of the semiconductor device (e.g., in the case of a FET, to a source/drain region of the FET). A contact sidewall spacer is positioned on the contact sidewall and incorporates an airgap. Since air has a lower dielectric constant than other typically used dielectric spacer or interlayer dielectric materials, the contact size can be increased for reduced parasitic resistance while minimizing corresponding increases in parasitic capacitance or the probability of shorts.

Tri-metal and dual-metal stacked inductors

A high performance inductor which has a relatively low sheet resistance that can be integrated within a semiconductor interconnect structure and can be used in RF applications, including RF CMOS and SiGe technologies, is provided. The inductor is either a dual-metal inductor including a first layer of metal which serves as an upper metal wire in the semiconductor structure and a second layer of metal located directly on top of the first layer of metal, or a tri metal inductor, which includes a third layer of metal located directly on top of the second layer of metal. No vias are located between the various metal layers of the inventive inductor.

VERTICAL LC TANK DEVICE

An LC tank structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.

TOP CORNER ROUNDING OF DAMASCENE WIRE FOR INSULATOR CRACK SUPPRESSION

A structure and method for fabricating the structure that provides a metal wire having a first height at an upper surface. An insulating material surrounding said metal wire is etched to a second height below said first height of said upper surface. The metal wire from said upper surface, after etching said insulating material, is planarized to remove sufficient material from a lateral edge portion of said metal wire such that a height of said lateral edge portion is equivalent to said second height of said insulating material surrounding said metal wire. 1. A structure comprising:a metal wire having a first height at a central portion, a second height at a first distal edge less than said first height, and a radius defined from said second height at said first distal edge to said first height at said central portion; andan insulating material surrounding said metal wire to said second height at said first distal edge of said metal wire,said first height of said metal wire extending above said second height of said first distal edge and said insulating material.2. The structure according to claim 1 , said metal wire comprising a non-planar damascene metal wire.3. The structure according to claim 2 , said non-planar metal wire comprising Cu.4. The structure according to claim 1 , said insulating material comprising an oxide material.5. The structure according to claim 4 , said oxide material comprising SiO.6. The structure according to claim 1 , a coefficient of thermal expansion of said metal wire being greater than 10 times a coefficient of thermal expansion of said insulating material.7. The structure according to claim 1 , said metal wire having a second distal edge equal to said second height and a second radius defined from said second height at said second distal edge to said first height at said central portion.8. A structure comprising:a non-planar damascene metal wire having a first height at a central portion, a second height at a first distal edge less ...

Method for making a dielectric region in a bulk silicon substrate providing a high-Q passive resonator

Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in <100> directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

SEMICONDUCTOR CHIP WITH A DUAL DAMASCENE WIRE AND THROUGH-SUBSTRATE VIA (TSV) STRUCTURE

Disclosed is a semiconductor chip having a dual damascene insulated wire and insulated through-substrate via (TSV) structure and methods of forming the chip. The methods incorporate a dual damascene technique wherein a trench and via opening are formed in dielectric layers above a substrate such that the trench is above a first via and the via opening is positioned adjacent to the first via and extends vertically from the trench and into the substrate. Dielectric spacers are formed on the sidewalls of the trench and via opening. A metal layer is deposited to form an insulated wire in the trench and an insulated TSV in the via opening. Thus, the insulated wire electrically connects the insulated TSV to the first via and, thereby to an on-chip device or lower metal level wire below. Subsequently, the substrate is thinned to expose the insulated TSV at the bottom surface of the substrate.

Integrated thin-film resistor with direct contact

A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.

LOCAL WIRING FOR A BIPOLAR JUNCTION TRANSISTOR INCLUDING A SELF-ALIGNED EMITTER REGION

Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing. 1. A method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter , comprising:performing an etch to remove the sacrificial emitter to form an emitter opening between nitride spacers;depositing an in-situ doped emitter into the emitter opening;performing a recess etch to partially remove a portion of the in-situ doped emitter;depositing a silicon dioxide layer over the recessed in-situ doped emitter;planarizing the silicon dioxide layer via chemical mechanical polishing;etching an emitter trench over the recessed in-situ doped emitter; anddepositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.2. The method of claim 1 , further comprising etching at least one base trench in base regions of the bipolar junction transistor.3. The method of claim 2 , further comprising depositing tungsten and forming wiring in the at least one base trench via chemical mechanical polishing.4. The method of claim 1 , further comprising claim 1 , prior to performing the etch to remove the sacrificial emitter claim 1 , performing a silicon dioxide etch to form base trenches in base regions of ...

BACK-END-OF-LINE METAL-OXIDE-SEMICONDUCTOR VARACTORS

Device structures, design structures, and fabrication methods for a varactor. The device structure includes a first electrode formed on a dielectric layer, and a semiconductor body formed on the first electrode. The semiconductor body is comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state. The device structure further includes an electrode insulator formed on the semiconductor body and a second electrode formed on the electrode insulator. 1. A method of fabricating a device structure , the method comprising:forming a first conductive layer on a dielectric layer;forming a semiconductor layer on the first conductive layer, the semiconductor layer comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state;forming a source region and a drain region in the semiconductor layer;forming an insulator layer on the semiconductor layer; andforming a second conductive layer on the insulator layer.2. The method of wherein forming the semiconductor layer on the first conductive layer comprises:depositing the silicon-containing semiconductor material in the amorphous state on the first conductive layer to form the semiconductor layer.3. The method of comprising:applying a patterned mask partially covering the semiconductor layer; andafter the mask is applied, etching the semiconductor layer selective to the first conductive layer to form a semiconductor body of the device structure where the semiconductor layer is partially covered by the patterned mask.4. The method of comprising:after the semiconductor layer is etched, laser annealing the semiconductor body to convert the silicon-containing semiconductor material from the amorphous state to the polycrystalline state.5. The method of further comprising:applying a first mask partially covering the second conductive layer;after the first mask is applied, etching the second conductive layer selective to the semiconductor layer to form ...

On-chip transmission line structures with balanced phase delay

A transmission wiring structure, associated design structure and associated method for forming the same. A structure is disclosed having: a plurality of wiring levels formed on a semiconductor substrate; a pair of adjacent first and second signal lines located in the wiring levels, wherein the first signal line comprises a first portion formed on a first wiring level and a second portion formed on a second wiring level; a primary dielectric structure having a first dielectric constant located between the first portion and a ground shield; and a secondary dielectric structure having a second dielectric constant different than the first dielectric constant, the secondary dielectric structure located between the second portion and the ground shield, and the second dielectric layer extending co-planar with the second portion and having a length that is substantially the same as the second portion.

Method and structure for creation of a metal insulator metal capacitor

The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.

Copper wire and dielectric with air gaps

Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

DESIGN STRUCTURES INCLUDING MEANS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES

A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

Passive components in the back end of integrated circuits

Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.

TSV WITH END CAP, METHOD AND 3D INTEGRATED CIRCUIT

A through silicon via (TSV), method and 3D integrated circuit are disclosed. The TSV extends through a substrate to a back side of the substrate and includes a body including a first metal for coupling to an interconnect on a front side of the substrate. A dielectric collar insulates the body from the substrate. The TSV also includes an end cap coupled to the body on the back side of the substrate, the end cap including a second metal that is different than the first metal. The end cap acts as a grinding stop indicator during back side grinding for 3D integration processing, preventing damage to the dielectric collar and first metal (e.g., copper) contamination of the substrate. 1. A through silicon via (TSV) extending through a substrate to a back side of the substrate , the TSV comprising:a body including a first metal for coupling to an interconnect on a front side of the substrate;a dielectric collar insulating the body from the substrate; andan end cap coupled to the body on the back side of the substrate, the end cap including a second metal that is different than the first metal.2. The TSV of claim 1 , wherein the end cap indicates a grinding stop point during grinding to remove a back side of the substrate for three dimensional integration processing.3. The TSV of claim 1 , wherein the end cap extends past an end of the dielectric collar.4. The TSV of claim 1 , wherein the first metal includes copper and the second metal includes one of: a silicide and a refractory metal.5. The TSV of claim 4 , wherein the silicide includes nickel claim 4 , and the refractory metal includes tungsten.6. The TSV of claim 1 , wherein the first metal includes copper and the second metal includes one of a non-copper metal and a non-copper metal alloy.7. The TSV of claim 1 , wherein the end cap couples to a backside metallization.8. A method comprising:forming a device layer on a substrate;forming a through silicon via (TSV) opening in the substrate, the TSV opening including a ...

Terminal pad structures and methods of fabricating same

Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.

Vertical LC tank device

An LC tack structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.

Dielectric region in a bulk silicon substrate providing a high-Q passive resonator

Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in <100> directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

Structure, Design Structure and Method of Manufacturing a Structure Having VIAS and High Density Capacitors

A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.

ONE-MASK HIGH-K METAL-INSULATOR-METAL CAPACITOR INTEGRATION IN COPPER BACK-END-OF-LINE PROCESSING

A MIM capacitor technique is described wherein bottom plates (electrodes) are composed of gate conductor material, and are formed in the same layer, in the same way, using the same masking and processing steps as transistor gates. The top plates (electrodes) are formed using a simple single-mask, single-damascene process. Electrical connections to both electrodes of the MIM capacitor are made via conventional BEOL metallization, requiring no additional dedicated process steps. The bottom plates (formed of gate conductor material) of the MIM capacitors overlie STI regions formed at the same time as STI regions between transistors. Method and apparatus are described.

DESIGN STRUCTURE FOR METAL-INSULATOR-METAL CAPACITOR USING VIA AS TOP PLATE AND METHOD FOR FORMING

A design structure for a metal-insulator-metal (MIM) capacitor using a via as a top plate and method for forming is described. In one embodiment, the MIM capacitor structure comprises a bottom plate and a capacitor dielectric layer formed on the bottom plate and at least one via formed on the capacitor dielectric layer. The at least one via provides a top plate of the MIM capacitor.

Semiconductor structures having low resistance paths throughout a wafer

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

INTEGRATION OF A MIM CAPACITOR OVER A METAL GATE OR SILICIDE WITH HIGH-K DIELECTRIC MATERIALS

A Metal Insulator-Metal (MIM) capacitor is formed on a semiconductor substrate with a base comprising a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. An ancillary MIM capacitor plate is selected either a lower electrode formed on the STI region in the semiconductor substrate or a doped well formed in the top surface of the semiconductor substrate. A capacitor HiK dielectric layer is formed on or above the MIM capacitor lower plate. A second MIM capacitor plate is formed on the HiK dielectric layer above the MIM capacitor lower plate.

ELECTROMIGRATION RESISTANT ALUMINUM-BASED METAL INTERCONNECT STRUCTURE

A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.

Isolated wire structures with reduced stress, methods of manufacturing and design structures

An integrated circuit (IC) including a set of isolated wire structures disposed within a layer of the IC, methods of manufacturing the same and design structures are disclosed. The method includes forming adjacent wiring structures on a same level, with a space therebetween. The method further includes forming a capping layer over the adjacent wiring structures on the same level, including on a surface of a material between the adjacent wiring structures. The method further includes forming a photosensitive material over the capping layer. The method further includes forming an opening in the photosensitive material between the adjacent wiring structures to expose the capping layer. The method further includes removing the exposed capping layer.

VERTICAL LC TANK DEVICE

An LC tack structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.

MIM CAPACITOR AND METHOD OF MAKING SAME

A MIM capacitor device and method of making the device. The device includes an upper plate comprising one or more electrically conductive layers, a dielectric block comprising one or more dielectric layers, a lower plate comprising one or more electrically conductive layer; and a spreader plate comprising one or more electrically conductive layers.

Structure for on chip shielding structure for integrated circuits or devices on a substrate

A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure comprises: a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate and at least one feed through capacitor and one transmission line associated with the conductive structure and providing the power supply and signals to the circuit or circuit device respectively. The design structure also comprises a shielding structure surrounding a circuit or a circuit device arranged on a substrate and at least one feed through capacitor or a transmission line arranged on a side of the shielding structure.

POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS

A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above a top surface of the substrate; an insulative layer on and above a top surface of the capping layer; an inductor comprising a first portion in and above the insulative layer and a second portion only above the insulative layer; and a wire bond pad within the insulative layer, wherein the first portion the inductor has a height in a first direction greater than a height of the wire bond pad in the first direction, wherein the first direction is perpendicularly directed from the top surface of substrate toward the insulative layer.

Semiconductor switching device employing a quantum dot structure

A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a thickness less than 2 nm to enable quantum tunneling effects. A source-side conductive material portion and a drain-side conductive material portion abuts the two portions of the at least one dielectric material layer. A gate conductor is located on the at least one dielectric material layer between the source-side conductive material portion and the drain-side conductive material portion. The potential of the semiconductor island responds to the voltage at the gate conductor to enable or disable tunneling current through the two portions of the at least one dielectric material layer. Design structures for the semiconductor device are also provided.

MIM capacitor and method of making same

A MIM capacitor device and method of making the device. The device includes an upper plate comprising one or more electrically conductive layers, a dielectric block comprising one or more dielectric layers, a lower plate comprising one or more electrically conductive layer; and a spreader plate comprising one or more electrically conductive layers.

INTEGRATED MILLIMETER WAVE ANTENNA AND TRANSCEIVER ON A SUBSTRATE

A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.

On-chip inductor with magnetic core

An inductor formed on an integrated circuit chip including one or more inner layers between two or more outer layers, inductor metal winding turns included in one or more inner layers, and a magnetic material forming the two or more outer layers and the one or more inner layers. In one embodiment, the magnetic material is a photoresist paste having magnetic particles. In another embodiment, the magnetic material is a series of magnetic metallic strips disposed on each of first and second portions of the two or more outer layers and on each of the one or more inner layers. The series of magnetic metallic strips on the first and second portions form a grid pattern. Other embodiments include an adjustable controlled compound deposit and control windings with adjustable electrical currents.

COMPOSITE COPPER WIRE INTERCONNECT STRUCTURES AND METHODS OF FORMING

Various embodiments include interconnect structures and methods of forming such structures. The interconnect structures can include a composite copper wire which includes at least two distinct copper sections. The uppermost copper section can have a thickness of approximately 1 micrometer or less, which inhibits surface roughening in that uppermost section, and helps to enhance cap adhesion with overlying layers. 1. An interconnect structure comprising:a substrate having a recess with a bottom surface and sidewalls; a liner layer over the bottom surface and the sidewalls of the recess;', 'a first copper layer over the liner layer, the first copper layer having a first thickness of approximately two micrometers or greater;', 'a copper grain growth barrier layer over the first copper layer; and', 'a second copper layer over the copper grain growth barrier layer, the second copper layer having a second thickness that is substantially less than the first thickness, the second thickness inhibiting surface roughness in the second copper layer., 'a composite copper wire formed within the recess in the substrate, the composite copper wire including2. The interconnect structure of claim 1 , wherein the second thickness is equal to approximately one (1) micrometer or less.3. The interconnect structure of claim 1 , further comprising:a copper diffusion layer over the composite copper wire;an insulator layer overlying the copper diffusion layer; anda via contact extending through the insulator layer and contacting the composite wire.4. The interconnect structure of claim 3 , wherein the via contact contacts the composite wire at the second copper layer.5. The interconnect structure of claim 3 , wherein the copper diffusion layer includes at least one of silicon nitride (SiN) claim 3 , a metal or cobalt tungsten phosphide (CoWP).6. The interconnect structure of claim 3 , further comprising a border layer separating the insulator layer and the substrate.7. The interconnect ...

Integrated parallel plate capacitors

A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.

POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS

A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An iductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

Top corner rounding of damascene wire for insulator crack suppression

A structure and method for fabricating the structure that provides a metal wire having a first height at an upper surface. An insulating material surrounding said metal wire is etched to a second height below said first height of said upper surface. The metal wire from said upper surface, after etching said insulating material, is planarized to remove sufficient material from a lateral edge portion of said metal wire such that a height of said lateral edge portion is equivalent to said second height of said insulating material surrounding said metal wire.

DIELECTRIC REGION IN A BULK SILICON SUBSTRATE PROVIDING A HIGH-Q PASSIVE RESONATOR

Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in <100> directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC. 1. A structure , comprising:a bulk silicon (Si) substrate having a bottom and a top, opposite said bottom, said bulk Si substrate comprising a dielectric region extending into said bulk Si substrate from said top, said dielectric region having vertical sidewalls oriented perpendicular to said bottom;a hard mask overlying said top of said bulk Si substrate, said hard mask comprising openings to said dielectric region;a dielectric layer overlying said hard mask and said dielectric region, said dielectric layer filling said openings to said dielectric region;a metallization layer overlying said dielectric layer; anda passive resonator formed in said metallization layer, said passive resonator overlying said dielectric region.2. The structure according to claim 1 , further comprising:a passivation layer above said dielectric layer and beneath said passive resonator.3. The structure according to claim 1 , said dielectric region comprising silicon oxide.4. The structure according to claim 1 , said hard mask comprising one of silicon oxide and silicon nitride.5. The structure according to claim 1 , said openings including any of square holes claim 1 , rectangular holes claim 1 , and a combination of square holes and rectangular holes.6. The structure according to claim 1 , said dielectric layer comprising one of a silicon oxide and a silicon nitride.7. The structure according to claim 1 , said passive resonator comprising one of an inductor and a capacitor.8. A device claim 1 , comprising: a bulk ...

SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE

Semiconductor structures with airgaps and/or metal linings and methods of manufacture are provided. The method of forming an airgap in a wiring level includes forming adjacent wires in a dielectric layer. The method further includes forming a masking layer coincident with the adjacent wire and forming a first layer on the masking layer to reduce a size of an opening formed in the masking layer between the adjacent wires. The method further includes removing exposed portions of the first layer and the dielectric layer to form trenches between the adjacent wires. The method further includes forming an interlevel dielectric layer upon the dielectric layer, where the interlevel dielectric layer is pinched off from filling the trenches so that an airgap is formed between the adjacent wires. A metal liner can also be formed in the trenches, prior to the formation of the airgap. 1. A method of forming an airgap in a wiring level comprising:forming adjacent wires in a dielectric layer;forming a masking layer coincident with the adjacent wires;forming a first layer on the masking layer to reduce a size of an opening formed in the masking layer between the adjacent wires;removing exposed portions of the first layer and the dielectric layer to faun trenches between the adjacent wires, wherein portions of the dielectric layer remain on sidewalls of the adjacent wires due to masking of the first layer;opening the trenches towards the adjacent wires; andforming an interlevel dielectric layer upon the dielectric layer, wherein the interlevel dielectric layer is pinched off from filling the trenches so that an airgap is formed between the adjacent wires.2. The method of claim 1 , wherein the opening of the trenches includes removing substantially all of the dielectric layer on the sidewalls within the trenches.3. The method of claim 1 , wherein the trenches are about one half of a minimum ground rule spacing.4. The method of claim 1 , wherein the first layer is one of an organic ...

METHOD OF ELECTROLYTIC PLATING AND SEMICONDUCTOR DEVICE FABRICATION

The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner. 1. A method of electrolytic plating comprising: a layer defining a feature;', 'a liner over the layer; and', 'a seed layer over the liner;, 'immersing an in-process substrate into an electrolytic plating solution, the in-process substrate includingrotating the in-process substrate in the electrolytic plating solution to form a first metal layer over the seed layer;performing a first chemical-mechanical polish (CMP) to the first metal layer and the liner on the in-process substrate,wherein a portion of the first metal layer is retained within the feature;immersing the in-process substrate into the electrolytic plating solution after the performing of the first CMP;rotating the in-process substrate in the electrolytic plating solution after the performing of the first CMP and the immersing to form a second metal layer directly on the portion of the first metal layer retained within the feature; andperforming a second chemical-mechanical polish to the liner.2. A method of electrolytic plating according to claim 1 , wherein the electrolytic plating solution comprises a copper sulfate solution claim 1 , a sulfuric acid solution claim 1 , and a solution of organic additives.3. A method of electrolytic plating according to claim 1 , wherein the immersing includes applying a current density of approximately 3 mA/cm2 to approximately 60 mA/cm2.4. A ...

INTEGRATED CIRCUIT AND INTERCONNECT, AND METHOD OF FABRICATING SAME

The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect. 1. An integrated circuit comprising:at least one trench within a dielectric layer disposed on a substrate, the trench conformally coated with a liner and seed layer; andan interconnect within the trench, the interconnect including a hard mask on sidewalls of the interconnect.2. The integrated circuit according to claim 1 , wherein the hard mask comprises an anti-seeding conductive material selected from one of titanium nitride (TiN) claim 1 , tungsten (W) claim 1 , tantalum (Ta) claim 1 , and tantalum nitride (TaN).3. The integrated circuit according to claim 1 , wherein the hard mask comprises a dielectric material selected from one of silicon nitride (SiN) claim 1 , silicon carbide (SiC) claim 1 , and aluminum oxide (AlO).4. The integrated circuit according to claim 1 , wherein the interconnect comprises a material selected from one of copper claim 1 , silver claim 1 , and gold.5. The integrated circuit according to claim 1 , wherein the interconnect is approximately 5 microns (μm) to approximately 150 μm an wide.6. The integrated circuit according to claim 1 , wherein the interconnect is an inductor or a transmission line.7. A method of fabricating an interconnect in an integrated circuit claim 1 , the method comprising:conformally coating a trench with a liner and seed layer, the trench being within a dielectric layer disposed on a substrate;depositing a hard mask on the liner and seed layer;masking and patterning the trench to expose the hard mask;removing exposed areas of the hard mask to expose areas of the liner and seed layer; ...

STRUCTURE AND DESIGN STRUCTURE FOR HIGH-Q VALUE INDUCTOR AND METHOD OF MANUFACTURING THE SAME

Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical. 1. A method of manufacturing a high Q-inductor , comprising:simultaneously forming a plurality of vertical openings in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors;depositing a dielectric layer in the plurality of vertical openings;depositing a metal layer on the dielectric layer in the plurality of vertical openings; andplanarazing a backside of the substrate to expose the metal layer in the first of the plurality of vertical openings.2. The method of claim 1 , wherein the planarazing the backside of the substrate results in a thickness of about 50 to 300 um.3. The method of claim 1 , wherein the substrate has a resistivity on an order of about 1000 Ω-cm.4. The method of claim 1 , further comprising forming a lower epitaxial layer on the substrate with resistivity on an order of about 10 Ω-cm.5. The method of claim 1 , wherein the second of the plurality of vertical openings is about 20% or more smaller in width than the first of the plurality of openings and the smaller opening slows down a deep silicon etch rate ...

SEMICONDUCTOR SWITCHING CIRCUIT EMPLOYING QUANTUM DOT STRUCTURES

A semiconductor circuit includes a plurality of semiconductor devices, each including a semiconductor islands having at least one electrical dopant atom and located on an insulator layer. Each semiconductor island is encapsulated by dielectric materials including at least one dielectric material portion. Conductive material portions, at least one of which abut two dielectric material portions that abut two distinct semiconductor islands, are located directly on the at least one dielectric material layer. At least one gate conductor is provided which overlies at least two semiconductor islands. Conduction across a dielectric material portion between a semiconductor island and a conductive material portion is effected by quantum tunneling. The conductive material portions and the at least one gate conductor are employed to form a semiconductor circuit having a low leakage current. A design structure for the semiconductor circuit is also provided. 1. A semiconductor structure comprising:first and second semiconductor portions, each including at least one dopant atom and encapsulated by dielectric materials, wherein said dielectric materials include an insulator layer located directly beneath said first and second semiconductor portions, a first dielectric material layer abutting said first semiconductor portion, and a second dielectric material layer abutting said second dielectric material portion;a gate conductor vertically abutting a top surface of said first dielectric material layer, a top surface of said second dielectric material layer, and a top surface of said insulator layer; anda conductive material portion abutting a portion of said first dielectric material layer and a portion of said second dielectric material layer, wherein said first and second dielectric material layers have a thickness less than 2 nm to enable quantum tunneling of electrical current into or from said conductive material portion.2. The semiconductor structure of claim 1 , wherein said ...

STRUCTURE AND DESIGN STRUCTURE FOR HIGH-Q VALUE INDUCTOR AND METHOD OF MANUFACTURING THE SAME

Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical. 1. A design structure embodied in a machine readable storage medium for designing , manufacturing , or testing an integrated circuit , the design structure comprising:a first set of openings in a substrate;a second set of vertical openings in a spiral shape in the substrate, the second set of openings being shallower and narrower than the first second of openings;a dielectric liner lining the first and second set of openings;a metal layer in the first and second set of openings with the metal layer in the first openings being exposed on a backside of the substrate; anda metal material on the backside of the substrate in contact with the metal layer exposed in the first openings.2. The design structure of claim 1 , wherein the design structure comprises a netlist.3. The design structure of claim 1 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.4. The design structure of claim 1 , wherein the design structure resides in a programmable gate array.5. A structure comprising:a first set of vertical openings in a substrate;a second set of vertical openings in a spiral shape in the ...

Interconnect structures and design structures for a radiofrequency integrated circuit

Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.

CORNER-ROUNDED STRUCTURES AND METHODS OF MANUFACTURE

Corner-rounded structures and methods of manufacture are provided. The method includes forming at least two conductive wires with rounded corners on a substrate. The method further includes forming a insulator film on the substrate and between the at least two conductive wires with the rounded corners. 1. A method , comprising:forming at least two conductive wires with rounded corners on a substrate; andforming a insulator film on the substrate and between the at least two conductive wires with the rounded corners.2. The method of claim 1 , wherein the at least two conductive wires comprise at least one of aluminum and copper.3. The method of claim 1 , wherein a distance between the at least two conductive wires is within a range of 5 μm-200 nm claim 1 , with the insulator film therebetween.4. The method of claim 3 , wherein the distance between the at least two conductive wires is within a range of 5 μm-30 μm claim 3 , with the insulator film therebetween.5. The method of claim 1 , wherein a width of each of the at least two conductive wires is within a range of 5 μm-200 μm.6. The method of claim 1 , wherein the rounded corners comprise outside rounded corners where outside edges of the at least two conductive wires meet.7. The method of claim 1 , wherein the rounded corners comprise inside rounded corners where inside edges of the at least two conductive wires meet.8. The method of claim 1 , wherein the rounded corners comprise:outside rounded corners where outside edges of the at least two conductive wires meet; andinside rounded corners where inside edges of the at least two conductive wires meet.9. The method of claim 1 , wherein a radius of curvature of each of the rounded corners is within a range of 1 μm-10 μm.10. The method of claim 9 , wherein the radius of curvature of each of the rounded corners is within a range of 2 μm-8 μm.11. The method of claim 10 , wherein the radius of curvature of each of the rounded corners is 5 μm.12. The method of claim 1 , ...

STRUCTURE AND METHOD FOR REDUCING VERTICAL CRACK PROPAGATION

A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers. 1. A semiconductor device comprising:an insulator; and at least one first dielectric insulator portion;', 'at least one first conductor within said first dielectric insulator portion;', 'at least one first nitride cap covering said first conductor;', 'at least one second dielectric insulator portion,', 'at least one second conductor within said second dielectric insulator portion; and', 'a second nitride cap covering said second conductor,, 'a plurality of vertically stacked layers on said insulator, each of said vertically stacked layers includingsaid first conductor within said vertically stacked layers forming first vertically stacked conductor layers,said second conductor within said vertically stacked layers forming second vertically stacked conductor layers,said first vertically stacked conductor layers being proximate said second vertically stacked conductor layers,each of said vertically stacked layers further including an inter-stack ...

METHOD OF MANUFACTURING COMPLIMENTARY METAL-INSULATOR-METAL (MIM) CAPACITORS

A low capacitance density, high voltage MIM capacitor and the high density MIM capacitor and a method of manufacture are provided. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor. 1. A method comprising: forming a first metal plate;', 'forming a high-k dielectric layer on the first metal plate;', 'forming a second metal plate on the high-k dielectric layer;', 'forming a low-k dielectric layer on the second metal plate; and', 'forming an upper metal plate on the low-k dielectric layer;, 'forming a plurality of plates and a plurality of dielectric layers interleaved with one another, wherein the forming the plurality of plates and the plurality of dielectric layers comprises at leastpatterning the upper metal plate by removing portions thereof;patterning portions of the low-k dielectric layer and the second metal plate; andpatterning portions of the high-k dielectric layer and first metal plate.2. The method of claim 1 , wherein the patterning portions of the high-k dielectric layer and first metal plate forms two distinct claim 1 , separate lower plates used for a low capacitance density claim 1 , high voltage MIM capacitor and high density capacitor.3. The method of claim 2 , wherein:the low capacitance density, high voltage MIM capacitor comprises the first metal plate, the high-k dielectric layer, the second metal plate, the low-k dielectric layer and the upper metal plate; andhigh density capacitor comprises the first metal plate and the high-k dielectric layer.4. The method of claim 1 , further comprising:etching a portion of an uppermost plate of the plurality of ...

TOP CORNER ROUNDING OF DAMASCENE WIRE FOR INSULATOR CRACK SUPPRESSION

A structure and method for fabricating the structure that provides a metal wire having a first height at an upper surface. An insulating material surrounding said metal wire is etched to a second height below said first height of said upper surface. The metal wire from said upper surface, after etching said insulating material, is planarized to remove sufficient material from a lateral edge portion of said metal wire such that a height of said lateral edge portion is equivalent to said second height of said insulating material surrounding said metal wire. 1. A method comprising:providing a metal wire within an insulating material;etching said insulating material to leave an exposed portion of said metal wire extending from said insulating material, said exposed portion having a central portion and distal edges; andpolishing said exposed portion of said metal wire, after etching said insulating material, to round said distal edges of said exposed portion of said metal wire, said polishing removing corners of said exposed portion of said metal wire such that said distal edges are reduced to a level approximately equal to a surface of said insulating material after etching and leaving said central portion of said exposed portion of said metal wire extending from said insulating material.2. The method according to claim 1 , said providing said metal wire further comprising damascene formation of said metal wire within said insulating material.3. The method according to claim 1 , said insulating material comprising an oxide material.4. The method according to claim 1 , a coefficient of thermal expansion of said metal wire being greater than 10 times a coefficient of thermal expansion of said insulating material.5. The method according to claim 1 , said polishing comprising soft-pad Chemical-Mechanical Polishing (CMP) using between 2 to 4 Pascals of downward force claim 1 , a wafer rotation between 50 to 150 revolutions-per-minute (RPM) claim 1 , a polish pad rotation ...

STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING

A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region. 1. A structure comprising:a substrate comprising a region having a circuit or device which is sensitive to electrical noise and electronic noise;a first isolation structure extending through an entire thickness of the substrate and surrounding the region; anda second isolation structure extending through the entire thickness of the substrate and surrounding the region, wherein the first isolation structure and the second isolation structure are formed as one of a continuous ring structure, a segmented ring structure having offset portions, and a combination thereof.2. The structure of claim 1 , wherein the first isolation structure and the second isolation structure are formed as continuous ring structures.3. The structure of claim 1 , wherein the first isolation structure and the second isolation structure are formed as segmented ring structures.4. The structure of claim 1 , further comprising at least a third isolation structure surrounding the first isolation structure and the second isolation structure.5. A structure comprising:at least one via extending partially in a substrate and filled with a metal comprising one of copper and tungsten;{'sub': '2', 'at least one via extending partially in the substrate and filled with a dielectric comprising SiO, an upper surface of the metal and the dielectric being exposed, wherein the metal and the dielectric is expose at an end opposing the exposed surface of the metal and the dielectric; and'}a metal layer in contact with a surface of the substrate to contact the exposed end of the metal and the dielectric to provide an electrical noise ...

STRUCTURE AND METHOD FOR REDUCING VERTICAL CRACK PROPAGATION

A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers. 1. A method of fabricating a semiconductor device , said method comprising:forming an insulator;forming a plurality of vertically stacked insulator layers on said insulator in a process that includes embedding first metal conductors and second metal conductors in each of said stacked insulator layers to form a plurality of first vertically stacked metal layers and a plurality of second vertically stacked metal layers proximate said first vertically stacked layers; andforming at least one air gap in an inter-stack material of said vertically stacked insulator layers between said first vertically stacked metal layers and said second vertically stacked metal layers.2. The method according to claim 1 , further comprising:positioning said air gap less than 10 μm between a first side edge of said first plurality of vertically stacked metal layers and a second side edge said second plurality of vertically stacked metal layers.3. The method according ...

Thick On-Chip High-Performance Wiring Structures

Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire. 1. A method of fabricating a back-end-of-line wiring structure , the method comprising:forming a first wire in a first dielectric layer;annealing the first wire in an oxygen-free atmosphere;after annealing the first wire, forming a second wire in alignment with the first wire; andforming a final passivation layer comprised of an organic material that covers an entirety of a sidewall of the second wire.2. The method of wherein forming the first wire in the first dielectric layer comprises:depositing the first dielectric layer;etching a trench in the first dielectric layer; anddepositing a conductor layer that partially resides in the trench to define the first wire and that covers a top surface of the first dielectric layer.3. The method of wherein further comprising:after annealing, removing the conductor layer from the top surface of the first dielectric layer so that the top surface of the first wire is planarized relative to the top surface of the first dielectric layer.4. The method of wherein the conductor layer is removed from the top surface of the first dielectric layer by chemical-mechanical polishing.5. The method of wherein the oxygen-free atmosphere comprises nitrogen gas.6. The method of wherein the first wire is annealed at a temperature in a range of 250° C. to 425° C.7. The method of wherein the second wire is formed in direct contact with the first wire claim 1 , the first wire is formed by a damascene process claim 1 , ...

HETEROJUNCTION BIPOLAR TRANSISTOR WITH REDUCED SUB-COLLECTOR LENGTH, METHOD OF MANUFACTURE AND DESIGN STRUCTURE

A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer. 1. A heterojunction bipolar transistor structure comprising:a semiconductor substrate having a sub-collector region of a first conductivity type therein;a collector region of a first conductivity type overlying a first portion of the sub-collector region, the collector region having a lower impurity concentration than the sub-collector region;an intrinsic base layer of a second conductivity type overlying at least a portion of the collector region;an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer;an isolation region extending vertically between the extrinsic base layer and a second portion of the sub-collector region;an emitter of the first conductivity type overlying a portion of the intrinsic base layer; anda collector contact electrically connected to the sub-collector region, the collector contact extending through at least a portion of the extrinsic base layer.2. The heterojunction bipolar transistor structure of claim 1 , wherein the ...

INDUCTORS AND WIRING STRUCTURES FABRICATED WITH LIMITED WIRING MATERIAL

Back-end-of-line (BEOL) wiring structures and inductors, methods for fabricating BEOL wiring structures and inductors, and design structures for a BEOL wiring structure or an inductor. A feature, which may be a trench or a wire, is formed that includes a sidewall intersecting a top surface of a dielectric layer. A surface layer is formed on the sidewall of the feature. The surface layer is comprised of a conductor and has a thickness selected to provide a low resistance path for the conduction of a high frequency signal. 1. A method of fabricating a back-end-of-line wiring structure , the method comprising:forming a feature having a first sidewall intersecting a top surface of a dielectric layer; andforming a first surface layer on the first sidewall of the feature, the first surface layer comprised of a first conductor and having a thickness selected to provide a low resistance path for conducting a high frequency signal.2. The method of wherein the feature is a trench claim 1 , the first sidewall extends below the top surface of the dielectric layer claim 1 , and the first surface layer has a thickness greater than or equal to a skin depth determined at an operating frequency for the high frequency signal.3. The method of wherein the feature is a trench claim 1 , the first sidewall extends below the top surface of the dielectric layer claim 1 , the trench is only partially occupied by the first surface layer claim 1 , and further comprising:filling unoccupied space inside the trench with an electrical insulator.4. The method of wherein the feature is a trench claim 1 , the first sidewall extends below the top surface of the dielectric layer claim 1 , and further comprising:forming a second surface layer that overlaps with the electrical insulator in the trench,wherein the first and second surface layers each have a thickness greater than or equal to a respective skin depth determined at an operating frequency for the high frequency signal.5. The method of wherein ...

SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE

Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer. 1. A method , comprising:forming a metal wiring layer in an organic insulator layer;forming a protective layer over the organic insulator layer;forming a via in the organic insulator layer over the metal wiring layer;depositing a metal layer in the via and on the protective layer;patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.2. The method of claim 1 , wherein the metal layer is Al and the patterning is performed using a chlorine based reactive ion etching process.3. The method of claim 2 , wherein:the metal wiring layer is formed by an electroplating process within a via of an underlying insulator layer;a layer is formed over the metal wiring layer, and under the organic insulator layer;the Al layer is formed by a blanket deposition process; andthe forming of the via exposes the metal wiring layer.4. The method of claim 3 , wherein the organic insulator layer is one of polyimide claim 3 , BCB (Benzocyclobutene) and PBO (polybenzoxazole).5. The method of claim 1 , further comprising removing exposed portions of the protective layer after the patterning.6. The method of claim 5 , wherein the removing of the exposed portions of the protective layer is a fluorine based etching process that minimizes damage to the organic insulator layer.7. The method of claim 6 , wherein the protective layer is a metal or metal alloy claim 6 , ...

METHOD FOR FORMING THIN FILM RESISTOR AND TERMINAL BOND PAD SIMULTANEOUSLY

Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires. 1. A semiconductor structure , comprising:a last wiring level including a terminal wire, two related wires, and another wire formed in a dielectric material layer;at least one of a diffusion barrier layer and an isolation layer formed on the dielectric material layer;a terminal bond pad formed on the terminal wire;a thin film resistor formed on and conductively linking the two related wires;a cap formed on the other wire;a passivation layer formed over the terminal bond pad, the thin film resistor, and the cap; andan opening formed in the passivation layer over the terminal bond pad,wherein the terminal bond pad, the thin film resistor, and the cap are composed of portions of a common layer of refractory metal.2. The semiconductor structure of claim 1 , wherein the at least one of a diffusion barrier layer and an isolation layer comprises:the diffusion barrier layer on and contacting the dielectric material layer; andthe isolation layer on and contacting the diffusion barrier layer.3. The semiconductor structure of claim 2 , wherein the terminal bond pad contacts a top surface of the terminal wire and a top surface of the isolation layer.4. The semiconductor structure of claim 2 , wherein the thin film resistor contacts a top surface of each of the two related wires and a top surface of the isolation layer.5. The semiconductor structure of claim 1 , wherein the refractory metal is composed of TaN.6. The semiconductor structure of claim 1 , wherein the passivation layer is composed of photosensitive polyimide.7. The semiconductor structure of claim 1 , further comprising a pad film on and contacting a top surface of the terminal bond pad.8. The semiconductor structure of claim 7 , wherein the passivation layer is over portions of the pad film.9. The ...

INTEGRATED CIRCUIT INCLUDING SENSOR STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE

An Integrated Circuit (IC) and a method of making the same. In one embodiment, an integrated circuit includes: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure. 1. An integrated circuit comprising:a substrate;a first metal layer disposed on the substrate and including a sensor structure configured to indicate a condition of a portion of the integrated circuit, wherein the sensor structure includes a set of via links configured to fracture in response to a crack in the integrated circuit, each of the via links connected to each other through at least one channel to form a chain of interconnected via links; anda second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure.2. The integrated circuit of claim 1 , wherein the sensor structure has a serpentine shape.3. The integrated circuit of claim 1 , wherein the sensor structure includes a plurality of net wires communicatively connected and oriented to form a grid proximate the second metal layer.4. The integrated circuit of claim 1 , wherein the wire component includes a plurality of metal layers.5. The integrated circuit of claim 1 , wherein the first metal layer is formed in a kerf between a set of connecting pads on the integrated circuit.6. The integrated circuit of claim 1 , wherein the wire component has a thickness greater than about 6 micrometers (μm).7. The integrated circuit of claim 1 , wherein the sensor structure is configured to conduct an electrical current from a first end of the sensor structure to a second end of the sensor structure claim 1 , a characteristic of the conduction of the electrical current dependent upon a proximity of the sensor ...

SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE

Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer. 1. A method , comprising:forming an organic insulator layer on an underlying substrate, using a spin on technique;forming a wiring layer in a patterned section of the organic insulator layer using an electroplating process;forming a protective layer over the organic insulator layer;forming a via in the organic insulator layer using an etching chemistry that minimizes damage to the organic insulator layer, the via being in alignment with the wiring layer;depositing an Al layer in the via and on the protective layer;patterning the Al layer with a chlorine etch chemistry to form at least a bond structure;forming an insulating layer over the bond structure; andforming a via structure to the patterned metal layer.2. The method of claim 1 , further comprising forming a layer over the wiring layer claim 1 , and under the organic insulator layer claim 1 , wherein:the Al layer is formed by a blanket deposition process; andthe forming of the via exposes the wiring layer.3. The method of claim 1 , wherein the organic insulator layer is one of polyimide claim 1 , BCB (Benzocyclobutene) and PBO (polybenzoxazole).4. The method of claim 1 , further comprising removing exposed portions of the protective layer using a fluorine based etching process that minimizes damage to the organic insulator layer claim 1 , after the patterning.5. The method of claim 4 , wherein the protective layer is a ...

SEMICONDUCTOR STRUCTURE INCORPORATING A CONTACT SIDEWALL SPACER WITH A SELF-ALIGNED AIRGAP AND A METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE

Disclosed is a semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure. The structure comprises a semiconductor device (e.g., a two-terminal device, such as a PN junction diode or Schottky diode, or a three-terminal device, such as a field effect transistor (FET), a bipolar junction transistor (BJT), etc.) and a dielectric layer that covers the semiconductor device. A contact extends vertically through the dielectric layer to a terminal of the semiconductor device (e.g., in the case of a FET, to a source/drain region of the FET). A contact sidewall spacer is positioned on the contact sidewall and incorporates an airgap. Since air has a lower dielectric constant than other typically used dielectric spacer or interlayer dielectric materials, the contact size can be increased for reduced parasitic resistance while minimizing corresponding increases in parasitic capacitance or the probability of shorts. 1. A semiconductor structure comprisinga semiconductor device;a dielectric layer covering said semiconductor device;a contact having a sidewall and extending vertically through said dielectric layer to said semiconductor device; anda contact sidewall spacer extending vertically through said dielectric layer to said semiconductor device,said contact sidewall spacer being positioned laterally around said contact immediately adjacent to said sidewall,said contact sidewall spacer having an essentially uniform width around said contact, andsaid contact sidewall spacer comprising an airgap.2. The semiconductor structure of claim 1 , said airgap being positioned laterally adjacent to a lower portion of said sidewall and said contact sidewall spacer further comprising a dielectric cap above said airgap and positioned laterally adjacent to an upper portion of said sidewall.3. The semiconductor structure of claim 2 , said dielectric cap comprising a different dielectric material than said ...

COPPER WIRE AND DIELECTRIC WITH AIR GAPS

Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers. 1. A method of manufacturing a semiconductor structure , comprising:forming a dielectric layer with a via opening; forming a barrier layer on and over the dielectric layer;', 'depositing an electroplated material on and over the barrier layer;', 'forming a cap layer on and over the electroplated material; and', 'forming spacers on sidewalls of the electroplated material; and, 'forming a wire comprisingforming a dielectric film over and around the wire and directly contacting a top surface of the cap layer, the spacers, and a top surface of the dielectric layer with the via opening, the barrier layer comprises a first conductive material;', 'the cap layer comprises a second conductive material different than the first conductive material; and', 'the spacers comprise an insulator material., 'wherein2. The method of claim 1 , further comprising:forming a second wire; andforming an air gap in the dielectric film between the wire and the second wire.3. The method of claim 2 , wherein the second wire is on and contacting the barrier layer.4. The method of claim 3 , wherein:the second wire comprises a cap composed of a same material as the electroplated material; andthe second wire comprises sidewall spacers composed of a same material as the insulator material.5. The method of claim 1 , wherein:the first conductive material comprises Ti or TiN;the second conductive material comprises Ni or CoWP; ...

INTEGRATED CIRCUIT INCLUDING WIRE STRUCTURE AND RELATED METHOD

An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via. 1. A method , comprising:forming a dielectric layer on a substrate;forming a metal layer on the dielectric layer;forming a set of wire components from the metal layer, the set of wire components including a first wire component proximate a second wire component;depositing a bond pad on the first wire component;forming a passivation layer on the dielectric layer and about portions of the set of wire components, the passivation layer including a wire component via connected to the second wire component; andforming a wire structure above the second wire component and physically isolated from the bond pad.2. The method of claim 1 , wherein the forming the wire structure includes patterned plating of copper on at least one of the dielectric layer and the set of wire components.3. The method of claim 1 , further comprising forming a diffusion barrier on at least one of the set of wire components following the forming of the passivation layer.4. The method of claim 3 , wherein the diffusion barrier is self-aligning.5. The method of claim 1 , further comprising:depositing a pattern resist on the bond pad following the depositing of the bond pad, the pattern resist configured to prevent formation of ...

TAPERED VIA AND MIM CAPACITOR

A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit. 113-. (canceled)14. A method comprising:selecting an insulating substrate having an upper surface and having a first wire in said insulating substrate;forming a first insulating layer over said upper surface of said insulating substrate and over said first wire;forming a first tapered opening in said first insulating layer over said first wire exposing said upper surface of said first wire;forming a bottom electrode of a capacitor on said first insulating layer;forming a first conductor over said upper surface of said first wire, said first tapered opening and said first insulating layer to said bottom electrode;forming a second insulating layer over said bottom electrode; andforming a top electrode of said capacitor on said second insulating layer positioned over said bottom electrode, said top electrode having a periphery interior of a periphery of said bottom electrode.15. The method of further comprising:forming a third insulating layer over said second insulating layer and said top electrode;a second wire embedded in said third insulating layer over said top electrode; andforming a plurality of vias formed in said third insulating layer extending from said second wire to an upper surface of said top electrode of said capacitor.16. An apparatus comprising:an insulating substrate having an upper surface and having a first wire in said insulating substrate;a first insulating layer over said upper surface of said insulating substrate and over said first wire;a first tapered opening in said first insulating layer over said first wire ...

Thick On-Chip High-Performance Wiring Structures

Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.

DIELECTRIC COVER FOR A THROUGH SILICON VIA

An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical semiconductor feature. A second dielectric layer is deposited on a first dielectric layer and a top surface of a topographical semiconductor feature. The second dielectric layer is patterned to one or more portions, wherein at least one portion of the patterned second dielectric layer is over the location of the void area of the topographical semiconductor feature. A first metal layer is deposited over the second dielectric layer, at least one portion of the first dielectric layer, and a portion of the top surface of the topographical semiconductor feature. A chemical mechanical polish of the first metal layer is performed, wherein the chemical mechanical polish reaches the top surface of at least one of the one or more portions of the second dielectric layer. 1. A semiconductor structure , the structure comprising:a first dielectric layer covering a barrier layer and adjacent a topographical semiconductor feature, wherein the topographical semiconductor feature has a void area;a patterned second dielectric layer covering the void area of the topographical semiconductor feature and at least one portion of the first dielectric layer; anda first metal layer covering a portion of the topographical semiconductor feature, a portion of the patterned second dielectric layer covering the void area of the topographical semiconductor feature, and a portion of the first dielectric layer.2. The semiconductor structure of claim 1 , wherein the patterned second dielectric layer has a first thickness covering the void area of the topographical semiconductor feature and a second thickness covering the at least one portion of the first dielectric layer.3. The semiconductor structure of claim 2 , wherein the first thickness of the patterned second dielectric layer covering the void area of the topographical semiconductor feature ...

ISOLATED WIRE STRUCTURES WITH REDUCED STRESS, METHODS OF MANUFACTURING AND DESIGN STRUCTURES

An integrated circuit (IC) including a set of isolated wire structures disposed within a layer of the IC, methods of manufacturing the same and design structures are disclosed. The method includes forming adjacent wiring structures on a same level, with a space therebetween. The method further includes forming a capping layer over the adjacent wiring structures on the same level, including on a surface of a material between the adjacent wiring structures. The method further includes forming a photosensitive material over the capping layer. The method further includes forming an opening in the photosensitive material between the adjacent wiring structures to expose the capping layer. The method further includes removing the exposed capping layer. 1. A method comprising:forming a capping layer over separate metal wiring structures, including on a surface of a dielectric layer exposed within a space between the separate metal wiring structures;forming a photosensitive material over the capping layer;forming an opening in the photosensitive material between the separate metal wiring structures to expose the capping layer; andremoving the exposed capping layer.2. The method of claim 1 , further comprising:forming a bond pad and wiring structures in the dielectric layer, at a predetermined level of a structure;forming vias in the dielectric layer, exposing the bond pad and the wiring structures;forming a diffusion barrier layer within the vias and exposed portions of the dielectric layer; blocking a via over the bond pad; and', 'forming the metal in the vias over the wiring structures and over portions of the diffusion barrier layer adjacent to the vias over the wiring structures; and, 'forming a metal over the wiring structures, at a higher level of the structure, wherein the forming of the metal comprisespatterning of the metal to form the separate metal wiring structures with the space therebetween.3. The method of claim 2 , wherein the metal is copper formed by an ...

COPPER WIRE AND DIELECTRIC WITH AIR GAPS

Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers. 1. A method of manufacturing a wire in an integrated circuit , comprising:forming a wire opening in a mask;electroplating a conductive material in the wire opening;forming a cap layer on the conductive material in the wire opening and such that an uppermost surface of the cap layer is at a vertical height lower than an uppermost surface of the mask;removing the mask after the forming the cap layer;forming sidewall spacers on sides of the conductive material by: forming a spacer layer on the cap layer, on sides of the conductive material, and on horizontal upper surfaces of a seed layer; and removing portions of the spacer layer from the cap layer and from the seed layer while leaving other portions of the spacer layer on the sides of the conductive material; andforming a dielectric film on surfaces of the cap layer and the sidewall spacers.2. The method of claim 1 , further comprising:forming a barrier layer;forming the seed layer on the barrier layer; andforming the mask on the seed layer.3. The method of claim 2 , wherein the barrier layer is formed on an upper surface of a dielectric layer and on surfaces of a via opening in the dielectric layer.4. The method of claim 3 , further comprising removing exposed portions of the seed layer and exposed portions of the barrier layer after the forming the sidewall spacers.5. The method of claim 4 , further comprising oxidizing the exposed portions ...

Copper wire and dielectric with air gaps

Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

INTEGRATED CIRCUIT AND INTERCONNECT, AND METHOD OF FABRICATING SAME

The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect. 1. A method of fabricating an interconnect in an integrated circuit , the method comprising:conformally coating a trench with a liner and seed layer, the trench being within a dielectric layer disposed on a substrate;depositing a hard mask on the liner and seed layer;masking and patterning the trench to expose the hard mask;removing exposed areas of the hard mask to expose areas of the liner and seed layer;electrolytic metal plating the exposed areas of the liner and seed layer to form an interconnect; andplanarizing the interconnect with a top surface of the trench.2. The method of fabricating an interconnect according to claim 1 , wherein the hard mask comprises a material selected from one of titanium nitride (TiN) claim 1 , tungsten (W) claim 1 , tantalum (Ta) claim 1 , tantalum nitride (TaN) claim 1 , silicon nitride (SiN) claim 1 , silicon carbide (SiC) and aluminum oxide (AlO).3. The method of fabricating an interconnect according to claim 1 , wherein the interconnect comprises a material selected from one of copper claim 1 , silver claim 1 , and gold.4. The method of fabricating an interconnect according to claim 1 , wherein the interconnect is approximately 5 microns (μm) to approximately 150 μm wide.5. The method of fabricating an interconnect according to claim 1 , wherein the planarizing step includes chemical-mechanical polishing the interconnect.6. The method of fabricating an interconnect according to claim 1 , wherein the removing step includes plasma etching one or more times the exposed areas of the liner and seed layer.7. The ...

SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path. 1. A method , comprising:forming a silicide layer on a substrate;forming a low resistance conduction path in a dicing channel in an interlevel dielectric layer above the silicide layer;forming an active device on the substrate and in contact with the silicide layer;forming a second interlevel dielectric layer over the interlevel dielectric layer;patterning the second interlevel dielectric layer to form a first opening exposing the low resistance conduction path and a second opening above the active device;forming a barrier layer on sidewalls and bottoms of the first and second openings and in contact with the low resistance conduction path; andforming a seed layer in contact with the barrier layer, wherein:the low resistance conduction path comprises a plurality of vias, andthe barrier layer is formed over the plurality of vias.2. The method of claim 1 , wherein the low resistance conduction path is provided into the interlevel dielectric material and the silicide layer.3. The method of claim 1 , wherein the silicide layer is formed at a junction between the interlevel dielectric material and the underlying substrate.4. The method of claim 1 , wherein the forming the low resistance conduction path comprises etching the plurality of vias into the interlevel dielectric layer to the silicide layer and filling the plurality of vias with metal material to form metal contacts in direct contact with the silicide layer.5. The method of claim 1 , wherein the silicide layer is formed by reaction of a thin metal film with silicon through an annealing process.6. The method of claim 1 , wherein the low resistance conduction path is part of a crackstop guard ring.7. A method claim 1 , comprising: ...

Optoelectronic structures having multi-level optical waveguides and methods of forming the structures

Disclosed are structures with an optical waveguide having a first segment at a first level and a second segment extending between the first level and a higher second level and further extending along the second level. Specifically, the waveguide comprises a first segment between first and second dielectric layers. The second dielectric layer has a trench, which extends through to the first dielectric layer and which has one side positioned laterally adjacent to an end of the first segment. The waveguide also comprises a second segment extending from the bottom of the trench on the side adjacent to the first segment up to and along the top surface of the second dielectric layer on the opposite side of the trench. A third dielectric layer covers the second segment in the trench and on the top surface of the second dielectric layer. Also disclosed are methods of forming such optoelectronic structures.

CAPACITOR USING BARRIER LAYER METALLURGY

A metal-insulator-metal (MIM) capacitor using barrier layer metallurgy and methods of manufacture are disclosed. The method includes forming a bottom plate of a metal-insulator-metal (MIM) capacitor and a bonding pad using a single masking process. The method further includes forming a MIM dielectric on the bottom plate. The method further includes forming a top plate of the MIM capacitor on the MIM dielectric. The method further includes forming a solder connection on the bonding pad. 1. A method of forming a structure , comprising:forming a bottom plate of a metal-insulator-metal (MIM) capacitor and a bonding pad using a single masking process;forming a MIM dielectric on the bottom plate;forming a top plate of the MIM capacitor on the MIM dielectric; andforming a solder connection on the bonding pad.2. The method of claim 1 , wherein the bottom plate and the bonding pad are formed by a single metal deposition process and an etching process using the single masking step.3. The method of claim 2 , wherein the bottom plate and the bonding pad are formed by an aluminum deposition process.4. The method of claim 1 , further comprising forming a Ball Limiting Metallurgy (BLM) and the top plate in a same deposition process.5. The method of claim 4 , wherein the BLM and the top plate are formed by depositing a metal material on the MIM dielectric and on the bonding pad in the same deposition process.6. The method of claim 5 , further comprising patterning the metal material over the bonding pad claim 5 , using the solder connection as a masking layer.7. The method of claim 6 , further comprising forming another solder connection over the top plate of the MIM capacitor claim 6 , and patterning the metal material using the another solder connection.8. The method of claim 1 , wherein the MIM dielectric comprises depositing one of SiN claim 1 , TaO claim 1 , AlOand SiOover the bottom plate.9. The method of claim 1 , wherein the forming of the top plate of the MIM capacitor ...

SEMICONDUCTOR STRUCTURES WITH METAL LINES

Disclosed are semiconductor structures with metal lines and methods of manufacture which reduce or eliminate extrusion formation. The method includes forming a metal wiring comprising a layered structure of metal materials with an upper constraining layer. The method further includes forming a film on the metal wiring which prevents metal extrusion during an annealing process. 1. A method , comprising:forming a metal wiring comprising a layered structure of metal materials with an upper constraining layer; andforming a film on the metal wiring which prevents metal extrusion during an annealing process.2. The method of claim 1 , further comprising forming a metal-insulator-metal (MIM) capacitor on a metal island claim 1 , adjacent to the metal wiring.3. The method of claim 2 , wherein the forming of the film is a low temperature oxide (LTO) deposition process formed over the metal wiring and MIM capacitor on the metal island.4. The method of claim 1 , wherein the forming of the film is a low temperature oxide (LTO) deposition process formed over the metal wiring.5. The method of claim 4 , wherein the film is formed to a thickness of about 200 Å to about 800 Å.6. The method of claim 5 , wherein the LTO deposition process is performed at about 190° C. to about 200° C.7. The method of claim 4 , further comprising removing a portion of the film from a top surface of the metal wiring claim 4 , leaving film sidewalls that prevent the formation of the metal extrusion.8. The method o f claim 1 , wherein the forming of the film is a plasma enhanced chemical vapor deposition (PECVD) process using an oxide or nitride material.9. The method of claim 8 , further comprising removing a portion of the film from a top surface of the metal wiring claim 8 , leaving oxide or nitride film sidewalls that prevent the formation of the metal extrusion.10. The method of claim 1 , wherein:the forming of the metal wiring comprises forming a layered structure of metal including an aluminum layer ...

DIELECTRIC REGION IN A BULK SILICON SUBSTRATE PROVIDING A HIGH-Q PASSIVE RESONATOR

Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in <100> directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC. 1. A method of making a dielectric region to provide a high-Q passive resonator in a mixed-signal integrated circuit (IC) , said method comprising:patterning and etching a hard mask to form a plurality of holes along <100> directions that overlie a bulk Si substrate of a (100) Si wafer;deep trench etching said bulk Si substrate through said plurality of holes, to form a plurality of deep trenches with vertical sidewalls;wet etching of said plurality of deep trenches, to provide a plurality of cavities with thin Si sidewalls between adjacent cavities and to remove undercut regions;oxidizing of sidewalls of said plurality of cavities, including said thin Si sidewalls, to form Si oxide sidewalls;filling said plurality of cavities with a Si oxide to form said dielectric region including a plurality of Si oxide filled cavities separated by said Si oxide sidewalls;depositing and planarizing a dielectric layer over said hard mask and said dielectric region; andforming said high-Q passive resonator in metallization layers, associated with back-end-of-line (BEOL) processes in said making of said mixed-signal IC, over said dielectric region.2. The method of claim 1 , further comprising depositing a topmost front-end-of-line (FEOL) layer claim 1 , associated with FEOL processes in said making of said mixed-signal IC claim 1 , on said dielectric layer before said forming of said high-Q passive resonator.3. The method of claim 1 , said hard mask comprising one of a silicon oxide and a silicon nitride.4. The ...

FABRICATING POLYSILICON MOS DEVICES AND PASSIVE ESD DEVICES

A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes. 1. A semiconductor device comprising:at least one MEMS device, wherein the at least one MEMS device is created during a back end of line process, each of the at least one MEMS device including: (i) at least one electrode; (ii) at least one empty cavity; and (iii) at least one via; andat least one MOS device, wherein the at least one MOS device is created during a back end of line process, each of the at least one MOS device including: (i) at least one electrode; (ii) at least one layer of semiconductor; (iii) at least one via; and (iv) at least one insulator.212. The semiconductor device of claim , further comprising at least one layer of dielectric material.312. The semiconductor device of claim , further comprising at least one layer of electrically isolated substrate.412. The semiconductor device of claim , wherein the at least one insulator of the MOS device comprises an oxide.512. The semiconductor device of claim , wherein the at least one layer of semiconductor of the MOS device is doped with boron or phosphorus.616. The semiconductor device of claim , wherein laser annealing is used to activate the dopants of ...

SEGMENTED GUARD-RING AND CHIP EDGE SEALS

The present disclosure relates to semiconductor structures and, more particularly, to segmented guard-ring and chip edge seals and methods of manufacture. The structure includes: a guard ring structure formed in a low-k dielectric material; and an edge seal structure formed through the low-k dielectric material to at least a substrate underneath the low-k dielectric material. 1. A structure comprising:a guard ring structure formed in a low-k dielectric material; andan edge seal structure formed through the low-k dielectric material to at least a substrate underneath the low-k dielectric material,wherein the substrate is a silicon on insulator substrate and the edge seal structure terminates below the low-k dielectric material.2. The structure of claim 1 , wherein the low-k dielectric material is low-K SiCOH or p-SiCOH middle of the line and/or back end of the line dielectric material.3. (canceled)4. The structure of claim 1 , wherein the guard ring structure is a segmented guard ring structure.5. The structure of claim 4 , wherein the edge seal structure is a trench lined with a passivation layer and filled with a polyimide.6. The structure of claim 5 , wherein the polyimide is planarized above a last metal layer or bond pad.7. The structure of claim 1 , wherein the edge seal structure is a trench filled with oxide material which is also covering a metal insulator metal structure.8. The structure of claim 7 , wherein the trench filled with the oxide is below a last metal layer or bond pad.9. The structure of claim 8 , wherein the trench filled with the oxide includes an airgap.10. A structure comprising:a guard ring structure formed in a low-k dielectric material; andan edge seal structure formed through the low-k dielectric material to at least a substrate underneath the low-k dielectric material,wherein the edge seal structure is one or more airgaps formed in the low-k dielectric material that is pinched off with oxide.11. The structure of claim 10 , wherein the ...

TIGHT PITCH WIRINGS AND CAPACITOR(S)

The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material. 1. A structure comprising: a bottom plate of a first conductive material;', 'an insulator material on the bottom plate; and', 'a top plate of a second conductive material on the insulator material; and, 'a capacitor comprisinga plurality of wirings on a same level as the bottom plate and composed of the second conductive material.2. The structure of claim 1 , wherein the plurality of wirings and the bottom plate are spaced apart.3. The structure of claim 2 , wherein the plurality of wirings and the bottom plate are spaced apart by about 30 microns.4. The structure of claim 1 , wherein the bottom plate and the plurality of wirings have a different height.5. The structure of claim 1 , wherein the top plate and the plurality of wirings have a same height.6. The structure of claim 5 , wherein the top plate and the plurality of wirings are a same continuous stack formed at different heights of the structure.7. The structure of claim 5 , further comprising at least one sidewall spacer on the bottom plate.8. The structure of claim 7 , wherein the at least one sidewall spacer claim 7 , the top plate and the plurality of wirings are of a same material.9. The structure of claim 8 , wherein the same material is AlCu.10. The structure of claim 1 , wherein the first conductive material is different than the second conductive material claim 1 , and the second conductive material is AlCu.11. A structure comprises:a metal insulator metal (MIM) capacitor comprising a bottom plate, an insulator material on the bottom ...

OPTOELECTRONIC STRUCTURES HAVING MULTI-LEVEL OPTICAL WAVEGUIDES AND METHODS OF FORMING THE STRUCTURES

Disclosed are structures with an optical waveguide having a first segment at a first level and a second segment extending between the first level and a higher second level and further extending along the second level. Specifically, the waveguide comprises a first segment between first and second dielectric layers. The second dielectric layer has a trench, which extends through to the first dielectric layer and which has one side positioned laterally adjacent to an end of the first segment. The waveguide also comprises a second segment extending from the bottom of the trench on the side adjacent to the first segment up to and along the top surface of the second dielectric layer on the opposite side of the trench. A third dielectric layer covers the second segment in the trench and on the top surface of the second dielectric layer. Also disclosed are methods of forming such optoelectronic structures. 1. An optoelectronic structure comprising:a first dielectric layer;a first segment of an optical waveguide on said first dielectric layer;a second dielectric layer on said first dielectric layer and covering said first segment, said second dielectric layer having a bottom surface, a top surface opposite said bottom surface, and a trench extending from said top surface to said bottom surface and having a first side and a second side opposite said first side, said first side being adjacent to an end of said first segment; a first portion extending through said trench from adjacent to said first segment at said first side to said top surface at said second side; and,', 'a second portion continuous with said first portion, said second portion being on said top surface adjacent to said second side; and, 'a second segment of said optical waveguide comprisinga third dielectric layer on said top surface, covering said second portion and further filling said trench, said first segment and said second segment each having a higher refractive index than said first dielectric layer, ...

SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path. 1. A structure , comprising:low resistance conduction paths comprising a plurality of metal vias located in a dielectric material, extending to an underlying substrate of a wafer, and within dicing channels of the wafer;an upper dielectric material on the dielectric material, the upper dielectric material having an opening patterned therein directly above the plurality of metal vias;an electroplated seed layer in direct contact with the barrier layer;a barrier layer in direct contact with the low resistance conductive path; anda silicide layer at a junction between the dielectric material and the underlying substrate which is in direct contact with the plurality of metal vias.2. The structure of claim 1 , wherein the plurality of metal vias are lined with an oxide material layer claim 1 , an adhesion layer and a copper layer.3. The structure of claim 2 , wherein the adhesion layer is one of Tantalum (Ta) or Titanium (Ti).4. The structure of claim 1 , further comprising an active device in the dielectric material and positioned on the silicide layer.5. The structure of claim 4 , wherein the upper dielectric material includes another opening patterned therein directly above the active device.6. A structure claim 4 , comprising:at least one low resistance conduction path in an interlevel dielectric material, extending to an underlying substrate of a wafer, and within dicing channels of the wafer;an upper dielectric material on the interlevel dielectric material, the upper dielectric material including an opening patterned therein directly above the at least one low resistance conduction path;a barrier layer in direct contact with the low resistance conductive path;an electroplated seed ...

Semiconductor structures having low resistance paths throughout a wafer

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

AIR GAP OVER TRANSISTOR GATE AND RELATED METHOD

A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches. 1. A method of forming an air gap for a semiconductor device , the method comprising:forming an air gap mask exposing a portion of an interconnect layer over a device layer, the device layer including a transistor gate therein;etching an opening through the interconnect layer using the air gap mask above the transistor gate, the opening exposing sidewalls of a dielectric of the interconnect layer;removing the air gap mask;andforming an air gap over the transistor gate by depositing an air gap capping layer to seal the opening at a surface of the interconnect layer.2. The method of claim 1 , wherein the interconnect layer includes a local interconnect layer over the device layer and a first metal layer over the local interconnect layer claim 1 , and the dielectric of the interconnect layer about the air gap covers any conductive wire in the first metal layer or any conductive via in the local interconnect layer.3. The method of claim 1 , further comprising recessing the exposed sidewalls of the dielectric of the interconnect layer in the opening after removing the air gap mask.4. The method of claim 3 , wherein the local interconnect layer includes a local interconnect cap layer at an upper surface thereof claim 3 , and the first metal layer includes a first metal cap layer at an upper surface thereof claim 3 , andwherein recessing the exposed sidewalls of the dielectric of the interconnect layer in the opening exposes an edge of at least one of the local interconnect cap layer and the first metal cap layer in the opening.5. The method of claim 4 , wherein forming the air gap over the transistor ...

AIR GAP OVER TRANSISTOR GATE AND RELATED METHOD

A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches. 1. A semiconductor device , comprising:a transistor gate in a device layer;an interconnect layer over the device layer, the interconnect layer including a dielectric layer and a first metal layer over the dielectric layer; andan air gap extending through the interconnect layer above the transistor gate, wherein the dielectric layer is disposed adjacent to the air gap such that the dielectric layer covers any conductive wire in the first metal layer adjacent to the air gap, and any conductive via in the interconnect layer adjacent to the air gap.2. The semiconductor device of claim 1 , wherein the dielectric layer is part of a local interconnect layer disposed over the device layer.3. The semiconductor device of claim 1 , wherein the first metal layer includes a first metal cap layer at an upper surface thereof claim 1 , and wherein a width of the air gap in the first metal cap layer is less than a width of the air gap in a dielectric of the first metal layer below the first metal cap layer.4. The semiconductor device of claim 2 , wherein the interconnect layer includes a local interconnect cap layer includes at an upper surface thereof claim 2 , and the first metal layer includes a first metal cap layer at an upper surface thereof claim 2 , and an edge of at least one of the local interconnect cap layer and the first metal cap layer extends into the air gap.5. The semiconductor device of claim 1 , wherein the first metal layer includes a metal wire extending laterally parallel to the transistor gate in the device layer claim 1 , and wherein the air gap vertically extends above and below the ...

Dielectric region in a bulk silicon substrate providing a high-q passive resonator

Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in < 100> directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path. 1. A method , comprising:forming a silicide layer on an underlying substrate;forming an interlevel dielectric material on the silicide layer;forming one or more metal wiring and interconnects in the interlevel dielectric material;forming a seed layer and barrier layer on the interlevel dielectric material, contacting the underlying metal wiring and interconnects; andforming a metal wiring in contact with the seed layer.2. The method of claim 1 , wherein the seed layer is formed in direct contact with conductive material of the metal wiring and interconnects.3. The method of claim 2 , wherein the seed layer has a thickness of about 500 Å to about 1 micron.4. The method of claim 1 , wherein the metal wiring is formed by depositing and patterning a resist on the interlevel dielectric material and over the seed layer and barrier layer claim 1 , patterning the resist to form openings and depositing metal material in the openings.5. The method of claim 4 , wherein the depositing metal material in the openings is an electroplating.6. The method of claim 5 , wherein after formation of the metal wiring claim 5 , the resist is removed. The invention relates to semiconductor structures and, more particularly, to a semiconductor structure with low resistance conduction paths and methods of manufacture.Metal electro-plating is widely used for multi metal level electronic device fabrication. Electro-plating requires a low resistance conduction path between the electrodes providing the current and the entire surface of the device being plated. Resistance between the electrode contact point and any portion of the device can result in significant differences in the thickness of the plated metal ...

Semiconductor structures having low resistance paths throughout a wafer

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path. 1. A structure , comprising:at least one low resistance conduction path in a dielectric material, extending to an underlying substrate; andan electroplated seed layer in direct contact with the low resistance conduction path, provided on a surface of the dielectric material.2. The structure of claim 1 , wherein:the at least one low resistance conduction path is a metal filled via provided into the underlying substrate and within a dicing channel of a wafer; andthe metal filled via is lined with insulator material and filled with metal material; andthe electroplated seed layer is provided in a patterned opening of the dielectric material, in direct contact with the metal material of the metal filled via.3. The structure of claim 1 , wherein the at least one low resistance conduction path comprises a plurality of metal vias in the dielectric material and a silicide layer at a junction between the dielectric material and the underlying substrate which is in direct contact with the plurality of metal vias.4. The structure of claim 2 , wherein the low resistance conduction path is provided into an interlevel dielectric material and an underlying substrate.5. The structure of claim 4 , wherein the low resistance conduction path comprises at least one via in the interlevel dielectric material and the underlying substrate claim 4 , lined with an insulator material and filled with a metal material over the insulator material.6. The structure of claim 5 , wherein the at least one via is formed within a dicing channel of a wafer.7. The structure of claim 6 , wherein the at least one via is about 10 micron tall claim 6 , with a resultant resistance of about 2 mΩ/□ claim 6 , and a seed layer is a ...

SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path. 1. A method , comprising:forming a silicide layer on a substrate;forming an interlevel dielectric material over the silicide layer;forming one or more metal wiring and interconnects in the interlevel dielectric material; andforming a plurality of devices in direct contact with the silicide layer,wherein the silicide layer extends between the devices such that sides of the devices are in direct contact with the silicide layer and the interlevel dielectric material, and a center of the devices is below the one or more metal wiring and interconnects such that the devices are electrically isolated from the one or more metal wiring and interconnects.2. The method of claim 1 , further comprising forming a seed and barrier layer on a upper surface of the interlevel dielectric material.3. The method of claim 2 , wherein the seed and barrier layer contact a surface of the one or more metal wiring and interconnects.4. The method of claim 3 , wherein the seed and barrier layer contacts a conductive material of the metal wiring and interconnects.5. The method of claim 4 , further comprising:removing exposed portions of the seed layer and barrier layer by a wet etch process to expose the one or more metal wiring and interconnects; andforming a metal wiring over the exposed one or more metal wiring and interconnects.6. The method of claim 5 , wherein the metal wiring is formed by depositing and patterning a resist on the interlevel dielectric material and over the seed layer and barrier layer claim 5 , patterning the resist to form openings and depositing metal material in the openings.7. The method of claim 6 , wherein the depositing metal material in the openings is an electroplating process.8. ...

Vertical parallel plate capacitor structures

Vertical parallel plate (VPP) capacitor structures that utilize different spacings between conductive plates in different levels of the capacitor stack. The non-even spacings of the conductive plates in the capacitor stack decrease the susceptibility of the capacitor stack of the VPP capacitor to ESD-promoted failures. The non-even spacings may be material specific in that, for example, the spacings between adjacent conductive plates in different levels of the capacitor stack may be chosen based upon material failure mechanisms for plates containing different materials.

Method for forming thin film resistor and terminal bond pad simultaneously

Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.

Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure

A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.

Metal-insulator-metal capacitor and method of fabrication

A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

Planar cavity mems and related structures, methods of manufacture and design structures

Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity (60a, 60b) having a planar surface using a reverse damascene process.

Method of electrolytic plating and semiconductor device fabrication

The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.

Mim capacitor and method of making same

Non-continuous encapsulation layer for mim capacitor

The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

Integrated parallel plate capacitors

A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.

Metal-insulator-metal capacitor and method of fabrication

A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interievel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interievel dielectric layer, atop surface of the bottom electrode co-planer with a top surface of the interievel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

Method of forming a high performance fet and a high voltage fet on a SOI substrate

A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectric and a gate electrode located over the first portion of the top semiconductor layer is formed. A portion of the exposed buried insulator layer is employed as a gate dielectric for a second field effect transistor. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer.

Optimum padset for wire bonding rf technologies with high-q inductors

An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF structure includes a dielectric layer having metal inductor wires of a first thickness and a metal bond pad having a major area of a second thickness located on a surface thereof, wherein the first thickness is greater than the second thickness. In the inventive RF structure, the majority of the metal bond pad is thinned for wire bonding, while maintaining the fill metal wire thickness in the other areas of the structure for inductor performance requirements, such as, for example, low resistivity. Methods for fabricating the aforementioned RF structure are also provided.

Interlevel conductive light shield

A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.

CMOS imager array with recessed dielectric

A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having “n” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.

Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor

A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

Integrated beol thin film resistor

In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

Planar cavity mems and related structures, methods of manufacture and design structures

A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower wiring layer on a substrate. The method further includes forming a plurality of discrete wires from the lower wiring layer. The method further includes forming an electrode beam over the plurality of discrete wires. The at least one of the forming of the electrode beam and the plurality of discrete wires are formed with a layout which minimizes hillocks and triple points in subsequent silicon deposition.

Integrated thin-film resistor with direct contact

A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.

Tight pitch wirings and capacitor(s)

The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.

On chip shielding structure for integrated circuits or devices on a substrate and method of shielding

An electromagnetic shielding structure that includes a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate. At least one feed through device is associated with the conductive structure and provides signals to the circuit or circuit device. The method includes forming a shielding structure so that the shielding structure at least one of is at least partially arranged within the substrate and surrounds the circuit or circuit device and associating at least one feed through device with the shielding structure.

Fabricating polysilicon MOS devices and passive ESD devices

A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.

Dielectric cover for a through silicon via

An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical semiconductor feature. A second dielectric layer is deposited on a first dielectric layer and a top surface of a topographical semiconductor feature. The second dielectric layer is patterned to one or more portions, wherein at least one portion of the patterned second dielectric layer is over the location of the void area of the topographical semiconductor feature. A first metal layer is deposited over the second dielectric layer, at least one portion of the first dielectric layer, and a portion of the top surface of the topographical semiconductor feature. A chemical mechanical polish of the first metal layer is performed, wherein the chemical mechanical polish reaches the top surface of at least one of the one or more portions of the second dielectric layer.

Electromigration resistant aluminum-based metal interconnect structure

A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl 3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl 3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl 3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.

Semiconductor structures having low resistance paths throughout a wafer

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

Non-Continuous encapsulation layer for MIM capacitor

The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

Bipolar and CMOS integration with reduced contact height

Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.