Slurry for chemical-mechanical polishing of metals and use thereof

A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad.

Semiconductor structures having low resistance paths throughout a wafer

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) STRUCTURES AND DESIGN STRUCTURES

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam. 1. A method comprising: forming both tungsten material and semiconductor material below the MEMS beam structure;', 'forming both the tungsten material and the semiconductor material above the MEMS beam structure by forming the semiconductor material within a via in contact with the semiconductor material below the MEMS beam structure and forming the tungsten material over the semiconductor material above the MEMS beam structure; and', 'venting both the tungsten material and the semiconductor material at least above and below the MEMS beam structure to form an upper cavity structure above the MEMS beam structure and a lower cavity structure below the MEMS beam structure,, 'forming a Micro-Electro-Mechanical System (MEMS) beam structure comprisingwherein the MEMS beam structure comprises a cantilevered beam structure.2. The method of claim 1 , wherein the venting and film thicknesses are controlled to ensure that all or substantially all of the tungsten material is removed claim 1 , prior to the semiconductor material.3. The method of claim 1 , wherein the semiconductor material is one of silicon material and germanium material.4. The method of claim 3 , wherein forming the tungsten material and silicon material below the MEMS beam structure comprises forming the tungsten material on a substrate and forming the silicon material over the tungsten material.5. The method of claim 4 , wherein the venting comprising forming a vent hole to expose at least the silicon material above the MEMS beam structure and performing an XeFetching process.6. The method of claim 5 , wherein the tungsten material at least ...

Micro-electro-mechanical system (MEMS) structures and design structures

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

Planar cavity micro-electro-mechanical system and related structures, methods of manufacture and design structures

Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity (60a, 60b) having a planar surface using a reverse damascene process.

Micro-electro-mechanical system (MEMS) structures and design structures

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

Planar cavity MEMS and related structures, methods of manufacture and design structures

Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process.

Semiconductor structures having low resistance paths throughout a wafer

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) STRUCTURES AND DESIGN STRUCTURES

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam. 1. A method comprising:forming a Micro-Electro-Mechanical System (MEMS) beam structure comprising: forming both the tungsten material and the semiconductor material above the MEMS beam structure;', 'forming a lid over the tungsten material formed above the MEMS beam structure;', 'forming at least one vent hole in the lid and through the tungsten material formed above the MEMS beam structure to expose the semiconductor material formed above the MEMS beam structure; and', 'venting the semiconductor material formed above the MEMS beam structure while venting the tungsten material formed above the MEMS beam structure to form an upper cavity structure above the MEMS beam structure; and', 'venting both the tungsten material and the semiconductor material below the MEMS beam structure to form a lower cavity structure below the MEMS beam structure,, 'forming both tungsten material and semiconductor material below the MEMS beam structure;'}wherein the MEMS beam structure comprises a cantilevered beam structure.2. The method of claim 1 , wherein the venting and film thicknesses are controlled to ensure that all or substantially all of the tungsten material is removed claim 1 , prior to the semiconductor material.3. The method of claim 1 , wherein the semiconductor material is one of silicon material and germanium material.4. The method of claim 3 , wherein the tungsten material and silicon material below the MEMS beam structure comprises forming the tungsten material on a substrate and forming the silicon material over the tungsten material.5. The method of claim 4 , wherein the tungsten material and silicon ...

MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) STRUCTURES AND DESIGN STRUCTURES

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam. 1. A method comprising forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and semiconductor material at least above and below the MEMS beam structure to form an upper cavity structure above the MEMS beam structure and a lower cavity structure below the MEMS beam structure ,wherein the MEMS beam structure comprises a cantilevered beam structure, andwherein the tungsten material above the MEMS beam structure is formed in seams formed in the semiconductor material above the MEMS beam, and the venting begins with the semiconductor material above the MEMS beams structure.2. The method of claim 1 , wherein the venting and film thicknesses are controlled to ensure that all or substantially all of the tungsten material is removed claim 1 , prior to the semiconductor material.3. The method of claim 1 , wherein the semiconductor material is one of silicon material and germanium material.4. The method of claim 3 , wherein the tungsten material and silicon material below the MEMS beam structure comprises forming the tungsten material on a substrate and forming the silicon material over the tungsten material.5. The method of claim 4 , wherein the tungsten material and silicon material above the MEMS beam structure comprises forming the silicon material within a via in contact with the silicon material below the MEMS beam structure and forming the tungsten material over the silicon material.6. The method of claim 5 , wherein the venting comprising forming a vent hole to expose at least the silicon material above the MEMS beam structure and performing an XeFetching ...

Copper wire and dielectric with air gaps

Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

Planar cavity mems and related structures, methods of manufacture and design structures

A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity (60b) includes forming a first sacrificial cavity layer (18) over a wiring layer (14) and substrate (10). The method further includes forming an insulator layer (40) over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity (60b) of the MEMS.

Semiconductor structures having low resistance paths throughout a wafer

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

METHOD OF ELECTROLYTIC PLATING AND SEMICONDUCTOR DEVICE FABRICATION

The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner. 1. A method of electrolytic plating comprising: a layer defining a feature;', 'a liner over the layer; and', 'a seed layer over the liner;, 'immersing an in-process substrate into an electrolytic plating solution, the in-process substrate includingrotating the in-process substrate in the electrolytic plating solution to form a first metal layer over the seed layer;performing a first chemical-mechanical polish (CMP) to the first metal layer and the liner on the in-process substrate,wherein a portion of the first metal layer is retained within the feature;immersing the in-process substrate into the electrolytic plating solution after the performing of the first CMP;rotating the in-process substrate in the electrolytic plating solution after the performing of the first CMP and the immersing to form a second metal layer directly on the portion of the first metal layer retained within the feature; andperforming a second chemical-mechanical polish to the liner.2. A method of electrolytic plating according to claim 1 , wherein the electrolytic plating solution comprises a copper sulfate solution claim 1 , a sulfuric acid solution claim 1 , and a solution of organic additives.3. A method of electrolytic plating according to claim 1 , wherein the immersing includes applying a current density of approximately 3 mA/cm2 to approximately 60 mA/cm2.4. A ...

INTEGRATED CIRCUIT AND INTERCONNECT, AND METHOD OF FABRICATING SAME

The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect. 1. An integrated circuit comprising:at least one trench within a dielectric layer disposed on a substrate, the trench conformally coated with a liner and seed layer; andan interconnect within the trench, the interconnect including a hard mask on sidewalls of the interconnect.2. The integrated circuit according to claim 1 , wherein the hard mask comprises an anti-seeding conductive material selected from one of titanium nitride (TiN) claim 1 , tungsten (W) claim 1 , tantalum (Ta) claim 1 , and tantalum nitride (TaN).3. The integrated circuit according to claim 1 , wherein the hard mask comprises a dielectric material selected from one of silicon nitride (SiN) claim 1 , silicon carbide (SiC) claim 1 , and aluminum oxide (AlO).4. The integrated circuit according to claim 1 , wherein the interconnect comprises a material selected from one of copper claim 1 , silver claim 1 , and gold.5. The integrated circuit according to claim 1 , wherein the interconnect is approximately 5 microns (μm) to approximately 150 μm an wide.6. The integrated circuit according to claim 1 , wherein the interconnect is an inductor or a transmission line.7. A method of fabricating an interconnect in an integrated circuit claim 1 , the method comprising:conformally coating a trench with a liner and seed layer, the trench being within a dielectric layer disposed on a substrate;depositing a hard mask on the liner and seed layer;masking and patterning the trench to expose the hard mask;removing exposed areas of the hard mask to expose areas of the liner and seed layer; ...

TEST STRUCTURE AND CALIBRATION METHOD

A test structure for measuring a Micro-Electro-Mechanical System (MEMS) cavity height structure and calibration method. The method includes forming a sacrificial cavity material over a plurality of electrodes and forming an opening into the sacrificial cavity material. The method further includes forming a transparent or substantially transparent material in the opening to form a transparent or substantially transparent window. The method further includes tuning a thickness of the sacrificial cavity material based on measurements obtained through the transparent or substantially transparent window. 1. A method comprising:forming a sacrificial cavity material over a plurality of electrodes;forming an opening into the sacrificial cavity material;forming a transparent or substantially transparent material in the opening to form a transparent or substantially transparent window; andtuning a thickness of the sacrificial cavity material based on measurements obtained through the transparent or substantially transparent window.2. The method of claim 1 , wherein the forming the transparent or substantially transparent material comprises depositing an oxide material within the opening.3. The method of claim 1 , wherein the opening is sized to avoid dishing of the transparent or substantially transparent material.4. The method of claim 3 , wherein the opening is about 20 to 50 microns in diameter.5. The method of claim 1 , wherein forming the sacrificial cavity material comprises depositing silicon.6. The method of claim 1 , wherein tuning the thickness includes planarizing the sacrificial cavity material.7. The method of claim 1 , wherein tuning the thickness includes depositing additional sacrificial cavity material.8. The method of claim 1 , wherein tuning the thickness occurs in a Micro-Electro-Mechanical System (MEMS) structure and a test structure on a same wafer.9. The method of claim 8 , wherein tuning the thickness in the MEMS structure and the test structure occurs ...

Slurry for chemical-mechanical polishing of metals and use thereof

A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad.

SLURRY FOR CHEMICAL-MECHANICAL POLISHING OF COPPER AND USE THEREOF

A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol, a controlled amount of chloride ion source and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad. 1. A slurry composition , comprising:between about 0.5% by weight and about 6% by weight abrasive particles;between about 1 gm/liter and 50 gm/liter of an oxidizer;between about 0.1 ml/liter and about 100 ml/liter of surfactant anion;between about 0.1 gm/liter and about 5 gm/liter of a copper corrosion inhibitor;25 ppm to 50 ppm of a chloride ion; anda diluent.2. The slurry composition of claim 1 , including between about 0.003 ml/liter and about 3.05 ml/liter of an alkyl alcohol.3. The slurry composition of claim 2 , wherein said alkyl alcohol has between about 6 and 14 carbon atoms.4. The slurry composition of claim 2 , wherein said alkyl alcohol has the formula C(H)OH and n has a value between 6 and 14.5. The slurry composition of claim 2 , wherein said surfactant anion is octyl sulfate and said alkyl alcohol is octanol.6. The slurry composition of claim 1 , further comprising:between about 0.001 gm/liter and about 20 gm/liter a sulfate ion source.7. The slurry composition of claim 1 , comprising:35 ppm to 45 ppm of a chloride ion.8. The slurry composition of claim 1 , wherein said oxidizer comprises ferric chloride.9. A slurry composition claim 1 , consisting essentially of:between about 0.5% by weight and about 6% by weight abrasive particles;between about 1 gm/liter and 50 gm/liter of an oxidizer;between about 0.1 ml/liter and about 100 ml/liter of surfactant anion;between about 0.1 gm/liter and about 5 gm/liter of a copper corrosion inhibitor;between about 0.003 ml/liter and about 3.05 ml/liter of an alkyl alcohol;25 ppm to 50 ppm of a chloride ion; anda diluent.10. ...

COPPER WIRE AND DIELECTRIC WITH AIR GAPS

Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers. 1. A method of manufacturing a semiconductor structure , comprising:forming a dielectric layer with a via opening; forming a barrier layer on and over the dielectric layer;', 'depositing an electroplated material on and over the barrier layer;', 'forming a cap layer on and over the electroplated material; and', 'forming spacers on sidewalls of the electroplated material; and, 'forming a wire comprisingforming a dielectric film over and around the wire and directly contacting a top surface of the cap layer, the spacers, and a top surface of the dielectric layer with the via opening, the barrier layer comprises a first conductive material;', 'the cap layer comprises a second conductive material different than the first conductive material; and', 'the spacers comprise an insulator material., 'wherein2. The method of claim 1 , further comprising:forming a second wire; andforming an air gap in the dielectric film between the wire and the second wire.3. The method of claim 2 , wherein the second wire is on and contacting the barrier layer.4. The method of claim 3 , wherein:the second wire comprises a cap composed of a same material as the electroplated material; andthe second wire comprises sidewall spacers composed of a same material as the insulator material.5. The method of claim 1 , wherein:the first conductive material comprises Ti or TiN;the second conductive material comprises Ni or CoWP; ...

PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES

A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a wiring layer and substrate. The method further includes forming an insulator layer over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity of the MEMS. 1. A planar MEMS structure , comprising:a lower cavity having a planar upper surface;an upper cavity having a planar upper surface;a via connecting the upper cavity to the lower cavity;electrodes formed in the upper cavity which act as beams for the MEMS structure; anda fixed wire formed in the lower cavity, below the beams.2. The structure of claim 1 , further comprising an opening over the lower cavity.3. The structure of claim 1 , further comprising an oxide film formed over the electrodes.4. The structure of claim 1 , further comprising:an insulator material formed over the fixed wire;a first electrode of the electrodes formed over the insulator material;a second insulator material formed over the first electrode and exposed portions of the insulator material;a second electrode of the electrodes formed over the second insulator layer, and within vias to contact the first electrode;a trench in the insulator material, exposing portions of the lower cavity.5. The structure of claim 1 , wherein at least one of a corner of the upper cavity and the lower cavity are chamfered.6. The structure of claim 5 , wherein the chamfering is at a 45 degree corner angle. The invention relates to semiconductor structures and methods of manufacture and, more particularly, to planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures.Integrated ...

Methods for selective reverse mask planarization and interconnect structures formed thereby

Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.

COPPER WIRE AND DIELECTRIC WITH AIR GAPS

Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers. 1. A method of manufacturing a wire in an integrated circuit , comprising:forming a wire opening in a mask;electroplating a conductive material in the wire opening;forming a cap layer on the conductive material in the wire opening and such that an uppermost surface of the cap layer is at a vertical height lower than an uppermost surface of the mask;removing the mask after the forming the cap layer;forming sidewall spacers on sides of the conductive material by: forming a spacer layer on the cap layer, on sides of the conductive material, and on horizontal upper surfaces of a seed layer; and removing portions of the spacer layer from the cap layer and from the seed layer while leaving other portions of the spacer layer on the sides of the conductive material; andforming a dielectric film on surfaces of the cap layer and the sidewall spacers.2. The method of claim 1 , further comprising:forming a barrier layer;forming the seed layer on the barrier layer; andforming the mask on the seed layer.3. The method of claim 2 , wherein the barrier layer is formed on an upper surface of a dielectric layer and on surfaces of a via opening in the dielectric layer.4. The method of claim 3 , further comprising removing exposed portions of the seed layer and exposed portions of the barrier layer after the forming the sidewall spacers.5. The method of claim 4 , further comprising oxidizing the exposed portions ...

Copper wire and dielectric with air gaps

Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

INTEGRATED CIRCUIT AND INTERCONNECT, AND METHOD OF FABRICATING SAME

The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect. 1. A method of fabricating an interconnect in an integrated circuit , the method comprising:conformally coating a trench with a liner and seed layer, the trench being within a dielectric layer disposed on a substrate;depositing a hard mask on the liner and seed layer;masking and patterning the trench to expose the hard mask;removing exposed areas of the hard mask to expose areas of the liner and seed layer;electrolytic metal plating the exposed areas of the liner and seed layer to form an interconnect; andplanarizing the interconnect with a top surface of the trench.2. The method of fabricating an interconnect according to claim 1 , wherein the hard mask comprises a material selected from one of titanium nitride (TiN) claim 1 , tungsten (W) claim 1 , tantalum (Ta) claim 1 , tantalum nitride (TaN) claim 1 , silicon nitride (SiN) claim 1 , silicon carbide (SiC) and aluminum oxide (AlO).3. The method of fabricating an interconnect according to claim 1 , wherein the interconnect comprises a material selected from one of copper claim 1 , silver claim 1 , and gold.4. The method of fabricating an interconnect according to claim 1 , wherein the interconnect is approximately 5 microns (μm) to approximately 150 μm wide.5. The method of fabricating an interconnect according to claim 1 , wherein the planarizing step includes chemical-mechanical polishing the interconnect.6. The method of fabricating an interconnect according to claim 1 , wherein the removing step includes plasma etching one or more times the exposed areas of the liner and seed layer.7. The ...

SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path. 1. A method , comprising:forming a silicide layer on a substrate;forming a low resistance conduction path in a dicing channel in an interlevel dielectric layer above the silicide layer;forming an active device on the substrate and in contact with the silicide layer;forming a second interlevel dielectric layer over the interlevel dielectric layer;patterning the second interlevel dielectric layer to form a first opening exposing the low resistance conduction path and a second opening above the active device;forming a barrier layer on sidewalls and bottoms of the first and second openings and in contact with the low resistance conduction path; andforming a seed layer in contact with the barrier layer, wherein:the low resistance conduction path comprises a plurality of vias, andthe barrier layer is formed over the plurality of vias.2. The method of claim 1 , wherein the low resistance conduction path is provided into the interlevel dielectric material and the silicide layer.3. The method of claim 1 , wherein the silicide layer is formed at a junction between the interlevel dielectric material and the underlying substrate.4. The method of claim 1 , wherein the forming the low resistance conduction path comprises etching the plurality of vias into the interlevel dielectric layer to the silicide layer and filling the plurality of vias with metal material to form metal contacts in direct contact with the silicide layer.5. The method of claim 1 , wherein the silicide layer is formed by reaction of a thin metal film with silicon through an annealing process.6. The method of claim 1 , wherein the low resistance conduction path is part of a crackstop guard ring.7. A method claim 1 , comprising: ...

MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) STRUCTURES AND DESIGN STRUCTURES

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam. 1. A method comprising: forming a sacrificial material, which is comprised of both tungsten material and semiconductor material, on a substrate;', 'forming the MEMS beam structure above the tungsten material and the semiconductor material;', 'forming both the tungsten material and the semiconductor material above the MEMS beam structure;', 'forming a lid over the tungsten material formed above the MEMS beam structure;', 'etching the semiconductor material formed above the MEMS beam structure while etching the tungsten material formed above the MEMS beam structure to form an upper cavity structure above the MEMS beam structure and below the lid; and', 'etching both the tungsten material and the semiconductor material below the MEMS beam structure to form a lower cavity structure above the substrate and below the MEMS beam structure,, 'forming a Micro-Electro-Mechanical System (MEMS) beam structure comprising{'sub': '2', 'wherein the etching comprises performing an XeFetching process.'}2. The method of claim 1 , wherein the etching and film thicknesses are controlled to ensure that all or substantially all of the tungsten material is removed above the MEMS beam structure claim 1 , prior to the semiconductor material above the MEMS beam structure.3. The method of claim 1 , wherein the semiconductor material is one of silicon material and germanium material.4. The method of claim 3 , wherein the semiconductor material is silicon material claim 3 , and wherein the tungsten material and silicon material below the MEMS beam structure comprises forming the tungsten material on the substrate and forming the ...

Semiconductor structures with metal lines

Disclosed are semiconductor structures with metal lines and methods of manufacture which reduce or eliminate extrusion formation. The method includes forming a metal wiring comprising a layered structure of metal materials with an upper constraining layer. The method further includes forming a film on the metal wiring which prevents metal extrusion during an annealing process.

MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) STRUCTURES AND DESIGN STRUCTURES

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both metal material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam. 1. A method of forming a Micro-Electro-Mechanical System (MEMS) beam structure comprising:forming metal material and semiconductor material on a substrate;forming a MEMS beam above the metal material and the semiconductor material;forming the metal material and the semiconductor material above the MEMS beam;forming a lid over the metal material and the semiconductor material formed above the MEMS beam; and{'sub': '2', 'venting, using an XeFetchant, both the metal material and the semiconductor material above the MEMS beam and below the MEMS beam to form an upper cavity structure above the MEMS beam and below the lid and to form a lower cavity structure below the MEMS beam and above the substrate.'}2. The method of claim 1 , wherein the venting and film thicknesses are controlled to ensure that all or substantially all of the metal material is removed above the MEMS beam claim 1 , prior to the removal of the semiconductor material above the MEMS beam.3. The method of claim 1 , wherein the semiconductor material above and below the MEMS beam is one of silicon material and germanium material.4. The method of claim 3 , wherein the semiconductor material above and below the MEMS beam is silicon material claim 3 , and wherein forming the metal material and silicon material below the MEMS beam comprises forming the metal material on a substrate and forming the silicon material over the metal material.5. The method of claim 4 , wherein forming the metal material and silicon material above the MEMS beam comprises forming the silicon material within a via in contact with the silicon material below the MEMS beam ...

MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) STRUCTURES AND DESIGN STRUCTURES

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam. 1. A method of forming a Micro-Electro-Mechanical System (MEMS) beam structure comprising:forming both tungsten material and semiconductor material above and below a MEMS beam; and{'sub': '2', 'etching both the tungsten material and the semiconductor material at least above and below the MEMS beam, using an XeFetchant.'}2. The method of claim 1 , wherein the etching is preformed by venting both the tungsten material and the semiconductor material at least above and below the MEMS beam to form an upper cavity structure above the MEMS beam and a lower cavity structure below the MEMS beam.3. The method of claim 2 , wherein the MEMS beam comprises a cantilevered beam structure.4. The method of claim 3 , wherein the cantilevered beam structure comprises a first cantilevered beam and a second cantilevered beam separated from one another by a via which connects the upper cavity structure and the lower cavity structure to one another.5. The method of claim 2 , wherein the venting and film thicknesses are controlled to ensure that all or substantially all of the tungsten material is removed claim 2 , prior to the semiconductor material.6. The method of claim 5 , wherein the venting comprises forming a vent hole to expose at least the semiconductor material above the MEMS beam and performing an XeFetching process.7. The method of claim 1 , wherein the semiconductor material is silicon material.8. The method of claim 7 , wherein forming the tungsten material and silicon material below the MEMS beam comprises forming the tungsten material on a substrate and forming the silicon material over the tungsten ...

MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) STRUCTURES AND DESIGN STRUCTURES

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam. 1. A method comprising forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and semiconductor material at least above and below the MEMS beam to form an upper cavity structure above the MEMS beam and a lower cavity structure below the MEMS beam.2. The method of claim 1 , wherein the venting and film thicknesses are controlled to ensure that all or substantially all of the tungsten material is removed claim 1 , prior to the semiconductor material.3. The method of claim 1 , wherein the semiconductor material is one of silicon material and germanium material.4. The method of claim 3 , wherein the tungsten material and silicon material below the MEMS beam comprises forming the tungsten material on a substrate and forming the silicon material over the tungsten material.5. The method of claim 4 , wherein the tungsten material and silicon material above the MEMS beam comprises forming the silicon material within a via in contact with the silicon material below the MEMS beam and forming the tungsten material over the silicon material.6. The method of claim 5 , wherein the venting comprising forming a vent hole to expose at least the silicon material above the MEMS beam and performing an XeFetching process.7. The method of claim 6 , wherein the tungsten material at least one of above and below the MEMS beam is formed by a physical vapor deposition process followed by a chemical vapor deposition process.8. The method of claim 6 , further comprising forming an additional silicon material on the tungsten material above the MEMS beam.9. The method of claim 8 , further ...

SLURRY FOR CHEMICAL-MECHANICAL POLISHING OF METALS AND USE THEREOF

A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad. 1. A composition , comprising:a minimum of about 32% by weight of a surfactant anion;between about 0.8% by weight and about 1.2% by weight of an alkyl alcohol; anda diluent.2. The composition of claim 1 , wherein said alkyl alcohol has between about 6 and 14 carbon atoms.3. The composition of claim 1 , wherein said alkyl alcohol has the formula C(H)OH and n has a value between 6 and 14.4. The composition of claim 1 , wherein said surfactant anion is octyl sulfate and said alkyl alcohol is octanol.5. The composition of claim 1 , further comprising:a maximum of about 1.0% by weight of a sulfate ion source; anda maximum of about 0.1% by weight of a chloride ion source.6. The composition of claim 1 , further comprising:between about 0.001 gm/liter and about 5 gm/liter of a chloride ion source; and between about 0.001 gm/liter and about 20 gm/liter of a sulfate ion source.7. The composition of claim 1 , wherein the viscosity of the composition is no greater than about 150 centipoise at 25° C. and a 10% by weight solution of the composition in water has a pH of between about 7 and about 9.8. A composition claim 1 , consisting essentially of:a minimum of about 32% by weight of a surfactant anion;between about 0.8% by weight and about 1.2% by weight of an alkyl alcohol; anda diluent.9. The composition of claim 8 , wherein said alkyl alcohol has the formula C(H)OH and n has a value between 6 and 14.10. The composition of claim 8 , wherein said surfactant anion is octyl sulfate and said alkyl alcohol is octanol.11. The composition of claim 8 , wherein the viscosity of the composition is no greater than about 150 centipoise at ...

SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path. 1. A structure , comprising:low resistance conduction paths comprising a plurality of metal vias located in a dielectric material, extending to an underlying substrate of a wafer, and within dicing channels of the wafer;an upper dielectric material on the dielectric material, the upper dielectric material having an opening patterned therein directly above the plurality of metal vias;an electroplated seed layer in direct contact with the barrier layer;a barrier layer in direct contact with the low resistance conductive path; anda silicide layer at a junction between the dielectric material and the underlying substrate which is in direct contact with the plurality of metal vias.2. The structure of claim 1 , wherein the plurality of metal vias are lined with an oxide material layer claim 1 , an adhesion layer and a copper layer.3. The structure of claim 2 , wherein the adhesion layer is one of Tantalum (Ta) or Titanium (Ti).4. The structure of claim 1 , further comprising an active device in the dielectric material and positioned on the silicide layer.5. The structure of claim 4 , wherein the upper dielectric material includes another opening patterned therein directly above the active device.6. A structure claim 4 , comprising:at least one low resistance conduction path in an interlevel dielectric material, extending to an underlying substrate of a wafer, and within dicing channels of the wafer;an upper dielectric material on the interlevel dielectric material, the upper dielectric material including an opening patterned therein directly above the at least one low resistance conduction path;a barrier layer in direct contact with the low resistance conductive path;an electroplated seed ...

Semiconductor structures having low resistance paths throughout a wafer

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path. 1. A method , comprising:forming a silicide layer on an underlying substrate;forming an interlevel dielectric material on the silicide layer;forming one or more metal wiring and interconnects in the interlevel dielectric material;forming a seed layer and barrier layer on the interlevel dielectric material, contacting the underlying metal wiring and interconnects; andforming a metal wiring in contact with the seed layer.2. The method of claim 1 , wherein the seed layer is formed in direct contact with conductive material of the metal wiring and interconnects.3. The method of claim 2 , wherein the seed layer has a thickness of about 500 Å to about 1 micron.4. The method of claim 1 , wherein the metal wiring is formed by depositing and patterning a resist on the interlevel dielectric material and over the seed layer and barrier layer claim 1 , patterning the resist to form openings and depositing metal material in the openings.5. The method of claim 4 , wherein the depositing metal material in the openings is an electroplating.6. The method of claim 5 , wherein after formation of the metal wiring claim 5 , the resist is removed. The invention relates to semiconductor structures and, more particularly, to a semiconductor structure with low resistance conduction paths and methods of manufacture.Metal electro-plating is widely used for multi metal level electronic device fabrication. Electro-plating requires a low resistance conduction path between the electrodes providing the current and the entire surface of the device being plated. Resistance between the electrode contact point and any portion of the device can result in significant differences in the thickness of the plated metal ...

Semiconductor structures having low resistance paths throughout a wafer

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path. 1. A structure , comprising:at least one low resistance conduction path in a dielectric material, extending to an underlying substrate; andan electroplated seed layer in direct contact with the low resistance conduction path, provided on a surface of the dielectric material.2. The structure of claim 1 , wherein:the at least one low resistance conduction path is a metal filled via provided into the underlying substrate and within a dicing channel of a wafer; andthe metal filled via is lined with insulator material and filled with metal material; andthe electroplated seed layer is provided in a patterned opening of the dielectric material, in direct contact with the metal material of the metal filled via.3. The structure of claim 1 , wherein the at least one low resistance conduction path comprises a plurality of metal vias in the dielectric material and a silicide layer at a junction between the dielectric material and the underlying substrate which is in direct contact with the plurality of metal vias.4. The structure of claim 2 , wherein the low resistance conduction path is provided into an interlevel dielectric material and an underlying substrate.5. The structure of claim 4 , wherein the low resistance conduction path comprises at least one via in the interlevel dielectric material and the underlying substrate claim 4 , lined with an insulator material and filled with a metal material over the insulator material.6. The structure of claim 5 , wherein the at least one via is formed within a dicing channel of a wafer.7. The structure of claim 6 , wherein the at least one via is about 10 micron tall claim 6 , with a resultant resistance of about 2 mΩ/□ claim 6 , and a seed layer is a ...

MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) STRUCTURES AND DESIGN STRUCTURES

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam. 1. A structure , comprising a cavity and a cantilevered beam formed within the cavity , the cantilevered beam including a recess , wherein the cavity and the recess are formed by removal of tungsten material and silicon material through a venting process.2. The structure of claim 1 , wherein the cantilevered beam comprises a first cantilevered Micro-Electro-Mechanical System (MEMS) beam structure formed within the cavity claim 1 , wherein the first cantilevered MEMS beam structure separates the cavity into an upper cavity portion and a lower cavity portion.3. The structure of claim 2 , wherein the recess is formed in an upper surface of the first cantilevered MEMS beam structure facing toward the upper cavity portion.4. The structure of claim 3 , wherein the upper cavity portion is formed over an entire upper surface of the first cantilevered MEMS beam structure and over the recess.5. The structure of claim 4 , further comprising a lid formed over the upper cavity portion.6. The structure of claim 5 , wherein the lid includes a vent hole configured to permit the venting process.7. The structure of claim 6 , further comprising a plug formed in the vent hole.8. The structure of claim 7 , wherein the plug is comprised of a dielectric material or a metal material.9. The structure of claim 6 , wherein the vent hole has a diameter of about 1 μm.10. The structure of claim 9 , wherein the lid has a thickness of about 3 μm.11. The structure of claim 10 , further comprising a second vent hole separated from the vent hole by at least 6 μm. The invention relates to semiconductor structures and methods of ...

SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path. 1. A method , comprising:forming a silicide layer on a substrate;forming an interlevel dielectric material over the silicide layer;forming one or more metal wiring and interconnects in the interlevel dielectric material; andforming a plurality of devices in direct contact with the silicide layer,wherein the silicide layer extends between the devices such that sides of the devices are in direct contact with the silicide layer and the interlevel dielectric material, and a center of the devices is below the one or more metal wiring and interconnects such that the devices are electrically isolated from the one or more metal wiring and interconnects.2. The method of claim 1 , further comprising forming a seed and barrier layer on a upper surface of the interlevel dielectric material.3. The method of claim 2 , wherein the seed and barrier layer contact a surface of the one or more metal wiring and interconnects.4. The method of claim 3 , wherein the seed and barrier layer contacts a conductive material of the metal wiring and interconnects.5. The method of claim 4 , further comprising:removing exposed portions of the seed layer and barrier layer by a wet etch process to expose the one or more metal wiring and interconnects; andforming a metal wiring over the exposed one or more metal wiring and interconnects.6. The method of claim 5 , wherein the metal wiring is formed by depositing and patterning a resist on the interlevel dielectric material and over the seed layer and barrier layer claim 5 , patterning the resist to form openings and depositing metal material in the openings.7. The method of claim 6 , wherein the depositing metal material in the openings is an electroplating process.8. ...

Chemical mechanical polishing slurry and method for polishing metal/oxide layers

A ferric nitrate-alumina based slurry useful for Chemical-Mechanical-Polishing of tungsten metallurgy and silica based oxides on semiconductor substrates in which the suspension and stability of abrasive material in the slurry is essentially stable. The slurry formulation is balanced to provide low residue of foreign material after polishing and due to its reduced ferric nitrate concentration will be less corrosive than prior art slurries. The recipe for the slurry includes of a 30% wt silica suspension, about 800 ml of 40% by wt ferric nonahydrate and enough 70% wt nitric acid to adjust the pH of the slurry to about 1.2 to 1.4.

Cmp method

The instant invention is a method of polishing a substrate including contacting a substrate having at least one metal layer including copper with a chemical-mechanical polishing composition. The CMP composition includes an abrasive, a surfactant, an oxidizer, an organic acid including polyacrylic acid or polymethacrylic acid, a corrosion inhibitor, and a liquid carrier. A portion of the copper in the metal layer is abraded to polish the substrate. A second CMP composition contacts the abraded substrate, the second acrylate free composition including an abrasive, a surfactant, an oxidizer, and a corrosion inhibitor, and a liquid carrier. Any dendrites that may have formed on the substrate are removed through abrasion.

Slurry for a chemical-mechanical polishing of metals and use thereof

Slurry-Zusammensetzung, wobei die Slurry-Zusammensetzung wässrig ist, die aufweist: zwischen 0,5 Gewichtsprozent und 6 Gewichtsprozent an Schleifmittelpartikeln; zwischen 1 g/Liter und 50 g/Liter eines Oxidationsmittels, wobei das Oxidationsmittel Eisennitrat ist; zwischen 0,1 ml/Liter und 100 ml/Liter eines Tensid-Anions, wobei das Tensid-Anion Octylsulfat ist; zwischen 0,1 g/Liter und 5 g/Liter eines Kupfer-Korrosions-Inhibitors; zwischen 0,003 ml/Liter und 3,05 ml/Liter eines Alkylalkohols, wobei der Alkylalkohol Octanol ist; sowie ein Verdünnungsmittel, wobei das Verdünnungsmittel Wasser ist. A slurry composition wherein the slurry composition is aqueous comprising: between 0.5% and 6% by weight of abrasive particles; between 1 g / liter and 50 g / liter of an oxidizing agent, wherein the oxidizing agent is iron nitrate; between 0.1 ml / liter and 100 ml / liter of a surfactant anion, wherein the surfactant anion is octylsulfate; between 0.1 g / liter and 5 g / liter of a copper corrosion inhibitor; between 0.003 ml / liter and 3.05 ml / liter of an alkyl alcohol, wherein the alkyl alcohol is octanol; and a diluent wherein the diluent is water.

CMP method

The instant invention is a method of polishing a substrate including contacting a substrate having at least one metal layer including copper with a chemical-mechanical polishing composition. The CMP composition includes an abrasive, a surfactant, an oxidizer, an organic acid including polyacrylic acid or polymethacrylic acid, a corrosion inhibitor, and a liquid carrier. A portion of the copper in the metal layer is abraded to polish the substrate. A second CMP composition contacts the abraded substrate, the second acrylate free composition including an abrasive, a surfactant, an oxidizer, and a corrosion inhibitor, and a liquid carrier. Any dendrites that may have formed on the substrate are removed through abrasion.

Solution for forming polishing slurry, polishing slurry and related methods

A solution for forming a polishing slurry, the polishing slurry and related methods are disclosed. The solution for forming a polishing slurry may include 1 H-benzotriazole (BTA) dissolved in an ionic surfactant such as a sodium alkyl sulfate solution, and perhaps a polyacrylic acid (PAA) solution. The solution can be filtered and used in a polishing slurry. This approach to solubilizing BTA results in a high BTA concentration in a polishing slurry without addition of foreign components to the slurry or increased safety hazard. In addition, the solution is easier to ship because it is very stable (e.g., can be frozen and thawed) and has less volume compared to conventional approaches. Further, the polishing slurry performance is vastly improved due to the removal of particles that can cause scratching.

Solution for forming polishing slurry, polishing slurry and related methods

A solution for forming a polishing slurry, the polishing slurry and related methods are disclosed. The solution for forming a polishing slurry may include 1H-benzotriazole (BTA) dissolved in an ionic surfactant such as a sodium alkyl sulfate solution, and perhaps a polyacrylic acid (PAA) solution. The solution can be filtered and used in a polishing slurry. This approach to solubilizing BTA results in a high BTA concentration in a polishing slurry without addition of foreign components to the slurry or increased safety hazard. In addition, the solution is easier to ship because it is very stable (e.g., can be frozen and thawed) and has less volume compared to conventional approaches. Further, the polishing slurry performance is vastly improved due to the removal of particles that can cause scratching.

Solution for forming polishing slurry, polishing slurry and related methods

A solution for forming a polishing slurry, the polishing slurry and related methods are disclosed. The solution for forming a polishing slurry may include 1H-benzotriazole (BTA) dissolved in an ionic surfactant such as a sodium alkyl sulfate solution, and perhaps a polyacrylic acid (PAA) solution. The solution can be filtered and used in a polishing slurry. This approach to solubilizing BTA results in a high BTA concentration in a polishing slurry without addition of foreign components to the slurry or increased safety hazard. In addition, the solution is easier to ship because it is very stable (e.g., can be frozen and thawed) and has less volume compared to conventional approaches. Further, the polishing slurry performance is vastly improved due to the removal of particles that can cause scratching.

Solution for forming polishing slurry, polishing slurry and related methods

A solution for forming a polishing slurry, the polishing slurry and related methods are disclosed. The solution for forming a polishing slurry may include 1H-benzotriazole (BTA) dissolved in an ionic surfactant such as a sodium alkyl sulfate solution, and perhaps a polyacrylic acid (PAA) solution. The solution can be filtered and used in a polishing slurry. This approach to solubilizing BTA results in a high BTA concentration in a polishing slurry without addition of foreign components to the slurry or increased safety hazard. In addition, the solution is easier to ship because it is very stable (e.g., can be frozen and thawed) and has less volume compared to conventional approaches. Further, the polishing slurry performance is vastly improved due to the removal of particles that can cause scratching.

Solution for forming polishing slurry, polishing slurry and related methods

A solution for forming a polishing slurry, the polishing slurry and related methods are disclosed. The solution for forming a polishing slurry may include 1 H-benzotriazole (BTA) dissolved in an ionic surfactant such as a sodium alkyl sulfate solution, and perhaps a polyacrylic acid (PAA) solution. The solution can be filtered and used in a polishing slurry. This approach to solubilizing BTA results in a high BTA concentration in a polishing slurry without addition of foreign components to the slurry or increased safety hazard. In addition, the solution is easier to ship because it is very stable (e.g., can be frozen and thawed) and has less volume compared to conventional approaches. Further, the polishing slurry performance is vastly improved due to the removal of particles that can cause scratching.

Chemical mechantical polishing slurry and method for polishing metal/oxide layers

Chemical-mechanical-polishing slurry and method for polishing metal/oxide layers

A ferric nitrate-alumina based slurry useful for Chemical-Mechanical-Polishing of tungsten metallurgy and silica based oxides on semiconductor substrates in which the suspension and stability of abrasive material in the slurry is essentially stable. The slurry formulation is balanced to provide low residue of foreign material after polishing and due to its reduced ferric nitrate concentration will be less corrosive than prior art slurries. The recipe for the slurry includes of a 30% wt silica suspension, about 800 ml of 40% by wt ferric nonahydrate, liters and enough 70% wt nitric acid to adjust the pH of the slurry to about 1.2 to 1.4.

Slurry for chemical-mechanical polishing of copper and use thereof

A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol, a controlled amount of chloride ion source and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad.

Slurry for chemical-mechanical polishing of metals and use thereof

A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad.

Planar cavity MEMS and related structures, methods of manufacture and design structures

A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a wiring layer and substrate. The method further includes forming an insulator layer over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity of the MEMS.

Planar cavity mems and related structures, methods of manufacture and design structures

A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity (60b) includes forming a first sacrificial cavity layer (18) over a wiring layer (14) and substrate (10). The method further includes forming an insulator layer (40) over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity (60b) of the MEMS.

Planar cavity mems and related structures, methods of manufacture and design structures

Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity (60a, 60b) having a planar surface using a reverse damascene process.

Method of electrolytic plating and semiconductor device fabrication

The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.

Reduction of foreign particulate matter on semiconductor wafers

A substantial reduction in the foreign particulate matter contamination on surfaces, such as the surfaces of semiconductor wafers, is achieved by treating the surfaces with a solution comprising a strong acid and a very small amount of a fluorine-containing compound. A preferred method employs a solution containing sulfuric acid, hydrogen peroxide and a very small amount of hydrofluoric acid, which is effective in reducing foreign particulate matter contamination, without significant etching, of the surface being treated.

Process for producing crackstops on semiconductor devices and devices containing the crackstops

A process for making a crackstop on a semiconductor device is disclosed. The process involves creating and metallizing a groove surrounding the active region on a chip at the same time as other functional metallization is occurring, and then selectively etching out the metal in the groove after final passivation. In various embodiments the groove passes through the surface dielectric or the semiconductor substrate. In one embodiment the groove is replaced by hollow metal rings that can be stacked through multiple dielectric layers.

Slurryless Mechanical Planarization for Substrate Reclamation

A patterned portion of a patterned semiconductor substrate is removed by abrasive mechanical planarization employing an abrasive pad but without employing any slurry. Preferably, water is supplied to enhance the removal rate during the mechanical planarization. The removal rate of material is substantially independent for common materials employed in back-end-of-line (BEOL) semiconductor materials, which enables non-selective removal of the material containing metallization structures. The removal rate of silicon is lower than the removal rate for the BEOL semiconductor materials, enabling a self-stopping planarization process.

Microcavity structures, fabrication processes, and applications thereof

A method is presented for controlled formation of microcavities for various semiconductor and micro-machine applications. The method involves the steps of defining a void in a support structure, sealing the void with a resilient gas-permeable material such that a chamber is formed, diffusing gas into the chamber through the gas permeable material to create a pressurized chamber, and then allowing expansion of the pressurized chamber within the resilient material, thereby creating an enlarged cavity. The applications set forth include the production of large capacitors, field isolation structures, tubular sensors for chromatography, pressure sensors, and cooling channels for integrated circuits.

Integrated beol thin film resistor

In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

Semiconductor structures having low resistance paths throughout a wafer

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

Micro-electro-mechanical system (MEMS) structures and design structures

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

Micro-electro-mechanical system (MEMS) structures and design structures

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

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Integrated circuit and interconnect, and method of fabricating same

Integrated circuit and interconnect, and method of fabricating same

The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC (10) includes at least one trench (20) within a dielectric layer (25) disposed on a substrate (30). The trench is conformally coated with a liner and seed layer (35), and includes an interconnect (40) within. The interconnect includes a hard mask (45) on the sidewalls of the interconnect.

Integrated circuit and interconnect, and method of fabricating same

The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC (10) includes at least one trench (20) within a dielectric layer (25) disposed on a substrate (30). The trench is conformally coated with a liner and seed layer (35), and includes an interconnect (40) within. The interconnect includes a hard mask (45) on the sidewalls of the interconnect.

Methods for selective reverse mask planarization and interconnect structures formed thereby

Micro-Electro-Mechanical System (MEMS) structures and design structures

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

Method for forming micro-electro-mechanical system (MEMS) beam structure

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.