MAGNETIC TUNNELING JUNCTION DEVICES, MEMORIES, ELECTRONIC SYSTEMS, AND MEMORY SYSTEMS, AND METHODS OF FABRICATING THE SAME

Provided is a magnetic tunneling junction device including a fixed magnetic structure; a free magnetic structure; and a tunnel barrier between the fixed magnetic structure and the free magnetic structure, at least one of the fixed magnetic structure and the free magnetic structure including a perpendicular magnetization preserving layer, a magnetic layer between the perpendicular magnetization preserving layer and the tunnel barrier, and a perpendicular magnetization inducing layer between the perpendicular magnetization preserving layer and the magnetic layer. 1. A magnetic tunneling junction device comprising:a fixed magnetic structure;a free magnetic structure; anda tunnel barrier between the fixed magnetic structure and the free magnetic structure, a perpendicular magnetization preserving layer,', 'a magnetic layer between the perpendicular magnetization preserving layer and the tunnel barrier, and', 'a perpendicular magnetization inducing layer between the perpendicular magnetization preserving layer and the magnetic layer., 'at least one of the fixed magnetic structure and the free magnetic structure including'}2. The magnetic tunneling junction device of claim 1 , wherein the magnetic layer is made of a ferromagnetic material.3. The magnetic tunneling junction device of claim 2 , wherein the ferromagnetic material is at least one of CoFeB claim 2 , CoFe claim 2 , NiFe claim 2 , CoFePt claim 2 , CoFePd claim 2 , CoFeCr claim 2 , CoFeTb claim 2 , CoFeGd or CoFeNi.4. The magnetic tunneling junction device of claim 1 , wherein the magnetic layer has a thickness in a range of about 1 angstrom to about 30 angstroms.5. The magnetic tunneling junction device of claim 4 , wherein the magnetic layer has a thickness in a range of about 3 angstroms to about 17 angstroms.6. The magnetic tunneling junction device of claim 1 , wherein the perpendicular magnetization inducing layer is in direct contact with the magnetic layer.7. The magnetic tunneling junction device of ...

MAGNETIC TUNNELING JUNCTION DEVICES, MEMORIES, MEMORY SYSTEMS, AND ELECTRONIC DEVICES

Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures. 1. A magnetic tunneling junction device comprising:a first structure including a magnetic layer;a second structure includingat least two extrinsic perpendicular magnetization structures, each includinga magnetic layer and;a perpendicular magnetization inducing layer on the magnetic layer; anda tunnel barrier between the first and second structures.2. The magnetic tunneling junction of claim 1 , the second structure further includingadditional extrinsic perpendicular magnetization structures, each includinga magnetic layer and;a perpendicular magnetization inducing layer on the magnetic layer.3. The magnetic tunneling junction of claim 1 , further comprising:a perpendicular magnetization preserving layer on one of the perpendicular magnetization inducing layers.4. The magnetic tunneling junction device of claim 3 , wherein each magnetic layer has an oxygen affinity less than each perpendicular magnetization inducing layer.5. The magnetic tunneling junction device of claim 3 , wherein each perpendicular magnetization preserving layer has an oxygen affinity less than each perpendicular magnetization inducing layer.6. The magnetic tunneling junction device of claim 3 , wherein the magnetic layers are made of a ferromagnetic material.7. The magnetic tunneling junction device of claim 6 , wherein the ferromagnetic material is at least one of CoFeB claim 6 , CoFe claim 6 , NiFe claim 6 , CoFePt claim 6 , CoFePd claim 6 , CoFeCr claim 6 , CoFeTb claim 6 , CoFeGd or CoFeNi.8. The magnetic tunneling junction device of claim 3 , wherein the magnetic layers have a thickness in a range of about 1 angstrom to about 30 ...

METHOD AND SYSTEM FOR SETTING A PINNED LAYER IN A MAGNETIC TUNNELING JUNCTION

A method and system for setting the direction of pinned layers in a magnetic junction are described. In one aspect, a magnetic field greater than the coercivity of the layers in a pinned layer but less than the coupling field between the layers is applied. In another aspect the pinned layers are switched from an anti-dual state to a dual state using a spin transfer torque current. In another aspect, a magnetic junction having a partial perpendicular anisotropy (PPMA) layer in the pinned layer is provided. In some aspects, the PPMA layer is part of a synthetic antiferromagnetic structure. In some embodiments, a decoupling layer is provided between the PPMA layer and another ferromagnetic layer in the pinned layer. 1. A method for setting a reference layer of a pinned layer in magnetic junction including a free layer , a nonmagnetic spacer layer , and the pinned layer , the nonmagnetic spacer layer residing between the pinned layer and the free layer , the pinned layer including a plurality of ferromagnetic layers interleaved with at least one spacer layer , the plurality of ferromagnetic layers having at least one easy axis , the method comprising:applying a magnetic field in a direction parallel to an easy axis of the at least one easy axis, the magnetic field having a magnitude greater than a coercivity of each of the plurality of layers and less than a coupling field between a portion of the plurality of layers.2. The method of wherein a ferromagnetic layer of the plurality of ferromagnetic layers has a saturation magnetic moment greater than any saturation magnetic moment of any remaining layer of the plurality of ferromagnetic layers and wherein the direction is parallel to the easy axis for the ferromagnetic layer.3. The method of wherein the ferromagnetic layer is a ferromagnetic pinned layer.4. The method of wherein the ferromagnetic layer is a reference layer.5. The method of wherein the magnetic junction includes an additional nonmagnetic spacer layer and ...

MAGNETIC DEVICE AND METHOD OF MANUFACTURING THE SAME

A magnetic device and a method of manufacturing the same. In the method, a lower magnetic layer, an insulation layer, and an upper magnetic layer are sequentially formed on a substrate. An upper magnetic layer pattern is formed by patterning the upper magnetic layer until an upper surface of the insulation layer is exposed. An isolation layer pattern is formed from portions of the insulation layer and the lower magnetic layer by performing an oxidation process on the exposed upper surface of the insulation layer, and an insulation layer pattern and a lower magnetic layer pattern are formed from portions of the insulation layer and the lower magnetic layer, where the isolation layer pattern is not formed. 1. A method of manufacturing a magnetic device , the method comprising:sequentially forming a lower magnetic layer, an insulation layer, and an upper magnetic layer on a substrate;forming an upper magnetic layer pattern by patterning the upper magnetic layer until an upper surface of the insulation layer is exposed; andperforming an oxidation process on the exposed upper surface of the insulation layer to form an isolation layer pattern from portions of the insulation layer and the lower magnetic layer and to form an insulation layer pattern and a lower magnetic layer pattern from portions of the insulation layer and the lower magnetic layer, where the isolation layer pattern is not formed.2. The method of claim 1 , wherein the performing the oxidation process is performed by a directional plasma oxidation process.3. The method of claim 2 , wherein the performing the oxidation process is performed by applying a biased voltage to the substrate.4. The method of claim 1 , wherein the forming of the upper magnetic layer pattern is performed by an ion etching process using low-mass species.5. The method of claim 4 , wherein the forming of the upper magnetic layer pattern is performed by an ion etching process using low-mass species of H claim 4 , He claim 4 , Ne claim 4 ...

NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME

A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen. 1. A nonvolatile memory device comprising:first and second electrodes on a substrate;a data storage layer between the first electrode and the second electrode, the data storage layer including a transition metal oxide layer comprising a transition metal oxide and a transition metal layer comprising a transition metal, wherein the transition metal oxide layer and the transition metal layer comprise the same transition metal; anda metal oxide layer between the transition metal layer and at least one of the first and second electrodes, the metal oxide layer being in direct contact with the transition metal layer and comprising a metal oxide,wherein a bond energy between a metal element and oxygen in the metal oxide layer is greater than a bond energy between a transition metal element and oxygen in the data storage layer, andwherein a conductive filament is formed in the transition metal layer which is not bonded to oxygen, when an external electric field is applied to the data storage layer.2. The nonvolatile memory device of claim 1 , wherein the metal oxide layer comprises aluminum (Al).3. The nonvolatile memory device of claim 2 , wherein the metal oxide layer is between the data storage layer and the first electrode claim 2 , and between the data storage layer and the second electrode.4. The nonvolatile memory device of claim 2 , wherein the metal oxide layer is between the data storage layer and the first electrode.5. The nonvolatile memory device of claim 2 , wherein the metal oxide layer is between the data ...

SEMICONDUCTOR DEVICE

A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring. 1. A semiconductor device comprising:a substrate including an element isolation layer, the element isolation layer defining an active region;a plurality of word lines traversing the active region in a first direction; anda plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction,{'claim-text': ['a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface,', 'a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and', 'a wiring line capping layer extending along the top surface of the ruthenium line wiring.'], '#text': 'wherein each of the plurality of bit line structures includes,'}2. The semiconductor device of claim 1 , further comprising:a first line wiring between the lower graphene layer and the substrate, the first line wiring extending along the lower graphene layer.3. The semiconductor device of claim 2 , wherein the first line wiring includes a doped ...

Magnetic tunneling junction devices, memories, electronic systems, and memory systems, and methods of fabricating the same

Provided is a magnetic tunneling junction device including a fixed magnetic structure; a free magnetic structure; and a tunnel barrier between the fixed magnetic structure and the free magnetic structure, at least one of the fixed magnetic structure and the free magnetic structure including a perpendicular magnetization preserving layer, a magnetic layer between the perpendicular magnetization preserving layer and the tunnel barrier, and a perpendicular magnetization inducing layer between the perpendicular magnetization preserving layer and the magnetic layer.

METHOD AND SYSTEM FOR PROVIDING A BULK PERPENDICULAR MAGNETIC ANISOTROPY FREE LAYER IN A PERPENDICULAR MAGNETIC JUNCTION USABLE IN SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY APPLICATIONS

A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a pinned layer and nonmagnetic spacer layer between the free and pinned layers. The free layer includes at least one of a hybrid perpendicular magnetic anisotropy (PMA) structure and tetragonal bulk perpendicular magnetic anisotropy (B-PMA) structure. At least one of the free layer and the pinned layer have a perpendicular magnetic anisotropy energy greater than an out-of-plane demagnetization energy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. 1. A magnetic junction residing on a substrate and usable in a magnetic device comprising:a free layer, the free layer including at least one of a hybrid perpendicular magnetic anisotropy (PMA) structure and tetragonal bulk perpendicular magnetic anisotropy (B-PMA) structure;a nonmagnetic spacer layer; anda pinned layer, the nonmagnetic spacer layer residing between the pinned layer and the free layer, at least one of the free layer and the pinned layer having a perpendicular magnetic anisotropy energy greater than an out-of-plane demagnetization energy;wherein the magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.2. The magnetic junction of wherein the free layer includes the hybrid PMA structure claim 1 , the hybrid PMA structure including a B-PMA layer claim 1 , an interfacial PMA (I-PMA) layer and a coupling layer between the B-PMA layer and the I-PMA layer.3. The magnetic junction of wherein the B-PMA layer includes at least one of FePd claim 2 , FePdB claim 2 , CoPt claim 2 , CoPd claim 2 , FePt claim 2 , TbCoFe claim 2 , GaMn claim 2 , at least one Co/Pd bilayer claim 2 , at least one Co/Pt bilayer ...

METHOD AND SYSTEM FOR PROVIDING A TOP PINNED LAYER PERPENDICULAR MAGNETIC ANISOTROPY MAGNETIC JUNCTION USABLE IN SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY APPLICATIONS

A method for providing a magnetic junction usable in a magnetic device and the magnetic junction are described. A free layer and nonmagnetic spacer layer are provided. The free layer and nonmagnetic spacer layer are annealed at an anneal temperature of at least three hundred fifty degrees Celsius. A pinned layer is provided after the annealing step. The nonmagnetic spacer layer is between the pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. 1. A method for providing a magnetic junction on a substrate usable in a magnetic device , the method comprising:providing a free layer;a nonmagnetic spacer layer;annealing the free layer and the nonmagnetic spacer layer at an anneal temperature of at least three hundred fifty degrees Celsius; andproviding a pinned layer after the annealing step, the nonmagnetic spacer layer residing between the pinned layer and the free layer, the free layer being between the substrate and the pinned layer;wherein the magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.2. The method of wherein at least one of the free layer and the pinned layer has a perpendicular magnetic anisotropy energy greater than an out-of-plane demagnetization energy.3. The method of further comprising:providing a polarization enhancement layer (PEL) between the pinned layer and the nonmagnetic spacer layer.4. The method of wherein the annealing step is performed after the step of providing the PEL.5. The method of wherein the annealing step is performed before the step of providing the PEL.6. The method of wherein the PEL includes at least one of CoFeB claim 3 , FeB claim 3 , a bilayer including a Fe layer and a CoFeB layer claim 3 , a half metallic material and a Heusler alloy.7. ...

Dual perpendicular magnetic anisotropy magnetic junction usable in spin transfer torque magnetic random access memory applications

A method for providing a dual magnetic junction usable in a magnetic device and the dual magnetic junction are described. First and second nonmagnetic spacer layers, a free layer and pinned are provided. The first pinned layer, free layer and nonmagnetic spacer layer may be annealed at an anneal temperature of at least three hundred fifty degrees Celsius before a second pinned layer is provided. The second pinned layer may include Co, Fe and Tb. The nonmagnetic spacer layers are between the pinned layers and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

MAGNETIC JUNCTIONS HAVING ELONGATED FREE LAYERS

A magnetic junction usable in a magnetic device is described. The magnetic junction has a free layer, a reference layer, and a nonmagnetic spacer layer between reference and free layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The free layer has a length in a first direction, a width in a second direction perpendicular to the first direction, an exchange stiffness and an aspect ratio equal to the length divided by the width. The aspect ratio is greater than one. The exchange stiffness is not less than 2×10erg/cm. 1. A magnetic junction residing on a substrate and usable in a magnetic device comprising:a reference layer;a nonmagnetic spacer layer; and{'sup': '−6', 'a free layer, the nonmagnetic spacer layer residing between reference layer and the free layer, the free layer having a length in a first direction, a width in a second direction, an aspect ratio and an exchange stiffness, the aspect ratio being the length divided by the width and being greater than one, the exchange stiffness being not less than 2×10erg/cm;'}wherein the magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.2. The magnetic junction of wherein the exchange stiffness is at least 3×10erg/cm.3. The magnetic junction of wherein the free layer has a thickness substantially perpendicular to the length and to the width claim 1 , the thickness being at least 1.5 nanometers and not more than two nanometers.4. The magnetic junction of wherein the free layer is substantially free of glass-forming agents.5. The magnetic junction of wherein the width is not more than twenty nanometers.6. The magnetic junction of wherein the width is not more than sixteen nanometers.7. The magnetic junction of wherein the free layer includes at least one of Fe claim 1 , Co claim 1 , SmCo claim 1 , MnGe claim 1 , CoFeSi ...

Magnetic tunneling junction devices, memories, memory systems, and electronic devices

Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures.

METHOD AND SYSTEM FOR PROVIDING MAGNETIC JUNCTIONS INCLUDING FREE LAYERS THAT ARE COBALT-FREE

A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a nonmagnetic spacer layer, and a reference layer. The free layer includes at least one of Fe and at least one Fe alloy. Furthermore, the free layer excludes Co. The nonmagnetic spacer layer adjoins the free layer. The nonmagnetic spacer layer residing between reference layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. 1. A magnetic junction residing on a substrate and usable in a magnetic device comprising:a free layer including at least one of Fe and at least one Fe alloy, the free layer excluding Co;a nonmagnetic spacer layer adjoining the free layer; anda reference layer, the nonmagnetic spacer layer residing between reference layer and the free layer;wherein the magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.2. The magnetic junction of wherein the free layer consists of at least one Fe layer and at least one Fe alloy layer.3. The magnetic junction of wherein the free layer includes at least one material selected from Fe metal and FeB.4. The magnetic junction of wherein the free layer includes an Fe layer and an FeBlayer.5. The magnetic junction of wherein the free layer further includes:{'sub': 1-x', 'x, 'an additional Fe layer, the FeBlayer being between the Fe layer and the additional Fe layer.'}6. The magnetic junction of wherein the free layer further includes an FeBlayer claim 4 , the FeBlayer being between the Fe layer and the FeBlayer.7. The magnetic junction of wherein x is greater than y.8. The magnetic junction of wherein the free layer further includes:{'sub': 1-x', 'x', '1-y', 'y, 'an additional Fe layer, the ...

METHOD AND SYSTEM FOR PROVIDING MAGNETIC JUNCTIONS USING THERMALLY ASSISTED SPIN TRANSFER TORQUE SWITCHING

A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a pinned layer and nonmagnetic spacer layer between the free and pinned layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The write current generates joule heating such that the free layer has a switching temperature greater than room temperature. The free layer includes a multilayer that is temperature sensitive and has at least one bilayer. Each bilayer includes first and second layers. The first layer includes an alloy of a magnetic transition metal and a rare earth. The second layer includes a magnetic layer. The multilayer has a room temperature coercivity and a switching temperature coercivity. The switching temperature coercivity is not more than one-half of the room temperature coercivity. 1. A magnetic junction residing on a substrate and usable in a magnetic device comprising:a free layer, the free layer being switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction, the write current generating joule heating in the free layer such that the free layer has a switching temperature greater than room temperature, the free layer having a free layer perpendicular magnetic anisotropy energy greater than a free layer out-of-plane demagnetization energy, the free layer including a multilayer, the multilayer being temperature sensitive and including at least one bilayer, each of the at least one bilayer including a first layer and a second layer, the first layer including an alloy of a magnetic transition metal and a rare earth, the second layer including a magnetic layer, the multilayer a room temperature coercivity and a switching temperature coercivity, the switching temperature coercivity being not more than one-half of the room temperature coercivity;a nonmagnetic ...

Method and system for providing a bottom pinned layer in a perpendicular magnetic junction usable in spin transfer torque magnetic random access memory applications

A magnetic junction and method for providing the magnetic junction are described. The magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The pinned layer has a perpendicular magnetic anisotropy (PMA) energy greater than its out-of-plane demagnetization energy. Providing the pinned layer includes providing a bulk PMA (B-PMA) layer, providing an interfacial PMA (I-PMA) layer on the B-PMA layer and then providing a sacrificial layer that is a sink for a constituent of the first I-PMA layer. An anneal is then performed. The sacrificial layer and part of the first I-PMA layer are removed after the anneal. Additional I-PMA layer(s) are provided after the removing. A remaining part of the first I-PMA layer and the additional I-PMA layer(s) have a thickness of not more than twenty Angstroms.

MAGNETIC TUNNELING JUNCTION DEVICES, MEMORIES, MEMORY SYSTEMS, AND ELECTRONIC DEVICES

Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures. 1. A magnetic tunneling junction device comprising:a first structure including a magnetic layer;a second structure includinga first extrinsic perpendicular magnetization layer;a second extrinsic perpendicular magnetization layer;a first non-magnetic layer disposed on the first extrinsic perpendicular magnetization layer;a second non-magnetic layer disposed on the second extrinsic perpendicular magnetization layer; anda third non-magnetic layer disposed on the second non-magnetic layer.2. The device of claim 1 , wherein the magnetic layer of the first structure comprises a ferromagnetic material.3. The device of claim 2 , wherein the ferromagnetic material is at least one of CeFeB claim 2 , CoFe claim 2 , NiFe claim 2 , CoFePt claim 2 , CoFePd claim 2 , CoFePd claim 2 , CoFeCr claim 2 , CoFeTb claim 2 , CoFeGd or CoFeNi.4. The device of claim 1 , wherein the first and second extrinsic perpendicular magnetization layer comprises CoFeB.5. The device of claim 1 , wherein at least one of the first and second non-magnetic layers comprise at least one of Ta claim 1 , Ti claim 1 , U claim 1 , Ba claim 1 , Zr claim 1 , Al claim 1 , Sr claim 1 , Hf claim 1 , La claim 1 , Ce claim 1 , Sm claim 1 , Mg claim 1 , Th claim 1 , Ca claim 1 , Sc claim 1 , or Y.6. The device of claim 1 , wherein the third non-magnetic layer comprises at least one of Ru claim 1 , Rh claim 1 , Pd claim 1 , Ag claim 1 , Os claim 1 , Ir claim 1 , Pt claim 1 , or Au.7. The device of claim 1 , wherein the oxygen affinity of the third non-magnetic layer is less than the oxygen affinity of the second non-magnetic layer.8. The device of claim 1 , ...

Magnetic random access memory devices having titanium-rich lower electrodes with oxide layer and oriented tunneling barrier

Magnetic Random Access Memory (MRAM) devices include a lower electrode and a magnetic tunnel junction on the lower electrode. The magnetic tunnel junction includes a seed layer and a tunneling barrier that is oriented in a same direction as the most closely packed plane direction of the seed layer. An oxide layer may be provided between the lower electrode and the magnetic tunnel junction. The lower electrode may be a titanium-rich TiN layer having more than 50 atomic percent titanium content. Analogous fabrication methods are also described.

Semiconductor memory device and method of fabricating the same

A semiconductor memory device with an improved electric characteristic and reliability is provided. The semiconductor memory device including a substrate including an active region defined by device separation film, the active region including a first part and second parts, the second parts being on two opposite sides of the first part, respectively a bit line extending on the substrate and across the active region, and a bit line contact between the substrate and the bit line and connected to the first part of the active region may be provided. The bit line contact includes a first ruthenium pattern, and a width of upper surface of the first ruthenium pattern is smaller than a width of bottom surface of the first ruthenium pattern.

Nonvolatile memory devices using variable resistors as storage elements and methods of operating the same

A nonvolatile memory device includes a first electrode and a second electrode, and a variable resistor interposed between the first and second electrodes. The variable resistor has a critical voltage, and a resistance-voltage characteristic of the variable resistor is switched at a voltage higher than the critical voltage, so that a resistance of the variable resistor is higher at a read voltage applied after the switching of the resistance-voltage curve than at a read voltage applied before the switching of the resistance-voltage curve. Methods of operating a nonvolatile memory device include setting a plurality of write voltages higher than an initial critical voltage, assigning respective data values to states in which a resistance-voltage characteristic is switched at the write voltages, setting a read voltage lower than the initial critical voltage, and reading the data values by measuring current flowing through the variable resistor in response to the read voltage.

Magnetic memory device and method of fabricating the same

There is provided a magnetic memory device and a method of forming the same. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions.

Resistive memory devices including selected reference memory cells operating responsive to read operations

A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.

Methods for sputtering a target material by intermittently applying a voltage thereto and related apparatus, and methods of fabricating a phase-changeable memory device employing the same

A method of sputtering to deposit a target material onto a substrate includes supplying an ionized gas to the substrate and the target material. A first DC bias voltage having a polarity opposite that of the ionized gas is applied to the target material to attract ions theretoward. A second DC bias voltage having a polarity opposite that of the first DC bias voltage is intermittently applied to the target material to reduce ion accumulation thereon. Related apparatus and methods of fabricating phase-changeable memory devices are also discussed.

Magnetic random access memory device and method of forming the same

Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line. A method of forming a semiconductor memory device may include forming a digit line on a substrate, forming an intermediate insulating layer covering the digit line, forming a magnetic tunnel junction (MTJ) pattern on the intermediate insulating layer, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., performing an annealing operation at a temperature of about 350° C. or higher, and forming a bit line connected to the capping pattern and disposed to intersect the digit line.

Magnetic tunnel junction structure having an oxidized buffer layer and method of fabricating the same

There are provided a magnetic tunnel junction structure and a method of fabricating the same. The magnetic tunnel junction structure includes a lower electrode, a lower magnetic layer pattern and a tunnel layer pattern, which are sequentially formed on the lower electrode. The magnetic tunnel junction structure further includes an upper magnetic layer pattern, a buffer layer pattern, and an upper electrode, which are sequentially formed on a portion of the tunnel layer pattern. The sidewall of the upper magnetic layer pattern is surrounded by an oxidized upper magnetic layer, and the sidewall of the buffer layer pattern is surrounded by an oxidized buffer layer. The depletion of the upper magnetic layer pattern and the lower magnetic layer pattern in the magnetic tunnel junction region can be prevented by the oxidized buffer layer.

Memory devices including multi-bit memory cells having magnetic and resistive memory elements and related methods

An integrated circuit memory device may include an integrated circuit substrate, and a multi-bit memory cell on the integrated circuit substrate. The multi-bit memory cell may be configured to store a first bit of data by changing a first characteristic of the multi-bit memory cell and to store a second bit of data by changing a second characteristic of the multi-bit memory cell. Moreover, the first and second characteristics may be different. Related methods are also discussed.

Resistive memory device e.g. magnetic random access memory, accessing method for storing data, involves applying predetermined voltage level to word line coupled to resistive memory cell block

The method involves applying a predetermined voltage level to a word line (W/L) coupled to a resistive memory cell block. Columns of resistive memory cells (R m, 500) are coupled to respective bitlines (BL1-BLn) that are coupled to respective sense amplifier circuits (SAl-SAn). A programming current is conducted via a pair of opposing current source transistors located on opposing sides of the block. A programming conductor is coupled to the current source transistor and extended across bit lines coupled to the memory cells. Independent claims are also included for the following: (1) a magnetic memory cell array device comprising a current source line (2) a method of reading data from a resistive memory device (3) a method of writing data to a resistive memory device (4) a method of providing programming current to resistive memory cells (5) a resistive memory device comprising a pair of opposing current source transistors.

Resistive memory devices and methods of forming resistive memory devices

Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.

Method of fabricating semiconductor device

A method of fabricating a semiconductor device, the method including providing a substrate; forming an underlying layer on the substrate; forming a sacrificial layer on the underlying layer; forming an opening in the sacrificial layer by patterning the sacrificial layer such that the opening exposes a predetermined region of the underlying layer; forming a mask layer in the opening; forming an oxide mask by partially or completely oxidizing the mask layer; removing the sacrificial layer; and etching the underlying layer using the oxide mask as an etch mask to form an underlying layer pattern.

Resistive memory devices including selected reference memory cells

Memory element of multi-bit memory cell, multi-bit memory cell, and method of operating same

【課題】多数抵抗状態を有する抵抗メモリ要素、抵抗メモリセル及びその動作方法、そして前記抵抗メモリ要素を適用したデータ処理システムを提供する。 【解決手段】多数抵抗状態を示す抵抗メモリセルが提供される。この抵抗メモリセルは、高抵抗状態のとき、多数レベルの電流を印加することによって、多数レベルの電流に対応する多数レベルの抵抗状態に切り換えられる。その結果、抵抗メモリセルは、多数レベルの抵抗状態及び高い抵抗状態に切り換えられ、これらの状態に応じて情報を貯蔵することができる。 【選択図】図３

Resistive memory devices including selected reference memory cells operating responsive to read operations

A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.

Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates

A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.

Semiconductor device

A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring.

磁性穿隧接面元件、電子元件、記憶體系統及磁性元件的製造方法

提供一種磁性穿隧接面元件，包括固定磁性結構；自由磁性結構；以及穿隧能障，其介於固定磁性結構及自由磁性結構之間。固定磁性結構及自由磁性結構中的至少一者包括垂直磁化維持層；磁性層，其介於垂直磁化維持層及穿隧能障之間；以及垂直磁化誘發層，其介於垂直磁化維持層及磁性層之間。

Multi-state resistive memory element, multi-bit resistive memory cell, operating method thereof, and data processing system using the memory element

Resistives Mehrfachzustands-Speicherelement, resistive Mehrfachbit-Speicherzelle, Betriebsverfahren davon und das Speicherelement verwendendes Datenverarbeitungssystem

Eine Multi-Bit-Speicherzelle (1) speichert Information, die einem hohen resistiven Zustand und mehreren anderen resistiven Zuständen unterhalb des hohen resistiven Zustandes entspricht. Ein Widerstand eines Speicherelementes (20) innerhalb der Multi-Bit-Speicherzelle (1) schaltet von dem hohen resistiven Zustand in einen der anderen mehreren resistiven Zustände durch Anlegen eines entsprechenden Stroms an das Speicherelement (20).

Halbleitervorrichtung

Es wird eine Halbleitervorrichtung geschaffen. Die Halbleitervorrichtung umfasst ein Substrat, das eine Elementisolationsschicht umfasst, wobei die Elementisolationsschicht eine aktive Region definiert, eine Mehrzahl von Wortleitungen, welche die aktive Region in einer ersten Richtung überqueren, und eine Mehrzahl von Bit-Leitungsstrukturen auf dem Substrat, die mit der aktiven Region verbunden sind, wobei sich die Mehrzahl von Bit-Leitungsstrukturen in einer zweiten Richtung erstrecken, die sich von der ersten Richtung unterscheidet. Jede der Mehrzahl von Bit-Leitungsstrukturen umfasst eine Ruthenium-Leitungsverdrahtung, die eine untere Fläche und eine obere Fläche gegenüber der unteren Fläche umfasst, eine untere Graphenschicht, die mit der unteren Fläche der Ruthenium-Leitungsverdrahtung in Kontakt ist und die sich entlang der unteren Fläche der Ruthenium-Leitungsverdrahtung erstreckt, und eine Verdrahtungsleitungs-Deckschicht, die sich entlang der oberen Fläche der Ruthenium-Leitungsverdrahtung erstreckt.

Resistive memory devices including selected reference memory cells and methods of operating the same

Semiconductor device having a graphene film and method for fabricating thereof

A semiconductor device and a method for fabricating the same. The semiconductor device comprising: a first level wiring disposed at a first metal level, and includes a first line wiring, a first insulating capping film and a first side wall graphene film, the first insulating capping film extending along an upper surface of the first line wiring, and the first side wall graphene film extending along a side wall of the first line wiring; an interlayer insulating film covering the side wall of the first line wiring and a side wall of the first insulating capping film; and a second level wiring disposed at a second metal level higher than the first metal level, and includes a second via connected to the first line wiring, and a second line wiring connected to the second via, wherein the second via penetrates the first insulating capping film.

Magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of forming a perpendicular magnetic film of the same

Methods of Forming Resistive Memory Devices

Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.

Semiconductor memory device and method for fabricating the same

A semiconductor memory device includes a substrate having an element separation film defining active areas; and gate structures in trenches on the substrate and intersecting the active areas, wherein each of the gate structures includes a gate insulating layer extending along sidewalls and a bottom surface of a corresponding one of the trenches, a gate electrode layer on the gate insulating layer and including a first metal layer and a second metal layer on the first metal layer, a liner film between the gate insulating layer and the first metal layer and including a same metal material as the first and second metal layers, and a capping film in contact with the second metal layer.

Storage of non-volatile memory device and method of forming the same

Method for making high-reliable vias in semiconductor integrated circuit device

Method and system for providing magnetic junctions using thermally assisted spin transfer torque switching

A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a pinned layer and nonmagnetic spacer layer between the free and pinned layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The write current generates joule heating such that the free layer has a switching temperature greater than room temperature. The free layer includes a multilayer that is temperature sensitive and has at least one bilayer. Each bilayer includes first and second layers. The first layer includes an alloy of a magnetic transition metal and a rare earth. The second layer includes a magnetic layer. The multilayer has a room temperature coercivity and a switching temperature coercivity. The switching temperature coercivity is not more than one-half of the room temperature coercivity.

Method and system for providing magnetic junctions including free layers that are cobalt-free

A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a nonmagnetic spacer layer, and a reference layer. The free layer includes at least one of Fe and at least one Fe alloy. Furthermore, the free layer excludes Co. The nonmagnetic spacer layer adjoins the free layer. The nonmagnetic spacer layer residing between reference layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Method and system for providing a bottom pinned layer in a perpendicular magnetic junction usable in spin transfer torque magnetic random access memory applications

A magnetic junction and method for providing the magnetic junction are described. The magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The pinned layer has a perpendicular magnetic anisotropy (PMA) energy greater than its out-of-plane demagnetization energy. Providing the pinned layer includes providing a bulk PMA (B-PMA) layer, providing an interfacial PMA (I-PMA) layer on the B-PMA layer and then providing a sacrificial layer that is a sink for a constituent of the first I-PMA layer. An anneal is then performed. The sacrificial layer and part of the first I-PMA layer are removed after the anneal. Additional I-PMA layer(s) are provided after the removing. A remaining part of the first I-PMA layer and the additional I-PMA layer(s) have a thickness of not more than twenty Angstroms.