Wafer level packaging to lidded chips

Methods are provided for making a plurality of lidded microelectronic elements. In an exemplary embodiment, a lid wafer is assembled with a device wafer. Desirably, the lid wafer is severed into a plurality of lid elements to remove portions of the lid wafer overlying contacts at a front face of the device wafer adjacent to dicing lanes of the device wafer. Thereafter, desirably, the device wafer is severed along the dicing lanes to provide a plurality of lidded microelectronic elements.

TAILORED SPACER WALL COATINGS

The present invention provides a spacer assembly (100) which is tailored to provide a secondary electron emission coefficient of approximately 1 for the spacer assembly (100) when the spacer assembly (100) is subjected to flat panel display operating voltages. The present invention further provides a spacer assembly (100) which accomplishes the above achievement and which does not degrade severely when subjected to electron bombardment. The present invention further provides a spacer assembly (100) which accomplishes both of the above-listed achievements and which does not significantly contribute to contamination of the vacuum environment of the flat panel display or be susceptible to contamination that may evolve within the tube. Specifically, in one embodiment, the present invention is comprised of a spacer structure (102) which has a specific secondary electron emission coefficient function associated therewith. The material comprising the spacer structure (102) is tailored to provide ...

Structure and method of making lidded chips

Methods are provided for fabricating packaged chips having protective layers, e.g., lids or other overlying layers having transparent, partially transparent, or opaque characteristics or a combination of such characteristics. Methods are provided for fabricating the packaged chips. Lidded chip structures and assemblies including lidded chips are also provided.

Method of forming a wall structure in a microelectronic assembly

A method of forming a wall structure in a microelectronic assembly includes selectively depositing a flowable material on an upper surface of a first element in the microelectronic assembly, positioning a molding surface in contact with the deposited flowable material and controlling a distance between the upper surface of the first element and the molding surface with one or more objects positioned between the upper surface and the molding surface.

Pin referenced image sensor to reduce tilt in a camera module

The present invention relates to a camera module. The camera module includes a circuit panel having a top side, a bottom side and transparent region, the circuit panel having conductors. The module further includes a sensor unit disposed on the bottom side of the circuit panel, and the sensor unit includes a semiconductor chip having a front surface including an imaging area facing in a forward direction in alignment with the transparent region and an imaging circuit adapted to generate signals representative of an optical image impinging on the imaging area. The module further includes posts protruding from the bottom side of the circuit panel, wherein at least some of the posts being engagement posts having bottom surfaces, and at least some of the bottom surfaces abutting an engagement surface of the sensor unit.

TUNABLE LIQUID CRYSTAL LENS WITH SINGLE SIDED CONTACTS

A tunable liquid crystal lens device is provided that uses a number of conductive elements and external contacts all located along a common side of a device housing. The device may include planar electrodes, a patterned electrode, a heating element and a sensor, which may be in different layers of the device. The device is produced as part of an array of such devices and, in addition to the devices in the array, a plurality of electrical conductive strips are used to provide high conductivity connection to conductive layers in each of the devices, thereby allowing simultaneous testing of the devices in the array. 1. A liquid crystal lens structure comprising:a liquid crystal layer;a plurality of conductive elements;a housing; anda plurality of contacts on an exterior of the housing, each of the contacts being in electrical communication with at least one of the conductive elements, the contacts being adjacent to one another in a first predetermined region of the housing.2. A liquid crystal lens structure according to wherein the plurality of conductive elements comprises an electrode.3. A liquid crystal lens structure according to wherein the plurality of conductive elements comprises a heater element.4. A liquid crystal lens structure according to wherein the plurality of conductive elements comprises an electrical sensor.5. A liquid crystal lens structure according to wherein the plurality of contacts are arranged in a row along a first side of the housing.6. A liquid crystal lens structure according to wherein the lens is manufactured using a wafer-scale process in which a plurality of said lenses are constructed as part of an array that is subsequently singulated to form individual lenses claim 1 , and wherein each of a plurality of layers of the array corresponds to a layer in each of the lenses.7. A liquid crystal lens structure according to wherein the layers of the array include at least one layer with conductive bands each of which corresponds to a ...

Method and apparatus for testing operation of an optical liquid crystal device

Methods and apparatus for testing operation of a single or multiple tunable active optical device(s) operated by one or more driving electrodes are described Test methods and apparatus are provided for device testing without necessarily requiring direct physical contact with the driving electrodes Testing subjects devices to incident light along an optical path and to an external electric field applied to the device producing a dipolar charge distribution within the electrodes, causing the device to operate The effect of device operation on incident light is optically sensed The sensed effect is analyzed to identify device defects Test methods and apparatus are provided for testing multiple unsingulated devices during fabrication employing a strip contact structure having contact strips connected to multiple devices and extending to wafer edges, such that singulating devices leaves portions of the strip contact structure exposed on device dice edges providing electrical contacts in use.

Method for selective area stamping of optical elements on a substrate

Selective area stamping of optical elements may be performed to make multiple micro-optic components on one or two sides of a substrate may be fabricated using a batch process. The presence of molding material may be controlled on the substrate through the use of gaps.

Structure and method of making lidded chips

Lidded chip packages are provided in which an optoelectronic device chip has microelectronic circuits exposed at a surface of the chip with a lid mounted to overlie the optoelectronic device and the microelectronic circuits. An opaque film may be attached to the lid to overlie the microelectronic circuits while exposing the optoelectronic device. Lidded chip packages are also provided in which the lid overlies an active or passive device mounted to the chip. Wiring traces may be embedded within an adhesive between the lid and the chip.

Compliant terminal mountings with vented spaces and methods

A method of making chip assemblies includes providing an in-process assembly including a semiconductor wafer, a wafer compliant structure overlying a front surface of the wafer and cavities, and terminals carried on the compliant structure adjacent the cavities and electrically connected to the wafer, the cavities being substantially sealed. The method includes subdividing the in-process assembly to form individual chip assemblies, each including one or more chip regions of the wafer, a portion of the compliant structure and the terminals carried on the portion, and opening vents communicating with said cavities after said providing step.

Pin referenced image sensor to reduce tilt in a camera module

The present invention relates to a camera module. The camera module includes a circuit panel having a top side, a bottom side and transparent region, the circuit panel having conductors. The module further includes a sensor unit disposed on the bottom side of the circuit panel, and the sensor unit includes a semiconductor chip having a front surface including an imaging area facing in a forward direction in alignment with the transparent region and an imaging circuit adapted to generate signals representative of an optical image impinging on the imaging area. The module further includes posts protruding from the bottom side of the circuit panel, wherein at least some of the posts being engagement posts having bottom surfaces, and at least some of the bottom surfaces abutting an engagement surface of the sensor unit.

CONTACT STRUCTURE FOR A TUNABLE LIQUID CRYSTAL OPTICAL DEVICE

A tunable liquid crystal optical device defining an optical aperture and having a layered structure. The device includes a film electrode formed on a surface of a first substrate and covered by a second substrate, and a contact structure filling a volume within the layered structure and contacting the film electrode. The contact structure is located outside of the optical aperture and provides an electrical connection surface much larger than a thickness of the film electrode, such that reliable electrical connections may be made to the electrode, particularly in the context of wafer scale manufacturing of such a device.

METHOD AND APPARATUS FOR TESTING OPERATION OF AN OPTICAL LIQUID CRYSTAL DEVICE

Methods and apparatus for testing operation of a single or multiple tunable active optical device(s) operated by one or more driving electrodes are described Test methods and apparatus are provided for device testing without necessarily requiring direct physical contact with the driving electrodes Testing subjects devices to incident light along an optical path and to an external electric field applied to the device producing a dipolar charge distribution within the electrodes, causing the device to operate The effect of device operation on incident light is optically sensed The sensed effect is analyzed to identify device defects Test methods and apparatus are provided for testing multiple unsingulated devices during fabrication employing a strip contact structure having contact strips connected to multiple devices and extending to wafer edges, such that singulating devices leaves portions of the strip contact structure exposed on device dice edges providing electrical contacts in use.

Method and apparatus for non-contact electrical probe

Methods and apparatus for non-contact electrical probes are described. In accordance with the invention, non-contact electrical probes use negative or positive corona discharge. Non-contact electrical probes are suited for testing of OLED flat panel displays.

Method of forming a wall structure in a microelectronic assembly

A method of forming a wall structure in a microelectronic assembly includes selectively depositing a flowable material on an upper surface of a first element in the microelectronic assembly, positioning a molding surface in contact with the deposited flowable material and controlling a distance between the upper surface of the first element and the molding surface with one or more objects positioned between the upper surface and the molding surface.

COMPLIANT TERMINAL MOUNTINGS WITH VENTED SPACES AND METHODS

A compliant structure 36 is provided on a semiconductor wafer 22. The compliant structure 36 includes cavities 42. The compliant structure 36 and the wafer 22 seal the cavities 42 during process steps used to form conductive elements on the compliant structure. After processing, vents 58 are opened to connect the cavities 42 to the exterior of the assembly. The vents 58 may be formed by severing the wafer and compliant structure to form individual units 62, so that the severance planes 34a intersect channels or other voids communicating with the cavities 42. Alternatively, the vents may be formed by forming holes in the compliant structure, or by opening bores extending through the wafer. © KIPO & WIPO 2008 ...

Compliant terminal mountings with vented spaces and methods

A method of making chip assemblies includes providing an in-process assembly including a semiconductor wafer, a wafer compliant structure overlying a front surface of the wafer and cavities, and terminals carried on the compliant structure adjacent the cavities and electrically connected to the wafer, the cavities being substantially sealed. The method includes subdividing the in-process assembly to form individual chip assemblies, each including one or more chip regions of the wafer, a portion of the compliant structure and the terminals carried on the portion, and opening vents communicating with said cavities after said providing step.

STRUCTURE AND FABRICATION OF DEVICE, SUCH AS LIGHT-EMITTING DEVICE OR ELECTRON-EMITTING DEVICE, HAVING GETTER REGION

A light-emitting device is provided with getter material (58) that can readily be distributed in a relatively uniform manner across the device's active light-emitting portion. An electron- emitting device is similarly provided with getter material (112, 110/112, 128, 132, and 142) that can readily be distributed relatively uniformly across the active electron-emitting portion of the device. Techniques such as thermal spraying, angled physical deposition, and maskless electrophoretic/dielectrophoretic deposition can be utilized in depositing the getter material. © KIPO & WIPO 2007 ...

Fabricating of a flat-panel displace using porous spacer

A flat-panel display is fabricated according to a process in which a liquid-containing film (92, 116, 124, 132, 144, or 166) is formed over a substrate (80). In addition to suitable liquid, the liquid-containing film contains oxide or/and hydroxide. Liquid is removed from the liquid-containing film to convert it into a solid porous film (82 or 150) having (a) a porosity of at least 10% along an exposed face of the film, (b) an average resistivity of 10<8>-10<14 >ohm-cm at 25° C., and (c) an average thickness of no more than 20 mum. A spacer (24) formed with at least a segment of the substrate and overlying solid porous film is positioned between opposing first and second plate structures (20 and 22) of the display. The second plate structure (22) emits light upon receiving electrons emitted by the first plate structure (20).

MICROELECTRONIC ASSEMBLY WITH MULTI-LAYER SUPPORT STRUCTURE

A method of forming a microelectronic assembly includes positioning a support structure adjacent to an active region of a device but not extending onto the active region. The support structure has planar sections. Each planar section has a substantially uniform composition. The composition of at least one of the planar sections differs from the composition of at least one of the other planar sections. A lid is positioned in contact with the support structure and extends over the active region. The support structure is bonded to the device and to the lid.

Fabrication of flat-panel display having spacer with rough face for inhibiting secondary electron escape

A flat-panel display is fabricated by a process in which a spacer ( 24 ) having a rough face ( 54 or 56 ) is positioned between a pair of plate structure ( 20 and 22 ). When electrons strike the spacer, the roughness in the spacer's face causes the number of secondary electrons that escape the spacer to be reduced, thereby alleviating positive charge buildup on the spacer. As a result, the image produced by the display is improved. The spacer facial roughness can be achieved in various ways such as providing suitable depressions ( 60, 62, 64, 66, 70, 74 , or 80 ) or/and protuberances ( 82, 84, 88 , and 92 ) along the spacer's face.

Method and apparatus for non-contact electrical probe

Methods and apparatus for non-contact electrical probes are described. In accordance with the invention, non-contact electrical probes use negative or positive corona discharge. Non-contact electrical probes are suited for testing of OLED flat panel displays.

Flat-panel display having spacer with rough face for inhibiting secondary electron escape

A flat-panel display contains a pair of plate structure (20 and 22) separated by a spacer (24) having a rough face (54 or 56). When electrons strike the spacer, the roughness in the spacer's face causes the number of secondary electrons that escape the spacer to be reduced, thereby alleviating positive charge buildup on the spacer. As a result, the image produced by the display is improved. The spacer facial roughness can be achieved in various ways such as depressions (60, 62, 64, 66, 70, 74, or 80) or/and protuberances (82, 84, 88, and 92). Various techniques are presented for manufacturing the display, including the rough-faced spacer.

Method for selective area stamping of optical elements on a substrate

Selective area stamping of optical elements may be performed to make multiple micro-optic components on one or two sides of a substrate may be fabricated using a batch process. The presence of molding material may be controlled on the substrate through the use of gaps.

Chip assembly including package element and integrated circuit chip

The present invention provides an integrated circuit chip assembly and a method of manufacturing the same. The assembly includes a package element having a top surface and an integrated circuit chip having a top surface, a bottom surface, edge surface between the top and bottom surfaces, and contacts exposed at the top surface. The package element is disposed below the chip with the top surface of the package element facing toward the bottom surface of the chip. At least one spacer element resides between the top surface of the package element and the bottom surface of the chip. According to one embodiment, the at least one spacer element may form a substantially closed cavity between the package element and the integrated circuit chip. According to another embodiment, first conductive features may extend from the contacts of the chip along the top surface, and at least some of said first conductive features extend along at least one of the edge surfaces of the chip.

Compliant terminal mountings with vented spaces and methods

A compliant structure is provided on a semiconductor wafer. The compliant structure includes cavities. The compliant structure and the wafer seal the cavities during process steps used to form conductive elements on the compliant structure. After processing, vents are opened to connect the cavities to the exterior of the assembly. The vents may be formed by severing the wafer and compliant structure to form individual units, so that the severance planes intersect channels or other voids communicating with the cavities. Alternatively, the vents may be formed by forming holes in the compliant structure, or by opening bores extending through the wafer.

WAFER-LEVEL FABRICATION OF LIQUID CRYSTAL OPTOELECTRONIC DEVICES

Liquid crystal optoelectronic devices are produced by fabricating a wafer-level component structure and affixing a plurality of discrete components to a surface structure prior to singulating the individual devices therefrom. After singulation, the individual devices include a portion of the wafer-level fabricated structure and at least of the discrete components. The wafer-level structure may include a liquid crystal and controlling electrodes, and the discrete components may include fixed lenses or image sensors. The discrete components may be located on either or both of two sides of the wafer-level structure. Multiple liquid crystal layers may be used to reduce nonuniformities in the interaction with light from different angles, and to control light of different polarizations. The liquid crystal devices may function as optoelectronic devices such as tunable lenses, shutters or diaphragms.

Contact structure for a tunable liquid crystal optical device

A tunable liquid crystal optical device defining an optical aperture and having a layered structure. The device includes a film electrode formed on a surface of a first substrate and covered by a second substrate, and a contact structure filling a volume within the layered structure and contacting the film electrode. The contact structure is located outside of the optical aperture and provides an electrical connection surface much larger than a thickness of the film electrode, such that reliable electrical connections may be made to the electrode, particularly in the context of wafer scale manufacturing of such a device.

Stackable electronic device assembly

A stackable chip assembly is disclosed, as are many different embodiments relating to same. The chip assembly preferably includes at least two substrates with components mounted on each. The substrates are preferably situated with respect to one another such that components on one substrate extend towards the other substrate and vice versa. The components of each substrate preferably extend between each other. In addition various connections between the substrates are disclosed, as well as methods of constructing such chip assemblies.

Compliant terminal mountings with vented spaces and methods

A compliant structure 36 is provided on a semiconductor wafer 22. The compliant structure 36 includes cavities 42. The compliant structure 36 and the wafer 22 seal the cavities 42 during process steps used to form conductive elements on the compliant structure. After processing, vents 58 are opened to connect the cavities 42 to the exterior of the assembly. The vents 58 may be formed by severing the wafer and compliant structure to form individual units 62 , so that the severance planes 34a intersect channels or other voids communicating with the cavities 42. Alternatively, the vents may be formed by forming holes in the compliant structure, or by opening bores extending through the wafer.

Structure and method of making lidded chips

Methods are provided for fabricating packaged chips, each packaged chip having a protective layer, e.g., a transparent lid, metallic enclosure layer, shield layer, etc., and methods are provided for manufacturing such protective layer to be incorporated into a packaged chip. Lidded chip structures, and assemblies are also provided which include lidded chips.

CONTACT STRUCTURE FOR A TUNABLE LIQUID CRYSTAL OPTICAL DEVICE

A tunable liquid crystal optical device defining an optical aperture and having a layered structure. The device includes a film electrode formed on a surface of a first substrate and covered by a second substrate, and a contact structure filling a volume within the layered structure and contacting the film electrode. The contact structure is located outside of the optical aperture and provides an electrical connection surface much larger than a thickness of the film electrode, such that reliable electrical connections may be made to the electrode, particularly in the context of wafer scale manufacturing of such a device. 118-. (canceled)19. A method of manufacturing a tunable liquid crystal optical device that defines an optical aperture and has a layered structure including a liquid crystal layer and a lens structure layer , said method comprising:a. forming a film electrode on a surface of a substrate;b. forming a contact structure connected to said film electrode, said contact structure providing an electrical connection surface that is much larger than a thickness of said film electrode;c. using said substrate with said film electrode and said contact structure formed thereon in the construction of said layered structure of said device, said contact structure filling a volume within said layered structure and being located outside of said optical aperture of said device.20. A method as defined in claim 19 , wherein said forming said contact structure includes positioning said contact structure in contact with said film electrode such that when said layered structure is constructed said contact structure is located at or near an edge of said device.21. A method as defined in claim 19 , wherein said forming a contact structure includes depositing conductive material on said thin film electrode.22. A method as defined in claim 19 , wherein said forming a contact structure includes etching a groove in a substrate other than said substrate on which is formed said ...

Microelectronic assembly with multi-layer support structure

A method of forming a microelectronic assembly includes positioning a support structure adjacent to an active region of a device but not extending onto the active region. The support structure has planar sections. Each planar section has a substantially uniform composition. The composition of at least one of the planar sections differs from the composition of at least one of the other planar sections. A lid is positioned in contact with the support structure and extends over the active region. The support structure is bonded to the device and to the lid.

Wafer level chip packaging

Packaged microelectronic elements are provided. In an exemplary embodiment, a microelectronic element having a front face and a plurality of peripheral edges bounding the front face has a device region at the front face and a contact region with a plurality of exposed contacts adjacent to at least one of the peripheral edges. The packaged element may include a plurality of support walls overlying the front face of the microelectronic element such that a lid can be mounted to the support walls above the microelectronic element. For example, the lid may have an inner surface confronting the front face. In a particular embodiment, some of the contacts can be exposed beyond edges of the lid.

Compliant and hermetic solder seal

A solder joint or seal attaching components having dissimilar coefficients of thermal expansion is made thin (e.g., less than 20 mum and preferably about 5 mum) and of a solder such as an indium-based solder that has a tendency to creep. The solder is toroidal or otherwise shaped to avoid tensile stress in the solder. Axial shearing stress in the solder causes reversible creep without causing failure of the joint or seal. In one embodiment, a toroidal solder seal has a diameter, a footprint, and a thickness in approximate proportions of 5000:200:1.

Light-emitting and electron-emitting devices having getter regions

A light-emitting device contains getter material ( 58 ) typically distributed in a relatively uniform manner across the device's active light-emitting portion. An electron-emitting device similarly contains getter material ( 112, 110/112, 128, 132 , and 142 ) typically distributed relatively uniformly across the active electron-emitting portion of the device.

Calibration of tunable liquid crystal optical device

A tunable liquid crystal optical device is described. The optical device has an electrode arrangement associated with a liquid crystal cell and includes a hole patterned electrode, wherein control of the liquid crystal cell depends on electrical characteristics of liquid crystal optical device layers. The optical device further has a circuit for measuring said electrical characteristics of the liquid crystal optical device layers, and a drive signal circuit having at least one parameter adjusted as a function of the measured electrical characteristics. The drive signal circuit generates a control signal for the electrode arrangement.

Getter for atmospheric gases in optical switch working fluid

An optical switch includes a core and a fluid reservoir. The core includes a base, a matrix controller substrate, and a planar lightwave circuit. The planar lightwave circuit has a plurality of waveguides and a plurality of trenches. Each trench is located at an intersection of two waveguides. The fluid reservoir supplies a fluid to the plurality of trenches of the core. The optical switch further includes a getter for removing atmospheric gases from the fluid. The getter may be a porous silica getter, a non-evaporable getter, or an evaporable getter. By removing atmospheric gases from the fluid, the getter improves the capacity and operation of the optical switch. The optical switch may further include a membrane to separate the getter in a getter chamber from the fluid in a fluid chamber.

Constitution and fabrication of flat-panel display and porous-faced structure suitable for partial or full use in spacer of flat-panel display

A structure that is suitable for partial or full use in a spacer of a flat-panel display. The structure may be formed with a porous body having a face along which multiple primary pores extend into the porous body. A coating consisting primarily of carbon and having a highly uniform thickness overlies the porous body's face, extending along the primary pores to coat their surfaces and converting the primary pores into further pores. The coating can be created by removing non-carbon material from carbon-containing species provided along the pores. A solid porous film whose thickness is normally no more than 20 mum has a resistivity of 108-1014 ohm-cm. A spacer for a flat-panel display contains a support body and an overlying, normally porous, layer whose resistivity is greater parallel to a face of the support body than perpendicular to the body's face.

High efficiency insulation for improving thermal efficiency of bubble optical switch

An optical switch includes a core, a fluid reservoir coupled to the core via a tube, a thermal solution, and an insulating structure. The core includes a base, a matrix controller substrate, and a planar lightwave circuit. The planar lightwave circuit has a plurality of waveguides and trenches for rerouting an optical stream. The fluid reservoir supplies fluid to the plurality of trenches of the core. The core and the fluid reservoir are mounted on the thermal solution, which maintains the fluid reservoir at a higher temperature than the core by removing heat from the core and transferring some heat to the fluid reservoir. The insulating structure reduces any thermal leakage from the fluid reservoir to the core. In addition, the insulating structure can improve the temperature of the planar lightwave circuit and prevent unwanted atmospheric gases from entering the optical switch.

Wire bonded wafer level cavity package

A microelectronic device includes a chip having a front surface and a rear surface, the front surface having an active region and a plurality of contacts exposed at the front surface outside of the active region. The device further includes a lid overlying the front surface. The lid has edges bounding the lid, at least one of the edges including one or more outer portions and one or more recesses extending laterally inwardly from the outer portions, with the contacts being aligned with the recesses and exposed through them.

Vented cavity, hermetic solder seal

Fluxless soldering processes use pressure variations and vented cavities within large-area solder joints to reduce void volumes and improve the properties of the large-area solder joints. The vents can be sealed after soldering if closed cavities are desired. A cavity can also improve hermeticity of a solder joint by providing an additional solder fillet around the cavity in addition to the solder fillet around the perimeter of the solder joint.

Microelectronic assembly with multi-layer support structure

A method of forming a microelectronic assembly includes positioning a support structure adjacent to an active region of a device but not extending onto the active region. The support structure has planar sections. Each planar section has a substantially uniform composition. The composition of at least one of the planar sections differs from the composition of at least one of the other planar sections. A lid is positioned in contact with the support structure and extends over the active region. The support structure is bonded to the device and to the lid.

Compliant terminal mountings with vented spaces and methods

A compliant structure is provided on a semiconductor wafer. The compliant structure includes cavities. The compliant structure and the wafer seal the cavities during process steps used to form conductive elements on the compliant structure. After processing, vents are opened to connect the cavities to the exterior of the assembly. The vents may be formed by severing the wafer and compliant structure to form individual units, so that the severance planes intersect channels or other voids communicating with the cavities. Alternatively, the vents may be formed by forming holes in the compliant structure, or by opening bores extending through the wafer.

Wire bonded wafer level cavity package

A microelectronic device includes a chip having a front surface and a rear surface, the front surface having an active region and a plurality of contacts exposed at the front surface outside of the active region. The device further includes a lid overlying the front surface. The lid has edges bounding the lid, at least one of the edges including one or more outer portions and one or more recesses extending laterally inwardly from the outer portions, with the contacts being aligned with the recesses and exposed through them.

Constitution and fabrication of flat-panel display and porous-faced structure suitable for partial of full use in spacer of flat-panel display

A structure suitable for partial or full use in a spacer (24) of a flat-panel display has a porous face (54). The structure may be formed with multiple aggregates (100) of coated particles (102) bonded together in an open manner to form pores (58). A coating (88) consisting primarily of carbon and having a highly uniform thickness may extend into pores of a porous body (46). The coating can be created by removing non-carbon material from carbon-containing species provided along the pores. A solid porous film (82) whose thickness is normally no more than 20 mum has a resistivity of 10<8>-10<14 >ohm-cm. A spacer for a flat-panel display contains a support body (80) and an overlying, normally porous, layer (82) whose resistivity is greater parallel to a face of the support body than perpendicular to the body's face.

Tailored spacer wall coatings for reduced secondary electron emission

The present invention provides a spacer assembly which is tailored to provide a secondary electron emission coefficient of approximately 1 for the spacer assembly when the spacer assembly is subjected to flat panel display operating voltages. The present invention further provides a spacer assembly which accomplishes the above achievement and which does not degrade severely when subjected to electron bombardment. The present invention further provides a spacer assembly which accomplishes both of the above-listed achievements and which does not significantly contribute to contamination of the vacuum environment of the flat panel display or be susceptible to contamination that may evolve within the tube. Specifically, in one embodiment, the present invention is comprised of a spacer structure which has a specific secondary electron emission coefficient function associated therewith. The material comprising the spacer structure is tailored to provide a secondary electron emission coefficient ...

Oriented niobate ferroelectric thin films for electrical and optical devices

SrxBa1-xNb2O6, where x is greater than 0.25 and less than 0.75, and KNbO3 ferroelectric thin films metalorganic chemical vapor deposited on amorphous or cyrstalline substrate surfaces to provide a crystal axis of the film exhibiting a high dielectric susceptibility, electro-optic coefficient, and/or nonlinear optic coefficient oriented preferentially in a direction relative to a crystalline or amorphous substrate surface. Such films can be used in electronic, electro-optic, and frequency doubling components.

Wafer level chip packaging

Packaged microelectronic elements are provided. In an exemplary embodiment, a microelectronic element having a front face and a plurality of peripheral edges bounding the front face has a device region at the front face and a contact region with a plurality of exposed contacts adjacent to at least one of the peripheral edges. The packaged element may include a plurality of support walls overlying the front face of the microelectronic element such that a lid can be mounted to the support walls above the microelectronic element. For example, the lid may have an inner surface confronting the front face. In a particular embodiment, some of the contacts can be exposed beyond edges of the lid.

Calibration of tunable liquid crystal optical device

A tunable liquid crystal optical device is described. The optical device has an electrode arrangement associated with a liquid crystal cell and includes a hole patterned electrode, wherein control of the liquid crystal cell depends on electrical characteristics of liquid crystal optical device layers. The optical device further has a circuit for measuring said electrical characteristics of the liquid crystal optical device layers, and a drive signal circuit having at least one parameter adjusted as a function of the measured electrical characteristics. The drive signal circuit generates a control signal for the electrode arrangement.

CONTACT STRUCTURE FOR A TUNABLE LIQUID CRYSTAL OPTICAL DEVICE

A tunable liquid crystal optical device defining an optical aperture and having a layered structure. The device includes a film electrode formed on a surface of a first substrate and covered by a second substrate, and a contact structure filling a volume within the layered structure and contacting the film electrode. The contact structure is located outside of the optical aperture and provides an electrical connection surface much larger than a thickness of the film electrode, such that reliable electrical connections may be made to the electrode, particularly in the context of wafer scale manufacturing of such a device. 122-. (canceled)23. A tunable liquid crystal optical device defining an optical aperture and having a layered structure , said device comprising:a first substrate having an upper surface and a side edge;a first film electrode on the upper surface, the first film electrode having a bottom surface on the upper surface and also having a top surface, a side edge between the first film electrode bottom surface and the first film electrode top surface, and a first thickness between the first film electrode top surface and the first film electrode bottom surface; anda second substrate having an upper surface, a lower surface on the top surface of the first film electrode, a side edge, a second thickness between the second substrate upper surface and the second substrate lower surface at a central portion of the second substrate and a third thickness between the second substrate upper surface and the second substrate lower surface at the second substrate side edge,the lower surface of the second substrate being spaced from the top surface of the first film electrode at the side edge of the second electrode such that a cavity is formed between the lower surface of the second substrate and the top surface of the first film electrode inward of the side edge of the first film electrode,wherein a distance from the top edge of the first film electrode at the side ...

AVOIDING GHOST IMAGES

Examples are disclosed herein that relate to reducing reflectivity in a micro-LED array in a display device to avoid ghost images. One example provides a method comprising forming a structure comprising a plurality of light emitters arranged to form a scannable light-emitter array, and forming a material having a lower reflectivity than inactive regions located between the light emitters. 1. A method comprising:forming a structure comprising a plurality of light emitters arranged to form a scannable light-emitter array; andforming a material having a lower reflectivity than inactive regions located between the light emitters.2. The method of claim 1 , wherein the material having the lower reflectivity than the backplane is formed on the backplane before mounting the light emitters to the backplane.3. The method of claim 2 , wherein the material having the lower reflectivity than the backplane onto the backplane is patterned on the backplane.4. The method of claim 1 , wherein the material having the lower reflectivity than the backplane is applied to the backplane after mounting light emitters to the backplane.5. The method of claim 4 , wherein forming the material having the lower reflectivity than the backplane comprises dispensing the material in the areas of the backplane located between the light emitters.6. The method of claim 4 , wherein forming the material having the lower reflectivity than the backplane comprises placing a pre-formed layer over the backplane claim 4 , the pre-formed layer comprising openings in locations matched to locations of the light emitters.7. The method of claim 1 , wherein forming the material having the lower reflectivity than the backplane comprises growing a field of optically absorbing nanotubes on the backplane.8. The method of claim 1 , wherein mounting the plurality of light emitters comprises mounting multiple staggered rows of light emitters to the backplane.9. The method of claim 1 , wherein the material having the lower ...

Method and apparatus for testing operation of an optical liquid crystal device

Methods and apparatus for testing operation of a single or multiple tunable active optical device(s) operated by one or more driving electrodes are described. Test methods and apparatus are provided for device testing without necessarily requiring direct physical contact with the driving electrodes. Testing subjects devices to incident light along an optical path and to an external electric field applied to the device producing a dipolar charge distribution within the electrodes, causing the device to operate. The effect of device operation on incident light is optically sensed. The sensed effect is analyzed to identify device defects. Test methods and apparatus are provided for testing multiple unsingulated devices during fabrication employing a strip contact structure having contact strips connected to multiple devices and extending to wafer edges, such that singulating devices leaves portions of the strip contact structure exposed on device dice edges providing electrical contacts in use.

Getter for atmospheric gases in optical switch working fluid

An optical switch (10, 10') includes a core (12) and a fluid reservoir (14). The core (12) includes a base (18), a matrix controller substrate (20), and a planar lightwave circuit (22). The planar lightwave circuit (22) has a plurality of waveguides (24) and a plurality of trenches (28). Each trench (28) is located at an intersection of two waveguides (24). The fluid reservoir (14) supplies a fluid (15) to the plurality of trenches (28) of the core (12). The optical switch (10, 10') further includes a getter (30) for removing atmospheric gases from the fluid (15). The getter (30) may be a porous silica getter, a non-evaporable getter, or an evaporable getter. By removing atmospheric gases from the fluid (15), the getter (30) improves the capacity and operation of the optical switch (10, 10'). The optical switch (10') may further include a membrane (32) to separate the getter (30) in a getter chamber (34) from the fluid (15) in a fluid chamber (36).

Method for selective area stamping of optical elements on a substrate

Selective area stamping of optical elements may be performed to make multiple micro-optic components on one or two sides of a substrate may be fabricated using a batch process. The presence of molding material may be controlled on the substrate through the use of gaps. Excess amounts of optically curable polymer (115) forced from between the stampers (110) and substrate (120) accumulate in gaps (191) at the edge of plateau areas (157) instead of being distributed as a film over the substrate (120). The stamper (110) may be coated with a release layer (117). Metal alignment marks (140) may be patterned for alignment purposes.

Packages and assemblies including lidded chips

A lidded chip is provided which includes a chip having a major surface and a plurality of first chip contacts exposed at the major surface. A lid overlies the major surface. A chip carrier is disposed between the chip and the lid, the chip carrier having an inner surface confronting the major surface and an outer surface confronting the lid. A plurality of first carrier contacts of the chip carrier are conductively connected to the first chip contacts. A plurality of second carrier contacts extend upwardly at least partially through the openings in the lid.

Wafer level chip packaging

Microelectronic assembly with multi-layer support structure

A method of forming a microelectronic assembly includes positioning a support structure adjacent to an active region of a device but not extending onto the active region. The support structure has planar sections. Each planar section has a substantially uniform composition. The composition of at least one of the planar sections differs from the composition of at least one of the other planar sections. A lid is positioned in contact with the support structure and extends over the active region. The support structure is bonded to the device and to the lid.

Microelectronic devices and methods of manufacturing such devices

A method of forming a microelectronic assembly includes providing a device (102) having an active region (106), applying an adhesive support structure (108) adjacent to the active region but not extending onto the active region, positioning a lid (110) in contact with the adhesive support structure and extending over the active region, pressing the lid (110) against a mold surface (118) that is contoured to complement the lid (110) and, while pressing the lid against the mold surface (118), molding a package (126) contiguous with the lid (110).

Structure and fabrication of device, such as light-emitting device or electron-emitting device, having getter region

A structure comprising: a plate; an electron emissive element overlying the plate; a support region overlying the plate; and a getter region overlying at least part of the support region, a composite opening extending through the getter region and through the support region generally laterally where the electron-emissive element overlies the plate.

Constitution and fabrication of flat-panel display and porous-faced structure suitable for partial or full used in spacer of flat-panel display

A STRUCTURE SUITABLE FOR PARTIAL OR FULL USE IN A SPACER (24) OF A FLAT-PANEL DISPLAY HAS A POROUS FACE (54). THE STRUCTURE MAY BE FORMED WITH MULTIPLE AGGREGATES (100) OF COATED PARTICLES (102) BONDED TOGETHER IN AN OPEN MANNER TO FORM PORES (58). A COATING (88) CONSISTING PRIMARILY OF CARBON AND HAVING A HIGHLY UNIFORM THICKNESS MAY EXTEND INTO PORES OF A POROUS BODY (46). THE COATING CAN BE CREATED BY REMOVING NON-CARBON MATERIAL FROM CARBON-CONTAINING SPECIES PROVIDED ALONG THE PORES. A SOLID POROUS FILM (82) WHOSE THICKNESS IS NORMALLY NO MORE THAN 20 µM HAS A RESISTIVITY OF 10(8) - 10(14) OHM-CM. A SPACER FOR A FLAT-PANEL DISPLAY CONTAINS A SUPPORT BODY (80) AND AN OVERLYING, NORMALLY POROUS, LAYER (82) WHOSE RESISTIVITY IS GREATER PARALLEL TO A FACE OF THE SUPPORT BODY THAN PERPENDICULAR TO THE BODY''S FACE.(FIG. 2)

Tailored spacer wall coatings

THE PRESENT INVENTION PROVIDES A SPACER ASSEMBLY (100) WHICH IS TAILORED TO PROVIDE A SECONDARY ELECTRON EMISSION COEFFICIENT OF APPROXIMATELY 1 FOR THE SPACER ASSEMBLY WHEN THE SPACER ASSEMBLY IS SUBJECTED TO FLAT PANEL DISPLAY OPERATING VOLTAGES. THE PRESENT INVENTION FURTHER PROVIDES A SPACER ASSEMBLY (100) WHICH ACCOMPLISHES THE ABOVE ACHIEVEMENT AND WHICH DOES NOT DEGRADE SEVERELY WHEN SUBJECTED TO ELECTRON BOMBARDMENT. THE PRESENT INVENTION FURTHER PROVIDES A SPACER ASSEMBLY (100) WHICH ACCOMPLISHES BOTH OF THE ABOVE-LISTED ACHIEVEMENTS AND WHICH DOES NOT SIGNIFICANTLY CONTRIBUTE TO CONTAMINATION OF THE VACUUM ENVIRONMENT OF THE FLAT PANEL DISPLAY OR BE SUSCEPTIBLE TO CONTAMINATION THAT MAY EVOLVE WITHIN THE TUBE. SPECIFICALLY, IN ONE EMBODIMENT, THE PRESENT INVENTION IS COMPRISED OF A SPACER STRUCTURE (102) WHICH HAS A SPECIFIC SECONDARY ELECTRON EMISSION COEFFICIENT FUNCTION ASSOCIATED HEREWITH. THE MATERIAL COMPRISING THE SPACER STRUCTURE (102) IS TAILORED TO PROVIDE A SECONDARY ELECTRON EMISSION COEFFICIENT OF APPROXIMATELY 1 FOR THE SPACER ASSEMBLY (100) WHEN THE SPACER ASSEMBLY IS SUBJECTED TO FLAT PANEL DISPLAY OPERATING VOLTAGES.

Angepasste Beschichtungen für einen Wandabstandshalter

Tailored spacer wall coatings

THE PRESENT INVENTION PROVIDES A SPACER ASSEMBLY (800) WHICH IS TAILORED TO PROVIDE A SECONDARY ELECTRON EMISSION COEFFICIENT OF APPROXIMATELY I FOR THE SPACER ASSEMBLY WHEN THE SPACER ASSEMBLY IS SUBJECTED TO FLAT PANEL DISPLAY OPERATING VOLTAGES. THE PRESENT INVENTION FURTHER PROVIDES A SPACER ASSEMBLY (800) WHICH ACCOMPLISHES THE ABOVE ACHIEVEMENT AND WHICH DOES NOT DEGRADE SEVERELY WHEN SUBJECTED TO ELECTRON BOMBARDMENT. THE PRESENT INVENTION FURTHER PROVIDES A SPACER ASSEMBLY (800) WHICH ACCOMPLLSHES BOTH OF THE ABOVE-LISTED ACHIEVEMENTS AND WHICH DOES NOT SIGNIFICANTLY CONTRIBUTE TO CONTAMINATION OF THE VACUUM ENVIRONMENT OF THE FLAT PANEL DISPLAY OR BE SUSCEPUBLE TO CONTAMINATION THAT MAY EVOLVE WITHIN THE TUBE. SPECIFICALLY, IN ONE EMBODIMENT, THE PRESENT INVENTION IS COMPRISED OF A SPACER STRUCTURE (802) WHICH HAS A SPECIFIC SECONDARY ELECTRON EMISSION COEFFICIENT FUNCTION ASSOCIATED THEREWITH. THE MATERIAL COMPRISING THE SPACER STRUCTURE (802) IS TAILORED TO PROVIDE A SECONDARY ELECTRON EMISSION COEFFICIENT OF APPROXIMATELY I FOR THE SPACER ASSEMBLY (800) WHEN THE SPACER ASSEMBLY IS SUBJECTED TO FLAT PANEL DISPLAY OPERATING VOLTAGES. (FIG. 8)

Angepasste beschichtungen für einen wandabstandshalter

Tailored spacer wall coatings

Angepasste beschichtungen für einen wandabstandshalter

Flat panel display, porous spacer structure and methods

A structure suitable for partial or full use in a spacer (24) of a flat panel display has a porous face (54). The structure (24) may be formed with multiple aggregates (100) of coated particles (102) bonded together in an open manner to form pores (58). A coating (88) consisting primarily of carbon and having a highly uniform thickness may extend into pores (58) of a porous body (46). The coating (88) can be created by removing non-carbon material from carbon-containing species provided alone the pores (58). A solid porous film (82) whose thickness is normally no more than 20 νm has a resistivity of 10?8 - 1014¿ ohm-cm. A spacer (24) for a flat panel display (Fig.1) contains a support body (80) and an overlaying, normally porous, layer (82) whose resistivity is greater parallel to a face of the support body then perpendicular to the body's face.

Constitution and fabrication of flat-panel display and porous-faced structure suitable for partial or full use in spacer of flat-panel display

Structure and fabrication of device, such as light-emitting device or electron-emitting device, having getter region

A light-emitting device is provided with getter material (58) that can readily be distributed in a relatively uniform manner across the device's active light-emitting portion. An electron-emitting device is similarly provided with getter material (112, 110/112, 128, 132, and 142) that can readily be distributed relatively uniformly across the active electron-emitting portion of the device. Techniques such as thermal spraying, angled physical deposition, and maskless electrophoretic/dielectrophoretic deposition can be utilized in depositing the getter material.

ゲッタ領域を有する発光装置又は電子放出装置のような装置の構造体及び製造方法

【課題】表示装置において、構造体の全体的な側面積を著しく増加させることなく、大きいゲッタ領域を得る。 【解決手段】発光装置が、装置のアクティブ発光部分を横切って相対的に均一な方法で容易に分配されるゲッタ物質（５８）を伴って設けられる。電子放出装置が、装置のアクティブ電子放出部分を横切って相対的に均一に容易に分配されるゲッタ物質（１１２と，１１０／１１２と，１２８と，１３２と，１４２）を伴って同様に設けられる。溶射、角を形成する物理析出、マスクレス電気泳動析出／誘電泳動析出のような技術が、ゲッタ物質を析出するために使用される。 【選択図】図５

ゲッタ領域を有する発光装置又は電子放出装置のような装置の構造体及び製造方法

【課題】表示装置において、構造体の全体的な側面積を著しく増加させることなく、大きいゲッタ領域を得る。 【解決手段】発光装置が、装置のアクティブ発光部分を横切って相対的に均一な方法で容易に分配されるゲッタ物質（５８）を伴って設けられる。電子放出装置が、装置のアクティブ電子放出部分を横切って相対的に均一に容易に分配されるゲッタ物質（１１２と，１１０／１１２と，１２８と，１３２と，１４２）を伴って同様に設けられる。溶射、角を形成する物理析出、マスクレス電気泳動析出／誘電泳動析出のような技術が、ゲッタ物質を析出するために使用される。 【選択図】図５

Structure and fabrication of device, such as light-emitting device or electron-emitting device, having getter region

A light-emitting device is provided with getter material (58) that can readily be distributed in a relatively uniform manner across the device's active light-emitting portion. An electron-emitting device is similarly provided with getter material (112, 110/112, 128, 132, and 142) that can readily be distributed relatively uniformly across the active electron-emitting portion of the device. Techniques such as thermal spraying, angled physical deposition, and maskless electrophoretic/dielectrophoretic deposition can be utilized in depositing the getter material.

有蓋晶片之晶圓級封裝

Method and apparatus for testing operation of an optical liquid crystal device

Methods and apparatus for testing operation of a single or multiple tunable active optical device(s) operated by one or more driving electrodes are described. Test methods and apparatus are provided for device testing without necessarily requiring direct physical contact with the driving electrodes. Testing subjects devices to incident light along an optical path and to an external electric field applied to the device producing a dipolar charge distribution within the electrodes, causing the device to operate. The effect of device operation on incident light is optically sensed. The sensed effect is analyzed to identify device defects. Test methods and apparatus are provided for testing multiple unsingulated devices during fabrication employing a strip contact structure having contact strips connected to multiple devices and extending to wafer edges, such that singulating devices leaves portions of the strip contact structure exposed on device dice edges providing electrical contacts in use.