METHOD FOR ACHIEVING IMPROVED EPITAXY QUALITY (SURFACE TEXTURE AND DEFECT DENSITY) ON FREE-STANDING (ALUMINUM, INDIUM, GALLIUM) NITRIDE ((AL,IN,GA)N) SUBSTRATES FOR OPTO-ELECTRONIC AND ELECTRONIC DEVICES

A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 10 5 , nitrogen source material partial pressure in a range of from about 1 to about 10 3 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 500 microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.

Large area, uniformly low dislocation density GaN substrate and process for making the same

Large area, uniformly low dislocation density single crystal III-V nitride material, e.g., gallium nitride having a large area of greater than 15 cm2, a thickness of at least 1 mm, an average dislocation density not exceeding 5E5 cm2, and a dislocation density standard deviation ratio of less than 25%, and methods of forming same, are disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

SINGLE CRYSTAL GROUP III NITRIDE ARTICLES AND METHOD OF PRODUCING SAME BY HVPE METHOD INCORPORATING A POLYCRYSTALLINE LAYER FOR YIELD ENHANCEMENT

In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article. 142.-. (canceled)43. A method of forming a semiconductor structure , the method comprising:depositing on a substrate a single-crystalline layer comprising a first III-nitride semiconductor material and a polycrystalline layer comprising a second III-nitride semiconductor material, thereby forming a semiconductor article; andafter the deposition of the single-crystalline layer and the polycrystalline layer, cooling the semiconductor article from a growth temperature to approximately room temperature, thereby forming a second semiconductor article, the second semiconductor article (a) being substantially crack-free and (b) having (i) a first surface comprising the single-crystalline first III-nitride semiconductor material and (ii) a second surface, opposite the first surface, comprising the polycrystalline second III-nitride semiconductor material.44. The method of claim 43 , further comprising planarizing the first surface of the second semiconductor article.45. The method of claim 44 , wherein the first surface of the second semiconductor article is planarized via chemical-mechanical polishing.46. The method of claim 43 , wherein claim 43 , during cooling from the growth ...

High electron mobility electronic device structures comprising native substrates and methods for making the same

An electronic device structure comprises a substrate layer of semi-insulating Al x Ga y In z N, a first layer comprising Al x Ga y In z N, a second layer comprising Al x′ Ga y′ In z′ N, and at least one conductive terminal disposed in or on any of the foregoing layers, with the first and second layers being adapted to form a two dimensional electron gas is provided. A thin (<1000 nm) III-nitride layer is homoepitaxially grown on a native semi-insulating III-V substrate to provide an improved electronic device (e.g., HEMT) structure.

Large diameter, high quality SiC single crystals, method and apparatus

A method and system of forming large-diameter SiC single crystals suitable for fabricating high crystal quality SiC substrates of 100, 125, 150 and 200 mm in diameter are described. The SiC single crystals are grown by a seeded sublimation technique in the presence of a shallow radial temperature gradient. During SiC sublimation growth, a flux of SiC bearing vapors filtered from carbon particulates is substantially restricted to a central area of the surface of the seed crystal by a separation plate disposed between the seed crystal and a source of the SiC bearing vapors. The separation plate includes a first, substantially vapor-permeable part surrounded by a second, substantially non vapor-permeable part. The grown crystals have a flat or slightly convex growth interface. Large-diameter SiC wafers fabricated from the grown crystals exhibit low lattice curvature and low densities of crystal defects, such as stacking faults, inclusions, micropipes and dislocations.

VICINAL GALLIUM NITRIDE SUBSTRATE FOR HIGH QUALITY HOMOEPITAXY

A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 m2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. Both upper and lower surfaces may be offcut. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

Amorphous silicon carbide thin film articles

Amorphous silicon carbide thin film structures, including: protective coatings for windows in infrared process stream monitoring systems and sensor domes, heated windows, electromagnetic interference shielding members and integrated micromachined sensors; high-temperature sensors and circuits; and diffusion barrier layers in VLSI circuits. The amorphous silicon carbide thin film structures are readily formed, e.g., by sputtering at low temperatures.

High surface quality GaN wafer and method of fabricating same

A high quality wafer comprising Al x Ga y In z N, wherein 0<y≦1 and x+y+z=1, characterized by a root mean square surface roughness of less than 1 nm in a 10×10 μm 2 area at its Ga-side. Such wafer is chemically mechanically polished (CMP) at its Ga-side, using a CMP slurry comprising abrasive particles, such as silica or alumina, and an acid or a base. The process of fabricating such high quality Al x Ga y In z N wafer may include steps of lapping, mechanical polishing, and reducing internal stress of said wafer by thermal annealing or chemical etching for further enhancement of its surface quality. The CMP process is usefully employed to highlight crystal defects on the Ga-side of the Al x Ga y In z N wafer.

Single crystal group III nitride articles and method of producing same by HVPE method incorporating a polycrystalline layer for yield enhancement

In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

Large diameter silicon carbide single crystals and apparatus and method of manufacture thereof

In an apparatus and method growing a SiC single crystal, a PVT growth apparatus is provided with a single crystal SiC seed and a SiC source material positioned in spaced relation in a growth crucible. A resistance heater heats the growth crucible such that the SiC source material sublimates and is transported via a temperature gradient that forms in the growth crucible in response to the heater heating the growth crucible to the single crystal SiC seed where the sublimated SiC source material condenses forming a growing SiC single crystal. Purely axial heat fluxes passing through the bottom and the top of the growth crucible form a flat isotherm at least at a growth interface of the growing SiC single crystal on the single crystal SiC seed.

Low defect group III nitride films useful for electronic and optoelectronic devices and methods for making the same

In a method for making a low-defect single-crystal GaN film, an epitaxial nitride layer is deposited on a substrate. A first GaN layer is grown on the epitaxial nitride layer by HVPE under a growth condition that promotes the formation of pits, wherein after growing the first GaN layer the GaN film surface morphology is rough and pitted. A second GaN layer is grown on the first GaN layer to form a GaN film on the substrate. The second GaN layer is grown by HVPE under a growth condition that promotes filling of the pits, and after growing the second GaN layer the GaN film surface morphology is essentially pit-free. A GaN film having a characteristic dimension of about 2 inches or greater, and a thickness normal ranging from approximately 10 to approximately 250 microns, includes a pit-free surface, the threading dislocation density being less than 1×108 cm−2.

Inclusion-free uniform semi-insulating group III nitride substrates and methods for making same

In a method for making an inclusion-free uniformly semi-insulating GaN crystal, an epitaxial nitride layer is deposited on a substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode, wherein a surface of the nucleation layer is substantially covered with pits and the aspect ratio of the pits is essentially the same. A GaN transitional layer is grown on the nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. After growing the transitional layer, a surface of the transitional layer is substantially pit-free. A bulk GaN layer is grown on the transitional layer by HVPE. After growing the bulk layer, a surface of the bulk layer is smooth and substantially pit-free. The GaN is doped with a transition metal during at least one of the foregoing GaN growth steps.

High surface quality GaN wafer and method of fabricating same

Al_xGa_yIn_zN, wherein 0<=x<=1, 0<=y<=1, 0<=z<=1, and x+y+z=1, characterized by a root mean square surface roughness of less than 1 nm in a 10x10 mum² area. The Al_xGa_yIn_zN may be in the form of a wafer, which is chemically mechanically polished (CMP) using a CMP slurry comprising abrasive particles, such as silica or alumina, and an acid or a base. High quality Al_xGa_yIn_zN wafers can be fabricated by steps including lapping, mechanical polishing, and reducing internal stress of said wafer by thermal annealing or chemical etching for further enhancement of its surface quality. CMP processing may be usefully employed to highlight crystal defects of an Al_xGa_yIn_zN wafer.

Fabrication and structure of electron emitters coated with material such as carbon

A cathode structure suitable for a flat panel display is provided with coated emitters. The emitters are formed with material, typically nickel, capable of growing to a high aspect ratio. These emitters are then coated with carbon containing material for improving the chemical robustness and reducing the work function. One coating process is a DC plasma deposition process in which acetylene is pumped through a DC plasma reactor to create a DC plasma for coating the cathode structure. An alternative coating process is to electrically deposit raw carbon-based material onto the surface of the emitters, and subsequently reduce the raw carbon-based material to the carbon containing material. Work function of coated emitters is typically reduced by about 0.8 to 1.0 eV.

Amorphous silicon carbide thin film coating

Amorphous silicon carbide thin film structures, including: protective coatings for windows in infrared process stream monitoring systems and sensor domes, heated windows, electromagnetic interference shielding members and integrated micromachined sensors; high-temperature sensors and circuits; and diffusion barrier layers in VLSI circuits. The amorphous silicon carbide thin film structures are readily formed, e.g., by sputtering at low temperatures.

GROUP III NITRIDE ARTICLES HAVING NUCLEATION LAYERS, TRANSITIONAL LAYERS, AND BULK LAYERS

Group III (Al, Ga, In)N single crystals, articles and films useful for producing optoelectronic devices (such as light emitting diodes (LEDs), laser diodes (LDs) and photodetectors) and electronic devices (such as high electron mobility transistors (HEMTs)) composed of III-V nitride compounds, and methods for fabricating such crystals, articles and films. 167-. (canceled)68. A bulk crystal structure comprising:a substrate;disposed over substantially all of a top surface of the substrate, a GaN nucleation layer having a pitted morphology, the GaN nucleation layer being single-crystalline and epitaxial with respect to the substrate;disposed over the GaN nucleation layer, a GaN transitional layer having a morphology that is less pitted with increasing distance from the GaN nucleation layer; anddisposed over the GaN transitional layer, a GaN bulk layer having (i) a morphology substantially free of pits through an entire thickness of the GaN bulk layer, and (ii) a surface that is substantially free of pits.69. The bulk crystal structure of claim 68 , further comprising an AlN layer disposed between the substrate and the GaN nucleation layer.70. The bulk crystal structure of claim 69 , wherein a thickness of the AlN layer is selected from the range of about 0.05 microns to about 10 microns.71. The bulk crystal structure of claim 68 , wherein the substrate comprises at least one of sapphire claim 68 , GaN claim 68 , silicon carbide claim 68 , gallium arsenide claim 68 , zinc oxide claim 68 , silicon claim 68 , spinel claim 68 , lithium gallate claim 68 , or lithium aluminate.72. The bulk crystal structure of claim 68 , wherein a thickness of the GaN nucleation layer is selected from the range of about 5 microns to about 100 microns.73. The bulk crystal structure of claim 68 , wherein a thickness of the GaN transitional layer is selected from the range of about 0.05 mm to about 1 mm.74. The bulk crystal structure of claim 68 , wherein a thickness of the GaN bulk layer is ...

III-V nitride homoepitaxial material of improved quality formed on free-standing (Al,In,Ga)N substrates

A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer of improved epitaxial quality deposited on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 10 5 , nitrogen source material partial pressure in a range of from about 1 to about 10 3 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 10 2 microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.

SINGLE CRYSTAL GROUP III NITRIDE ARTICLES AND METHOD OF PRODUCING SAME BY HVPE METHOD INCORPORATING A POLYCRYSTALLINE LAYER FOR YIELD ENHANCEMENT

In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article. 126.-. (canceled)27. A semiconductor structure comprising:a substrate;disposed over the substrate, a single-crystalline layer comprising a first III-nitride semiconductor material; anddisposed over the single-crystalline layer, a polycrystalline layer comprising a second III-nitride semiconductor material.28. The semiconductor structure of claim 27 , wherein the first III-nitride semiconductor material and the second III-nitride semiconductor material are the same.29. The semiconductor structure of claim 27 , wherein the single-crystalline layer comprises a nucleation layer comprising a plurality of pits and claim 27 , disposed thereover claim 27 , a bulk layer substantially free of pits.30. The semiconductor structure of claim 29 , wherein the nucleation layer and the bulk layer each comprise a material selected from the group consisting of GaN claim 29 , AlN claim 29 , InN claim 29 , and ternary and quaternary alloys and mixtures including one or more thereof.31. The semiconductor structure of claim 29 , wherein the single-crystalline layer comprises claim 29 , disposed between the nucleation layer and the bulk layer claim 29 , a transitional layer having a morphology that is ...

LARGE DIAMETER SILICON CARBIDE SINGLE CRYSTALS AND APPARATUS AND METHOD OF MANUFACTURE THEREOF

In an apparatus and method growing a SiC single crystal, a PVT growth apparatus is provided with a single crystal SiC seed and a SiC source material positioned in spaced relation in a growth crucible. A resistance heater heats the growth crucible such that the SiC source material sublimates and is transported via a temperature gradient that forms in the growth crucible in response to the heater heating the growth crucible to the single crystal SiC seed where the sublimated SiC source material condenses forming a growing SiC single crystal. Purely axial heat fluxes passing through the bottom and the top of the growth crucible form a flat isotherm at least at a growth interface of the growing SiC single crystal on the single crystal SiC seed. 1. A Physical Vapor Transport (PVT) growth apparatus for PVT growing an SiC single crystal comprising:a growth chamber;a growth crucible positioned in the growth chamber, the growth crucible configured to be charged with a SiC source material at a bottom of the growth crucible and a single crystal SiC seed at a top or lid of the growth crucible with the SiC source material and the single crystal SiC seed in spaced relation;thermal insulation surrounding the growth crucible inside of the growth chamber, the thermal insulation including a side insulation piece between a side of the growth crucible and a side of the growth chamber, a bottom insulation piece between the bottom of the growth crucible and a bottom of the growth chamber, a top insulation piece between the top of the growth crucible and a top of the growth chamber, and an insulation insert positioned in an opening in the top insulation piece, wherein the insulation insert has a thickness between 20 mm and 50 mm and a largest dimension between 90% and 120% of a largest dimension of the single crystal SiC seed; anda heater positioned between the bottom of the growth crucible and the bottom insulation piece, wherein a geometry of the insulation insert is tuned to control ...

Group III Nitride Articles and Methods for Making Same

Group III (Al, Ga, In)N single crystals, articles and films useful for producing optoelectronic devices (such as light emitting diodes (LEDs), laser diodes (LDs) and photodetectors) and electronic devices (such as high electron mobility transistors (HEMTs)) composed of III-V nitride compounds, and methods for fabricating such crystals, articles and films.

Laser Diode Orientation on Mis-Cut Substrates

A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate ( 201 ). In an illustrative implementation, a laser diode is oriented on a GaN substrate ( 201 ) wherein the GaN substrate includes a GaN (0001) surface off-cut from the <0001> direction predominantly towards either the <1120> or the <11 00> family of directions. For a <11 20> off-cut substrate, a laser diode cavity ( 207 ) may be oriented along the <1 100> direction parallel to lattice surface steps ( 202 ) of the substrate ( 201 ) in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For <11 00> off-cut substrate, the laser diode cavity may be oriented along the <1 100> direction orthogonal to lattice surface steps ( 207 ) of the substrate ( 201 ) in order to provide a cleave laser facet that is aligned with the surface lattice steps.

VICINAL GALLIUM NITRIDE SUBSTRATE FOR HIGH QUALITY HOMOEPITAXY

A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm−2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

Large area, uniformly low dislocation density GaN substrate and process for making the same

Large area, uniformly low dislocation density single crystal III-V nitride material, e.g., gallium nitride having a large area of greater than 15 cm2, a thickness of at least 1 mm, an average dislocation density not exceeding 5E5 cm−2, and a dislocation density standard deviation ratio of less than 25%. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

High surface quality GaN wafer and method of fabricating same

AlxGayInzN, wherein 0≦x≦1, 0≦y≦1, 0≦z≦1, and x+y+z=1, characterized by a root mean square surface roughness of less than 1 nm in a 10×10 μm2 area. The AlxGayInzN may be in the form of a wafer, which is chemically mechanically polished (CMP) using a CMP slurry comprising abrasive particles, such as silica or alumina, and an acid or a base. High quality AlxGayInzN wafers can be fabricated by steps including lapping, mechanical polishing, and reducing internal stress of said wafer by thermal annealing or chemical etching for further enhancement of its surface quality. CMP processing may be usefully employed to highlight crystal defects of an AlxGayInzN wafer.

Fabrication of flat-panel display having spacer with rough face for inhibiting secondary electron escape

A flat-panel display is fabricated by a process in which a spacer ( 24 ) having a rough face ( 54 or 56 ) is positioned between a pair of plate structure ( 20 and 22 ). When electrons strike the spacer, the roughness in the spacer's face causes the number of secondary electrons that escape the spacer to be reduced, thereby alleviating positive charge buildup on the spacer. As a result, the image produced by the display is improved. The spacer facial roughness can be achieved in various ways such as providing suitable depressions ( 60, 62, 64, 66, 70, 74 , or 80 ) or/and protuberances ( 82, 84, 88 , and 92 ) along the spacer's face.

Single crystal group III nitride articles and method of producing same by HVPE method incorporating a polycrystalline layer for yield enhancement

In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

Vicinal gallium nitride substrate for high quality homoepitaxy

A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm−2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

Method for making group III nitride articles

Group III (Al, Ga, In)N single crystals, articles and films useful for producing optoelectronic devices (such as light emitting diodes (LEDs), laser diodes (LDs) and photodetectors) and electronic devices (such as high electron mobility transistors (HEMTs)) composed of III-V nitride compounds, and methods for fabricating such crystals, articles and films.

Flat-panel display having spacer with rough face for inhibiting secondary electron escape

A flat-panel display contains a pair of plate structure (20 and 22) separated by a spacer (24) having a rough face (54 or 56). When electrons strike the spacer, the roughness in the spacer's face causes the number of secondary electrons that escape the spacer to be reduced, thereby alleviating positive charge buildup on the spacer. As a result, the image produced by the display is improved. The spacer facial roughness can be achieved in various ways such as depressions (60, 62, 64, 66, 70, 74, or 80) or/and protuberances (82, 84, 88, and 92). Various techniques are presented for manufacturing the display, including the rough-faced spacer.

Low dislocation density III-V nitride substrate including filled pits and process for making the same

Large area single crystal III-V nitride material having an area of at least 2 cm2, having a uniformly low dislocation density not exceeding 3×106 dislocations per cm2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

Vanadium compensated, SI SiC single crystals of NU and PI type and the crystal growth process thereof

In a crystal growth apparatus and method, polycrystalline source material and a seed crystal are introduced into a growth ambient comprised of a growth crucible disposed inside of a furnace chamber. In the presence of a first sublimation growth pressure, a single crystal is sublimation grown on the seed crystal via precipitation of sublimated source material on the seed crystal in the presence of a flow of a first gas that includes a reactive component that reacts with and removes donor and/or acceptor background impurities from the growth ambient during said sublimation growth. Then, in the presence of a second sublimation growth pressure, the single crystal is sublimation grown on the seed crystal via precipitation of sublimated source material on the seed crystal in the presence of a flow of a second gas that includes dopant vapors, but which does not include the reactive component.

Group III nitride articles and methods for making same

Group III (Al, Ga, In)N single crystals, articles and films useful for producing optoelectronic devices (such as light emitting diodes (LEDs), laser diodes (LDs) and photodetectors) and electronic devices (such as high electron mobility transistors (HEMTs)) composed of III-V nitride compounds, and methods for fabricating such crystals, articles and films.

PRODUCTION OF CARBON NANOTUBES

A method and apparatus for manufacture of carbon nanotubes, in which a substrate is contacted with a hydrocarbonaceous feedstock containing a catalytically effective metal to deposit the feedstock on the substrate, followed by oxidation of the deposited feedstock to remove hydrocarbonaceous and carbonaceous components from the substrate, while retaining the catalytically effective metal thereon, and contacting of the substrate having retained catalytically effective metal thereon with a carbon source material to grow carbon nanotubes on the substrate. The manufacture can be carried out with a petroleum feedstock such as an oil refining atmospheric tower residue, to produce carbon nanotubes in high volume at low cost. Also disclosed is a composite including porous material having single-walled carbon nanotubes in pores thereof.

High surface quality GaN wafer and method of fabricating same

AlxGayInzN, wherein 0≦x≦1, 0≦y≦1, 0≦z≦1, and x+y+z=1, characterized by a root mean square surface roughness of less than 1 nm in a 10×10 μm22area. The AlxGayInzN may be in the form of a wafer, which is chemically mechanically polished (CMP) using a CMP slurry comprising abrasive particles, such as silica or alumina, and an acid or a base. High quality AlxGayInzN wafers can be fabricated by steps including lapping, mechanical polishing, and reducing internal stress of said wafer by thermal annealing or chemical etching for further enhancement of its surface quality. CMP processing may be usefully employed to highlight crystal defects of an AlxGayInzN wafer.

Fabrication of electron emitters coated with material such as carbon

A cathode structure suitable for a flat panel display is provided with coated emitters. The emitters are formed with material, typically nickel, capable of growing to a high aspect ratio. These emitters are then coated with carbon containing material for improving the chemical robustness and reducing the work function. One coating process is a DC plasma deposition process in which acetylene is pumped through a DC plasma reactor to create a DC plasma for coating the cathode structure. An alternative coating process is to electrically deposit raw carbon-based material onto the surface of the emitters, and subsequently reduce the raw carbon-based material to the carbon containing material. Work function of coated emitters is typically reduced by about 0.8 to 1.0 eV.

SINGLE CRYSTAL GROUP III NITRIDE ARTICLES AND METHOD OF PRODUCING SAME BY HVPE METHOD INCORPORATING A POLYCRYSTALLINE LAYER FOR YIELD ENHANCEMENT

In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

Microelectronic and microelectromechanical devices comprising carbon nanotube components, and methods of making same

A microelectronic or microelectromechanical device, including a substrate and a carbon microfiber formed thereon, which may be employed as an electrical connector for the device or as a selectively translational component of a microelectromechanical (MEMS) device.

Single crystal group III nitride articles and method of producing same by HVPE method incorporating a polycrystalline layer for yield enhancement

In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

HIGH SURFACE QUALITY GAN WAFER AND METHOD OF FABRICATING SAME

A high quality wafer comprising AlxGayInzN, wherein 0 Подробнее

Semi-insulating GaN and method of making the same

Large-area, single crystal semi-insulating gallium nitride that is usefully employed to form substrates for fabricating GaN devices for electronic and/or optoelectronic applications. The large-area, semi-insulating gallium nitride is readily formed by doping the growing gallium nitride material during growth thereof with a deep acceptor dopant species, e.g., Mn, Fe, Co, Ni, Cu, etc., to compensate donor species in the gallium nitride, and impart semi-insulating character to the gallium nitride.

Large area, uniformly low dislocation density GaN substrate and process for making the same

Large area single crystal III-V nitride material having an area of at least 2 cm 2 , having a uniformly low dislocation density not exceeding 3×10 6 dislocations per cm 2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 10 2 pits/cm 2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

Large Diameter Silicon Carbide Single Crystals and Apparatus and Method of Manufacture Thereof

In an apparatus and method growing a SiC single crystal, a PVT growth apparatus is provided with a single crystal SiC seed and a SiC source material positioned in spaced relation in a growth crucible. A resistance heater heats the growth crucible such that the SiC source material sublimates and is transported via a temperature gradient that forms in the growth crucible in response to the heater heating the growth crucible to the single crystal SiC seed where the sublimated SiC source material condenses forming a growing SiC single crystal. Purely axial heat fluxes passing through the bottom and the top of the growth crucible form a flat isotherm at least at a growth interface of the growing SiC single crystal on the single crystal SiC seed. 1. A Physical Vapor Transport (PVT) growth apparatus for PVT growing an SiC single crystal comprising:a growth chamber;a growth crucible positioned in the growth chamber, the growth crucible configured to be charged with a SiC source material at a bottom of the growth crucible and a single crystal SiC seed at a top or lid of the growth crucible with the SiC source material and the single crystal SiC seed in spaced relation;thermal insulation surrounding the growth crucible inside of the growth chamber, the thermal insulation including a side insulation piece between a side of the growth crucible and a side of the growth chamber, a bottom insulation piece between the bottom of the growth crucible and a bottom of the growth chamber, a top insulation piece between the top of the growth crucible and a top of the growth chamber, and an insulation insert positioned in an opening in the top insulation piece, wherein the insulation insert has a thickness between 20 mm and 50 mm and a largest dimension between 90% and 120% of a largest dimension of the single crystal SiC seed; anda heater positioned between the bottom of the growth crucible and the bottom insulation piece, wherein a geometry of the insulation insert is tuned to control ...

Inclusion-free uniform semi-insulating group III nitride substrates and methods for making same

In a method for making an inclusion-free uniformly semi-insulating GaN crystal, an epitaxial nitride layer is deposited on a substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode, wherein a surface of the nucleation layer is substantially covered with pits and the aspect ratio of the pits is essentially the same. A GaN transitional layer is grown on the nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. After growing the transitional layer, a surface of the transitional layer is substantially pit-free. A bulk GaN layer is grown on the transitional layer by HVPE. After growing the bulk layer, a surface of the bulk layer is smooth and substantially pit-free. The GaN is doped with a transition metal during at least one of the foregoing GaN growth steps.

Vicinal gallium nitride substrate for high quality homoepitaxy

A III–V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm 2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm −2 . The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III–V nitride-based microelectronic and opto-electronic devices.

Vanadium Compensated, SI SiC Single Crystals of NU and PI Type and the Crystal Growth Process Thereof

In a crystal growth apparatus and method, polycrystalline source material and a seed crystal are introduced into a growth ambient comprised of a growth crucible disposed inside of a furnace chamber. In the presence of a first sublimation growth pressure, a single crystal is sublimation grown on the seed crystal via precipitation of sublimated source material on the seed crystal in the presence of a flow of a first gas that includes a reactive component that reacts with and removes donor and/or acceptor background impurities from the growth ambient during said sublimation growth. Then, in the presence of a second sublimation growth pressure, the single crystal is sublimation grown on the seed crystal via precipitation of sublimated source material on the seed crystal in the presence of a flow of a second gas that includes dopant vapors, but which does not include the reactive component. 1. A crystal growth method comprising:(a) providing a SiC single crystal seed and a polycrystalline SiC source material in spaced relation inside of a growth crucible that is disposed inside of a furnace chamber, the growth crucible disposed inside of a furnace chamber defining a growth ambient; and(b) sublimation growing a SiC single crystal on the SiC seed crystal via precipitation of sublimated SiC source material on the SiC seed crystal in the presence of a reactive atmosphere in the growth ambient that removes donor and/or acceptor background impurities from the growth ambient.2. The method of claim 1 , wherein the reactive atmosphere includes a halide vapor compound and one or more gases.3. The method of claim 2 , wherein:the halide vapor compound is comprised of (1) fluorine or chlorine, and (2) tantalum or niobium; andthe one or more gases includes argon, hydrogen, or a mixture of argon+hydrogen.4. The method of claim 2 , further including:(c) following step (b), changing the atmosphere in the growth ambient to a non-reactive atmosphere; and(d) following step (c), introducing ...

Integrated circuit devices and methods employing amorphous silicon carbide resistor materials

Integrated circuits, including field emission devices, have a resistor element of amorphous SixC1-x wherein 0 Подробнее

Large Diameter Silicon Carbide Single Crystals and Apparatus and Method of Manufacture Thereof

In an apparatus and method growing a SiC single crystal, a PVT growth apparatus is provided with a single crystal SiC seed and a SiC source material positioned in spaced relation in a growth crucible. A resistance heater heats the growth crucible such that the SiC source material sublimates and is transported via a temperature gradient that forms in the growth crucible in response to the heater heating the growth crucible to the single crystal SiC seed where the sublimated SiC source material condenses forming a growing SiC single crystal. Purely axial heat fluxes passing through the bottom and the top of the growth crucible form a flat isotherm at least at a growth interface of the growing SiC single crystal on the single crystal SiC seed. 1. A PVT growth apparatus for PVT growing an SiC single crystal comprising:a growth chamber;a growth crucible positioned in the growth chamber, the growth crucible configured to be charged with a SiC source material at a bottom of the growth crucible and a single crystal SiC seed at a top or lid of the growth crucible with the SiC source material and the single crystal SiC seed in spaced relation;thermal insulation surrounding the growth crucible inside of the growth chamber, the thermal insulation including a side insulation piece between a side of the growth crucible and a side of the growth chamber, a bottom insulation piece between the bottom of the growth crucible and a bottom of the growth chamber, a top insulation piece between the top of the growth crucible and a top of the growth chamber, and an insulation insert positioned in an opening in the top insulation piece, wherein the insulation insert has a thickness between 20 mm and 50 mm and a largest dimension between 90% and 120% of a largest dimension of the single crystal SiC seed; anda heater positioned between the bottom of the growth crucible and the bottom insulation piece, wherein a geometry of the insulation insert is tuned to control heat flux in the SiC single ...

Orientation of electronic devices on mis-cut substrates

A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate. In an illustrative implementation, a laser diode is oriented on a GaN substrate wherein the GaN substrate includes a GaN (0001) surface off-cut from the <0001>direction predominantly towards either the <11 20> or the <1 100> family of directions. For a <11 20> off-cut substrate, a laser diode cavity may be oriented along the <1 100> direction parallel to lattice surface steps of the substrate in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For a <1 100> off-cut substrate, the laser diode cavity may be oriented along the <1 100> direction orthogonal to lattice surface steps of the substrate in order to provide a cleaved laser facet that is aligned with the surface lattice steps.

Vanadium compensated, SI SiC single crystals of NU and PI type and the crystal growth process thereof

In a crystal growth apparatus and method, polycrystalline source material and a seed crystal are introduced into a growth ambient comprised of a growth crucible disposed inside of a furnace chamber. In the presence of a first sublimation growth pressure, a single crystal is sublimation grown on the seed crystal via precipitation of sublimated source material on the seed crystal in the presence of a flow of a first gas that includes a reactive component that reacts with and removes donor and/or acceptor background impurities from the growth ambient during said sublimation growth. Then, in the presence of a second sublimation growth pressure, the single crystal is sublimation grown on the seed crystal via precipitation of sublimated source material on the seed crystal in the presence of a flow of a second gas that includes dopant vapors, but which does not include the reactive component.

Inclusion-free uniform semi-insulating group III nitride substrate and methods for making same

In a method for making an inclusion-free uniformly semi-insulating GaN crystal, an epitaxial nitride layer is deposited on a substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode, wherein a surface of the nucleation layer is substantially covered with pits and the aspect ratio of the pits is essentially the same. A GaN transitional layer is grown on the nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. After growing the transitional layer, a surface of the transitional layer is substantially pit-free. A bulk GaN layer is grown on the transitional layer by HVPE. After growing the bulk layer, a surface of the bulk layer is smooth and substantially pit-free. The GaN is doped with a transition metal during at least one of the foregoing GaN growth steps.

Large diameter, high quality SiC single crystals, method and apparatus

A method and system of forming large-diameter SiC single crystals suitable for fabricating high crystal quality SiC substrates of 100, 125, 150 and 200 mm in diameter are described. The SiC single crystals are grown by a seeded sublimation technique in the presence of a shallow radial temperature gradient. During SiC sublimation growth, a flux of SiC bearing vapors filtered from carbon particulates is substantially restricted to a central area of the surface of the seed crystal by a separation plate disposed between the seed crystal and a source of the SiC bearing vapors. The separation plate includes a first, substantially vapor-permeable part surrounded by a second, substantially non vapor-permeable part. The grown crystals have a flat or slightly convex growth interface. Large-diameter SiC wafers fabricated from the grown crystals exhibit low lattice curvature and low densities of crystal defects, such as stacking faults, inclusions, micropipes and dislocations.

Laser diode orientation on mis-cut substrates

A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate ( 201 ). In an illustrative implementation, a laser diode is oriented on a GaN substrate ( 201 ) wherein the GaN substrate includes a GaN (0001) surface off-cut from the <0001> direction predominantly towards either the <1120> or the <1100> family of directions. For a <1120> off-cut substrate, a laser diode cavity ( 207 ) may be oriented along the <1100> direction parallel to lattice surface steps ( 202 ) of the substrate ( 201 ) in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For <1100> off-cut substrate, the laser diode cavity may be oriented along the <1100> direction orthogonal to lattice surface steps ( 207 ) of the substrate ( 201 ) in order to provide a cleave laser facet that is aligned with the surface lattice steps.

Group III nitride articles having nucleation layers, transitional layers, and bulk layers

Group III (Al, Ga, In)N single crystals, articles and films useful for producing optoelectronic devices (such as light emitting diodes (LEDs), laser diodes (LDs) and photodetectors) and electronic devices (such as high electron mobility transistors (HEMTs)) composed of III-V nitride compounds, and methods for fabricating such crystals, articles and films.

Electron emitters coated with carbon containing layer

A cathode structure suitable for a flat-panel display contains an emitter layer ( 213 ) divided into emitter lines, a plurality of electron emitters ( 229, 239 , or 230 ) situated over the emitter lines, and a gate layer ( 215 A) having an upper surface spaced largely above the electron emitters. The gate layer has a plurality of gate holes ( 215 B) each corresponding to one of the electron emitters. The cathode structure further includes a carbon-containing layer ( 340, 240 , or 241 ) coated over the electron emitters and directly on at least part of the upper surface of the gate layer such that at least part of the carbon-containing layer extending along and above the gate layer is exposed.

GaN boule grown from liquid melt using GaN seed wafers

A method of making a single crystal GaN boule, comprising contacting a GaN seed wafer with a GaN source environment under process conditions including a thermal gradient in the GaN source environment producing growth of gallium nitride on the GaN seed wafer, thereby forming the GaN boule. The GaN source environment in various implementations includes gallium melt in an ambient atmosphere of nitrogen or ammonia, or alternatively, supercritical ammonia containing solubilized GaN. The method produces single crystal GaN boules >10 millimeters in diameter, of device quality suitable for production of GaN wafers useful in the fabrication of microelectronic, optoelectronic and microelectromechanical devices and device precursor structures therefor.

Single crystal group III nitride articles and method of producing same by HVPE method incorporating a polycrystalline layer for yield enhancement

In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

High quality silicon carbide crystals and method of making the same

A physical vapor transport (PVT) apparatus suitable for growing SiC boules comprises a crystal growth chamber (with a defined central vertical axis), a sealed crucible containing sublimation source material and including a seed fixture disposed in an offset position with respect to the central vertical axis of the apparatus, and a heat source disposed to surround the crystal growth chamber. The heat source is configured to raise the temperature within the sealed crucible such that the source material vaporizes and deposits on the seed wafer. The offset position of the seed fixture creates a radial temperature gradient across an exposed surface of the seed as the crystal boule is grown.

Vicinal gallium nitride substrate for high quality homoepitaxy

A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm−2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

Production of carbon nanotubes

A method and apparatus for manufacture of carbon nanotubes, in which a substrate is contacted with a hydrocarbonaceous feedstock containing a catalytically effective metal to deposit the feedstock on the substrate, followed by oxidation of the deposited feedstock to remove hydrocarbonaceous and carbonaceous components from the substrate, while retaining the catalytically effective metal thereon, and contacting of the substrate having retained catalytically effective metal thereon with a carbon source material to grow carbon nanotubes on the substrate. The manufacture can be carried out with a petroleum feedstock such as an oil refining atmospheric tower residue, to produce carbon nanotubes in high volume at low cost. Also disclosed is a composite including porous material having single-walled carbon nanotubes in pores thereof.

Vicinal gallium nitride substrate for high quality homoepitaxy

A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm 2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm −2 . The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

Large Diameter, High Quality SiC Single Crystals, Method and Apparatus

A method and system of forming large-diameter SiC single crystals suitable for fabricating high crystal quality SiC substrates of 100, 125, 150 and 200 mm in diameter are described. The SiC single crystals are grown by a seeded sublimation technique in the presence of a shallow radial temperature gradient. During SiC sublimation growth, a flux of SiC bearing vapors filtered from carbon particulates is substantially restricted to a central area of the surface of the seed crystal by a separation plate disposed between the seed crystal and a source of the SiC bearing vapors. The separation plate includes a first, substantially vapor-permeable part surrounded by a second, substantially non vapor-permeable part. The grown crystals have a flat or slightly convex growth interface. Large-diameter SiC wafers fabricated from the grown crystals exhibit low lattice curvature and low densities of crystal defects, such as stacking faults, inclusions, micropipes and dislocations.

Fabrication of electron emitters coated with material such as carbon

A cathode structure suitable for a flat panel display is provided with coated emitters. The emitters are formed with material, typically nickel, capable of growing to a high aspect ratio. These emitters are then coated with carbon containing material for improving the chemical robustness and reducing the work function. One coating process is a DC plasma deposition process in which acetylene is pumped through a DC plasma reactor to create a DC plasma for coating the cathode structure. An alternative coating process is to electrically deposit raw carbon-based material onto the surface of the emitters, and subsequently reduce the raw carbon-based material to the carbon containing material. Work function of coated emitters is typically reduced by about 0.8 to 1.0 eV.

INCLUSION-FREE UNIFORM SEMI-INSULATING GROUP III NITRIDE SUBSTRATES AND METHODS FOR MAKING SAME

In a method for making an inclusion-free uniformly semi-insulating GaN crystal, an epitaxial nitride layer is deposited on a substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode, wherein a surface of the nucleation layer is substantially covered with pits and the aspect ratio of the pits is essentially the same. A GaN transitional layer is grown on the nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. After growing the transitional layer, a surface of the transitional layer is substantially pit-free. A bulk GaN layer is grown on the transitional layer by HVPE. After growing the bulk layer, a surface of the bulk layer is smooth and substantially pit-free. The GaN is doped with a transition metal during at least one of the foregoing GaN growth steps.

ORIENTATION OF ELECTRONIC DEVICES ON MIS-CUT SUBSTRATES

A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate. In an illustrative implementation, a laser diode is oriented on a GaN substrate wherein the GaN substrate includes a GaN (0001) surface off-cut from the <0001> direction predominantly towards either the <11 20> or the <1 100> family of directions. For a <11 20> off-cut substrate, a laser diode cavity may be oriented along the <1 100> direction parallel to lattice surface steps of the substrate in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For a <1 100> off-cut substrate, the laser diode cavity may be oriented along the <1 100> direction orthogonal to lattice surface steps of the substrate in order to provide a cleaved laser facet that is aligned with the surface lattice steps.

Large area, uniformly low dislocation density GaN substrate and process for making the same

Large area, uniformly low dislocation density single crystal III-V nitride material, e.g., gallium nitride having a large area of greater than 15 cm 2 , a thickness of at least 1 mm, an average dislocation density not exceeding 5E5 cm −2 , and a dislocation density standard deviation ratio of less than 25%. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 10 2 pits/cm 2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

III-V Nitride homoepitaxial material of improved MOVPE epitaxial quality (surface texture and defect density) formed on free-standing (Al,In,Ga)N substrates, and opto-electronic and electronic devices comprising same

A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer of improved epitaxial quality deposited on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 10 5 , nitrogen source material partial pressure in a range of from about 1 to about 10 3 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 10 2 microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.

GaN boule grown from liquid melt using GaN seed wafers

A method of making a single crystal GaN boule, comprising contacting a GaN seed wafer with a GaN source environment under process conditions including a thermal gradient in the GaN source environment producing growth of gallium nitride on the GaN seed wafer, thereby forming the GaN boule. The GaN source environment in various implementations includes gallium melt in an ambient atmosphere of nitrogen or ammonia, or alternatively, supercritical ammonia containing solubilized GaN. The method produces single crystal GaN boules >10 millimeters in diameter, of device quality suitable for production of GaN wafers useful in the fabrication of microelectronic, optoelectronic and microelectromechanical devices and device precursor structures therefor.

Single crystal group III nitride articles and method of producing same by HVPE method incorporating a polycrystalline layer for yield enhancement

In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

Large diameter silicon carbide single crystals and apparatus and method of manufacture thereof

In an apparatus and method growing a SiC single crystal, a PVT growth apparatus is provided with a single crystal SiC seed and a SiC source material positioned in spaced relation in a growth crucible. A resistance heater heats the growth crucible such that the SiC source material sublimates and is transported via a temperature gradient that forms in the growth crucible in response to the heater heating the growth crucible to the single crystal SiC seed where the sublimated SiC source material condenses forming a growing SiC single crystal. Purely axial heat fluxes passing through the bottom and the top of the growth crucible form a flat isotherm at least at a growth interface of the growing SiC single crystal on the single crystal SiC seed.

LARGE AREA, UNIFORMLY LOW DISLOCATION DENSITY GAN SUBSTRATE AND PROCESS FOR MAKING THE SAME

Large area, uniformly low dislocation density single crystal Ill-V nitride material, e.g., gallium nitride having a large area of greater than 15 cm 2 , a thickness of at least 1 mm, an average dislocation density not exceeding 5E5 cm −2 , and a dislocation density standard deviation ratio of less than 25%, and methods of forming same, are disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the Ill-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 10 2 pits/cm 2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

LARGE AREA, UNIFORMLY LOW DISLOCATION DENSITY GAN SUBSTRATE AND PROCESS FOR MAKING THE SAME

Large area single crystal III-V nitride material having an area of at least 2 cm2, having a uniformly low dislocation density not exceeding 3×106 dislocations per cm2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

Vicinal gallium nitride substrate for high quality homoepitaxy

A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 m2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3 E6 cm2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. Both upper and lower surfaces may be offcut. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

GROUP III NITRIDE ARTICLES AND METHODS FOR MAKING SAME

Group III (Al, Ga, In)N single crystals, articles and films useful for producing optoelectronic devices (such as light emitting diodes (LEDs), laser diodes (LDs) and photodetectors) and electronic devices (such as high electron mobility transistors (HEMTs)) composed of III-V nitride compounds, and methods for fabricating such crystals, articles and films. 167.-. (canceled)68. A method for forming a bulk crystal structure , the method comprising:providing a substrate within a growth reactor;growing a GaN nucleation layer over the substrate under nucleation layer growth conditions that produce a pitted nucleation layer surface;introducing a first doping impurity into the growth reactor during at least a portion of the growth of the GaN nucleation layer, at least some of the first doping impurity being incorporated within the GaN nucleation layer;growing a GaN transitional layer over the GaN nucleation layer under transitional layer growth conditions that (i) are different from the nucleation layer growth conditions and (ii) produce a transitional layer surface having a lesser percentage of pits than the pitted nucleation layer surface; andgrowing a GaN bulk layer over the transitional layer, the GaN bulk layer having a surface that is substantially free of pits.69. The method of claim 68 , further comprising depositing an AlN layer over the substrate prior to growing the GaN nucleation layer.70. The method of claim 69 , wherein the AlN layer is deposited by sputtering.71. The method of claim 68 , wherein at least one of the GaN nucleation layer claim 68 , the GaN transitional layer claim 68 , or the GaN bulk layer are grown by hydride vapor phase epitaxy.72. The method of claim 68 , wherein the nucleation layer growth conditions include a first growth temperature claim 68 , a first ammonia partial pressure claim 68 , a first V:III ratio claim 68 , and a first growth rate claim 68 , the transitional layer growth conditions include a second growth temperature claim 68 , ...

Semi-insulating GaN and method of making the same

Large-area, single crystal semi-insulating gallium nitride that is usefully employed to form substrates for fabricating GaN devices for electronic and/or optoelectronic applications. The large-area, semi-insulating gallium nitride is readily formed by doping the growing gallium nitride material during growth thereof with a deep acceptor dopant species, e.g., Mn, Fe, Co, Ni, Cu, etc., to compensate donor species in the gallium nitride, and impart semi-insulating character to the gallium nitride.

Vicinal gallium nitride substrate for high quality homoepitaxy

A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the <0001> direction predominantly toward a direction selected from the group consisting of <10-10> and <11-20> directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50x50 mum² AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm^-2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

High surface quality gan wafer and method of fabricating same

A high quality wafer comprising AlxGayInzN, wherein 0<y<1 and x+y+z=1, characterized by a root mean square surface roughness of less than 1 nm in a 10 x 10µm2 arera at its Gaside. Such wafer is chemically mechanically polished (CMP) at its Ga-side, using a CMP slurry comprising abrasive particles, such as silica or alumina, and an acid or a base. The process of fabricating such high quality Al¿x?GayInzN wafer may include steps of lapping, mechanical polishing, and reducing internal stress of said wafer by thermal annealing or chemical etching for further enhancement of its surface quality. The CMP process is usefuffy employed to highlight crystal defects on the Ga-side of the AlxGayInzN wafer.

High surface quality gan wafer and method of fabricating same

A high quality wafer comprising AlxGayInzN, wherein 0<y<1 and x+y+z=1, characterized by a root mean square surface roughness of less than 1 nm in a 10 x 10µm2 arera at its Gaside. Such wafer is chemically mechanically polished (CMP) at its Ga-side, using a CMP slurry comprising abrasive particles, such as silica or alumina, and an acid or a base. The process of fabricating such high quality Al¿x?GayInzN wafer may include steps of lapping, mechanical polishing, and reducing internal stress of said wafer by thermal annealing or chemical etching for further enhancement of its surface quality. The CMP process is usefuffy employed to highlight crystal defects on the Ga-side of the AlxGayInzN wafer.

High surface quality gan wafer and method of fabricating same

A method for producing a high quality wafer comprising Al x Ga y In z N, wherein 0<y≤1 and x+y+z=1, the method comprising the steps of: chemically mechanically polishing (CMP) said Al x Ga y In z N wafer blank at its Ga-side utilizing an acidic CMP slurry comprising abrasive particles having particle sizes of less than 200 nm, an acid, and optionally at least one oxidizing agent.

SEMI-INSULATING GaN AND METHOD OF MAKING THE SAME

Large area, uniformly low dislocation density gan substrate and process for making the same

The invention provides a vapor phase growth process utilizing a growth reactor for forming a large area, uniformly low dislocation density single crystal III-V nitride material on a substrate, said process comprising: (i) a first phase including one or more steps of growing the III-V nitride material on the substrate by a vapor phase growth technique under pitted growth conditions; and (ii) a second phase including one or more steps of growing the III-V nitride material by the vapor phase growth technique under pit-filling conditions effecting closure of pits and annihilation of defects on a growth surface of the III-V nitride material, wherein the process further comprises at least one of the following items (a) and (b): (a) any of the first phase and the second phase comprises a flow of any of ammonia and hydrogen chloride to the growth reactor, and the second phase comprises a lower ratio of flow of ammonia to flow of hydrogen chloride relative to the first phase; and (b) upon conclusion of the second phase, the growth surface is essentially pit-free. The large area, uniformly low dislocation density single crystal III-V nitride material produced by such process is suitable for use as a substrate, for example for the fabrication of microelectronic and/or optoelectronic devices.

LARGE AREA, UNIFORMLY LOW DISLOCATION DENSITY GaN SUBSTRATE AND PROCESS FOR MAKING THE SAME

The invention provides a vapor phase growth process utilizing a growth reactor for forming a large area, uniformly low dislocation density single crystal III-V nitride material on a substrate, said process comprising: (i) a first phase including one or more steps of growing the III-V nitride material on the substrate by a vapor phase growth technique under pitted growth conditions; and (ii) a second phase including one or more steps of growing the III-V nitride material by the vapor phase growth technique under pit-filling conditions effecting closure of pits and annihilation of defects on a growth surface of the III-V nitride material, wherein the process further comprises at least one of the following items (a) and (b): (a) any of the first phase and the second phase comprises a flow of any of ammonia and hydrogen chloride to the growth reactor, and the second phase comprises a lower ratio of flow of ammonia to flow of hydrogen chloride relative to the first phase; and (b) upon conclusion of the second phase, the growth surface is essentially pit-free. The large area, uniformly low dislocation density single crystal III-V nitride material produced by such process is suitable for use as a substrate, for example for the fabrication of microelectronic and/or optoelectronic devices.

Production of carbon nanotubes

A method and apparatus for manufacture of carbon nanotubes, in which a substrate is contacted with a hydrocarbonaceous feedstock containing a catalytically effective metal to deposit the feedstock on the substrate, followed by oxidation of the deposited feedstock to remove hydrocarbonaceous and carbonaceous components from the substrate, while retaining the catalytically effective metal thereon, and contacting of the substrate having retained catalytically effective metal thereon with a carbon source material to grow carbon nanotubes on the substrate. The manufacture can be carried out with a petroleum feedstock such as an oil refining atmospheric tower residue, to produce carbon nanotubes in high volume at low cost. Also disclosed is a composite including porous material having single-walled carbon nanotubes in pores thereof.

Production of carbon nanotubes

A method and apparatus for manufacture of carbon nanotubes, in which a substrate is contacted with a hydrocarbonaceous feedstock containing a catalytically effective metal to deposit the feedstock on the substrate, followed by oxidation of the deposited feedstock to remove hydrocarbonaceous and carbonaceous components from the substrate, while retaining the catalytically effective metal thereon, and contacting of the substrate having retained catalytically effective metal thereon with a carbon source material to grow carbon nanotubes on the substrate. The manufacture can be carried out with a petroleum feedstock such as an oil refining atmospheric tower residue, to produce carbon nanotubes in high volume at low cost. Also disclosed is a composite including porous material having single-walled carbon nanotubes in pores thereof.

Integrated circuit devices and methods employing amorphous silicon carbide resistor materials

Integrated circuits, including field emission devices, have a resistor element of amorphous Si x C 1-x wherein 0<x<1, and wherein the Si x C 1-x incorporates at least one impurity selected from the group consisting of hydrogen, halogens, nitrogen, oxygen, sulphur, selenium, transition metals, boron, aluminum, phosphorus, gallium, arsenic, lithium, beryllium, sodium and magnesium.

High electron mobility electronic device structures comprising native substrates and methods for making the same

An electronic device structure comprises a substrate layer of semi-insulating AlxGayInzN, a first layer comprising AlxGayInzN, a second layer comprising Alx-GayInz,N, and at least one conductive terminal disposed in or on any of the foregoing layers, with the first and second layers being adapted to form a two dimensional electron gas is provided. A thin (<1000 nm) III-nitride layer is homoepitaxially grown on a native semi-insulating III-V substrate to provide an improved electronic device (e.g., HEMT) structure.

Vanadium compensated, si sic single crystals of nu and pi type and the crystal growth process thereof

LARGE AREA, UNIFORMLY LOW DISLOCATION DENSITY GaN SUBSTRATE AND PROCESS FOR MAKING THE SAME

Large area single crystal III-V nitride material having an area of at least 2 cm 2 , having a uniformly low dislocation density not exceeding 3×10 6 dislocations per cm 2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 10 2 pits/cm 2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

LARGE DIAMETER, HIGH QUALITY SiC SINGLE CRYSTALS, METHOD AND APPARATUS

A method and system of forming large-diameter SiC single crystals suitable for fabricating high crystal quality SiC substrates of 100, 125, 150 and 200 mm in diameter are described. The SiC single crystals are grown by a seeded sublimation technique in the presence of a shallow radial temperature gradient. During SiC sublimation growth, a flux of SiC bearing vapors filtered from carbon particulates is substantially restricted to a central area of the surface of the seed crystal by a separation plate disposed between the seed crystal and a source of the SiC bearing vapors. The separation plate includes a first, substantially vapor-permeable part surrounded by a second, substantially non vapor-permeable part. The grown crystals have a flat or slightly convex growth interface. Large-diameter SiC wafers fabricated from the grown crystals exhibit low lattice curvature and low densities of crystal defects, such as stacking faults, inclusions, micropipes and dislocations.

Grossfläches gan-substrat mit einheitlich geringer versetzungsdichte und herstellungsverfahren dafür

Large diameter silicon carbide single crystals and apparatus and method of manufacture thereof

In an apparatus and method growing a SiC single crystal, a PVT growth apparatus is provided with a single crystal SiC seed and a SiC source material positioned in spaced relation in a growth crucible. A resistance heater heats the growth crucible such that the SiC source material sublimates and is transported via a temperature gradient that forms in the growth crucible in response to the heater heating the growth crucible to the single crystal SiC seed where the sublimated SiC source material condenses forming a growing SiC single crystal. Purely axial heat fluxes passing through the bottom and the top of the growth crucible form a flat isotherm at least at a growth interface of the growing SiC single crystal on the single crystal SiC seed.

开关柜带电闭锁装置

本实用新型公开了开关柜带电闭锁装置，包括壳体和伺服电机，所述壳体的内部设置有环氧树脂涂层，且环氧树脂涂层的内部设置有滑槽，所述滑槽的内部设置有缓冲弹簧，且缓冲弹簧的内部贯穿有顶杆，所述顶杆的一侧安装有齿条，且齿条一侧中部的上方安装有调节齿轮，所述伺服电机位于调节齿轮的后端，所述调节齿轮的一侧安装有限位片，且限位片的上方安装挡片，所述挡片之间安装有限位弹簧，且限位弹簧的内部贯穿有连接杆。该开关柜带电闭锁装置设置有缓冲弹簧和顶杆，使得顶杆沿滑槽的水平中心线方向压缩缓冲弹簧，避免缓冲弹簧偏斜，使得缓冲弹簧能够高效的作用于齿条，为齿条提供可靠的防护，以及能够有效的顶紧齿条。