HOSE INSPECTION SYSTEM

The invention relates to an inflight refuelling system and a method and apparatus for observing and monitoring the condition of a hose used for refuelling. A number of sensors observe the hose as it is deployed or retracted into the system to allow assessment of the condition of the hose. 1. A hose monitoring system for use in an aerial refuelling system having a hose deployment system for deploying and retracting a hose in and out of an aircraft; the hose monitoring system having:an observation system including one or more sensing devices arranged to observe the hose as it as it is deployed and retracted from the aircraft.2. A hose monitoring system according to claim 1 , wherein the observation system includes a plurality of sensing devices radially distributed around the hose for observing the hose from different directions.3. A hose monitoring system according to claim 1 , wherein each sensing device is one of the following types: an infra-red camera; an ultraviolet camera; a visible light camera; a hyperspectral camera; or a 3D laser profile sensor system.4. A hose monitoring system according to claim 1 , wherein the observation system includes one or more pairs of sensing devices which are different types claim 1 , wherein each pair of sensing devices is arranged to observe the same portion of the hose. A hose monitoring system according to claim 1 , further comprising a signal processor arranged to combine data provided from each of said pair of sensing devices to produce hybrid data.6. A hose monitoring system according to claim 1 , further comprising storage means for storing the data provided from the one or more sensing devices.7. A hose monitoring system according to claim 1 , wherein the hose deployment system further comprises a hose storage device for storing the hose when not deployed and a hose server having an aperture through which the hose passes claim 1 , the hose server arranged to translate generally laterally relative to the axis of the hose ...

COMPLIANT SILICON SUBSTRATES FOR HETEROEPITAXIAL GROWTH BY HYDROGEN-INDUCED EXFOLIATION

A method of fabricating a semiconductor device includes implanting dopants into a silicon substrate, and performing a thermal anneal process that activates the implanted dopants. In response to activating the implanted dopants, a layer of ultra-thin single-crystal silicon is formed in a portion of the silicon substrate. The method further includes performing a heteroepitaxy process to grow a semiconductor material from the layer of ultra-thin single-crystal silicon. 1. A method of fabricating a semiconductor device , the method comprising:implanting dopants into a silicon substrate;performing a thermal anneal process that activates the implanted dopants, and in response to activating the implanted dopants forming a layer of ultra-thin single-crystal silicon in a portion of the silicon substrate; andperforming a heteroepitaxy process to grow a semiconductor material from the layer of ultra-thin single-crystal silicon.2. The method of claim 1 , wherein the semiconductor material is different from silicon material included in the silicon substrate.3. The method of claim 1 , wherein the dopants comprise hydrogen (H).4. The method of claim 1 , wherein the layer of ultra-thin single-crystal silicon is contained between a first interfaced defined by direct contact between an underlying portion of the silicon substrate and the layer of ultra-thin single-crystal silicon and a second interface defined by direct contact between the semiconductor material and the layer of ultra-thin single-crystal silicon.5. The method of claim 4 , wherein a distance between the first interface and the second interface defines a thickness of the layer of ultra-thin single-crystal silicon that is less than 100 nm.6. The method of claim 1 , wherein the layer of ultra-thin single-crystal silicon accommodates stress and strain into itself claim 1 , while held on top of the silicon substrate.7. The method of claim 6 , wherein the strain and thickness of the ultra-thin single-crystal silicon ...

System and method for forming an assembly

A method for forming an assembly of a plurality of components. The method includes receiving, by a controller, one or more assembly identification parameters and controlling, by the controller, a light array disposed along an assembly jig based on the one or more assembly identification parameters.

COMPUTER-IMPLEMENTED METHODS AND SYSTEMS FOR AUTOMATIC GENERATION OF LAYOUT VERSUS SCHEMATIC (LVS) RULE FILES AND REGRESSION TEST DATA SUITES

A system, a computer program product, and a computer-implemented method are provided for automatically generating a LVS rule file, and/or for automatically generating a regression test data suite. 1. A method , the comprising: processing a design rule manual (DRM) document to generate a data structure that corresponds to the DRM document, wherein the data structure comprises an entry for each particular device, wherein each entry specifies one or more prohibited layers and one or more required layers for that particular device; and', 'automatically generating, based on the entries for each particular device in the data structure, a LVS rule file., 'in a processor in a computer, performing operations for2. The method of claim 1 , wherein processing the design rule manual (DRM) document to generate the data structure claim 1 , comprises:in the processor, performing operations for a parsing module, the operations comprising:reading text of the DRM document;extracting particular information from the text to generate extracted information comprising: a list of all layers of an integrated circuit that is specified by the DRM document, a list of all devices of the integrated circuit that are specified by the DRM document, a list of all prohibited layers for each particular device, and a list of all required layers for each particular device;generating, based on the extracted information, the entries for each particular device; andstoring each of the entries in the data structure that corresponds to the DRM document.3. The method of claim 2 , wherein the DRM document comprises information that describes and specifies physical design rules for particular devices of an integrated circuit claim 2 , wherein the information comprises:truth tables that describe one or more prohibited layers for each particular device, and one or more required layers for each particular device.4. The method of claim 1 , wherein automatically generating the LVS rule file claim 1 , comprises:in the ...

Offset vertical interconnect and compression post for 3d-integrated electrical device

An electrical device including a substrate, a dielectric layer supported by the substrate having at least one vertical post disposed within a via hole of the dielectric layer, and at least one electrically conductive vertical interconnect laterally offset from the post. The post is configured to impart a non-tensile state to a region of the electrical device underlying the post. The coefficient of thermal expansion (CTE) of the post may be configured to cooperate with the CTE of the dielectric layer to provide the non-tensile state, such as the dielectric layer having a CTE that is equal to or greater than a CTE of the post. The dielectric layer may have a CTE that is less than the CTE of the electrically conductive vertical interconnect, and may be arranged to provide a buffer to tensile forces imparted by the vertical interconnect.

Method of creating photolithographic masks for semiconductor device features with reduced design rule violations

A method of creating photolithographic masks for semiconductor device features with reduced design rule violations is provided. The method begins by providing preliminary data that represents an overall mask pattern. The preliminary data is processed to decompose the overall mask pattern into a plurality of component mask patterns. Next, a design rule check is performed on the plurality of component mask patterns to identify tip-to-tip and tip-to-line violations in the plurality of component mask patterns. The method continues by modifying at least one of the plurality of component mask patterns in accordance with the identified violations to obtain a modified set of component mask patterns, wherein each mask pattern in the modified set of component mask patterns is void of tip-to-tip and tip-to-line violations. Photolithographic masks are then created for the modified set of component mask patterns.

Cigarette-case.

Improvements in Cases for Cigarettes and the like.

2175. Pattison, J. W. H. Jan. 27. Contents, facilitating access to.-A cigarette or like case is provided in one or both of its halves with a cigarette-holding frame A, Fig. 1, consisting of a longitudinal central member B carrying transverse members, the ends of one of which are turned up at D to support an elastic band C, which holds the cigarette in position, the central member being of spring-blade form and fixed to the case. In the form shown in Fig. 3, in which the longitudinal member H is arranged parallel to the case hinge, the transverse part J is fashioned to hold the elastic band C, the second transverse part K being formed as a loop to retain the cigarettes. In both forms, the frames rise only to a limited extent, and are automatically restored to the flat position on the closing of the case.

Electrical contact fabrication

In one aspect, a method includes forming an electrical path between p-type mercury cadmium telluride and a metal layer. The forming of the electrical path includes depositing a layer of polycrystalline p-type silicon directly on to the p-type mercury cadmium telluride and forming the metal layer on the layer of polycrystalline p-type silicon. In another aspect, an apparatus includes an electrical path. The electrical path includes a p-type mercury cadmium telluride layer, a polycrystalline p-type silicon layer in direct contact with the p-type mercury cadmium telluride layer, a metal silicide in direct contact with the polycrystalline p-type silicon layer, and an electrically conductive metal on the metal silicide. In operation, holes, indicative of electrical current on the electrical path, flow from the p-type mercury cadmium telluride layer to the electrically conductive metal.

Improved Ammoniacal Preparations.

Offset vertical interconnect and compression post for 3d-integrated electrical device

Offset vertical interconnect and compression post for 3d-integrated electrical device

An electrical device including a substrate (130), a dielectric layer (120) supported by the substrate having at least one vertical post (122) disposed within a via hole (123) of the dielectric layer, and at least one electrically conductive vertical interconnect (126) laterally offset from the post. The post is configured to impart a non-tensile state to a region of the electrical device underlying the post. The coefficient of thermal expansion (CTE) of the post may be configured to cooperate with the CTE of the dielectric layer to provide the non- tensile state, such as the dielectric layer having a CTE that is equal to or greater than a CTE of the post. The dielectric layer may have a CTE that is less than the CTE of the electrically conductive vertical interconnect, and may be arranged to provide a buffer to tensile forces imparted by the vertical interconnect.

Trolling hook

Design for a wheel

Design for a wheel

Design fob a wheel

Design fob a wheel

Manufacture of centres for confectionery

Design for a wheel

Thermo electric alarm

Thermo electric alarm

Manufacture of centres for confectionery

Offset vertical interconnect and compression post for 3d-integrated electrical device

An electrical device including a substrate (130), a dielectric layer (120) supported by the substrate having at least one vertical post (122) disposed within a via hole (123) of the dielectric layer, and at least one electrically conductive vertical interconnect (126) laterally offset from the post. The post is configured to impart a non-tensile state to a region of the electrical device underlying the post. The coefficient of thermal expansion (CTE) of the post may be configured to cooperate with the CTE of the dielectric layer to provide the non- tensile state, such as the dielectric layer having a CTE that is equal to or greater than a CTE of the post. The dielectric layer may have a CTE that is less than the CTE of the electrically conductive vertical interconnect, and may be arranged to provide a buffer to tensile forces imparted by the vertical interconnect.

Improvements in Coal Washing, and Apparatus therefor.

Revolving pipe joint

Vehicle wheel

Rotating light

Vehicle wheel

Compliant silicon substrates for heteroepitaxial growth by hydrogen-induced exfoliation

A method of fabricating a semiconductor device includes implanting dopants into a silicon substrate, and performing a thermal anneal process that activates the implanted dopants. In response to activating the implanted dopants, a layer of ultra-thin single-crystal silicon is formed in a portion of the silicon substrate. The method further includes performing a heteroepitaxy process to grow a semiconductor material from the layer of ultra-thin single-crystal silicon.

Design for a wheel

Compliant silicon substrates for heteroepitaxial growth by hydrogen-induced exfoliation

A method of fabricating a semiconductor device includes implanting dopants into a silicon substrate, and performing a thermal anneal process that activates the implanted dopants. In response to activating the implanted dopants, a layer of ultra-thin single-crystal silicon is formed in a portion of the silicon substrate. The method further includes performing a heteroepitaxy process to grow a semiconductor material from the layer of ultra-thin single-crystal silicon.

Hair styling device, attachment for a handle of a hair styling device, and method for straightening or curling hair using the hair styling device

A hair styling device comprises first and second arms 14, 16 coupled together at a first end and arranged to receive hair within a cavity 64 formed between the arms in the closed position. The first arm comprises a first plenum 38, said first plenum comprising a first air outlet 42 for emitting air towards hair within the cavity. The second arm comprises a first air inlet 60 for receiving air emitted from the first air outlet. The second arm preferably has a first exhaust 58 through which air can exit. In one embodiment the second arm has a second plenum 52 and a second outlet 56 for emitting air towards the cavity. Air from the second arm can be received by a second air inlet 46 on the first arm and is exhausted via a second exhaust 44 on the first arm. Hair may be wrapped around the device and heated by air exiting the first and second exhaust. The outer walls 36, 50 may be removably attached to the inner walls 18 of the first and second arms.

Hair styling device, attachment for a handle of a hair styling device, and method for straightening or curling hair using the hair styling device

A hair styling device is described. The hair styling device comprises a first arm and a second arm coupled together at a first end thereof. An inner wall of the first arm is facing an inner wall of the second arm. The first arm and the second arm are arranged to receive hair within a cavity formed between the first arm and the second arm. The first arm comprises a first plenum, said first plenum comprising a first air outlet for emitting air towards hair within the cavity. The second arm comprises a first air inlet for receiving air emitted from the first air outlet.