Vacuum cleaner hose cleaning brush

The subject invention pertains to a tool that may be used for cleaning hoses from vacuum cleaner machines. The tool comprises a brush or similar cleaning device attached to an end of a length a semi-rigid tube. In use, the cleaning tool is inserted into a vacuum cleaner hose after detachment of the hose from the vacuum cleaner; the inside surface of the hose is then cleaned of dust and other entrapped particles.

Device enabling two containers to be joined with each other and container having such a device

A device for joining a first face of a first container to a second face of a second container, in which the first face and the second face are alignable along a longitudinal axis, includes a plurality of hooks and a hook receiving portion. The plurality of hooks are spaced around a periphery of the first face of the first container. The hooks have tips and are movable in a direction parallel to the longitudinal axis. The hook receiving portion is disposed around a periphery of the second face of the second container. The hook receiving portion includes a groove shaped to receive the tips of the hooks so that the first container can be joined to the second container. As a result, the device permits two containers to be joined securely yet disassembled quickly.

Tube and hose cleaning brush

The subject invention pertains to a tool that may be used for cleaning the interior of tubing or hoses. The tool comprises a brush or similar cleaning device attached to an end of a length a semi-rigid tube. In use, the cleaning tool is inserted into a a tube or hose opening and the interior surface of the hose is then cleaned of dust and other entrapped particles.

Alignment control

A data processing system includes a stack pointer register storing a stack pointer value for use in stack access operations to a stack data store Stack alignment checking circuitry which is selectively disabled may be provided to check memory address alignment of the stack pointer value associated with a stack memory access. The action of the stack alignment checking circuitry is independent of any further other alignment checking performed in respect of all memory accesses. Thus, general alignment checking circuitry may be provided and independently selectively disabled in respect of any memory access. 1. Apparatus for processing data comprising:processing circuitry responsive to program instructions to perform data processing operations;a stack pointer register coupled to said processing circuitry and configured to store a stack pointer value indicative of an address within a memory of a stack data store;stack alignment checking circuitry coupled to said processing circuitry and to said stack pointer register and configured to respond to a program instruction specifying a memory access to said stack data store at an address specified by said stack pointer value to detect if said stack pointer value matches a predetermined stack alignment condition;alignment checking control circuitry coupled to said stack alignment checking circuitry and responsive to a stack configuration parameter to selectively disable said stack alignment checking circuitry independently of further alignment checking performed upon memory accesses.2. Apparatus as claimed in claim 1 , wherein said further alignment checking comprises alignment checking for all memory accesses.3. Apparatus as claimed in claim 1 , wherein said stack memory access is one of:(i) a stack push operation storing one or more data values to said stack memory starting at a top of stack address specified by said stack pointer value and updating said stack pointer value to indicate a new top of stack address; and(ii) a ...

Memory access control

A data processing system including processing circuitry operating in either a first mode or a second mode. Page table data including access control bits , is used to control permissions for memory access to memory pages. In the first mode, the access control bits include at least one instance of a redundant encoding. In the second mode, the redundant encoding is removed to provide more efficient use of the access control bit encoding space. 1. Apparatus for processing data comprising:processing circuitry responsive to program instructions to perform data processing operations and configured to operate in a plurality of modes; andmemory management circuitry coupled to said processing circuitry and to a memory and configured to control access permissions to data values stored within said memory in dependence upon page table data; whereinsaid memory has a memory address space divided in to a plurality of memory pages and said page table data comprises a plurality of access control bits for each of said plurality of memory pages defining access permissions for a respective memory page;when said processing circuitry is in a first of said plurality of modes using a predetermined number of access control bits to encode access permissions, said memory management circuitry is responsive to at least one instance of a redundant encoding in which a plurality of different combinations of said access control bits provides a same set of access permissions; andwhen said processing circuitry is in a second of said plurality of modes using said predetermined number of access control bits to encode access permissions, said memory management unit is responsive said plurality of different combinations of access control bits to provide a plurality of different sets of access permissions in a non-redundant encoding.2. Apparatus as claimed in claim 1 , wherein said plurality of different sets of access permissions include said same set of access permissions providing a set of access ...

Debugging of a data processing apparatus

A data processing apparatus is provided comprising processing circuitry and instruction decoding circuitry. The data processing apparatus is capable of operating at a plurality of different privilege. Processing circuitry of the data processing apparatus imposes on program instructions different access permissions to at least one of a memory and a set of registers at different ones of the different privilege levels. A debug privilege-level switching instruction is provided and decoding circuitry is responsive to this instruction to switch the processing circuitry from a current privilege level to a target privilege level if the processing circuitry is in a debug mode. However, if the processing circuitry is in a non-debug mode the instruction decoding circuitry prevents execution of the privilege-level switching instruction regardless of the current privilege level.

Data processing apparatus and method

A data processing apparatus comprises a processing circuit and instruction decoder . A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements src, src. Each result data element includes a portion corresponding to a bitfield bf of the corresponding first source data element src. Bits of the result data element that are more significant than the inserted bitfield bf have a prefix value p that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element src, and a third prefix value corresponding to a sign extension of the bitfield bf of the first source data element src 2. The data processing apparatus according to claim 1 , wherein said third prefix value comprises bits each having the bit value of bit of said corresponding first source data element.3. The data processing apparatus according to claim 1 , wherein if B>0 claim 1 , then each result data element further comprises bits having bit values corresponding to a suffix value selected claim 1 , in dependence on said control value claim 1 , as one of (i) a first suffix value comprising bits each having a zero value claim 1 , and (ii) a second suffix value having the bit values of bits of said corresponding second source data element.4. The data processing apparatus according to claim 1 , comprising a plurality of storage locations configured to store data values for processing by said processing circuitry;wherein said bitfield manipulation instruction identifies at least a first source storage location for storing said first source data value, and a destination storage location; andsaid instruction decoder is responsive to said bitfield manipulation instruction to generate control signals for controlling said processing ...

Multiple Cycle Memory Write Completion

A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner. 1. A method of operating a memory system having a plurality of memory banks comprising:performing an incomplete write operation of a first data value to a first address location in a first memory bank during a first memory cycle, wherein the incomplete write operation fails to pull a storage node of a memory cell at the first address location all the way to a first voltage associated with a first data state; andperforming a write operation of the first data value to a first address location in a cache memory during the first memory cycle.2. The method of claim 1 , further comprising:determining that there are no required accesses to the first memory bank during a second memory cycle; andretrieving the first data value from the cache memory and writing this retrieved first data value to the first address location in the first memory bank during the second memory cycle.3. The method of claim 2 , further comprisingperforming an incomplete write operation of a second data value to a second address location in a second memory bank during a second memory cycle; andperforming a write operation of the second data ...

System and method for delivering a stent to a bifurcated vessel

A stent delivery catheter system for accurately positioning a stent in a bifurcated vessel is disclosed. The system includes a catheter having a terminal portion and distal tip that is placed in a main branch of the vessel proximate the bifurcation. A fixed guidewire is attached to distal tip. A port is defined in the terminal portion of the catheter. The port is aligned with an ostium of a side branch of the bifurcated vessel to allow the passage of a stent delivery device, such as a balloon catheter having a stent crimped thereon, into the side branch. Radiopaque bands are positioned on opposite ends of the port. A positioning balloon is included on a surface of the catheter opposite the port and is selectively inflatable to position the radiopaque bands adjacent the side branch ostium. The radiopaque bands are referenced to place the stent proximate the side branch ostium.

DIAGNOSING CODE USING SINGLE STEP EXECUTION

A method and apparatus for controlling a processor to execute in a single step mode such that a single instruction from the instruction stream is executed, the processor determines if the single instruction is one of at least one predetermined type of instruction and stores a type indicator in a data storage location and a diagnostic exception is taken after the processor has processed the single instruction. Additionally, a diagnostic operation is performed including accessing the type indicator stored in the data storage location and, when the single instruction was not one of the predetermined type, controlling the processor to continue executing instructions in the single step mode, and, when the single instruction was one of the at least one predetermined type, controlling the processor to exit the single step mode and not execute the next instruction within the instruction stream as a single instruction followed by an exception. 1. A method for diagnosing a processor processing a stream of instructions comprising:(i) controlling said processor to execute in a single step mode such that a single instruction from said instruction stream is executed, said processor determines if said single instruction is one of at least one predetermined type of instruction and stores a type indicator in a data storage location and a diagnostic exception is taken after said processor has processed said single instruction; 'accessing said type indicator stored in said data storage location; and', '(ii) performing diagnostic operations following said diagnostic exception including(iiia) in response to said type indicator indicating said single instruction was not one of said predetermined type controlling said processor to continue executing instructions in said single step mode such that a next single instruction is executed on return form said diagnostic exception;(iiib) in response to said type indicator indicating said single instruction was one of said at least one ...

Separate Pass Gate Controlled Sense Amplifier

A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated.

Methods For Accessing DRAM Cells Using Separate Bit Line Control

A memory system that includes a first bit line coupled to a first set of dynamic random access memory (DRAM) cells, a second (complementary) bit line coupled to a second set of DRAM cells, and a sense amplifier coupled to the first and second bit lines. The sense amplifier includes a pair of cross-coupled inverters (or a similar latching circuit) coupled between the first and second bit lines, as well as a first select transistor coupling the first bit line to a first global bit line, and a second select transistor coupling the second bit line to a second global bit line. The first and second select transistors are independently controlled, thereby enabling improved read and write access sequences to be implemented, whereby signal loss associated with bit line coupling is eliminated, ‘read bump’ conditions are eliminated, and late write conditions are eliminated. 1. A method of accessing a dynamic random access memory (DRAM) cell comprising:driving a first bit line and a second bit line to a pre-charge voltage; thenceasing to drive the first bit line to the pre-charge voltage, and enabling a DRAM cell coupled to the first bit line, thereby developing a read voltage on the first bit line;continuing to drive the second bit line to the pre-charge voltage while the read voltage is developing on the first bit line; and thenceasing to drive the second bit line to the pre-charge voltage, and enabling a sense amplifier coupled to the first and second bit lines, whereby the sense amplifier drives the first bit line to a first supply voltage and the second bit line to a second supply voltage in response to the read voltage on the first bit line.2. The method of claim 1 , wherein the step of driving the first and second bit lines to the pre-charge voltage comprises:driving a first global bit line and a second global bit line to the pre-charge voltage;electrically connecting the first global bit line to the first bit line; andelectrically connecting the second global bit line ...

Apparatus and Method for Exercising a User's Muscles

The invention is directed to an apparatus for exercising a user's muscles that includes a frame. A platform is attached to the frame, which defines an area on which a user stands. A weight stack is attached to the frame. A lineal shaft is attached to the frame between the platform and the weight stack. A carriage runs on the lineal shaft and is attached to the weight stack by a cable. An extension arm is pivotally connected to the carriage. A handle is attached to the extension arm. The lineal shaft and platform allow the user to adjust the machine to their body by just standing in the position that fits their body. The lineal shaft, carriage, and pivotal connected extension arm provides a resistance curve that fits the user's strength curve. 1. An apparatus for exercising a user's muscles , comprising:a frame;a platform attached to the frame defining an area on which a user stands;a weight stack attached to the frame;a lineal shaft attached to the frame between the platform and the weight stack;a carriage running on the lineal shaft and attached to the weight stack by a cable;an extension arm pivotally connected to the carriage; anda handle attached to the extension arm.2. The apparatus of claim 1 , wherein the lineal shaft is essentially vertical.3. The apparatus of claim 3 , wherein the lineal shaft is canted at an angle.4. The apparatus of claim 1 , wherein the lineal shaft slopes away from the platform and essentially extends along the center longitudinal axis of the apparatus.5. The apparatus of claim 1 , further including a rubber dampener between the lineal shaft and the frame.6. The apparatus of claim 1 , wherein the platform is roughly triangular.7. An apparatus for exercising a user's muscles comprising:a frame;a weight stack attached to the frame;a lineal shaft attached to the frame;a carriage traveling on the lineal shaft attached to the weight stack by a cable; andan extension arm pivotally attached to the carriage.8. The apparatus of claim 7 , further ...

Integrated circuit package with segregated tx and rx data channels

A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.

CRYPTOGRAPHIC SUPPORT INSTRUCTIONS

A data processing system includes a single instruction multiple data register file and single instruction multiple processing circuitry . The single instruction multiple data processing circuitry supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file . The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand. 1. Data processing apparatus comprising:a single instruction multiple data register file; andsingle instruction multiple data processing circuitry coupled to said single instruction multiple data register file and configured to be controlled by a single instruction multiple data program instruction to perform a processing operation independently upon separate data elements stored within separate lanes within an input operand register of said single instruction multiple data register file; whereinsaid single instruction multiple data processing circuitry is configured to be controlled by a further program instruction to perform a further processing operation upon a vector data value comprising a sequence of data elements held within an input operand register of said single instruction multiple data register file to produce an output operand stored within and an output operand register of said single instruction multiple data register file, said output operand having a first portion with a value dependent upon all data elements within said sequence of data elements.2. Data processing apparatus as claimed in claim 1 , wherein said further program instruction is a cryptographic program instruction that operates to generate an output hash value as said output operand in dependence upon a plurality of words of data forming said vector data value.3. Data processing ...

DATA PROCESSING APPARATUS AND METHOD FOR PROTECTING SECURE DATA AND PROGRAM CODE FROM NON-SECURE ACCESS WHEN SWITCHING BETWEEN SECURE AND LESS SECURE DOMAINS

A data processing apparatus includes processing circuitry and a data store including a plurality of regions including a secure region and a less secure region. The secure region is configured to store sensitive data accessible by the circuitry when operating in a secure domain and not accessible by the circuitry when operating in a less secure domain. The data store includes a plurality of stacks with a secure stack in the secure region. Stack access circuitry is configured to store predetermined processing state to the secure stack. The processing circuitry further comprises fault checking circuitry configured to identify a first fault condition if the data stored in the predetermined relative location is the first value. This provides protection against attacks from the less secure domain, for example performing a function call return from an exception, or an exception return from a function call. 1. A data processing apparatus , said data processing apparatus comprising:processing circuitry configured to perform data processing operations in response to program code;a data store configured to store data, said data store comprising a plurality of regions including a secure region and a less secure region, the secure region configured to store sensitive data accessible by said processing circuitry when operating in a secure domain and not accessible by said processing circuitry when operating in a less secure domain;said data store comprising a plurality of stacks, including a secure stack in said secure region;the processing circuitry including stack access circuitry configured in response to an event requiring a transition from the secure domain to the less secure domain, to store predetermined processing state to the secure stack;if said event is a first event type, the predetermined processing state stored by the stack access circuitry comprising at least a return address which is stored at a predetermined relative location on the secure stack;if the event is a ...

MAINTAINING SECURE DATA ISOLATED FROM NON-SECURE ACCESS WHEN SWITCHING BETWEEN DOMAINS

A data processing apparatus including circuitry for performing data processing, a plurality of registers; and a data store including regions having different secure levels, at least one secure region (for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in a less secure domain) and a less secure region (for storing less secure data). The circuitry is configured to determine which stack to store data to, or load data from, in response to the storage location of the program code being executed. In response to program code calling a function to be executed, the function code being stored in a second region, the second region having a different secure level to the first region, the data processing circuitry is configured to determine which of the first and second region have a lower secure level. 1. A data processing apparatus , said data processing apparatus comprising:data processing circuitry for performing data processing operations in response to program code;a plurality of registers; anda data store for storing data, said data store comprising a plurality of regions each region having a secure level, and comprising at least one secure region for storing sensitive data accessible by said data processing circuitry operating in said secure domain and not accessible by said data processing circuitry operating in a less secure domain and a less secure region for storing less secure data;said data store comprising at least two stacks a secure stack in said secure region and a less secure stack in said less secure region; said data processing circuitry operating in said secure domain when processing program code stored in said secure region and operating in said less secure domain when processing program code stored in said less secure region; whereinsaid data processing circuitry is configured to determine which stack to store data to, or load data from, in ...

DATA PROCESSING APPARATUS AND METHOD USING SECURE DOMAIN AND LESS SECURE DOMAIN

A data processing apparatus has processing circuitry which has a secure domain and a less secure domain of operation. When operating in the secure domain the processing circuitry has access to data that is not accessible in the less secure domain. In response to a control flow altering instruction, processing switches to a program instruction at a target address. Domain selection is performed to determine a selected domain in which the processing circuitry is to operate for the instruction at the target address. Domain checking can be performed to check which domains are allowed to be the selected domain determining the domain selection. A domain check error is triggered if the selected domain in the domain selection is not an allowed selected domain. 2. The data processing apparatus according to claim 1 , wherein the control flow altering instruction comprises a branch instruction.3. The data processing apparatus according to claim 1 , wherein if the control flow altering instruction is executed while operating in the less secure domain claim 1 , the processing circuitry is also configured to perform the domain checking and trigger the domain check error if the selected domain determined in the domain selection does not match an allowed domain determined in the domain checking.4. The data processing apparatus according to claim 1 , wherein one of the domain selection and the domain checking comprises first determining and the other of the domain selection and the domain checking comprises second determining.5. The data processing apparatus according to claim 4 , comprising a data store for storing data claim 4 , the data store comprising a plurality of regions including a secure region and a less secure region claim 4 , wherein the secure region is for storing data which is accessible by the processing circuitry when operating in the secure domain and not accessible by the processing circuitry when operating in the less secure domain;wherein the first determining ...

EXCEPTION HANDLING IN A DATA PROCESSING APPARATUS HAVING A SECURE DOMAIN AND A LESS SECURE DOMAIN

A data processing apparatus and method are provided for handling exceptions, including processing circuitry configured to perform data processing operations in response to program code, said circuitry including exception control circuitry. A plurality of registers are provided including a first and second subsets of registers, and a data store. The data store includes a secure region and a less secure region, wherein the secure region is for storing data accessible by the processing circuitry when operating in a secure domain and not accessible by the processing circuitry when operating in a less secure domain. The exception control circuitry performs state saving of data from the first subset of registers before triggering the processing circuitry to perform an exception handling routine corresponding to the exception. Where background processing was performed by the processing circuitry in the secure domain, the exception control circuitry performs additional state saving of the data. 1. A data processing apparatus comprising:processing circuitry configured to perform data processing operations in response to program code, the processing circuitry comprising exception control circuitry for controlling exception processing;a plurality of registers configured to store data, the registers including a first subset of registers and a second subset of registers; anda data store configured to store data, the data store comprising a plurality of regions including a secure region and a less secure region, wherein the secure region is for storing data which is accessible by the processing circuitry when operating in a secure domain and not accessible by the processing circuitry when operating in a less secure domain; wherein:in response to an initial exception from background processing performed by the processing circuitry, the exception control circuitry is configured to perform state saving of data from the first subset of registers before triggering the processing ...

Semiconductor chip layout with staggered tx and tx data liness

A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.

Hierarchical Multi-Bank Multi-Port Memory Organization

A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead. 1. A memory system comprising:a first plurality of ports, including one or more read ports and one or more write ports, wherein each of the first plurality of ports includes a corresponding address bus; and wherein each access control circuit is coupled to the address buses of the first plurality of ports,', in response to these received addresses,', 'determines whether any of the first plurality of ports address the corresponding memory bank, and', 'initiates a read operation to the corresponding array of single port memory cells in response to determining that one of the one or more read ports addresses the corresponding memory bank, and', 'initiates a write operation to the corresponding array of single port memory cells in response to determining that one of the one or more write ports addresses the corresponding memory bank., 'wherein each access control circuit is coupled to receive addresses provided on each of the address busses, and'}], 'a first plurality of memory banks, each including a corresponding array of single port memory cells and a ...

SUB-CALIBER PROJECTILE WITH A FITTED HEAD STRUCTURE

An arrow-type sub-caliber projectile has a piercing bar extended by a conical portion, and is surrounded by a sabot made of a lightweight material and allows the firing of the projectile in a weapon. This conical portion has a tip of a heating-resistant material with a diameter less than half the diameter of the bar, the tip being connected to the bar by a support structure having no ballistic effects, the bar having a flat front face substantially to the diameter of the bar. 1. An arrow-type sub-caliber projectile comprising a piercing bar extended by a conical portion , and surrounded by a sabot made of a lightweight material and allowing the firing of the projectile in a weapon , the projectile being that the conical portion comprises a tip of a heating-resistant material with a diameter less than half the diameter of the bar , the tip being connected to the bar by a support structure having no ballistic effects , the bar comprising a flat front face substantially to the diameter of the bar.2. The sub-caliber projectile according to claim 1 , wherein the support structure comprises a block made of a plastic or ceramic material.3. The sub-caliber projectile according to claim 1 , wherein the support structure comprises an aluminum conical tubular sleeve.4. The sub-caliber projectile according to claim 1 , wherein the support structure comprises a foot connecting the tip to a middle portion of the front face of the bar claim 1 , the foot having a diameter less than a quarter of the diameter of the bar.5. The sub-caliber projectile according to claim 4 , wherein the foot is surrounded by a tube of a plastic or ceramic material. Applicant claims priority under 35 U.S.C. 119 of French patent application no. 12-00677 filed on Jun. 3, 2012.Not ApplicableNot ApplicableNot Applicable1. Field of the InventionThe technical field of the invention is that of sub-caliber projectiles and in particular of armor-piercing discarding sabot-type sub-caliber projectiles of a large ...

BARRIER TRANSACTIONS IN INTERCONNECTS

Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained. 1. Interconnect circuitry for a data processing apparatus , said interconnect circuitry being configured to provide data routes via which at least one initiator device may access at least one recipient device , said interconnect circuitry comprising:at least one input for receiving transaction requests from said at least one initiator device;at least one output for outputting transaction requests to said at least one recipient device;at least one path for transmitting said transaction requests between said at least one input and said at least one output;control circuitry for routing said received transaction requests from said at least one input to said at least one output; whereinsaid control circuitry, in response to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, is configured to not allow reordering of at least some transactions requests that occur before said ...

TRANSLATION TABLE CONTROL

Memory address translation circuitry 14 performs a top down page table walk operation to translate a virtual memory address VA to a physical memory address PA using translation data stored in a hierarchy of translation tables A page size variable S is used to control the memory address translation circuitry to operate with different sizes S of pages of physical memory addresses, pages of virtual memory address and translation tables. These different sizes may be all 4 kBs or all 64 kBs. The system may support multiple virtual machine execution environments. These virtual machine execution environments can independently set their own page size variable as can the page size of an associated hypervisor 1. Apparatus for processing data comprising:memory address translation circuitry configured to perform a top down page table walk operation to translate a virtual memory address to a physical memory address using translation data stored in a hierarchy of translation tables; wherein{'sup': N', 'N, 'said translation data specifies translations between pages of 2contiguous bytes of virtual memory addresses and corresponding pages of 2contiguous bytes of physical memory addresses, where N is a positive integer;'}{'sup': 'N', 'said hierarchy of translation tables comprises translation tables of 2contiguous bytes in size such that a complete translation table is stored within one page of said physical memory; and'}said memory address translation circuitry is responsive to a page size variable specifying a current value of N to control said memory address translation circuitry to operate with a selected size of pages of physical memory addresses, pages of virtual memory addresses and translation tables.2. Apparatus as claimed in claim 1 , comprising a processor configured to execute program instructions providing a plurality of virtual machine execution environments claim 1 , said page size variable for each of said plurality of virtual machine execution environments being ...

STORE-EXCLUSIVE INSTRUCTION CONFLICT RESOLUTION

A data processing system includes a plurality of transaction masters () each with an associated local cache memory () and coupled to coherent interconnect circuitry (). Monitoring circuitry () within the coherent interconnect circuitry () maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing. 120.-. (canceled)21. A method managing data coherency within a data processing apparatus having a plurality of transaction masters connected via a coherent interconnect and including a subject transaction master , said method comprising performing in respect of each of said plurality of transaction masters serving as a subject transaction master the steps of:setting a subject state variable and a subject control value to match so as to indicate an exclusive store access state to subject data within a subject cache memory coupled to said subject transaction master; and comparing a store address of a store data value associated with said store-exclusive instruction with addresses of data values stored within said subject cache memory to determine if said store data value is currently stored within said target cache memory and is valid;', 'if said stored data value is not marked as valid within said subject cache memory, then marking as failed execution of said store-exclusive instruction; and', (i) comparing a current ...

PROJECTILE WITH STEERABLE FINS AND CONTROL METHOD OF THE FINS OF SUCH A PROJECTILE

The invention relates to a steering method of a projectile and to the associated projectile with incidence steerable fins, comprising at least three fins, each being pivotable with respect to the projectile around a pivot axis perpendicular to the longitudinal axis X of the projectile, wherein the projectile comprises a fin orientation ring, the ring comprising as many arms as there are fins, wherein the ring can translate in a plan P perpendicular to the longitudinal axis X of the projectile and following at least two directions of this plan P, wherein the orientation ring can rotate on itself around its centre parallel to the longitudinal axis X of the projectile, each arm comprising means cooperating with an orientation lever fixed to a fin to be able to pivot the fin around its pivot axis during translation of the ring by positioning means. 1- A projectile with incidence steerable fins comprising at least three fins , each incidence steerable fin being rotatable with respect to the projectile around a pivot axis perpendicular to the longitudinal axis X of the projectile , wherein the projectile comprises a fin orientation ring , the ring comprising as many arms as there are fins , wherein the ring can translate in a plan P perpendicular to the longitudinal axis X of the projectile and following at least two directions of this plan P , wherein the orientation ring can rotate on itself around the centre of the orientation ring parallel to the longitudinal axis X of the projectile , each arm comprising means cooperating with an orientation lever fixed to a fin to be able to cause a rotation of the fin around the rotation axis of the fin during movement of the ring , the translation of the ring being ensured by positioning means of the centre of the ring in the plan P with respect to an absolute frame centered on the longitudinal axis of the projectile.2- The projectile with incidence steerable fins according to claim 1 , wherein the positioning means comprises a ...

TRANSACTIONAL MEMORY SUPPORT

An asymmetric multiprocessor system () includes a plurality of processor cores () supporting transactional memory via controllers () as well as one or more processor cores which do not support transactional memory via hardware. The controllers respond to receipt of a request for exclusive access to a lock address by determining whether or not their associated processing element is currently executing a memory transaction guarded by a lock value stored at that lock address and if their processing element is executing such a transaction, then delaying releasing the lock address for exclusive access until a predetermined condition is met. If the processing element is not executing such a guarded memory transaction, then the lock address may be unconditionally released for exclusive access. The predetermined condition may be that a threshold delay has been exceeded since the request was received and/or that the request has previously been received and refused a threshold number of times. The request may arise through execution of a transaction start instruction which serves to read a lock address from an architectural register () storing the lock address should the processor executing that transaction start instruction not already be executing a pending memory transaction. If the processor is already executing a memory transaction, then the transaction start instruction need not access the lock value stored at the lock address held within the lock address register () as it may be assumed that the lock value has already been checked. 1. Apparatus for processing data and including hardware support for atomic memory transactions , said apparatus comprising:a plurality of processing elements each configured to execute a sequence of program instructions; anda memory configured to store data values shared by said plurality of processing elements; (i) when said transactional-memory-supporting processing element is executing a memory transaction guarded by said lock address, ...

DATA PROCESSING APPARATUS AND METHOD

A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element. 1. A data processing apparatus comprising:processing circuitry configured to perform processing operations;an instruction decoder responsive to program instructions to generate control signals for controlling said processing circuitry to perform said processing operations; wherein:said program instructions include at least one instruction specifying a control value having a first portion for indicating a selected data size selected from a plurality of data sizes and a second portion for indicating at least one control parameter having a number of bits that varies in dependence on said selected data size, said first portion and said second portion each having a variable number of bits; andsaid instruction decoder is responsive to said at least one instruction to generate control signals for controlling said processing circuitry to perform a corresponding processing operation in dependence on said selected data size and said at least one control parameter;wherein when processing said at least one instruction, at least one of said instruction decoder and said processing circuitry is configured to identify the number of bits comprised by said first portion of said ...

MAINTAINING SECURE DATA ISOLATED FROM NON-SECURE ACCESS WHEN SWITCHING BETWEEN DOMAINS

A data processing apparatus including circuitry for performing data processing, a plurality of registers; and a data store including regions having different secure levels, at least one secure region (for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in a less secure domain) and a less secure region (for storing less secure data). The circuitry is configured to determine which stack to store data to, or load data from, in response to the storage location of the program code being executed. In response to program code calling a function to be executed, the function code being stored in a second region, the second region having a different secure level to the first region, the data processing circuitry is configured to determine which of the first and second region have a lower secure level. 1. A data processing apparatus comprising:processing circuitry configured to execute a stack select flag set instruction specifying a register and, in response to said select flag set instruction, to determine whether a target address that is stored in said register is in a less secure region of a data store than a current operating region, and when said target address is determined to be in said less secure region to set a stack select flag to indicate said less secure region.2. The data processing apparatus according to claim 1 , wherein said processing circuitry is configured to set the stack select flag to indicate the current operating region when said target address is determined to be in said current operating region.3. The data processing apparatus according to claim 1 , wherein the processing circuitry is configured to determine which of a plurality of stacks stored in the data store to use for accessing function arguments and function return data values in dependence on the stack select flag.4. The data processing apparatus according to claim 1 , comprising a ...

CRYPTOGRAPHIC SUPPORT INSTRUCTIONS

A data processing system includes a single instruction multiple data register file and single instruction multiple processing circuitry. The single instruction multiple data processing circuitry supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand. 1. Data processing apparatus comprising:a single instruction multiple data register file; andsingle instruction multiple data processing circuitry coupled to said single instruction multiple data register file and configured to be controlled by a single instruction multiple data program instruction to perform a processing operation independently upon separate data elements stored within separate lanes within an input operand register of said single instruction multiple data register file; whereinsaid single instruction multiple data processing circuitry is configured to be controlled by a first further program instruction and a second further program instruction to perform a further processing operation upon an input digest data value to generate an output digest data value, the first further program instruction being operable to generate a first output operand representative of a first portion of the output digest data value, the second further program instruction being operable to generate a second output operand representative of a remaining portion of the output digest data value, andwherein the input digest data value comprises a sequence of data elements held within said single instruction multiple data register file, said first portion and said second portion of the output digest data value being dependent upon all data elements within said sequence of data ...

DRAM-TYPE DEVICE WITH LOW VARIATION TRANSISTOR PERIPHERAL CIRCUITS, AND RELATED METHODS

A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from power supply voltages of the DRAM; and peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits comprising deeply depleted channel (DDC) transistors having bodies coupled to receive the body bias voltage, each DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region. 1. A dynamic random access memory (DRAM) , comprising:at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor;a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from a power supply voltage of the DRAM; and{'sup': 18', '3, 'peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits having at least one deeply depleted channel (DDC) transistor having a body coupled to receive the body bias voltage, the DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region, the screening region having a dopant concentration that is no less than 1×10dopant atoms/cmand that is different from a dopant concentration of a substrate portion or well containing the DDC transistor.'}2. The DRAM of claim 1 , wherein:the peripheral circuits comprise first DDC transistors and second DDC transistors of a same conductivity type, the first DDC transistors having a different threshold voltage than the second DDC transistors.3. The DRAM of claim 1 , wherein:the peripheral circuits comprises a sense amplifier circuit coupled to the DRAM cell array, and ...

APPARATUS AND METHOD FOR CONTROLLING USE OF BOUNDED POINTERS

An apparatus and method are provided for controlling use of bounded pointers. The apparatus includes storage to store bounded pointers, where each bounded pointer comprises a pointer value and associated attributes, with the associated attributes including range information indicative of an allowable range of addresses when using the pointer value. Processing circuitry is used to perform a signing operation on an input bounded pointer in order to generate an output bounded pointer in which a signature generated by the signing operation is contained within the output bounded pointer in place of specified bits of the input bounded pointer. In addition, the associated attributes include signing information which is set by the processing circuitry within the output bounded pointer to identify that the output bounded pointer has been signed. Such an approach provides increase resilience to control flow integrity attack when using bounded pointers. 1. An apparatus , comprising:storage to store bounded pointers, each bounded pointer comprising a pointer value and associated attributes, the associated attributes including range information indicative of an allowable range of addresses when using said pointer value; andprocessing circuitry to perform a signing operation on an input bounded pointer in order to generate an output bounded pointer in which a signature generated by the signing operation is contained within the output bounded pointer in place of specified bits of the input bounded pointer;the associated attributes including signing information which is set by the processing circuitry within the output bounded pointer to identify that the output bounded pointer has been signed.2. An apparatus as claimed in claim 1 , wherein the processing circuitry is arranged claim 1 , for at least one requested operation requiring use of a bounded pointer within the storage claim 1 , to determine from the signing information within the associated attributes whether that bounded ...

Puming system

A pump unit which includes a pipe, a flexible bladder inside the pipe, an operating volume between an outer surface of the bladder and an opposing inner surface of the pipe, a valve arrangement to introduce pressurised water into the operating volume and to allow pressurised water to flow from the operating volume and another valve arrangement to allow slurry to flow into the interior of the bladder as water is expelled from the operating volume and to—allow slurry to flow from the bladder when water is introduced into the operating volume.

COMMUNICATION OF MESSAGE SIGNALLED INTERRUPTS

A global interrupt number space is provided for use in message signalled interrupts. Interrupt destinations are provided with pending interrupt caches with either backing storage provided by global pending status memory shared by all the caches or separate individual pending status memories . The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination. 1. Interrupt communication apparatus for communicating message signalled interrupts between one or more interrupt sources and a plurality of interrupt destinations , said apparatus comprising:interrupt translation circuitry configured to receive a message signalled interrupt from one of said one or more interrupt sources and to trigger storage of pending status data with an associated storage location within pending status data storage circuitry, said storage location representing an interrupt number of said message signalled interrupt within a global interrupt number space shared by said plurality of interrupt destinations; anda plurality of interrupt data reading circuits each associated with a respective one of said plurality of interrupt destinations and configured to read pending status data with an associated interrupt number within said global interrupt number space from said pending status data storage circuitry and to trigger interrupt processing by said respective one of said plurality of interrupt destination.2. Interrupt communication apparatus as claimed in claim 1 , wherein said pending status data storage circuitry includes a plurality of pending interrupt caches each ...

APPARATUS AND METHOD FOR HANDLING EXCEPTION EVENTS

Processing circuitry has a plurality of exception states EL0-EL3 for handling exception events, the exception states including a base level exception state EL0 and at least one further level exception state EL1-EL3. Each exception state has a corresponding stack pointer indicating the location within the memory of a corresponding stack data store . When the processing circuitry is in the base level exception state EL0, stack pointer selection circuitry selects the base level stack pointer as a current stack pointer indicating a current stack data store for use by the processing circuitry . When the processing circuitry is a further exception state, the stack pointer selection circuitry selects either the base level stack pointer or the further level stack pointer corresponding to the current further level exception state as a current stack pointer. 1. A data processing apparatus comprising:processing circuitry configured to process data in one of a plurality of exception states including a base level exception state and at least one further level exception state;a base level stack pointer register for storing a base level stack pointer indicating the location within a memory of a base level stack data store;at least one further level stack pointer register for storing at least one further level stack pointer indicating the location within said memory of at least one further level stack data store, the at least one further level exception state each having a corresponding further level stack pointer; wherein:when processing data in a current further level exception state, said processing circuitry is configured to use a current stack data store indicated by a current stack pointer;said data processing apparatus comprises a stack pointer selection register configured to store a stack pointer selection value controlling whether the current stack pointer is the base level stack pointer or a current further level stack pointer corresponding to said current further level ...

SEMICONDUCTOR DEVICE INCLUDING THRESHOLD VOLTAGE MEASUREMENT CIRCUITRY

A semiconductor device may include a substrate, active circuitry on the substrate and including differential transistor pairs, and threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors may each include spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Each of the channel regions may include a superlattice. 1. A semiconductor device comprising:a substrate;active circuitry on the substrate and comprising a plurality of differential transistor pairs; and a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, each test transistor having a respective input and output, and', 'at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof;, 'threshold voltage test circuitry on the substrate and comprising'}wherein the plurality of differential transistor pairs and the pair of differential test transistors each comprises spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region;wherein each of the channel regions comprises a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon ...

METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING THRESHOLD VOLTAGE MEASUREMENT CIRCUITRY

A method for making a semiconductor device may include forming active circuitry on a substrate including differential transistor pairs, and forming threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors each includes spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Moreover, each of the channel regions may include a superlattice. 1. A method for making a semiconductor device comprising:forming active circuitry on a substrate and comprising a plurality of differential transistor pairs; and a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, each test transistor having a respective input and output, and', 'at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof;, 'forming threshold voltage test circuitry on the substrate and comprising'}wherein the plurality of differential transistor pairs and the pair of differential test transistors each comprises spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region;wherein each of the channel regions comprises a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at ...

SPECULATIVE CACHE STORAGE REGION

An apparatus () comprises processing circuitry () to perform speculative execution of instructions; a main cache storage region (); a speculative cache storage region (); and cache control circuitry () to allocate an entry, for which allocation is caused by a speculative memory access triggered by the processing circuitry, to the speculative cache storage region instead of the main cache storage region while the speculative memory access remains speculative. This can help protect against potential security attacks which exploit cache timing side-channels to gain information about allocations into the cache caused by speculative memory accesses. 1. An apparatus comprising:processing circuitry to perform speculative execution of instructions;a main cache storage region;a speculative cache storage region; andcache control circuitry to allocate an entry, for which allocation is caused by a speculative memory access triggered by the processing circuitry, to the speculative cache storage region instead of the main cache storage region while the speculative memory access remains speculative, in which:when the speculative memory access which triggered allocation of the entry to the speculative cache storage region is a speculative load memory access for loading data from a memory system, the entry allocated to the speculative cache storage region in response to the speculative load memory access specifies the data loaded from the memory system.2. The apparatus of claim 1 , in which the cache control circuitry is configured to exclusively allocate to the main cache storage region entries corresponding to non-speculative memory accesses or speculative memory accesses which have been resolved as correct.3. The apparatus of claim 1 , in which both the main cache storage region and the speculative cache storage region are accessible in response to reads triggered by speculative instructions executed by the processing circuitry.4. The apparatus of claim 3 , in which in response ...

DATA PROCESSING APPARATUS AND METHOD FOR PROTECTING SECURE DATA AND PROGRAM CODE FROM NON-SECURE ACCESS WHEN SWITCHING BETWEEN SECURE AND LESS SECURE DOMAINS

A data processing apparatus includes processing circuitry and a data store including a plurality of regions including a secure region and a less secure region. The secure region is configured to store sensitive data accessible by the circuitry when operating in a secure domain and not accessible by the circuitry when operating in a less secure domain. The data store includes a plurality of stacks with a secure stack in the secure region. Stack access circuitry is configured to store predetermined processing state to the secure stack. The processing circuitry further comprises fault checking circuitry configured to identify a first fault condition if the data stored in the predetermined relative location is the first value. This provides protection against attacks from the less secure domain, for example performing a function call return from an exception, or an exception return from a function call. 1. A data processing apparatus comprising:processing circuitry to perform data processing operations, the processing circuitry being operable in a secure domain and a less secure domain;a stack pointer register to store a stack pointer value;stack access circuitry to, in response to an event requiring a transition from the secure domain to the less secure domain, store a data item to a data store at a given location determined relative to the stack pointer value, the data item comprising a return address when said event is of a first event type, and comprising a first value when said event is of a second event type; andfault checking circuitry configured, on receipt of a first event type return from the less secure domain, to identify a fault condition if the data item stored at the given location comprises the first value,wherein one of the first event type and the second event type comprises a function call, and the other of said first event type and the second event type comprises an exception.2. A data processing apparatus as claimed in claim 1 , wherein said first ...

Dynamic content aggregation

Methods, systems, and devices for dynamically aggregating content, especially digital content, are described. These include tools and techniques for automatically creating a unique package that tells a user-specific story about memorable life events. Electronic media files such as photographs, videos, and the like, of a user may be captured and linked to a unique identifier. The electronic media files may be transmitted to a central server where they may be aggregated and utilized to generate a multimedia file for user. The multimedia file may include electronic media files captured at disparate locations and times, and it may include stock content, user-generated content, third-party content, and the like. Users may access archived stories (e.g., multimedia files) in a virtual bookshelf Third-parties may be compensated for their content that is provided to a user.

BRANCH INSTRUCTION

A data processing system provides a branch forward instruction (BF) which has programmable parameters specifying a branch target address to be branched to and a branch point identifying a program instruction following the branch forward instruction which, when reached, is followed by a branch to the branch target address. 1. Apparatus for processing data comprising:processing circuitry to perform processing operations specified by a sequence of program instructions;an instruction decoder to decode said sequence of program instructions to generate control signals to control said processing circuitry to perform said processing operations; whereinsaid instruction decoder comprises branch-future instruction decoding circuitry to decode a branch-future instruction, said branch-future instruction having a programmable parameter associated with a branch target address and further programmable branch point data parameter indicative of a predetermined instruction following said branch-future instruction within said sequence of program instructions; andsaid processing circuitry comprises branch control circuitry controlled by said branch-future instruction decoding circuitry and responsive to said branch point data to trigger a branch to processing of program instructions starting from a branch target instruction corresponding to said branch target address when processing of said sequence of program instructions reaches said predetermined instruction.2. Apparatus as claimed in claim 1 , whereinwhen said branch control circuitry triggers said branch, said branch target instruction follows an instruction immediately preceding said predetermined instruction in said sequence of program instructions, and an operation specified by said branch-future instruction and an operation specified by said instruction immediately preceding said predetermined instruction are performed contiguously by said processing circuitry.3. Apparatus as claimed in claim 1 , wherein claim 1 , said branch ...

APPARATUS AND METHOD FOR MAPPING ARCHITECTURAL REGISTERS TO PHYSICAL REGISTERS

An apparatus and method are provided for performing register renaming. Available register identifying circuitry is provided to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration data whose value is modified during operation of the processing circuitry is stored such that, when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry. The register identifying circuitry is arranged to reference the modified data value, such that when the configuration data has the first value, the number of physical registers in the pool is increased due to the reduction in the number of architectural registers which require mapping to physical registers. 1. Apparatus for processing data , comprising:a set of physical registers for storing data;processing circuitry configured to execute instructions of an instruction set, the processing circuitry requiring access to said data when executing said instructions;register renaming circuitry configured to map from architectural registers of a set of architectural registers to physical registers of said set of physical registers, said set of architectural registers being registers as specified by said instructions and said set of physical registers being physical registers for use when executing said instructions;available register identifying circuitry, responsive to a current state of said apparatus, configured to identify which physical registers of said set of physical registers form a pool of physical registers available to be mapped by said register renaming circuitry to an architectural register specified by an instruction to be executed; andconfiguration storage configured to store configuration data ...

MEMORY INTERFACE HAVING DATA SIGNAL PATH AND TAG SIGNAL PATH

A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer. 1. An apparatus comprising:a requester to issue a request specifying a target address indicating an addressed location in a memory system;a completer to respond to the request issued by the requester; andtag error checking circuitry to perform a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag, the tag error checking operation comprising determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request; in which: at least one data signal path to exchange read data or write data between the requester and the completer; and', 'at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer., 'the requester and the completer are configured to communicate via a memory interface having at least2. The apparatus according to ...

CRYPTOGRAPHIC SUPPORT INSTRUCTIONS

A data processing system includes a single instruction multiple data register file and single instruction multiple processing circuitry . The single instruction multiple data processing circuitry supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file . The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand. 1. Data processing apparatus comprising:a single instruction multiple data register file; andsingle instruction multiple data processing circuitry coupled to said single instruction multiple data register file and configured to be controlled by a single instruction multiple data program instruction to perform a processing operation independently upon separate data elements stored within separate lanes within an input operand register of said single instruction multiple data register file; whereinsaid single instruction multiple data processing circuitry is configured to be controlled by a further program instruction to perform a further processing operation upon a vector data value comprising a sequence of data elements held within an input operand register of said single instruction multiple data register file to produce an output operand stored within an output operand register of said single instruction multiple data register file, said output operand having a first portion with a value dependent upon all data elements within said sequence of data elements; andwherein said single instruction multiple data processing circuitry is configured to be controlled by a rotate instruction having an input operand and generating an output operand with a value the same as given by a right rotation of said input operand by two bit positions.2. Data processing apparatus as ...

DATA PROCESSING APPARATUS AND METHOD WITH OWNERSHIP TABLE

A data processing apparatus () comprises processing circuitry () to execute a plurality of processes. An ownership table () comprises one or more entries () each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses. 1. A data processing apparatus comprising:processing circuitry to execute a plurality of processes; andan ownership table comprising one or more entries each indicating, for a corresponding block of physical addresses, which of said plurality of processes is an owner process that has exclusive control of access to the corresponding block of physical addresses.2. The apparatus according to claim 1 , wherein in response to an ownership request requesting that a requesting process of said plurality of processes becomes the owner process for a target block of physical addresses claim 1 , the processing circuitry is configured to update the ownership table to indicate that said requesting process is the owner process for said target block of physical addresses.3. The apparatus according to claim 2 , wherein the processing circuitry is configured to prevent said requesting process becoming the owner process for said target block of physical addresses until after successful completion of an overwriting procedure for overwriting data at every physical address of said target block.4. The apparatus according to claim 3 , wherein the processing circuitry comprises hardware to perform the overwriting procedure in response to the ownership request.5. The apparatus according to claim 3 , wherein the processing circuitry is configured to check whether the requesting process or a trusted process has successfully completed the overwriting procedure.6. The apparatus according to claim 5 , wherein the processing circuitry is configured to determine that the overwriting procedure has failed when the physical addresses overwritten in one or ...

METHOD FOR SEALING OFF AN ORIFICE OF A STORAGE CELL CONTAINER AND CONTAINER SEALED OFF BY THIS METHOD

There is provided a method for sealing a filling orifice formed on a wall of a container in a leak-proof manner using a stopper arrangement comprising a tubular member with a flange having an upper face, and a lower face for covering the orifice, and a mandrel with a stem which is housed inside the tubular member, the force necessary for rupturing the stem being greater than the force resulting from the entry and advancement of a head of the mandrel inside the tubular member, comprising introducing the stopper arrangement into the orifice, bringing the nosepiece of the riveting tool into abutment with the upper face of the flange, actuating the riveting tool so as to exert a tensile force on the stem and bring about expansion of the tubular member against the wall of the orifice and rupturing the stem of the stopper arrangement. 1. A method for sealing in a leak-proof manner a filling orifice formed on a wall of a container using a stopper arrangement , said stopper arrangement comprising:a tubular member, said tubular member being provided at one of its ends with a flange having an upper face adapted to receive a nosepiece of a riveting tool and a lower face adapted to cover the orifice, anda mandrel provided with a stem terminating with a head, the stem being housed inside the tubular member and the head being located at one end of the mandrel, opposite the flange, said mandrel head having a cross section that is comprised between the inside cross section and the outer cross section of the tubular member, the material constituting the stem having a hardness that is equal to or greater than three times the hardness of the material constituting the tubular member and the material constituting the container wall having a hardness greater than or equal to 1.3 times that of the tubular member,said method comprising the steps of:introducing the stopper arrangement into the orifice, the cross section of the orifice being greater than the outer cross section of the ...

PROJECTILE WITH STEERABLE CONTROL SURFACES AND CONTROL METHOD OF THE CONTROL SURFACES OF SUCH A PROJECTILE

The subject-matter of the invention is a method for controlling the control surfaces of a projectile and the associated projectile comprising incidence steerable control surfaces and comprising at least two control surfaces, each one being rotatable with respect to the projectile around a pivot axis perpendicular to the longitudinal axis X of the projectile, wherein the projectile comprises central means for controlling the control surfaces having at least a spherical shape, a control arm secured to the spherical shape and adapted to rotate the spherical shape, for each control surface a transmission member cooperating with the spherical shape and adapted to transmit to the control surface the rotation movements of the spherical shape, and means for positioning the arm. 1. A projectile with incidence steerable control surfaces comprising at least two control surfaces , each control surface being rotatable with respect to the projectile around a pivot axis perpendicular to the longitudinal axis X of the projectile , wherein the projectile comprises:central means for controlling the control surfaces comprising at least a spherical shape, the center O of the spherical shape being on the longitudinal axis X, the spherical shape being arranged in a housing of the projectile,{'b': '2', 'a control arm secured to the spherical shape and adapted to rotate the spherical shape at least around the pitch Y and yaw axes of the projectile passing through the center O of the spherical shape,'}for each control surface, a transmission member cooperating with the spherical shape by a first side and with the control surface foot by a second side, wherein the transmission member is intended to transmit to the control surface the rotation movements of the spherical shape around the pivot axis of the control surface,means for positioning the arm adapted to position an end of the arm in a position determined with respect to an absolute frame RA centered on the longitudinal axis X of the ...

SYSTEM ERROR HANDLING IN A DATA PROCESSING APPARATUS

Apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to data processing instructions. An error exception condition is set if a data processing operation has not been successful. It is determined if an error memory barrier condition exists and an error memory barrier procedure is performed in dependence on whether the error memory barrier condition exists. The error memory barrier procedure comprises, if the error exception condition is set and if an error mask condition is set: setting a deferred error exception condition and clearing the error exception condition. 1. Apparatus for data processing comprising:processing circuitry to perform data processing operations in response to data processing instructions, to determine if an error memory barrier condition exists and to perform an error memory barrier procedure in dependence on whether the error memory barrier condition exists,wherein the processing circuitry is capable of setting an error exception condition upon detection that a data processing operation has not been successful, and setting a deterred error exception condition; and', 'clearing the error exception condition., 'wherein the error memory barrier procedure comprises, if the error exception condition is set and if an error mask condition is set2. The apparatus as claimed in claim 1 , wherein the processing circuitry claim 1 , if error exception condition is set and the error mask condition is not set claim 1 , is capable of performing an exception handling procedure.3. The apparatus as claimed in claim 1 , wherein the data processing operations comprise memory accesses claim 1 , andwherein the processing circuitry is capable of receiving an error response for a memory access, and wherein the processing circuitry is capable of setting the error exception condition if the error response indicates that the memory access has not been successful.4. The apparatus as claimed in ...

SHARED PAGES

A data processing system comprising: ownership circuitry to enforce ownership rights of memory regions within a physical memory address space, a given memory region having a given owning process specified from among a plurality of processes and independently of privilege level, said given owning process having exclusive rights to control access to said given memory region, wherein said given owning process designates said given memory region as one of: private to said given owning process; and shared between said given owning process and at least one further source of memory access requests. 1. Apparatus for processing data comprising: private to said given owning process; and', 'shared between said given owning process and at least one further source of memory access requests., 'ownership circuitry to enforce ownership rights of memory regions within a physical memory address space, a given memory region having a given owning process specified from among a plurality of processes and independently of privilege level, said given owning process having exclusive rights to control access to said given memory region, wherein said given owning process designates said given memory region as one of2. Apparatus as claimed in claim 1 , wherein said given owning process designates said given memory region when shared as one of shared between said given owning process and one of:one or more bus mastering devices mapped within memory regions also owned by said given owning process;a parent process that transferred ownership of said given memory region to said given owning process;an ancestor process of said given owning process that transferred ownership of said given memory region prior to ownership of said given memory region by said given owning process; andany other process.3. Apparatus as claimed in claim 1 , wherein said ownership circuitry permits said given owning process to deny access to said given memory region to a process having a greater level of privilege than ...

Protected exception handling

A data processing system for processing data comprising: ownership circuitry to enforce ownership rights of memory regions, a given more privileged state memory region having a given owning process specified from among a plurality of processes, said given owning process having exclusive rights to control access to said given memory region; and context switching circuitry responsive to receipt of an interrupt to trigger a context switch from a first active process to a second active process whereby one or more items of state for use in restarting said first process is saved to one or more context data memory regions owned by said first process and one or more items of state accessible to said second process and dependent upon processing by said first process is overwritten prior to commencing execution of said second process.

DATA PROCESSING APPARATUS AND METHOD

A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element. 2. The data processing apparatus according to claim 1 , wherein the number of bits of said first portion increases in dependence on said selected data size as the number of bits of said second portion decreases in dependence on said selected data size.3. The data processing apparatus according to claim 1 , wherein for at least a subset of said plurality of data sizes claim 1 , said first portion comprises at least a first bit having a first state and X remaining bits having a second state claim 1 , where X is a variable integer greater than claim 1 , or equal to claim 1 , 0; andsaid at least one of said instruction decoder and said processing circuitry is configured to identify the number of bits comprised by said first portion of said control value in dependence on a bit position of said first bit within a predetermined portion of said control value.4. The data processing apparatus according to claim 3 , wherein said first portion comprises at least one additional bit for providing further information for identifying said selected data size.5. The data processing apparatus according to claim 1 , wherein said at least one control parameter comprises a plurality of ...

Address translation

A data processing apparatus ( 20 ) comprises address translation circuitry ( 40 ) to translate a first address into a physical address directly identifying a corresponding location in a data store, and a table ( 50 ) comprising one or more entries indexed by the physical address, wherein at least one of the entries specifies the first address from which the corresponding physical address was translated by the address translation circuitry ( 40 ).

SECURE INITIALISATION

A data processing system for processing data using a memory having a plurality of memory regions, a given memory region within said plurality of memory regions having an associated owning process having exclusive rights to control access to said given memory region, said system comprising: a security controller to: receive a request to initialise a guest execution environment; claim one or more regions of memory to be owned by said security controller; store executable program code of said guest execution environment within said one or more regions of memory; and transfer ownership of said one or more regions to said guest execution environment. 1. A method of processing data using a memory having a plurality of memory regions , a given memory region within said plurality of memory regions having an associated owning process having exclusive rights to control access to said given memory region , said method comprising:receiving at a security controller a request to initialise a guest execution environment;claiming with the security controller one or more regions of memory to be owned by said security controller;storing with said security controller executable program code of said guest execution environment within said one or more regions of memory; andtransferring with said security controller ownership of said one or more regions to said guest execution environment.2. A method as claimed in claim 1 , comprising executing said executable program code of said guest execution environment using said one of more regions owned by said guest execution environment.3. A method as claimed in claim 2 , wherein said executable program code executing in said guest execution environment requests claiming of one or more further memory regions to be owned by said guest execution environment.4. A method as claimed in claim 1 , wherein claiming of a given memory region to a new owning process includes overwriting data stored within said given memory region before said new owning ...

APPARATUS AND METHOD FOR HANDLING WRITE OPERATIONS

An apparatus and method are provided for handling write operations. The apparatus has a first processing device for executing a sequence of instructions, where the sequence comprises at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region. A writeback cache associated with the first processing device is used to store the write data output during the one or more write operations. Coherency circuitry is coupled to the writeback cache and to at least one further cache associated with at least one further processing device. The first processing device is responsive to a trigger event to initiate a clean operation in order to cause the write data to be written from the writeback cache to memory. Further, the coherency circuitry is responsive to the clean operation to interact with the at least one further cache to implement a hardware protocol in order to make the write data visible to the at least one further processing device. This can provide a very efficient and cost effective mechanism for implementing cache coherency in certain systems. 1. An apparatus comprising:a first processing device to execute a sequence of instructions, said sequence comprising at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region;a writeback cache associated with the first processing device and arranged to store the write data output during the one or more write operations; ...

ADDRESS TRANSLATION DATA INVALIDATION

A data processing system () including one or more transaction buffers () storing address translation data executes translation buffer invalidation instructions TLBI within respective address translation contexts VMID, ASID, X. Translation buffer invalidation signals generated as a consequence of execution of the translation buffer invalidation instructions are broadcast to respective translation buffers and include signals which specify the address translation context of the translation buffer invalidation instruction that was executed. This address translation context specified within the translation buffer invalidation signals is used to gate whether or not those translation buffer invalidation signals when received by translation buffers which are potential targets for the invalidation are or are not flushed. The address translation context data provided within the translation buffer invalidation signals may also be used to control whether or not local memory transactions for a local transactional memory access are or are not aborted upon receipt of the translation buffer invalidation signals. 1. Apparatus for processing data comprising:one or more translation buffers to store respective address translation data to map received addresses to translated addresses; andprocessing circuitry to execute program instructions; whereinsaid processing circuitry is responsive to a translation buffer invalidation instruction within a sequence of program instructions executing using a given address translation context to broadcast translation buffer invalidation signals to said one or more translation buffers, andsaid translation buffer invalidation signals specify said given address translation context.2. Apparatus as claimed in claim 1 , wherein said apparatus supports execution of a plurality of virtual machine execution contexts and said given address translation context includes a virtual machine identifier to identify a virtual machine execution context of said ...

HANDLING GUARD TAG LOSS

An apparatus comprising memory access circuitry to perform a tag-guarded memory access in response to a received target address and methods of operation of the same are disclosed. In the tag-guarded memory access a guard-tag retrieval operation seeks to retrieve a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the received target address, and a guard-tag check operation compares an address tag associated with the received target address with the guard tag retrieved by the guard-tag retrieval operation. When the guard-tag retrieval operation is unsuccessful in retrieving the guard tag, a substitute guard tag value is stored as the guard tag in association with the block of one or more memory locations comprising the addressed location identified by the target address. 1. An apparatus comprising: a guard-tag retrieval operation to retrieve a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the received target address; and', 'a guard-tag check operation of comparing an address tag associated with the received target address with the guard tag retrieved by the guard-tag retrieval operation,, 'memory access circuitry to perform a tag-guarded memory access in response to a received target address, the tag-guarded memory access comprisingwherein the memory access circuitry is responsive to the guard-tag retrieval operation being unsuccessful in retrieving the guard tag to cause storage of a substitute guard tag value as the guard tag stored in association with the block of one or more memory locations comprising the addressed location identified by the target address.2. The apparatus as claimed in claim 1 , wherein the substitute guard tag value is selected to match the address tag associated with the received target address in the guard-tag check operation.3. The apparatus as claimed in claim 1 , wherein the substitute ...

CONTINGENT LOAD SUPPRESSION

A data processing system () supports non-speculative execution of vector load instructions that perform at least one contingent load of a data value. Fault detection circuitry () serves to detect whether a contingent load is fault-generating contingent load or a fault-free contingent load. Contingent load suppression circuitry () detects and suppresses a fault-free contingent load that matches a predetermined criteria that may result in an undesired change of architectural state (undesired side-effect). Examples of such predetermined criteria are that the contingent load is to a non-memory device or that the contingent load will trigger a diagnostic response such as entry of a halting debug halting mode or triggering of a debug exception. 1. Apparatus for processing data comprising:vector load circuitry responsive to non-speculative execution of a vector load instruction to perform at least one contingent load of a data value read from a memory address location of a memory to an element of a vector register;fault detection circuitry to detect whether said contingent load is a fault-generating contingent load or a fault-free contingent load; andcontingent load suppression circuitry to detect and suppress a fault-free contingent load that matches a predetermined criteria.2. Apparatus as claimed in claim 1 , wherein said predetermined criteria is indicative of a capability to result in a change of state of said apparatus beyond fault-free loading of said data value to said element of said vector register.3. Apparatus as claimed in claim 1 , wherein said vector load circuitry is responsive to said vector load instruction to perform a plurality of loads comprising a non-contingent load and a plurality of contingent loads.4. Apparatus as claimed in claim 1 , wherein said vector load circuitry is responsive to said vector load instruction to perform a plurality of contingent loads.5. Apparatus as claimed in claim 3 , wherein said non-contingent load is permitted to load a ...

CONTROL OF USER-SELECTABLE VEHICLE DECELERATION RATE TO MAXIMIZE REGENERATION FOR ELECTRIFIED PROPULSION SYSTEMS

An electrical regeneration and vehicle deceleration control method comprises operating an electrified powertrain in normal or maximum regeneration modes associated with lesser and greater electrical regeneration and vehicle deceleration rates, respectively, receiving an input from a driver of the vehicle indicative of a request to enable the maximum regeneration mode, detecting a status indicative of an availability of the maximum regeneration mode, and in response to receiving the request and based on the status of the maximum regeneration mode and a current vehicle deceleration rate: (i) operating the electrified powertrain in either the maximum regeneration mode or a normal regeneration mode, (ii) selectively outputting a message to the driver indicative of the status of the maximum regeneration mode, and (iii) selectively commanding a hydraulic brake system of the vehicle to generate brake force based on a driver-expected vehicle deceleration rate associated with the operative regeneration mode. 1. An electrical regeneration and vehicle deceleration control system for an electrified vehicle having an electrified powertrain comprising an engine and at least one electric motor , the control system comprising:a user interface; and operate the electrified powertrain in a normal regeneration mode associated with first electrical regeneration and vehicle deceleration rates or a maximum regeneration mode associated with greater second electrical regeneration and vehicle deceleration rates;', 'receive, via the user interface, an input from a driver of the vehicle indicative of a request to enable the maximum regeneration mode;', 'detect a status of the maximum regeneration mode, wherein the status is indicative of an availability of the maximum regeneration mode; and', (i) operate the electrified powertrain in either the maximum regeneration mode or the normal regeneration mode;', '(ii) selectively output, via the user interface, a message to the driver indicative of ...

SPECULATION BARRIER INSTRUCTION

An apparatus comprises processing circuitry to perform data processing and instruction decoding circuitry to decode instructions to control the processing circuitry to perform the data processing. The instruction decoding circuitry is responsive to a speculation barrier instruction to control the processing circuitry to prevent a subsequent operation, appearing in program order after the speculation barrier instruction, that has an address dependency on an earlier instruction preceding the speculation barrier instruction in the program order, from speculatively influencing allocations of entries in a cache. This provides protection against speculative cache-timing side-channel attacks. 1. An apparatus comprising:processing circuitry to perform data processing;instruction decoding circuitry to decode instructions to control the processing circuitry to perform the data processing; andin which:the instruction decoding circuitry is responsive to a speculation barrier instruction to control the processing circuitry to prevent a subsequent operation, appearing in program order after the speculation barrier instruction, that has an address dependency on an earlier instruction preceding the speculation barrier instruction in the program order, from speculatively influencing allocations of entries in a cache.2. The apparatus according to claim 1 , in which said subsequent operation is one of a load instruction and a store instruction.3. The apparatus according to claim 1 , in which said earlier instruction is a load instruction.4. The apparatus according to claim 1 , in which until the speculation barrier instruction completes: the conditional select instruction has a register data dependency on a load R1 that has been executed speculatively, for one of its input registers, and', 'the conditional select instruction does not have a register dependency on R1 for its other input register, and', 'the condition for the conditional select instruction is such that the input that is ...

WRITE OPERATIONS TO NON-VOLATILE MEMORY

An apparatus for processing data and a method of data processing are provided. A processor core in the apparatus performs data processing operations in response to a sequence of instructions, including write operations which write data items to a non-volatile memory. A write-back cache stores local copies of the data items retrieved from the memory and written to the memory by the processor core. A storage unit is provided which stores indications of the write operations initiated by the processor core and the processor core is configured to respond to an end instruction by causing the local copies of data items which are the subject of the write operations by the processor core, and for which an indication is stored in the storage unit, to be cleaned from the write-back cache to the memory. The indications of the write operations stored in the storage unit are then cleared. 1. Apparatus for processing data comprising:a processor core capable of performing data processing operations in response to a sequence of instructions, wherein the data processing operations comprise read operations which retrieve data items from a memory and write operations which write data items to the memory, wherein the memory is a non-volatile memory;a write-back cache capable of storing local copies of the data items retrieved from the memory and written to the memory by the processor core when executing the sequence of instructions; anda storage unit capable of storing indications of the write operations initiated by the processor core, andthe processor core is capable of responding to an end instruction in the sequence of instructions by:causing the local copies of data items which are the subject of the write operations by the processor core and for which an indication is stored in the storage unit to be cleaned from the write-back cache to the memory; andclearing the indications of the write operations stored in the storage unit.2. The apparatus as claimed in claim 1 , wherein the ...

Integrated Circuit Devices and Methods

An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells. 119-. (canceled)20. An integrated circuit comprising:multiple static random access memory (SRAM) cells, each SRAM cell having at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; 'a bias voltage network operable to apply one bias voltage to the SRAM cell that is being accessed for a read operation and the other bias voltage to the other SRAM cells that are being not accessed for the read operation.', 'at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region positioned a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read ...

DEVICE FOR WASTEWATER PURIFICATION

An integrated device for wastewater purification, comprising a coagulation zone; a flocculation zone connected to and in fluid communication with the coagulation zone; a flotation zone connected to and in fluid communication with the flocculation zone and comprising a froth discharge port; and a separation zone below and in fluid communication with the flotation zone and comprising a contaminant separator and a purified wastewater discharge port; the wastewater entering the device being mixed with electrolytically-generated coagulants and gas bubbles in the coagulation zone; the flocculation zone receiving and gently mixes coagulated wastewater contaminants and gas bubbles formed in the coagulation zone and aggregating them into flocs before flotation of buoyant flocs in the flotation zone and the separation zone being adapted for further floc formation, oil coalescence, settling and discharge of non-buoyant contaminants. 1. An integrated device for wastewater purification , comprising:a coagulation zone, comprising a feed port for the wastewater to enter the device;a flocculation zone connected to and in fluid communication with said coagulation zone;a flotation zone connected to and in fluid communication with said flocculation zone and comprising a froth discharge port; anda separation zone below and in fluid communication with said flotation zone and comprising a contaminant separator and a purified wastewater discharge port;wherein the wastewater entering the device through said feed port is mixed with electrolytically-generated coagulants and gas bubbles in said coagulation zone; said flocculation zone receives and gently mixes coagulated wastewater contaminants and gas bubbles formed in said coagulation zone and aggregates them into flocs before flotation of buoyant flocs in said flotation zone; said separation zone being adapted for further floc formation, oil coalescence, settling and discharge of non-buoyant contaminants.2. The device of claim 1 , wherein ...

DEBUGGING OF A DATA PROCESSING APPARATUS

A data processing apparatus is provided comprising data processing circuitry and debug circuitry. The debug circuitry controls operation of the processing circuitry when operating in a debug mode. The data processing circuitry determines upon entry into a debug mode a current operating state of the data processing apparatus. The data processing circuitry allocates one of a plurality of instruction sets to be used as a debug instruction set depending upon the determined current operating state. 1. A data processing apparatus comprising:data processing circuitry for performing data processing operations in response to execution of program instructions, said data processing circuitry being configured to operate in at least an operational mode and a debug mode;debug circuitry configured to provide an interface between said data processing circuitry and a debugger unit external to said data processing circuitry, said debug circuitry being configured to control operation of said data processing circuitry when said data processing circuitry is operating in said debug mode;wherein said data processing circuitry is configured to determine, upon entry of said data processing circuitry into said debug mode, a current operating state of said data processing apparatus and to allocate, depending upon said current operating state, one of a plurality of instruction sets to be used as a debug instruction set.2. Data processing apparatus according to claim 1 , wherein said data processing circuitry is configured to indicate to said debugger unit said allocated debug instruction set to be used to control said data processing circuitry.3. Data processing apparatus according to claim 1 , wherein said data processing circuitry is configurable to operate at a plurality of privilege levels claim 1 , wherein at different privilege levels claim 1 , said data processing circuitry imposes on program instructions different access permissions to at least one of a memory and a set of registers.4. ...

VALVE

A valve with a housing () in which is formed a chamber (), an inlet () to the chamber, an outlet () from the chamber which is at a right angle relative to the inlet, a metallic valve seat () at the inlet, a resilient valve seal () mounted to the valve seat at the inlet and a spherical valve member () inside the chamber. 1. A valve which includes a housing in which is formed a chamber , an inlet , to the chamber , through which fluid flows in a first direction , an outlet , from the chamber , through which fluid flows in a second direction which is transverse to the first direction , an annular seal adjacent the inlet , an annular valve seat adjacent the seal , a flange structure which is secured to the housing and which is engaged at least with the seal and with the valve seat , and a spherical valve member which is movable inside the chamber and which is sealingly engageable at least with the seal2. A valve according to wherein the flange structure includes a retention assembly with a locating formation with which the annular valve seat is engageable.3. A valve according to wherein the retention assembly includes a seat retaining ring and a seal retaining ring which are secured to each other and which define a recessed annular formation with which a projection on the seal claim 2 , of complementary shape claim 2 , is engageable.4. A valve according to wherein opposing surfaces of the annular valve seat and the retention assembly define an undercut formation with which a formation claim 2 , on the seal claim 2 , which is of complementary shape to the undercut formation claim 2 , is engageable.5. A valve according to wherein the flange structure includes a weld neck which is secured to the housing on an outer side of the housing surrounding the inlet and a ring which is enagageable with a plurality of fasteners and which is coupled to the weld neck through the medium of a snap-ring.6. A valve according to wherein the seal includes an outer surface which abuts an ...

Exception handling

A data processing system (2) includes exception handling circuitry (26) to detect attempted execution of an exception-triggering processing operation which includes transfer of a data value with a given register of a register bank (20). Upon detection of such an exception-triggering processing operation, syndrome data is stored within a syndrome register (32) characterising the exception-triggering processing operation with that syndrome data including the data value. The value may be stored into the syndrome register upon occurrence of the exception in the case of an aborting write instruction. The data value may be stored into the syndrome register by emulating code triggered by exception in the case of an aborting read instruction.

PAGE TABLE MANAGEMENT

Page table data for each page within a memory address space includes a write permission flag and a dirty-bit-modifier flag. The write permission flag is initialised to a value indicating that write access is not permitted. When a write access occurs, then the dirty-bit-modifier flag indicates whether or not the action of the write permission flag may be overridden. If the action of the write permission flag may be overridden, then the write access is permitted and the write permission flag is changed to indicate that write access is thereafter permitted. A page for which the write permission flag indicates that writes are permitted is a dirty page. 1. Apparatus for processing data comprising:processing circuitry configured to manage page table data, said page table data specifying access management parameters associated with pages of memory within a memory address space; whereinfor each page of memory, said access management parameters include:a write permission flag indicating whether or not write access is permitted to said page; anda dirty-bit-modifier flag indicating whether or not, if said write permission flag indicates write access is not permitted to said page, then action of said write permission flag is permitted to be overridden to permit a write access to said page and changing of said write permission flag to indicate write access is permitted to said page.2. Apparatus as claimed in claim 1 , comprising hardware-updating memory management circuitry coupled to said processing circuitry and configured to respond to generation of a write access by said processing circuitry to a page having an write permission flag indicating that write access is not permitted to said page claim 1 , by reading said dirty-bit-modifier flag associated with said write permission flag claim 1 , and claim 1 , if said dirty-bit-modifier indicates that action of said write permission flag is permitted to be overridden claim 1 , then permitting said write access and performing said ...

Diagnosing code using single step execution

A method and apparatus for controlling a processor to execute in a single step mode such that a single instruction from the instruction stream is executed, the processor determines if the single instruction is one of at least one predetermined type of instruction and stores a type indicator in a data storage location and a diagnostic exception is taken after the processor has processed the single instruction. Additionally, a diagnostic operation is performed including accessing the type indicator stored in the data storage location and, when the single instruction was not one of the predetermined type, controlling the processor to continue executing instructions in the single step mode, and, when the single instruction was one of the at least one predetermined type, controlling the processor to exit the single step mode and not execute the next instruction within the instruction stream as a single instruction followed by an exception.

Additive Manufacturing Systems and Methods of Generating CAD Models for Additively Printing on Workpieces

An additive manufacturing system may include a controller operably coupled to a vision system and an additive manufacturing machine. The controller may be configured to determine in a library-CAD model, a nominal model-interface traversing a nominal model corresponding to a workpiece, to compare the nominal model-interface of the library-CAD model to a digital representation of a workpiece-interface of the workpiece, where the digital representation has been obtained using the vision system, and to generate a model of an extension segment based at least in part on the nominal model-interface, with the model of the extension segment being configured to be additively printed on the workpiece-interface of the workpiece.

METHOD AND APPARATUS FOR INTERRUPT HANDLING

A data processing device comprises a plurality of system registers and a set of interrupt handling registers for controlling handling of an incoming interrupt. The device also includes processing circuitry configured to execute software of the plurality of execution levels, and interrupt controller circuitry configured to route said incoming interrupts to interrupt handling software that is configured to run at one of said plurality of execution levels, and register access control circuitry configured to dynamically control access to at least some of said interrupt handling registers in dependence upon one of said plurality of execution levels that said incoming interrupt is routed to. The interrupt handling software configured to run at a particular execution level does not have access to interrupt handling registers for handling a different incoming interrupt that is routed to interrupt handling software that is configured to run at a more privileged execution level. 1. A data processing device comprising:a plurality of system registers, comprising a set of interrupt handling registers for controlling handling of an incoming interrupt;processing circuitry configured to execute software at a plurality of execution levels,interrupt controller circuitry configured to route said incoming interrupt to interrupt handling software configured to run at one of said plurality of execution levels;register access control circuitry configured to dynamically control access to at least some of said interrupt handling registers in dependence upon said one of said plurality of execution levels that said incoming interrupt is routed to, such that interrupt handling software configured to run at said execution level has access to said at least some of said interrupt handling registers for handling said incoming interrupt, and such that said interrupt handling software configured to run at said execution level does not have access to interrupt handling registers for handling a second ...

An apparatus and method to generate trace data in response to transactional execution

There is provided an apparatus comprising processing circuitry to execute a transaction comprising a number of program instructions that execute to generate updates to state data, to commit the updates if the transaction completes without a conflict, and to generate trace control signals during execution of the number of program instructions. The processing circuitry uses at least one resource during execution of the program instructions. Transaction trace circuitry generates trace items in response to the trace control signals. In response to the trace control signals indicating that a change in a usage level of the at least one resource has occurred during execution of the program instructions, the transaction trace circuitry generates at least one trace item that indicates the usage level of the at least one resource.

PROJECTILE WITH STEERABLE CONTROL SURFACES

A projectile () with incidence steerable control surfaces () each pivotable with respect to the projectile (), comprises: 1- A projectile with incidence steerable control surfaces , the projectile comprising at least two control surfaces , each control surface being pivotable with respect to the projectile around a pivot axis perpendicular to a longitudinal axis of the projectile , the projectile comprising:central control means for controlling the control surfaces, the central control means comprising at least one spherical form a center of which is located on the longitudinal axis, the spherical form being arranged in a housing of the projectile,a control arm integral with the spherical form and adapted to rotate the spherical form at least around pitch and yaw axes of the projectile passing through the center of the spherical form,for each control surface, a transmission member cooperating with the spherical form by a first side and with a foot of the control surface by a second side, the transmission member being intended to transmit to the control surface the rotation movements of the spherical form around the pivot axis of the control surface,positioning means for positioning the arm, the positioning means being adapted to position one end of the arm in a position determined with respect to an absolute reference frame centered on the longitudinal axis of the projectile, wherein:the positioning means comprises a cone movable in translation along the longitudinal axis of the projectile between a first, so-called neutral, position and a second, so-called piloting, position in which the cone pushes a ramp carried by a first end of the control arm so as to pivot the central control means around a so-called orientation axis passing through the center of the central control means,the central control means is freely rotatable around the longitudinal axis of the control arm,the positioning means comprises a toothed wheel centered on the longitudinal axis of the ...

Fin blocking device and projectile having such a device

A device for blocking a fin of a projectile, the fin including a fin base pivoting about a pivot pin secured to the body of the projectile between a withdrawn fin position and a deployed fin position, wherein the device includes at least one recess housing at least one shape of revolution pushed by a resilient means between a first surface borne by the fin and a second surface borne by the body of the projectile, at least one of the two surfaces forming a ramp that converges toward the other surface to tend to cause jamming of the shape of revolution between the two surfaces.

HANDLING LOAD-EXCLUSIVE INSTRUCTIONS IN APPARATUS HAVING SUPPORT FOR TRANSACTIONAL MEMORY

An apparatus is described with support for transactional memory and load/store-exclusive instructions using an exclusive monitor indication to track exclusive access to a given address. In response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, any exclusive monitor indication previously set for the load target address is cleared. In response to a load-exclusive instruction, an abort is triggered for a transaction for which the given address is specified as one of its working set of addresses. This helps to maintain mutual exclusion between transactional and non-transactional threads even if there is load speculation in the non-transactional thread. 1. An apparatus comprising:processing circuitry to process threads of data processing; andtransactional memory support circuitry to support execution of a transaction within a thread processed by the processing circuitry, the transaction comprising instructions of the thread executed speculatively between a transaction start instruction and a transaction end instruction, for which the processing circuitry is configured to prevent commitment of results of the speculatively executed instructions until the transaction end instruction is reached, the transaction memory support circuitry comprising conflict detection circuitry to trigger an abort of the transaction in response to detecting a conflicting access from another thread to one of a working set of addresses tracked for the transaction; in which:in response to a load-exclusive instruction specifying a given address, the processing circuitry is configured to set an exclusive monitor indication for the given address;in response to a store-exclusive instruction specifying the given address, the processing circuitry is configured to return a store-exclusive fail indication when the given address no longer has the exclusive monitor indication set;in response to a predetermined type of load ...

MOVE PREFIX INSTRUCTION

An apparatus has instruction fusing circuitry for fusing two or more instructions fetched from a data store to generate a fused instruction to be processed by processing circuitry . A move prefix instruction is provided which indicates to the instruction fusing circuitry that the move prefix instruction can be fused with an immediately following data processing instruction without needing to compare registers specified by the move prefix instruction and the immediately following instruction. This enables the instruction fusing circuitry to be implemented with reduced hardware and energy cost. 1. An apparatus comprising:processing circuitry to perform data processing in response to instructions; andinstruction fusing circuitry to fuse a move prefix instruction and an immediately following instruction fetched from a data store to generate a fused data processing instruction to be processed by the processing circuitry;wherein the move prefix instruction identifies a move destination register and a move source register specifying a data value to be at least partially copied to the move destination register; andin response to detecting said move prefix instruction, the instruction fusing circuitry is configured to determine whether to fuse said move prefix instruction and said immediately following instruction independently of whether the move destination register of the move prefix instruction is the same register as any register specified by said immediately following instruction.2. The apparatus according to claim 1 , wherein the move prefix instruction indicates that the immediately following instruction is expected to be a destructive data processing instruction for which a destination register is to be set to a result value corresponding to a result of applying a predetermined processing operation to at least two source values specified by at least two source registers claim 1 , and for which the destination register and one of said at least two source registers ...

APPARATUS AND METHOD FOR HANDLING EXCEPTION EVENTS

Processing circuitry has a plurality of exception states for handling exception events, the exception states including a base level exception state and at least one further level exception state. Each exception state has a corresponding stack pointer indicating the location within the memory of a corresponding stack data store. When the processing circuitry is in the base level exception state, stack pointer selection circuitry selects the base level stack pointer as a current stack pointer indicating a current stack data store for use by the processing circuitry. When the processing circuitry is a further exception state, the stack pointer selection circuitry selects either the base level stack pointer or the further level stack pointer corresponding to the current further level exception state as a current stack pointer. 113-. (canceled)14. A data processing apparatus comprising:processing circuitry configured to process data in one of a plurality of exception states, including at least a base level exception state and a further level exception state;a base level stack pointer register for storing a base level stack pointer indicating a location within memory of a base level stack data store;a further level stack pointer register for storing a further level stack pointer indicating a location within memory of a further level stack data store;an exception return register for storing exception return data for use when returning from the further level exception state; andstack pointer selection circuitry for selecting a current stack pointer from at least the base level stack pointer and the further level stack pointer when processing data in the further level exception state,wherein the processing circuitry is configured to use the exception return register when returning from the further level exception state, irrespective of whether the current stack pointer is the base level stack pointer or the further level stack pointer.15. The data processing apparatus ...

PERMITTING UNABORTED PROCESSING OF TRANSACTION AFTER EXCEPTION MASK UPDATE INSTRUCTION

A data processing apparatus has processing circuitry with transactional memory support circuitry to support execution of a transaction using transactional memory. In response to an exception mask updating instruction which updates exception mask information to enable at least one subset of exceptions which was disabled at the start of processing of a transaction, the processing circuitry permits un-aborted processing of one or more subsequent instruction of the transaction that follow the exception mask update instruction. 1. An apparatus comprising:processing circuitry to perform data processing in response to instructions, the processing circuitry comprising transactional memory support circuitry to support execution of a transaction within a thread of data processing by the processing circuitry, the transaction comprising instructions of the thread executed speculatively between a transaction start instruction and a transaction end instruction, for which the processing circuitry is configured to prevent commitment of results of the speculatively executed instructions until the transaction end instruction is reached, and to abort processing of the transaction when an abort event occurs before the transaction end instruction is reached; andexception handling circuitry to determine whether to mask an exception in dependence on exception mask information specifying whether one or more subsets of exceptions are enabled or disabled;wherein in response to an exception mask update instruction executed within a transaction to update the exception mask information to enable at least one subset of exceptions which was disabled at the start of processing of the transaction, the processing circuitry is configured to permit unaborted processing of one or more subsequent instructions of the transaction following said exception mask update instruction.2. The apparatus according to claim 1 , wherein the transactional memory support circuitry comprises restoration state storage ...

Integrated Circuit Devices and Methods

An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells. 119-. (canceled)20. An integrated circuit comprising:multiple SRAM cells, each SRAM cell having at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; andthe pull-up transistors, the pull-down transistors, and the pass-gate transistors having a screening region positioned a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer,wherein the screening region provides an enhanced body coefficient for the pull-up transistors, the enhanced body coefficient acting to increase a read static noise margin of the SRAM cell when a bias voltage is applied to the screening region; anda plurality of SRAM cell groups, each group having a plurality of SRAM cells;at least one body bias control circuit to generate a body bias control signal for each ...

MEMORY ACCESS INSTRUCTIONS

A data processing system () includes an instruction decoder () which decodes protected memory access instructions (LDR/STR) and less-protected memory access instructions (LDNPR/STNPR) to generate control signals for controlling a load store unit (). The less-protected memory access instructions are associated with less restrictive memory access conditions than the protected memory access instructions. As an example, less-protected memory access instructions may be used to access shared memory regions () whereas protected memory access instructions may not be used to access such shared regions. Conversely, less-protected memory access instructions may not be used to access private memory regions (). 1. Apparatus for processing data comprising:processing circuitry to perform processing operations specified by program instructions; anda decoder to decode memory access instructions to generate control signals to control said processing circuitry to perform memory access operations; wherein protected memory access instructions corresponding to protected memory access operations; and', 'less-protected memory access instructions corresponding to less-protected memory access operations; and, 'said memory access instructions have respective encodings specifyingsaid less-protected memory access operations are associated with less restrictive memory access conditions than said protected memory access operations.2. Apparatus as claimed in claim 1 , wherein said less-protected memory access instructions have an encoding permitting a different number of variants than said protected memory access instructions.3. Apparatus as claimed in claim 2 , wherein said less-protected memory access instructions have an encoding permitting fewer variants than said protected memory access instructions.4. Apparatus as claimed in claim 1 , comprising memory access control circuitry to control access to regions of memory address space in dependence upon memory protection data claim 1 , said memory ...

Dram-Type Device With Low Variation Transistor Peripheral Circuits, and Related Methods

A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from power supply voltages of the DRAM; and peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits comprising deeply depleted channel (DDC) transistors having bodies coupled to receive the body bias voltage, each DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region. 120-. (canceled)21. An integrated circuit , comprising:a body bias control circuit configured to generate body bias voltage from a bias supply voltage;functional circuits having at least one transistor having a body coupled to receive the body bias voltage, wherein;the functional circuits comprise a digital delay line circuit including at least a fine delay circuit having a plurality of delay stages arranged in series, each delay stage including the transistors; andthe body bias control circuit is a delay control circuit configured to apply different body biases to the transistors of the delay stages in response to a delay set value.22. An integrated circuit of claim 21 , further comprising:a plurality of dynamic random access memory (DRAM) cells formed in the same substrate as the functional circuits, each DRAM cell including a storage capacitor and access transistor, wherein;the body bias voltage is different from a power supply voltage of the DRAM cell; and{'sup': 18', '3, 'the transistor is deeply depleted channel (DDC) transistor, the DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region, the screening region having a dopant concentration that is no less than 1×10dopant atoms/cmand that is different from a ...

CONDITIONAL SELECTION OF DATA ELEMENTS

An apparatus performs an operation on a register, and then conditionally selects either that register or a further register on which no operation has been performed. The apparatus includes a decoder that decodes a conditional select instruction that specifies a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. A data processor is responsive to the decoded conditional select instruction and the condition (i) having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register, and (ii) not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register. 1. A data processing apparatus comprising:a data store comprising a plurality of storage elements for storing data elements;an instruction decoder configured to decode at least one conditional select instruction, said at least one conditional select instruction comprising a primary source storage element field specifying a primary source storage element, and a secondary source storage element field specifying a secondary source storage element, wherein said at least one conditional select instruction further specifies a condition and an operation to be performed on a data element stored in said secondary source storage element;a data processor configured to perform data processing operations controlled by said instruction decoder wherein:said data processor is responsive to said decoded at least one conditional select instruction and said condition having a predetermined outcome to perform said operation on said data element from said secondary source storage element to output a resultant data element;said data processor is responsive ...

DRAM ARCHITECTURE TO REDUCE ROW ACTIVATION CIRCUITRY POWER AND PERIPHERAL LEAKAGE AND RELATED METHODS

A semiconductor device may include a plurality of memory cells, and at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice. The superlattice may include a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode, and a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode. 1. A semiconductor device comprising:a plurality of memory cells;at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions;a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode; anda second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.2. The semiconductor device of wherein the first operating mode comprises an active mode claim 1 , and wherein the second operating mode comprises a standby mode.3. The semiconductor device of wherein the at least one peripheral circuit comprises a sense amplifier.4. The semiconductor device of ...

VIRTUALISATION SUPPORTING GUEST OPERATING SYSTEMS USING MEMORY PROTECTION UNITS

A processor () is provided with a first memory protection unit () applying a first set of permissions and a second memory protection unit () applying a second set of permissions. A memory access will only be permitted if both the first set of permissions and the second set of permissions are satisfied. The processor also includes a memory management unit () which serves to translate from virtual addresses VA to physical addresses PA. A selectable one of the first memory protection unit () and the memory management unit () is active at any given time under control of a selection bit set by a hypervisor program () executing at an exception level with higher privilege than the exception level at which the guest operating systems execute. 1. Apparatus for processing data comprising:processing circuitry configured to execute a stream of program instructions; to receive a physical address directly specifying a memory address location within a memory for a memory access operation to be performed by said processing circuitry; and', 'to determine in accordance with a first set of permissions whether or not said memory access operation is permitted; and, 'a first memory protection unit configured to receive said physical address; and', 'to determine in accordance with a second set of permissions whether or not said memory access operation is permitted; whereby, 'a second memory protection unit configuredsaid memory access operation is permitted only if it satisfies both said first set of permissions and said second set of permissions.2. Apparatus as claimed in claim 1 , whereinsaid processing circuitry is configured to operate at selectable exception level within a hierarchy of exception levels;when operating at a first exception level within said hierarchy of exception levels, said processing circuitry is permitted to change said first set of permissions and is not permitted to change said second set of permissions; andwhen operating at a second exception level within said ...

HANDLING MEMORY ACCESS OPERATIONS IN A DATA PROCESSING APPARATUS

A processing apparatus has a memory protection unit (MPU) and an address translation unit (ATU) which operate concurrently for memory access operations performed by processing circuitry . The MPU stores access permission data for corresponding regions of an address space. The ATU stores address translation entries for defining virtual-to-physical mappings for corresponding pages of the address space. In response to a memory access operation specifying a target address, one of the MPU and the ATU is selected to handle the memory access operation based on the target address. If the MPU is selected then the target address is a physical address and the MPU checks access permissions using a corresponding set of permission data. If the ATU is selected then the target address is a virtual address and is translated into a physical address using a corresponding translation entry. 1. A data processing apparatus comprising:processing circuitry configured to perform memory access operations for accessing data from a memory;a memory protection unit configured to store sets of permission data for defining access permissions for corresponding regions of a memory address space; andan address translation unit configured to store address translation entries for defining virtual-to-physical address mappings for corresponding pages of the memory address space; wherein:in response to a memory access operation specifying a target address, said data processing apparatus is configured to select, in dependence on said target address, which of said memory protection unit and said address translation unit to use for handling said memory access operation; if said memory protection unit is selected for handling said memory access operation, then said memory protection unit is configured to determine whether said memory access operation is permitted using a corresponding set of permission data corresponding to a region including said target address, and if said memory access operation is ...

DEBUGGING DATA PROCESSING TRANSACTIONS

A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to be performed by software emulation rather than direct execution by the processing hardware. The software emulation may store data representing one or more versions of the speculative updates generated during the emulation. The software emulation may also detect conflicts with the transaction being emulated. In order to facilitate modifying the behaviour of other parts of the system interacting with a transaction under investigation, a non-standard response signal may be returned in response to a detected memory access request to a transaction being emulated. The non-standard response signal may be used to initiate the request source to follow a subsequent path of processing different from that which it would otherwise follow. Support is also provided for detecting a trigger condition which results in the halting (freezing) of a partially completed transaction and the saving the speculative updates associated with that partially completed transaction to the architectural state of the system. 1. A method of processing data comprising:executing program instructions including a target transaction having one or more program instructions that execute to generate speculative updates to state data and to commit said speculative updates if said target transaction completes without a conflict;detecting a trigger condition corresponding to direct execution by processing hardware of a program instruction of said target transaction; to store data representing one or more versions of said speculative updates generated during emulation of execution of said target transaction; and', 'to detect a conflict with said target transaction., ' ...

Additive Manufacturing Systems and Methods of Pretreating and Additively Printing on Workpieces

Methods of additively printing an extension segment on a workpiece may include pretreating a workpiece-interface of a workpiece using an energy beam from an additive manufacturing machine, providing a pretreated workpiece-interface having received a pretreatment, with the pretreatment remediating an aberrant feature of the workpiece and/or the workpiece-interface. Such methods may additionally include additively printing an extension segment on the pretreated workpiece-interface using the energy beam from the additive manufacturing machine. Exemplary additive manufacturing system for printing an extension segment on a workpiece may include a controller operably coupled to a vision system and an additive manufacturing machine.

Ethylene copolymerisation process

Ethylene is copolymerised in the gas phase, for example in a fluidised bed, using a gaseous mixture comprising ethylene, at least one olefine monomer containing at least 4 carbon atoms, an inert gaseous diluent and, optionally, hydrogen at a total absolute pressure of at least one MN/M 2 . The comonomer preferably contains 6 or 8 carbon atoms. The partial pressure of the comonomer may be in the range from 1 kN/m 2 up to 550 kN/m 2 . The inert gaseous diluent typically has a partial pressure of at least 250 kN/m 2 and forms 20% molar of the gaseous mixture. The inert gaseous diluent may be nitrogen and is preferably ethane.

Compilable block clear mechanism on per I/O basis for high-speed memory

A circuit for selectively erasing a semiconductor memory instance on a per I/O basis. The circuit is provided as a tilable architectural element in a memory compiler for the semiconductor memory instance. A plurality of pass gates are disposed between global wordlines provided by the row decoder of the memory array and local wordlines that select memory bit cells in a particular I/O. One or more memory clear signals are used to decouple the local wordlines from the global wordlines and to connect them to a high voltage node, V DD . The I/O is cleared by placing a predetermined logic state (typically 0 ) on the bitline nodes of the I/O and selectively coupling the local wordlines to the V DD node.

Production of polyethylene

Ethylene is polymerized or copolymerized using a pressure of at least 300 kgm/cm 2 and a multi-zone (i.e. two or more) reaction vessel wherein the feed to the first zone is fresh ethylene, which is preferably mixed with recycle gas from the low pressure hopper and into at least a subsequent zone there is introduced a feed containing return gas recycled from the separator. By this technique the composition of the gas feed to the various zones can be varied, for example the hydrogen content of the gas streams to the various zones can be varied and this can produce a polymer of broader molecular weight distribution.

Precision fragmentation assemblages and olefin polymerization catalysts made therefrom

A precision fragmentation assemblage is disclosed, along with precision fragmentation assemblage catalysts derivable therefrom. A method for the preparation of a precision fragmentation assemblage is also disclosed, along with a method for preparing precision fragmentation assemblage catalysts from precision fragmentation assemblages. A method is further disclosed for using precision fragmentation catalysts in the polymerization of olefins to produce polyolefins.

METHOD AND DEVICE FOR THE POLYMERIZATION OF AETHYLENE

Humanised recombinant anti-vla4 antibody and diagnostic compositions and medicaments

The present invention disclosed recombinant anti-VLA-4 antibody molecules, including humanized recombinant anti-VLA-4 antibody molecules. These antibodies are useful in the treatment of specific and non-specific inflammation, including asthma and inflammatory bowel disease. In addition, the humanized recombinant anti-VLA-4 antibodies disclosed can be useful in methods of diagnosing and localizing sites of inflammation.

Display units more particularly for cassettes, tape cartridges and the like

This invention relates to display units for cassettes and like articles. The display unit comprises a vertical support spindle on which is rotatably mounted a plurality of spaced trays. Display sections are formed by adjacent trays for receiving the cassettes and the cassettes are released by axial movement of the adjacent trays on the support spindle. According to the invention adjacent trays are rotatable relative to each other to produce the necessary axial movement and locking means is provided along the length of the spindle to prevent unauthorized operation.

Precision fragmentation assemblages and olefin polymerization catalysts made therefrom

A precision fragmentation assemblage is disclosed, along with precision fragmentation assemblage catalysts derivable therefrom. A method for the preparation of a precision fragmentation assemblage is also disclosed, along with a method for preparing precision fragmentation assemblage catalysts from precision fragmentation assemblages. A method is further disclosed for using precision fragmentation catalysts in the polymerization of olefins to produce polyolefins.

ARTICLE PRESENTATION APPARATUS

WING AND PROJECTILE LOCKING DEVICE INCLUDING SUCH A DEVICE

------ DISPOSITIF DE BLOCAGE D’AILETTE ET PROJECTILE COMPORTANT UN TEL DISPOSITIF L’invention porte sur un dispositif de blocage (10) d’une ailette (3) d’un projectile (100), ailette (3) comportant un pied (3a) d’ailette pivotant autour d’un axe (4) solidaire du corps (2) du projectile (100) entre une position d’ailette rentrée et une position d’ailette sortie, dispositif (10) caractérisé en ce qu’il comporte au moins un évidement (5) abritant au moins une forme de révolution (7) poussée par un moyen élastique (6) entre une première surface (S1) portée par l’ailette (3) et une deuxième surface (S2) portée par le corps du projectile (2), au moins une des deux surfaces (S1,S2) formant une rampe (5a) qui converge vers l’autre surface pour tendre à provoquer un coincement de la forme de révolution (7) entre les deux surfaces. -Fig.2- ------ DEVICE FOR LOCKING A FIN AND PROJECTILE COMPRISING SUCH A DEVICE The invention relates to a device (10) for locking a fin (3) of a projectile (100), fin (3) comprising a fin foot (3a) pivoting about an axis (4) secured to the body (2) of the projectile (100) between a retracted fin position and an extended fin position, device (10) characterized in that that it comprises at least one recess (5) housing at least one form of revolution (7) pushed by an elastic means (6) between a first surface (S1) carried by the fin (3) and a second surface (S2 ) carried by the body of the projectile (2), at least one of the two surfaces (S1, S2) forming a ramp (5a) which converges towards the other surface to tend to cause jamming of the shape of revolution (7) between both surfaces. -Fig.2-

DEVICE FOR CONNECTING CONCORDANCE OF SHAPE BETWEEN A SHOE AND A BAR OF A PROJECTILE

L'invention a pour objet un dispositif de liaison par concordance de forme entre un sabot (2) et un barreau (3) d'un projectile de type flèche. Ce dispositif comprend des profils alternant dents (7,9) et sillons (8,10) et il est caractérisé en ce qu'il comporte une partie avant (F) et une partie arrière (R) dans lesquelles les jeux entre les dents du barreau (3) et leurs logements (8) dans le sabot (2) sont variables, le jeu étant, au niveau de chaque partie, croissant entre une zone médiane (M) du sabot et une extrémité avant ou arrière du sabot. The object of the invention is a form-fitting connection device between a shoe (2) and a bar (3) of an arrow projectile. This device comprises profiles alternating teeth (7,9) and grooves (8,10) and is characterized in that it comprises a front portion (F) and a rear portion (R) in which the play between the teeth of the bar (3) and their housings (8) in the shoe (2) are variable, the game being, at each part, growing between a central zone (M) of the shoe and a front end or back of the shoe.

CONNECTION DEVICE BETWEEN A SOCKET AND A PROJECTILE AND METHOD OF MOUNTING A BELT ON A PROJECTILE USING SUCH A CONNECTION DEVICE

ORIENTABLE GOVERNANCE PROJECTILE

L'invention porte sur un projectile (100) à gouvernes (2) orientables en incidence, pouvant chacune pivoter par rapport au projectile (100) et comportant : un moyen central (5) de commande des gouvernes (2), un bras de commande (11) apte à faire tourner le moyen central de commande (5) autour des axes de tangage (Y) et lacet (Z) du projectile (100), un moyen de positionnement du bras (11) apte à positionner une extrémité du bras (11) dans une position déterminée relativement à un repère absolu, le moyen de positionnement comporte un cône mobile (13) en translation pour faire pivoter le moyen central (5) de commande autour d'un axe d'orientation (AO), ainsi qu' une roue dentée (16) engrenant avec une motorisation destinée à piloter la position angulaire de l'axe d'orientation dans un repère absolu. The invention relates to a projectile (100) with control surfaces (2) orientable in incidence, each able to pivot relative to the projectile (100) and comprising: a central means (5) for controlling the control surfaces (2), a control arm (11) capable of rotating the central control means (5) around the pitch (Y) and yaw (Z) axes of the projectile (100), arm positioning means (11) capable of positioning one end of the arm (11) in a determined position relative to an absolute reference, the positioning means comprises a movable cone (13) in translation to cause the central control means (5) to pivot around an orientation axis (AO), thus a toothed wheel (16) meshing with a motorization intended to control the angular position of the orientation axis in an absolute reference.

Warhead e.g. missile, has enclosure comprising three sectors, which are regularly angularly distributed and delimited longitudinally by support or by grooves or ribs that extend from one end to another end of enclosure

The warhead has an explosive load (2) placed in an enclosure (3) in shape of a twin wheel. The explosive load forms shape of revolution generated by a curved profile whose convexity is directed toward a revolution axis of the enclosure. Two ignition units are arranged at an end of the explosive load. The enclosure comprises three sectors (3a-3c), which are regularly angularly distributed and delimited longitudinally by grooves (12) or ribs or by a support that surrounds the enclosure, where the ribs extend from one end to another end of the enclosure.

Warhead for use in projectile for dispersing kinetic submunitions that attack e.g. persons, has housing comprising opening, which is placed in vicinity of deflector and allows passage of submunitions that are pulled by pushing unit

The warhead (1) has a housing (1a) containing loads of submunitions (7), which are located between a deflector (6) and a pushing unit (8b) of the submunitions toward the deflector. The housing comprises an opening (9) that is closed by a releasable sealing unit (9a). The opening is placed in vicinity of the deflector, and allows passage of the submunitions that are pulled by the pushing unit. The deflector comprises a conical form whose top (6a) is directed toward the submunitions loads, where the submunitions include balls made of dense material.

Load support

AGENTS REF: FT36 PCT ABSTRACT A support between the floor (22) and the roof (24) of e.g a mine stope, is made by using an inflatable container comprising an inner bag (10), received in an outer bag (12). An inlet valve (14) extends through both bags as does a relatively higher pressure relief outlet valve (16). In use, air is pumped into the container until it is fully inflated, following by a grout, the air escaping via the valve (16) until the inner bag (10) is filled.

Device for securing two containers and container associated with such a device.

STABILIZATION DEVICE AND PROJECTILE EQUIPPED WITH SUCH A DEVICE

L'invention porte sur un dispositif de stabilisation (1) destiné à équiper un projectile (100) tiré par un canon et un tel projectile équipé dudit dispositif. Ce dispositif comporte au moins une ailette (2), pivotante autour d'un axe de rotation (3) perpendiculaire à l'axe longitudinal (7) du projectile entre une position rentrée où l'extrémité libre de l'ailette (2b) est orientée vers l'avant du projectile (100) et une position sortie. Ce dispositif (1) comporte au moins une masselotte (4) apte à se mouvoir parallèlement à l'axe longitudinal (7) du projectile (100) sous l'action de l'accélération axiale du projectile (100) développée lors du tir, dispositif caractérisé en ce que la masselotte (4) est maintenue en appui lors du tir contre une surface d'appui (5) du pied (2a) de l'ailette (2) en position rentrée s'opposant ainsi au déploiement de l'ailette (2) vers sa position sortie. The invention relates to a stabilizing device (1) for equipping a projectile (100) fired by a gun and such a projectile equipped with said device. This device comprises at least one fin (2), pivotable about an axis of rotation (3) perpendicular to the longitudinal axis (7) of the projectile between a retracted position where the free end of the fin (2b) is facing the front of the projectile (100) and an extended position. This device (1) comprises at least one flyweight (4) able to move parallel to the longitudinal axis (7) of the projectile (100) under the action of the axial acceleration of the projectile (100) developed during the firing, device characterized in that the weight (4) is maintained in support when fired against a bearing surface (5) of the foot (2a) of the fin (2) in the retracted position thus opposing the deployment of the fin (2) to its extended position.