GATE DRIVING UNIT, GATE DRIVING METHOD, GATE DRIVING CIRCUITRY AND DISPLAY DEVICE

The present disclosure provides a gate driving unit, a gate driving method, a gate driving circuitry and a display device. The gate driving unit includes a reverse-phase gate driving signal output end, a normal-phase gate driving signal output end, an input circuitry, an output control circuitry, an input node control circuitry and an output circuitry. The input circuitry is configured to control an input end to be electrically connected to an input node under the control of a first clock signal. The output control circuitry is configured to control a potential at an output node under the control of a potential at the input node and a second clock signal. The input node control circuitry is configured to control the potential at the input node in accordance with the potential at the output node under the control of the second clock signal. The output circuitry is configured to output a reverse-phase gate driving signal and output a normal-phase gate driving signal in accordance with the potential at the output node.

LAUNDRY TREATMENT APPARATUS

A laundry treatment apparatus includes a cabinet. The laundry treatment apparatus further includes an outer tub. The laundry treatment apparatus further includes a circulation duct that is configured to guide air circulating through the outer tub. The laundry treatment apparatus further includes an exhaust duct that is configured to guide air exhausted from the outer tub. The laundry treatment apparatus further includes an air suction duct that is configured to guide air from outside the laundry treatment apparatus into the outer tub. The laundry treatment apparatus further includes a fan that is configured to circulate air through the outer tub. The laundry treatment apparatus further includes a heater that is located in the circulation duct and that is configured to heat air entering the outer tub. The laundry treatment apparatus further includes a plurality of heat-exchanging tubes. The laundry treatment apparatus further includes a condensed water pipe.

PIXEL CIRCUIT, PIXEL DRIVING METHOD AND DISPLAY DEVICE

The present application provides a pixel circuit, a pixel driving method and a display device. The pixel circuit is to be coupled to a to-be-driven element. The pixel circuit includes a first energy storage circuit, a driving circuit, a light-emitting control circuit, a data writing circuit, and a compensation control circuit. The compensation control circuit is configured to, under control of a third control signal, control conduction between the first node and the first terminal of the driving circuit, and control conduction between the second node and the second terminal of the driving circuit.

SHIFT REGISTER CIRCUIT, ARRAY SUBSTRATE AND DISPLAY DEVICE

The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.

PIXEL CIRCUIT AND DRIVING METHOD THEREOF, DISPLAY PANEL AND DISPLAY APPARATUS

A pixel circuit includes a driving circuit, a first control circuit and a second control circuit. The driving circuit is configured to receive a data signal in response to a scan signal, and generate, in response to a first enable signal, a driving signal according to a first voltage and the data signal. The first control circuit is configured to: receive a first input signal in response to a first control signal, and transmit a third input signal in response to the first input signal; and receive a second input signal in response to a second control signal, and transmit a second enable signal in response to the second input signal. The second control circuit is configured to transmit the driving signal to an element to be driven in response to one of the third input signal and the second enable signal. 1. A pixel circuit , comprising:a driving circuit coupled to at least a data signal terminal, a scan signal terminal, a first voltage terminal and a first enable signal terminal, the driving circuit being configured to: receive a data signal received at the data signal terminal, in response to a scan signal received at the scan signal terminal; and generate, in response to a first enable signal received at the first enable signal terminal, a driving signal according to a first voltage at the first voltage terminal and the data signal;a first control circuit coupled to at least a second enable signal terminal, a first control signal terminal, a first input signal terminal, a second control signal terminal, a second input signal terminal and a third input signal terminal, the first control circuit being configured to: receive a first input signal received at the first input signal terminal in response to a first control signal received at the first control signal terminal, and transmit a third input signal received at the third input signal terminal in response to the first input signal; and receive a second input signal received at the second input signal terminal in ...

Display Panel, Control Method for Same, and Display Device

Disclosed are a display panel, a control method for the same, and a display device. The display panel includes: M rows and N columns of pixel units, N current data lines sequentially arranged along a row direction, and N time-length data lines sequentially arranged along the row direction. Each pixel unit includes a pixel circuit, the pixel circuit including a current data terminal and a time-length data terminal. An i th column of the current data lines and an i th column of the time-length data lines are respectively located on two sides of an i th column of pixel units, the current data terminals of the pixel circuits of the i th column of pixel units are electrically connected to the i th column of the current data lines.

PIXEL CIRCUIT, DRIVING METHOD THEREOF AND ELECTRONIC DEVICE

A pixel circuit, a driving method thereof and a light emitting device, and relates to the technical field of display. The pixel circuit comprises driving sub-circuit comprising a control terminal, first terminal and a second terminal, driving sub-circuit being configured to control driving signal flowing through the first terminal and second terminal according to signal of control terminal; first capacitor comprising first pole and second pole coupled to control terminal of driving sub-circuit; first data writing sub-circuit configured to write first initialization signal to first pole of first capacitor in response to first scanning signal, write first data signal into driving sub-circuit in response to first scanning signal, so that signal of control signal of driving sub-circuit changes with first data signal; second data writing sub-circuit configured to write second data signal to first pole of first capacitor in response to second scanning signal.

PIXEL CIRCUIT AND DRIVING METHOD THEREOF, DISPLAY PANEL AND DISPLAY APPARATUS

A pixel circuit includes a driving circuit, a first control circuit and a second control circuit. The driving circuit is configured to receive a data signal in response to a scan signal, and generate, in response to a first enable signal, a driving signal according to a first voltage and the data signal. The first control circuit is configured to: receive a first input signal in response to a first control signal, and transmit a third input signal in response to the first input signal; and receive a second input signal in response to a second control signal, and transmit a second enable signal in response to the second input signal. The second control circuit is configured to transmit the driving signal to an element to be driven in response to one of the third input signal and the second enable signal.

Reflective Display Panel, Driving Method Thereof, Control Method of Pixel Unit, and Reflective Display Device

The present application discloses a reflective display panel, a driving method thereof, a control method of a pixel unit and a reflective display device. The reflective display panel comprises: a base substrate, a reflective layer, first and second electrode layers, wherein the first electrode layer is on a side of the reflective layer distal to the base substrate, the second electrode layer is on a side of the first electrode layer distal to the base substrate and insulated from the first electrode layer, materials of the first and second electrode layers are each an electro-optic material, and orthogonal projections of the second and first electrode layers on the base substrate have overlapping areas corresponding to the pixel units. 1. A reflective display panel , having a plurality of pixel units and comprising:a base substrate;a reflective layer on a side of the base substrate;a first electrode layer on a side of the reflective layer distal to the base substrate, a material of the first electrode layer being an electro-optic material; anda second electrode layer on a side of the first electrode layer distal to the base substrate and insulated from the first electrode layer, a material of the second electrode layer being an electro-optic material, wherein an orthogonal projection of the second electrode layer on the base substrate and an orthogonal projection of the first electrode layer on the base substrate overlap to form overlapping areas each corresponding to one of the plurality of pixel units.2. The reflective display panel according to claim 1 , wherein the first electrode layer comprises a number of first strip-like electrodes parallel to each other;the second electrode layer comprises a number of second strip-like electrodes parallel to each other; andthe first strip-like electrodes intersect with the second strip-like electrodes.3. The reflective display panel according to claim 2 , wherein the first strip-like electrodes are perpendicular to the ...

DISPLAY APPARATUSES, PIXEL CIRCUITS AND METHODS OF DRIVING PIXEL CIRCUIT

The present disclosure provides a display apparatus, a pixel circuit and a method of driving a pixel circuit. In one or more embodiments, the pixel circuit includes a driving transistor, a data signal module and a bias signal module. A first electrode of the driving transistor is connected with a first power signal terminal, a second electrode of the driving transistor is connected with a first terminal of a light emitting element, and the driving transistor includes a first control electrode and a second control electrode. The data signal module is connected with the driving transistor, a data writing signal terminal and a data signal terminal. The bias signal module is connected with the driving transistor, a bias writing signal terminal and a bias signal terminal, and is configured to adjust a threshold voltage of the driving transistor under control of the bias writing signal terminal and the bias signal terminal.

LAUNDRY DRYING MACHINE AND CONTROLLING METHOD OF LAUNDRY DRYING MACHINE

Disclosed herein is a method of controlling a laundry dryer for generating high-temperature steam through a steam part and controlling each of rotation of a drum and rotation of a circulation fan. The method includes a steam drying procedure drying operation of increasing an internal temperature of the drum to dry an object to be dried, a steam drying procedure steam supply operation of supplying steam into the drum after the steam drying procedure drying operation, and a re-drying operation of supplying hot air into the drum after the steam drying procedure steam supply operation. When steam is sprayed from the steam part, the rotation of the drum is maintained, the rotation of the circulation fan is stopped, such that the steam is evenly supplied to the object to be dried, damage to the object is prevented, and sterilization of the object is enhanced. 1. A laundry dryer comprising:a cabinet that defines an exterior of the laundry dryer;a drum rotatably disposed inside the cabinet and configured to receive an object to be dried;a duct part configured to guide air discharged from the drum and to supply the air to the drum;a circulation fan configured to move the air along the duct part;a heat exchanger disposed at the duct part and configured to perform heat exchange with the air guided along the duct part;a compressor configured to compress refrigerant that is configured to exchange heat with the air guided along the duct part;a steam part configured to generate steam and to supply the steam into the drum; anda controller configured to control the drum, the circulation fan, the compressor, and the steam part,wherein the controller is configured to, while supplying the steam into the drum through the steam part, rotate the drum and stop rotation of the circulation fan.2. The laundry dryer of claim 1 , wherein the controller is configured to claim 1 , while supplying the steam into the drum through the steam part claim 1 , stop driving the compressor.3. The laundry ...

Gate Driver on Array Circuit and Driving Method Thereof, and Display Device

The present invention discloses a gate driver on array circuit and a driving method thereof, and a display device. The gate driver on array circuit comprises a first gate driver on array sub-circuit and a second gate driver on array sub-circuit; the first gate driver on array sub-circuit is configured to drive in a first working state which is a state in which no defect occurs in the first gate driver on array sub-circuit; the second gate driver on array sub-circuit is configured to drive in a second working state which is a state in which a defect occurs in the first gate driver on array sub-circuit. The present invention improves the yield rate of the gate driver on array circuit. 1. A gate driver on array circuit , comprising a first gate driver on array sub-circuit and a second gate driver on array sub-circuit;the first gate driver on array sub-circuit is configured to drive gate lines in a first working state, wherein the first working state is a state in which no defect occurs in the first gate driver on array sub-circuit;the second gate driver on array sub-circuit is configured to drive the gate lines in a second working state, wherein the second working state is a state in which a defect occurs in the first gate driver on array sub-circuit.2. The gate driver on array circuit of claim 1 , wherein the first gate driver on array sub-circuit is configured to perform driving when no defect occurs therein and to stop driving when a defect occurs therein;the second gate driver on array sub-circuit is configured to perform driving when the first gate driver on array sub-circuit stops driving due to occurrence of a defect in the first gate driver on array sub-circuit.3. The gate driver on array circuit of claim 1 , wherein the first gate driver on array sub-circuit and the second gate driver on array sub-circuit each include a plurality of cascaded shift registers claim 1 , and output signal terminals of the shift registers in the first gate driver on array sub- ...

Pixel Circuit and Drive Method for Same, and Display Panel and Drive Method for Same

Disclosed are a pixel circuit and a drive method for the same, and a display panel and a drive method for the same. The pixel circuit is configured to drive a light-emitting element to emit light, including: a current control sub-circuit and a time-length control sub-circuit. The current control sub-circuit is electrically connected to a current data terminal, a scanning signal terminal, a reset signal terminal, an initial signal terminal, a light-emitting signal terminal, a first power terminal, a first node, and a second node, respectively. The time-length control sub-circuit is electrically connected to a first control terminal, a second control terminal, a time-length data terminal, a ground terminal, a light-emitting signal terminal, a high-frequency input terminal, and the first node, respectively.

SHIFT REGISTER, GOA CIRCUIT CONTAINING THE SAME, AND RELATED DISPLAY DEVICE

The present disclosure provides a shift register, including: an input unit, an output control unit, a first pull-down unit, a second pull-down unit, a reset unit, and a pull-down control unit. The input unit comprises a control terminal connected to a signal input terminal, a first terminal connected to a first voltage terminal, and a second terminal connected to a first node. The output control unit comprises a control terminal connected to the first node, a first terminal connected to a first clock signal terminal, and a second terminal connected to a signal output terminal. The first pull-down unit comprises a control terminal connected to a second node, a first terminal connected to the first node, and a second terminal connected to a compensation signal terminal. The second pull-down unit comprises a control terminal connected to the compensation signal terminal, and a first terminal connected to the second node.

SHIFT REGISTER AND DRIVING METHOD THEREOF, GATE DRIVER AND DISPLAY DEVICE

A shift register includes: an input circuit for transmitting an input signal to a first node under control of a first clock signal, and for transmitting the first clock signal to the second node under control of a level of the first node; a control circuit for transmitting a second power supply signal to the first node under control of a level of the second node and a second clock signal, for transmitting the second clock signal to the third node under control of a level of the fourth node and/or the first; a pull-down control circuit; and an output circuit for transmitting the fourth power supply signal or the third power supply signal to the signal output terminal. The pull-down control circuit controls a level of the fifth node regardless of the first clock signal.

PIXEL CIRCUIT AND CONTROL METHOD THEREFOR, DISPLAY SUBSTRATE AND DISPLAY DEVICE

This disclosure discloses a pixel circuit and a control method therefor, a display substrate and a display device. The pixel circuit comprises a first transistor, a second transistor, a third transistor, a storage capacitor and a light-emitting element. The pixel circuit further comprises a first sensing circuit and a second sensing circuit, wherein the first sensing circuit is connected in parallel with the first transistor, and the second sensing circuit is connected in parallel with the second transistor; a first sensing signal and a second sensing signal are respectively input to the first sensing circuit and the second sensing circuit for completing acquisition of electrical parameters of the pixel circuit according to the first sensing signal and the second sensing signal. 1. A pixel circuit comprising:a first transistor, a second transistor, a third transistor, a storage capacitor and a light-emitting element; wherein a control electrode of the first transistor is connected to a first scanning line, first and second electrodes of the first transistor are respectively connected to a data line and a control electrode of the third transistor, a control electrode of the second transistor is connected to a second scanning line, first and second electrodes of the second transistor are respectively connected to a second electrode of the third transistor and a sensing line, a first electrode of the third transistor is connected to a first power supply terminal, first and second ends of the storage capacitor are respectively connected to the control electrode of the third transistor and the first electrode of the second transistor, and first and second electrodes of the light-emitting element are respectively connected to the second electrode of the third transistor and a second power supply terminal; anda first sensing circuit and a second sensing circuit, wherein the first sensing circuit is connected in parallel with the first transistor, and the second sensing ...

DISPLAY SUBSTRATE AND DRIVING METHOD THEREFOR, AND DISPLAY APPARATUS

A display substrate a driving method therefor, and a display apparatus. The display substrate comprises: M rows and N columns of sub-pixels, N data signal lines and a data reset circuit, wherein at least one sub-pixel comprises a pixel circuit; an ith data signal line is connected to pixel circuits in an ith column, where M≥1, N≥1, and 1≤i≤N; and the data reset circuit is electrically connected to a data reset control end, a data initial signal end and the N data signal lines, and is configured to provide a signal of the data initial signal end to the N data signal lines under the control of the data reset control end.

GATE DRIVE UNIT CIRCUIT, GATE DRIVE CIRCUIT, DISPLAY DEVICE AND DRIVING METHOD

The present application relates to a gate drive unit circuit, comprising an input unit, an output unit, a pull-up node control unit, a pull-down node control unit and a pull-down unit. The input unit is used for transmitting a signal inputted by a first input signal terminal to a first node. The pull-up node control unit is used for transmitting a signal inputted by a first voltage terminal or a second voltage terminal to a pull-up node. The output unit is used for transmitting a signal inputted by a first control signal terminal to an output signal terminal. The pull-down node control unit is used for transmitting the input inputted by the first voltage terminal or the second voltage terminal to a pull-down node. The pull-down unit is used for transmitting a signal inputted by the second voltage terminal to the output signal terminal. 1. (canceled)2. A gate drive unit circuit , comprising an input unit , an output unit , a pull-up node control unit , a pull-down node control unit and a pull-down unit , wherein:the input unit is connected to the pull-up node control unit and the pull-down node control unit through a first node, the pull-up node control unit is connected to the output unit through a pull-up node, and the pull-down node control unit is connected to the pull-up node control unit and the pull-down unit through a pull-down node,the input unit is connected to a first input signal terminal, a first control terminal and the first node, for transmitting a signal inputted by the first input signal terminal to the first node under control of a signal inputted by the first control terminal,the pull-up node control unit is connected to the first node, the pull-up node, the pull-down node, a first voltage terminal and a second voltage terminal, for transmitting a signal inputted by the first voltage terminal or the second voltage terminal to the pull-up node under control of the first node and the pull-down node,the output unit is connected to the pull-up node, a ...

Shift Register and Driving Method Thereof, Gate Drive Circuit and Display Apparatus

A shift register, a gate drive circuit, a display apparatus and a driving method of the shift register are provided. The shift register includes an input subcircuit, a first and a second output subcircuits, a trigger signal input terminal, a first and a second signal output terminals, a first and a second clock terminals and a pull-up node, a control terminal and an output terminal of the input subcircuit are electrically coupled to the trigger signal input terminal and the pull-up node, respectively, for providing a valid signal received by the control terminal of the input subcircuit to the pull-up node. The shift register is provided with the first and second output subcircuits which share the same input subcircuit, greatly reducing the number of devices and thus greatly simplifying the structure of the cascaded shift registers and reducing the area of the whole display apparatus. 1. A shift register , comprising an input subcircuit , a first output subcircuit , a second output subcircuit , a trigger signal input terminal , a first signal output terminal , a second signal output terminal , a first clock terminal , a second clock terminal and a pull-up node , whereina control terminal and an output terminal of the input subcircuit are electrically coupled to the trigger signal input terminal and the pull-up node, respectively, for providing a valid signal received by the control terminal of the input subcircuit to the pull-up node;a control terminal, an input terminal and an output terminal of the first output subcircuit are electrically coupled to the pull-up node, the first clock terminal and the first signal output terminal, respectively, for providing a signal at the first clock terminal to the first signal output terminal under the control of the valid signal at the pull-up node; anda control terminal, an input terminal and the output terminal of the second output subcircuit are electrically coupled to the pull-up node, the second clock terminal and the ...

SHIFT REGISTER UNIT AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT AND DISPLAY DEVICE

The present disclosure provides a shift register unit and a driving method thereof, a gate driving circuit and a driving method thereof, and a display device. The shift register unit includes: a first shift register, a second shift register and a switch control circuit, signal input terminals of the first and second shift registers are coupled to a cascade signal input terminal through the switch control circuit, the switch control circuit is configured to allow a current between the signal input terminal of the first shift register and the cascade signal input terminal or not, and allow a current between the signal input terminal of the second shift register and the cascade signal input terminal or not; the first shift register and the second shift register are configured such that at least one of them operates upon receiving a cascade signal provided by the cascade signal input terminal.

PIXEL COMPENSATION CIRCUIT, DRIVING METHOD THEREOF, DISPLAY PANEL, AND DISPLAY DEVICE

The present disclosure discloses a circuit, a driving method thereof, a display panel and a display device. The circuit may include: a signal control module, a compensation control module, an initialization module, a data writing module, a driving control module, and a light emitting device. With the signal control module which is cooperated with other modules, the threshold voltage compensation time of the driving transistor can be increased, and the threshold voltage compensation can be ensured, thereby improving the image display quality. 1. A circuit comprising:a light emitting device;{'b': '4', 'a data writing module () having a control terminal connected to a first signal terminal, an input terminal connected to a data signal terminal, and an output terminal connected to a first node (A), wherein the data writing module is configured to provide a signal at the data signal terminal to the first node under control of a signal at the first signal terminal;'}{'b': '1', 'a signal control module () having a first input terminal connected to the first signal terminal, second input terminal(s) respectively connected to second signal terminal(s), and an output terminal connected to a second node (B); wherein the signal control module is configured to provide a control signal to the second node based on the signal at the first signal terminal and signal(s) at the respective second signal terminal(s);'}{'b': '2', 'a compensation control module () having a control terminal connected to the second node, an input terminal connected to a third node (C), and an output terminal connected to a fourth node (D); wherein the compensation control module is configured to connect the third node and the fourth node under control of the signal at the second node;'}{'b': '3', 'an initialization module () having a control terminal connected to a reset signal terminal, an input terminal connected to an initialization signal terminal, and an output terminal connected to the fourth node (D ...

DISPLAY BACK PLATE AND METHOD FOR MANUFACTURING SAME, DISPLAY PANEL AND DISPLAY DEVICE

A drive back plate is provided. The drive back plate includes a base substrate, and a drive circuit and a bonding structure disposed on the base substrate. The drive circuit includes a target drive structure, and a film layer disposed on at least one side of the target drive structure and adjacent to the target drive structure in the drive back plate is an inorganic insulating layer. The bonding structure is disposed on the same layer as the target drive structure, and the material of the bonding structure is the same as the material of the target drive structure.

GATE DRIVER ON ARRAY CIRCUIT, DRIVING METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SAME

The present invention discloses a Gate-driver-On-Array (GOA) circuit and the driving method thereof and a display device. The GOA circuit comprises a driving module, a low-resolution module and at least two high-resolution modules, the driving module being connected with the low-resolution module and the at least two high-resolution modules respectively; wherein, the driving module is used to output control signal to the low-resolution module and the high-resolution modules; the low-resolution module is used to output a low-resolution signal to at least two rows of pixels under the control of the control signal during low-resolution display; and each high-resolution module is used to output a high-resolution signal to corresponding one row of pixels under the control of the control signal during high-resolution display. The GOA circuit of the present invention may be used to drive multiple rows of pixels and implement the switching between low resolution display and high resolution display. 1. A Gate driver On Array (GOA) circuit , comprising:a driving module, a low-resolution module and at least two high-resolution modules, the driving module being connected with the low-resolution module and the at least two high-resolution modules, respectively; wherein,the driving module is used to output a control signal to the low-resolution module and each of the high-resolution modules;the low-resolution module is used to output a low-resolution signal to at least two rows of pixels under the control of the control signal during low-resolution display; andeach of the at least two high-resolution modules is used to output a high-resolution signal to corresponding one row of pixels under the control of the control signal during high-resolution display.2. The GOA circuit according to claim 1 , wherein the low-resolution module includes:a low-resolution signal generation unit which is used to generate the low-resolution signal according to a first clock signal under the control ...

LAUNDRY TREATMENT APPARATUS

A laundry treatment apparatus includes a circulation flow channel, which is divided into a first branch flow channel and a second branch flow channel so as to circulate air in a treatment chamber, a condenser disposed in the first branch flow channel, a heat radiation part for heating flowing air that has passed through the condenser, and a heat absorption part disposed in the second branch flow channel, wherein the heat radiation part and the heat absorption part constitute a thermoelectric heat pump device.

PIXEL CIRCUIT AND METHOD FOR DRIVING SAME, DISPLAY PANEL, AND DISPLAY DEVICE

Provided are a pixel circuit and a method for driving the same, a display panel and a display device. A drive circuit (04) in the pixel circuit is capable of controlling conduction/non-conduction between a second node (N2) and a third node (N3) under the control of a potential of a first node (N1). A light-emission control circuit (03) in the pixel circuit is capable of controlling conduction/non-conduction between a cathode of a light-emitting element and a second node (N2), and controlling conduction/non-conduction between the third node (N3) and a pull-down power terminal (LVSS) under the control of a potential of a light-emission control signal; and a potential of the first node (N1) is not be affected by a potential of an anode of the light-emitting element. Furthermore, in the case that the cathode of the light-emitting element and the second node (N2) are conducted, the second node (N2) and the third node (N3) are conducted, and the third node and the pull-down power terminal (LVSS) are conducted, the light-emitting element can emit light reliably.

GAMMA REFERENCE VOLTAGE GENERATING CIRCUIT, METHOD FOR MEASURING VOLTAGE-TRANSMISSION CURVE AND DISPLAY DEVICE

The present disclosure provides a gamma reference voltage generating circuit including a center voltage generation unit, a gamma reference voltage generation unit configured to generate positive and negative gamma reference voltages and control the positive gamma reference voltage and the negative gamma reference voltage to be symmetrical with respect to the center voltage; a first voltage divider unit including a first terminal for receiving the positive gamma reference voltage and a second terminal for receiving the center voltage; and a second voltage divider unit including a first terminal coupled with the second terminal of the first voltage divider unit and a second terminal for receiving the negative gamma reference voltage. 1. A gamma reference voltage generating circuit used to provide a gamma reference voltage for a source driver; the gamma reference voltage comprising a positive gamma reference voltage and a negative gamma reference voltage; the gamma reference voltage generating circuit comprising:a center voltage generation unit configured to generate a center voltage;a gamma reference voltage generation unit configured to generate the positive gamma reference voltage and the negative gamma reference voltage, and control the positive gamma reference voltage and the negative gamma reference voltage to be symmetrical with respect to the center voltage;a first voltage divider unit comprising a first terminal for receiving the positive gamma reference voltage and a second terminal for receiving the center voltage; the first voltage divider unit being configured to divide a voltage between the positive gamma reference voltage and the center voltage; anda second voltage divider unit comprising a first terminal for receiving the center voltage, and a second terminal for receiving the negative gamma reference voltage; the second voltage divider unit being configured to divide a voltage between the center voltage and the negative gamma reference voltage.2. The ...

SHIFT REGISTER UNIT AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT AND DISPLAY DEVICE

The present disclosure relates to a shift register unit and driving method thereof, a gate driving circuit and a display device. The shift register unit comprises: an input module for controlling a level of a first node based on a scan pulse, an output module for controlling a scan pulse output based on the level of the first node, a reset module for resetting the first node and the scan pulse output, and a control module for generating a reset trigger signal, wherein the reset module further resets the first node based on the reset trigger signal. The shift register units can be cascaded to form a gate driving circuit to realize output of multiple scan pulses. By integrating such a gate driving circuit on the array substrate, area of the bezel region of the array substrate can be reduced, thereby facilitating bezel narrowing of a display device. At the same time, due to presence of the control module, the reset module is enabled to reset the first node more stably while normal output of the scan pulse is maintained. 1. A shift register unit , comprising:an input module, connected to a scan pulse input and a first node, and adapted to control a level of the first node based on a scan pulse inputted on the scan pulse input;an output module, connected to a first clock signal input, the first node and a scan pulse output, and adapted to selectively set the scan pulse output at a level of a clock signal inputted on the first clock signal input based on the level of the first node;a reset module, connected to a first reset control signal input and the first node, and adapted to reset the first node and the scan pulse output based on a level of the first reset control signal input; anda control module, connected to the first node, the first clock signal input, a second clock signal input, a third clock signal input and the reset module, and adapted to, when the first node is at a second level, generate a reset trigger signal based on relative level relation(s) among clock ...

LIGHT-EMITTING DRIVING CIRCUIT AND DRIVING METHOD THEREOF, AND LIGHT-EMITTING APPARATUS

A light-emitting driving circuit includes a driving sub-circuit, a control sub-circuit, a data writing sub-circuit and a compensation sub-circuit. The control sub-circuit is configured to initialize voltages of a first node and a control terminal of the driving sub-circuit in response to a second scan signal. The data writing sub-circuit is configured to write a data signal into a first terminal of the driving sub-circuit in response to a first scan signal. The driving sub-circuit is configured to output, from a second terminal of the driving sub-circuit, the data signal and a compensation signal. The compensation sub-circuit is configured to transmit the data signal and the compensation signal to the first node in response to the first scan signal, and adjust the voltage of the control terminal according to the data signal, the compensation signal, the initialized voltages of the first node and the control terminal. 1. A light-emitting driving circuit , comprising:a driving sub-circuit;a control sub-circuit coupled to a first node and a control terminal of the driving sub-circuit;a data writing sub-circuit coupled to a first terminal of the driving sub-circuit; anda compensation sub-circuit coupled to the first node, the control terminal of the driving sub-circuit and a second terminal of the driving sub-circuit, whereinthe control sub-circuit is configured to initialize a voltage of the first node and a voltage of the control terminal of the driving sub-circuit in response to a second scan signal;the data writing sub-circuit is configured to write a data signal into the first terminal of the driving sub-circuit in response to a first scan signal;the driving sub-circuit is configured to output, from the second terminal of the driving sub-circuit, the data signal and a compensation signal;the compensation sub-circuit is configured to transmit the data signal and the compensation signal to the first node in response to the first scan signal, and to adjust the voltage ...

PIXEL CIRCUIT, ARRAY SUBSTRATE, DISPLAY PANEL AND ELECTRONIC APPARATUS

A pixel circuit, an array substrate, a display panel and an electronic apparatus are provided. The pixel circuit includes: a data writing sub-circuit, a first data storage sub-circuit, a second data storage sub-circuit and a light-emitting control sub-circuit. The data writing sub-circuit writes, under the control of a signal input from a first control signal input end, to the first data storage sub-circuit a data signal input from a data signal input end, and writes, under the control of a signal input from a second control signal input end, to the second data storage sub-circuit the data signal input from the data signal input end. The light-emitting control sub-circuit controls on/off states of corresponding thin film transistors in accordance with data signals output from the first data storage sub-circuit and the second data storage sub-circuit, so that different gray-scales may be rendered. 1. A pixel circuit , comprising: a data writing sub-circuit , a first data storage sub-circuit , a second data storage sub-circuit and a light-emitting control sub-circuit;the data writing sub-circuit is connected to a data signal input end, a first control signal input end, a second control signal input end, the first data storage sub-circuit and the second data storage sub-circuit, and is configured to write, under the control of a signal input from the first control signal input end, to the first data storage sub-circuit a data signal input from the data signal input end, and write, under the control of a signal input from the second control signal input end, to the second data storage sub-circuit the data signal input from the data signal input end;the first data storage sub-circuit is connected to the data writing sub-circuit and a first node, and is configured to store the data signal written by the data writing sub-circuit and output the data signal to the first node;the second data storage sub-circuit is connected to the data writing sub-circuit, the first node, a ...

COOKING APPLIANCE

A cooking appliance includes a main body forming a machine room; a cooking chamber arranged below the machine room; an intermediate flow path including a first suction port and formed between the machine room and the cooking chamber; and a fan configured to suction air into the intermediate flow path, wherein the machine room includes a second suction port through which air is suctioned, and an opening portion connected to the intermediate flow path, the opening portion includes a first opening portion and a second opening portion arranged at a farther distance from the fan than the first opening portion, and the second opening portion has an area larger than an area of the first opening portion.

SHIFT REGISTER UNIT, SHIFT REGISTER, DISPLAY PANEL AND DISPLAY DEVICE

A shift register unit includes: a discharging TFT, a source electrode and a drain electrode of which are connected to a first low level signal input end and a pull-up node respectively; and a first discharging control unit connected to a gate electrode of the discharging TFT and configured to output a first control signal to the gate electrode of the discharging TFT between a first and a second time points, so as to enable the discharging TFT to be in an on state and output a first low level signal to the pull-up node, thereby to discharge the pull-up node. The first time point is a time point when the processing of a first frame by the shift register is ended, and the second time point is a time point when the processing of a second frame adjacent to the first frame by the shift register is started. 1. A shift register unit , a plurality of which is cascaded to form a shift register , the shift register unit comprising a bootstrapping capacitor connected between a current-level driving output node and a pull-up node ,the shift register unit further comprising:a first low level signal input end configured to receive a first low level signal;a discharging thin film transistor (TFT), a source electrode and a drain electrode of which are connected to the first low level signal input end and the pull-up node respectively; anda first discharging control unit connected to a gate electrode of the discharging TFT and configured to output a first control signal to the gate electrode of the discharging TFT between a first time point and a second time point, so as to enable the discharging TFT to be in an on state, thereby to output the first low level signal to the pull-up node and discharge the pull-up node,wherein the first time point is a time point when processing of a first frame by the shift register is ended, and the second time point is a time point when processing of a second frame adjacent to the first frame by the shift register is started.2. The shift register ...

PIXEL DRIVE CIRCUIT, METHOD FOR DRIVING THE SAME, AND DISPLAY DEVICE

Embodiments of the present disclosure provide a pixel drive circuit, a method for driving the pixel drive circuit, and a display device. The pixel drive circuit includes: a drive sub-circuit, a write sub-circuit and a control circuit. The control circuit further is coupled to a light-emitting control signal terminal, a second scanning signal terminal and a second data signal terminal, and is configured to determine a duration of providing a driving signal to a to-be-driven element under control of a light-emitting control signal provided by the light-emitting control signal terminal and a second scanning signal provided by the second scanning signal terminal.

GATE DRIVER CIRCUIT, ITS DRIVING METHOD, ARRAY SUBSTRATE AND DISPLAY DEVICE

The present disclosure provides a gate driver circuit including at least one set of clock signal lines and multiple levels of shift registers arranged in a cascaded manner. Each set of the clock signal lines includes two clock signal lines. The multiple levels of shift registers is divided into at least one set, and each set of the clock signal lines corresponds to a set of the shift registers. One clock signal line in each set of the clock signal lines is connected to a resetting signal input end of a last-level shift register in the set of the shift registers corresponding to the set of the clock signal lines. The present disclosure further provides an array substrate, a display device and a method for driving the gate driver circuit. 1. A gate driver circuit , comprising at least one set of clock signal lines and multiple levels of shift registers arranged in a cascaded manner , each set of the clock signal lines comprising two clock signal lines , the multiple levels of shift registers being divided into at least one set , and each set of the clock signal lines corresponding to a set of the shift registers , wherein one clock signal line in each set of the clock signal lines is connected to a resetting signal input end of a last-level shift register in the set of the shift registers corresponding to the set of the clock signal lines , so as to provide a resetting signal to the resetting signal input end of the last-level shift register in the set of the shift registers at the beginning of a resetting stage.2. The gate driver circuit according to claim 1 , wherein the gate driver circuit comprises an even number of levels of the shift registers claim 1 , a set of odd-numbered clock signal lines and a set of even-numbered clock signal lines;the set of odd-numbered clock signal lines comprises a first odd-numbered clock signal line and a second odd-numbered clock signal line, and the set of even-numbered clock signal lines comprises a first even-numbered clock ...

DRIVING CIRCUIT, DRIVING CONTROL METHOD AND DISPLAY PANEL

The present application discloses a driving circuit and a display panel. The driving circuit includes a driving current generation circuit and a light emitting time control circuit. The driving current generation circuit is connected to a first reference voltage terminal, a data voltage terminal and the light emitting time control circuit, and is configured to generate a driving current under the control of the first reference voltage terminal and the data voltage terminal, and transmit the driving current to the light emitting time control circuit. The light emitting time control circuit is connected to the driving current generation circuit, a time control signal terminal, a reference signal terminal and a light emitting element, and is configured to control a duration of transmitting the driving current to the light emitting element under the control of the time control signal terminal and the reference signal terminal.

COOKER

Disclosed is a cooking apparatus with a cooktop. The cooking apparatus includes: a cooker body including a cooking compartment and a storage compartment below the cooking compartment; a drawer including a storage space, and sliding the drawer into and out of the storage compartment closes and opens the storage space; a steam supplier configured to generate steam and supply the generated steam to the cooking compartment; and a water tank configured to store water for generating the steam, and provided in a certain region of the storage compartment independently of the drawer to be pushed in or pulled out.

PIXEL DRIVING STRUCTURE AND DISPLAY PANEL

The present disclosure provides a pixel driving structure and a display panel. The pixel driving structure includes a pulse width modulation driving circuit, a pulse amplitude modulation driving circuit, and a buffer circuit. The pulse width modulation driving circuit is configured to control a pulse width of a driving current supplied to the light emitting device to be driven according to a pulse width modulation data voltage; the pulse amplitude modulation driving circuit is configured to control an amplitude of the driving current supplied to the light emitting device to be driven according to a pulse amplitude modulation data voltage; and the buffer circuit is electrically coupled between the pulse width modulation driving circuit and the pulse amplitude modulation driving circuit and is configured to adjust a rate at which the pulse width modulation driving circuit applies a pulse width modulation voltage to the pulse amplitude modulation driving circuit. 1. A pixel driving structure , comprising:a pulse width modulation driving circuit configured to control a pulse width of a driving current supplied to a light emitting device to be driven according to a pulse width modulation data voltage;a pulse amplitude modulation driving circuit configured to control an amplitude of the driving current supplied to the light emitting device to be driven according to a pulse amplitude modulation data voltage; anda buffer circuit electrically coupled between the pulse width modulation driving circuit and the pulse amplitude modulation driving circuit for adjusting a rate at which the pulse width modulation driving circuit applies a pulse width modulation voltage to the pulse amplitude modulation driving circuit.2. The pixel driving structure according to claim 1 , wherein the pulse amplitude modulation driving circuit comprises a first driving transistor and a first storage capacitor; wherein claim 1 ,a first electrode of the first storage capacitor is electrically coupled ...

LAUNDRY TREATMENT APPARATUS

Disclosed is a laundry treatment apparatus equipped with an exhaust type drying system, which is capable of not only enhancing drying efficiency while reducing consumption of energy and cooling water required to dry laundry, but also achieving smooth exhaust of air even when a water trap is formed in a drainage duct. The laundry treatment apparatus includes a casing, an outer tub, an inner tub, a drainage duct for guiding wash water stored in the outer tub to be discharged to the outside of the casing, a first exhaust duct connected, at one end thereof, to the drainage duct, to guide air present in the outer tub into the drainage duct, and a second exhaust duct upwardly branched from the drainage duct, to exhaust air present in the drainage duct to the outside of the outer tub or the outside of the cashing. 1. A laundry treatment apparatus comprising:a casing;an outer tub disposed within the casing, to store wash water;an inner tub disposed within the outer tub, to receive laundry;a drainage duct for guiding wash water stored in the outer tub to be discharged to the outside of the casing;a first exhaust duct connected, at one end thereof, to the drainage duct, to guide air present in the outer tub into the drainage duct; anda second exhaust duct upwardly branched from the drainage duct, to exhaust air present in the drainage duct to the outside of the outer tub or the outside of the cashing.2. The laundry treatment apparatus according to claim 1 , further comprising:a circulation duct for guiding a portion of air present in the outer tub to be re-supplied to the outer tub after being discharged from the outer tub.3. The laundry treatment apparatus according to claim 2 , further comprising:a fan provided at the circulation duct, to circulate air present in the outer tub.4. The laundry treatment apparatus according to claim 1 , further comprising:a heater for heating air introduced into the outer tub.5. The laundry treatment apparatus according to claim 1 , wherein ...

SUPPLEMENT RESETTING MODULE, GATE DRIVER CIRCUIT AND DISPLAY DEVICE

A supplement resetting module for a gate driver circuit, including a pull-up control unit, a pull-down control unit, a clock signal input end, a predetermined level input end, a first control signal input end, a second control signal input end and a signal output end. A control end of the pull-up control unit is connected to the clock signal input end, an output end of the pull-up control unit is connected to the signal output end, a first control end of the pull-down control unit is connected to the first control signal input end, a second control end of the pull-down control unit is connected to the second control signal input end, an input end of the pull-down control unit is connected to the predetermined level input end, and an output end of the pull-down control unit is connected to the signal output end. 14.-. (canceled)5. A gate driver circuit , comprising multiple levels of shift register units and 2N clock signal lines , whereinthe shift register unit at each level comprises an output resetting end and a pull-up node resetting end;the multiple levels of shift register units comprise display shift register units and resetting shift register units, and at least the shift register units at the latter N levels are the resetting shift register units, where N is a natural number greater than 0;among at least the multiple levels of shift register units including the display shift register units and a first-level resetting shift register unit of the resetting shift register units at the latter N levels, an output resetting end of a current-level shift register unit is connected to a pull-up node resetting end of a previous-level shift register unit;the gate driver circuit further comprises a first supplement resetting module, and at least the first-level resetting shift register unit of the resetting shift register units at the latter N levels corresponds to the first supplement resetting module;the first supplement resetting module comprises a first pull-up ...

LAUNDRY TREATMENT APPARATUS

A laundry treatment apparatus equipped with a thermoelectric module includes a thermoelectric element configured to emit heat from a first surface and to absorb heat through a second surface, 1. A laundry treatment apparatus equipped with a thermoelectric module , the apparatus comprising:a thermoelectric element having a first surface and a second surface that is opposite the first surface, the thermoelectric element being configured to emit heat from the first surface and to absorb heat through the second surface;a first heat exchange unit configured to contact the first surface of the thermoelectric element so as to undergo heat exchange with air upon receiving heat from the first surface;a heat transfer member having an interconnecting surface that is configured to contact the second surface of the thermoelectric element so as to be in a heat conducting relationship with the second surface; anda second heat exchange unit configured to contact the interconnecting surface of the heat transfer member, the second heat exchange unit being configured to undergo heat exchange with air upon receiving heat from the second surface of the thermoelectric element through the heat transfer member.2. The laundry treatment apparatus according to claim 1 , wherein the first heat exchange unit and the second heat exchange unit define a space therebetween claim 1 , the space being configured to prevent movement of condensed water from the second heat exchange unit to the first heat exchange unit.3. The laundry treatment apparatus according to claim 1 , wherein the first heat exchange unit and the second heat exchange unit are arranged in a line.4. The laundry treatment apparatus according to claim 1 , wherein the first heat exchange unit is configured to emit heat upon undergoing heat exchange with air claim 1 , and the second heat exchange unit is configured to absorb heat upon undergoing heat exchange with air.5. The laundry treatment apparatus according to claim 1 , wherein at ...

SHIFT REGISTER UNIT AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT, AND DISPLAY DEVICE

Disclosed is a shift register unit, including a first input circuit, an input control circuit, a pull-down control circuit, a pull-down circuit, an output circuit and a second input circuit. The first input circuit includes a first input sub-circuit, and is configured to, under control of the first signal input terminal, cause a voltage of the first voltage terminal to be output to a second terminal of the first input sub-circuit and output to the pull-up node via a first terminal thereof. The input control circuit is configured to pull down a potential of the second terminal to the potential of a first power supply voltage terminal under control of an enable signal terminal. 1. A shift register unit , comprising a first input circuit , an input control circuit , a pull-down control circuit , a pull-down circuit , an output circuit and a second input circuit;the first input circuit being connected to a first signal input terminal, a pull-up node, a first voltage terminal and the input control circuit, and comprises a first input sub-circuit, wherein the first input circuit is connected to the pull-up node via a first terminal of the first input sub-circuit and to the input control circuit via a second terminal of the first input sub-circuit, and the first input circuit being configured to, under control of the first signal input terminal, cause a voltage of the first voltage terminal to be output to the second terminal of the first input sub-circuit and output to the pull-up node via the first terminal of the first input sub-circuit;the input control circuit being also connected to a first power supply voltage terminal and an enable signal terminal; the input control circuit being configured to pull down a potential of the second terminal of the first input sub-circuit to a potential of the first power supply voltage terminal under control of the enable signal terminal;the pull-down control circuit being connected to a pull-down node, and the pull-down control ...

COOKING APPLIANCE

A cooking appliance includes a main body forming a machine room; a cooking chamber arranged below the machine room; an intermediate flow path including a first suction port and formed between the machine room and the cooking chamber; and a fan configured to suction air into the intermediate flow path, wherein the machine room includes a second suction port through which air is suctioned, and an opening portion connected to the intermediate flow path, the opening portion includes a first opening portion and a second opening portion arranged at a farther distance from the fan than the first opening portion, and the second opening portion has an area larger than an area of the first opening portion.

GATE DRIVING CIRCUIT AND A DRIVING METHOD THEREOF, AS WELL AS A DISPLAY DEVICE

The present invention provides a gate driving circuit and a driving method thereof, a display device, which relates to the field of display technology. The gate driving circuit may comprise a plurality of mutually cascaded shift register units and a pre-charging unit, the gate row drive scanning and touch control scanning of the plurality of mutually cascaded shift register units are performed alternately. By additionally arranging a pre-charging unit connected with the corresponding first stage of shift register unit when the gate row drive scanning is performed again after the touch control scanning is accomplished, the first stage of shift register unit can be pre-charged during the touch control scanning. In this way, the electric leakage phenomenon of the pull-up control node (PU point) of the corresponding first stage of shift register unit when the gate row drive scanning is performed again after the touch control scanning is accomplished due to a relatively long touch control scanning time interval between outputs of two rows of shift register units is avoided, thereby avoiding the defect of insufficient charging rate of row of pixels while ensuring touch control scanning of high report rate. 1. A gate driving circuit , characterized in that , comprising:a plurality of mutually cascaded shift register units located in a first region and a second region respectively, except for a first stage of shift register unit of the first region, a signal output terminal of each of the other shift register units is connected to a reset signal terminal of a previous stage of shift register unit adjacent to it, and except for the last stage of shift register unit of the second region, a signal output terminal of each of the other shift register units is connected to a signal input terminal of a next stage of shift register unit adjacent to it; anda pre-charging unit connected to a first stage of shift register unit of the second region,wherein gate row drive scanning and ...

SHIFT REGISTER UNIT, METHOD FOR DRIVING THE SAME, SHIFT REGISTER AND DISPLAY DEVICE

According to an embodiment of the present disclosure, a shift register unit may include: a first control module, configured to transmit a start signal to a first node; a second control module, configured to pull a potential of a second node to a potential different from a potential of the first node, under a control of a first clock signal; a carry output module, configured to output a carry signal according to the potential of the first node and the potential of the second node; and a shift output module, configured to output a shift signal according to the potential of the first node and the potential of the second node. 1. A shift register unit , comprising:a first control module, configured to transmit a start signal to a first node;a second control module, configured to pull a potential of a second node to a potential different from a potential of the first node, under a control of a first clock signal;a carry output module, configured to output a carry signal according to the potential of the first node and the potential of the second node; anda shift output module, configured to output a shift signal according to the potential of the first node and the potential of the second node.2. The shift register unit according to claim 1 , further comprising:an output feedback module, configured to maintain the potential of the first node by controlling the first control module according to the carry signal and the shift signal.3. The shift register unit according to claim 1 , further comprising:a reset module, configured to control the shift signal to be reset.4. The shift register unit according to claim 1 , whereinthe carry output module comprises a first carry output transistor and a second carry output transistor;a gate electrode of the first carry output transistor is connected to the first node, a first electrode of the first carry output transistor is connected to a carry signal output end, and a second electrode of the first carry output transistor is ...

SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DRIVING METHOD, AND DISPLAY APPARATUS

The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK/CLK, a second bias-control terminal to receive a second/first bias signal CLK/CLK, and a first control level terminal provided with a first control voltage VC, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK/CLK, a fourth bias-control terminal to receive a fourth/third bias signal CLK/CLK, and a second control level terminal provided with a second control voltage VC; configuring the first bias signal CLK and the second bias signal CLK as first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VC to a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLK and the fourth bias signal CLK to a turn-off level and the second control voltage VC to turn-on level during the first sub-cycle; configuring the third bias signal CLK and the fourth bias signal CLK as second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VC to a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock ...

Gate driving circuit and method for controlling the same, and display apparatus

The embodiments of the present disclosure provide a gate driving circuit and a method for controlling the same, and a display apparatus. The gate driving circuit includes: M decoding sub-circuits, wherein each of the M decoding sub-circuits has K signal input terminals and 2K signal output terminals, where K=N/M, M, N and K are positive integers, 4≤M<N, and K≥2, N signal input terminals of the M decoding sub-circuits are connected to receive N-bit address data, and each of the M decoding sub-circuits is configured to receive respective K-bit data in the N-bit address data at K signal input terminals thereof, and select one of the 2K signal output terminals thereof which matches the received K-bit data; and a plurality of driving sub-circuits, wherein each of the plurality of driving sub-circuits is connected to M signal output terminals belonging to the M decoding sub-circuits respectively according to an address allocated thereto, and is configured to output a row driving signal when the M signal output terminals connected to the driving sub-circuit are all selected.

SHIFT REGISTER CIRCUIT, AND DRIVING METHOD THEREOF, GATE DRIVE CIRCUIT AND DISPLAY DEVICE

A shift register circuit, a driving method thereof, a gate drive circuit and a display device are provided. The shift register circuit includes an input sub-circuit, an output sub-circuit, a discharge sub-circuit and a noise reduction sub-circuit. The input sub-circuit is connected to an input signal terminal, a first power source terminal and a pull-down node, and configured to, under the control of an input signal, output a first power source terminal signal to the pull-down node. In the shift register circuit, the discharge sub-circuit may control the potential of the pull-down node to be an ineffective potential at the input stage, thereby preventing the noise reduction sub-circuit from affecting the potentials of the pull-up node and the output terminal under the control of the pull-down node, and ensuring normal output of the shift register circuit. 1. A shift register circuit , comprising:an input sub-circuit, an output sub-circuit, a discharge sub-circuit and a noise reduction sub-circuit; whereinthe input sub-circuit is connected to an input signal terminal, a first control signal terminal and a pull-up node respectively, and configured to, under the control of an input signal from the input signal terminal, output a first control signal from the first control signal terminal to the pull-up node;the output sub-circuit is connected to a clock signal terminal, the pull-up node and an output terminal respectively, and configured to, under the control of the pull-up node, output a clock signal from the clock signal terminal to the output terminal;the discharge sub-circuit is connected to the input signal terminal, a first power source terminal and a pull-down node respectively, and configured to, under the control of the input signal, output a first power source signal from the first power source terminal to the pull-down node; andthe noise reduction sub-circuit is connected to the pull-down node, the first power source terminal, the pull-up node and the output ...

ARRAY SUBSTRATE, DRIVING METHOD THEREOF, AND DISPLAY APPARATUS

Disclosed is an array substrate including multiple first selection circuits with each including at least two first selection transistors and at least two first anticreeping transistors. Each first selection transistor is connected with one first anticreeping transistor in series. When the first selection transistor is turned on by a first turn-on signal from a first control signal terminal, the first anticreeping transistor is turned on by a second turn-on signal from a second control signal terminal. When the first selection transistor is turned off by a first turn-off signal from the first control signal terminal, the first anticreeping transistor is turned off to make the first selection transistors and the data signal terminal disconnected, by a second turn-off signal from the second control signal terminal. A voltage of the first turn-off signal is greater than a voltage of the second turn-off signal. 1. An array substrate , comprising:a plurality of first selection circuits, wherein each first selection circuit comprises at least two first selection transistors and at least two first anticreeping transistors, and each first selection transistor is correspondingly connected with one first anticreeping transistor of the at least two first anticreeping transistors in series; and when the first selection transistor is turned on under control of a first turn-on signal provided by a first control signal terminal, the first anticreeping transistor is turned on under control of a second turn-on signal provided by a second control signal terminal to form a conducting path between a data signal terminal and the first selection transistor; and', 'when the first selection transistor is turned off under control of a first turn-off signal provided by the first control signal terminal, the first anticreeping transistor is turned off under control of a second turn-off signal provided by the second control signal terminal to make the first selection transistor and the data ...

DRIVING CIRCUIT OF DISPLAY PANEL, DRIVING METHOD THEREOF, AND DISPLAY PANEL

The present disclosure is related to a driving circuit of a display panel. The driving circuit may include a turn-on voltage adjusting circuit. The turn-on voltage adjusting circuit may include a control subcircuit and a switching and voltage division subcircuit. The switching and voltage division subcircuit may include a switching subcircuit and a basic voltage division subcircuit. The switching subcircuit may be configured to perform voltage division of a signal outputted by the output terminal of the control subcircuit to form a voltage division feedback signal of the corresponding resolution under control of the control signal and output the voltage division feedback signal to the voltage division feedback node. 1. A driving circuit of a display panel , comprising:a turn-on voltage adjusting circuit, the turn-on voltage adjusting circuit comprising:a control subcircuit; and a switching subcircuit; and', 'a basic voltage division subcircuit;', 'wherein the switching subcircuit includes a control terminal, a first input terminal, a second input terminal and an output terminal; the control terminal of the switching subcircuit is configured to input a control signal of a corresponding resolution, the first input terminal thereof is electrically connected with an output terminal of the control subcircuit, the second input terminal is configured to access a ground power supply signal, and the output terminal thereof is electrically connected with a voltage division feedback node; and, 'a switching and voltage division subcircuit; the switching and voltage division sub circuit comprisingthe switching subcircuit is configured to perform voltage division of a signal outputted by the output terminal of the control subcircuit to form a voltage division feedback signal of the corresponding resolution under control of the control signal and output the voltage division feedback signal to the voltage division feedback node; andwherein the control subcircuit includes a first ...

FLEXIBLE DISPLAY PANEL, FLEXIBLE DISPLAY APPARATUS, AND DISPLAY CONTROL METHOD THEREOF

The present disclosure is related to a flexible display panel. The flexible display panel may include a display substrate, a plurality of pixel units arranged in an array on the display substrate, and at least a strain sensor on the display substrate. The strain sensor may be arranged corresponding to a region comprising at least one of the plurality of pixel units. The strain sensor may be configured to detect deformation in the region comprising at least one of the plurality of pixel units and to generate a detection signal. 1. A flexible display panel comprising:a display substrate;a plurality of pixel units arranged in an array on the display substrate; andat least one strain sensor on the display substrate,wherein the at least one strain sensor is configured to detect deformation of the flexible display panel.2. The flexible display apparatus according to claim 1 , wherein each of the at least one strain sensor corresponds to a region of the flexible display panel comprising a plurality of rows of pixel units and is configured to detect the deformation in the region of the flexible display panel.3. The flexible display panel according to claim 1 , wherein the at least one strain sensor comprises a plurality of strain sensors claim 1 , and the plurality of the strain sensors is arranged in a non-display region along a first direction.4. The flexible display panel according to claim 1 , wherein the strain sensor is a resistive strain sensor.5. The flexible display panel according to claim 4 , wherein the resistive strain sensor comprises a repeatedly folded strain resistance wire along the first direction with a plurality of folding portions and the plurality of folding portions are arranged along a second direction.6. The flexible display panel according to claim 4 , wherein the at least one strain sensor in the non-display region is configured to detect the deformation of the display panel along the second direction.7. The flexible display panel according to ...

SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DRIVING METHOD THEREOF, AND DISPLAY APPARATUS

Disclosed is a shift register unit, a gate driving circuit and a driving method, as well as a display apparatus. The shift register unit has a working cycle including an input phase, an output phase, a reset phase and a maintaining phase. In the reset phase, a clock signal is transmitted to an output terminal to pull a voltage of the output terminal down to a reference voltage, and the pulled-down voltage of the output terminal is subsequently changed from the reference voltage to a gate-off voltage. In the maintaining phase, the voltage of the output terminal is maintained at the gate-off voltage. The reference voltage is smaller than the gate-off voltage. 1. A shift register unit comprising:an input module configured to transmit an input signal to a pull-up node in an input phase to pull up a voltage of the pull-up node;an output module configured to a) in an output phase transmit a clock signal to an output terminal as a gate-on voltage and further pull up the voltage of the pull-up node by an amount, and to b) in a reset phase transmit the clock signal to the output terminal to pull a voltage of the output terminal down to a reference voltage and pull the voltage of the pull-up node down by the amount;a first reset module configured to further pull the pulled-down voltage of the pull-up node down to the reference voltage in response to a first reset signal in the reset phase; anda first pull-down control module configured to, responsive to a first pull-down control signal, a) change the pulled-down voltage of the output terminal from the reference voltage to a gate-off voltage in the reset phase, and b) maintain the voltage of the pull-up node at the reference voltage and the voltage of the output terminal at the gate-off voltage in a maintaining phase, the reference voltage being smaller than the gate-off voltage.2. The shift register unit of claim 1 , wherein the input module comprises a first transistor having a control terminal and a first terminal that both ...

PXIEL DRIVING CIRCUIT AND DRIVING METHOD THEREOF, ARRAY SUBSTRATE, DISPLAY PANEL, AND DISPLAY APPARATUS

A pixel driving circuit for a display apparatus. The pixel driving circuit may include a first gate line, a second gate line, a data line, a first thin-film transistor, and a second thin-film transistor. A gate of the first thin-film transistor may be coupled to the first gate line. A source of the first thin-film transistor may be coupled to the data line. A drain of the first thin-film transistor may be coupled to a source of the second thin-film transistor. A gate of the second thin-film transistor may be coupled to the second gate line. A drain of the second thin-film transistor may be coupled to a pixel electrode. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. A driving method of a pixel driving circuit , the driving method comprising a first scanning period and a second scanning period ,wherein the pixel driving circuit comprising:a first gate line,a second gate line,a data line,a first thin-film transistor, anda second thin-film transistor,a gate of the first thin-film transistor is coupled to the first gate line, a source of the first thin-film transistor is coupled to the data line, a drain of the first thin-film transistor is coupled to a source of the second thin-film transistor, a gate of the second thin-film transistor is coupled to the second gate line, anda drain of the second thin-film transistor is coupled to a pixel electrode,wherein, in the first scanning period, a first voltage is constantly applied to the gate of the first thin-film transistor through the first gate line, and a first voltage pulse having a pulse width is applied to the gate of the second thin-film transistor through the second gate line, and a second voltage is constantly applied to the gate of the second thin-film transistor through the second gate line during a time outside the pulse width; andin the second scanning period, the first voltage is constantly applied to the gate of the second thin-film transistor through the second gate line, and ...

SHIFT REGISTER, GATE DRIVER CIRCUIT AND DISPLAY APPARATUS

A shift register is disclosed including an input module, an output module, a first reset module, a first pull-down module and a second pull-down module. The first pull-down module is configured to supply a reference signal to a first node and an output terminal in response to an active level of a first control signal. The second pull-down module is configured to supply the reference signal to the first node and the output terminal in response to an active level of a second control signal. The active levels of the first control signal and the second control signal occur alternately. Also disclosed are a gate driver circuit and a display apparatus.

SHIFT REGISTER UNIT, GATE DRIVE CIRCUIT AND METHOD OF DRIVING THE SAME

A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises: a control circuit configured to output a control signal, at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line. As such, the scan signals output from the at least two buffer circuits would be synchronized so that the gate lines respectively coupled to the two buffer circuits can be scanned simultaneously. 1. A shift register unit cascaded in a gate drive circuit , wherein the shift register unit comprises:a control circuit configured to output a control signal,at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line,wherein the control circuit comprises a first pull-up control sub-circuit coupled to a first signal input terminal, a signal output terminal of the control circuit, and a first voltage terminal, the first pull-up control sub-circuit configured to output a signal of the first voltage terminal to the signal output terminal of the control circuit under control of a signal of the first signal input terminal;a first pull-down control sub-circuit coupled to a first clock signal terminal, a second clock signal terminal, the first signal input terminal, a second voltage terminal, a fourth voltage terminal, and a first pull-down node, the first pull-down control sub-circuit configured to control a voltage level of the first pull-down node under control of signals of the first clock signal terminal, the second clock signal terminal and the first signal input terminal;a second pull-down control sub-circuit coupled to the first clock signal terminal, the second clock signal terminal, the first signal input terminal, a third voltage terminal, the fourth voltage terminal, and a second pull-down node, the second pull-down control sub-circuit configured to control a voltage level of the ...

CONTROL CIRCUIT FOR CONTROLLING A NOISE REDUCTION THIN FILM TRANSISTOR IN A SHIFT REGISTER UNIT AND METHOD OF REDUCING NOISE

The present application discloses a control circuit for controlling a noise reduction thin film transistor in a shift register unit. The control circuit includes a timer for initiating a timing process when the shift register is turned on, to obtain an operating time of the shift register; a threshold voltage calculator coupled to the timer for calculating a present threshold voltage based on the operating time, a gate voltage of the noise reduction thin film transistor, and an initial threshold voltage of the noise reduction thin film transistor; and a gate voltage controller coupled to the threshold voltage calculator for adjusting the gate voltage of the noise reduction thin film transistor during the noise reduction phase, to control the noise reduction thin film transistor in an ON state during the noise reduction phase. 1. A control circuit for controlling a noise reduction thin film transistor in a shift register unit comprising a shift register having an input terminal , an output terminal for outputting a gate scanning signal during an output phase , and the noise reduction thin film transistor coupled to the output terminal for reducing noise of the shift register by maintaining the output terminal at a low voltage level during a noise reduction phase between two output phases; the control circuit comprising:a timer for initiating a timing process when the shift register is turned on, to obtain an operating time of the shift register;a threshold voltage calculator coupled to the timer for calculating a present threshold voltage based on the operating time, a gate voltage of the noise reduction thin film transistor, and an initial threshold voltage of the noise reduction thin film transistor; anda gate voltage controller coupled to the threshold voltage calculator for adjusting the gate voltage of the noise reduction thin film transistor during the noise reduction phase, to control the noise reduction thin film transistor in an ON state during the noise ...

ARRAY SUBSTRATE AND DRIVING METHOD, DRIVING CIRCUIT, AND DISPLAY APPARATUS

The present application discloses an array substrate comprising a plurality of gate lines and a plurality of data lines crossing over each other thereby defining an array of a plurality of sub-pixel areas, each sub-pixel area comprising a pixel electrode and multiple switching transistors having respective gate electrodes coupled to multiple different gate lines, wherein the pixel electrode is configured to be charged by a data signal from a data line only with all the multiple switching transistors being turned on concurrently during a pixel electrode charging period by an effective voltage level applied on the respective multiple different gate lines. 1. An array substrate comprising:a plurality of gate lines and a plurality of data lines crossing over each other thereby defining an array of a plurality of sub-pixel areas, each sub-pixel area comprising a pixel electrode and multiple switching transistors, a gate electrode of each of the multiple switching transistors coupled to one of multiple different gate lines;wherein the pixel electrode is configured to be charged by a data signal from a data line only with all the multiple switching transistors being turned on concurrently during a pixel electrode charging period by an effective voltage level applied respectively on the multiple different gate lines.2. The array substrate of claim 1 , wherein the multiple switching transistors in each sub-pixel area comprises a first switching transistor and a second switching transistor claim 1 , wherein the first switching transistor includes a gate electrode connected to a first gate line of the plurality of gate lines and the second switching transistor includes a gate electrode connected to a second gate line of the plurality of gate lines.3. The array substrate of claim 2 , wherein the first gate line and the second gate line are two adjacent gate lines among the plurality of gate lines.4. The array substrate of claim 3 , wherein the first switching transistor ...

DISPLAY APPARATUS AND DRIVING METHOD THEREOF

The present application discloses a method for driving a display panel, including receiving one or more frames of image data one after another each of which having image data for a plurality of subpixels in the display panel; determining an initial driving voltage corresponding to one subpixel of the plurality of subpixels based on each frame of image data; determining an overdrive voltage corresponding to the one subpixel based on the initial driving voltage and a compensation voltage corresponding to the one subpixel, wherein an amplitude of the overdrive voltage is greater than an amplitude of the initial driving voltage; and applying the overdrive voltage to the one subpixel for an overdrive time period followed by applying the initial driving voltage to a same one subpixel for displaying a subpixel image associated with each frame of image data. 1. A method for driving a display panel comprising:receiving one or more frames of image data one after another each of which having image data for a plurality of subpixels in the display panel;determining an initial driving voltage corresponding to one subpixel of the plurality of subpixels based on each frame of image data;determining an overdrive voltage corresponding to the one subpixel based on the initial driving voltage and a compensation voltage corresponding to the one subpixel, wherein an amplitude of the overdrive voltage is greater than an amplitude of the initial driving voltage; andapplying the overdrive voltage to the one subpixel for an overdrive time period followed by applying the initial driving voltage to a same one subpixel for displaying a subpixel image associated with each frame of image data.2. The method of claim 1 , wherein the overdrive voltage equals to a sum of the initial driving voltage and the compensation voltage.3. The method of claim 1 , wherein determining the overdrive voltage comprises determining the compensation voltage corresponding to the one subpixel; andthe compensation ...

THIN FILM TRANSISTOR AND CIRCUIT STRUCTURE

The present disclosure provides a TFT and a circuit structure to improve the characteristics of the threshold voltage drift of the TFT. The TFT includes a gate electrode, a semiconductor layer, an etch stop layer, and a source electrode and a drain electrode connected to the semiconductor layer. The TFT further includes a stopping structure arranged over the etch stop layer. The stopping structure is electrically isolated from the source electrode and the drain electrode, and an orthogonal projection of the stopping structure onto the etch stop layer at least partially overlaps an orthogonal projection of the semiconductor layer onto the etch stop layer. The present disclosure improves the characteristics of the threshold voltage drift of the TFT. 1. A thin film transistor (TFT) , comprising a gate electrode , a semiconductor layer , an etch stop layer , and a source electrode and a drain electrode connected to the semiconductor layer; wherein the TFT further comprises:a stopping structure arranged over the etch stop layer;wherein the stopping structure is electrically isolated from the source electrode and the drain electrode, and an orthogonal projection of the stopping structure onto the etch stop layer at least partially overlaps an orthogonal projection of the semiconductor layer onto the etch stop layer.2. The TFT according to claim 1 , wherein the orthogonal projection of the stopping structure onto the etch stop layer is located within a region where the orthogonal projection of the semiconductor layer onto the etch stop layer is located.3. The TFT according to claim 1 , wherein the stopping structure claim 1 , the source electrode and the drain electrode are formed by a single etching process.4. The TFT according to claim 1 , wherein a length of a perpendicular line between parallel facing sides of the source electrode and the drain electrode is D; a width of the stopping structure in a direction parallel to the perpendicular line is W claim 1 , and W/D is ...

SHIFT REGISTER UNIT AND DRIVING METHOD, GATE DRIVE CIRCUIT, AND DISPLAY APPARATUS

The present application discloses an N-th shift register unit circuit including at least a gate-drive signal output sub-circuit, a pull-up control sub-circuit, and a pull-down control sub-circuit respectively connected between a pull-up node and a pull-down node and provided with a p-th clock signal in addition to an n-th clock signal. A driving method includes controlling the pull-down node at turn-off voltage level when the p-th clock signal is at turn-on voltage level during which the n-th clock signal is correspondingly rising to turn-on voltage level from turn-off voltage level. 1. A method of driving a shift register unit , wherein the shift register unit is an N-th unit cascaded in the multi-stage gate driving circuit , wherein N is a positive integer , the N-th unit comprising:an N-th gate-drive signal output port;a gate-drive output sub-circuit including a capacitor connected between a pull-up node and the N-th gate-drive signal output port, and configured to output an n-th clock signal at the N-th gate drive signal output port, wherein n to be a remainder of N divided by 4 or n=4 if N is divisible by 4;a pull-up control sub-circuit connected to an (N−1)th gate-drive signal output port of a previous adjacent (N−1)th unit, a pull-down node, the pull-up node, and a fixed voltage port set to turn-off voltage level, and controlled by a m-th clock signal, wherein m is a remainder of (n+2) divided by 4 or equal to 4 if (n+2) is divisible by 4; anda pull-down control sub-circuit connected to the pull-up node, the fixed voltage port set to tum-off voltage level, the (N−1)th gate-drive signal output port, and the pull-down node, and controlled by the n-th clock signal and a p-th clock signal, wherein p is a remainder of (n+3) divided by 4 or equal to 4 if (n+3) is divisible by 4;the method comprising:controlling the p-th dock signal at turn-on voltage level during a time period corresponding to a rising, edge of the n-th clock signal during which the n-th clock ...

SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT, DRIVING METHOD AND DISPLAY APPARATUS

The embodiments of the present application provide a shift register unit and a method for driving the same, a gate driving circuit, and a display apparatus. Here, the shift register unit includes a first controlling sub-circuit, a first voltage dividing sub-circuit, a charging and discharging sub-circuit, and an outputting sub-circuit. Here, an output signal of the outputting sub-circuit is controlled by the charging and discharging sub-circuit. A first input signal and a second input signal input at a first input signal terminal Forward and a second input signal terminal Backward electrically coupled to the charging and discharging sub-circuit are pulse signals. 1. A shift register unit , comprising:a first controlling sub-circuit configured to receive a first voltage signal and write the first voltage signal to a first node under a control of the first voltage signal, and receive a second voltage signal and write a second voltage signal to a second node under a control of the second voltage signal;a first voltage dividing sub-circuit electrically coupled to the first controlling sub-circuit and an outputting signal terminal, and configured to receive a third voltage signal and an outputting signal from the outputting signal terminal, write the third voltage signal to the first node under a control of the outputting signal; and write the third voltage signal to the second node under the control of the outputting signal;a charging and discharging sub-circuit electrically coupled to the first controlling sub-circuit, the first voltage dividing sub-circuit, a first inputting signal terminal and a second inputting signal terminal, and configured to receive a first clock signal, and write a first inputting signal from the first inputting signal terminal to a third node or receive a second inputting signal from the second inputting signal terminal to the third node, under a control of the first clock signal, a voltage at the first node, and a voltage at the second node; ...

Laundry treatment apparatus

Disclosed is a laundry treatment apparatus equipped with a condenser for condensing air exhausted during a drying procedure. The laundry treatment apparatus includes an outer tub (5) disposed in a cabinet (1), to receive air containing moisture generated from laundry, a circulation duct (40) for guiding a portion of air present in the outer tub (5) to be re-supplied to the outer tub (5) after being discharged from the outer tub (5), an exhaust duct (50) for guiding some other portion of the air present in the outer tub (5) to be exhausted, an air suction duct (45) for guiding outdoor air to be introduced into the outer tub (5), a fan (41), a heater (43), heat-exchanging tubes (61) disposed at the exhaust duct (50) such that the exhaust air passes through the tubes (61), and a condensed water pipe (70) for guiding condensed water generated in the tubes (61). The tubes (61) are spaced apart from each other by a predetermined distance, to form gaps (62).

Shift register unit, gate drive circuit and method of driving the same

Cooker

Shift register unit, gate driving circuit, driving method and display apparatus

The embodiments of the present application provide a shift register unit and a method for driving the same, a gate driving circuit, and a display apparatus. Here, the shift register unit includes a first controlling sub-circuit, a first voltage dividing sub-circuit, a charging and discharging sub-circuit, and an outputting sub-circuit. Here, an output signal of the outputting sub-circuit is controlled by the charging and discharging sub-circuit. A first input signal and a second input signal input at a first input signal terminal Forward and a second input signal terminal Backward electrically coupled to the charging and discharging sub-circuit are pulse signals.

Shift register circuit, and driving method thereof, gate drive circuit and display device

A shift register circuit, a driving method thereof, a gate drive circuit and a display device are provided. The shift register circuit includes an input sub-circuit, an output sub-circuit, a discharge sub-circuit and a noise reduction sub-circuit. The input sub-circuit is connected to an input signal terminal, a first power source terminal and a pull-down node, and configured to, under the control of an input signal, output a first power source terminal signal to the pull-down node. In the shift register circuit, the discharge sub-circuit may control the potential of the pull-down node to be an ineffective potential at the input stage, thereby preventing the noise reduction sub-circuit from affecting the potentials of the pull-up node and the output terminal under the control of the pull-down node, and ensuring normal output of the shift register circuit.

Gate driver on array circuit and driving method thereof, and display device

The present invention discloses a gate driver on array circuit and a driving method thereof, and a display device. The gate driver on array circuit comprises a first gate driver on array sub-circuit and a second gate driver on array sub-circuit; the first gate driver on array sub-circuit is configured to drive in a first working state which is a state in which no defect occurs in the first gate driver on array sub-circuit; the second gate driver on array sub-circuit is configured to drive in a second working state which is a state in which a defect occurs in the first gate driver on array sub-circuit. The present invention improves the yield rate of the gate driver on array circuit.

Laundry treatment apparatus

Pixel circuit, driving method thereof, display panel, and display apparatus

The present disclosure relates to a pixel circuit. The pixel circuit may include a switch sub-circuit ( 10 ), a storage sub-circuit ( 20 ), and a driving sub-circuit ( 30 ). The storage sub-circuit ( 20 ) may include a first storage transistor (Tf 1 ) and a second storage transistor (Tf 2 ). Both the first storage transistor (Tf 1 ) and the second storage transistor (Tf 2 ) may be floating gate transistors. The storage sub-circuit ( 20 ) and the driving sub-circuit ( 30 ) may be configured to transmit a data signal from one of a plurality of data lines to a pixel electrode under control of the switch sub-circuit ( 10 ).

Control circuit for controlling a noise reduction thin film transistor in a shift register unit and method of reducing noise

A control circuit (30) for controlling a noise reduction thin film transistor in a shift register unit (40). The control circuit (30) includes a timer (31) for initiating a timing process when the shift register (40) is turned on, to obtain an operating time of the shift register (40); a threshold voltage calculator (32) coupled to the timer (31) for calculating a present threshold voltage based on the operating time, a gate voltage of the noise reduction thin film transistor, and an initial threshold voltage of the noise reduction thin film transistor; and a gate voltage controller (33) coupled to the threshold voltage calculator (32) for adjusting the gate voltage of the noise reduction thin film transistor during the noise reduction phase, to control the noise reduction thin film transistor in an ON state during the noise reduction phase.

Laundry drying machine and controlling method of laundry drying machine

Disclosed herein is a method of controlling a laundry dryer for generating high-temperature steam through a steam part and controlling each of rotation of a drum and rotation of a circulation fan. The method includes a steam drying procedure drying operation of increasing an internal temperature of the drum to dry an object to be dried, a steam drying procedure steam supply operation of supplying steam into the drum after the steam drying procedure drying operation, and a re-drying operation of supplying hot air into the drum after the steam drying procedure steam supply operation. When steam is sprayed from the steam part, the rotation of the drum is maintained, the rotation of the circulation fan is stopped, such that the steam is evenly supplied to the object to be dried, damage to the object is prevented, and sterilization of the object is enhanced.

Pixel circuit and drive method for same, and display panel and drive method for same

Disclosed are a pixel circuit and a drive method for the same, and a display panel and a drive method for the same. The pixel circuit is configured to drive a light-emitting element to emit light, including: a current control sub-circuit and a time-length control sub-circuit. The current control sub-circuit is electrically connected to a current data terminal, a scanning signal terminal, a reset signal terminal, an initial signal terminal, a light-emitting signal terminal, a first power terminal, a first node, and a second node, respectively. The time-length control sub-circuit is electrically connected to a first control terminal, a second control terminal, a time-length data terminal, a ground terminal, a light-emitting signal terminal, a high-frequency input terminal, and the first node, respectively.

Pixelschaltung, Treiberverfahren dafür, Anzeigesubstrat und Anzeigevorrichtung

Eine Pixelschaltung umfasst eine erste Treiberschaltung, eine erste Steuerschaltung, eine zweite Treiberschaltung und eine zweite Steuerschaltung. Die erste Treiberschaltung ist dazu konfiguriert, in Reaktion auf ein an dem Abtastsignalanschluss empfangenes Abtastsignal ein an dem ersten Datensignalanschluss empfangenes erstes Datensignal in den ersten Knoten zu schreiben; die erste Steuerschaltung ist dazu konfiguriert, als Reaktion auf ein an dem Freigabesignalanschluss empfangenes Freigabesignal ein erstes Treibersignal gemäß der Spannung des ersten Knotens und dem von dem ersten Spannungssignalanschluss übertragenen ersten Spannungssignal zu erzeugen; die zweite Treiberschaltung ist dazu konfiguriert, als Reaktion auf das Abtastsignal ein an dem zweiten Datensignalanschluss empfangenes zweites Datensignal in den zweiten Knoten zu schreiben; die zweite Steuerschaltung ist dazu konfiguriert, als Reaktion auf ein an dem Steuersignalanschluss empfangenes Steuersignal ein zweites Treibersignal gemäß der Spannung des zweiten Knotens und dem ersten Spannungssignal zu erzeugen.

Gate driving circuit and method for controlling the same, and display apparatus

The embodiments of the present disclosure provide a gate driving circuit and a method for controlling the same, and a display apparatus. The gate driving circuit includes: M decoding sub-circuits, wherein each of the M decoding sub-circuits has K signal input terminals and 2 K signal output terminals, where K=N/M, M, N and K are positive integers, 4≤M<N, and K≥2, N signal input terminals of the M decoding sub-circuits are connected to receive N-bit address data, and each of the M decoding sub-circuits is configured to receive respective K-bit data in the N-bit address data at K signal input terminals thereof, and select one of the 2 K signal output terminals thereof which matches the received K-bit data; and a plurality of driving sub-circuits, wherein each of the plurality of driving sub-circuits is connected to M signal output terminals belonging to the M decoding sub-circuits respectively according to an address allocated thereto, and is configured to output a row driving signal when the M signal output terminals connected to the driving sub-circuit are all selected.

Shift register and driving method therefor, gate driver, and display apparatus

A shift register, a driving method thereof, a gate driver and a display device are provided. The shift register includes: an input circuit for transmitting an input signal to a first node and a first power supply signal to a second node under control of a first clock signal, and for transmitting the first clock signal to the second node under control of a level of the first node; a control circuit for transmitting a second power supply signal to the first node under control of a level of the second node and a second clock signal, for transmitting the second clock signal to the third node under control of a level of the fourth node and/or a level of the first node, and for transmitting the second power supply signal to the third node under control of the level of the second node; a pull-down control circuit; and an output circuit for transmitting the fourth power supply signal to the signal output terminal under control of a level of the third node and for transmitting the third power supply signal to the signal output terminal under control of a level of the fifth node. The pull-down control circuit controls a level of the fifth node regardless of the first clock signal.

Shift register and driving method therefor, gate driver, and display apparatus

Pixel circuit and method for driving same, display panel, and display device

Provided is a pixel circuit. The pixel circuit includes a reset circuit, a data write circuit, a light-emission control circuit, and a drive circuit; wherein the reset circuit is configured to transmit a reset power signal supplied by the reset power terminal to the first node in response to a reset control signal; the data write circuit is configured to transmit a data signal supplied by the data signal terminal to the first node in response to a gate drive signal; the light-emission control circuit is configured to control conduction/non-conduction between the cathode of the light-emitting element and the second node, and control conduction/non-conduction between the third node and the pull-down power terminal, in response to a light-emission control signal; and the drive circuit is configured to control conduction/non-conduction between the second node and the third node in response to a potential of the first node.

Pixel drive circuit, method for driving the same, and display device

Embodiments of the present disclosure provide a pixel drive circuit, a method for driving the pixel drive circuit, and a display device. The pixel drive circuit includes: a drive sub-circuit, a write sub-circuit and a control circuit. The control circuit further is coupled to a light-emitting control signal terminal, a second scanning signal terminal and a second data signal terminal, and is configured to determine a duration of providing a driving signal to a to-be-driven element under control of a light-emitting control signal provided by the light-emitting control signal terminal and a second scanning signal provided by the second scanning signal terminal.

Shift register circuit, array substrate and display device

Display panel and electronic device

A display panel is provided. The display panel includes a base substrate and a plurality of display units disposed on the base substrate. The display unit includes a signal line, a light-emitting device and a drive unit. The light-emitting device is disposed in a flexible display region of the base substrate, the drive unit is disposed in a pixel circuit region of the base substrate, and the signal line is connected with the light-emitting device and the drive unit.

Display panel with reduced cross talk of signal wires, control method for same, and display device

Disclosed are a display panel, a control method for the same, and a display device. The display panel includes: M rows and N columns of pixel units, N current data lines sequentially arranged along a row direction, and N time-length data lines sequentially arranged along the row direction. Each pixel unit includes a pixel circuit, the pixel circuit including a current data terminal and a time-length data terminal. An ith column of the current data lines and an ith column of the time-length data lines are respectively located on two sides of an ith column of pixel units, the current data terminals of the pixel circuits of the ith column of pixel units are electrically connected to the ith column of the current data lines.

Pixel circuit and driving method thereof, and display panel and driving method thereof

A drive method for a display panel, wherein the display panel includes a plurality of current data lines, a plurality of time-length data lines, a first current selection signal line, a second current selection signal line, a first time-length selection signal line and a second time-length selection signal line, at least one current data line is connected with the first current selection signal line or the second current selection signal line, and at least one time-length data line is connected with the first time-length selection signal line or the second time-length selection signal line; the method includes: providing a valid level signal to the first time-length selection signal line, the second time-length selection signal line, the first current selection signal line and the second current selection signal line.

Shift register and driving method thereof, light emission control driver and display apparatus

A shift register includes: an input circuit configured to receive an input signal; a first control circuit configured to control, in response to a second clock signal and a voltage at a second node, a voltage at the first node; a second control circuit configured to control, in response to a first clock signal, the second clock signal, and the voltage at the first node, a voltage at the second node, and control, in response to the second clock signal and the voltage at the first node, a voltage at the fifth node; and an output circuit configured to transmit, in response to an active level at the first node, a second power signal to an output signal terminal, and transmit, in response to an active level at the fifth node, the first power signal to the output signal terminal. All transistors included in the shift register are N-type transistors.

Display substrate and driving method therefor, and display device

A display substrate (100), comprising: a plurality of data lines (DL) extending in a first direction; and a plurality of subpixels (2). Each subpixel (2) comprises a pixel driving circuit (21) and a light-emitting device (22). The pixel driving circuit (21) comprises: a current control circuit (211) and a duration control circuit (212) electrically connected to the current control circuit (211) and the light-emitting device (22). The current control circuit (211) is configured to generate a driving signal, so as to drive the light-emitting device (22) to emit light; and the duration control circuit (212) is configured to generate a duration control signal, so as to control the duration of conduction between the current control circuit (211) and the light-emitting device (22). The current control circuit (211) and the duration control circuit (212) are electrically connected to a same data line.

Shift register circuit, array substrate and display device

The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.

Cooking appliance

A cooking appliance includes a main body forming a machine room; a cooking chamber arranged below the machine room; an intermediate flow path including a first suction port and formed between the machine room and the cooking chamber; and a fan configured to suction air into the intermediate flow path, wherein the machine room includes a second suction port through which air is suctioned, and an opening portion connected to the intermediate flow path, the opening portion includes a first opening portion and a second opening portion arranged at a farther distance from the fan than the first opening portion, and the second opening portion has an area larger than an area of the first opening portion.

Display substrate and driving method therefor, and display device

Laundry treatment apparatus

A laundry treatment apparatus equipped with a thermoelectric module includes a thermoelectric element configured to emit heat from a first surface and to absorb heat through a second surface, a first heat exchange unit configured to contact the first surface of the thermoelectric element so as to undergo heat exchange with air upon receiving heat from the first surface, a heat transfer member having an interconnecting surface that is configured to contact the second surface of the thermoelectric element so as to be in a heat conducting relationship with the second surface, and a second heat exchange unit configured to contact the interconnecting surface of the heat transfer member, the second heat exchange unit being configured to undergo heat exchange with air upon receiving heat from the second surface of the thermoelectric element through the heat transfer member.

Display substrate and driving method thereof, and display apparatus

A display substrate includes a plurality of data lines extending in a first direction, and a plurality of sub-pixels. A sub-pixel includes a pixel driving circuit and a light-emitting device. The pixel driving circuit includes a current control circuit, and a duration control circuit electrically connected to the current control circuit and the light-emitting device. The current control circuit is configured to generate a driving signal to drive the light-emitting device to emit light; and the duration control circuit is configured to generate a duration control signal to control a duration of a connection between the current control circuit and the light-emitting device. The current control circuit and the duration control circuit are electrically connected to a same data line.

Array substrate, driving method thereof, and display apparatus

Disclosed is an array substrate including multiple first selection circuits with each including at least two first selection transistors and at least two first anticreeping transistors. Each first selection transistor is connected with one first anticreeping transistor in series. When the first selection transistor is turned on by a first turn-on signal from a first control signal terminal, the first anticreeping transistor is turned on by a second turn-on signal from a second control signal terminal. When the first selection transistor is turned off by a first turn-off signal from the first control signal terminal, the first anticreeping transistor is turned off to make the first selection transistors and the data signal terminal disconnected, by a second turn-off signal from the second control signal terminal. A voltage of the first turn-off signal is greater than a voltage of the second turn-off signal.

Pixel circuit and method for driving same, display panel, and display device

Provided is a pixel circuit. The pixel circuit includes a reset circuit, a data write circuit, a light-emission control circuit, and a drive circuit; wherein the reset circuit is configured to transmit a reset power signal supplied by the reset power terminal to the first node in response to a reset control signal; the data write circuit is configured to transmit a data signal supplied by the data signal terminal to the first node in response to a gate drive signal; the light-emission control circuit is configured to control conduction/non-conduction between the cathode of the light-emitting element and the second node, and control conduction/non-conduction between the third node and the pull-down power terminal, in response to a light-emission control signal; and the drive circuit is configured to control conduction/non-conduction between the second node and the third node in response to a potential of the first node.

Display apparatus and driving method thereof

A method for driving a display panel, including receiving one or more frames of image data one after another each of which having image data for a plurality of subpixels in the display panel; determining an initial driving voltage corresponding to one subpixel of the plurality of subpixels based on each frame of image data; determining an overdrive voltage corresponding to the one subpixel based on the initial driving voltage and a compensation voltage corresponding to the one subpixel, wherein the amplitude of the overdrive voltage is greater than the amplitude of the initial driving voltage; and applying the overdrive voltage to the one subpixel for an overdrive time period followed by applying the initial driving voltage to the same one subpixel for displaying a subpixel image associated with each frame of image data.

Pixel circuit, driving method therefor and display apparatus

Embodiments of the present disclosure provide a pixel circuit, a driving method therefor and a display apparatus. The pixel circuit includes: an input circuit, configured to input data signals loaded to a first data signal terminal into corresponding input nodes in response to signals loaded to 2 N −1 first scanning signal terminals; a control circuit, configured to control signals of 2 N control nodes respectively in response to signals of at least two input nodes in the 2 N −1 input nodes; an output circuit, configured to provide a signal of an men selection control signal terminal in 2 N selection control signal terminals to an output node in response to a signal of an m th control node in the 2 N control nodes; and a light-emitting drive circuit, configured to drive a to-be-driven device to work in response to a signal of the output node.

Pixel circuit having control circuit for controlling a light emitting element and driving method thereof, display panel and display apparatus

A pixel circuit includes a driving circuit, a first control circuit and a second control circuit. The driving circuit is configured to receive a data signal in response to a scan signal, and generate, in response to a first enable signal, a driving signal according to a first voltage and the data signal. The first control circuit is configured to: receive a first input signal in response to a first control signal, and transmit a third input signal in response to the first input signal; and receive a second input signal in response to a second control signal, and transmit a second enable signal in response to the second input signal. The second control circuit is configured to transmit the driving signal to an element to be driven in response to one of the third input signal and the second enable signal.

Shift register and driving method thereof, light emission control driver and display apparatus

A shift register includes: an input circuit configured to receive an input signal; a first control circuit configured to control, in response to a second clock signal and a voltage at a second node, a voltage at the first node; a second control circuit configured to control, in response to a first clock signal, the second clock signal, and the voltage at the first node, a voltage at the second node, and control, in response to the second clock signal and the voltage at the first node, a voltage at the fifth node; and an output circuit configured to transmit, in response to an active level at the first node, a second power signal to an output signal terminal, and transmit, in response to an active level at the fifth node, the first power signal to the output signal terminal. All transistors included in the shift register are N-type transistors.

Gate driver circuit, its driving method, array substrate and display device

The present disclosure provides a gate driver circuit including at least one set of clock signal lines and multiple levels of shift registers arranged in a cascaded manner. Each set of the clock signal lines includes two clock signal lines. The multiple levels of shift registers is divided into at least one set, and each set of the clock signal lines corresponds to a set of the shift registers. One clock signal line in each set of the clock signal lines is connected to a resetting signal input end of a last-level shift register in the set of the shift registers corresponding to the set of the clock signal lines. The present disclosure further provides an array substrate, a display device and a method for driving the gate driver circuit.

Gate driver on array circuit for different resolutions, driving method thereof, and display device including the same

The present invention discloses a Gate-driver-On-Array (GOA) circuit and the driving method thereof and a display device. The GOA circuit comprises a driving module, a low-resolution module and at least two high-resolution modules, the driving module being connected with the low-resolution module and the at least two high-resolution modules respectively; wherein, the driving module is used to output control signal to the low-resolution module and the high-resolution modules; the low-resolution module is used to output a low-resolution signal to at least two rows of pixels under the control of the control signal during low-resolution display; and each high-resolution module is used to output a high-resolution signal to corresponding one row of pixels under the control of the control signal during high-resolution display. The GOA circuit of the present invention may be used to drive multiple rows of pixels and implement the switching between low resolution display and high resolution display.

Thin film transistor and circuit structure

The present disclosure provides a TFT and a circuit structure to improve the characteristics of the threshold voltage drift of the TFT. The TFT includes a gate electrode, a semiconductor layer, an etch stop layer, and a source electrode and a drain electrode connected to the semiconductor layer. The TFT further includes a stopping structure arranged over the etch stop layer. The stopping structure is electrically isolated from the source electrode and the drain electrode, and an orthogonal projection of the stopping structure onto the etch stop layer at least partially overlaps an orthogonal projection of the semiconductor layer onto the etch stop layer. The present disclosure improves the characteristics of the threshold voltage drift of the TFT.

Gate driving circuit and a driving method thereof, as well as a display device

The present disclosure provides a gate driving circuit and a driving method thereof, a display device, which relates to the field of display technology. The gate driving circuit may comprise a plurality of mutually cascaded shift register units and a pre-charging unit, the gate row drive scanning and touch control scanning of the plurality of mutually cascaded shift register units are performed alternately. By additionally arranging a pre-charging unit connected with the corresponding first stage of shift register unit when the gate row drive scanning is performed again after the touch control scanning is accomplished, the first stage of shift register unit can be pre-charged during the touch control scanning.

Shift register unit, gate driving circuit and display device

The present invention provides a shift register unit, a gate driving circuit and a display device, which belongs to the field of display technology. The shift register unit of the present invention comprises: an input module, a pull-up module, a pull-down control module, a pull-down module, a reset module and a discharge module.