Reconfigurable RF Front End And Antenna Arrays For Radar Mode Switching

Concepts and examples pertaining to reconfigurable radio frequency (RF) front end and antenna arrays for radar mode switching are described. A processor associated with a radar system selects a mode of a plurality of modes in which to operate the radar system. The processor then controls the radar system to operate in the selected mode by utilizing a plurality of antennas in a respective configuration of a plurality of configurations of the antennas which corresponds to the selected mode. Each configuration of the plurality of configurations of the antennas results in respective antenna characteristics. Each configuration of the plurality of configurations of the antennas utilizes a respective number of antennas of the plurality of antennas. 1. A method , comprising:selecting, by a processor associated with a radar system, a mode of a plurality of modes in which to operate the radar system; andcontrolling, by the processor, the radar system to operate in the selected mode by utilizing a plurality of antennas in a respective configuration of a plurality of configurations of the antennas which corresponds to the selected mode,wherein each configuration of the plurality of configurations of the antennas results in respective antenna characteristics, andwherein each configuration of the plurality of configurations of the antennas utilizes a respective number of antennas of the plurality of antennas.2. The method of claim 1 , wherein the selecting of the mode of the plurality of modes comprises selecting a mode from a plurality of modes comprising:an ultra-short-range radar (USRR) mode;a short-range radar (SRR) mode;a medium-range radar (MRR) mode; anda long-range radar (LRR) mode.3. The method of claim 1 , wherein the respective antenna characteristics of each configuration of the plurality of configurations of the antennas comprise respective values in terms of at least an antenna gain and a field of view.4. The method of claim 1 , wherein the controlling of the radar ...

Chip Level Critical Point Analysis with Manufacturer Specific Data

A method and computer program are provided for analyzing a set of layers within an integrated circuit design to determine a set of critical points for each layer within the set of layers. The critical points are based at least in part on manufacturer specific process parameters. The method includes assigning a critical point value to each of the critical points within each set of critical points, analyzing a path through the integrated circuit design across multiple integrated circuit design layers, and determining a sum of critical point values of each critical point along the path. 1. A method performed by a computer processing system , the method comprising:analyzing a set of layers within an integrated circuit design to determine a set of critical points for each layer within the set of layers, the critical points being based at least in part on manufacturer specific process parameters;assigning a critical point value to each of the critical points within each set of critical points;analyzing a path through the integrated circuit design across multiple integrated circuit design layers; anddetermining a sum of critical point values of each critical point along the path.2. The method of claim 1 , further comprising claim 1 , reporting a potential issue to a user if the sum of critical point values is greater than a threshold value.3. The method of claim 2 , wherein the threshold values are determined based on criteria for determining the critical point values.4. The method of claim 1 , wherein the path runs through a specified point within the integrated circuit design.5. The method of claim 4 , further comprising claim 4 , analyzing additional paths of the integrated circuit design that pass through the specified point and determining a sum of critical point values assigned to critical points along the additional paths.6. The method of claim 1 , wherein the critical points include at least one of:a hotspot that may cause an immediate performance issue; anda weak ...

APPARATUS AND METHOD FOR APPLYING FREQUENCY CALIBRATION TO LOCAL OSCILLATOR SIGNAL DERIVED FROM REFERENCE CLOCK OUTPUT OF ACTIVE OSCILLATOR THAT HAS NO ELECTROMECHANICAL RESONATOR

A wireless system includes a local oscillator (LO) signal generation circuit, a receiver (RX) circuit, and a calibration circuit. The LO signal generation circuit generates an LO signal according to a reference clock. The LO signal generation circuit includes an active oscillator. The active oscillator generates the reference clock, wherein the active oscillator includes at least one active component, and does not include an electromechanical resonator. The RX circuit generates a down-converted RX signal by performing down-conversion upon an RX input signal according to the LO signal. The calibration circuit generates a frequency calibration control output according to a signal characteristic of the down-converted RX signal, and outputs the frequency calibration control output to the LO signal generation circuit. The LO signal generation circuit adjusts an LO frequency of the LO signal in response to the frequency calibration control output.

LAYOUT DESIGN FOR ELECTRON-BEAM HIGH VOLUME MANUFACTURING

The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step. In some embodiments a routing grid is refined to rule out interactions between a subset of design constructs and the layout grid. Remaining design shape placement is then optimized along the routing grid relative to the stitching lines. 1. A method to create an electron-beam lithography layout , comprising:using a computer, which is configured to provide an integrated circuit layout made of multiple integrated circuit layers, to produce an electronic version of an initial integrated circuit layer made up of one or more design shapes;resolving the initial integrated circuit layer into a plurality of e-beam subfields, wherein respective e-beam subfields correspond to respective passes of an electron beam and wherein neighboring e-beam subfields meet at a stitching line which overlaps a length or area on a design shape in the initial integrated circuit layer; andmodifying the electronic version of the initial integrated circuit layer to produce a modified integrated circuit layer in which the design shape is moved or altered to reduce the ...

Chip level critical point analysis with manufacturer specific data

A method and computer program are provided for analyzing a set of layers within an integrated circuit design to determine a set of critical points for each layer within the set of layers. The critical points are based at least in part on manufacturer specific process parameters. The method includes assigning a critical point value to each of the critical points within each set of critical points, analyzing a path through the integrated circuit design across multiple integrated circuit design layers, and determining a sum of critical point values of each critical point along the path.

Layout Design for Electron-Beam High Volume Manufacturing

The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step. In some embodiments a routing grid is refined to rule out interactions between a subset of design constructs and the layout grid. Remaining design shape placement is then optimized along the routing grid relative to the stitching lines. 1. A method to create a layout for electron-beam lithography , comprising:assembling a layout comprising graphical data by arranging a plurality of standard cells within a design tool, a standard cell comprising one or more design shapes;defining a layout grid for the layout within the design tool, wherein the layout grid comprises first vertical grid lines spaced at integer multiples of a design shape minimum pitch; andminimizing an intersection of the design shapes with the first vertical grid lines.2. The method of claim 1 , minimizing intersection of design shapes with first vertical grid lines further comprising avoiding first vertical grid lines with design shapes within the standard cell by shifting the standard cell horizontally claim 1 , wherein design shapes comprise a width value below a first ...

COMMUNICATION CIRCUIT AND ASSOCIATED CALIBRATION METHOD

A communication circuit includes a receiver path, a frequency translating loop filter and a signal source circuit. The frequency translating loop filter includes an auxiliary mixer, and a frequency translating filter backend circuit such as a filter. The signal source circuit can be shared with a transmitter path. When the receiver path receives an external signal, the auxiliary mixer and the frequency translating filter backend circuit perform high-frequency filtering. When the receiver path need not receive the external signal, the auxiliary mixer up-converts a low-frequency auxiliary signal provided by the signal source circuit to a high-frequency domain, and the up-converted signal is received by the receiver path. Thus, an operation parameter of the receiver path can be adjusted and calibrated according to a response of the receiver path. 1. A communication circuit , comprising: an input port; and', 'a reception mixer, coupled to the input port, configured to mix a signal of the input port with a reception oscillation frequency; and, 'a receiver path, comprisinga signal source circuit; andan auxiliary mixer, coupled between the input port and the signal source circuit, operable in an auxiliary mode;wherein, when the auxiliary mixer operates in the auxiliary mode, the signal source circuit provides an auxiliary signal, and the auxiliary mixer mixes the auxiliary signal with the reception oscillation frequency and sends a mixed result to the input port.2. The communication circuit according to claim 1 , wherein the auxiliary mixer is further operable in a reception mode; when the auxiliary mixer operates in the reception mode claim 1 , the auxiliary mixer is configured to co-operate with a frequency translating filter backend circuit to filter the signal of the input port.3. The communication circuit according to claim 2 , wherein when the auxiliary mixer operates in the reception mode claim 2 , the auxiliary mixer mixes a first passband with the reception ...

Distinguishable IC patterns with encoded information

A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used.

APPARATUS AND METHOD FOR APPLYING FREQUENCY CALIBRATION TO LOCAL OSCILLATOR SIGNAL DERIVED FROM REFERENCE CLOCK OUTPUT OF ACTIVE OSCILLATOR

A system includes a local oscillator (LO) signal generation circuit, a receiver (RX) circuit, and a calibration circuit. The LO signal generation circuit generates an LO signal according to a reference clock, and includes an active oscillator that generates the reference clock. The active oscillator includes at least one active component. The RX circuit generates a processed RX signal by processing an RX input signal according to the LO signal. The calibration circuit checks a signal characteristic of the processed RX signal by detecting if a calibration tone exists within a receiver bandwidth, set a frequency calibration control output in response to the calibration tone being not found in the receiver bandwidth, and output the frequency calibration control output to the LO signal generation circuit. The LO signal generation circuit adjusts an LO frequency of the LO signal in response to the frequency calibration control output.

Distinguishable IC Patterns with Encoded Information

A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used. 1. A method of making an integrated circuit (“IC”) design layout in a way to distinguish a plurality of similar patterns contained therein , each of the patterns comprising a plurality of dummy features , the method comprising:identifying an anchor group of anchor dummy features as a subset of the plurality of dummy features in each of the patterns, the anchor group being present in each of the patterns and having identical configuration, size, and location thereof;identifying at least one tunable dummy feature as a subset of the plurality of dummy features in each of the patterns, the at least one tunable dummy feature having a fixed spatial relationship with the anchor group of the respective pattern;determining tuning parameters to be varied for having the at least one tunable dummy feature deviated;determining, for each tuning parameter, deviation values by which the tuning parameter can be varied; andusing a computer, varying the at least one tunable dummy feature in each of the patterns by at least one of the deviation values in such a way that different patterns become distinguishable from one another through the tunable dummy features so varied.2. ...

Electron Beam Data Storage System and Method for High Volume Manufacturing

The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table. 1. A method comprising:receiving a design layout having a data representation of a first data size, wherein the design layout includes a plurality of pattern portions; including the plurality of pattern portions in the data representation of the second size, wherein any pattern portion that is repeated in the design layout is included once in the data representation of the second data size, and', 'creating a lookup table that maps each of the included plurality of pattern portions to at least one location within the design layout; and, 'reducing the data representation from the first data size to a second data size, the second data size being less than the first data size, wherein the reducing includesusing the data representation of the second data size and the lookup table to write the design layout on an energy sensitive layer.2. The method of further including transferring the data representation of the second data size from an electron beam data processing module to an electron beam exposure module claim 1 , wherein the electron beam exposure module writes the design layout on the energy sensitive layer using the data representation of the second data size and the lookup table.3. The method of further including performing a proximity correction process on the data representation of the first data size.4. The method of further including dithering the data representation of the second data size.5. The method of further including storing the data ...

Striping methodology for maskless lithography

The present disclosure involves a method of performing a maskless lithography process. The method includes receiving a computer layout file for an integrated circuit (IC) device. The layout file contains a plurality of IC sections. The method includes separating the computer layout file into a plurality of sub-files. The method includes striping the plurality of sub-files concurrently using a plurality of computer processors, thereby generating a plurality of striped sub-files. The method includes transferring the plurality of striped sub-files to a maskless lithography system.

Apparatus and method for applying frequency calibration to local oscillator signal derived from reference clock output of active oscillator

A system includes a local oscillator (LO) signal generation circuit, a receiver (RX) circuit, and a calibration circuit. The LO signal generation circuit generates an LO signal according to a reference clock, and includes an active oscillator that generates the reference clock. The active oscillator includes at least one active component. The RX circuit generates a processed RX signal by processing an RX input signal according to the LO signal. The calibration circuit checks a signal characteristic of the processed RX signal by detecting if a calibration tone exists within a receiver bandwidth, set a frequency calibration control output in response to the calibration tone being not found in the receiver bandwidth, and output the frequency calibration control output to the LO signal generation circuit. The LO signal generation circuit adjusts an LO frequency of the LO signal in response to the frequency calibration control output.

Communication circuit and associated calibration method

A communication circuit includes a receiver path, a frequency translating loop filter and a signal source circuit. The frequency translating loop filter includes an auxiliary mixer, and a frequency translating filter backend circuit such as a filter. The signal source circuit can be shared with a transmitter path. When the receiver path receives an external signal, the auxiliary mixer and the frequency translating filter backend circuit perform high-frequency filtering. When the receiver path need not receive the external signal, the auxiliary mixer up-converts a low-frequency auxiliary signal provided by the signal source circuit to a high-frequency domain, and the up-converted signal is received by the receiver path. Thus, an operation parameter of the receiver path can be adjusted and calibrated according to a response of the receiver path.

Layout design for electron-beam high volume manufacturing

The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step. In some embodiments a routing grid is refined to rule out ...

SEMICONDUCTOR CHIP WITH LOCAL OSCILLATOR BUFFER REUSED FOR LOOP-BACK TEST AND ASSOCIATED LOOP-BACK TEST METHOD

A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a loop-back test function through the auxiliary path.

Electron beam data storage system and method for high volume manufacturing

The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.

Apparatus and method for applying frequency calibration to local oscillator signal derived from reference clock output of active oscillator that has no electromechanical resonator

A wireless system includes a local oscillator (LO) signal generation circuit, a receiver (RX) circuit, and a calibration circuit. The LO signal generation circuit generates an LO signal according to a reference clock. The LO signal generation circuit includes an active oscillator. The active oscillator generates the reference clock, wherein the active oscillator includes at least one active component, and does not include an electromechanical resonator. The RX circuit generates a down-converted RX signal by performing down-conversion upon an RX input signal according to the LO signal. The calibration circuit generates a frequency calibration control output according to a signal characteristic of the down-converted RX signal, and outputs the frequency calibration control output to the LO signal generation circuit. The LO signal generation circuit adjusts an LO frequency of the LO signal in response to the frequency calibration control output.

GEOMETRIC PATTERN DATA QUALITY VERIFICATION FOR MASKLESS LITHOGRAPHY

The present disclosure involves a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour. The method includes determining whether the deformed pattern is lithography-ready in response to the identifying.

STRIPING METHODOLOGY FOR MASKLESS LITHOGRAPHY

The present disclosure involves a method of performing a maskless lithography process. The method includes receiving a computer layout file for an integrated circuit (IC) device. The layout file contains a plurality of IC sections. The method includes separating the computer layout file into a plurality of sub-files. The method includes striping the plurality of sub-files concurrently using a plurality of computer processors, thereby generating a plurality of striped sub-files. The method includes transferring the plurality of striped sub-files to a maskless lithography system. 1. A method of fabricating a semiconductor device , comprising:providing a layout plan;dividing the layout plan into a plurality of portions;performing a striping process for each of the portions of the layout plan to generate a plurality of striped portions of the layout plan; andsending the striped portions of the layout plan to a maskless lithography apparatus.2. The method of claim 1 , wherein the performing the striping process is carried out in a manner such that the striping process for each portion of the layout plan is performed using a different one of a plurality of data processing machines that operate concurrently to carry out the striping process.3. The method of claim 1 , further including claim 1 , before the dividing: performing a proximity correction process to the layout plan.4. The method of claim 1 , wherein the dividing is performed according to a set of predefined criteria so as to optimize the dividing.5. The method of claim 1 , wherein the layout plan contains a plurality of integrated circuit (IC) sections claim 1 , and further including: before the dividing claim 1 , merging the IC sections of the layout plan into a single file claim 1 , wherein the dividing is carried out on the single file.6. The method of claim 1 , wherein the layout plan contains a plurality of integrated circuit (IC) sections claim 1 , and wherein the dividing is carried out in a manner such ...

Method and System for Image-Based Defect Alignment

The present disclosure provides one embodiment of a method for defect diagnosis to a semiconductor wafer. The method includes collecting raw data that include a defect image (IMG), defect coordinate-on-wafer (CW) and layout database (DB); performing an image-based defect alignment to IMG according to CW and DB; and compensating coordinate mismatch according to the image-based defect alignment. 1. A method for defect diagnosis to a semiconductor wafer , comprising:collecting raw data that include a defect image (IMG), defect coordinate-on-wafer (CW) and layout database (DB);performing an image-based defect alignment to IMG according to CW and DB; andcompensating coordinate mismatch according to the image-based defect alignment.2. The method of claim 1 , further comprising transferring CW to defect coordinate-on-database (CD) after the collecting raw data and before the performing an image-based defect alignment.3. The method of claim 2 , wherein the compensating the coordinate mismatch further includes extracting a matched coordinate-on-database (CD′) from the image-based defect alignment.4. The method of claim 3 , wherein the compensating the coordinate mismatch further includes finding a coordinate offset based on CD′ and CD.5. The method of claim 4 , wherein the coordinate offset is equals to a difference between CD′ and CD.6. The method of claim 4 , wherein the compensating the coordinate mismatch further includes compensating CW of IMG with the coordinate offset.7. The method of claim 4 , whereinCW is a coordinate of a center point of IMG;the collecting raw data further includes collecting a second defect image with a second CW; andthe compensating the coordinate mismatch further includes compensating the second CW of the second defect image with the coordinate offset.8. The method of claim 7 , wherein IMG and the second defect image are collected from the semiconductor wafer.9. The method of claim 4 , wherein the performing an image-based defect alignment to ...

ELECTRON BEAM DATA STORAGE SYSTEM AND METHOD FOR HIGH VOLUME MANUFACTURING

The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table. 1. A method comprising:receiving a design layout having a data representation of a first data size, wherein the design layout includes a plurality of pattern portions; including the plurality of pattern portions in the data representation of the second size, wherein any pattern portion that is repeated in the design layout is included once in the data representation of the second data size, and', 'creating a lookup table that maps each of the included plurality of pattern portions to at least one location within the design layout; and, 'reducing the data representation from the first data size to a second data size, the second data size being less than the first data size, wherein the reducing includesusing the data representation of the second data size and the lookup table to write the design layout on an energy sensitive layer.2. The method of further including transferring the data representation of the second data size from an electron beam data processing module to an electron beam exposure module claim 1 , wherein the electron beam exposure module writes the design layout on the energy sensitive layer using the data representation of the second data size and the lookup table.3. The method of further including performing a proximity correction process on the data representation of the first data size.4. The method of further including dithering the data representation of the second data size.5. The method of further including storing the data ...

Geometric pattern data quality verification for maskless lithography

Provided is a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour. The method includes determining whether the deformed pattern is lithography-ready in response to the identifying ...

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Electron beam data storage system and method for high volume manufacturing

The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.

SEMICONDUCTOR CHIP WITH LOCAL OSCILLATOR BUFFER REUSED FOR SIGNAL TRANSMISSION AND ASSOCIATED TRANSMISSION METHOD

A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a transmit (TX) function through the auxiliary path.

SEMICONDUCTOR CHIP WITH LOCAL OSCILLATOR BUFFER REUSED FOR LOOP-BACK TEST AND ASSOCIATED LOOP-BACK TEST METHOD

A semiconductor chip includes a first wireless communication circuit, a second wireless communication circuit, and an auxiliary path. The first wireless communication circuit includes a signal path, wherein the signal path includes a signal node. The second wireless communication circuit includes a mixer and a local oscillator (LO) buffer. The LO buffer is arranged to receive and buffer an LO signal, and is further arranged to provide the LO signal to the mixer. The auxiliary path is arranged to electrically connect the LO buffer to the signal node of the signal path, wherein the LO buffer is reused for a loop-back test function of the first wireless communication circuit through the auxiliary path.

Reconfigurable RF front end and antenna arrays for radar mode switching

Concepts and examples pertaining to reconfigurable radio frequency (RF) front end and antenna arrays for radar mode switching are described. A processor associated with a radar system selects a mode of a plurality of modes in which to operate the radar system. The processor then controls the radar system to operate in the selected mode by utilizing a plurality of antennas in a respective configuration of a plurality of configurations of the antennas which corresponds to the selected mode. Each configuration of the plurality of configurations of the antennas results in respective antenna characteristics. Each configuration of the plurality of configurations of the antennas utilizes a respective number of antennas of the plurality of antennas.

CONTOUR ALIGNMENT SYSTEM

The present disclosure describes a method of calibrating a contour. The method includes designing an anchor pattern, printing the anchor pattern on a substrate, collecting scanning electron microscope (SEM) data of the printed anchor pattern on the substrate, wherein the SEM data includes a SEM image of the printed anchor pattern on the substrate, converting the SEM image of the printed anchor pattern on the substrate into a SEM contour of the printed anchor pattern, analyzing the SEM contour of the printed anchor pattern, and aligning the SEM contour of the anchor pattern to form the calibrated SEM contour. 1. A method of calibrating a contour , the method performed by a data processor , the method comprising:designing a pattern, wherein the pattern includes a designed anchor pattern and a designed verification pattern to be printed onto a substrate;collecting scanning electron microscope (SEM) data of a printed anchor pattern on the substrate, wherein the SEM data includes a SEM image of the printed anchor pattern on the substrate;converting the SEM image of the printed anchor pattern on the substrate into a SEM contour of the printed anchor pattern;analyzing the SEM contour of the printed anchor pattern; andaligning the SEM contour of the anchor pattern, to calibrate the SEM contour.2. The method of claim 1 , wherein analyzing the SEM contour of the printed anchor pattern includes measuring a distance between the SEM contour of the printed anchor pattern and the designed anchor pattern at a contour point.3. The method of claim 2 , further comprising calculating a plurality of distortion parameters of the SEM contour of the printed anchor pattern using the distance between the SEM contour of the printed anchor pattern and the designed anchor pattern at a contour point.4. The method of claim 3 , wherein calculating the distortion parameters of the SEM contour includes calculating displacement claim 3 , scale claim 3 , or rotation of the SEM contour of the printed ...

Method for high volume e-beam lithography

The present disclosure describes a method of forming a pattern by an electron beam lithography system. The method includes receiving an integrated circuit (IC) design layout data having a polygon and a forbidden pattern, modifying the polygon and the forbidden pattern using an electron proximity correction (EPC) technique, stripping the modified polygon into subfields, converting the stripped polygon to an electron beam writer format data, and writing the electron beam writer formatted polygon onto a substrate by an electron beam writer. Stripping the modified polygon includes finding the modified forbidden pattern as a reference layer, and stitching the modified polygon to avoid stitching the modified forbidden pattern.

Method for high volume e-beam lithography

The present disclosure describes a method of forming a pattern by an electron beam lithography system. The method includes receiving an integrated circuit (IC) design layout data having a polygon and a forbidden pattern, modifying the polygon and the forbidden pattern using an electron proximity correction (EPC) technique, stripping the modified polygon into subfields, converting the stripped polygon to an electron beam writer format data, and writing the electron beam writer formatted polygon onto a substrate by an electron beam writer. Stripping the modified polygon includes finding the modified forbidden pattern as a reference layer, and stitching the modified polygon to avoid stitching the modified forbidden pattern.

Electron beam data storage system and method for high volume manufacturing

The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.

Semiconductor chip with local oscillator buffer reused for signal transmission and associated transmission method

A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a transmit (TX) function through the auxiliary path.

Wireless system having local oscillator signal derived from reference clock output of active oscillator that has no electromechanical resonator

A wireless system includes an active oscillator and a front-end circuit. The active oscillator is used to generate and output a reference clock. The active oscillator includes at least one active component, and does not include an electromechanical resonator. The front-end circuit is used to process a transmit (TX) signal or a receive (RX) signal according to a local oscillator (LO) signal. The LO signal is derived from the reference clock.

Electron Beam Data Storage System and Method for High Volume Manufacturing

The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table. 1. A particle beam apparatus comprising:a particle beam source operable to generate at least one particle beam;a beam controller operable to selectively expose portions of a substrate to the at least one particle beam in response to a write instruction; and receive a design layout;', 'generate a lookup table mapping a plurality of instances of a repeating pattern in the design layout to a single representation of the repeating pattern to thereby reduce a data size of the design layout; and', 'generate the write instruction based on the lookup table., 'a data processing module operable to2. The particle beam apparatus of claim 1 , wherein the lookup table correlates the representation of the repeating pattern to a location of each instance of the plurality of instances of the repeating pattern.3. The particle beam apparatus of claim 1 , wherein the data processing module is further operable to divide the design layout into a plurality of stripe/segment regions of a size such that each of the plurality of stripe/segment regions is associated with a single beam of the at least one particle beam.4. The particle beam apparatus of claim 3 , wherein the representation of the repeating pattern represents a region equivalent in area to each of the plurality of stripe/segment regions.5. The particle beam apparatus of claim 1 , wherein the data processing module is further operable to divide the design layout into a plurality of regions corresponding to at least ...

LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF

A manufacturing method of light-emitting device is disclosed. The method includes providing an LED wafer comprising a substrate and a semiconductor stack formed on the substrate, wherein the semiconductor stack has a lower surface; providing a first laser to the LED wafer to cut through the semiconductor stack with a depth into the substrate; providing and focusing a second laser on an interior of the substrate to form a plurality of textured areas in the substrate; and providing force on the LED wafer to separate the LED wafer into a plurality of LED chips. 1. A method of manufacturing a light-emitting device , comprising:providing a light-emitting diode wafer, comprising a substrate and a semiconductor stack on the substrate, wherein the semiconductor stack has a lower surface;providing a first laser to the light-emitting diode wafer to cut through the semiconductor stack with a depth into the substrate;providing and focusing a second laser on an interior of the substrate to form a plurality of textured areas in the substrate; andproviding force on the light-emitting diode wafer to separate the light-emitting diode wafer into a plurality of light-emitting diode chips.2. The method of claim 1 , wherein the textured area has a roughness (root mean squared) of ranges from 1 μm to 5 μm.3. The method of claim 1 , wherein a thickness of the substrate is not smaller than 150 μm.4. The method of claim 1 , wherein the second laser is a stealth dicing laser claim 1 , and the stealth dicing laser is repeatedly irradiated in the substrate for a number of cycles to form the plurality of textured areas on the same cross section of the substrate.5. The method of claim 4 , wherein a thickness of the substrate is not smaller than 150 μm claim 4 , and the number of cycles is not greater than a value rounded up to integer of (thickness of the substrate −100)μm/50.6. The method of claim 4 , wherein the repeated stealth dicing laser comprises:performing a first stealth dicing laser ...

WIRELESS SYSTEM HAVING LOCAL OSCILLATOR SIGNAL DERIVED FROM REFERENCE CLOCK OUTPUT OF ACTIVE OSCILLATOR THAT HAS NO ELECTROMECHANICAL RESONATOR

A wireless system includes an active oscillator and a front-end circuit. The active oscillator is used to generate and output a reference clock. The active oscillator includes at least one active component, and does not include an electromechanical resonator. The front-end circuit is used to process a transmit (TX) signal or a receive (RX) signal according to a local oscillator (LO) signal. The LO signal is derived from the reference clock. 1. A wireless system comprising:an active oscillator, arranged to generate and output a reference clock, wherein the active oscillator comprises at least one active component, and does not include an electromechanical resonator; anda front-end circuit, arranged to process a transmit (TX) signal or a receive (RX) signal according to a local oscillator (LO) signal, wherein the LO signal is derived from the reference clock.2. The wireless system of claim 1 , wherein the wireless system is a Radio Detection and Ranging (radar) system.3. The wireless system of claim 1 , wherein the LO signal has an LO frequency at a 3.1-10.6 GHz band claim 1 , 24 GHz claim 1 , 60 GHz claim 1 , a 76-77 GHz band claim 1 , or a 77-81 GHz band.4. The wireless system of claim 1 , wherein the wireless system is implemented on a chip claim 1 , and the active oscillator is an on-chip oscillator.5. The wireless system of claim 1 , wherein the reference clock with an LO frequency is supplied to the front-end circuit claim 1 , and the reference clock received by the front-end circuit acts as the LO signal directly.6. The wireless system of claim 1 , further comprising:a frequency processing circuit, arranged to receive the reference clock with a reference frequency different from an LO frequency, generate the LO signal with the LO frequency according to the reference clock, and output the LO signal to the front-end circuit.7. The wireless system of claim 1 , further comprising:a digital circuit, arranged to perform at least one data processing function according ...

LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME

A light emitting device, includes: a substrate, including a top surface, a bottom surface, a first side surface connecting the top surface and the bottom surface, a first group of deteriorated region, and a second group of deteriorated region; and a semiconductor stack formed on the top surface of the substrate, wherein the first side surface includes a first group of convex region and a first group of concave region, wherein the first group of convex region includes the first group of deteriorated region, and the first group of concave region includes the second group of deteriorated region. 1. A light emitting device , comprising:a substrate, comprising a top surface, a bottom surface, a first side surface connecting the top surface and the bottom surface, a first group of deteriorated region, and a second group of deteriorated region; anda semiconductor stack formed on the top surface of the substrate, wherein the first side surface comprises a first group of convex region and a first group of concave region, wherein the first group of convex region comprises the first group of deteriorated region, and the first group of concave region comprises the second group of deteriorated region.2. The light emitting device as claimed in claim 1 , wherein the first group of deteriorated region comprises one or a plurality of first deteriorated regions claim 1 , the second group of deteriorated region comprises one or a plurality of second deteriorated regions claim 1 , wherein the first group of convex region comprises a first convex region claim 1 , and the first group of concave region comprises a first concave region claim 1 , wherein a top of the first convex region comprises the one or the plurality of first deteriorated regions claim 1 , and a bottom of the first concave region comprises the one or the plurality of second deteriorated regions.3. The light emitting device as claimed in claim 2 , wherein the first group of deteriorated region further comprises one or a ...

Relief engraved doorplate

A type of relief engraved doorplate, comprising an inside plate that is composed of a first Bakelite layer and a second Bakelite layer, said first Bakelite layer and second Bakelite layer being composed of coarse wood dust and fine wood powder respectively, the second Bakelite layer enveloping the exterior of the first Bakelite layer before they are subjected to heated compression molding to obtain the relief engraved pattern on the top and bottom panels of the inside plate; and, at least one pair of outside decorative plates, including at least a layer of thin wood plate and a layer of water-resistant paper, the water-resistant paper being glued onto the thin wood plate and put in a compression mold with a pattern that is opposite to that of the inside plate, to obtain a depressed pattern on one side of the outside decorative plate, which is opposite to the relief engraved pattern on the inside plate, and then it is fitted to the top and bottom panels of the inside plate and subjected to compression molding process to obtain a relief engraved doorplate that has a tightly knit structure and tenacity to resist water and fire.

Wireless system having local oscillator signal derived from reference clock output of active oscillator that has no electromechanical resonator

A wireless system includes an active oscillator and a front-end circuit. The active oscillator is used to generate and output a reference clock. The active oscillator includes at least one active component, and does not include an electromechanical resonator. The front-end circuit is used to process a transmit (TX) signal or a receive (RX) signal according to a local oscillator (LO) signal. The LO signal is derived from the reference clock.

A method of making an ic design layout, ic design layout and a method of locating a pattern in an ic design layout

Relief engraved doorplate

A type of relief engraved doorplate, comprising an inside plate that is composed of a first Bakelite layer and a second Bakelite layer, said first Bakelite layer and second Bakelite layer being composed of coarse wood dust and fine wood powder respectively, the second Bakelite layer enveloping the exterior of the first Bakelite layer before they are subjected to heated compression molding to obtain the relief engraved pattern on the top and bottom panels of the inside plate; and, at least one pair of outside decorative plates, including at least a layer of thin wood plate and a layer of water-resistant paper, the water-resistant paper being glued onto the thin wood plate and put in a compression mold with a pattern that is opposite to that of the inside plate, to obtain a depressed pattern on one side of the outside decorative plate, which is opposite to the relief engraved pattern on the inside plate, and then it is fitted to the top and bottom panels of the inside plate and subjected to compression molding process to obtain a relief engraved doorplate that has a tightly knit structure and tenacity to resist water and fire.

Semiconductor chip with local oscillator buffer reused for loop-back test and associated loop-back test method

A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a loop-back test function through the auxiliary path.

通訊電路與相關校準方法

一種通訊電路與相關校準方法。通訊電路包括接收路徑、轉頻迴路濾波器與訊源電路；轉頻迴路濾波器可包括一輔助混波器與一轉頻濾波後側電路，如一濾波器；訊源電路可以與一發射路徑共用。當接收路徑接收外來訊號時，輔助混波器與轉頻濾波後側電路可進行高頻領域濾波。當接收路徑不接收外來訊號時，輔助混波器可將訊源電路提供的低頻輔助訊號升轉至高頻領域，並由接收路徑接收，以依據接收路徑的響應調整、校準接收路徑的運作參數。

Semiconductor chip with local oscillator buffer reused for loop-back test and associated loop-back test method

A semiconductor chip includes a first wireless communication circuit, a second wireless communication circuit, and an auxiliary path. The first wireless communication circuit includes a signal path, wherein the signal path includes a signal node. The second wireless communication circuit includes a mixer and a local oscillator (LO) buffer. The LO buffer is arranged to receive and buffer an LO signal, and is further arranged to provide the LO signal to the mixer. The auxiliary path is arranged to electrically connect the LO buffer to the signal node of the signal path, wherein the LO buffer is reused for a loop-back test function of the first wireless communication circuit through the auxiliary path.

通訊電路與相關校準方法

圖案化基板的方法

目前揭露描述一藉由電子束微影系統形成一圖案之方法。此方法包括：接收一積體電路(IC)設計佈局數據，包括具有一多邊形以及一禁止圖形之複數個圖案層；利用電子鄰近校正技術(EPC)分解多邊形至多個子域；轉換已分解之多邊形至一電子束寫入格式資料；以及藉由一電子束寫入機寫入電子束寫入格式資料於一基板。分解已修改之多邊形的步驟包括尋找一已修改之禁止圖形作為一參考層，並且經由避免分解禁止圖形分解已修改之多邊形。

Semiconductor chip with local oscillator buffer reused for signal transmission and associated transmission method

A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a transmit (TX) function through the auxiliary path.