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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 1616. Отображено 100.
05-07-2012 дата публикации

Performing a perform timing facility function instruction for synchronizing tod clocks

Номер: US20120173917A1
Автор: Eberhard Engler, Evangelyn K. Smith, Klaus Meissner, Mark A. Check, Mark S. Farrell, Ronald M. Smith, Sr.
Принадлежит: International Business Machines Corp

A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The method includes receiving, at a processing unit, a request to change a clock steering rate used to control a TOD-clock offset value for the processing unit, the TOD-clock offset defined as a function of a start time (s), a base offset (b), and a steering rate (r). The unit schedules a next episode start time with which to update the TOD-clock offset value. After updating TOD-clock offset value (d) at the scheduled time, TOD-clock offset value is added to a physical-clock value (Tr) value to obtain a logical TOD-clock value (Tb), where the logical TOD-clock value is adjustable without adjusting a stepping rate of the oscillator.

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Номер записи: 1
25-10-2012 дата публикации

Electronic Timepiece and Time Adjustment Method

Номер: US20120269042A1
Автор: Katsuyuki Honda
Принадлежит: Seiko Epson Corp

An electronic timepiece efficiently receives satellite signals, reduces power consumption, and displays the correct time. A GPS wristwatch 1 has a satellite signal reception unit 10 A that receives satellite signals and acquires time information contained in the satellite signals; a time information adjustment unit 25 that keeps times and adjusts the kept time based on the time information acquired by the automatic receiving unit 24 ; a reception result memory unit 313 that stores the reception result of the reception process performed by the automatic receiving unit 24 ; and a reception time setting unit 21 that sets the reception start time at which the reception process starts based on the reception result stored in the reception result memory unit 313. The automatic receiving unit 24 executes the reception process when the kept time reaches the reception start time set by the reception time setting unit 21.

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Номер записи: 2
28-03-2013 дата публикации

CONVERSION OF TIMESTAMPS BETWEEN MULTIPLE ENTITIES WITHIN A COMPUTING SYSTEM

Номер: US20130080818A1
Автор: III ALWOOD P., Kumar Aditya, WENDZEL KEVIN, Williams
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Method is described for converting received timestamps to a time-recording standard recognized by the receiving computing system. Embodiments of the invention generally include receiving data from an external device that includes a timestamp. If the received data is the first communication from the external device, creating a time base used for converting subsequently received timestamps to a recognized standard. Moreover, the system updates the time base if a counter failure at the external device is detected. When the external device transmits subsequent data, the time base is added to the subsequently received timestamps to convert the subsequent timestamps to a time-recording standard recognized by the computing system. 1. A method of converting a timestamp between a computing system and a subsystem of the computing system , comprising:receiving a relative timestamp from the subsystem;upon determining that a time skew has occurred based on the relative timestamp and a time base, updating the time base by operation of one or more computer processors, wherein the time base is a conversion variable for converting the relative timestamp to an absolute timestamp,if the time base is updated, determining the absolute timestamp based on the relative timestamp and the updated time base, wherein the absolute timestamp is a timestamp of a time measure used by the computing system; andif the time base is not updated, determining the absolute timestamp based on the relative timestamp and the time base.2. The method of claim 1 , wherein determining that the time skew has occurred comprises claim 1 ,adding the time base to the relative timestamp to yield a predicted time of transmission; anddetermining whether the predicted time of transmission is within a pre-defined delta from an absolute system time, wherein the absolute system time is a timestamp of the time measure used by computing system and indicates when the relative timestamp was received.3. The method of claim 1 , ...

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Номер записи: 3
06-06-2013 дата публикации

TIME MEASUREMENT DEVICE, MICRO-CONTROLLER AND METHOD OF MEASURING TIME

Номер: US20130145198A1
Автор: YASUDA Kosuke
Принадлежит: LAPIS SEMICONDUCTOR CO., LTD.

A time measurement device includes a first measurement unit configured to measure a clock number of a first reference clock signal within a specific cycle of a second reference clock signal; a calculation unit configured to calculate a physical amount indicating a variance amount of the clock number relative to a reference clock number; a compensation unit configured to compensate an expected measurement value indicating the clock number of the first reference clock signal corresponding to a time as a measurement target according to the physical amount calculated with the calculation unit; and an output unit configured to output time information indicating that the clock number of the first reference clock signal reaches the expected measurement value when the clock number of the first reference clock signal measured with the first measurement unit reaches the expected measurement value compensated with the compensation unit. 1. A time measurement device comprising:a first measurement unit configured to measure a clock number of a first reference clock signal within a specific cycle of a second reference clock signal, said second reference clock signal having an oscillation frequency lower than that of the first reference clock signal and oscillation accuracy higher than that of the first reference clock signal;a calculation unit configured to calculate a physical amount indicating a variance amount of the clock number measured with the first measurement unit relative to a reference clock number measured in advance as the clock number of the first reference clock signal within the specific cycle of the second reference clock signal;a compensation unit configured to compensate an expected measurement value indicating the clock number of the first reference clock signal corresponding to a time as a measurement target according to the physical amount calculated with the calculation unit; andan output unit configured to output time information indicating that the clock ...

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Номер записи: 4
27-06-2013 дата публикации

CALCULATION APPARATUS, CALCULATION METHOD, AND RECORDING MEDIUM FOR CALCULATION PROGRAM

Номер: US20130166941A1
Автор: Kato Miho, Kitayama Tsubasa, Kurobane Norio, SUZUKI Hiroyuki
Принадлежит: FUJITSU LIMITED

A calculation method includes calculating, by a processor, a difference between a first value and a second value, the first value being read from a clock counter that counts pulses of a clock signal having a plurality of types of frequencies, supplied to the processor in response to control command to start processing for an unit to be allocated to the processor, the second value being read from the clock counter in response to control command to stop processing. 1. A calculation method comprising:calculating, by a processor, a difference between a first value and a second value, the first value being read from a clock counter that counts pulses of a clock signal having a plurality of types of frequencies, supplied to the processor in response to control command to start processing for an unit to be allocated to the processor, the second value being read from the clock counter in response to control command to stop processing.2. The calculation method according to claim 1 , further comprising:calculating a cost value obtained by multiplying the calculated difference with a coefficient indicating a cost value for a certain type per unit number of clock ticks.3. The calculating method according to claim 1 , whereinwhether the control command to stop processing is performed is determined in accordance with a processing status of the processor.4. The calculation method according to claim 1 , further comprising:storing, in a storage device, the calculated difference in association with identification information that identifies the unit.5. The calculating method according to claim 4 , further comprising:calculating a difference between a third value and a fourth value, the third value being read from the clock counter in response to control command to start processing further performed when processing of the unit is to be further performed, the fourth value being read from the clock counter in response to control command to stop the processing that has been controlled to ...

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Номер записи: 5
04-07-2013 дата публикации

OPERATING METHOD AND PORTABLE ELECTRONIC DEVICE USING THE SAME

Номер: US20130170324A1
Автор: Gong Jian-Wei, Huang Shuai-Feng, Tu Chang-Jhu, WANG Chun-Yi
Принадлежит: ASUSTEK COMPUTER INC.

An operating method of a clock-calendar and a portable electronic device using the same are provided, where a touch screen display of the portable electronic device displays the clock-calendar with a clock pattern. In the method, a gesture on the touch screen display corresponding to the clock-calendar is detected and analyzed, where the gesture includes a gesture starting point and a gesture finishing point on the touch screen display. After the gesture is analyzed, the clock-calendar is operated according to the gesture. 1. An operating method for a portable electronic device having a touch screen display , wherein the touch screen display displays a clock-calendar having a clock pattern , the operating method comprising:detecting an gesture on the touch screen display corresponding to the clock-calendar, wherein the gesture comprises an gesture starting point and an gesture finishing point;analysing the gesture; andoperating the clock-calendar according to the gesture.2. The operating method as claimed in claim 1 , wherein when the gesture corresponds to an operation for creating an event claim 1 , an event line segment corresponding to the event and event information corresponding to the gesture are displayed at a peripheral of the clock pattern claim 1 , wherein the event line segment is used to represent a duration of the event claim 1 , the gesture starting point corresponds to a start time of the event claim 1 , and the gesture finishing point corresponds to an end time of the event.3. The operating method as claimed in claim 2 , further comprising:displaying an edit window on the touch screen display to edit the event.4. The operating method as claimed in claim 2 , further comprising:displaying a floating dialog box on the clock-calendar to edit the event.5. The operating method as claimed in claim 1 , wherein when the gesture corresponds to an operation for deleting an event claim 1 , the gesture starting point of the gesture corresponds to an event line ...

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Номер записи: 6
29-08-2013 дата публикации

Information processing apparatus, control method therefor, and recording medium

Номер: US20130222614A1
Автор: Toshiyuki Takagi
Принадлежит: Canon Inc

An information processing apparatus capable of communicating with a first external device storing first time information and a second external device storing second time information, the information processing apparatus, includes a storage unit configured to store third time information, a reception unit configured to receive the first time information, a time adjustment unit configured to regularly adjust the third time information based on the first time information, an operation unit configured to receive a synchronization instruction from a user, a time synchronization unit configured to communicate with the second external device and synchronize the second time information and the third time information if the synchronization instruction is received by the operation unit, and a notification unit configured to notify the user that the third time information can be adjusted by the time adjustment unit in a case of the synchronization instruction being received by the operation unit.

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Номер записи: 7
05-09-2013 дата публикации

Method and Memory Device for Generating a Time Estimate

Номер: US20130232308A1
Автор: Dror Itai, Pomerantz Itzhak, Stern Ori, Yairi Rahav
Принадлежит:

A method and memory device for generating a time estimate are provided. In one embodiment, a memory device generates a time estimate from time stamps in file system metadata for a plurality of files stored in the memory device and uses the time estimate to perform a time-based activity in the memory device. In another embodiment, a memory device generates a time estimate from time stamps stored in a plurality of files stored in the memory device and uses the time estimate to perform a time-based activity in the memory device. In yet another embodiment, a memory device obtains a plurality of time stamps, selects one or more of the plurality of time stamps based on validity rankings, generates a time estimate from the selected time stamp(s), and uses the time estimate to perform a time-based activity in the memory device. 1. A method for generating a time estimate in a memory device , the method comprising: storing in the memory device: (i) a plurality of files and (ii) file system metadata for each of the plurality of files, wherein file system metadata for a given file contains a time stamp associated with that file;', 'generating an estimate of what time it is from the time stamps in the file system metadata for the plurality of files, wherein the memory device does not have a real-time clock; and', 'using the estimate of what time it is to perform a time-based activity in the memory device., 'performing by a processor in a memory device embedded in and in communication with a host2. The method of claim 1 , wherein the time-based activity comprises sending a request to the host for scheduling a memory device management task.3. The method of claim 1 , wherein the file system metadata comprises an entry in a file allocation table.4. The method of claim 1 , wherein the time stamp comprises one or more of the following: a file creation time claim 1 , a last access time claim 1 , and a last modification time.5. The method of claim 1 , wherein the time-based activity ...

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Номер записи: 8
26-09-2013 дата публикации

INFORMATION PROCESSING APPARATUS AND COMPUTER PROGRAM PRODUCT

Номер: US20130254427A1
Автор: Kozakai Yasuyuki
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to an embodiment, an information processing apparatus includes a selector. The selector is configured to acquire a first time obtained by converting a measurement time of a first piece of measurement data based on a clock of a first time server, a second time obtained by converting the measurement time of the first piece of measurement data based on a clock of a second time server, a third time obtained by converting a measurement time of a second piece of measurement data based on the clock of the first time server, and a fourth time obtained by converting the measurement time of the second piece of measurement data based on the clock of the second time server. The selector is also configured to select a time server with the largest number of combinations of the converted times resulting in no error among pieces of measurement data and time servers. 1. An information processing apparatus , comprising: acquire a first converted time obtained by converting a measurement time of a first piece of measurement data on the basis of a clock of a first time server, a second converted time obtained by converting the measurement time of the first piece of measurement data on the basis of a clock of a second time server, a third converted time obtained by converting a measurement time of a second piece of measurement data on the basis of the clock of the first time server, and a fourth converted time obtained by converting the measurement time of the second piece of measurement data on the basis of the clock of the second time server,', 'determine whether an error occurs on the basis of the first, second, third, and fourth converted times,', 'calculate the number of combinations of the first, second, third, and fourth converted times in which it is determined that no error occurs among two or more pieces of measurement data and two or more time servers, and', 'select a time server with the largest number of combinations., 'a selector configured to'}2. The apparatus ...

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Номер записи: 9
03-10-2013 дата публикации

METHOD AND DATA PROCESSING UNIT FOR PROVIDING A TIMESTAMP

Номер: US20130262911A1
Автор: BOERGER Ralf Grosse, Schmidt Marco
Принадлежит: dSPACE digital signal processing and control engineering GmbH

A method for providing a timestamp in a real-time system, whereby the real-time system has an FPGA and a CPU, which cooperate with one another, and at least one register, which contains a system time, is implemented in the FPGA. The method includes the steps of providing a CPU counter for the system time, which is driven by a clock signal of the CPU, providing a synchronization counter in the CPU, whereby the synchronization counter is driven by a clock signal of the CPU, reading of the counter for providing the system time by a real-time application, querying the synchronization counter in the real-time application, and synchronizing the counter with the system time in the real-time application, when the synchronization counter outputs a value that corresponds to more than a predefined time period since the last synchronization of the CPU counter with the system time. 1. A method for providing a timestamp in a real-time system , the real-time system comprising an FPGA and a CPU , which cooperate with one another , and at least one register , which contains a system time , is implemented in the FPGA , the method comprising:providing a CPU counter for the system time, the counter being driven by a clock signal of the CPU;providing a synchronization counter in the CPU, the synchronization counter being driven by a clock signal of the CPU;reading the CPU counter to provide the system time by a real-time application;querying the synchronization counter in the real-time application; andsynchronizing the CPU counter with the system time in the real-time application when the synchronization counter outputs a value that corresponds to more than a predetermined time period since the last synchronization of the CPU counter with the system time.2. The method according to claim 1 , wherein the synchronizing of the CPU counter with the system time comprises storing the CPU counter and the FPGA register value at the time of the synchronization claim 1 , and wherein the step of ...

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Номер записи: 10
31-10-2013 дата публикации

COMMAND PROTOCOL FOR ADJUSTMENT OF WRITE TIMING DELAY

Номер: US20130290767A1
Автор: Barakat Shadi M., Kruger W. Fritz, LEE Ming-Ju E., Litt Michael J., Nygren Aaron J., Pham Toan D., Xu Xiaoling
Принадлежит:

Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data. 1. An apparatus for adjusting write timing , the apparatus comprising:an address/control bus configured to concurrently enable a write clock data recovery (WCDR) mode of operation and an active mode of operation;a WCDR signal bus configured to transmit WCDR data to a memory device during the WCDR mode of operation; anda timing adjustment module configured to adjust a timing based on a phase shift in the WCDR data.2. The apparatus of claim 1 , wherein an unused address/control bit from the address/control bus is configured to enable the WCDR mode of operation.3. The apparatus of claim 1 , wherein the WCDR data comprises a data pattern substantially similar to a data signal on a data bus.4. The apparatus of claim 1 , wherein the WCDR data comprises a data pattern with a periodic pattern.5. The apparatus of claim 1 , wherein the active mode of operation comprises at least one of a read claim 1 , a write claim 1 , and a refresh mode of operation.6. The apparatus of claim 1 , wherein the WCDR signal bus is configured for an alternate function outside of the WCDR mode of operation.7. The apparatus of claim 6 , wherein the alternate function comprises providing an external voltage reference to the apparatus.8. The apparatus of claim 1 , wherein the WCDR signal bus is configured to receive data associated with the phase shift from the memory device.9. The apparatus of claim 1 , whereinthe WCDR signal bus is configured to receive a ...

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Номер записи: 11
21-11-2013 дата публикации

MULTIPOINT SIMULTANEOUS MEASUREMENT METHOD AND MULTIPOINT SIMULTANEOUS MEASUREMENT SYSTEM IN ELECTRIC POWER STATION, AND INTERNAL CLOCK USED THEREFOR

Номер: US20130311135A1
Автор: CHIBA Tatsuya, Sato Masaki, YANAGISAWA Yoichi
Принадлежит:

A multipoint simultaneous measurement method and a multipoint simultaneous measurement system in an electric power station and an internal clock used therefor, capable of performing measurement at the correct time even at a place in the electric power station where GPS radio waves cannot be received, and of securing simultaneity with high accuracy and with ease without connecting a plurality of measurement points via a cable and the like. 15-. (canceled)6. A multipoint simultaneous measurement method in an electric power station , comprising the steps of:providing a plurality of measuring devices and a master unit configured to be able to wirelessly transmit/receive a signal to/from the measuring devices;providing an internal clock that is operated by time correcting means having an oscillator contained therein and a counter for counting an output pulse from the oscillator in each of the measuring devices, the internal clock being configured to correct its time by adding a difference between a pulse number that is obtained by multiplying an actual oscillating frequency oscillated by the oscillator by a fixed period of time and a product that is obtained by multiplying a target oscillating frequency by the fixed period of time, to the pulse number at intervals of the fixed period of time, the fixed period of time being a time when the pulse number after a decimal point of the oscillating frequency of the oscillator is rounded to be an integer;synchronizing the internal clocks of the measuring devices by UPS radio waves or by connecting the measuring devices;correcting the internal clocks of the measuring devices continuously at intervals of the fixed period of time from when the internal clocks are synchronized until when measurement is finished;arranging the measuring devices to respective measurement points;transmitting a measurement time from the master unit to the measuring devices; andmeasuring a predetermined physical quantity by the measuring devices when the ...

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Номер записи: 12
23-01-2014 дата публикации

INFORMATION PROCESSING EQUIPMENT AND CONTROL METHOD

Номер: US20140025982A1
Автор: HATAMORI Shuei
Принадлежит: FUJITSU LIMITED

Information processing equipment that has one or plurality of partitions further includes: a detection unit configured to detect switching of a clock unit from a first clock unit for counting a time used by an operating system in the partition to a second clock unit; a first setting unit configured to set a time obtained from the first clock unit to a third clock unit for counting a time used in the partition when switching of the clock unit is not detected, and to set a time obtained from the third clock unit to the second clock unit when switching of the clock unit is detected; and a second setting unit configured to set a time that is set to the first clock unit by the operating system to the third clock unit when time setting to the first clock unit performed by the operating system is detected. 1. Information processing equipment that has one or plurality of partitions , the information processing equipment comprising:a detection unit configured to detect switching of a clock unit from a first clock unit for counting a time used by an operating system in the partition to a second clock unit;a first setting unit configured to set a time obtained from the first clock unit to a third clock unit for counting a time used in the partition when switching of the clock unit is not detected, and to set a time obtained from the third clock unit to the second clock unit when switching of the clock unit is detected; and{'b': '20', 'a second setting unit configured to set a time that is set to the first clock unit by the operating system to the third clock unit when time setting to the first clock unit performed by the operating system is detected.'}2. The information processing equipment according to claim 1 , further comprising a control unit configured to control configuration of the partition claim 1 , whereinwhen the control unit changes hardware included in the partition and a clock unit included in the hardware that is used before the change is the first clock unit ...

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Номер записи: 13
06-03-2014 дата публикации

Devices for Quantifying the Passage of Time

Номер: US20140064039A1
Автор: Jones John David
Принадлежит: DS ZODIAC, INC.

Devices, systems, and methods for presenting date and time information are described. In some embodiments, a date and/or a time value is presented as a base-36 number. In some embodiments, an integral portion of the base-36 number represents a date value, and a fractional portion of the base-36 number represents a time value. Each base-36 digit may be represented by one of the numerals 0-9 and the letters A-Z. Both digital and analog clocks and a clock application displaying date and/or time information in which a day is broken into thirty-six increments are disclosed. A clock application displaying coordinates of a location based on a base-36 geo-positioning system is disclosed. 1. A mobile device for displaying time information , comprising:a mechanism configured to generate an indication of passing time;a processor configured to interpret the generated indication of passing time received from the mechanism, wherein the processor is running a clock application;at least one input device communicatively coupled to the processor; anda display communicatively coupled to the processor and configured to present an alphanumeric string representing a time; cause the display to present an alphanumeric string representing the time in a first format or a second format; and', 'cause the display to switch between the first format and the second format in response to an interaction with the at least one input device;, 'wherein the processor is configured towherein the first format includes a time of day in an hours-minutes format;{'b': '36', 'wherein the second format includes a time that has passed since a beginning of a day in base- format.'}2. The mobile device as recited in claim 1 , wherein the first format includes a date in a traditional calendar format claim 1 , and wherein the second format includes a number of days that have passed since a specified point in time in base-36 format.3. The mobile device as recited in claim 2 , wherein the time that has passed since the ...

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Номер записи: 14
27-03-2014 дата публикации

ELECTRONIC WATCH

Номер: US20140086023A1
Автор: Enokida Michihiro, Kasai Tsuneharu, Mamiya Masahiro, Maruyama Tetsuro, Nakamura Fumio
Принадлежит:

Provided is an electronic watch capable of surely acquiring a movement start position and a stop position of a hand when the hand moves at high speed such as a case of manual correction by a winding stem or the like, while reducing a load on a CPU. The electronic watch includes: a decode circuit for outputting data corresponding to regions acquired by segmenting a movement range of the hand; and a position information circuit for automatically acquiring region data corresponding to the movement start position of the hand and region data corresponding to the stop position thereof and sending a notification to the CPU when acquiring both the data. In this manner, the CPU can stop until the acquisition of both the data, thereby reducing the load on the CPU. 1. An electronic watch , comprising:an indicator;a decode circuit configured to segment a whole movable region of the indicator and output region data corresponding to the segmented regions;a position information circuit configured to acquire movement start region data corresponding to a movement start position of the indicator and stop region data corresponding to a stop position after start of movement, and configured to output, when the movement start region data or the stop region data are acquired, an acquisition signal indicating that one or both of the movement start region data and stop region data are acquired; anda control unit configured to acquire the movement start region data and the stop region data from the position information circuit in response to the acquisition signal from the position information circuit, and configured to perform processing relating to the movement of the indicator.3. The electronic watch according to claim 2 , wherein the acquisition signal is output from the stop circuit when the stop region data is acquired by the stop circuit.4. The electronic watch according to claim 1 , wherein the whole movable region of the indicator is segmented within a limited region around a ...

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Номер записи: 15
27-03-2014 дата публикации

SEMICONDUCTOR DEVICE, CONTROL METHOD FOR THE SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME

Номер: US20140089723A1
Автор: Kondo Chikara, Nishioka Naohisa
Принадлежит: ELPIDA MEMORY, INC.

The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side. 1. A device comprising: a plurality of first terminals;', 'a plurality of second terminals;', 'a plurality of first memory blocks each including a plurality of first memory cells, each of the first memory blocks being configured to be accessed to produce first data;', 'a plurality of first circuits each producing a first output timing control signal;', 'a plurality of first buffers each coupled to an associated one of the first terminals, an associated one of the first memory blocks and an associated one of the first circuits and configured to respond to the first output timing control signal produced from the associated one of the first circuits to drive the associated one of the first terminals in accordance with the first data produced from the associated one of the first memory blocks; and', 'a plurality of second buffers each coupled to an associated one of the second terminals and an associated one of the first circuits and configured to respond to the first output timing control signal produced from the associated one of the first circuits to drive the associated one of the second terminals;, 'a first semiconductor chip that comprises a plurality of first through-vias each penetrating the second semiconductor chip and having first and second ends;', 'a plurality of second through-vias each penetrating the second semiconductor chip and ...

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Номер записи: 16
03-04-2014 дата публикации

METHOD, DEVICE, SERVER, AND SYSTEM FOR CONFIGURING DAYLIGHT SAVING TIME

Номер: US20140092713A1
Автор: Wu Tiejun
Принадлежит: HUAWEI DEVICE CO., LTD.

The present invention discloses a method, a device, a server, and a system for configuring daylight saving time, belonging to the field of communications. The method includes: receiving, by a CPE, a message carrying a daylight saving time rule parameter; if a daylight saving time enable flag displays that daylight saving time is enabled, extracting, by the CPE, the daylight saving time rule parameter from the message; obtaining the current year of the CPE; and obtaining start time or end time of daylight saving time according to the current year and the daylight saving time rule parameter. The system includes a CPE and a server. The CPE includes a receiving module, an extracting module, a first obtaining module, and a second obtaining module. The server includes a generating module and a sending module. Through the present invention, daylight saving time can be configured in a single attempt and used permanently. 1. A method for configuring daylight saving time , comprising:receiving, by a customer premises equipment CPE, a message carrying a daylight saving time rule parameter;if a daylight saving time enable flag displays that daylight saving time is enabled, extracting, by the CPE, the daylight saving time rule parameter from the message;obtaining, by the CPE, the current year of the CPE; andobtaining, by the CPE, start time or end time of daylight saving time according to the current year and the daylight saving time rule parameter.2. The method according to claim 1 , wherein the daylight saving time rule parameter comprises: month m claim 1 , week w claim 1 , day d claim 1 , hour H claim 1 , minute M claim 1 , and second S; ormonth m, date D, hour H, minute M, and second S.3. The method according to claim 2 , further comprising:if no date complying with the daylight saving time rule parameter exists, obtaining a last day of month m of the current year, and combining the current year, the month m, the obtained last day, the extracted hour H, minute M, and second ...

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Номер записи: 17
03-04-2014 дата публикации

CLOCK CONTROL METHOD FOR PERFORMANCE THERMAL AND POWER MANAGEMENT SYSTEM

Номер: US20140095919A1
Автор: Gammie Gordon, Ko Uming, Mair Hugh Thomas, Wang Alice
Принадлежит: MEDIATEK SINGAPORE PTE. LTD.

A control method for a clock signal for a CPU contained in a CMOS circuit includes: when a load current for the CMOS circuit is enabled, generating a first clock signal; in a first period, selectively gating certain cycles of the first clock signal to generate a second clock signal which has a clock rate less than a clock rate of the first clock signal; and in a second period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal. The second clock signal is continuously input to the CMOS circuit during the first period and the second period. 1. A control method for a clock signal for a CPU contained in a CMOS circuit , the method comprising:when a load current for the CMOS circuit is enabled, generating a first clock signal;in a first time period, selectively gating cycles of the first clock signal to generate a second clock signal which has a clock rate less than a clock rate of the first clock signal; andin a second time period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal;wherein the second clock signal is continuously input to the CMOS circuit during the first time period and the second time period.2. The control method of claim 1 , wherein every other cycle of the first clock signal is gated off during the first period so that the second clock signal has a clock rate which is half that of the first clock signal.3. The control method of claim 2 , wherein a length of time of the first period is equal to a time period for allowing transients in the second clock signal to settle.4. The control method of claim 1 , wherein a length of time of the first period is a predetermined time according to the CMOS circuit.5. The control method of claim 1 , wherein the step of dithering in the gated cycles comprises:gradually reducing the number of gated cycles at a steady rate until no cycles are gated off;wherein the ...

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Номер записи: 18
05-01-2017 дата публикации

Electronic Timepiece and Movement

Номер: US20170003659A1
Автор: Nobuhiko Nakanishi
Принадлежит: Seiko Epson Corp

An electronic timepiece has a display device that displays display information, a drive mechanism that drives the display device, a crown that can perform a rotary operation, and a control device that corrects the display information displayed on the display device by the rotary operation of the crown. The control device has a single correction mode and a continuous correction mode which are selected by the rotary operation of the crown. In the single correction mode, a single correction signal is output to the drive mechanism so that the display device is corrected as much as a single correction quantity. In the continuous correction mode, a continuous correction signal is output to the drive mechanism so that the display device is corrected as much as a continuous correction quantity. The continuous correction quantity is set depending on types of the display information to be corrected in the continuous correction mode.

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Номер записи: 19
07-01-2016 дата публикации

APPARATUS, A METHOD AND MACHINE READABLE INSTRUCTIONS FOR QUERYING TIMERS

Номер: US20160004274A1
Автор: BAR RON-MICHAEL, GLICKMAN ERAN, MODAN AMIR DAVID
Принадлежит: Freescale Semiconductor, Inc.

An apparatus including: an input interface configured to enable user configuration of a future time window; and a report interface configured to produce a report relating to a first sub-set of a plurality of active timers that expire at programmed future points in time, wherein the first sub-set of the plurality of active timers expire during the user-configured future time window. 1. An apparatus comprising:an input interface configured to enable user configuration of a future time window; anda report interface configured to produce a report relating to a first sub-set of a plurality of active timers of the apparatus that expire at programmed future points in time, wherein the first sub-set of the plurality of active timers are predicted to expire during the user-configured future time window.2. An apparatus as claimed in claim 1 , further comprising timer circuitry and multiple-timer access circuitry configured to access the timer circuitry claim 1 , responsive to user configuration of a future time window claim 1 , to obtain information for at least the first sub-set of a plurality of active timers claim 1 , wherein the timer circuitry is configured to provide a plurality of active timers that expire at programmed future points in time.3. An apparatus as claimed in claim 2 , wherein the multiple-timer access circuitry is configured to access the timer circuitry autonomously claim 2 , responsive to user configuration of a future time window claim 2 , to obtain claim 2 , as an uninterrupted sequence claim 2 , information for at least each of the first sub-set of the plurality of active timers.4. An apparatus as claimed in claim 2 , further comprising processing circuitry configured to process the information obtained by the multiple-timer access circuitry from the timer circuitry to produce the report.5. An apparatus as claimed in claim 4 , wherein the processing circuitry is configured to filter the information obtained by the multiple-timer access circuitry from ...

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Номер записи: 20
21-01-2016 дата публикации

ELECTRONIC TIMEPIECE

Номер: US20160018789A1
Автор: HASEGAWA Kosuke
Принадлежит: CASIO COMPUTER CO., LTD.

An electronic timepiece including: a clocking unit; a storage unit; a setting selection unit which selects, as summer time implementation information, the summer time implementation rule or user setting that specifies whether to implement summer time; and a local time acquisition unit which acquires local time at a predetermined point, wherein the local time acquisition unit includes: a movement determination unit which determines, when the setting selection unit selects the user setting, whether a previous point and a new point belong to a predetermined range in which local time counted at the previous point is equal to local time counted at the new point; and a summer time implementation information switching unit which acquires local time on the basis of the summer time implementation rule when the previous point and the new point do not belong to the predetermined range. 1. An electronic timepiece comprising:a clocking unit which counts current date and time;a storage unit in which a summer time implementation rule set for each area is stored;a setting selection unit which selects, as summer time implementation information, the summer time implementation rule or user setting that specifies whether to implement summer time; anda local time acquisition unit which acquires local time at a predetermined point by using the summer time implementation information,wherein a movement determination unit which determines, when the setting selection unit selects the user setting, whether a previous point and a new point belong to a predetermined range in which local time counted at the previous point is equal to local time counted at the new point, the previous point being a position where local time is previously acquired, and the new point being a position where local time is to be newly acquired; and', 'a summer time implementation information switching unit which acquires local time on the basis of the summer time implementation rule when the previous point and the new ...

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Номер записи: 21
21-01-2021 дата публикации

INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING APPARATUS, AND METHOD OF CONTROLLING AN INFORMATION PROCESSING SYSTEM

Номер: US20210019186A1
Автор: NAKATA Yu, SAKAGUCHI Masanori, Tanaka Daiki
Принадлежит:

A data flow containing a distributed processing starting block, a distributed processing ending block, and a distributed processing target block which is a block described between the distributed processing starting block and the distributed processing ending block is edited by using a flow editor. A master apparatus forming a cluster transmits a message containing an execution instruction of the distributed processing target block to worker apparatuses forming the cluster when the distributed processing starting block has been reached at the time executing the data flow, and upon receipt of the message, each of the worker apparatuses executes the distributed processing target block and transmits a message containing an execution result of the distributed processing target block to the master apparatus, and upon receipt of the execution results from the worker apparatuses, the master apparatus executes a block of the data flow which follows the distributed processing ending block. 1. An information processing system which executes software based on a data flow edited by a flow editor , comprising:a plurality of information processing apparatuses which form a cluster for conducting distributed processing of the software, wherein a distributed processing starting block which is a block to start the distributed processing;', 'a distributed processing ending block which is a block to end the distributed processing; and', 'a distributed processing target block which is a block which is described between the distributed processing starting block and the distributed processing ending block,, 'the data flow containsa master apparatus which is one of the information processing apparatuses forming the cluster transmits a message containing an execution instruction of the distributed processing target block to a plurality of worker apparatuses which form the cluster when the distributed processing starting block has been reached at the time of executing the data flow,upon ...

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Номер записи: 22
28-01-2016 дата публикации

Calibration Unit for Calibrating an Oscillator, Oscillator Arrangement and Method for Calibrating an Oscillator

Номер: US20160026209A1
Автор: Burns Adam, Leme Carlos Azeredo, Toffolon Dino
Принадлежит:

Disclosed is a calibration unit for calibrating an oscillator of a device comprises a counting and comparing unit and a control circuit. The counting and comparing unit is configured to determine a number of periods of a clock signal lying between a starting instance and an ending instance. Therein, the clock signal is generated by the oscillator. The counting and comparing unit is further configured to determine a deviation of the number of periods from a reference number. The control circuit is configured to adjust the oscillator depending on the deviation. 1. An oscillator arrangement comprising an oscillator of a USB device and a calibration unit for calibrating the oscillator , the calibration unit comprising: to determine a number of periods of a clock signal, generated by the oscillator, between a starting instance and an ending instance, and', 'to determine a deviation of the number of periods from a reference number; and, 'a counting and comparing unit configured'}a control circuit configured to adjust the oscillator depending on the deviation.2. The oscillator arrangement according to claim 1 , whereinthe starting instance corresponds to a first point in time when the counting and comparing unit receives a first timing signal corresponding to a first start-of-frame (SOF) token from a USB host; andthe ending instance corresponds to a second point in time when the counting and comparing unit receives a second timing signal corresponding to a second SOF token from the USB host.3. The oscillator arrangement according to claim 1 , wherein the reference number is given by a ratio of a time period between the starting instance and the ending instance and a reference clock period.4. The oscillator arrangement according to claim 1 , wherein the control circuit is further configured to generate a lock indication signal indicating whether the deviation is below a threshold.5. The oscillator arrangement according to claim 1 , wherein the control circuit is configured ...

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Номер записи: 23
17-04-2014 дата публикации

ABNORMAL CLOCK RATE DETECTION IN IMAGING SENSOR ARRAYS

Номер: US20140108850A1
Автор: Boulanger Pierre, Goodland Jim, Hoelter Theodore R., Högasten Nicholas, Kurth Eric A., Nussmeier Mark, Sharp Barbara, Simolon Brian, Strandemar Katrin
Принадлежит: FLIR Systems, Inc.

Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select the current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value. 1. A device comprising:a counter adapted to receive a clock signal and adjust a count value in response to the clock signal;a ramp generator adapted to generate a ramp signal having a slope independent of the clock signal;a comparator adapted to receive a reference signal and the ramp signal, and select the current count value in response to the reference signal and the ramp signal; anda processor adapted to determine, based on the selected count value, if a frequency of the clock signal is within a specified range.2. The device of claim 1 , further comprising an imaging sensor array adapted to receive the clock signal claim 1 , wherein the imaging sensor array is adapted to provide images at a frame rate dependent on the clock frequency.3. The device of claim 2 , wherein the imaging sensor array comprises a plurality of infrared sensors.4. The device of claim 2 , wherein the processor is adapted to disable the imaging sensor array if the clock frequency is outside the specified range.5. The device of claim 1 , further ...

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Номер записи: 24
10-02-2022 дата публикации

TIME SYNCHRONIZATION SYSTEM, MASTER DEVICE, SLAVE DEVICE, AND PROGRAM

Номер: US20220045836A1
Автор: HIOKI Eitaro, Uchiyama Naoya
Принадлежит: Mitsubishi Electric Corporation

A time synchronization system includes a master and slave devices connected to each other via a data bus and a signal line dedicated to transmission of a fixed-period signal. The master device transmits the fixed-period signal through the signal line regularly at a transmission period, and transmits start time information indicating a transmission start time at which transmission of the fixed-period signal is started and transmission period information indicating the transmission period for the fixed-period signal through the data bus. The slave device counts a number of times the fixed-period signal is received and calculates, as a current time in the master device, a transmission time at which the master device transmits the fixed-period signal based on the number of times the fixed-period signal is received. The slave device corrects the time to the calculated current time in the master device. 1. A time synchronization system comprising:a master device; anda slave device,the master device and the slave device being connected to each other via a data communication line and a signal line dedicated to transmission of a fixed-period signal, a master timekeeper to measure a time,', 'a fixed-period signal transmitter to, regularly at a transmission period, generate the fixed-period signal and transmit the fixed-period signal to the slave device through the signal line,', 'a start time transmitter to transmit, to the slave device through the data communication line, start time information indicating a transmission start time at which transmission of the fixed-period signal is started,', 'and', 'a transmission period transmitter to transmit, to the slave device through the data communication line, the transmission period information indicating the transmission period for the fixed-period signal,, 'the master device including'} a slave timekeeper to measure a time,', 'a fixed-period signal receiver to receive the fixed-period signal from the master device through the ...

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Номер записи: 25
04-02-2016 дата публикации

Systems and Methods for Determining Absolute Time Corresponding to Relative Time-Stamped Events

Номер: US20160033990A1
Автор: Luciani Vincent P.
Принадлежит:

System and methods for transferring time-stamped event data and correcting the relative time associated with the time-stamped event to the correct “absolute” time, wherein “absolute” time is an official reference time. A time stamp relative to a predetermined event is obtained from a real time clock (RTC) that is unsynchronized to absolute time and associated with event data, as may be acquired by a data monitoring component. The relative time of the event data is correlated with “absolute” time to find a correction factor or time offset that defines the variation between the relative time and the absolute time. The time offset is applied to some or all of a plurality of event data sets transferred to other components in a utilization system to provide time corrected event data sets. 1. A system for determining absolute time corresponding to relative time-stamped events , comprising:a data collection device comprising an event monitoring component for obtaining data corresponding to a monitored event, a control component, a memory, a data communication port, and a real time clock (RTC), the RTC providing time signals that are unsynchronized to absolute time for association with data from the event monitoring component;the control component in the data collection device operative to receive data corresponding to a monitored event and associate a time stamp derived from the RTC with the monitored event data and store time-stamped monitored event data in the memory;a second device comprising a control component, a memory, a data communication port, and a second real time clock (RTC), the second RTC providing time signals for association with data received by the second device;the second device coupled for data communications to the data collection device via their respective data communication ports;the control component in the second device operative to receive time-stamped monitored event data from the data collection device;the control component in the second device ...

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Номер записи: 26
31-01-2019 дата публикации

ENERGY DEMAND CHARGE OFFSET SYSTEM

Номер: US20190033353A1
Автор: Andrew Arthur A., Naifeh Michael J., Quinn Derek R.
Принадлежит:

A system and method for offsetting peak demand for a customer of an electrical utility is disclosed. The system includes a source of stored electrical energy connected between an electrical service panel and a load. Demand spikes are detected by monitoring current flowing to the load, and when a demand spike is detected, the source of stored energy is connected to the load. 1. An electrical peak demand offset system , comprising:at least one electrical current monitor electrically connected between a service panel connection and an electrical load at an electrical utility customer;a source of stored electrical energy connectable to the electrical load by a switch;a programmable processor in electronic communication with the electrical current monitor and the switch.2. The system of claim 1 , wherein the source of stored electrical energy comprises a battery or a capacitor.3. The system of claim 2 , wherein the battery or capacitor is electrically connected between the service panel connection and the load.4. An electrical peak demand offset system claim 2 , connected between a service panel and an electrical load claim 2 , the system comprising:a pass-though electrical path between the service panel and the load including an inductor;a switch;a source of stored electrical energy selectably connectable to the electrical load by the switch;a power input electrically connected to the service panel;a power output electrically connected to the load;a microprocessor connected to the switch by a data communications path;a communications interface connected to the microprocessor by a data communications path;5. The system of claim 4 , wherein the source of stored electrical energy comprises a battery or a capacitor.6. A method of offsetting peak electrical demand by an electrical utility customer claim 4 , the method comprising:measuring current on an electrical connection between a load and an electrical utility;computing, on the basis of the current measurements, the ...

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Номер записи: 27
08-02-2018 дата публикации

DATA PROCESSING SYSTEM

Номер: US20180039557A1
Автор: Hata Hisashi
Принадлежит:

A method of performing a cooperative data processing, said method comprising performing a plurality of processes in each of a plurality of control modules capable of communicating with each other to perform the cooperative data processing, the plurality of processes includes a required application process of the cooperative data processing. 1. A method of performing a cooperative data processing , said method comprising performing a plurality of processes in each of a plurality of control modules capable of communicating with each other to perform the cooperative data processing , the plurality of processes comprising:a required application process of the cooperative data processing;a unit log generation process during which, at a test point designated by a program executed in the unit log generation process, the unit log generation process generates timestamps in accordance with log information and with time information derived from the timer and accumulates the timestamps together with attribute information about the test point to generate a unit log; anda time synchronization process in accordance with a program executed by the control modules, the time synchronization process being performed by the timer for time synchronization specifically for the cooperative data processing performed by the plurality of control modules, the time synchronization process synchronizing an overall time for the cooperative data processing by synchronizing time information derived from a timer in a low-level control module with time information derived from a timer in a high-level control module,wherein the time synchronization process comprises a process in which the low-level control module receives from the high-level control module information about the timer time of the high-level control module and corrects its local timer time in accordance with the received information about the time and with the information about its local timer time and other information prevailing when ...

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Номер записи: 28
07-02-2019 дата публикации

SYSTEM, METHOD, AND APPARATUS FOR SRIS MODE SELECTION FOR PCIE

Номер: US20190041898A1
Автор: Das Sharma Debendra, Froelich Daniel S., Harriman David J., Stalley Sean O.
Принадлежит:

Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration. 1. A method for operating a downstream port of an upstream component connected to one or more downstream components across a Peripheral Component Interconnect Express (PCIe)-compliant link , the method comprising:determining that the downstream port supports one or more Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode selection mechanisms;determining a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link;setting an SRIS mode in the downstream port; andtransmitting data across the link from the downstream port using the determined system clock configuration.2. The method of claim 1 , wherein setting the SRIS mode in the downstream port comprises setting the SRIS mode based claim 1 , at least in part claim 1 , on the determination of the system clock configuration.3. The method of claim 1 , further comprising communicating the SRIS mode to one or more upstream ports connected to the downstream port across the PCIe-compliant link.4. The method of claim 3 , wherein the one or more upstream ports comprise a pseudo port of a retimer.5. The method of claim 1 , wherein determining that the downstream port supports one or more SRIS mode selection mechanisms comprises determining that an SRIS mode selection mechanism bit is set in ...

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Номер записи: 29
01-05-2014 дата публикации

MEASUREMENT OF CLOCK SKEW BETWEEN TWO REMOTE HOSTS CONNECTED THROUGH COMPUTER NETWORKS

Номер: US20140122742A1
Автор: Rojas-Cessa Roberto, Salehin Khondaker M.
Принадлежит: NEW JERSEY INSTITUTE OF TECHNOLOGY

Technologies are generally described for measuring clock skew between two remote hosts connected through a computer network. According to some examples, pairs of probe packets, also referred to as a compound probe, may be transmitted over an end-to-end path in both directions (forward and reverse paths) to measure a gap value at the end nodes for clock skew estimation. Compound probes may arrive at the end nodes with a zero dispersion gap (no separation) and the gap values along the forward and reverse paths may be determined by a capacity of the links connected to the end nodes added to the clock speeds of the measuring nodes upon arriving at the end nodes. The link capacity is a constant network parameter. Thus, the ratio of the measured gap values may provide an estimate of clock speed discrepancy between the end nodes. 1. A method for estimating a clock skew between two remotely connected hosts , the method comprising:transmitting a train of compound probes comprising two or more packets from a source host to a destination host;determining a minimum intra-compound gap of the train of compound probes received at the destination host;transmitting another train of compound probes comprising two or more packets from the destination host to the source host;determining a minimum intra-compound gap of the other train of compound probes received at the source host;computing a difference between the minimum intra-compound gaps; andestimating the clock skew at the destination host based on a ratio of the computed difference and the minimum intra-compound gap of the other train of compound probes received at the source host.2. The method according to claim 1 , further comprising:selecting the packets in the train of compound probes of different sizes.3. The method according to claim 2 , further comprising:selecting the packet sizes such that a packet size of a first packet is larger than a packet size of a second packet in each compound probe.4. (canceled)5. The method ...

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Номер записи: 30
25-02-2016 дата публикации

DYNAMICALLY RECONFIGURING TIME ZONES IN REAL-TIME USING PLURAL TIME ZONE LIBRARIES

Номер: US20160054708A1
Автор: Clissold David N., Liu Su, Ow Michael, Tinnakul Teerasit
Принадлежит:

A method for dynamically reconfiguring time zones in real-time using plural time zone (TZ) libraries is provided. The method provides integrating a first time zone information data (TZID) version and a second TZID version into a TZ library in an operating system. A first configuration comprising the TZ library and the first TZID version is selected. Responsive to adjusting the first configuration to a second configuration comprising the TZ library and the second TZID version, the second configuration is used automatically without restarting the operating system and without restarting an application. 18-. (canceled)9. A computer program product for dynamically reconfiguring time zones in real-time using a plurality of time zone (TZ) libraries comprising:a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:integrating a first time zone information data (TZID) version and a second TZID version into a TZ library in an operating system;selecting a first configuration, wherein the first configuration includes the TZ library and the first TZID version; andresponsive to adjusting the first configuration to a second configuration, utilizing the second configuration, wherein the second configuration includes the TZ library and the second TZID version, and wherein the second configuration is utilized automatically without restarting the operating system or an application.10. The computer program product of claim 9 , wherein the TZ rules of reconfiguration include at least one of:at least one pre-defined environment variable;a list for prioritizing the loading of TZ libraries;a list of locations used by the operating system to locate and load the one or more TZ libraries and TZID versions; andlogic for selecting and reconfiguring the order of the TZ library and TZID version.11. The computer program product of claim 9 , further comprising:reviewing a first list of ...

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Номер записи: 31
25-02-2016 дата публикации

DYNAMICALLY RECONFIGURING TIME ZONES IN REAL-TIME USING PLURAL TIME ZONE LIBRARIES

Номер: US20160054709A1
Автор: Clissold David N., Liu Su, Ow Michael, Tinnakul Teerasit
Принадлежит:

A method for dynamically reconfiguring time zones in real-time using plural time zone (TZ) libraries is provided. The method provides integrating a first time zone information data (TZID) version and a second TZID version into a TZ library in an operating system. A first configuration comprising the TZ library and the first TZID version is selected. Responsive to adjusting the first configuration to a second configuration comprising the TZ library and the second TZID version, the second configuration is used automatically without restarting the operating system and without restarting an application. 1. A method for dynamically reconfiguring time zones in real-time using a plurality of time zone (TZ) libraries comprising:integrating a first time zone information data (TZID) version and a second TZID version into a TZ library in an operating system;selecting a first configuration, wherein the first configuration includes the TZ library and the first TZID version; andresponsive to adjusting the first configuration to a second configuration, utilizing the second configuration, wherein the second configuration includes the TZ library and the second TZID version, and wherein the second configuration is utilized automatically without restarting the operating system or an application.2. The method of claim 1 , wherein the selecting the first configuration is performed utilizing TZ rules of reconfiguration.3. The method of claim 2 , wherein the TZ rules of reconfiguration include at least one of:at least one pre-defined environment variable;a list for prioritizing the loading of TZ libraries;a list of locations used by the operating system to locate and load the one or more TZ libraries and TZID versions; andlogic for selecting and reconfiguring the order of the TZ library and TZID version.4. The method of claim 1 , further comprising:reviewing a first list of TZID versions from a TZ library;re-ordering the first list of TZID versions, based on user-defined input;creating a ...

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Номер записи: 32
08-05-2014 дата публикации

Application Memory Preservation for Dynamic Calibration of Memory Interfaces

Номер: US20140129870A1
Автор: Goplan Mahesh, LEE Jung
Принадлежит: UNIQUIFY, INCORPORATED

A calibrating memory interface circuit is described wherein prior to a calibration operation at least a portion of application information contained in a memory circuit is moved or copied to an alternate location to preserve that information. At the completion of the calibration operation, the information is restored to the same location of the memory circuit. Thus, the calibration operation can be performed from time to time during normal operation of a system containing the memory circuit. Non-limiting examples of calibration operations are described including operations where a capture clock for a memory read circuit is calibrated, and operations where CAS latency compensation is calibrated for a DDR memory interface. 1. A memory interface circuit that is calibrated from time to time in conjunction with functional operation of a memory circuit , comprising: 'one or more calibration controller circuits associated with said one or more memory controller circuits;', 'one or more memory controller circuits for controlling the memory interface circuit;'}wherein control settings for the one or more memory controller circuits are determined and set using said one or more calibration controller circuits according to a calibration operation performed from time to time; andwherein prior to commencing the calibration operation, a known data pattern for calibration is located in the memory circuit, and wherein if the known data pattern for calibration is not fully present in the memory circuit immediately prior to a calibration operation, at least a portion of said known data pattern for calibration is written to the memory circuit prior to the calibration operation; andwherein prior to writing said at least a portion of the known data pattern, at least a portion of functional application data located in the memory circuit is preserved by moving said at least a portion of functional application data to an alternate location.2. The memory interface circuit of wherein said ...

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Номер записи: 33
22-02-2018 дата публикации

DEVICE, METHOD AND SYSTEM FOR DETECTING AND RESOLVING TIME INFORMATION OF DIFFERENT ADMINISTRATIVE DOMAINS

Номер: US20180052485A1
Автор: Falk Rainer, Fischer Kai, Fries Steffen, Klasen Wolfgang
Принадлежит:

A device is provided for detecting time information of different administrative domains. The device includes a plurality of detection units, wherein each detection unit is assigned to one of the administrative domains and is configured to receive time information from a timer of the assigned administrative domains for synchronising with the assigned administrative domains, a storage device having a plurality of storage areas, and a plurality of control units, wherein each control unit is assigned exclusively to one of the detection units and the control units are configured to detect, synchronised with one another, a respective most recent item of the received time information of the respective assigned detection unit and to store the synchronously detected time information of the plurality of detection units together as synchronised data in one of the storage regions. 1. A device for detecting time information of different administrative domains comprising:a plurality of detection units, wherein each detection unit of the plurality of detection units is assigned to one of the administrative domains and is configured to receive time information from a timer of the assigned administrative domain for synchronizing with the assigned administrative domain;a storage device with a plurality of storage areas; anda plurality of control units wherein each control unit of the plurality of control units is assigned to precisely one detection unit of the plurality of detection units, the plurality of control units being configured to detect, synchronously with one another, a respective most recent item of received time information of the respective assigned detection unit and to store the synchronously detected time information of the plurality of detection units together as synchronization data in one of the plurality of storage areas.2. The device as claimed in claim 1 ,whereinthe plurality of control units are configured to detect, at a certain point in time of a reference ...

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Номер записи: 34
23-02-2017 дата публикации

MOVEMENT AND ELECTRONIC TIMEPIECE

Номер: US20170052511A1
Автор: IHASHI Tomohiro, MUGISHIMA Katsuya, Ogasawara Kenji, Sakai Satoshi
Принадлежит:

There is provided a movement including a center wheel & pinion that drives a minute hand, a second wheel & pinion that is arranged coaxially with a center axle of the center wheel & pinion, a first light emitting element that is arranged on one side in an axial direction of the center axle with respect to the center wheel & pinion and the second wheel & pinion, and a first light receiving element that is arranged on the other side in the axial direction of the center axle across the second wheel & pinion, and that detects light emitted from the first light emitting element. The center wheel & pinion has a first center wheel transmittable portion through which the light emitted from the first light emitting element is transmittable, and a second center wheel transmittable portion which is disposed on a rotation trajectory of the first center wheel transmittable portion and through which the light emitted from the first light emitting element is transmittable. The second wheel & pinion has a first second wheel transmittable portion which is disposed on the rotation trajectory of the first center wheel transmittable portion and the second center wheel transmittable portion when viewed in the axial direction of the center axle and through which the light emitted from the first light emitting element is transmittable. 1. A movement comprising:a first gear that is rotated by power of a first drive source so as to drive a first indicating hand;a second gear that is arranged coaxially with a center axle of the first gear, and that is rotated by power of a second drive source so as to drive a second indicating hand;a light emitting element that is arranged on one side in an axial direction of the center axle of the first gear, with respect to the first gear and the second gear; anda first light receiving element that is arranged on the other side in the axial direction across the first gear and the second gear, and that detects light emitted from the light emitting element, ...

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Номер записи: 35
25-02-2021 дата публикации

TIME SYNCHRONIZATION SYSTEM AND TIME SYNCHRONIZATION METHOD

Номер: US20210058223A1
Автор: Arai Kaoru, Hisashima Takaaki, Kurokawa Osamu, Matsumura Kazuyuki, Sakuma Hiroki, Sugiyama Ryuta, Tsuboi Shunichi
Принадлежит:

[Problem] To synchronize timings of transmitting and receiving a pulse signal (1 PPS signal) at a constant interval between communication apparatuses even in a case where an optical fiber connecting the communication apparatuses fluctuates in an optical characteristic and an optical fiber length. 1. A time synchronization system for transmitting and receiving a pulse signal at a constant interval at a synchronization timing between first and second communication apparatuses connected through a first optical fiber and a second optical fiber , which are two-core bidirectional , to synchronize time , the time synchronization system comprising:the first communication apparatus that includesa first transmitter configured to transmit a first pulse signal of a first wavelength and a second pulse signal of a second wavelength different from the first wavelength to the second communication apparatus through the first optical fiber, anda first receiver configured to receive a plurality of pulse signals including the first pulse signal and the second pulse signal transmitted from the second communication apparatus through the second optical fiber; andthe second communication apparatus that includesa second receiver configured to receive the first pulse signal and the second pulse signal from the first optical fiber, anda second transmitter configured to generate a third pulse signal of a wavelength identical to the second wavelength of the second pulse signal when receiving the first pulse signal, to simultaneously transmit the first pulse signal and the third pulse signal to the first communication apparatus through the second optical fiber, to generate a fourth pulse signal of a wavelength identical to the first wavelength of the first pulse signal when receiving the second pulse signal, and to simultaneously transmit the second pulse signal and the fourth pulse signal to the first communication apparatus through the second optical fiber,wherein the first communication ...

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Номер записи: 36
15-05-2014 дата публикации

GENERATION AND DISTRIBUTION OF A SYNCHRONIZED TIME SOURCE

Номер: US20140136877A1
Автор: Engler Eberhard, GERWIG Guenter, Hinrichs Willm, Ramanandray Barinjato
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

An apparatus comprising a first oscillator, a time source controller coupled with the first oscillator and corrected time interval counters coupled with the time source controller. The first oscillator is configured to transmit a raw time interval pulse at regular or near regular intervals. The time source controller is configured to receive an indication of time that indicates at least one of the current day and the current time and to determine that the raw interval pulse should be adjusted based on the indication of time. The time source controller is also configured to generate a steered time interval pulse based, at least partly, on the raw time interval pulse and the indication of time, and distribute the steered time interval pulse to a plurality of hardware components. The time interval counters are configured to host a time value based on the output from the time source controller. 1. A method comprising:receiving an indication of time, wherein the indication indicates at least one of the current day and the current time;determining that a raw time interval pulse transmitted by a first oscillator of a computing system should be adjusted based, at least partly, on the indication of time;responsive to said determining that the raw time interval pulse transmitted by the first oscillator of the computing system should be adjusted, generating a steered time interval pulse based, at least partly, on the raw time interval pulse and the indication of time; anddistributing the steered time interval pulse to a plurality of hardware components of the computing system that use the output for timestamps.2. The method of claim 1 , wherein the indication of time is received from a source external to the computing system.3. The method of claim 1 , wherein the indication of time further comprises at least one of a pulse per second value and a steering rate.4. The method of claim 1 , wherein said generating the steered time interval pulse based claim 1 , at least partly ...

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Номер записи: 37
05-03-2015 дата публикации

Crossing Pipelined Data between Circuitry in Different Clock Domains

Номер: US20150067384A1
Автор: Rozario Ranjit J.
Принадлежит:

An integrated circuit implements a multistage processing pipeline, where control is passed in the pipeline with data to be processed according to the control. At least some of the different pipeline stages can be implemented by different circuits, being clocked at different frequencies. These frequencies may change dynamically during operation of the integrated circuit. Control and data to be processed according to such control can be offset from each other in the pipeline; e.g., control can precede data by a pre-set number of clock events. To cross a clock domain, control and data can be temporarily stored in respective FIFOs. Reading of control by the destination domain is delayed by a delay amount determined so that reading of control and data can be offset from each other by a minimum number of clock events of the destination domain clock, and control is read before data is available for reading. 1. A method of crossing pipelined control and data between clock domains in a multi-clock domain integrated circuit , comprising: storing an element of control information in a control queue,', 'storing an element of data in a data queue, after a pipeline delay characterized by a pre-set number of clock events of the first clock;, 'by a first circuit, clocked by a first clock,'}initializing a counter to an initial value;updating the counter; andreading the element of control information from the control queue by a second circuit, clocked by a second clock, operating at a different frequency than the first clock, responsive to the counter reaching a pre-determined value, and then reading the element of data from the data queue after the pre-set number of clock events have occurred for the second clock.2. The method of crossing pipelined control and data between clock domains in a multi-clock domain integrated circuit of claim 1 , wherein the counter is updated based on the first clock and the initial value to which the counter is initialized is determined based on a ...

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Номер записи: 38
02-03-2017 дата публикации

Time Distribution Switch

Номер: US20170063482A1
Автор: Achanta Shankar V., Loehner Henry, Whitehead David E.
Принадлежит:

Systems and methods for detecting the failure of a precision time source using an independent time source are disclosed. Additionally, detecting the failure of a GNSS based precision time source based on a calculated location of a GNSS receiver is disclosed. Moreover, the system may be further configured to distribute a time derived from the precision time source as a precision time reference to time dependent devices. In the event of a failure of the precision time source, the system may be configured to distribute a time derived from a second precision time source as the precision time signal during a holdover period. 120-. (canceled)21. A time distribution device comprising:a receiver configured to receive periodic time signals from each of first and second external time sources;an output configured to provide a precision time signal to an intelligent electronic device (IED), wherein the precision time signal is determined from a best available time source of the first and second external time sources; determine, for the first external time source, a first variation of duration between the periodic time signals from the first external time source, the first variation in duration based on a local oscillator;', 'determine, for the second external time source, a second variation of duration between the periodic time signals from the second external time source, the second variation in duration based on the local oscillator;', 'compare the first variation and the second variation; and', 'select the best available time source as one of the first time source and the second time source with the lowest variation., 'a time quality module configured to22. The time distribution device of claim 21 , wherein the local oscillator comprises an internal oscillator.23. The time distribution device of claim 21 , wherein the time quality module is further configured to:detect a failure of the selected precision time source; anddetermine a backup precision time source for use as the ...

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Номер записи: 39
22-05-2014 дата публикации

Timing Optimized Implementation of Algorithm to Reduce Switching Rate on High Throughput Wide Buses

Номер: US20140143586A1
Автор: Cohen Baruch, DALUMI EFRAIM, Lerner Eitan
Принадлежит: SANDISK TECHNOLOGIES INC.

A dynamic bus inversion (DBI) circuit disposed between a transmitter and a receiver for generating an inversion control signal that is communicated to the receiver and used to perform inversion control on data communicated along a data path between the transmitter and the receiver includes a delay data setup circuit to receive the data from the transmitter. A majority vote function circuit is used to perform majority voting for consecutive bits of data output by the delay data setup circuit to generate majority data output. An inversion control circuit receives the majority data output, retrieves feedback data from a preceding inversion control output and interprets the two data to generate inversion control signal, which is used to perform inversion control on data along the data path before being communicated to the receiver. The inversion control signal is used by the receiver to interpret the data received from the data path. 1. A dynamic bus inversion (DBI) circuit for coupling between a transmitter and a receiver , the DBI circuit configured to generate an inversion control signal that is communicated to the receiver and used to perform inversion control on data communicated along a data path between the transmitter and the receiver , the circuit comprising:a delay data setup circuit configured to receive the data from the transmitter;a majority vote function circuit for performing majority voting for consecutive bits of the data to generate majority data output, wherein the consecutive bits of the data include bits obtained from an output of the delay data setup circuit; andan inversion control circuit configured to receive the majority data output from the majority vote function and retrieve feedback data from a preceding inversion control output of the inversion control circuit, the inversion control circuit acting to interpret the majority data output and the feedback data to generate an inversion control signal, the inversion control signal performing the ...

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Номер записи: 40
27-02-2020 дата публикации

TIME SOURCE RANKING SYSTEM FOR AN AUTONOMOUS DRIVING VEHICLE

Номер: US20200064836A1
Автор: KWAN Oh, YOU Xiangtao, ZHANG Manjiang
Принадлежит:

In one embodiment, a system receives a number of times from a number of time sources including sensors and real-time clocks (RTCs), wherein the sensors are in communication with the ADV and the sensors include at least a GPS sensor, and where the RTCs include at least a central processing unit real-time clock (CPU-RTC). The system generating a difference histogram based on a time for each of the time sources for a difference between a time of the GPS sensor and a time for each of the other sensors and RTCs. The system ranks the sensors and RTCs based on the difference histogram. The system selects a time source from one of the sensors or RTCs with a least difference in time with respect to the GPS sensor. The system generates a timestamp based on the selected time source to timestamp sensor data for a sensor unit of the ADV. 1. A method to rank time sources for an autonomous driving vehicle (ADV) , the method comprising:receiving a plurality of times from a plurality of time sources including sensors and real-time clocks (RTCs), wherein the sensors are in communication with the ADV and the sensors include at least a global positioning system (GPS) sensor, and wherein the RTCs include at least a central processing unit real-time clock (CPU-RTC);generating a difference histogram based on a time for each of the time sources for a difference between a time of the GPS sensor and a time for each of the other sensors and RTCs;ranking the sensors and RTCs based on their respective difference histograms;selecting a time source from one of the sensors or RTCs with a least difference in time with respect to the GPS sensor; andgenerating a timestamp based on the selected time source to timestamp sensor data for a sensor unit of the ADV.2. The method of claim 1 , wherein a difference histogram includes an average difference histogram comprising an average time difference distribution for the GPS sensors and each of the other sensors and RTCs.3. The method of claim 1 , further ...

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Номер записи: 41
16-03-2017 дата публикации

ANALOG ELECTRONIC TIMEPIECE AND HAND DRIVE CONTROL DEVICE

Номер: US20170075313A1
Автор: HASEGAWA Kosuke
Принадлежит: CASIO COMPUTER CO., LTD.

An analog electronic timepiece, including: a hand which is provided to be rotatable; and a processor which makes the hand perform at least one of an acceleration operation and a deceleration operation as a speed change operation when the hand is made to perform a fast forward movement, the acceleration operation being an operation of gradually increasing a fast forward speed of the hand from a stopped state when the fast forward movement is started, and the deceleration operation being an operation of gradually decreasing the fast forward speed until the hand comes into the stopped state when the fast forward movement is ended. 1. An analog electronic timepiece , comprising:a hand which is provided to be rotatable; anda processor which makes the hand perform at least one of an acceleration operation and a deceleration operation as a speed change operation when the hand is made to perform a fast forward movement, the acceleration operation being an operation of gradually increasing a fast forward speed of the hand from a stopped state when the fast forward movement is started, and the deceleration operation being an operation of gradually decreasing the fast forward speed until the hand comes into the stopped state when the fast forward movement is ended.2. The analog electronic timepiece according to claim 1 , wherein claim 1 , when a target movement amount of the hand in the fast forward movement is determined claim 1 , the processor sets a speed change start movement amount and a speed change end movement amount in the fast forward movement for the target movement amount on the basis of the target movement amount claim 1 , the speed change start movement amount being a movement amount of the hand at a timing when the speed change operation is started claim 1 , and the speed change end movement amount being a movement amount of the hand at a timing when the speed change operation is ended.3. The analog electronic timepiece according to claim 1 , wherein claim 1 , ...

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Номер записи: 42
24-03-2016 дата публикации

SYNCHRONIZATION OF DOMAIN COUNTERS

Номер: US20160085263A1
Автор: Feit Itai, Kuzi Tal, LEVY ORI, NATHAN OFER J., Shulman Nadav
Принадлежит:

In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed. 1. A processor comprising:a master counter to store a time stamp count for the processor;a plurality of cores, each core including a core counter to store a time stamp count for the core; and obtain a value of the master counter;', 'initiate a first core counter using the value of the master counter, wherein the first core counter is included in the first core;', 'compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and', 'in response to a determination that the synchronization digit of the first core counter does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal., 'synchronization logic to, in response to a de-synchronization event in a first core of the plurality of cores2. The processor of claim 1 , wherein the synchronization logic is to:in response to a determination that an edge of the synchronization digit of the first core counter does not match an edge of the synchronization signal, set the ...

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Номер записи: 43
23-03-2017 дата публикации

ELECTRONIC TIMEPIECE

Номер: US20170082980A1
Автор: MIYAKE Takeshi, MOROHOSHI Hiroshi, OMURA Tatsuyoshi
Принадлежит: CASIO COMPUTER CO., LTD.

An electronic timepiece includes a turnable hand and a processor that controls a turn of the hand. When the processor performs a rapid shift of the hand to a set target position, the processor performs a control of a damping of reciprocation of the hand in which the hand performs a predetermined reciprocation about the target position as a reference position and gradually decreases an amplitude of the reciprocation thereof during the rapid shift. 1. An electronic timepiece comprising:a turnable hand; anda processor that controls a turn of the hand,wherein, when the processor performs a rapid shift of the hand to a set target position, the processor performs a control of a damping of reciprocation of the hand in which the hand performs a predetermined reciprocation about the target position as a reference position and gradually decreases an amplitude of the reciprocation thereof during the rapid shift.2. The electronic timepiece according to claim 1 , wherein the processor continues to perform the control of the damping of the reciprocation of the hand after the hand reaches the target position.3. The electronic timepiece according to claim 2 , whereinthe predetermined reciprocation includes bouncing of the hand in which a direction of the hand reaching the target position from a predetermined incident direction is inverted at the target position and the hand is returned in an opposite direction by a predetermined distance, andthe processor performs the control of the damping of the reciprocation by repeating the bouncing while decreasing the predetermined distance.4. The electronic timepiece according to claim 3 , wherein the predetermined incident direction is defined to be identical to a direction of the rapid shift of the hand.5. The electronic timepiece according to claim 2 , whereinthe predetermined reciprocation includes oscillation about the target position at a predetermined amplitude, andthe processor performs the control of the damping of the reciprocation ...

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Номер записи: 44
02-04-2015 дата публикации

INTEGRATED CIRCUIT COMPRISING AN IO BUFFER DRIVER AND METHOD THEREFOR

Номер: US20150095525A1
Автор: Kuzmin Dan, Priel Michael, Sofer Sergey
Принадлежит: Freescale Semiconductor, Inc.

An integrated circuit for bias stress condition removal comprising at least one input/output (IO) buffer driver circuit comprising at least one input signal is described. A primary buffer driver stage receives the at least one input signal and providing an output signal in a first time period; and a secondary buffer driver stage receives the at least one input signal and providing an output signal in a second time period. The primary buffer driver stage and the secondary buffer driver stage cooperate and an operational mode of the primary buffer driver stage and an operational mode of the secondary buffer driver stage is varied to produce a varying output signal. 1. An integrated circuit for bias stress condition removal comprising at least one input/output (IO) buffer driver circuit comprising:at least one input signal;a primary buffer driver stage for receiving the at least one input signal and providing an output signal in a first time period; anda secondary buffer driver stage for receiving the at least one input signal and providing an output signal in a second time period,wherein the primary buffer driver stage and the secondary buffer driver stage cooperate and an operational mode of the primary buffer driver stage and an operational mode of the secondary buffer driver stage is varied to produce a variable output signal.2. The integrated circuit of wherein the first time period is different to the second time period.3. The integrated circuit of wherein the first time period overlaps the second time period.4. The integrated circuit of further comprising a processor module operably coupled to a timer circuit arranged to ensure that the first time period is different to the second time period.5. The integrated circuit of wherein the primary buffer driver stage is connected in parallel to the secondary buffer driver stage.6. The integrated circuit of wherein the secondary buffer driver stage is configured to maintain at an output of the IO buffer driver circuit a ...

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Номер записи: 45
19-06-2014 дата публикации

CLOCK RECOVERY USING REMOTE ARRIVAL TIMESTAMPS

Номер: US20140173136A1
Автор: Hazelet Keith
Принадлежит:

Methods and systems may provide for a sink module that receives packets from a source module, wherein each of the packets has a source timestamp corresponding to a source module packet arrival time. A reference timestamp may be associated with the source timestamp of the most recent packet having a program clock reference. A sink counter may be synchronized to a broadcaster transmit counter based on a current source timestamp and the reference timestamp. The sink counter and the source counter may be driven by asynchronous clocks, wherein the current source timestamp may be inferred based on a current value of the source counter. The packets may include video data and/or audio data. The sink counter may be synchronized by adjusting the frequency of a source clock and/or adjusting the sink counter. 1. A system comprising:a broadcast head-end; a source input to receive a plurality of packets from the broadcast head-end;', 'a source counter incremented by a source clock; and', 'a timestamper to add a source timestamp to each of a plurality of packets based on the source counter; and, 'a source module including a sink input to receive the plurality of packets from the source module;', 'a reference timestamp module to associate as a reference timestamp, the source timestamp of the most recent packet in the plurality of packets having a program clock reference;', 'a sink counter incremented by a sink clock; and', 'a synchronization module to synchronize the sink counter to a broadcaster transmit counter using a current source timestamp and the reference timestamp., 'a sink module including2. The system according to claim 1 , wherein the source module is a playback module.3. The system according to claim 1 , wherein the source module is a receiver module.4. The system according to claim 1 , wherein the source module and sink module are co-located.5. The system according to claim 1 , wherein the plurality of packets include one or more of video data and audio data.6. An ...

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Номер записи: 46
01-04-2021 дата публикации

CLOCK DATA RECOVERY CIRCUIT

Номер: US20210096592A1
Автор: Evans David Wayne, Hanschke Michael Ryan, Pandey Pankaj, Pham Joseph
Принадлежит:

A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration. 1. A clock data recovery circuit , comprising:a signal input terminal;a recovered data output terminal; a data input terminal coupled to the signal input terminal; and', 'a deglitched data output terminal;, 'a deglitch filter circuit including an enable terminal coupled the deglitched data output terminal of the deglitch filter circuit;', 'a bit output terminal; and', 'a reset terminal;, 'a timer circuit including an input terminal coupled to the deglitched data output terminal of the deglitch filter circuit; and', 'a pulse output terminal coupled to the reset terminal of the timer circuit; and, 'a delayed pulse circuit including a data input coupled to the bit output terminal of the timer circuit;', 'a clock input coupled to the deglitched data output terminal of the deglitch filter circuit; and', 'an output coupled to the recovered data output terminal., 'a flip-flop including2. The clock data recovery circuit of claim 1 , wherein the deglitch filter circuit includes: an input terminal coupled to the data input terminal; and', 'an output terminal;, 'a falling edge deglitch filter including'} an input terminal coupled to the data input terminal; and', 'an output terminal; and, 'a rising edge deglitch filter including'} a reset input coupled to the output of the falling edge deglitch filter;', 'a set input coupled to the output of the rising edge deglitch filter; and', 'an output coupled to the deglitched data output terminal., 'a latch circuit including3. ...

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Номер записи: 47
12-05-2022 дата публикации

ZERO-OFFSET PHASE DETECTOR APPARATUS AND METHOD

Номер: US20220149848A1
Автор: Chou Chun-Ju, Fredenburg Jeffrey Alan, Mu Yuxiang
Принадлежит:

A phase detection circuit includes a first phase detection path having a first input to receive a first signal, and a second input to receive a second signal. Asynchronous transition detection circuitry detects an early/late relationship between the first signal and the second signal when at least one of the first signal and the second signal transitions from a first state to a second state. Output circuitry generates a control signal with a value based on the early/late relationship. 1. A phase detection circuit , comprising: a first input to receive a first signal, and a second input to receive a second signal;', 'asynchronous transition detection circuitry to detect an early/late relationship between the first signal and the second signal solely when the first signal transitions from a first state to a second state irrespective of how many times the second signal transitions; and', 'output circuitry to generate a control signal with a value based on the early/late relationship., 'a first phase detection path including'}2. The phase detection circuit of claim 1 , further comprising:capture circuitry coupled to the asynchronous transition detection circuitry to capture respective states of the first and second signals corresponding to the detected early/late relationship.3. The phase detection circuit of claim 2 , wherein:the capture circuitry comprises symmetric latch circuitry.4. The phase detection circuit of claim 1 , wherein:the control signal is fed to a delay circuit; andthe second signal is delayed by the delay circuit in response to the control signal.5. The phase detection circuit of claim 1 , further comprising:a second phase detection path comprising a flip-flop having a timing input to receive the first signal, a data input to receive the second signal, and an output to indicate state information between the first signal and the second signal; anda selector to select between the first phase detection path and the second detection path for detecting the ...

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Номер записи: 48
19-04-2018 дата публикации

METHOD AND SYSTEM FOR HIGH PRECISION TIME SYNCHRONIZATION

Номер: US20180107626A1
Автор: Shao Wesley, SURABHI VIVEK
Принадлежит:

In one embodiment, a dedicated time processing device inserted into a peripheral bus coupling or embedded with at least some of the rest of system components (e.g., processor, memory) of a data processing system to synchronize a system clock of the data processing system. The peripheral bus can be a Peripheral Component Interface (PCI) bus, a PCI Express (PCIe) link, a PCI extended (PCI-X) bus, or the like. The time processing device receives high precision time from a high precision time source, such as global positioning system (GPS) time source. The time processing device decodes and processes the received time and stores the time in an internal time register. The time processing device further includes an interface to allow an external component (e.g., a processor) to retrieve with low latency the time stored in the time register for the purpose of synchronizing the system clock. 1. A data processing system , comprising:a processor;a Peripheral Component Interface Express (PCIe) link; and 'receive time data representing date and time from a time data source, and store the time data in the time register,', 'a time processing device coupled to the processor via the PCIe link, the time processing device including time processing logic and a time register, wherein the time processing logic is to'}wherein the processor retrieves the time data from the time register via a single read instruction over the PCIe bus and updates a system clock of the data processing system based on the time data.2. The system of claim 1 , wherein the time processing device comprises:a first input to receive a first signal from the time data source, the first signal indicating that an update of the time data is available from the time data source; anda second input to receive a message having the updated time data from the time data source.3. The system of claim 2 , wherein the first signal comprises a pulse-per-second (PPS) signal claim 2 , and wherein the message is a GPRMC compatible ...

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Номер записи: 49
03-05-2018 дата публикации

Information processing device

Номер: US20180121294A1
Автор: Kengo IBE
Принадлежит: Mitsubishi Electric Corp

An information processing device including a recording module to record a program having cleared a watchdog timer; a determination module to refer, when the watchdog timer expires, to the recording module to determine an application to be executed from among a plurality of applications, and to determine an operating system to be executed from among a plurality of operating systems; an execution module to execute the operating system determined by the determination module; and a communication module to notify the operating system to be executed of the application to be executed.

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Номер записи: 50
27-05-2021 дата публикации

WATCH CORRECTOR AND WATCH MIDDLE

Номер: US20210157268A1
Автор: Avril Hervé, MARCOS Ricardo
Принадлежит: Meco SA

A watch corrector () including at least one case () and at least one mobile element (). In order to avoid a movement according to a degree of freedom, the at least one mobile element () is inserted by force, preferably, the at least one mobile element () includes at least one second immobilisation member () configured to immobilise the at least one mobile element () in the at least one case (), and the at least one case () is inserted by force, preferably, the at least one case () includes at least one first immobilisation member () being configured to immobilise the at least one case () in the watch middle (). 1100200200100. A watch corrector () configured to be inserted in a watch middle (); said watch middle () includes a primary contour , in particular of a left-hand shape , preferably of a left-hand curve; said watch corrector () comprising at least one:{'b': 110', '110', '111', '200', '111', '200', '111', '200', '110', '200, 'at least one case (); said at least one case () comprises at least one first surface () and being configured to be inserted, preferably by force, in said watch middle (); said at least one first surface () representing a first portion of said primary contour, in particular of a left-hand shape, preferably of a left-hand curve and being configured to follow said primary contour, in particular of a left-hand shape, preferably of a left-hand curve of said watch middle (), preferably, said at least one first surface () being configured to be combined with said primary contour, in particular of a left-hand shape, preferably of a left-hand curve of said watch middle () when said at least one case () is inserted in said middle of said watch ();'}{'b': 120', '120', '110', '110', '121', '200', '111', '110', '121', '200', '111', '110', '110', '200, 'at least one mobile element (); said at least one mobile element () being configured to be inserted, preferably by force, in said at least one case (), preferably to be mobile in said at least one case ...

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Номер записи: 51
14-05-2015 дата публикации

INFORMATION PROCESSING APPARATUS CAPABLE OF CORRECTING TIME-OF-DAY MANAGEMENT FUNCTION, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM

Номер: US20150135000A1
Автор: Kimura Tomohiro
Принадлежит:

An information processing apparatus that is capable of correcting a time-of-day management function in the information processing apparatus even in an environment where the time of day cannot be properly measured in the information processing apparatus in a power-saving mode. A first time of day is obtained from an external apparatus on a network. A second time of day is identified based on the number of input CPU clocks per prescribed time period. The number of input CPU clocks per prescribed time period is corrected based on the first time of day and the second time of day. 1. An information processing apparatus comprising:an obtaining unit configured to obtain a first time of day from an external apparatus on a network;an identifying unit configured to identify a second time of day based on the number of input CPU clocks per prescribed time period; anda correction unit configured to correct the number of input CPU clocks per prescribed time period based on the first time of day and the second time of day.2. The information processing apparatus according to claim 1 , wherein said correction unit corrects the number of input CPU clocks per prescribed time period based on a difference between the first time of day and the second time of day.3. The information processing apparatus according to claim 1 , wherein said obtaining unit obtains the first time of day using SNTP (simple network time protocol).4. The information processing apparatus according to claim 1 , wherein the prescribed time period corresponds to an interval at which said correction unit corrects the number of input CPU clocks.5. A control method for an information processing apparatus comprising:an obtaining step of obtaining a first time of day from an external apparatus on a network;an identifying step of identifying a second time of day based on the number of input CPU clocks per prescribed time period; anda correction step of correcting the number of input CPU clocks per prescribed time period ...

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Номер записи: 52
07-08-2014 дата публикации

GESTURE-BASED TIME INPUT

Номер: US20140219066A1
Автор: Sadilek Daniel
Принадлежит: GOOGLE INC.

A computing device is described that outputs for display, a graphical user interface comprising a clock having regions associated with a first set of time increments. Responsive to receiving an indication of an input at a portion of a presence-sensitive input device corresponding to a location of a display device at which one of the regions of the clock is displayed, the computing device determines one of the first set of time increments. The computing device outputs for display, and proximate to the location, a second set of time increments. The computing device determines a time based on the determined one of the first set of time increments and a selected one of the second time increments. 1. A method comprising:outputting, by a computing device and for display, a graphical user interface comprising a clock having regions associated with a first set of time increments;responsive to receiving an indication of an input at a portion of a presence-sensitive input device corresponding to a location of a display device at which one of the regions of the clock is displayed, determining, by the computing device, one of the first set of time increments and outputting, for display and proximate to the location, a second set of time increments; anddetermining, by the computing device, a time based on the determined one of the first set of time increments and a selected one of the second time increments.2. The method of claim 1 , wherein the second set of time increments is of finer-grain time increments than the first set of time increments.3. The method of claim 1 , wherein the first set of time increments comprise at least one of one day increments of time claim 1 , one hour increments of time claim 1 , one half hour increments of time claim 1 , one minute increments of time claim 1 , and one second increments of time.4. The method of claim 1 , where each increment in the second set of time increments comprises a fractional value of each increment in the first set of time ...

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Номер записи: 53
07-08-2014 дата публикации

ANALOG ELECTRONIC TIMEPIECE

Номер: US20140219068A1
Автор: KYOU Kazuho
Принадлежит: CASIO COMPUTER CO., LTD.

An analog electronic timepiece, including: a magnetic field measurement unit; a time counting unit; a plurality of hands which are arranged so as to rotate freely; a hand control unit which controls rotation of the plurality of hands; and a timing control unit which executes the rotation of the hands by the hand control unit and measurement of a magnetic field by the magnetic field measurement unit so that periods of time do not overlap each other. 1. An analog electronic timepiece , comprising:a magnetic field measurement unit;a time counting unit;a plurality of hands which are arranged so as to rotate freely;a hand control unit which controls rotation of the plurality of hands; anda timing control unit which executes the rotation of the hands by the hand control unit and measurement of a magnetic field by the magnetic field measurement unit so that periods of time do not overlap each other,whereinat least one hand of the plurality of hands is independent drive hand(s) which is rotatable independently from other hand(s) by the hand control unit,the hand control unit makes a part or all of the independent drive hand(s) indicate a predetermined direction based on measurement data by the magnetic field measurement unit and makes other hand(s) among the plurality of hands as time hand(s) indicate a current time at a predetermined time interval, the current time being counted by the time counting unit,when the current time becomes a timing of a movement operation of the time hand(s) during the measurement of the magnetic field, in a case where the time hand(s) includes a hand for which the predetermined time interval is less than a predetermined setting time, the timing control unit interrupts the measurement of the magnetic field and performs the movement operation of the time hand(s), andin a case where the time hand(s) does not include the hand for which the predetermined time interval is less than the predetermined setting time, the movement operation of the time ...

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Номер записи: 54
09-05-2019 дата публикации

TOOL FOR ACTUATING A CORRECTOR FITTED IN A SMALL PORTABLE OBJECT SUCH AS A TIMEPIECE

Номер: US20190137938A1
Автор: GOLAY Patrice, Riedo Christophe, ZAUGG Alain
Принадлежит: Montres Breguet S.A.

A tool for actuating a corrector push-button fitted in a small portable object, wherein this actuation tool includes a body which extends between a rear end which defines a gripping zone of the actuation tool and a front end which defines an actuation zone of the actuation tool, at least the front end of the actuation tool being magnetised. 1. A tool arranged to actuate a corrector push-button fitted in a small portable object , wherein this actuation tool comprises a body which extends between a rear end which defines a gripping zone of the actuation tool and a front end which defines an actuation zone of the actuation tool , wherein at least the front end of the actuation tool is magnetised , wherein the portable object comprises a middle inside which the corrector push-button is arranged , wherein at least one component of the corrector push-button or a zone of the middle immediately surrounding the corrector push-button is made of a magnetic material such as a ferromagnetic material , such that , when the actuation tool is moved towards the portable object , the actuation tool will come spontaneously into contact with the corrector push-button under the effect of the magnetic attraction force exerted thereon by the corrector push-button or the at least one zone of the middle.2. The actuation tool according to claim 1 , wherein it comprises a bar magnet arranged in the front end thereof.3. The actuation tool according to claim 1 , wherein the body of the actuation tool is made of a magnetic material.4. A small portable object such as a timepiece claim 1 , wherein this portable object comprises a middle in an opening whereof is arranged a corrector push-button claim 1 , wherein at least one component of the corrector push-button or at least one zone of the middle immediately surrounding the corrector push-button is made of a magnetic material such as a ferromagnetic material claim 1 , wherein this corrector push-button is arranged to be actuated by means of an ...

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Номер записи: 55
26-05-2016 дата публикации

METHOD AND APPARATUS FOR DATA TRANSFER TO THE CYCLIC TASKS IN A DISTRIBUTED REAL-TIME SYSTEM AT THE CORRECT TIME

Номер: US20160147568A1
Автор: GLüCK Martin, Kopetz Hermann, Poledna Stefan
Принадлежит:

The invention relates to a method for the time-correct data transfer between cyclic tasks in a distributed real-time system, which real-time system comprises a real-time communication system and a multiplicity of computer nodes, wherein a local real-time clock in each computer node is synchronised with the global time, wherein all periodic trigger signals zfor the start of a new cycle i are derived in each computer node simultaneously from the advance of the global time, wherein these periodic trigger signals start the tasks, and wherein a task reads the output data of the other tasks from local input memory areas, to which the real-time communication system writes, and wherein a task writes the result data of the current cycle to a local output memory area, which is associated with the communications system, at an a priori determined individual production instant zbefore the end of a cycle, and wherein the schedules for the time-controlled communication system are configured such that the result data of a task present in the local output memory area is transported to the local input memory areas of the tasks requiring the data during the time interval , so that at the start of the following cycle this result data is available in the local input memory areas of the tasks that require this result data. 1. A method for the time-correct data transfer between cyclic tasks in a distributed real-time system , which real-time system comprises a real-time communication system and a multiplicity of computer nodes , wherein a local real-time clock in each computer node is synchronised with the global time , characterised in that all periodic trigger signals zfor the start of a new cycle i are derived in each computer node simultaneously from the advance of the global time , wherein these periodic trigger signals start the tasks , and wherein a task reads the output data of the other tasks from local input memory areas , to which the real-time communication system writes ...

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Номер записи: 56
02-06-2016 дата публикации

Time Synchronization System

Номер: US20160154420A1
Автор: HAGIHARA Kazunari
Принадлежит:

A control device includes a preset time determinator for determining a preset time to be set to a first real-time clock of a terminal device based on a second real-time clock. The terminal device includes a latency time timer for clocking a lapse of a latency time which is a period of time from the terminal device acquiring the preset time until the preset time being set to the first real-time clock and is calculated in a clocking accuracy having the number of effective figures greater than that of the first real-time clock, and a time setter for setting the preset time to the first real-time clock when the latency time is lapsed. 1. A time synchronization system , comprising:one or more terminal devices, each having a first real-time clock; anda control device having a second real-time clock of which the number of effective figures per clocking is greater then that of the first real-time clock,wherein the control device includes a preset time determinator for determining a preset time to be set to the first real-time clock of the terminal device based on the second real-time clock, and a latency time timer for clocking a lapse of a latency time, the latency time being a period of time from the terminal device acquiring the preset time until the preset time being set to the first real-time clock, and the latency time being calculated in a clocking accuracy having the number of effective figures greater than that of the first real-time clock; and', 'a time setter for setting the preset time to the first real-time clock when the latency time is lapsed., 'wherein the terminal device includes2. The time synchronization system of claim 1 , wherein the control device further includes a latency time calculator for calculating the latency time by subtracting a time required for the terminal device to acquire the preset time from the preset time.3. The time synchronization system of claim 2 , wherein the control device calculates the latency time when setting the same preset ...

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Номер записи: 57
17-06-2021 дата публикации

SINGLE-COUNTER, MULTI-TRIGGER SYSTEMS AND METHODS IN COMMUNICATION SYSTEMS

Номер: US20210181788A1
Автор: MISHRA Lalan Jee, Wietfeldt Richard Dominic
Принадлежит:

Single-counter, multi-trigger systems and methods in communication systems consolidate tracking of multiple trigger events into a single counter in place of plural counters. The single counter may track multiple trigger events for a single triggered element. Likewise, the single counter may track trigger events for a plurality of triggered elements. By consolidating tracking of trigger events with reference to a single counter, the size of the circuit may be reduced and power savings may be achieved. 1. An integrated circuit (IC) , comprising:a counter;a comparator comprising a set-point register, the comparator coupled to the counter and configured to compare a value from the counter to a value in the set-point register and output a signal when there is a match;a register coupled to the comparator and configured to receive the signal; anda trigger circuit coupled to the register and configured to receive a register value stored in the register when the register receives the signal.2. The IC of claim 1 , further comprising:a bus interface configured to be coupled to a bus and configured to receive a datagram from a host through the bus; and populate a trigger window from the datagram to the counter;', 'populate the value in the set-point register from the datagram; and', 'populate the register value from the datagram to the register., 'a control circuit configured to3. The IC of claim 2 , wherein the bus interface comprises a radio frequency front end (RFFE) bus interface.4. The IC of claim 1 , wherein the IC is configured to operate as a slave in an RFFE system.5. The IC of claim 1 , wherein the IC comprises one of a power amplifier claim 1 , a tuner claim 1 , or a switch.6. The IC of claim 1 , wherein the IC comprises a power amplifier and the trigger circuit comprises a low noise amplifier.7. The IC of claim 1 , further comprising a plurality of trigger circuits.8. The IC of claim 7 , further comprising a plurality of registers claim 7 , individual ones of the ...

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Номер записи: 58
09-06-2016 дата публикации

CALIBRATED TIMEOUT INTERVAL ON A CONFIGURATION VALUE, SHARED TIMER VALUE, AND SHARED CALIBRATION FACTOR

Номер: US20160161982A1
Автор: Farmer James V., GRITTER Daniel S., Katzen Glenn I.
Принадлежит:

A processor-implemented method for implementing a shared counter architecture is provided. The method may include receiving, by a worker thread, an application request; recording, by a common timer thread, a shared timer value and acquiring, by the worker thread, the shared timer value. The method may further include recording, by the common timer thread, a shared calibration factor; acquiring, by the worker thread, a configuration value corresponding to the application request and generating, by the worker thread, a calibrated timeout interval for the application request based on the shared calibration factor, the shared timer value, and the configuration value. The method may further include registering, by the worker thread, the calibrated timeout interval for the application request on a current timeout list; determining, by the common timer thread, a timeout occurrence for the application request based on the registered calibrated timeout interval; and releasing resources based on the timeout occurrence. 1. A processor-implemented method for implementing a shared counter architecture , the method comprising:receiving, by a worker thread, an application request;recording, by a common timer thread, a shared timer value;acquiring, by the worker thread, the shared timer value;recording, by the common timer thread, a shared calibration factor;acquiring, by the worker thread, a configuration value corresponding to the application request;generating, by the worker thread, a calibrated timeout interval for the application request based on the shared calibration factor, the shared timer value, and the configuration value, and wherein the calibrated timeout interval for the application request comprises the sum of a configuration value for the application request; the shared timer value; and the shared calibration factor;registering, by the worker thread, the calibrated timeout interval for the application request on a current timeout list;determining, by the common ...

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Номер записи: 59
23-05-2019 дата публикации

INFORMATION PROCESSING SYSTEM

Номер: US20190155330A1
Автор: HAYASHI Masato, Kato Takeshi, Yamaoka Masanao, YOSHIMURA Chihiro
Принадлежит:

An aspect of the present invention for solving the above problem is a system including a first computer, a control module controlled by the first computer, and a second computer configured to be associated with the control module. The second computer includes a plurality of units, and each of the plurality of units includes a first memory that stores a value indicating a state of a node, a second memory that stores a coefficient, and an arithmetic circuit. The arithmetic circuit performs an arithmetic process of determining a value indicating a state of a node of its own unit, based on a value indicating a state of a node of a different unit and the coefficient of its own unit, and storing the determined value in the first memory. The control module supplies a control signal for controlling the arithmetic process to the second computer. 1. An information processing system comprising:a first computer;a control module controlled by the first computer; anda second computer configured to be associated with the control module,wherein the second computer includes a plurality of units,wherein each of the plurality of units includes a first memory that stores a value indicating a state of a node, a second memory that stores a coefficient, and an arithmetic circuit,wherein the arithmetic circuit performs an arithmetic process of determining a value indicating a state of the node of its own unit, based on a value indicating a state of a node of a different unit and the coefficient of its own unit, and storing the determined value in the first memory, andwherein the control module supplies a control signal for controlling the arithmetic process to the second computer.2. The information processing system according to claim 1 ,wherein the control signal includes an address for designating the unit to perform the arithmetic process, and a clock for generating a timing to perform the arithmetic process.3. The information processing system according to claim 2 ,wherein the control ...

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Номер записи: 60
18-06-2015 дата публикации

ELECTRONIC TIMEPIECE AND OPERATION SETTING SWITCHING SYSTEM

Номер: US20150168920A1
Автор: NISHIHARA Satoshi
Принадлежит: CASIO COMPUTER CO., LTD.

An electronic timepiece, including: a first operation unit; a first communication unit; and a first control unit, wherein one of the plurality of the operation receiving units is a function switching operation receiving unit, i) when a first input signal is input, the first control unit assigns the operation receiving units including the function switching operation receiving unit as external device operation receiving units according to predetermined operation processing to be executed by the external device, ii) when an input operation to the operation receiving units is detected, the first control unit transmits an operation request according to the operation processing corresponding to the input operation to the external device via the first communication unit, and iii) when a second input signal is input, the first control unit ends assignment of the operation receiving units as the external device operation receiving units. 1. An electronic timepiece , comprising:a first operation unit which has a plurality of operation receiving units and outputs an input signal corresponding to an input operation to the operation receiving units;a first communication unit which communicates with an external device to receive an input signal and transmit an output signal; anda first control unit which performs operation control corresponding to an input signal,whereinone of the plurality of the operation receiving units is a function switching operation receiving unit for selecting and switching any one of a plurality of function modes which are executable by the first control unit,i) when a first input signal is input, the first control unit assigns the operation receiving units including the function switching operation receiving unit as external device operation receiving units according to predetermined operation processing to be executed by the external device,ii) when an input operation to the operation receiving units assigned as the external device operation receiving ...

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Номер записи: 61
24-06-2021 дата публикации

PARALLEL PROCESSING DEVICE

Номер: US20210191847A1
Автор: Kim Tae Hyoung
Принадлежит: MORUMI CO., LTD.

A parallel processing device includes a calculation path network configured to receive a plurality of pieces of delay data output from a delay processing unit, a plurality of pieces of memory output data output from a memory, and a plurality of calculation path network control signals and configured to output a plurality of pieces of calculation path network output data, and the delay processing unit configured to output the plurality of pieces of delay data obtained by delaying the plurality of pieces of calculation path network output data. Each of the plurality of pieces of calculation path network output data is a value obtained by performing a calculation, which corresponds to one of the plurality of calculation path network control signals corresponding to the piece of calculation path network output data, on the plurality of pieces of delay data and the plurality of pieces of memory output data. 1. A parallel processing device which allows consecutive parallel data processing to be performed , the parallel processing device comprising:a calculation path network configured to receive a plurality of pieces of delay data output from a delay processing unit, a plurality of pieces of memory output data output from a memory, and a plurality of calculation path network control signals and configured to output a plurality of pieces of calculation path network output data; andthe delay processing unit configured to output the plurality of pieces of delay data obtained by delaying the plurality of pieces of calculation path network output data,wherein each of the plurality of pieces of calculation path network output data is a value obtained by performing a calculation, which corresponds to one of the plurality of calculation path network control signals corresponding to the piece of calculation path network output data, on the plurality of pieces of delay data and the plurality of pieces of memory output data.2. The parallel processing device of claim 1 , wherein the ...

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Номер записи: 62
29-09-2022 дата публикации

CLOCK DATA RECOVERY CIRCUIT

Номер: US20220308618A1
Автор: Evans David Wayne, Hanschke Michael Ryan, Pandey Pankaj, Pham Joseph
Принадлежит:

A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration. 1. A clock data recovery circuit , comprising:a deglitch filter circuit configured to remove pulses having less than a particular duration from a data signal to produce a deglitched data signal; and compare a duration of a pulse of the deglitched data signal to a threshold duration; and', 'identify the pulse of the deglitched data signal as representing a logic one based on the duration of the pulse exceeding the threshold duration., 'a timer circuit coupled to the deglitch filter circuit, and configured to2. The clock data recovery circuit of claim 1 , wherein the timer circuit is configured to identify the pulse as representing a logic zero based on the duration of the pulse not exceeding the threshold duration.3. The clock data recovery circuit of claim 1 , wherein the timer circuit includes a flip-flop configured to store the logic one represented by the pulse at an end of the threshold duration.4. The clock data recovery circuit of claim 3 , further comprising:a delayed pulse circuit configured to generate, responsive to a leading edge of the pulse, a reset pulse;wherein the timer circuit is configured to apply the reset pulse to reset the flip-flop.5. The clock data recovery circuit of claim 4 , wherein the delayed pulse circuit includes:a delay circuit configured to delay the pulse produce a delayed pulse; anda pulse generation circuit configured to generate the reset pulse at a leading edge of the delayed pulse.6. The clock data recovery circuit of ...

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Номер записи: 63
21-05-2020 дата публикации

REAL TIME CLOCK DEVICE FOR VEHICLE AND OPERATING METHOD THEREOF

Номер: US20200159282A1
Автор: Jang Dong On, JANG Doo Jin, Jo Won Hee, KIM Young Suk, Lee Ji Haeng, Park Hyung Min
Принадлежит: Hyundai Autron Co., Ltd.

A real time clock device for a vehicle may include: a register set provided with a first register, in which second time information is stored, and configured to store Real Time Clock (RTC) data including the time or date; and a data compensation circuit to block an input of a 1 second (1 s) tick to the first register and compensate for a delay time according to the block of the input of the 1 s tick to the first register by an RTC lock signal during a process of transmitting the RTC data to an external device or receiving setting data for the RTC data from the external device. 1. A real time clock device for a vehicle , comprising:a register set provided with a first register, in which second time information is stored, and configured to store Real Time Clock (RTC) data including time or date; anda data compensation circuit configured to block an input of a 1 second (1 s) tick to the first register and compensate for a delay time based on the block of the input of the 1 s tick to the first register by an RTC lock signal during a process of transmitting the RTC data to an external device or receiving setting data for the RTC data from the external device.2. The real time clock device of claim 1 , wherein the RTC lock signal is set by the external device.3. The real time clock device of claim 2 , wherein when there is no setting of the RTC lock signal by the external device claim 2 , a normal operation of the register set is performed by the is tick.4. The real time clock device of claim 1 , wherein the data compensation circuit includes a 1 s tick generator configured to receive a clock from an outside and generate the 1 s tick.5. The real time clock device of claim 4 , wherein the data compensation circuit further includes a 1 s tick register configured to store a result of a calculation of the 1 s tick and the RTC lock signal.6. The real time clock device of claim 5 , wherein the data compensation circuit further includes a 1 s tick counter configured to count a 1 ...

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Номер записи: 64
22-06-2017 дата публикации

PUSH-BUTTON ARRANGEMENT FOR AN ELECTRONIC OR ELECTROMECHANICAL WRISTWATCH

Номер: US20170178834A1
Автор: Balmer Raphael, LAGORGETTE Pascal
Принадлежит: ETA SA Manufacture Horlogere Suisse

A push-button arrangement includes an electronic plate. The push-button is of the type surface mounted on a flexible printed circuit sheet that is itself partially fixed to the electronic plate. A portion of the flexible printed circuit sheet that carries the push-button remains free and is folded around a peripheral edge of the electronic plate, such that the push-button extends substantially perpendicularly to the electronic plate and bears against a lateral surface of the electronic plate. 1. A push-button arrangement comprising:an electronic plate, wherein the push-button is of the type surface mounted on a flexible printed circuit sheet that is itself partially fixed to the electronic plate, wherein a portion of the flexible printed circuit sheet that carries the push-button remains free and is folded around a peripheral edge of the electronic plate, such that the push-button extends substantially perpendicularly to the electronic plate and bears against a lateral surface of the electronic plate.2. The push-button arrangement according to claim 1 , wherein the push-button is disposed in a housing arranged in the electronic plate claim 1 , wherein the housing limits the displacement of the push-button horizontally forwards and backwards claim 1 , and vertically downwards.3. The push-button arrangement according to claim 2 , wherein the housing provided in the electronic plate is covered by an additional plate that limits the displacement of the push-button vertically upwards.4. A portable object comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a case inside which is housed a push-button arrangement according to , wherein the case of the portable object is pierced with a through hole inside which slides a stem of an external push-button, wherein the stern is held in a rest position by an elastic device that pushes the stem outwards, and wherein the stem is moved into an operating position in which the stem presses on the surface mount push-button by ...

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Номер записи: 65
18-09-2014 дата публикации

INFORMATION PROCESSING DEVICE, TIME ADJUSTING METHOD, AND TIME ADJUSTING PROGRAM

Номер: US20140281660A1
Автор: AKIYAMA Haruhiko, GOTO Masataka, Kobayashi Yuta, Sugasawa Nobuhiko
Принадлежит: KABUSHIKI KAISHA TOSHIBA

One embodiment provides an information processing device which includes a clock unit, a file access unit and a setting unit. The clock unit is configured to count up an elapsed time from a prescribed reference time if an origin time has not been set, and to count up an elapsed time from the origin time if the origin time has been set. The file access unit is configured to access a file which has time information given by an external device or the information processing device. The file is stored in a storage device. The setting unit is configured to acquire the time information from the file via the file access unit, and to set the acquired time information into the clock unit as the origin time. 1. An information processing device , comprising:a clock unit configured to count up an elapsed time from a prescribed reference time if an origin time has not been set, and to count up an elapsed time from the origin time if the origin time has been set;a file access unit configured to access a file which has time information given by an external device or the information processing device, the file being stored in a storage device; anda setting unit configured to acquire the time information from the file via the file access unit, and to set the acquired time information into the clock unit as the origin time.2. The information processing device of claim 1 ,wherein the file has plural time information, andwherein the setting unit acquires the plural time information, and sets time information indicating a latest time among the acquired plural time information into the clock unit as the origin time.3. The information processing device of claim 1 ,wherein plural files are stored in the storage device, andwherein the setting unit acquires plural time information from the plural files via the file access unit, and sets time information indicating a latest time among the acquired plural time information into the clock unit as the origin time.4. The information processing ...

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Номер записи: 66
12-07-2018 дата публикации

DETERMINING CLOCK SIGNAL QUALITY USING A PLURALITY OF SENSORS

Номер: US20180198595A1
Автор: Restle Phillip John, Vezyrtzis Christos, Warnock James Douglas
Принадлежит:

Techniques for determining the quality of a clock signal are provided. In one example, a method can comprise comparing, by a sensory circuitry of a system, a first output of a first sensor and a second output of a second sensor. The first output and the second output can be based on a parameter of a clock signal. Further, in some embodiments, the first sensor and the second sensor can be local clock buffers. The method can also comprise determining, by a controller of the system, a quality of the clock signal based on the comparing of the first output and the second output. 116-. (canceled)17. A system , comprising: a first sensor that generates a first output;', 'a second sensor that generates a second output, wherein the first sensor and the second sensor comprise local clock buffers; and', 'a sensor circuit that receives and compares the first output and the second output from the first sensor and the second sensor, respectively, wherein the first output and the second output are generated based on a parameter of a clock signal; and, 'sensory circuitry comprisinga controller communicatively coupled to the sensor circuit and that determines a quality of the clock signal based on the comparison of the first output and the second output, wherein the sensor circuit comprises a digital delay sensor, and wherein the digital delay sensor determines a difference between a first time associated with receipt of the first output and a second time associated with receipt of the second output.18. The system of claim 17 , further comprising a clock distribution network having at least one buffer and communicatively coupled to the controller claim 17 , wherein the controller also activates or deactivates the at least one buffer in the clock distribution network based on the quality of the clock signal.19. The system of claim 17 , wherein the first sensor and the second sensor have respective programmable capacitances.20. (canceled) The subject disclosure relates to determining ...

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Номер записи: 67
12-07-2018 дата публикации

DETERMINING CLOCK SIGNAL QUALITY USING A PLURALITY OF SENSORS

Номер: US20180198596A1
Автор: Restle Phillip John, Vezyrtzis Christos, Warnock James Douglas
Принадлежит:

Techniques for determining the quality of a clock signal are provided. In one example, a method can comprise comparing, by a sensory circuitry of a system, a first output of a first sensor and a second output of a second sensor. The first output and the second output can be based on a parameter of a clock signal. Further, in some embodiments, the first sensor and the second sensor can be local clock buffers. The method can also comprise determining, by a controller of the system, a quality of the clock signal based on the comparing of the first output and the second output. 1. A method , comprising:comparing, by sensory circuitry of a system, a first output of a first sensor and a second output of a second sensor, wherein the first output and the second output are based on a parameter of a clock signal, and wherein the first sensor and the second sensor are local clock buffers; anddetermining, by a controller of the system, a quality of the clock signal based on the comparing of the first output and the second output.2. The method of claim 1 , wherein the parameter is selected from a group consisting of a signal amplitude claim 1 , a rising slew rate and a falling slew rate.3. The method of claim 1 , further comprising outputting claim 1 , by a clock distribution network of the system claim 1 , the clock signal to an integrated circuit of the system.4. The method of claim 3 , wherein the integrated circuit comprises a third sensor claim 3 , wherein the first sensor is a same type of sensor as the third sensor claim 3 , and wherein the parameter causes greater variation between the second output and the clock signal than between a third output of the integrated circuit and the clock signal claim 3 , wherein the third output is an output of the third sensor.5. The method of claim 1 , wherein the first sensor and the second sensor are adapted to have respective programmable capacitances.6. The method of claim 5 , further comprising receiving claim 5 , by a digital ...

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Номер записи: 68
19-07-2018 дата публикации

COMMUNICATION APPARATUS, ELECTRONIC TIMEPIECE, COMMUNICATION METHOD AND RECORDING MEDIUM

Номер: US20180203420A1
Автор: MARUYAMA Hirohisa, MOROHOSHI Hiroshi
Принадлежит: CASIO COMPUTER CO., LTD.

A communication apparatus comprises a communicator that receives a standard time from an external apparatus, a manipulation receiver that receives a time correction action from a user, and a controller that performs a timing processing for clocking time and a time correction processing for correcting the time clocked by the timing processing, on the basis of the standard time received by the communicator, or on the basis of the time correction action received by the manipulation receiver. The controller changes processing contents of the time correction processing until a prescribed time interval has elapsed, when the time clocked by the timing processing is corrected on the basis of the time correction action received by the manipulation receiver. 1. An apparatus comprising: control a memory to store one or more values of a corresponding one or more time information associated with a first location;', 'receive a manipulation content based on a manipulation of one or more input mechanisms by a user;', 'perform a manual time correction process comprising changing at least one of the one or more values of the one or more time information stored in the memory, based on the manipulation content;', 'in response to performing the manual time correction process, set a value of a counter to a predetermined time interval and incrementally reduce the value of the counter towards an end value; and', determining whether the value of the counter has been incrementally reduced to the end value;', 'in response to determining that the value of the counter has been incrementally reduced to the end value, performing a first process comprising correcting the time information based on a standard time information associated with a second location, wherein the standard time information is received through a wireless transmitter/receiver from an external apparatus; and', 'in response to determining that the value of the counter has not been incrementally reduced to the end value, ...

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Номер записи: 69
02-10-2014 дата публикации

On-Demand Scalable Timer Wheel

Номер: US20140298073A1
Автор: Cox Matthew R., Pashov Ivan D., Silvera Jonathan A., ZHOU Ziyan
Принадлежит: MICROSOFT CORPORATION

Various embodiments enable on-demand scaling of a timer wheel. Some embodiments dynamically start and stop a timer wheel based, at least in part, on whether the timer wheel has any associated active timers. In some cases, the timer wheel is suspended when all associated active timers have been serviced. Alternately or additionally, the timer wheel is re-activated upon associating one or more active timers in need of service to the timer wheel. Various embodiments enable addition and removal of timer(s) to the timer wheel and/or various time slots associated with the timer wheel without using a global lock associated with the timer wheel. 1. A computer-implemented method comprising:instantiating a scalable timer wheel configured to manage a plurality of timers;determining whether the scalable timer wheel is void of timers;responsive to determining the scalable timer wheel is void of timers, suspending periodic activity of the scalable timer wheel; andresponsive to adding at least one timer to said void scalable timer wheel, reactivating the periodic activity of the scalable timer wheel.2. The computer-implemented method of further comprising assigning at least one timer to at least one time slot associated with the scalable timer wheel.3. The computer-implemented method of claim 2 , wherein determining whether the scalable timer wheel is void of timer comprises utilizing an atomic counter configured to track when the at least one timer is assigned to the at least one time slot and when the at least one timer is disassociated with the at least one time slot.4. The computer-implemented method of claim 1 , wherein the periodic activity comprises:identifying an active time slot from of a plurality of time slots associated with the scalable timer wheel;identifying any timers associated with the active time slot;enabling servicing of each of said identified timers associated with the active time slot; andtemporarily suspending execution of the scalable timer wheel until a ...

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Номер записи: 70
26-07-2018 дата публикации

CIRCUIT DEVICE, REAL-TIME CLOCKING DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

Номер: US20180210488A1
Автор: Kamiyama Masayuki, KIYA Hiroshi
Принадлежит:

A circuit device includes a processing unit that detects occurrence of an internal event of the circuit device, a storage unit, and a clocking unit that generates clocking data which is real-time clock information on the basis of an oscillation signal generated using a resonator. The processing unit stores specific information on the internal event and the clocking data when the occurrence of the internal event is detected, in the storage unit when the occurrence of the internal event is detected. 1. A circuit device comprising:a processing circuit configured to detect occurrence of an internal event of the circuit device;a storage circuit; anda clocking circuit configured to generate clocking data which is real-time clock information based on an oscillation signal,wherein the processing circuit stores specific information on the internal event and the clocking data when the occurrence of the internal event is detected, in the storage circuit when the occurrence of the internal event is detected.2. The circuit device according to claim 1 ,wherein in a case where occurrence of an i-th internal event (i is an integer of equal to or greater than 1 and equal to or less than n) among first to n-th internal events (n is an integer of 2 or greater) is detected, the processing circuit stores information for specifying the occurrence of at least the i-th internal event in the storage circuit as the specific information.3. The circuit device according to claim 2 ,wherein the j-th internal event (j is an integer of equal to or greater than 1 and equal to or less than n, and is an integer different from i) among the first to n-th internal events occurs after the i-th internal event occurs, the processing circuit stores information for specifying the occurrence of the j-th internal event in a storage region of an address different from an address in which the information for specifying the occurrence of the i-th internal event is stored.4. The circuit device according to claim 2 ...

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Номер записи: 71
26-07-2018 дата публикации

CIRCUIT DEVICE, OSCILLATION DEVICE, PHYSICAL QUANTITY MEASURING DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

Номер: US20180212786A1
Автор: Kamiyama Masayuki, KIYA Hiroshi, USUDA Toshiya
Принадлежит:

A circuit device includes an oscillation circuit that generates an oscillation signal by using an oscillator, a processing unit that controls the oscillation circuit, and an interface unit that outputs authentication information to an external device. The authentication information being information based on specific information of the circuit device and is used to authenticate the circuit device. 1. A circuit device comprising:an oscillation circuit configured to generate an oscillation signal;a processing circuit configured to control the oscillation circuit; andan interface circuit configured to output authentication information to an external device, the authentication information corresponding to specific information uniquely identifying the circuit device.2. The circuit device according to claim 1 , further comprising:a non-volatile memory configured to store oscillation adjustment data of the oscillation circuit and the specific information,wherein the interface circuit is configured to output the authentication information to the external device based on the specific information stored in the non-volatile memory.3. The circuit device according to claim 1 , further comprising:a non-volatile memory configured to store the oscillation adjustment data as the specific information,wherein the interface circuit is configured to output the authentication information to the external device based on the specific information stored in the non-volatile memory.4. The circuit device according to claim 1 ,wherein the interface circuit is configured to receive external device authentication information, andwherein the processing circuit is configured to authenticate the external device based on the external device authentication information.5. The circuit device according to claim 1 , further comprising:an encoding processing circuit configured to encode the authentication information,wherein the interface circuit is configured to output the authentication information ...

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Номер записи: 72
04-08-2016 дата публикации

REAL-TIME-CALIBRATION CIRCUIT FOR MULTIPLE CPUS

Номер: US20160224054A1
Автор: Lin Mu-Chun
Принадлежит:

A real-time-calibration circuit for multiple CPUs includes the CPUs for communication, for control and for acting as a panel board. The CPUs each have a real-time clock built therein. The CPU for communication is connected with an external real-time clock, and only the external real-time clock is connected with a battery. Through the CPU for communication, a standard time is obtained from an external network and provided to the external real-time clock for time calibration. Then a calibration value generated from the time calibration is fed back to the CPU for communication to be used by the real-time clock of the CPU for communication and the real-time clocks of the other CPUs, so as to prevent the CPUs from interfering communication during time calibration, and reduce the need of power and of batteries, thereby saving energy and costs and being friendly to the environment. 1. A real-time-calibration circuit for multiple CPUs , the real-time-calibration circuit comprising:an external real-time clock, being connected with and alternatively powered by a battery;a first CPU acting for communication when connected with an external network for communication, wherein the first CPU is connected with the external real-time clock and includes a first real-time clock built therein;a second CPU acting for control, wherein the second CPU is connected with the first CPU and includes a second real-time clock built therein; anda third CPU acting as a panel board, wherein the third CPU is connected with the first CPU and includes a third real-time clock built therein;whereby, after the first CPU obtains a standard time from the external network and sends the standard time to the external real-time clock for time calibration, the external real-time clock sends a calibration value beck to the first CPU so that the first CPU performs time calibration on the first real-time clock built therein, and sends the calibration value to the second real-time clock and the third real-time clock ...

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Номер записи: 73
04-08-2016 дата публикации

ABNORMAL CLOCK RATE DETECTION IN IMAGING SENSOR ARRAYS

Номер: US20160224055A1
Автор: Aziz Naseem Y., Boulanger Pierre, Goodland Jim, Hoelter Theodore R., Högasten Nicholas, Kurth Eric A., Nussmeier Mark, Sharp Barbara, Simolon Brian, Strandemar Katrin
Принадлежит:

Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select a current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value. 1. A device comprising:a counter configured to receive a clock signal and adjust a count value in response to the clock signal;a ramp generator configured to generate a ramp signal having a slope independent of the clock signal;a comparator configured to receive a reference signal via a first input and the ramp signal via a second input, and select a current count value of the counter in response to the reference signal and the ramp signal; anda processor configured to determine, based on the current count value, if a frequency of the clock signal is within a specified range.2. The device of claim 1 , wherein the reference signal and the ramp signal exhibit similar variations over temperature such that the current count value selected by the comparator is substantially stable over temperature.3. The device of claim 2 , further comprising:a reference signal generator configured to generate the reference signal that is independent of the clock signal; anda matched pair of first and second analog components that are ...

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Номер записи: 74
20-08-2015 дата публикации

METHOD AND A SYSTEM FOR SENDING A FIRST AND SECOND MESSAGE

Номер: US20150234691A1
Автор: Fitzpatrick Matthew John, Hurd Matthew John
Принадлежит:

A system for sending a first message and a second message subsequent to the first message. The system comprises a message sender arranged to send the first message to a processor arranged to process the first message and the second message. The processor is arranged to refuse the second message until after the processor concludes transmitting a response to the first message. The message sender is further arranged to send the second message to the processor before receipt of the response to the first message and at a time for the second message to arrive at the processor after the processor concludes the sending of the response to the first message. 1. A system for sending a first message and a second message subsequent to the first message , the system comprising:a message sender arranged to send the first message to a processor arranged to process the first message and the second message, the processor being arranged to refuse the second message until after the processor concludes transmitting a response to the first message, the message sender being further arranged to send the second message to the processor before receipt of the response to the first message and at a time for the second message to arrive at the processor after the processor concludes the sending of the response to the first message.2. A system defined by comprising a time determiner arranged to determine the time.3. A system defined by wherein the time determiner is arranged to determine the time using processing interval information indicative of a predicted interval between the processor receiving the first message and the processor sending the response to the first message.4. A system defined by wherein the time determiner is arranged to determine the time by adding the value of the predicted interval to a time at which the first message was sent.5. A system defined by wherein the time determiner is arranged to determine the time by causing the message sender to send a plurality of ...

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Номер записи: 75
09-08-2018 дата публикации

APPARATUS AND METHOD FOR ASYNCHRONOUS EVENT TIMESTAMPING

Номер: US20180224887A1
Автор: Pitigoi-Aron Radu
Принадлежит:

Methods and apparatuses are described for obtaining a timestamp of an interface event. In one configuration, a host receives an in-band interrupt (IBI) from a sensor. The IBI indicates an interface event occurring at a first time on the sensor. The host issues a first host-initiated event at a second time after the first time in response to the IBI and starts a first host count of cycles of a host clock, wherein a start of the first host count of cycles is concurrent with issuing the first host-initiated event. The host further detects whether reception of the IBI was delayed. If the reception of the IBI was not delayed, the host obtains the timestamp of the interface event based on a first set of variables. If the reception of the IBI was delayed, the host obtains the timestamp of the interface event based on a second set of variables. 1. A method of a host controller for obtaining a timestamp of an interface event occurring on an interface , comprising:receiving an in-band interrupt (IBI) from a sensor, the IBI indicating an occurrence of an interface event caused by the sensor, the interface event occurring at a first time on the sensor;issuing a first host-initiated event on the interface at a second time after the first time in response to the received IBI and starting a first host count of cycles of a host controller clock, wherein a start of the first host count of cycles is concurrent with issuing the first host-initiated event;detecting whether reception of the IBI was delayed; 'obtaining the timestamp of the interface event occurring at the first time based at least in part on a first sensor clock count, a clock period of the sensor, and a host controller timestamp of the second time; and', 'if the reception of the IBI was not delayed 'obtaining the timestamp of the interface event occurring at the first time based at least in part on the first host count of cycles of the host controller clock, the first sensor clock count, a second sensor clock count, a ...

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Номер записи: 76
30-10-2014 дата публикации

SYNTHETIC TIME SERIES DATA GENERATION

Номер: US20140325251A1
Автор: Arlitt Martin, Bash Cullen E., Marwah Manish, Shah Amip J.
Принадлежит: Hewlett-Packard Development Company, L.P.

According to an example, synthetic time series data generation may include receiving time series data for a plurality of users, and applying dimensionality reduction to transform the time series data from a high dimensional space n of the time series data to a low dimensional space m, where m Подробнее

Номер записи: 77
26-08-2021 дата публикации

REAL TIME SENSE & CONTROL ARCHITECTURE

Номер: US20210263777A1
Автор: Bydeley David Kenneth, CHARLES Gordon Alexander, Ng Gary Wayne
Принадлежит:

A system for providing synchronous access to hardware resources includes a first network interface element to receive a network time signal from a data communication network and a memory to store sequence of one or more instructions selected from an instruction set of the first processing circuit. The sequence of one or more instructions include a first instruction that is configured to synchronize execution of a second instruction of the sequence of one or more instructions with the network time signal. The system further includes a first processing circuit to use the first instruction and a timing parameter associated with a second instruction to execute the second instruction in synchrony with the network time signal. 1. A system for providing synchronous access to hardware resources , the system comprising:first network interface element to receive a network time signal from a data communication network;a memory to store sequence of one or more instructions selected from an instruction set of the first processing circuit, the sequence of one or more instructions comprising a first instruction that is configured to synchronize execution of a second instruction of the sequence of one or more instructions with the network time signal; anda first processing circuit to use the first instruction and a timing parameter associated with a second instruction to execute the second instruction in synchrony with the network time signal.2. The system of claim 1 , wherein the first processing circuit comprises a synchronization element to:synchronize an internal time signal with the network time signal; andexecute the sequence of one or more instructions in synchrony with the internal time signal.3. The system of claim 2 , wherein the system comprises an internal timing element to maintain the internal time signal in a time of day format within the processor.4. The system of claim 1 , wherein the first processing circuit comprises a synchronization element to use the first ...

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Номер записи: 78
26-08-2021 дата публикации

DOCUMENTING TIMESTAMPS WITHIN A BLOCKCHAIN

Номер: US20210263907A1
Автор: KRUEGER Benedikt
Принадлежит: Siemens Healthcare GmbH

A method is for determining a further data block. An embodiment of the method includes receiving a further timestamp transaction via a first interface, including a hash of a dataset and a further verification time; receiving a distributed ledger via the first interface, including data blocks; determining via a first computation unit, a first time by querying a time server; performing via the first computation unit, a first check based on the first time and the further verification time; and determining via the first computation unit, upon first check being positive, the further data block based on the distributed ledger, the further data block including the further timestamp transaction. A block creation system is also included in another embodiment, for determining a further data block, the system including a first interface and first computation unit. 1. A method for determining a further data block comprising:receiving a further timestamp transaction via a first interface, the further timestamp transaction including a hash of a dataset and a further verification time;receiving a distributed ledger via the first interface, the distributed ledger including data blocks;determining via a first computation unit, a first time by querying a time server; andperforming via the first computation unit, a first check based on the first time and the further verification time; anddetermining via the first computation unit, upon first check being positive, the further data block based on the distributed ledger, the further data block including the further timestamp transaction.2. The method of claim 1 , wherein the first check is positive if the further verification time is relatively later than the first time.5. The method of claim 4 , wherein the second check is positive upon a number of data blocks contained in the distributed ledger related to the further timestamp transaction claim 4 , is relatively lower that a threshold number.9. The method of claim 7 , wherein the ...

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Номер записи: 79
07-09-2017 дата публикации

SETTING AN ALARM CLOCK ON A SMART DEVICE

Номер: US20170255168A1
Автор: Zhu Yimeng
Принадлежит:

Embodiments of the present application relate to a method and apparatus for setting an alarm clock. The method includes receiving an input directed at a time-display area on a display screen of a device, adjusting time information displayed on the display screen according to the input, and setting an alarm clock according to the adjusted time information. 1. A method , comprising:receiving an input to a device, wherein the device is in a locked state; andconfiguring one or more alarm clock settings based at least in part on the input without s requiring the device to be unlocked.2. The method of claim 1 , wherein the input is directed to a predefined area of a display screen to the device.3. The method of claim 1 , wherein the input corresponds to a touch-control operation to a touchscreen.4. The method of claim 1 , wherein the configuring of the one or more alarm clock settings comprises adjusting time information displayed on a display screen of the device based at least in part on the input.5. The method of claim 4 , wherein the time information displayed on the display screen comprises time information in a time-display area.6. The method of claim 1 , wherein the configuring of the one or more alarm clock settings comprises:in response to receiving the input, displaying an alarm clock setting interface on a display screen of the device,wherein time information displayed on the display screen comprises time information in the alarm clock setting interface.7. The method of claim 1 , wherein the device comprises a touchscreen claim 1 , the input corresponds to a touch-control operation to a touchscreen claim 1 , and the touch-control operation comprises:a time numeral touch-control operation directed at a time-display area on the touchscreen, a time numeral in the time-display area comprising an hour numeral or a minute numeral; ora time touch-control operation directed at an hour hand or a minute hand of a dial clock displayed in the time-display area.8. The ...

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Номер записи: 80
21-09-2017 дата публикации

Method of Actuator Navigation And Electronic Device Comprising An Actuation Navigator Function

Номер: US20170269555A1
Автор: Poguntke Felix
Принадлежит:

A method of setting/calibrating a feature or function in a setting/calibrating mode of an electronic device comprising at least one actuatable selector, wherein the setting/calibrating of the feature or function requires an actuation of the at least one selector, wherein the electronic device comprises at least one indicator hand coupled to an actuation mechanism that rotates the at least one indicator hand in at least one of a clockwise and counterclockwise direction, wherein the method comprises the steps of using the at least one indicator hand to indicate the actuatable selector for actuation; setting/calibrating the feature or function; and exiting the setting/calibration mode. An electronic device that carries out the foregoing method is also disclosed.

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Номер записи: 81
22-09-2016 дата публикации

CLOCK SYNCHRONIZED DYNAMIC PASSWORD SECURITY LABEL VALIDITY REAL-TIME AUTHENTICATION SYSTEM AND METHOD THEREOF

Номер: US20160277393A1
Автор: FAN XIAODONG
Принадлежит: Hangzhou Wopuwulian Science & Technology Co., LTD

This invention discloses a clock synchronized dynamic password security label validity real-time authentication system and method thereof, which comprises, the electronic label module, the user authentication terminal module, and the authentication service module. The electronic label module is used for generating the dynamic password data and displaying. The user authentication terminal module captures the dynamic password data generated by the electronic label module and the image data of the ID number of the electronic label module. After the analyzing processing, the text data is obtained, and then is sent to the authentication service module through the Internet. After receiving the text data, the authentication service module obtains the result of whether the first dynamic password data generating algorithm of the electronic label module is consistent with the second dynamic password data generating algorithm of the authentication service module. The result is returned to the user authentication terminal module. 1. A clock synchronized dynamic password security label validity real-time authentication method , wherein the clock synchronized dynamic password security label validity real-time authentication method comprising the following steps:step one: assigning a unique ID number for each electronic label module, wherein the ID number is expressed as IDS1 and located on a surface of the electronic label module; defining an identical clock accumulating cycle in the electronic label module and an authentication server module; writing a product information and related information to a service configuring unit, wherein the product information and the related information are represented by an ID number IDS1 of the electronic label module; defining a torrent file for associating the electronic label module with the authentication service module, wherein the torrent file comprises: a clock data DSS1, a random number RandomD, and the ID number IDS1 of the electronic ...

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Номер записи: 82
20-09-2018 дата публикации

Electronic Timepiece And Method For Controlling Electronic Timepiece

Номер: US20180267483A1
Автор: Baba Norimitsu
Принадлежит:

An electronic timepiece includes: an information display unit; a storage unit which stores a plurality of pieces of region information and a daylight savings time observation rule corresponding to the region information; a selection unit which selects one of the plurality of pieces of region information stored in the storage unit; a determination unit which determines whether it is a region where daylight savings time is observed or not, based on the daylight savings time observation rule corresponding to the region information selected by the selection unit; and a display control unit which causes the information display unit to display that it is the region where daylight savings time is observed, if it is determined as the region where daylight savings time is observed. 1. An electronic timepiece comprising:an information display;a memory configured to store a plurality of pieces of region information and a daylight savings time observation rule corresponding to the region information;a selector configured to select one of the plurality of pieces of region information stored in the memory;a determiner configured to determine whether the one piece of region information identifies a region where daylight savings time is observed or not, based on the daylight savings time observation rule corresponding to the one piece of region information selected by the selector; anda display controller configured to cause the information display to display that daylight savings time is observed, if it is determined that daylight savings time is observed in the region.2. The electronic timepiece according to claim 1 , further comprising:a satellite signal receiver configured to receive a satellite signal and obtain location information of a current location based on the satellite signal,wherein the selector is configured to select region information to which the current location belongs from the plurality of pieces of region information as the one piece of region information, ...

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Номер записи: 83
11-11-2021 дата публикации

MANAGEMENT OF PEAK CURRENT OF MEMORY DIES IN A MEMORY SUB-SYSTEM

Номер: US20210349663A1
Автор: Aglubat John Paul, Rori Fulvio, Yu Liang
Принадлежит:

A memory management operation is executed on a plurality of memory dies of a memory sub-system. The memory sub-system determines whether a first measured current level corresponding to execution of the memory management operation satisfies a condition pertaining to a threshold peak current level. The memory sub-system determines whether a second measured current level corresponding to execution of the memory management operation satisfies the condition pertaining to the threshold peak current level. Mask data is generated identifying the first measured current level and the second measured current level. A request is received from a host system to execute the memory management operation. The memory sub-system performs, based on the mask data, a peak current management action during execution of the memory management operation.

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Номер записи: 84
29-09-2016 дата публикации

Setting an alarm clock on a smart device

Номер: US20160282816A1
Автор: Yimeng Zhu
Принадлежит: Alibaba Group Holding Ltd

Embodiments of the present application relate to a method and apparatus for setting an alarm clock. The method includes receiving an input directed at a time-display area on a display screen of a device, adjusting time information displayed on the display screen according to the input, and setting an alarm clock according to the adjusted time information.

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Номер записи: 85
28-09-2017 дата публикации

ELECTRONIC TIMEPIECE

Номер: US20170277135A1
Автор: SHIRAO Akira
Принадлежит:

An electronic timepiece includes: a latch unit that latches and outputs specification data designating a specification in accordance with a latch signal; a signal output unit that outputs one of a plurality of driving signals including driving pulses at different periods based on the specification data output from the latch unit; a driving unit that drives a motor based on the driving signal output from the signal output unit; and a control unit that generates the latch signal so that the latch signal has at least an active level at a timing before generation of each driving pulse in the driving signal with a shortest period of the driving pulse among the plurality of driving signals. 1. An electronic timepiece comprising:a latch unit that latches and outputs specification data designating a specification in accordance with a latch signal;a signal output unit that outputs one of a plurality of driving signals including driving pulses at different periods based on the specification data output from the latch unit;a driving unit that drives a motor based on the driving signal output from the signal output unit; anda control unit that generates the latch signal so that the latch signal has at least an active level at a timing before generation of each driving pulse of the driving signal with a shortest period of the driving pulse among the plurality of driving signals.2. The electronic timepiece according to claim 1 , further comprising:a storage unit that stores the specification data,wherein the latch unit latches the specification data read from the storage unit.3. The electronic timepiece according to claim 1 , further comprising:a setting terminal with which one of a plurality of voltages is supplied,wherein the latch unit latches and outputs the specification data according to the voltage of the setting terminal in accordance with the latch signal.4. The electronic timepiece according to claim 1 ,wherein the driving pulse includes a plurality of sub-pulses, ...

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Номер записи: 86
08-10-2015 дата публикации

CONTENT OUTPUT DEVICE FOR OUTPUTTING CONTENT

Номер: US20150286598A1
Автор: MURAKAMI Bungo, Suzuki Hideo
Принадлежит: CASIO COMPUTER CO., LTD.

In order to perform processing corresponding to an instruction or a reaction at appropriate timing when a predetermined instruction is given or a reaction by a user is made while content is being outputted, a CPU detects instruction timing when a predetermined user instruction is given for data outputted while pieces of data constituting content are being sequentially outputted; stores the detected instruction timing in an instruction information memory; specifies predetermined timing that comes later than the instruction timing stored in the instruction information memory as timing for performing processing in accordance with the user's instruction; and performs the processing. 1. A content output device for outputting content , comprising:an output control section which outputs output details in the content while sequentially changing the output details;a content storage section which stores each of the output details of the content in association with each output timing;a detection control section which detects, when an instruction is given at arbitrary timing by a user while the output details of the content are being sequentially changed and outputted, instruction timing of the instruction;a storage control section which causes the detected instruction timing to be stored in an instruction storage section in association with the content;a specification control section which judges whether the instruction timing has been stored in the instruction storage section at predetermined timing after a series of outputs of the output details of the content is completed, reads out the instruction timing stored in the instruction storage section when the instruction timing is judged to have been stored, and specifies an output detail of the content that has been outputted at point of the instruction timing; anda processing execution control section which performs processing corresponding to the specified output detail.2. The content output device according to claim 1 , ...

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Номер записи: 87
27-09-2018 дата публикации

Testing apparatus and control method therefor

Номер: US20180275153A1
Автор: Se Do GWON
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A test apparatus and control method thereof are disclosed, which relate to a technology for providing an in-vitro diagnostic apparatus for enabling a user to change time information used in the system, and displaying the changed time information to use the time information according to local time of a desired country. Also, the present disclosure is directed to providing a test apparatus for determining whether the validity date of test medium has expired to prevent use of expired test medium and to analyze a test object through available test medium, and a method for controlling the test apparatus. The test apparatus of analyzing a test object included in test medium includes a Real Time Clock (RTC) portion configured to provide current time, a user interface configured to receive a time offset command for changing the current time and displaying the changed current time, a first offset manager configured to reflect the time offset command to the current time provided from the RTC portion to calculate time to be displayed, a second offset manager configured to decide reference time to be used to determine whether validity date of the test medium has expired, based on the current time provided from the RTC portion, a validity date acquirer configured to acquire validity date information of the test medium, and a controller configured to determine whether validity date of the test medium has expired, based on the reference time and the validity date information of the test medium.

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Номер записи: 88
27-09-2018 дата публикации

INFORMATION DISPLAY METHOD, SYSTEM, PROGRAM, AND INFORMATION DISPLAY DEVICE

Номер: US20180275615A1
Автор: Tanaka Seiichi
Принадлежит: SEIKO EPSON CORPORATION

An information display method includes recognizing a position relationship between a dial and an indicating hand from an image in which an electronic timepiece having a dial and an indicating hand for indicating the dial is included as an imaged subject, specifying a value corresponding to the position relationship, based on specification information of the electronic timepiece, and displaying an annotation image relating to the specified value along with the image. 1. An information display method comprising:recognizing a position relationship between a dial and an indicating hand from an image in which an electronic timepiece having a dial and an indicating hand for indicating the dial is included as an imaged subject;specifying a value corresponding to the position relationship, based on specification information of the electronic timepiece; anddisplaying an annotation image relating to the specified value along with the image.2. The information display method according to claim 1 ,wherein the dial includes a main dial, and a sub dial disposed in a partial region of the main dial,wherein the indicating hand includes a sub indicating hand for indicating the sub dial, andwherein in the recognizing the position relationship, the position relationship between the sub dial and the sub indicating hand is recognized.3. The information display method according to claim 1 ,wherein in the specifying the value, the value is specified, based on a sensor measurement value indicated by the electronic timepiece.4. The information display method according to claim 2 ,wherein in the specifying the value, the value is specified, based on a sensor measurement value indicated by the electronic timepiece.5. The information display method according to claim 1 ,wherein in the displaying the annotation image, the annotation image is displayed in association with the indicating hand for indicating the specified value.6. The information display method according to claim 3 ,wherein in the ...

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Номер записи: 89
18-12-2014 дата публикации

Virtual Per-Processor Timers for Multiprocessor Systems

Номер: US20140372786A1
Автор: Hartwig Cody, JR. Bruce, SHERWIN, Wohlgemuth Jason
Принадлежит:

A system provides virtual per-processor timers based on a timer such as a platform timer. To virtualize a timer to be used by each processor independently, a data structure is maintained in memory for the timer. The data structure has an entry for each interrupt to be produced for each processor using the timer, specifying the processor and the due time, with the entries sorted by due time. If the virtualized timer is a platform timer that maintains context during power transitions, a processor can switch to the virtual per-processor timer upon a context-losing power transition. 1. A computer comprising:a plurality of processors;a timer;the computer including computer program instructions that when executed by one of the processors configures the computer such that the timer is virtualized to define, for each processor of the plurality of processors, a virtual per-processor timer for the processor by having data specifying a due time for an interrupt for the processor and the processor to receive the interrupt.2. The computer of claim 1 , comprising:in memory, a data structure virtualizing the timer for each processor, the data structure including one or more entries, each entry specifying a due time for an interrupt and a processor to receive the interrupt, the entries being sorted by due time.3. The computer of claim 2 , wherein the data structure is a timer list comprising an entry for each processor claim 2 , wherein an entry is valid if the processor is using the virtual per-processor timer and invalid if the processor is not using the virtual per-processor timer claim 2 , and a queue of valid entries sorted by due time.4. The computer of claim 3 , wherein the computer program instructions configure the computer to arm the platform timer by setting the entry for a processor to be valid claim 3 , and setting the due time of the entry.5. The computer of claim 3 , wherein the computer program instructions configure the computer to stop the virtual per-processor ...

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Номер записи: 90
06-10-2016 дата публикации

DATA BANDWIDTH SCALABLE MEMORY SYSTEM

Номер: US20160291634A1
Автор: CHUN Dexter Tamio, Suh Jungwon, WEST David Ian
Принадлежит:

A clock is distributed to a processor-side base mode clocked transceiver and to a memory-side base mode clocked transceiver, interfacing respective ends of a data lane between a processor and the memory, for duplex communicating over the data lane. Concurrent with the duplex communicating, a bandwidth mode switches between a base bandwidth mode and a scale-up mode. The scale-up mode enables scale-up clock lines that distribute the clock to a processor-side scale-up transceiver and to a memory-side scale-up transceiver, interfacing respective ends of a scale-up data lane between the processor and the memory, for additional duplex communicating over the scale-up data lane. The base bandwidth mode disables the scale-up clock lines, which disables communicating over the scale-up data lane. 1. A method for scalable data bandwidth interfacing , comprising:a concurrent clocking of a processor-side clocked transceiver and a memory-side clocked transceiver, interfacing a processor side and a memory side of a base mode data lane, respectively, which extends from a processor to a memory; andwhile clocking the processor-side clocked transceiver and the memory-side clocked transceiver, switching from a base bandwidth mode to a scale-up mode,wherein the scale-up mode comprises a concurrent clocking of a processor-side scale-up clocked transceiver and a memory-side scale-up clocked transceiver, interfacing a processor side and a memory side of a scale-up data lane, respectively, which extends from the processor to the memory,wherein the base bandwidth mode comprises disabling a clocking of the processor-side scale-up clocked transceiver, or disabling a clocking of the memory-side scale-up clocked transceiver, or both.2. The method of claim 1 , wherein the concurrent clocking of the processor-side clocked transceiver and the memory-side clocked transceiver comprises feeding a clock claim 1 , through a processor-side clock line claim 1 , to a clock input of the processor-side ...

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Номер записи: 91
16-12-2021 дата публикации

Digital Clock with Free Form Path

Номер: US20210389732A1
Автор: Schooley John L.
Принадлежит:

A clock that runs along a path while lighting elements along the path. Each element along the path can be lit in a different color. One of the colors represents hours one represents minutes and the other represents seconds. Values which are lit continually change as times change, but this allows an artistic display of time. 1. A clock comprising:a series of lighting elements arranged along a path;a driver for the lighting elements; anda computing device which keeps track of a current time, the computing device operating the driver for the lighting elements to change the lighting elements which are illuminated along the path based on the time,where the computing device operates the driver to light a first element at a first location along the path representing minutes of the current time, and to light a second element at a second location along the path based on hours of the current time.2. The clock as in claim 1 , wherein the lighting elements are along a single continuous path.3. The clock as in claim 2 , wherein each of the lighting elements are energized to display in multiple colors claim 2 , with a first color representing hours claim 2 , and a second color representing minutes.4. The clock as in claim 3 , further comprising each of the lighting elements being displaying in a third color representing seconds claim 3 , and where there are 60 of the lighting elements.5. The clock as in claim 4 , wherein the display of the third color representing seconds changes once a second claim 4 , the display of the second color representing minutes changes once a minute claim 4 , and the display of the first color representing hours changes once every 12 minutes.6. The clock as in claim 3 , where the computing device includes switches which control setting a current time claim 3 , and a timekeeping device which monitors elapsed time claim 3 , and changes which of the lighting devices are illuminated claim 3 , in respective colors claim 3 , based on starting at the current ...

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Номер записи: 92
25-12-2014 дата публикации

Detecting Full-System Idle State In Adaptive-Tick Kernels

Номер: US20140380084A1
Автор: McKenney Paul E.
Принадлежит:

A technique for detecting full-system idle state in an adaptive-tick kernel includes detecting non-timekeeping CPU idle state, initiating a hysteresis period, waiting for the hysteresis period to end, manipulating a data structure whose state indicates whether a scheduling clock tick may be disabled on all CPUs, and disabling the scheduling clock tick if the data structure is in an appropriate state. In a first embodiment, non-timekeeping CPUs manipulate a global counter when entering an idle state, but add hysteresis to avoid thrashing the counter. Timekeeping is turned off based on the count maintained on the global counter. In a second embodiment, a Read-Copy Update (RCU) dynticks-idle subsystem running on a timekeeping CPU manipulates a global state variable whose states indicate whether all non-timekeeping CPUs are in an idle state, and if so, for how long. Timekeeping is turned off based on the state of the global state variable. 1. In a computer system having plural CPUs , including a timekeeping CPU and one or more non-timekeeping CPUs , operatively coupled to one or more memory devices , said system running an adaptive tick kernel , a method for detecting full-system idle state in said adaptive-tick kernel , comprising detecting a non-timekeeping CPU idle state , initiating a hysteresis period , waiting for said hysteresis period to end , manipulating a data structure whose state indicates whether a scheduling clock tick may be disabled on all of said CPUs , and disabling said scheduling clock tick on all of said CPUs if said data structure is determined to be in an appropriate state.2. The method of claim 1 , wherein:said detecting a non-timekeeping CPU idle state comprises each non-timekeeping CPU detecting it is ready to enter an idle state;said initiating a hysteresis period comprises each non-timekeeping CPU setting a timer, then entering said idle state;said waiting for said hysteresis period to end comprises each non-timekeeping CPU remaining in said ...

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Номер записи: 93
10-09-2020 дата публикации

METHOD FOR AUTOMATICALLY TESTING PROCESSOR

Номер: US20200284838A1
Автор: Wang Yong, Zeng Tao
Принадлежит:

The present invention relates to processor testing technology, specifically relating to a method for automatically testing a processor, the method comprising: S, carrying out test preparation; S, setting an operation voltage and a clock frequency of a processor to be tested; S, carrying out load testing at the current operation voltage and clock frequency; S, determining whether the processor is normal during current load testing; if yes, then turning to step S; if no, then raising the current operation voltage by a first growth value and returning to step S; and S, recording an operation voltage, subject to load testing, which corresponds to the current clock frequency as a test result and determining whether the current clock frequency reaches an upper limit; if yes, then ending the operation; if no, then raising the current clock frequency by a second growth value and returning to step S. The described method is capable of implementing the automatic testing of processors and rapidly and effectively obtaining operation voltages corresponding to clock frequencies when the processors are operating normally, and is thus suitable for a plurality of platforms. 1. A method for automatically testing a processor , the method comprising:{'b': '1', 'step S, carrying out test preparation;'}{'b': '2', 'step S, setting an operation voltage and a clock frequency of a processor to be tested;'}{'b': '3', 'step S, carrying out load testing at the current operation voltage and clock frequency;'}{'b': '4', 'step S, determining whether the processor is normal during current load testing;'}{'b': 5', '2, 'if yes, then turning to step S; if no, then raising the current operation voltage by a first growth value and returning to step S; and'}{'b': '5', 'step S, recording an operation voltage, subject to load testing, which corresponds to the current clock frequency as a test result and determining whether the current clock frequency reaches an upper limit;'}{'b': '2', 'if yes, then ending ...

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Номер записи: 94
17-09-2020 дата публикации

Device Clock Setting While Booting a Device

Номер: US20200293083A1
Автор: LaCroix Dennis R.
Принадлежит:

A computing device may perform a method that includes determining whether internal time reference data is available while booting the computing device. When the internal time reference data is unavailable, the device clock is set to a default time setting. However, when the internal time reference data is available while booting the computing device, the method includes searching the internal time reference data for a most recent time reference, and setting the device clock to a current time setting based on the most recent time reference.

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Номер записи: 95
08-11-2018 дата публикации

Timestamp Alignment Across a Plurality Of Computing Devices

Номер: US20180321706A1
Автор: Brown Gary Peter
Принадлежит:

Methods, systems, and computer program products are included for aligning timestamps of activities. A method includes receiving a first entry from a first server, the first entry corresponding to an activity, wherein the first entry includes a first timestamp corresponding to the activity. The method further includes receiving a second entry from a second serve, the second entry including a second entry corresponding to the activity, wherein the second entry includes a second timestamp corresponding to the activity. The method further includes determining an aligned timestamp of the activity by adjusting the first timestamp or the second timestamp by an offset. 1. A computer-implemented method , the method comprising:receiving a first entry from a first server, the first entry corresponding to an activity, wherein the first entry includes a first timestamp corresponding to the activity;receiving a second entry from a second server, the second entry including a second entry corresponding to the activity, wherein the second entry includes a second timestamp corresponding to the activity; anddetermining an aligned timestamp of the activity by adjusting the first timestamp or the second timestamp by an offset.2. The computer-implemented method of claim 1 , wherein the adjusting includes incrementing the first timestamp by the offset.3. The computer-implemented method of claim 1 , further comprising a first time duration corresponding to a first activity and a second time duration corresponding to a second activity claim 1 , and wherein the offset is equal to one-half of a difference between the first time duration and the second time duration.4. The computer-implemented method of claim 1 , the method further comprising:querying a data store that includes one or more offsets, wherein an input of the query includes a first server identifier corresponding to the first server and a second server identifier corresponding to the second server.5. The computer-implemented ...

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Номер записи: 96
08-11-2018 дата публикации

VALIDATION OF CLOCK TO PROVIDE SECURITY FOR TIME LOCKED DATA

Номер: US20180322071A1
Автор: Borlick Matthew G., GUPTA Lokesh M.
Принадлежит:

A computational device receives an input/output (I/O) operation directed to a data set. In response to determining that there is a time lock on the data set, a determination is made as to whether a clock of the computational device is providing a correct time. In response to determining that the clock of the computational device is not providing the correct time, the I/O operation is restricted from accessing the data set. In response to determining that the clock of the computational device is providing the correct time, a determination is made from one or more time entries of the time lock whether to provide the I/O operation with access to the data set. 1. A method , comprising:receiving, by a computational device, an input/output (I/O) operation directed to a data set;in response to determining that there is a time lock on the data set, determining whether a clock of the computational device is providing a correct time;in response to determining that the clock of the computational device is not providing the correct time, restricting the I/O operation from accessing the data set; andin response to determining that the clock of the computational device is providing the correct time, determining from one or more time entries of the time lock whether to provide the I/O operation with access to the data set.2. The method of claim 1 , wherein the determining of whether the clock of the computational device is providing the correct time is performed by:comparing a time provided by the clock of the computational device and a time provided via a GPS receiver of the computational device.3. The method of claim 1 , wherein the determining of whether the clock of the computational device is providing the correct time is performed by:comparing a time provided by the clock of the computational device and a time provided via an atomic clock.4. The method of claim 1 , wherein the determining of whether the clock of the computational device is providing the correct time is ...

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Номер записи: 97
17-10-2019 дата публикации

IMPLEMENTATION METHOD AND APPARATUS OF TIMER

Номер: US20190317809A1
Автор: Hu LiHua, WANG MINGLIANG, YIN GUOCHAO, ZHU Ming
Принадлежит:

The present disclosure provides an implementation method and apparatus of timer, the method includes: determining a counting period of a hardware timer according to expiration time of a timer node expires first in a timer linked list; and when the counting period of the hardware timer is expired, traversing through the timer node in the timer linked list and updating the counting period of the hardware timer. The present disclosure provides a technical solution that can effectively reduce system power consumption and processor resource occupancy. 1. An implementation method of timer , comprising:determining a counting period of a hardware timer according to expiration time of a timer node expires first in a timer linked list; andwhen the counting period of the hardware timer is expired, traversing through the timer node in the timer linked list and updating the counting period of the hardware timer.2. The method according to claim 1 , wherein the updating the counting period of the hardware timer comprises:determining whether the timer linked list is empty and,if the timer linked list is empty, updating the counting period of the hardware timer with a maximum counting period of the hardware timer;if the timer linked list is not empty, obtaining the expiration time of the timer node expires first in the timer linked list and current system time;determining whether a time interval between the expiration time of the timer node expires first and the current system time is greater than the maximum counting period of the hardware timer and,if the time interval is greater than the maximum counting period of the hardware timer, updating the counting period of the hardware timer with the maximum counting period of the hardware timer;if the time interval is less than or equal to the maximum counting period of the hardware timer, updating the counting period of the hardware timer with the time interval.3. The method according to claim 1 , wherein each timer node in the timer ...

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Номер записи: 98
03-12-2015 дата публикации

APPARATUS MANAGEMENT DEVICE, CLOCK SPEED CONTROL METHOD, AND PROGRAM

Номер: US20150346763A1
Автор: Ishizaka Taichi, Ito Takahiro, Komiya Noriyuki, Kuroiwa Takeru, Suzuki Shigeki
Принадлежит: Mitsubishi Electric Corporation

An apparatus manager monitors and controls respective apparatus connected via a network. A learner learns load periods when a significant load is imposed on a processor, on the basis of a utilization condition of the processor, and stores load period information indicating the learned load periods in auxiliary storage. The clock speed controller references the load period information, and controls the operating clock speed of the processor to be a normal level clock speed if the current time is during a load period, and a low level clock speed if the current time is during a time period other than a load period. 1. An apparatus management device , equipped with a processor , configured to manage apparatus connected via a communication network according to a process by the processor , the apparatus management device comprising:a learner configured to learn, for attributes of a day, a load period when a significant load is imposed on the processor, from a utilization condition of the processor on a day having each attribute; anda clock speed controller configured to control an operating clock speed of the processor so that the operating clock speed of the processor during a time period other than the load period corresponding to an attribute of a current day is less than the operating clock speed of the processor during the load period corresponding to the attribute of the current day.2. The apparatus management device according to claim 1 , whereinthe learner learns the load period in a plurality of stages, on the basis of a level of magnitude of load imposed on the processor, andthe clock speed controller controls the operating clock speed of the processor to be an operating clock speed corresponding to a load period in each stage.3. The apparatus management device according to claim 1 , whereinthe learner learns the load period on the basis of a utilization of the processor.4. (canceled)5. A clock speed control method for controlling an operating clock speed of a ...

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Номер записи: 99
15-11-2018 дата публикации

Method of Actuator Navigation And Electronic Device Comprising An Actuation Navigator Function

Номер: US20180329370A1
Автор: Poguntke Felix
Принадлежит:

A method of setting/calibrating a feature or function in a setting/calibrating mode of an electronic device comprising at least one actuatable selector, wherein the setting/calibrating of the feature or function requires an actuation of the at least one selector, wherein the electronic device comprises at least one indicator hand coupled to an actuation mechanism that rotates the at least one indicator hand in at least one of a clockwise and counterclockwise direction, wherein the method comprises the steps of using the at least one indicator hand to indicate the actuatable selector for actuation; setting/calibrating the feature or function; and exiting the setting/calibration mode. An electronic device that carries out the foregoing method is also disclosed. 1. A method of setting/calibrating a feature or function in a setting/calibrating mode of an electronic device comprising at least one actuatable selector , wherein the setting/calibrating of the feature or function requires N selector actuations , wherein the electronic device comprises at least one indicator hand rotatable in at least one of a clockwise and counterclockwise direction , wherein the method comprises the steps of:setting/calibrating the feature or function by using the at least one indicator hand (N) time(s), wherein N≥2, to indicate an actuatable selector for actuation; andexiting the setting/calibration mode.2. The method as claimed in claim 1 , wherein the at least one indicator hand indicates the actuatable selector for actuation in a manner that is independent of an actuation sequence.3. The method as claimed in claim 2 , wherein the at least one indicator hand points to the actuatable selector for selecting.4. The method as claimed in claim 2 , wherein the at least one indicator hand indicates the actuatable selector for actuation by rotating in both a clockwise and counterclockwise direction proximate the selector for actuation.5. (canceled)6. (canceled)7. An electronic device comprising ...

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Номер записи: 100