Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год
Применить Всего найдено 31470. Отображено 100.
05-01-2012 дата публикации

Pre-Emptive Garbage Collection of Memory Blocks

Номер: US20120005405A1
Автор: Jianmin Huang, Neil David Hutchison, Shai Traister, Steven Sprouse, William Wu
Принадлежит: SanDisk Technologies LLC

A method and system pre-emptively perform garbage collection operations of a forced amount on update blocks in a memory device. The amount of garbage collection needed by a certain data write is monitored and adjusted to match the forced amount if necessary. Update blocks may be selected on the basis of their recent usage or the amount of garbage collection required. Another method and system may store control information about update blocks in a temporary storage area so that a greater number of update blocks are utilized. The sequential write performance measured by the Speed Class test may be optimized by using this method and system.

Подробнее
Номер записи: 1
05-01-2012 дата публикации

Garbage Collection of Memory Blocks Using Volatile Memory

Номер: US20120005406A1
Автор: Neil David Hutchison, Steven Sprouse
Принадлежит: SanDisk Technologies LLC

A method and system for performing garbage collection operations on update blocks in a memory device using volatile memory is disclosed. When performing a garbage collection operation, a first part of the data related to the garbage collection operation is written to a volatile memory in the memory device, and a second part of the data related to the garbage collection operation is written to a non-volatile memory in the memory device. The first part of the data that is written to the volatile memory (such as a random access memory) may comprise control information (such as mapping information of the logical addressable unit to a physical metablock). The second part of the data related to the garbage collection that is written to the non-volatile memory (such as a flash memory) may comprise the consolidated data in the update block.

Подробнее
Номер записи: 2
19-01-2012 дата публикации

Information Handling System with Processing System, Low-power Processing System and Shared Resources

Номер: US20120013795A1
Автор: Andrew T. Sultenfuss, Steven L. Belt
Принадлежит: Dell Products LP

An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.

Подробнее
Номер записи: 3
19-01-2012 дата публикации

Managing extended raid caches using counting bloom filters

Номер: US20120017041A1
Автор: Ross E. Zwisler
Принадлежит: LSI Corp

Contentual metadata of an extended cache is stored within the extended cache. The contentual metadata of the extended cache is approximated utilizing a counting Bloom filter. The counting Bloom filter is stored within a primary cache. Contentual metadata of the primary cache is stored within the primary cache. One of a data read or a data write is executed without accessing the contentual metadata of the extended cache stored within the extended cache.

Подробнее
Номер записи: 4
19-01-2012 дата публикации

Information Handling System Universal Memory Wear Leveling System and Method

Номер: US20120017052A1
Автор: William F. Sauber
Принадлежит: Individual

An information handling system universal memory architecture assigns memory blocks to information handling system functions, such as a persistent storage function and a working storage function, that have different relative rates of writes of information. The blocks are periodically analyzed for remaining memory life to reassign blocks to functions that result in wear leveling across the blocks. For example, blocks having relatively low life remaining that are assigned to functions having a relatively high number of writes have their function switched with blocks that have a relatively high life remaining that are assigned to functions having a relatively low number of writes. In addition, wear leveling performed within a block ensures even wear of the memory cells within the block.

Подробнее
Номер записи: 5
02-02-2012 дата публикации

Method, Mobile Terminal and Computer Program Product for Sharing Storage Device

Номер: US20120030433A1
Автор: Chunhui Sun, Fuliang Zhang, Jinmei Yang, Wenying Shan
Принадлежит: Lenovo Beijing Ltd

The invention discloses a method of sharing a storage device and a mobile terminal. The mobile terminal comprises a first processor, a second processor and a readable and writable nonvolatile storage device. A processing capacity of the first processor is different from that of the second processor. A state in which the first processor is operating and using the storage device is a second state. A state in which the second processor is operating and using the storage device is a third state. The method comprising: the first processor receiving a switch instruction; the first processor controlling the storage device to enter the second state or the third state according to the switch instruction. As compared with the prior art, by controlling the sharing of the storage device by the first processor, the invention reduces the elements in the mobile terminal and saves the hardware cost of the mobile terminal; moreover, the physical connection between the components in the mobile terminal is simple and easily controlled.

Подробнее
Номер записи: 6
02-02-2012 дата публикации

Electrical apparatus and power supply control method

Номер: US20120030491A1
Автор: Shigeharu Itou
Принадлежит: Kyocera Mita Corp

An electrical apparatus has a controller for switching between a normal power mode and power saving modes. A receiver receives instructions for a manipulation on the apparatus. A switch controller switches to a first power saving mode when no instruction for manipulation is received within a first standby time in the normal power mode, switches to a second and lower power saving mode when no instruction for manipulation is received and the time reaches a preset second standby time in the first power saving mode, switches to the normal power mode when an instruction for manipulation is received when the apparatus is in the first or second power saving mode, and switches to the second or a third power saving mode for supplying less power than the first power saving mode but more than the second when the time reaches the first standby time if a predetermined condition is satisfied.

Подробнее
Номер записи: 7
09-02-2012 дата публикации

Coordinated garbage collection for raid array of solid state disks

Номер: US20120036309A1
Автор: David A. Dillow, Feiyi Wang, Galen M. Shipman, Hakki S. Oral, Youngjae Kim
Принадлежит: UT Battelle LLC

An optimized redundant array of solid state devices may include an array of one or more optimized solid-state devices and a controller coupled to the solid-state devices for managing the solid-state devices. The controller may be configured to globally coordinate the garbage collection activities of each of said optimized solid-state devices, for instance, to minimize the degraded performance time and increase the optimal performance time of the entire array of devices.

Подробнее
Номер записи: 8
09-02-2012 дата публикации

Wear Leveling Technique for Storage Devices

Номер: US20120036312A1
Автор: Jonathan Haines, Timothy Feldman
Принадлежит: SEAGATE TECHNOLOGY LLC

A method for managing wear levels in a storage device having a plurality of data blocks, the method comprising moving data to data blocks having higher erasure counts based on a constraint on static wear levelness that tightens over at least a portion of the lives of the plurality of data blocks.

Подробнее
Номер записи: 9
09-02-2012 дата публикации

Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads

Номер: US20120036509A1
Автор: Chien-Chun Chou, Drew E. Wingard, Harutyun Aslanyan, Krishnan Srinivasan, Ruben Khazhakyan
Принадлежит: Sonics Inc

A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.

Подробнее
Номер записи: 10
01-03-2012 дата публикации

Memory device and operating method thereof

Номер: US20120054419A1
Автор: CHEN Xiu, LIANG Chen
Принадлежит: Via Technologies Inc

The invention provides a memory device. In one embodiment, the memory device comprises a flash memory, a memory, and a controller. The flash memory comprises a plurality of blocks for data storage. The memory stores an address mapping table recording relationships between logical addresses and physical addresses of the blocks therein. The controller divides the address mapping table stored in the memory to a plurality of mapping table units, updates relationships between the logical addresses and the physical addresses stored in the mapping table units, determines whether data access performed to the flash memory fulfills the conditions of a first specific requirement, and when the data access fulfills the conditions of the first requirement, the controller selects a target mapping table unit from the mapping table units, and stores the target mapping table unit and a corresponding time stamp as a mapping table unit data to the flash memory.

Подробнее
Номер записи: 11
01-03-2012 дата публикации

Method and apparatus for fuzzy stride prefetch

Номер: US20120054449A1
Автор: Shiliang Hu, Youfeng Wu
Принадлежит: Intel Corp

In one embodiment, the present invention includes a prefetching engine to detect when data access strides in a memory fall into a range, to compute a predicted next stride, to selectively prefetch a cache line using the predicted next stride, and to dynamically control prefetching. Other embodiments are also described and claimed.

Подробнее
Номер записи: 12
08-03-2012 дата публикации

Hybrid memory management

Номер: US20120059992A1
Автор: John Geldman, Martin Ragnar Furuhjelm, Michael Murray, William H. Radke
Принадлежит: Micron Technology Inc

Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.

Подробнее
Номер записи: 13
08-03-2012 дата публикации

Method for using bad blocks of flash memory

Номер: US20120060054A1
Автор: Junhong Weng, Yingtong Sun
Принадлежит: Nationz Technologies Inc

A method is provided for using bad blocks in flash memory. The method includes placing in a replacement area of the flash memory a special bad block that meets a “still usable” condition from the bad blocks of the flash memory. The method also includes receiving a use request for using the special bad block in the replacement area to store user data, writing the user data into the special bad block, and determining whether the user data is successfully written into the special bad block. Further, the method includes placing the special bad block back into the replacement area for a next use request when it is determined that the user data is not successfully written into the special bad block.

Подробнее
Номер записи: 14
15-03-2012 дата публикации

Scheduling of i/o writes in a storage environment

Номер: US20120066435A1
Автор: Bo Hong, Craig Harmer, Ethan MILLER, Feng Wang, John Colgrove, John Hayes
Принадлежит: Pure Storage Inc

A system and method for effectively scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency.

Подробнее
Номер записи: 15
15-03-2012 дата публикации

System and method of page buffer operation for memory devices

Номер: US20120066442A1
Автор: Hakjune Oh, Hong Beom Pyeon, Jin-Ki Kim
Принадлежит: Mosaid Technologies Inc

Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

Подробнее
Номер записи: 16
15-03-2012 дата публикации

Apparatus for detecting presence or absence of oscillation of clock signal

Номер: US20120066557A1
Автор: Kimiharu Eto
Принадлежит: Renesas Electronics Corp

A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit and output a notification signal, and a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal.

Подробнее
Номер записи: 17
22-03-2012 дата публикации

Selection of Units for Garbage Collection in Flash Memory

Номер: US20120072639A1
Автор: Mark Allen Gaertner, Ryan James Goss
Принадлежит: SEAGATE TECHNOLOGY LLC

A data structure is formed that references a garbage collection metric for each of a plurality of associated garbage collection units of a flash memory device. Each garbage collection metric is based on one or more device state characteristics of the associated garbage collection unit. In response to a threshold change in the one or more device state variables, a region of interest within the data structure is sorted based on the garbage collection metrics. One or more garbage collection units are selected for garbage collection operations from the sorted region of interest.

Подробнее
Номер записи: 18
29-03-2012 дата публикации

Nonvolatile semiconductor memory device with advanced multi-page program operation

Номер: US20120079173A1
Автор: Dong-Hyuk Chae, Young-Ho Lim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A nonvolatile semiconductor memory device includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks.

Подробнее
Номер записи: 19
05-04-2012 дата публикации

Circuit and method for determining memory access, cache controller, and electronic device

Номер: US20120084513A1
Автор: Kazuhiko Okada
Принадлежит: Fujitsu Semiconductor Ltd

A memory access determination circuit includes a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value based on the first reference value or the second reference value. A controller performs a cache determination based on an address that corresponds to the count value and outputs the control signal in accordance with the cache determination. A changing unit changes the second reference value in accordance with the cache determination.

Подробнее
Номер записи: 20
12-04-2012 дата публикации

Memory storage device, memory controller thereof, and method for automatically creating fill-file thereof

Номер: US20120089805A1
Автор: Sing-Chang Liu
Принадлежит: Phison Electronics Corp

A memory storage device, a memory controller thereof, and a method for automatically creating a fill-file thereof are provided. In the present method, a plurality of logical addresses is configured and grouped into a plurality of logical blocks to be mapped to physical blocks of a memory chip in the memory storage device. When a host system is powered on, whether the logical addresses have been formatted into a partition is determined. If the logical addresses have been formatted into a partition, whether a fill-file of a predetermined file capacity exists is determined. If the fill-file does not exist, data related to the fill-file is respectively filled into a file allocation table (FAT) and a root directory of the formatted partition when the host system reads the FAT and the root directory, so as to automatically create the fill-file.

Подробнее
Номер записи: 21
19-04-2012 дата публикации

Method, Apparatus, and System for Energy Efficiency and Energy Conservation Through Dynamic Management of Memory and Input/Output Subsystems

Номер: US20120095607A1
Автор: Avinash N. Ananthakrishnan, Eric C. Samson, Inder Sodhi, Joydeep Ray, Ryan D. Wells
Принадлежит: Ananthakrishnan Avinash N, Inder Sodhi, Joydeep Ray, Samson Eric C, Wells Ryan D

According to one embodiment of the invention, an integrated circuit device comprises an interconnect, at least one compute engine and a control unit. Coupled to the at least one compute engine via the interconnect, the control unit to analyze heuristic information from the at least one compute engine and to increase or decrease a bandwidth of the interconnect based on the heuristic information.

Подробнее
Номер записи: 22
19-04-2012 дата публикации

Power-cap settings

Номер: US20120096248A1
Автор: Clifford A. McCarthy
Принадлежит: Hewlett Packard Development Co LP

When the maximum power consumption of a computer exceeds a currently selected power-consumption cap, a cap setting corresponding to the currently selected power-consumption cap is reduced in addition, power-cap settings corresponding to power-consumption caps between said currently selected power-consumption cap and said maximum power consumption are reduced.

Подробнее
Номер записи: 23
19-04-2012 дата публикации

Data processing method and semiconductor integrated circuit

Номер: US20120096335A1
Автор: Nobuhiro Tsuboi, Tomohisa Sezaki, Tsukasa Takahashi, Yoshiteru Mino
Принадлежит: Panasonic Corp

A read process is performed on an ith designated block storing an ith divided data string. If the ith divided data string is not normally read, the read process is sequentially executed on ith ordinary blocks each storing the ith divided data string, where the ith ordinary blocks are included in ordinary block groups, respectively. When the ith divided data string is normally read, it is determined whether or not reading p divided data strings has been completed. If it is determined that the reading the p divided data strings has not been completed, the read process is performed on an (i+1)th designated block storing an (i+1)th divided data string following the ith divided data string.

Подробнее
Номер записи: 24
26-04-2012 дата публикации

Transitioning from mimo to siso to save power

Номер: US20120099497A1
Автор: Harish Vaidya, Manoj Raveendranath Kamath, Rakesh Raman
Принадлежит: Broadcom Corp

Various example embodiments are disclosed. According to an example embodiment, an apparatus may include at least one processor and at least one memory. The at least one memory may include computer-executable code that, when executed by the processor, is configured to cause the apparatus to send a message to a node in wireless communication with the apparatus, the message indicating a transition by the apparatus from multiple-input multiple-output (MIMO) to single-input single-output (SISO), and transition from wireless MIMO communication with the node to wireless SISO communication with the node after sending the message to the node.

Подробнее
Номер записи: 25
10-05-2012 дата публикации

Low power dual processor architecture for multi mode devices

Номер: US20120115456A1
Автор: Albert S. Ludwin, Ranganathan Krishnan, William R. Gardner
Принадлежит: Qualcomm Inc

A mobile computing device with multiple modes, for example, wireless communication and personal computing, has an application processor and a communication processor. In the computing mode, the application processor is the master processor. In the communication mode, the application processor is deenergized to conserve battery power, with the communication processor functioning as the master processor by accessing the device's peripheral bus using the memory interface of the communication processor.

Подробнее
Номер записи: 26
24-05-2012 дата публикации

Correlation-based instruction prefetching

Номер: US20120131311A1
Автор: Yuan C. Chou
Принадлежит: Oracle International Corp

The disclosed embodiments provide a system that facilitates prefetching an instruction cache line in a processor. During execution of the processor, the system performs a current instruction cache access which is directed to a current cache line. If the current instruction cache access causes a cache miss or is a first demand fetch for a previously prefetched cache line, the system determines whether the current instruction cache access is discontinuous with a preceding instruction cache access. If so, the system completes the current instruction cache access by performing a cache access to service the cache miss or the first demand fetch, and also prefetching a predicted cache line associated with a discontinuous instruction cache access which is predicted to follow the current instruction cache access.

Подробнее
Номер записи: 27
07-06-2012 дата публикации

Monitoring processes in a computer

Номер: US20120144028A1
Автор: Andrew Hawkins, Geoff Collins, Mark Blackburn
Принадлежит: 1E Ltd

A monitoring program is run on a computer to identify a process running on the computer, and, for the identified process, determine whether or not one or more predetermined characteristics of the process complies with respective reference characteristics. This allows the program to automatically distinguish whether the process is likely to be a productive process or a non-productive process. For each characteristic a certainty value is incremented or decremented depending on whether the characteristic complies with the reference characteristic. Examples of characteristics are the time pattern of running of a process and the use of hardware resources by the process. Other characteristics include receiving input from a user and connections to known IP addresses. The monitoring process may be used to control power consumption to detect and run non-productive processes in a low power state.

Подробнее
Номер записи: 28
07-06-2012 дата публикации

Dynamic adjustment of read/write ratio of a disk cache

Номер: US20120144109A1
Автор: Brian M. Rogers, Ganesh Balakrishnan, Gordon B. Bell, MVV Anil Krishna, Timothy H. Heil
Принадлежит: International Business Machines Corp

Embodiments of the invention are directed to optimizing the performance of a split disk cache. In one embodiment, a disk cache includes a primary region having a read portion and write portion and one or more smaller, sample regions also including a read portion and a write portion. The primary region and one or more sample region each have an independently adjustable ratio of a read portion to a write portion. Cached reads are distributed among the read portions of the primary and sample region, while cached writes are distributed among the write portions of the primary and sample region. The performance of the primary region and the performance of the sample region are tracked, such as by obtaining a hit rate for each region during a predefined interval. The read/write ratio of the primary region is then selectively adjusted according to the performance of the one or more sample regions.

Подробнее
Номер записи: 29
07-06-2012 дата публикации

Fast computer startup

Номер: US20120144177A1
Автор: Brian E. King, Emily N. Wilson, Kirsten V. Stark, Mehmet Iyigun, Neel Jain, Patrick L. Stemen, Sushu Zhang, Vasilios Karagounis, Yevgeniy Bak
Принадлежит: Microsoft Corp

Fast computer startup is provided by, upon receipt of a shutdown command, recording state information representing a target state. In this target state, the computing device may have closed all user sessions, such that no user state information is included in the target state. However, the operating system may still be executing. In response to a command to startup the computer, this target state may be quickly reestablished from the recorded target state information. Portions of a startup sequence may be performed to complete the startup process, including establishing user state. To protect user expectations despite changes in response to a shutdown command, creation and use of the file holding the recorded state information may be conditional on dynamically determined events. Also, user and programmatic interfaces may provide options to override creation or use of the recorded state information.

Подробнее
Номер записи: 30
14-06-2012 дата публикации

Method for operating flash memories on a bus

Номер: US20120151122A1
Автор: Ming-Hung Hsieh
Принадлежит: Individual

Enable a read command of a first flash memory. After the read command of the first flash memory is enabled, a ready/busy signal of the first flash memory enters a busy waiting time, and a read command of a second flash memory starts to be enabled. Start to read data of the first flash memory when the busy waiting time is over. Enable the read command of the first flash memory again upon completion of reading the data of the first flash memory. Start to read data of the second flash memory after the read command of the first flash memory is enabled again. And enable the read command of the second flash memory again upon completion of reading the data of the second flash.

Подробнее
Номер записи: 31
14-06-2012 дата публикации

Power-Saving Device for Universal Serial Bus Modem Apparatus and Method Thereof

Номер: US20120151239A1
Автор: Wei Wang
Принадлежит: ZTE Corp

A power-saving apparatus for universal serial bus (USB) modem equipment is disclosed in the present invention, which includes: a personal computer and USB Modem equipment. Accordingly, a power-saving method for USB Modem equipment is provided in the present invention, which includes: regularly detecting whether selective suspending is allowed, if not allowed, processing a received request from an application program, and if allowed, transmitting an instruction for entering the selective suspending state to the USB Modem equipment; after receiving the instruction for entering the selective suspending state, the USB Modem equipment entering the selective suspending state. Thus, the present invention can realize that the USB Modem equipment enters the power-saving state in the idle period and resumes the work state when receiving a service request.

Подробнее
Номер записи: 32
21-06-2012 дата публикации

Protecting Data During Different Connectivity States

Номер: US20120159078A1
Автор: Apurva Ashwin Doshi, Bohdan W. Raciborski, Grigory Borisovich Lyakhovitskiy
Принадлежит: Microsoft Corp

Aspects of the subject matter described herein relate to data protection. In aspects, during a backup cycle, backup copies may be created for files that are new or that have changed since the last backup. If external backup storage is not available, the backup copies may be stored in a cache located on the primary storage. If backup storage is available, the backup copies may be stored in the backup storage device and backup copies that were previously stored in the primary storage may be copied to the backup storage. The availability of the backup storage may be detected and used to seamlessly switch between backing up files locally and remotely as availability of the backup storage changes.

Подробнее
Номер записи: 33
05-07-2012 дата публикации

Solid state drive with low write amplification

Номер: US20120173795A1
Автор: Anthony Leach, Franz Michael Schuette
Принадлежит: OCZ Technology Group Inc

A solid state drive having a non-volatile memory device and methods of operating the solid state drive to compare existing data stored on the memory device to subsequent data in an incoming data stream received by the solid state drive from a host system. If matching data are found, the solid state drive uses the existing data instead of writing the subsequent data to the memory device. Common data patterns can be shared among different files stored on the memory device.

Подробнее
Номер записи: 34
05-07-2012 дата публикации

Flash memory storage system

Номер: US20120173802A1
Автор: Kazuhisa Fujimoto, Shunji Kawamura, Takashige Iwamura, Yoshiaki Eguchi
Принадлежит: Individual

A flash memory storage system has a plurality of flash memory devices comprising a plurality of flash memories, and a controller having an I/O processing control unit for accessing a flash memory device specified by a designated access destination in an I/O request received from an external device from among the plurality of flash memory devices. A parity group can be configured of flash memory devices having identical internal configuration.

Подробнее
Номер записи: 35
12-07-2012 дата публикации

Mobile information apparatus and display control method

Номер: US20120176353A1
Автор: Junichi Ishii
Принадлежит: NEC Corp

Multiple displays are arranged such that their display surfaces are arrayed side by side. A measurement section measures orientation information about apparatus orientation. A control section determines the display surface a user is viewing from among multiple displays, based on the orientation information measured by the measurement section. The control section causes the display surface of displays, other than the display surface determined as being viewed by the user, to become darker than the display surface of the display determined as being viewed by the user.

Подробнее
Номер записи: 36
12-07-2012 дата публикации

Method and system for dynamic templatized query language in software

Номер: US20120179720A1
Автор: Christopher J. Kasten, Greg Seitz
Принадлежит: eBay Inc

A system to automatically generate query language in software is described. The system receives a request for data that is persistently stored in a database. The system selects a predefined query template from a number of query templates based on the request. The system utilizes the query template to receive content from at least one different source, the first source being a prototype data object. The system generates a query statement based on the query template that includes the content. Finally the system queries the database using the query statement to retrieve the requested data.

Подробнее
Номер записи: 37
19-07-2012 дата публикации

Method and system for cache endurance management

Номер: US20120185638A1
Автор: Daniel Schreiber, Judah Gamliel Hahn, Robert K. KHEDOURI
Принадлежит: Sandisk IL Ltd

A system and method for cache endurance management is disclosed. The method may include the steps of querying a storage device with a host to acquire information relevant to a predicted remaining lifetime of the storage device, determining a download policy modification for the host in view of the predicted remaining lifetime of the storage device and updating the download policy database of a download manager in accordance with the determined download policy modification.

Подробнее
Номер записи: 38
19-07-2012 дата публикации

Distributed Storage Service Systems and Architecture

Номер: US20120185641A1
Автор: Alain Nochimowski, Itzhak Pomerantz, Micha Rave
Принадлежит: Sandisk IL Ltd

Various methods, devices and systems are described for providing distributed storage services. A data storage device is capable of initiating a communication session with an external entity such as a local host computer (and vice versa) coupled directly to the data storage device, a remote server computer, or directly with remote data storage devices with or without intervention by a local host computer.

Подробнее
Номер записи: 39
26-07-2012 дата публикации

Storage apparatus and method of managing data storage area

Номер: US20120191903A1
Автор: Akihiko Araki, Sadahiro Sugimoto, Yoshiki Kano, Yusuke Nonaka
Принадлежит: Individual

To extend endurance and reduce bit cost, a storage apparatus includes a controller and a first storage device and a second storage device having a smaller erase count upper limit than the first storage device. Area conversion information includes correspondence of a first address of a data storage destination and a second address of a data storage area The controller selects an area corresponding to the first address, determines whether a rewrite frequency of the selected area is equal to or larger than a first threshold and, when the rewrite frequency is equal to or larger than the threshold, selects an area of the first storage device, and, when the rewrite frequency is smaller than the threshold, selects an area of the second storage device and maps the address of the selected area to the first address.

Подробнее
Номер записи: 40
26-07-2012 дата публикации

Just in time garbage collection

Номер: US20120191936A1
Автор: David S. Ebsen, Ryan J. Goss
Принадлежит: SEAGATE TECHNOLOGY LLC

The disclosure is related to systems and methods of managing a memory. In a particular embodiment, a memory is disclosed that includes multiple garbage collection units. The memory also includes a controller that determines whether to select a garbage collection unit of the multiple garbage collection units for garbage collection based on a variable threshold number of the multiple garbage collection units to garbage collect.

Подробнее
Номер записи: 41
26-07-2012 дата публикации

Garbage collection management in memories

Номер: US20120191937A1
Автор: Jonathan W. Haines, Timothy R. Feldman, Wayne H. Vinson
Принадлежит: SEAGATE TECHNOLOGY LLC

The disclosure is related to systems and methods of managing a memory. In a particular embodiment, a memory channel is disclosed that includes multiple memory units, with each memory unit comprising multiple garbage collection units. The memory channel also includes a controller that is communicatively coupled to the multiple memory units. The controller selects a memory unit of the multiple memory units for garbage collection based on a calculated number of memory units, of the multiple memory units, to garbage collect.

Подробнее
Номер записи: 42
02-08-2012 дата публикации

Binary Rewriting in Software Instruction Cache

Номер: US20120198169A1
Автор: Brad W. Michael, Brian Flachs, John K.P. O'Brien, Kathryn M. O'Brien, Mark R. Nutter, Tao Zhang, Tong Chen
Принадлежит: International Business Machines Corp

Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.

Подробнее
Номер записи: 43
02-08-2012 дата публикации

Controlling power sequence in a blade center environment

Номер: US20120198261A1
Автор: Deanna Lynn Quigg Brown, II Ronald Ivan Olguin, Jason James Graves, Kevan D. Holdaway, Nhu Thanh Nguyen
Принадлежит: International Business Machines Corp

For controlling power sequence in a blade center environment, a relationship component module creates a topology of interdependent relationships of devices in the blade center environment. The devices include server blades, storage blades, and switch modules. A sequence module defines a sequence of the devices in the blade center environment to power off and on based on the topology of interdependent relationships. The sequence includes an order of a first independent blade server, each dependent storage blade of the first independent blade server, and a second independent blade server. A monitor component module monitors a command from an Advanced Management Module (AMM) to regulate power for the devices in the blade center environment. The AMM regulates power within the blade center. A validation module validates that the command does not violate the interdependent relationships and the sequence of devices or else blocks the command if the command is not validated.

Подробнее
Номер записи: 44
09-08-2012 дата публикации

Storage control system with change logging mechanism and method of operation thereof

Номер: US20120203958A1
Автор: Joseph Taylor, Robert W. Ellis, Ryan Jones
Принадлежит: Smart Storage Systems Inc

A method of operation of a storage control system including: providing a memory controller; accessing a volatile memory table by the memory controller; writing a non-volatile semiconductor memory for persisting changes in the volatile memory table; and restoring a logical-to-physical table in the volatile memory table, after a power cycle, by restoring a random access memory with a logical-to-physical partition from a most recently used list.

Подробнее
Номер записи: 45
09-08-2012 дата публикации

Apparatus and methods for processor power supply voltage control using processor feedback

Номер: US20120204047A1
Автор: Jae Kwan Ryoo
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Methods of operating an integrated circuit include determining a difference between a reference level and a level of a power supply voltage at a processor circuit of the integrated circuit, generating a digital code responsive to the determined difference and transmitting the digital code to a power management integrated circuit that provides power to the integrated circuit. The power management integrated circuit may adjust the power supply voltage responsive to the transmitted code. Integrated circuits and data processing systems are also provided.

Подробнее
Номер записи: 46
09-08-2012 дата публикации

Management apparatus and program

Номер: US20120204050A1
Автор: Hidekazu Miyoshi, Takashi Yano, Takeshi Ozaki
Принадлежит: Sumitomo Electric Industries Ltd

Power consumption of a communication apparatus having a plurality of operating modes can be accurately determined. A management apparatus 4 manages a communication apparatus 3 having a plurality of operating modes, and includes an obtaining unit 421 that obtains information about power consumption of the communication apparatus 3 ; a mode identifying unit 422 that identifies an operating mode of the communication apparatus 3 ; and a power managing unit 424 that determines power consumption in each operating mode of the communication apparatus 3 by associating information about power consumption (signals S 21 ) obtained by the obtaining unit 421 with operating modes (signals S 23 ) identified by the mode identifying unit 422.

Подробнее
Номер записи: 47
16-08-2012 дата публикации

Energy-saving apparatus using computer user information, and energy-saving method using same

Номер: US20120210148A1
Автор: Hae-Yong Choi
Принадлежит: Individual

Provided are an energy-saving apparatus using computer user information and an energy-saving method using same. In detail, in order to minimize power consumption of a computer by automatically switching a power mode of the computer to an energy-saving mode according to whether the computer recognizes the computer user information, the energy-saving apparatus includes: a signal generation unit which stores and transmits the computer user information; an information transceiving unit which receives the computer user information from the signal generation unit; a storage space for storing user authentication information; a comparison unit which compares the computer user information received from the signal generation unit with the user authentication information stored in the storage space to determine whether or not the computer user information and the user authentication information match each other; and a mode switching unit which switches the power mode of the computer into the energy-saving mode according to a result of the determination of the comparison unit.

Подробнее
Номер записи: 48
23-08-2012 дата публикации

Control apparatus for controlling data reading and writing to flash memory

Номер: US20120215968A1
Автор: Nobuya Uematsu, Tsuneo Yamamoto
Принадлежит: Denso Corp

To record data in a flash memory, upon detecting that a current destination memory block is full, a control apparatus records data in a destination memory block one block by one block, with “in-advance” data erasure of the next memory block and by determining if data erasure of the next memory block is successful. When data erasure of the next memory block fails, such memory block is designated as broken, and such memory block is excluded from a group of blocks to be used as recording destination. After determining the data erasure result of a yet-next memory block is successful, the required data is copied to the yet-next memory block. Therefore, even when one of the blocks is broken, a sequential data recording in the flash memory is performed without increasing the number of data copy operations between blocks.

Подробнее
Номер записи: 49
30-08-2012 дата публикации

Sub-lun input/output profiling for ssd devices

Номер: US20120221778A1
Автор: David Montgomery, II Paul A. Jennas, Jason L. Peipelman, Joshua M. Rhoades, Larry Juarez, Philip M. Doatmas, Todd C. Sorenson
Принадлежит: International Business Machines Corp

A read/write ratio for each of a plurality of data segments classified in a hot category as hot data segments is determined. Each of the plurality of hot data segments is ordered by the read/write ratio in a descending order. Each of a plurality of available SSD devices is ordered by a remaining life expectancy in an ascending order. Those of the plurality of hot data segments are matched with those of the plurality of hot data segments with those of the plurality of available SSD devices such that a hot data segment having a higher read/write ratio is provided to an SSD device having a smaller remaining life expectancy than another hot data segment having a lower read/write ratio.

Подробнее
Номер записи: 50
30-08-2012 дата публикации

Memory controller and methods for enhancing write performance of a flash device

Номер: US20120221784A1
Автор: Amir Ban
Принадлежит: Individual

A memory controller and methods for managing efficient writing to a flash memory are presented. Fresh data is written to at least one block of the flash memory. During a space reclamation process, other data, previously written to the flash memory, is relocated to at least one other block of the flash memory, such that the fresh data and the relocated data always are maintained in separate blocks of the flash memory. During writing, an update frequency level is selected for the fresh data from among multiple update frequency levels and the fresh data is written to a block that is associated with the selected update frequency level. During space reclamation, a plurality of blocks, space of which is to be reclaimed, is selected and the valid pages thereof are copied to at least one destination block.

Подробнее
Номер записи: 51
06-09-2012 дата публикации

Logical address translation

Номер: US20120226887A1
Автор: Martin L. Culley, Troy A. Manning, Troy D. Larsen
Принадлежит: Micron Technology Inc

The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.

Подробнее
Номер записи: 52
13-09-2012 дата публикации

Power supply and control method thereof

Номер: US20120233474A1
Автор: Tetsuki IWATA
Принадлежит: Sanken Electric Co Ltd

A first power supply is configured to feed power to a computer. The power supply includes a virtual machine management unit configured to transmit an instruction to any one of a second virtual host that is executed on the computer and a fourth virtual machine that is run in the second virtual host. Here, the fourth virtual machine is configured to control a virtualization management system including virtual hosts different from the second virtual host.

Подробнее
Номер записи: 53
20-09-2012 дата публикации

Flash storage device with read disturb mitigation

Номер: US20120239990A1
Автор: Mark Moshayedi, Po-Jen Hsueh, Richard A. Mataya
Принадлежит: Stec Inc

A method for managing a flash storage device includes initiating a read request and reading requested data from a first storage block of a plurality of storage blocks in the flash storage device based on the read request. The method further includes incrementing a read count for the first storage block and moving the data in the first storage block to an available storage block of the plurality of storage blocks when the read count reaches a first threshold value.

Подробнее
Номер записи: 54
27-09-2012 дата публикации

Data processing apparatus and data processing method

Номер: US20120246360A1
Автор: Akira Ueno, Masami Shimamura, Ryusuke Tsuchida, Takashi Yanada, Tomoyuki Sengoku, Yoshinobu Tanaka
Принадлежит: Olympus Corp

A data processing apparatus may include a data conversion unit for, when converting a plurality of sequentially input data into conversion data of the same bit number as a data bus having a prescribed bit number and sequentially transferring the conversion data, arranging the input data in each conversion unit using the conversion data as one transfer unit and a prescribed number of transfer units as one conversion unit. The data conversion unit may include a first data generation unit, a second data generation unit for generating second data obtained by allocating a prescribed second number of input data in the input data not allocated to the first data, to the second bit range and a data coupling unit for coupling the first data and the second data to generate the conversion data having the bit number of the bus width of the data bus.

Подробнее
Номер записи: 55
27-09-2012 дата публикации

Memory system with interleaved addressing method

Номер: US20120246395A1
Автор: Eun Chu Oh, Hong Rak Son, Kyoung Lae Cho
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Disclosed is a memory system which includes a nonvolatile memory device including a memory cell array having a plurality of word lines including a first set of word lines storing first data having a high bit error rate, and a second set of word lines storing second data having low bit error rate less than the high bit error rate, and a memory controller that during a program operation maps logical addresses for a portion of the first data and a portion of the second data onto a selected word line selected from the plurality of word lines.

Подробнее
Номер записи: 56
27-09-2012 дата публикации

Storage Device and Memory Controller

Номер: US20120246399A1
Автор: Koji Matsuda, Masahiro Shiraishi, Masataka Nishi, Ryo Fujita, Ryoichi Inada, Takuma Nishimura
Принадлежит: HITACHI LTD

Disclosed is a storage device using non-volatile semiconductor memory that achieves high performance and long life for the device. When managing the non-volatile semiconductor memory ( 2 ), physical blocks are classified into three types: scratch blocks ( 22 ), data blocks ( 23 ), and erased blocks ( 24 ). Data writing from a host device ( 3 ) is performed on the scratch blocks. When the number of empty pages within a scratch block becomes less than a predetermined number or no longer exists, the block is treated thereafter as a data block, and one of the erased blocks is newly assigned as a scratch block. If there are insufficient erased blocks, a block with relatively less valid data is selected from among the data blocks. After copying all valid data included in the block to a scratch block, the block is erased, and thus an erased block is acquired.

Подробнее
Номер записи: 57
27-09-2012 дата публикации

Data merging method for non-volatile memory and controller and storage apparatus using the same

Номер: US20120246415A1
Автор: Wei-Chen Teo
Принадлежит: Phison Electronics Corp

A data merging method for merging data belonging to a first logical block in a rewritable non-volatile memory module is provided. The method includes getting a second physical block from a free area of the rewritable non-volatile memory module and determining whether a valid logical page number is smaller than a predetermined number. The method also includes, when the valid logical page number is smaller than the predetermined number, storing a corresponding page mapping table in a start physical page of the second physical block and writing at least one valid page data belonging to the first logical block into at least one physical page of the second physical block. Accordingly, the method can effectively shorten the time for merging data.

Подробнее
Номер записи: 58
04-10-2012 дата публикации

Extending Cache for an External Storage System into Individual Servers

Номер: US20120254509A1
Автор: Andrew D. Walls, John C. Elliott, Lee D. Cleveland, Yu-Cheng Hsu
Принадлежит: International Business Machines Corp

Mechanisms are provided for extending cache for an external storage system into individual servers. Certain servers may have cards with cache in the form of dynamic random access memory (DRAM) and non-volatile storage, such as flash memory or solid-state drives (SSDs), which may be viewed as actual extensions of the external storage system. In this way, the storage system is distributed across the storage area network (SAN) into various servers. Several new semantics are used in communication between the cards and the storage system to keep the read caches coherent.

Подробнее
Номер записи: 59
04-10-2012 дата публикации

Cache memory allocation process based on tcpip network and/or storage area network array parameters

Номер: US20120254533A1
Автор: Himanshu Dwivedi, Madhukar Gunjan Chakhaiyar, Mahmoud K. Jibbe
Принадлежит: LSI Corp

An apparatus comprising a controller, one or more host devices and one or more storage devices. The controller may be configured to store and/or retrieve data in response to one or more input/output requests. The one or more host devices may be configured to present the input/output requests. The one or more storage devices may be configured to store and/or retrieve the data. The controller may include a cache memory configured to store the input/output requests. The cache memory may be configured as a memory allocation table to store and/or retrieve a compressed version of a portion of the data in response to one or more network parameters. The compressed version may be retrieved from the memory allocation table instead of the storage devices based on the input/output requests to improve overall storage throughput.

Подробнее
Номер записи: 60
04-10-2012 дата публикации

Non-Volatile Memory System Allowing Reverse Eviction of Data Updates to Non-Volatile Binary Cache

Номер: US20120254549A1
Автор: Neil David Hutchison, Robert George Young
Принадлежит: SanDisk Technologies LLC

A non-volatile memory system includes a memory section having a non-volatile cache portion storing data in a binary format, a primary user data storage section that stores user data in multi-state format, and an update memory area where the memory system stores data updating user data previously stored in the primary user data. The memory system allows a maximum number of blocks for use in the update memory area. When the memory system receives updated data corresponding to user data already written into the primary user data storage section, it determines whether a block of memory is available in the update memory area. In response to determining that a block of memory is not available in the update memory area, the system determines a block of the update memory to remove from the update memory; copies the data content of the determined update block into the cache portion of the memory section; and subsequently writes the updated data into the update memory.

Подробнее
Номер записи: 61
04-10-2012 дата публикации

Mode of Operation of a Portable Device

Номер: US20120254631A1
Автор: Eric Liu, Karl Townsend, Manjirnath Chatterjee, Nathaniel Wolf, Peter Nils Skillman
Принадлежит: Hewlett Packard Development Co LP

A portable device to determine whether a user is holding the portable device, launch a mode of operation of the portable device if the user is holding the portable device, and modify an amount of power supplied to a component of the portable device based on the mode of operation.

Подробнее
Номер записи: 62
11-10-2012 дата публикации

Load multiple and store multiple instructions in a microprocessor that emulates banked registers

Номер: US20120260042A1
Автор: G. Glenn Henry, Rodney E. Hooker, Terry Parks
Принадлежит: Via Technologies Inc

A microprocessor supports an instruction set architecture that specifies: processor modes, architectural registers associated with each mode, and a load multiple instruction that instructs the microprocessor to load data from memory into specified ones of the registers. Direct storage holds data associated with a first portion of the registers and is coupled to an execution unit to provide the data thereto. Indirect storage holds data associated with a second portion of the registers and cannot directly provide the data to the execution unit. Which architectural registers are in the first and second portions varies dynamically based upon the current processor mode. If a specified register is currently in the first portion, the microprocessor loads data from memory into the direct storage, whereas if in the second portion, the microprocessor loads data from memory into the direct storage and then stores the data from the direct storage to the indirect storage.

Подробнее
Номер записи: 63
25-10-2012 дата публикации

Execution of signal processing tasks

Номер: US20120271478A1
Автор: Florin Tatar, Frank de Wit
Принадлежит: SKF AB

An apparatus has a signal processing system for executing a plurality of pre-determined signal processing tasks, and an energy source for powering the signal processing system in operational use of the apparatus. The energy source supplies an amount of energy that varies over the service life of the energy source. The signal processing system determines an amount of energy available from the energy source and selects for execution a specific one of the pre-determined signal processing tasks in dependence on the amount determined.

Подробнее
Номер записи: 64
01-11-2012 дата публикации

Semiconductor storage apparatus and method for controlling semiconductor storage apparatus

Номер: US20120278533A1
Автор: Akifumi Suzuki, Takashi Tsunehiro
Принадлежит: HITACHI LTD

A reliability maintained period is calculated for each storage area based on the degree of deterioration and read frequency for each storage area of a flash memory, and refresh is executed on each storage area in a planned manner based on the calculated reliability maintained period. A semiconductor storage apparatus 100 A is configured so that flash memories 120 to 128 and a memory controller 110 are connected and the flash memories 120 to 128 include a plurality of blocks as storage areas; and the memory controller 110 manages the degree of deterioration and read frequency of the blocks for each of the plurality of blocks, obtains a reliability maintained period of data stored in the block based on the managed degree of deterioration and read frequency of the block, and executes refresh for correcting failure bits of the relevant data by newly storing the data stored in the block in another block based on the obtained reliability maintained period.

Подробнее
Номер записи: 65
08-11-2012 дата публикации

Memory system and bad block management method

Номер: US20120284469A1
Автор: Dong-young Seo
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Disclosed is a bad block management method of a memory system that includes virtual blocks having a plurality of units and at least one reserved block. The bad block management method includes mapping the virtual blocks and the at least one reserved block onto one physical block in the plurality of physical blocks, determining that a first virtual block in the virtual blocks includes a bad virtual block unit, and replacing the bad virtual block unit in the first virtual block with a first reserved block unit selected from the reserved block units.

Подробнее
Номер записи: 66
29-11-2012 дата публикации

Managing unmodified tracks maintained in both a first cache and a second cache

Номер: US20120303898A1
Автор: Kenneth W. Todd, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos, Michael T. Benhase
Принадлежит: International Business Machines Corp

Provided are a computer program product, system, and method for managing unmodified tracks maintained in both a first cache and a second cache. The first cache has unmodified tracks in the storage subject to Input/Output (I/O) requests. Unmodified tracks are demoted from the first cache to a second cache. An inclusive list indicates unmodified tracks maintained in both the first cache and a second cache. An exclusive list indicates unmodified tracks maintained in the second cache but not the first cache. The inclusive list and the exclusive list are used to determine whether to promote to the second cache an unmodified track demoted from the first cache.

Подробнее
Номер записи: 67
06-12-2012 дата публикации

Pre-organization of Data

Номер: US20120311000A1
Автор: Benjamin H. Nham, Daniel E. Crosby, Daniel Jeffrey Post, David Michael Chan, Erik C. NEUENSCHWANDER, Ken Herman
Принадлежит: Apple Inc

In a method of writing data to a file system on a solid state drive, a file stream is opened for writing to a file in the file system. A life expectancy value predicting a length of time the data to be written will be stored in the file system is attached to the file stream. The data is written to the file stream and stored on the solid state storage device according to the life expectancy value attached to the data. In one embodiment, a unique identifier may be used as the life expectancy value for writing a group of related files predicted to be stored in the file system for substantially the same length of time. The life expectancy value may be predicted based on a file type of the file being written. The life expectancy value may be stored as metadata for the file being written.

Подробнее
Номер записи: 68
06-12-2012 дата публикации

Apparatus including memory system controllers and related methods

Номер: US20120311232A1
Автор: Kent A. Porterfield
Принадлежит: Micron Technology Inc

Memory controllers can include a switch and non-volatile memory control circuitry including channel control circuits coupled to the switch. The channel control circuits can coupled to logical units including blocks. Volatile memory and memory management circuitry including local memory can be coupled to the switch. The memory management circuitry can be configured to store health and status information for each of the blocks in a block table in the volatile memory, store a candidate block table that identifies a candidate block for a particular operation based on criteria in the local memory, update the health and status information for a particular block in the block table, compare the updated health and status information for the particular block with the candidate block according to the criteria, and update the candidate block table to identify the particular block in response to the comparison indicating that the particular block better satisfies the criteria.

Подробнее
Номер записи: 69
06-12-2012 дата публикации

System and method for managing a non-volatile memory

Номер: US20120311233A1
Автор: Hanan Weingarten, Michael KATZ
Принадлежит: Densbits Technologies Ltd

A method, computer readable medium storing instructions and system for managing flash memory. Data sector are received and each is written into a data block of a buffer of a non-volatile memory device. Pointers in a data management structure are created for each data sector corresponding to an associated logical block and a storage location of the data sector in the buffer. When a predefined criterion is fulfilled before the buffer becomes full, a number of logical blocks to be merged is determined and data sectors corresponding to the number of logical blocks to be merged are written from the buffer to a primary non-volatile data storage memory of the non-volatile memory device.

Подробнее
Номер записи: 70
06-12-2012 дата публикации

Information Handling System with Processing System, Low-power Processing System and Shared Resources

Номер: US20120311364A1
Автор: Andrew T. Sultenfuss, Steven L. Belt
Принадлежит: Dell Products LP

An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.

Подробнее
Номер записи: 71
13-12-2012 дата публикации

Processor bridging in heterogeneous computer system

Номер: US20120317321A1
Автор: Teng-Chang Chang
Принадлежит: INSTITUTE FOR INFORMATION INDUSTRY

A bridge logic device for a heterogeneous computer system that has at least one performance processor, a processor supporting logic supporting the at least one performance processor to execute tasks of the software, and a hypervisor processor consuming less power than the at least one performance processor is disclosed. The bridge logic device comprises a hypervisor operation logic that maintains status of the system under the at least one performance processor; a processor language translator logic that translates between processor languages of the at least one performance and the hypervisor processors; and a high-speed bus switch that has first, second and third ports for relaying data across any two of the three ports bidirectionally. The switch is connected to the at least one performance processor, the hypervisor processor via the processor language translator logic, and to the processor supporting logic respectively at the first, second, and third port.

Подробнее
Номер записи: 72
13-12-2012 дата публикации

Cache prefetching from non-uniform memories

Номер: US20120317364A1
Автор: Gabriel H. Loh
Принадлежит: Advanced Micro Devices Inc

An apparatus is disclosed for performing cache prefetching from non-uniform memories. The apparatus includes a processor configured to access multiple system memories with different respective performance characteristics. Each memory stores a respective subset of system memory data. The apparatus includes caching logic configured to determine a portion of the system memory to prefetch into the data cache. The caching logic determines the portion to prefetch based on one or more of the respective performance characteristics of the system memory that stores the portion of data.

Подробнее
Номер записи: 73
13-12-2012 дата публикации

Releasing blocks of storage class memory

Номер: US20120317391A1
Автор: Harry M. Yudenfriend, Kenneth J. Oakes, Peter D. Driever, Peter G. Sutton, Peter K. Szwed, Steven G. Glassen
Принадлежит: International Business Machines Corp

An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Подробнее
Номер записи: 74
20-12-2012 дата публикации

List based prefetch

Номер: US20120324142A1
Автор: Alan Gara, Changhoan Kim, Krishnan Sugavanam, Martin Ohmacht, Norman Christ, Peter Boyle, Robert Mawhinney
Принадлежит: International Business Machines Corp

A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current cache miss address is valid. If the current cache miss address is valid, the list prefetch engine compares the current cache miss address and a list address. A list address represents an address in a list. A list describes an arbitrary sequence of prior cache miss addresses. The prefetch engine prefetches data according to the list, if there is a match between the current cache miss address and the list address.

Подробнее
Номер записи: 75
20-12-2012 дата публикации

Flash storage wear leveling device and method

Номер: US20120324299A1
Автор: Mark Moshayedi
Принадлежит: Stec Inc

A flash storage device performs wear-leveling by tracking data errors that occur when dynamic data is read from a storage block of the flash storage device and moving the dynamic data to an available storage block of the flash storage device. Additionally, the flash storage device identifies a storage block containing static data and moves the static data to the storage block previously containing the dynamic data.

Подробнее
Номер записи: 76
27-12-2012 дата публикации

Method of processing a print job within a printing system, a printing system, and a program

Номер: US20120327459A1
Автор: Karsten Huster
Принадлежит: Canon Europa NV

The present invention is generally related to a method of processing a print job within a printing system. The device status of each printer within the network is collected and used for a determination of the energy consumption of the print job. The results of the energy consumption are displayed to a user and the user may designate the most energy efficient printer for printing the print job.

Подробнее
Номер записи: 77
03-01-2013 дата публикации

Techniques for moving data between memory types

Номер: US20130007345A1
Автор: Francois Barbou-Des-Places, Joseph Sokol, Jr., Lionel D. Desai, Neil G. Crane
Принадлежит: Apple Inc

A two-level paging mechanism. The first level gathers data from reclaimable memory locations for a process and compacts the data into a single container. The second level sends the compact container's contents to a swap file and may use optimal I/O operations to the target memory device. On-demand paging is made possible by having a first pager locate the requested data in the compact container and then having a second pager retrieve the corresponding data from the swap file.

Подробнее
Номер записи: 78
03-01-2013 дата публикации

Limiting activity rates that impact life of a data storage media

Номер: US20130007380A1
Автор: David Scott Seekins, Kristofer Carlson Conklin, Ryan James Goss
Принадлежит: SEAGATE TECHNOLOGY LLC

A first cumulative data transfer over a first time window from an intermediary module to a data storage media is determined. The intermediary module is coupled between a host interface and the data storage media. An activity rate from the intermediary module to the data storage media is limited for one or more subsequent time windows if the first cumulative activity rate exceeds a threshold value that impacts life of the data storage media. The limitation of the activity rate is removed after the one or more subsequent time windows expire

Подробнее
Номер записи: 79
17-01-2013 дата публикации

Multi-partitioning of memories

Номер: US20130019058A1
Автор: Danilo Caraccio, Emanuele Confalonieri, Federico Tiziani
Принадлежит: Individual

Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

Подробнее
Номер записи: 80
17-01-2013 дата публикации

Mobile terminal and power control method

Номер: US20130019114A1
Автор: Haruhiko SUMIDA
Принадлежит: Nec Infrontia Corp

A mobile terminal includes: a tamper-detection circuit ( 17 ), an information processor ( 13 ) that is capable of executing a suspend function, a first battery ( 23 ) supplying power to the information processor ( 13 ) and the tamper-detection circuit ( 17 ), and a switch ( 27 ) that is provided on a power-source supply line ( 431 ) that connects the first battery ( 23 ) and the information processor ( 13 ) and the switch that is capable of switching between a state in which information processor ( 13 ) is connected to first battery ( 23 ) and a state in which information processor ( 13 ) is not connected to first battery ( 23 ).

Подробнее
Номер записи: 81
24-01-2013 дата публикации

Method and apparatus for high speed cache flushing in a non-volatile memory

Номер: US20130024623A1
Автор: Robert Alan Reid
Принадлежит: Cadence Design Systems Inc

An invention is provided for performing flush cache in a non-volatile memory. The invention includes maintaining a plurality of free memory blocks within a non-volatile memory. When a flush cache command is issued, a flush cache map is examined to obtain a memory address of a memory block in the plurality of free memory blocks within the non-volatile memory. The flush cache map includes a plurality of entries, each entry indicating a memory block of the plurality of free memory blocks. Then, a cache block is written to a memory block at the obtained memory address within the non-volatile memory. In this manner, when a flush cache command is received, the flush cache map allows cache blocks to be written to free memory blocks in the non-volatile memory without requiring a non-volatile memory search for free blocks or requiring erasing of memory blocks storing old data.

Подробнее
Номер записи: 82
24-01-2013 дата публикации

Hardware acceleration components for translating guest instructions to native instructions

Номер: US20130024661A1
Автор: Mohammad Abdallah
Принадлежит: Soft Machines Inc

A hardware based translation accelerator. The hardware includes a guest fetch logic component for accessing guest instructions; a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling guest instructions into a guest instruction block; and conversion tables coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block. The hardware further includes a native cache coupled to the conversion tables for storing the corresponding native conversion block, and a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block, wherein upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache.

Подробнее
Номер записи: 83
31-01-2013 дата публикации

Power consumption amount management system for managing power consumption amount, power consumption management method, and storage medium

Номер: US20130031385A1
Автор: Hidekazu Seto
Принадлежит: Canon Inc

A power consumption amount management system which is capable of appropriately managing the amount of power consumption according to the situation. In the power consumption amount management system, an image forming apparatus and a power consumption management server are connected to a network. An electric power measurement section in the image forming apparatus measures the amount of electric power consumed by the apparatus. A measurement error determination section determines whether or not measurement of the power consumption amount is successful. An interface section outputs a notification of information on the power consumption amount measured in the image forming apparatus and a result of the determination. The power consumption management server receives the notification from the image forming apparatus, and corrects the information on the power consumption amount in the image forming apparatus by referring to the result of the determination.

Подробнее
Номер записи: 84
07-02-2013 дата публикации

Wear leveling for a memory device

Номер: US20130036253A1
Автор: Robert Baltar
Принадлежит: Micron Technology Inc

Memory devices and methods to facilitate wear leveling operations in a memory device. In one such method, particular blocks of memory cells are excluded from experiencing wear leveling operations performed on the memory device. In at least one method, a user selects blocks of memory to be excluded from wear leveling operations performed on the remainder of blocks of the memory device. Selected blocks of memory are excluded from wear leveling operations responsive to a command initiated by a user identifying, either directly or indirectly, the selected blocks to be excluded.

Подробнее
Номер записи: 85
28-02-2013 дата публикации

Digital Signage Mode of Portable Device

Номер: US20130054994A1
Автор: Charles J. Stancil
Принадлежит: Hewlett Packard Development Co LP

A portable device includes a power component to receive power from a power source and a controller to transition the portable device from a power on state to a lower power state with a basic input output system (BIOS) of the portable device if the power component detects a loss of power received from the power source and transition the portable device from the lower power state to a digital signage mode with the BIOS if the power component receives power from the power source.

Подробнее
Номер записи: 86
14-03-2013 дата публикации

Flash memory storage device and method of judging problem storage regions thereof

Номер: US20130067142A1
Автор: Chiang-Chang Hsien, Chih-Ming Hsu, Kuo-Chung Liao, Yen-Hsin Liu, Young-Joon Choi, Yun-Hui Wang
Принадлежит: A Data Technology Suzhou Co Ltd

A method of judging problem storage regions adapted for a flash memory storage device includes steps of: sending a writing order to a flash memory chip for writing a written data to an appointed storage paging; when the flash memory chip beginning writing the written data to the appointed storage paging, getting the first time; when the flash memory chip finishing writing the written data to the appointed storage paging, getting the second time; calculating a writing time according to the first time and the second time; if the writing time not coincident with a standard value, then labeling the appointed storage paging as a problem storage region and copying the written data to a backup paging; updating a Mapping Table.

Подробнее
Номер записи: 87
14-03-2013 дата публикации

Method for efficient storage of metadata in flash memory

Номер: US20130067151A1
Автор: Mark Murin, Menahem Lasser
Принадлежит: Sandisk IL Ltd

A method includes writing a first portion of received user data to a first page of a block of a memory according to a writing schedule and writing a subsequent portion of the received user data to another page of the block according to the writing schedule. The method includes storing first metadata corresponding to writing the first portion in the memory. The method further includes associating the first metadata with the subsequent portion.

Подробнее
Номер записи: 88
21-03-2013 дата публикации

METHOD AND DEVICE FOR STORING DATA

Номер: US20130073782A1
Автор: Chen Weihua, Shu Jun, TIAN Ming, Xiong Huan, ZHUANG Sihua
Принадлежит:

The invention discloses a method for storing data and a device of implementing the same. The method comprises receiving a request for storing data sent by a user and storing the data to an SSD according to the received request. The device comprises a request receiving module used to receive the request storing data and an SSD storage module used to store the data to an SSD according to the received request. The invention ensures consistency of data storage by storing data to an SSD according to the received request, thereby reducing data redundancy caused by using a cache layer to cache the data in the prior art. Additionally, the use of a single layer of an SSD to store data avoids the need of reloading data in the cache layer once a machine is power-down, thereby reducing the complexity of system design and the cost of operation and maintenance. 1. A method for storing data , comprising the steps of:receiving a request for storing data sent by a user; andstoring the data in a solid state disk (SSD) according to the received request.2. The method according to claim 1 , after the step of receiving the request for storing the data claim 1 , further comprising the steps of:determining whether a storage type of the request for storing the data is a random access; if the request does not meet the pre-set storage condition, rejecting the request for storing the data; and', 'if the request meets the pre-set storage condition, executing the step of storing the data in the SSD according to the received request; and, 'if the storage type of the request for storing the data is a random access, determining whether the request for storing the data meets a pre-set storage condition;'}if the storage type of the request for storing the data is not the random access, executing the step of storing the data in the SSD according to the received request.3. The method according to claim 2 , wherein the pre-set storage condition comprises a maximum number of the request for which the SSD ...

Подробнее
Номер записи: 89
21-03-2013 дата публикации

Method and system for random write unalignment handling

Номер: US20130073784A1
Автор: King Ying Ng, Marielle Bundukin, Paul Lassa
Принадлежит: SanDisk Technologies LLC

A method and system are disclosed for handling host write commands associated with both data aligned with physical page boundaries of parallel write increments in non-volatile storage areas in a non-volatile storage device and data unaligned with the physical page boundaries. The method may include a controller of a storage device identifying the aligned and unaligned portions of received data, temporarily storing the aligned and unaligned portions in different queues, and then writing portions from the unaligned data queue or the aligned data queue in parallel to the non-volatile memory areas when one of the queues has been filled with a threshold amount of data or when the controller detects a timeout condition. The system may include a storage device with a controller configured to perform the method noted above, where the non-volatile memory areas may be separate banks and the queues are random access memory.

Подробнее
Номер записи: 90
21-03-2013 дата публикации

Weave sequence counter for non-volatile memory systems

Номер: US20130073788A1
Автор: Daniel J. Post, Nir Jacob Wakrat, Vadim Khmelnitsky
Принадлежит: Apple Inc

Systems and methods are disclosed for providing a weave sequence counter (“WSC”) for non-volatile memory (“NVM”) systems. The WSC can identify the sequence in which each page of the NVM is programmed. The “weave” aspect can refer to the fact that multiple blocks can be open for programming at once, thus allowing the pages of these blocks to be programmed in a “woven” manner. Systems and methods are also disclosed for providing a host weave sequence counter (“HWSC”). Each time new data is initially programmed to the NVM, this data can be associated with a particular HWSC. The HWSC associated with the data may not change, even when the data is moved to a new page (e.g., for wear leveling purposes and the like). The WSC and HWSC may aid in, for example, performing rollback, building logical-to-physical mappings, determining static-versus-dynamic page statuses, and performing maintenance operations (e.g., wear leveling).

Подробнее
Номер записи: 91
21-03-2013 дата публикации

Flash memory device and data management method

Номер: US20130073798A1
Автор: Dawoon Jung, Nam Wook Kang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Disclosed is a data management method for a flash storage device. The method includes collecting cold data stored in the flash memory device with reference to a cold list table, compressing the collected cold data, and then storing the compressed cold data in the flash memory.

Подробнее
Номер записи: 92
21-03-2013 дата публикации

Electronic Control Unit for Vehicle and Method of Writing Data

Номер: US20130073799A1
Автор: Koji Yuasa, Toshihisa ARAI, Yusuke Abe
Принадлежит: HITACHI AUTOMOTIVE SYSTEMS LTD

An electronic control unit for a vehicle including a nonvolatile memory capable of erasing and writing data electrically and two buffers to acquire, by communication, divided data obtained by dividing a program by predetermined size. Then, in parallel with using the two buffers alternately to receive divided data, the electronic control unit for a vehicle uses one buffer that is not used to receive divided data to write the received divided data into the nonvolatile memory.

Подробнее
Номер записи: 93
21-03-2013 дата публикации

Multipage Preparation Commands For Non-Volatile Memory Systems

Номер: US20130073800A1
Автор: Anthony Fai, Daniel Jeffrey Post, Nir Jacob Wakrat, Tahoma Toelkes, Vadim Khmelnitsky
Принадлежит: Apple Inc

Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation.

Подробнее
Номер записи: 94
21-03-2013 дата публикации

Method of storing data in a storage medium and data storage device including the storage medium

Номер: US20130073816A1
Автор: Junjin Kong, Mankeun SEO
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of storing data in a storage medium and a data storage device including the storage medium are provided. The method of storing data in accordance with exemplary embodiments of the inventive concept may include receiving data to be stored in the storage medium; determining whether the received data is user data or metadata used to manage the user data; and selectively compressing the received data according to a type of the determined data. Selectively compressed data is stored in the storage medium.

Подробнее
Номер записи: 95
28-03-2013 дата публикации

Information processing apparatus and control method

Номер: US20130080717A1
Автор: Keiichi Uehara
Принадлежит: Toshiba Corp

According to one embodiment, an apparatus includes a volatile memory, a nonvolatile semiconductor disk drive, a hibernation control module, a resume control module, and a release module. The drive includes SLC and MLC areas. The hibernation control module saves system context data in a first storage area in the SLC area in response to a hibernate request. The system context data includes contents of the volatile memory. The resume control module reads the system context data from the first storage area to restore the contents of the volatile memory, in response to a resume request. The release module releases the first storage area so as to allow the first storage area to be used to store other data, in response to completion of the read of the system context data.

Подробнее
Номер записи: 96
28-03-2013 дата публикации

Flash memory system

Номер: US20130080730A1
Автор: Jin-Ki Kim
Принадлежит: Mosaid Technologies Inc

A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.

Подробнее
Номер записи: 97
28-03-2013 дата публикации

Apparatus, system, and method for an address translation layer

Номер: US20130080732A1
Автор: David Nellans, Jens Axboe, Nick Piggin
Принадлежит: Fusion IO LLC

An apparatus, system, and method are disclosed for storage address translation. The method includes storing, in volatile memory, a plurality of logical-to-physical mapping entries for a non-volatile recording device. The method includes persisting a logical-to-physical mapping entry from the volatile memory to recording media of the non-volatile recording device. The logical-to-physical mapping entry may be selected for persisting based on a mapping policy indicated by a client. The method includes loading the logical-to-physical mapping entry from the recording media of the non-volatile recording device into the volatile memory in response to a storage request associated with the logical-to-physical mapping entry.

Подробнее
Номер записи: 98
04-04-2013 дата публикации

Enabling Throttling on Average Write Throughput for Solid State Storage Devices

Номер: US20130086302A1
Автор: Andrew D. Walls, Gary A. Tressler
Принадлежит: International Business Machines Corp

A mechanism is provided for enabling throttling on average write throughput instead of peak write throughput for solid-state storage devices. The mechanism assures an average write throughput within a range but allows excursions of high throughput with periods of low throughput offsetting against those of heavy usage. The mechanism periodically determines average throughput and determines whether average throughput exceeds a high throughput threshold for a certain amount of time without being offset by periods of low throughput.

Подробнее
Номер записи: 99
04-04-2013 дата публикации

FLASH-DRAM HYBRID MEMORY MODULE

Номер: US20130086309A1
Автор: Bhakta Jayesh, Chen Chi-She, Lee Hyun, Milton Scott, Solomon Jeffrey C.
Принадлежит: Netlist, Inc.

A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands. 1. A memory module couplable to a memory controller of a host system , comprising:a non-volatile memory subsystem;a data manager coupled to the non-volatile memory subsystem;a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager; anda controller operable to receive commands from the memory controller and to direct (i) operation of the non-volatile memory subsystem, (ii) operation of the volatile memory subsystem, and (iii) transfer of data between any two or more of the memory controller, the volatile memory subsystem, and the non-volatile memory subsystem based on at least one received command from the memory controller.2. The memory module of claim 1 , wherein the data manager is operable to control one or more of data flow rate claim 1 , data transfer size claim 1 , data buffer size claim 1 , data error monitoring claim 1 , and data error correction in response to receiving at least one of a control signal and control information from the controller.3. The memory module of claim 1 , wherein the data manager controls data traffic between any two or more of the memory controller claim 1 , the volatile memory subsystem claim 1 , and the non-volatile memory subsystem based on instructions received from the controller.4. The memory module of claim 3 , wherein data traffic control relates to any one or more of data ...

Подробнее
Номер записи: 100