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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 35688. Отображено 100.

05-01-2012 дата публикации

Communication circuit of inter-integrated circuit device

Номер: US20120005385A1

Автор: Ming-Yuan Hsu

Принадлежит: Hon Hai Precision Industry Co Ltd

A communication circuit of an Inter-Integrated Circuit (I2C) includes a master device, a switch circuit, first and second groups of slave devices. Each slave device includes a data signal pin and a clock signal pin, which are connected to the switch circuit. The master device includes a data signal pin, a clock signal pin, and a general purpose input output (GPIO) pin, which are connected to the switch circuit. The GPIO pin of the master device outputs a control signal to the switch circuit, to allow communication between the first group of slave devices and the master device or communication between the second group of slave devices and the master device.

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Номер записи: 1

12-01-2012 дата публикации

Transmitting Retry Request Associated With Non-Posted Command Via Response Credit Channel

Номер: US20120011283A1

Автор: Curtis C. Wollbrink, Elizabeth A. McGlone, John L. Pike, Ronald E. Freking

Принадлежит: International Business Machines Corp

In a particular embodiment, a method is disclosed that includes, at a first computing device coupled to a second computing device via a bus, receiving a request from the second computing device to complete a non-posted command, where the request is received via a request credit channel of the bus, and where the first computing device is configured to receive requests to complete non-posted commands and requests to complete posted commands via the request credit channel. The method also includes removing the request to complete the non-posted command from the request credit channel. The method further includes transmitting a retry request associated with the non-posted command to the second computing device via a response credit channel of the bus.

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Номер записи: 2

12-01-2012 дата публикации

Apparatus and method for controlling issuing of transaction requests

Номер: US20120011291A1

Автор: Andrew David Tune, Timothy Charles Mace

Принадлежит: ARM LTD

Transaction requests requesting a service from the slave device are received from a master device at a transaction interface. The transaction requests are selectively issued to the bus system under control of an issue control circuit. A target outstanding transaction value N.x is received at a control interface. The target outstanding transaction value has an integer portion N and a fractional portion x. The issue control circuit controls the transaction interface to issue the transaction requests to the bus system in dependence upon the target outstanding transaction value so that a time averaged number of outstanding transaction requests corresponds to the target outstanding transaction value.

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Номер записи: 3

12-01-2012 дата публикации

Method and apparatus for wireless broadband systems direct data transfer

Номер: US20120011295A1

Автор: Assaf Touboul, Meir Tsadik, Moshe Tanach

Принадлежит: DESIGNART NETWORKS LTD

Apparatus and method for direct data transfer in a wireless broadband system having an operating system, the apparatus including a central processing unit (CPU), at least one dedicated Direct Memory Access unit (DMA) local to the CPU, coupled directly to the CPU, and a commands FIFO (First In First Out) receiving commands from the CPU and automatically transferring the commands in sequence to the DMA for implementation by the DMA, in the absence of intervention by the operating system.

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Номер записи: 4

19-01-2012 дата публикации

Data transfer circuit and data transfer method

Номер: US20120017017A1

Автор: Masaru Nishiyashiki

Принадлежит: Fujitsu Ltd

A port A request queue is configured with a port AQ 0 to a port AQn for each of request types Q 0 to Qn connected with a requester resource busy flag controller Q 0 to a requester resource busy flag controller Qn, respectively. A port A resource checking unit of a port X arbiter unit gives instructions to the requester resource busy flag controller of the port AQ 0 to turn a busy flag on when it is determined that a data request from the port AQ 0 has difficulty in being output to a port X inter-port arbiter unit due to resources being busy as a result of referring to a resource information unit of a port X resource managing unit. The port AQ 0 inhibits output of a data request as long as the busy flag is on.

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Номер записи: 5

19-01-2012 дата публикации

Verifying access-control policies with arithmetic quantifier-free form constraints

Номер: US20120017260A1

Автор: Gary Levin, Sanjai Narain

Принадлежит: Telcordia Technologies Inc

A system and method is provided for verifying an access-control policy against a particular constraint for a multi-step operation. In disclosed embodiments, the method includes expressing the access-control policy as a first quantifier-free form (QFF) constraint and identifying the particular constraint as a second QFF constraint. The method also includes identifying an operation vector and providing copies of the operation vector associated with steps in the multi-step operation. The method also includes determining a third QFF constraint using the first QFF constraint, the second QFF constraint, and the copies of the operation vector. The method also includes solving the third QFF constraint to determine a solution and outputting a result of the solving.

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Номер записи: 6

09-02-2012 дата публикации

Optical memory expansion

Номер: US20120033978A1

Автор: Michael Renne Ty Tan, Terrel Morris

Принадлежит: Hewlett Packard Development Co LP

Various embodiments of the present invention are directed to optical-based methods and expansion memory systems for disaggregating memory of computer systems. In one aspect, an expansion memory system comprises a first optical/electronic interface in electrical communication with a processor, a memory expansion board configured with memory, and a second optical/electronic interface attached to the memory expansion board. The first interface converts optical signals into electronic signals that are sent to the processor and converts electronic signals produced by the processor into optical signals. The second interface converts optical signals into electronic signals that are sent to the memory and converts electronic signals produced by the memory into optical signals. The optical signals are exchanged between the first and second interfaces. Embodiments also include methods for sending and receiving data in an expansion memory system.

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Номер записи: 7

09-02-2012 дата публикации

Systems and methods for using a shared buffer construct in performance of concurrent data-driven tasks

Номер: US20120036288A1

Автор: David Goodwin, Peter Mattson

Принадлежит: Calos Fund LLC

Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory accessible to the operation of the first task is created. A second task is initiated to perform of an operation of the second task that is configured to be timed to initiate in response to the buffer construct being communicated to the second task from the first task.

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Номер записи: 8

09-02-2012 дата публикации

Data Flow Control Within and Between DMA Channels

Номер: US20120036289A1

Автор: Dominic Go, Mark D. Hayter, Puneet Kumar

Принадлежит: Individual

In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

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Номер записи: 9

16-02-2012 дата публикации

Bus bandwidth monitoring device and bus bandwidth monitoring method

Номер: US20120042111A1

Автор: Akira Ueno, Keisuke Nakazono, Tomonori Yonemoto

Принадлежит: Olympus Corp

A bus bandwidth monitoring device may include a buffer unit that is connected to a common bus, the buffer unit storing data that has been input via the common bus, a processing unit that performs predetermined processing based on the data stored in the buffer unit, and a detection unit that detects a bandwidth of the data of the common bus based on a state of storage of the data that is input to the buffer unit through the common bus.

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Номер записи: 10

01-03-2012 дата публикации

Methods and apparatus for improved serial advanced technology attachment performance

Номер: US20120054403A1

Автор: Brian A. Day

Принадлежит: LSI Corp

Methods and apparatus for improved performance in communications with a SATA target device. Features and aspects hereof provide for continuing DMA transfers from a storage controller (e.g., a SATA host or a SAS/STP initiator) to a SATA target device without regard to receipt of DMA ACTIVATE Frame Information Structures (FIS). Logic to implement these features may be provided by bridge logic within an enhanced SAS expander coupled with an enhanced SAS/STP initiator or may be provided by suitable logic in an enhanced SATA host coupled directly with an enhanced SATA target device. By continuing DMA transfer of data from the initiator/host to the SATA target device without regard to receipt of a DMA ACTIVATE FIS, more of the available bandwidth of the SAS/SATA communication link may be utilized. Other standard features of the SAS/SATA protocols provide for flow control to prevent overrun of the SATA target device's buffers.

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Номер записи: 11

08-03-2012 дата публикации

Method for Assigning Addresses to Nodes of a Bus System, and Installation

Номер: US20120059959A1

Автор: Olaf Simon

Принадлежит: SEW Eurodrive GmbH and Co KG

A method for assigning addresses to nodes of a bus system, and installation, bus nodes being furnished with an identical delivery address, where (i) an assigning entity, particularly a central computer, start-up computer or bus node sends information to the delivery address via the bus system, (ii) the information includes a first address, (iii) an action is performed whose effect is detected by a first bus node, (iv) the first bus node accepts the first address, (v) the first bus node sends a response to the assigning entity, (vi) steps (i) through (v) are repeated, each time with a further address for a further bus node.

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Номер записи: 12

08-03-2012 дата публикации

Non-invasive direct-mapping usb switching device

Номер: US20120059969A1

Автор: Cheng-Sheng Chou, Chien-Fa Lin

Принадлежит: June On Technology Co Ltd

A non-invasive direct-mapping USB switching device includes a main-controlled microprocessing module connected to a high-impedance module, and the high-impedance module is provided for detecting and monitoring a functional instruction code of a USB device transmitted from a data transmission module, such that a USB connecting module can be used for transmitting the USB data and functional instruction code to detect and monitor the data transmission module when the USB device is connected to the USB switching device. If the data transmitted from the data transmission module is not the required functional code, the non-required functional code (such as the USB data) will be passed, so that the USB device can be connected and communicated with a plurality of computer devices through another USB connecting module and a switching module to achieve a plug-and-play function.

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Номер записи: 13

15-03-2012 дата публикации

Multi-device docking with a displayport compatible cable

Номер: US20120066425A1

Автор: Henry Zeng, Ji Park

Принадлежит: Integrated Device Technology Inc

A docking system utilizing a single DisplayPort cable connection to a computer system is provided. In one embodiment, the docking system includes a single DisplayPort (“DP”) input, a management layer module coupled to receive video inputs from the single DP input and to provide video data to at least one video monitor output, and a USB layer module coupled to receive an AUX channel from the single DP input and to couple the AUX channel with a USB hub.

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Номер записи: 14

15-03-2012 дата публикации

Use of pci express for cpu-to-cpu communication

Номер: US20120066430A1

Автор: Braden Michael Cooper, Stephen Dale Cooper

Принадлежит: Individual

CPUs that generate PCIe auxiliary signals and changing clock signals nevertheless communicate with each other using PCIe owing to PCIe switch assemblies that are disposed in the communication paths to isolate and terminate the auxiliary signals from reaching other CPUs and to isolate changing clock signals, communicating with each other using a fixed clock derived from one of the changing clock signals. Also, the CPUs directly access the memories of CPUs to which they wish to write data so that data is directly written from one CPU memory to another without store-and-forward operations being needed in the network.

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Номер записи: 15

22-03-2012 дата публикации

Memory system having high data transfer efficiency and host controller

Номер: US20120072618A1

Автор: Akihisa Fujimoto

Принадлежит: Individual

According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.

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Номер записи: 16

22-03-2012 дата публикации

Communication system, master device and slave device, and communication method

Номер: US20120072629A1

Автор: Masashi Tokuda

Принадлежит: Ricoh Co Ltd

A communication system includes a master device and slave devices. Each slave device includes a request signal generation part configured to, when data to transmit is generated, generate a request signal indicating a transmission request to a master device; and a transmission part configured to transmit the request signal to the master device. The master device includes a request signal reception part configured to receive the request signals from the slave devices; a selection part acting configured to select one of the slave devices according to the request signals received by the reception part; a transmission part configured to transmit a signal indicating to allow data transmission to the slave device selected by the selection part; and a data reception part configured to receive data from the selected slave device.

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Номер записи: 17

29-03-2012 дата публикации

Cache with Multiple Access Pipelines

Номер: US20120079204A1

Автор: Abhijeet Ashok Chachad, Jonathan (Son) Hung Tran, Raguram Damodaran, Sanjive Agarwala, Timothy David Anderson

Принадлежит: Texas Instruments Inc

Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.

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Номер записи: 18

05-04-2012 дата публикации

Analog front end protocol converter/adapter for slpi protocol

Номер: US20120082166A1

Автор: Danilo Ranieri, Kenneth Jay Helfrich, Leonardo Sala

Принадлежит: Maxim Integrated Products Inc

In an embodiment, an analog front end (AFE) bridge for a SLPI PHY includes: an AFE LINK-side circuit having at least one pair of differential LINK-side nodes which does not conform to SLPI PHY specifications; an AFE PHY-side circuit having a pair of differential PHY-side nodes conforming to SLPI PHY specifications, wherein the AFE PHY-side circuit is coupled to the AFE LINK-side circuit; and a termination control circuit coupled to the AFE PHY-side circuit. A method of bridging a legacy LINK circuit to a SLPI PHY circuit includes: communicating with a legacy LINK circuit with a legacy LINK protocol; communicating with a SLPI PHY circuit with a SLPY PHY protocol over a differential pair; converting outputs of the legacy LINK circuit into inputs of the SLPI PHY circuit; converting outputs of the SLPI PHY circuit into inputs of the legacy LINK circuit; controlling a termination of the differential pair.

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Номер записи: 19

12-04-2012 дата публикации

Method of adjusting transfer speed after initialization of SATA interface

Номер: US20120089755A1

Автор: Hsieh-Huan Yen, Huei-Chiang Shiu, Teng-Chuan Hsieh

Принадлежит: Individual

In a method of adjusting transfer speed after initialization of a SATA interface, a SATA link device transmits a first predetermined primitive to a SATA link partner for requesting to change a first transfer speed of the SATA link device from a first speed to a second speed, the SATA link partner replies to the SATA link device with a second predetermined primitive according to the first predetermined primitive, and the SATA link device and the SATA link partner respectively adjust the first transfer speed of the SATA link device and a second transfer speed of the SATA link partner according to the second predetermined primitive.

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Номер записи: 20

19-04-2012 дата публикации

Formal Verification of Random Priority-Based Arbiters Using Property Strengthening and Underapproximations

Номер: US20120096204A1

Автор: David J. Levitt, Fady Copty, Gadiel Auerbach, Viresh Paruthi

Принадлежит: International Business Machines Corp

A mechanism is provide for formally verifying random priority-based arbiters. A determination is made as to whether a random priority-based arbiter is blocking one of a set of output ports or a set of input ports. Responsive to the first predetermined time period expiring before the processor determines whether the random priority-based arbiter is blocking, a determination is made as to whether the random priority-based arbiter is blocking one of the set of output ports or the set of input ports within a second predetermined time period using the random seed and at least one of property strengthening or underapproximation. Responsive to the processor determining that the random priority-based arbiter satisfies a non-blocking specification such that not one of the set of output ports or the set of input ports is blocked within the second predetermined time period, the random priority-based arbiter is validated as satisfying the non-blocking specification.

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Номер записи: 21

26-04-2012 дата публикации

Communication control apparatus and method of controlling the same

Номер: US20120102244A1

Автор: Yasuhiro Shiraishi

Принадлежит: Canon Inc

A communication control apparatus includes a first interface, a second interface, a determination unit, and a control unit. The first interface is connected to a detachable recording medium. The second interface is connected to an external device. The second interface includes a first bus controlled by a first bus controller and a second bus controlled by a second bus controller. The second bus has a maximum transfer rate less than that of the first bus. The determination unit is configured to determine a data transfer rate of the detachable recording medium when the detachable recording medium is connected to the first interface. The control unit is configured to establish a connection to the external device via the first bus when the determined data transfer rate exceeds a predetermined threshold, and via the second bus when the determined data transfer rate does not exceed the predetermined threshold.

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Номер записи: 22

03-05-2012 дата публикации

Tiered data storage system with data management and method of operation thereof

Номер: US20120110259A1

Автор: Andrew Mills, Marshall Lee

Принадлежит: ENMOTUS Inc

A method of operation of a data storage system includes: enabling a system interface for receiving host commands; updating a mapping register for monitoring transaction records of a logical block address for the host commands including translating a host virtual block address to a physical address for storage devices; accessing by a storage processor, the mapping register for comparing the transaction records with a tiering policies register; and enabling a tiered storage engine for transferring host data blocks by the system interface and concurrently transferring between a tier zero, a tier one, or a tier two if the storage processor determines the transaction records exceed the tiering policies register.

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Номер записи: 23

10-05-2012 дата публикации

Providing indirect data addressing for a control block at a channel subsystem of an i/o processing system

Номер: US20120117275A1

Автор: Catherine C. Huang, Dale F. Riedy, Daniel F. Casper, Gustav E. Sittmann, John R. Flanagan, Matthew J. Kalos, Ugochukwu C. Njoku

Принадлежит: International Business Machines Corp

An computer program product, apparatus, and method for facilitating input/output (I/O) processing for an I/O operation at a host computer system configured for communication with a control unit. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes the host computer system obtaining a transport command word (TCW) for an I/O operation. The TCW specifies a location of one or more I/O commands and a flag set to indicate that the location is an indirect address. The host computer system extracts the location of the one or more I/O commands and the flag from the TCW, gathers the one or more I/O commands responsive to the location specified by the TCW and the flag, and then forwards the one or more I/O commands to the control unit for execution.

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Номер записи: 24

10-05-2012 дата публикации

Fencing Direct Memory Access Data Transfers In A Parallel Active Messaging Interface Of A Parallel Computer

Номер: US20120117281A1

Автор: Amith R. Mamidala, Michael A. Blocksome

Принадлежит: International Business Machines Corp

Fencing direct memory access (‘DMA’) data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

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Номер записи: 25

17-05-2012 дата публикации

Switch circuit and method for switching input/output port and electronic device using the same

Номер: US20120124253A1

Автор: Hsu-Hung Cheng

Принадлежит: ASUSTeK Computer Inc

A switch circuit for switching input/output port includes a control unit, a built-in input/output (I/O) port, an external I/O port and a switch unit. The switch unit is electrically connected to the control unit, the built-in I/O port and the external I/O port. The switch unit receives a control signal and selectively forms a channel between the control unit and the built-in I/O port or between the control unit and the external I/O port accordingly.

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Номер записи: 26

17-05-2012 дата публикации

Technique for communicating interrupts in a computer system

Номер: US20120124264A1

Автор: James B. Crossland, Keshavan Tiruvallur, Luke Hood, Rajesh Parthasarathy, Shivnanda Kaushik

Принадлежит: Individual

A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APlC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

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Номер записи: 27

17-05-2012 дата публикации

Hybrid storage device and electronic system using the same

Номер: US20120124266A1

Автор: Byung-Hoon Chung, Jae-won You, Kyu-yeol Park, Tae-yung Kim

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A hybrid storage device is provided. The hybrid storage device includes a first storage part that comprises an interface device based on a first standard, a second storage part that comprises an interface device based on a second standard, and a connector for interface devices that is shared by the first storage part and the second storage part and comprises a plurality of pins.

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Номер записи: 28

24-05-2012 дата публикации

Determining addresses of electrical components arranged in a daisy chain

Номер: US20120131231A1

Автор: Gerardo Monreal

Принадлежит: Allegro Microsystems LLC

In one aspect, a system includes electrical components arranged in a daisy chain that include a first electrical component disposed at a first end of the daisy chain and a second electrical component disposed at an opposite end of the daisy chain than the first end. Each of the first and second electrical components includes an input port, an output port and a common port. The input port of the first electrical component is coupled to one of a supply voltage port or ground and the common ports of the first and second electrical components are coupled to the other one of the supply voltage or the ground. An address of the second electrical component is determined before addresses of the other of the electrical components are determined, and the addresses determine a position of an electrical component with respect to the other of the electrical components.

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Номер записи: 29

31-05-2012 дата публикации

Communication system, master node, and slave node

Номер: US20120137034A1

Автор: Naoji Kaneko

Принадлежит: Denso Corp

In a node communicably coupled to alternative nodes through a bus, a transmitting unit receives first designation information from an alternative node. When the first designation information designates the node, the transmitting unit successively transmits, on the bus, the first designation information and data. When a request of an active communication occurs in the node, a request unit determines whether to receive a former part of the first identification information indicative of start timing of an active communication mode on the bus. When determining to receive the former part of the first identification information, the request unit transmits, on the bus, collision information at a timing that allows the collision information to collide with a latter part of the first identification information, resulting in rewrite of the first identification information based on bus arbitration, and transmits second designation information meeting the request of the active communication.

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Номер записи: 30

31-05-2012 дата публикации

Computing device and serial communication method of the computing device

Номер: US20120137035A1

Автор: Ji-Zhi Yin, Jian Peng

Принадлежит: Hon Hai Precision Industry Co Ltd, Hongfujin Precision Industry Shenzhen Co Ltd

A serial communication method is applied in a computing device to communicate serially with any external serial device. The computing device includes a baseboard management controller (BMC) and an operating system (OS). The BMC includes at least one physical serial port. The method generates a virtual serial port for the OS by emulating serial port functionality of the physical serial port. When the BMC is initializing the physical serial port and a serial device is connected to the physical serial port, an interrupt handler is activated to handle an interrupt triggered to the BMC by the serial device. The interrupt handler is deactivated when the physical serial port has been initialized by the BMC.

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Номер записи: 31

07-06-2012 дата публикации

Apparatuses, systems, and methods for facilitating optical communication between electronic devices

Номер: US20120141132A1

Автор: Richard C. Walker

Принадлежит: CORNING OPTICAL COMMUNICATIONS LLC

Active optical cable assemblies, and systems, methods, and adapter modules and integrated circuits for facilitating communication between a host and a client device over a fiber optic cable are disclosed. In one embodiment, an active optical cable assembly includes a fiber optic cable having at least one optical fiber, a host active circuit, a client active circuit, a host connector, and a client connector. Upon a connection between the host active circuit and a host device, the client termination switch closes to couple the client termination impedance to the ground reference potential. Upon a connection between the client active circuit and a client device, the host termination switch closes to the couple the host termination impedance to the ground reference potential. In another embodiment, a method includes enabling a host termination impedance upon a connection of an active optical cable to a client device.

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Номер записи: 32

07-06-2012 дата публикации

Baseboard management controller and method for sharing serial port

Номер: US20120144180A1

Автор: Chiang-Chung Tang

Принадлежит: Hon Hai Precision Industry Co Ltd

A baseboard management controller (BMC) connects with a COM serial port. The BMC includes an input queue and an output queue. If a basic input output system (BIOS) of the BMC has been initialized, the COM serial port is used by the BIOS. When a processor of the BMC sends a control command to a sharing system of the BMC, the input queue and the output queue are converted to time division multiplex (TDM) queues. The COM serial port may be used by the BIOS or by the BMC according to an ID flag of each element of the TDM queues.

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Номер записи: 33

21-06-2012 дата публикации

System and method for peripheral device communications

Номер: US20120159018A1

Автор: Alon Tsafrir, Mark N. Fullerton, Ofer Bar-Shalom

Принадлежит: Alon Tsafrir, Fullerton Mark N, Ofer Bar-Shalom

A method for operating a host device includes comparing a predetermined response of a peripheral device to a response token received from the peripheral device. The predetermined response and the response token are generated based on a first command transmitted from the host device to the peripheral device. The method further includes controlling a transfer of first data from a first memory to a peripheral control module based on the comparison between the predetermined response and the response token without interrupting a host control module, and selectively passing interrupts to the host control module when the predetermined response does not match the response token.

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Номер записи: 34

28-06-2012 дата публикации

Selectively enabling a host transfer interrupt

Номер: US20120166685A1

Автор: Jing Booth, Rebekah A. Wilson

Принадлежит: Western Digital Technologies Inc

Embodiments of the invention are directed to systems and methods for reducing the number of interrupts on a controller for a non-volatile storage device to improve data transfer performance of the storage system. The embodiments described herein selectively enable an interrupt generated by host transfer hardware for a host command. The interrupt can be enabled or disabled by considering the command type, availability of interface resources to accept additional host transfers, and the command size. Embodiments described herein are useful for host interfaces implementing a tagging scheme for host transfers with a limited range of identification tags.

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Номер записи: 35

28-06-2012 дата публикации

Multi-root sharing of single-root input/output virtualization

Номер: US20120166690A1

Автор: Jack Regula

Принадлежит: PLX Technology Inc

In a first embodiment of the present invention, a method for multi-root sharing of a plurality of single root input/output virtualization (SR-IOV) endpoints is provided, the method comprising: CSR redirection to a management processor which either acts as a proxy to execute the CSR request on behalf of the host or filters it and performs an alternate action, downstream routing of memory mapped I/O request packets through the switch in the host's address space and address translation with VF BAR granularity, upstream routing of requests originated by I/O devices by table lookup indexed by Requester ID, and requester ID translation using a fixed local-global RID offset.

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Номер записи: 36

28-06-2012 дата публикации

Bus-handling

Номер: US20120166826A1

Автор: Victor Flachs

Принадлежит: Nuvoton Technology Corp

A processor, comprising a processing unit having an active state and a sleep state in which at least one of its sub-sections is inactive and a communication port adapted to receive signals from external units over a bus, which is configured to be not fully operative when the processor is in the sleep state. The processor additionally includes a bus monitoring unit configured to stall the bus responsive to identifying transmissions on the bus directed to the communication port, while the processing unit is in the sleep state and to indicate to the communication port that a transmission started while it was in the sleep state.

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Номер записи: 37

12-07-2012 дата публикации

Electrical Circuit For Transmitting Signals Between Two Masters And One Or More Slaves

Номер: US20120179848A1

Автор: Volker Frese

Принадлежит: ROBERT BOSCH GMBH

An electrical circuit for transmitting signals between two masters and one or more slaves is described. The two masters and the slave or slaves are connected to one another via a bus system. At least one master data signal can be generated by each of the two masters, which signal can be received by the slave or slaves. A three-state gate is present at each of the outputs of the two masters at which the respective master data signal is present. The three-state gates are effective either as closed or as open switches. The three-state gates are activated in such a way that the three-state gate associated with the one of the two masters acts as a closed switch, and the three-state gate associated with the other of the two masters acts as an open switch.

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Номер записи: 38

19-07-2012 дата публикации

Apparatus and methods for serial interfaces

Номер: US20120185623A1

Автор: Florinel G. Balteanu, James Henry Ross

Принадлежит: Skyworks Solutions Inc

Apparatus and methods for serial interfaces are provided. In one embodiment, an integrated circuit operable to communicate over a serial interface is provided. The integrated circuit includes analog circuitry, registers for controlling the operation of the analog circuitry, and a distributed slave device including a primary block and a secondary block. The registers are accessible over the serial interface using a shared register address space. Additionally, the primary block is electrically connected to the serial interface and to a first portion of the registers and the secondary block is electrically connected to the primary block and to a second portion of the registers.

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Номер записи: 39

19-07-2012 дата публикации

Operation method for a computer system

Номер: US20120185631A1

Автор: Hua-Chih Yang, Liang-Chun Lin

Принадлежит: Prolific Technology Inc

A device receives a standard command. The device judges whether an address field and/or a data length field and/or a data field of the standard command includes at least one of a vendor command, a vendor data and a checkword. The device judges whether the address field and/or a data length field and/or the data field of the standard command matches a vendor predetermined pattern. If matched, the device performs a vendor operation based on the vendor command and/or the vendor data of the standard command.

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Номер записи: 40

26-07-2012 дата публикации

Providing virtual functions after an input/output adapter is moved from a first location to a second location

Номер: US20120191884A1

Автор: Bryan M. Logan, Gregory M. Nordstrom, John R. Oberly, III, Sean T. Brownlow

Принадлежит: International Business Machines Corp

A computer implemented method includes identifying a hardware input/output adapter in a first physical slot location. The computer implemented method includes determining that the hardware input/output adapter is capable of hosting a plurality of virtual functions in the first physical slot location. The computer implemented method also includes selecting a group identifier that is unassociated with another physical slot location. The computer implemented method includes associating the group identifier with the first physical slot location of the hardware input/output adapter.

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Номер записи: 41

02-08-2012 дата публикации

Memory Attribute Sharing Between Differing Cache Levels of Multilevel Cache

Номер: US20120198166A1

Автор: Joseph Raymond Michael Zbiciak, Naveen Bhoria, Raguram Damodaran

Принадлежит: Texas Instruments Inc

The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.

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Номер записи: 42

02-08-2012 дата публикации

System and Method for Facilitating Data Transfer Between a First Clock Domain and a Second Clock Domain

Номер: US20120198267A1

Автор: Alexander Raykhman, Philip Crary, Srinjoy Das

Принадлежит: Qualcomm Atheros Inc

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

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Номер записи: 43

09-08-2012 дата публикации

Transfer of Uncompressed Multimedia Contents or Data Communications

Номер: US20120203937A1

Автор: Ning Zhu, Soumendra Mohanty

Принадлежит: Individual

A system and corresponding method for transferring data via an interface assembly. The data may be transferred between a USB port of a first device and a media port of a second device. Uncompressed high definition media data may be received from the USB port. The received uncompressed high definition media data may be supplied to a media connector in accordance with a first media standard, such that the supplied data can be transmitted in accordance with the first media standard via the media connector to the media port of the second device. The uncompressed high definition media data may include multimedia data and side-band communication data. A single signal may be encoded and decoded in accordance with a protocol that enables the single signal to communicate all side-band communication to and from the source device via a single pin of a USB connector.

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Номер записи: 44

09-08-2012 дата публикации

Livelock prevention mechanism in a ring shaped interconnect utilizing round robin sampling

Номер: US20120203946A1

Автор: Amit Golander, Eric F. Robinson, Nadav Levison, Omer Heymann

Принадлежит: International Business Machines Corp

A novel and useful cost effective mechanism for detecting the livelock/starvation of transactions in a ring shaped interconnect that utilizes minimal logic resources. Rather than monitor all transactions concurrently in the ring, the mechanism monitors only a single transaction in the ring. A sampling point is located at a point in the ring which contains a set of N latches. If the monitored transaction is not being starved, it is released and the detection logic moves on the next candidate transaction in round robin fashion. If the monitored transaction passes the sampling point a threshold number of times, it is deemed to be starved and a starvation prevention handling procedure is activated. By traversing the entire ring a single transaction at a time, all starving transactions will eventually be detected with an upper limit on the detection time of O(N 2 ).

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Номер записи: 45

09-08-2012 дата публикации

Memory System with Calibrated Data Communication

Номер: US20120204054A1

Автор: Benedict Chung-Kwong Lau, Bruno W. Garlepp, Donald C. Stark, Jared Levan Zerbe, Jun Kim, Kevin S. Donnelly, Leung Yu, Mark A. Horowitz, Roxanne Vu, Stefanos Sidiropoulos, Tsyr-Chyang Ho

Принадлежит: RAMBUS INC

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

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Номер записи: 46

16-08-2012 дата публикации

Optical transceiver installing cpu and interface communicating with upper device by mdio protocol

Номер: US20120207478A1

Автор: Hiromi Tanaka, Ryutaro Futami

Принадлежит: Sumitomo Electric Industries Ltd

An optical transceiver able to communicate with an upper device is disclosed. The optical transceiver distinguishes the peripheral interface from the CPU. The CPU monitors includes MDIO register that stores inner conditions of the optical transceiver. The peripheral interface is coupled with the upper device with the MDIO bus, and the CPU with the parallel bus. The upper device acquires one of the conditions by defining the address of the MDIO register and receiving data through the peripheral interface.

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Номер записи: 47

30-08-2012 дата публикации

Method for the operation of a data bus, and data bus system

Номер: US20120218601A1

Автор: Arno Best, Herbert Gibisch, Hermann Andresen, Robert Heimbach, Thomas Kreppold

Принадлежит: Individual

For operation of a data bus to which multiple bus participants each with a respective serial number are connected, a new bus participant is connected. A request bus message is generated by the new bus participant containing a preliminary participant identification number. The request bus message is arbitrated in the data bus by means of the identification number. A final participant identification number is assigned for the new bus participant having fewer digits than the serial number of the new participant. The final participant identification number is used for further bus messages by the new bus participant. During an initialization bus messages are used with an identifier in which a complete serial number is entered as the identifier. After the initialization a different type of bus message is used that has a shorter identifier.

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Номер записи: 48

06-09-2012 дата публикации

Processor, and method of loop count control by processor

Номер: US20120226894A1

Автор: Katsutoshi Seki

Принадлежит: NEC Corp

The present invention provides a processor comprising: a loop counter that is reset to 0 when a loop instruction for executing a process in a loop from a loop start address to a loop end address is issued; a data memory that receives, from outside, data that is used for executing a process in the loop; a calculator that uses the data transferred to said data memory to execute the process in the loop; a data counter that increments said loop counter by 1 every time a certain amount of data is transferred from outside to said data memory; and a loop controller that decrements said loop counter by 1 and causes said calculator to execute the process in the loop when the loop count value of said loop counter is not 0.

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Номер записи: 49

13-09-2012 дата публикации

Data transfer control device, integrated circuit of same, data transfer control method of same, data transfer completion notification device, integrated circuit of same, data transfer completion notification method of same, and data transfer control system

Номер: US20120233372A1

Автор: Hideki Taniguchi, Masaaki Harada, Satomi Amano, Satoru Kuriki, Yuusaku Ohta

Принадлежит: Panasonic Corp

A data transfer control device 1061 includes a read pointer update unit 5004 updating a value of a global read pointer RPg with a value of a local read pointer (first local read pointer) RP 11 held by a local read pointer hold unit 5007 when completion of data transfer is recognized and a position, in an order of reading descriptors, of a descriptor D 3010 a indicated by the local read pointer RP 11 is earlier than positions of descriptors D 3010 b and D 3010 c respectively indicated by local read pointers (second local read pointers) RP 12 and RP 13 held by the other data transfer control devices 1062 and 1063.

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Номер записи: 50

27-09-2012 дата публикации

Host computer, computer terminal, and card access method

Номер: US20120246357A1

Автор: Masayoshi Murayama

Принадлежит: Individual

According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit that includes both a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information for an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.

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Номер записи: 51

11-10-2012 дата публикации

Coupling a Specialty System, Such as Metering System, to Multiple Control Systems

Номер: US20120259435A1

Автор: Lawson H. Ramsay

Принадлежит: Daniel Measurement and Control Inc

A metering system configured to couple to multiple specialty systems, such as a control system. At least some of the illustrative embodiments are processing units comprising a processor, a memory coupled to the processor, and a communication port configured to coupled to a backbone communication network of a control system. The memory stores a program that causes the processor to selectively participate (over the communication port) as a processing unit of a control system of a first manufacturer (the control system implements a first proprietary communication protocol between processing units), and to participate (over the communication port) as a processing unit of a control system of a second manufacturer different than the first manufacturer (the control system of the second manufacturer implements a second proprietary communication protocol between the processing units).

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Номер записи: 52

11-10-2012 дата публикации

Electronic device with card interface

Номер: US20120260001A1

Автор: Akihisa Fujimoto, Hiroyuki Sakamoto, Kosei Okamoto, Masao Suga

Принадлежит: Toshiba Corp

When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

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Номер записи: 53

18-10-2012 дата публикации

System and method of indirect register access

Номер: US20120265970A1

Автор: Gavin Huggins, Harold B Noyes, Mark Jurenka

Принадлежит: Micron Technology Inc

Systems and methods are provided for managing access to registers. A system may include a set of direct registers and a set of indirect registers. The indirect registers may be accessed through the direct registers, and the direct registers may provide various features to provide faster access to the indirect registers. One of the direct registers may indicate access modes for accessing the indirect registers. The access modes may include auto-increment, auto-decrement, auto-reset, and no change modes. Based on the access mode, the currently accessed address may be automatically modified after accessing the indirect register at the address.

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Номер записи: 54

18-10-2012 дата публикации

Memory device including memory controller

Номер: US20120266045A1

Автор: Hiroshi Sukegawa

Принадлежит: Hiroshi Sukegawa

A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory.

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Номер записи: 55

25-10-2012 дата публикации

Data transfer system and data transfer method

Номер: US20120271973A1

Автор: Masaharu Adachi

Принадлежит: Ricoh Co Ltd

A data transfer system includes: a processor; a main memory that is connected to the processor; a peripheral controller that is connected to the processor; and a peripheral device that is connected to the peripheral controller and includes a register set, wherein the peripheral device transfers data stored in the register set to a predetermined memory region of the main memory or the processor by a DMA (Data Memory Access) transfer, and the processor reads out the data transferred to the memory region by the DMA transfer without accessing to the peripheral device.

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Номер записи: 56

01-11-2012 дата публикации

Reconfigurable memory module and method

Номер: US20120278524A1

Автор: Joseph M. Jeddeloh, Terry R. Lee

Принадлежит: Round Rock Research LLC

A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

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Номер записи: 57

01-11-2012 дата публикации

METHOD AND SYSTEM FOR COUPLING SERIAL ATTACHED SCSI (SAS) DEVICES AND INTERNET SMALL COMPUTER SYSTEM INTERNET (iSCSI) DEVICES THROUGH SINGLE HOST BUS ADAPTER

Номер: US20120278551A1

Автор: Madhukar Gunjan Chakhaiyar, Mahmoud K. Jibbe

Принадлежит: LSI Corp

An apparatus comprising an interface, a first port, and a second port. The interface may be configured to connect to a host computer. The first port may be configured to connect to a first set of storage devices using a first protocol. The second port may be configured to connect to a second set of storage devices using a second protocol. The apparatus may provide support for the first protocol and the second protocol to allow communication using both the first protocol and the second protocol through the interface.

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Номер записи: 58

08-11-2012 дата публикации

Zone group manager virtual phy

Номер: US20120284435A1

Автор: Balaji Natrajan, Michael G. Myrah, Sohail Hameed

Принадлежит: Hewlett Packard Development Co LP

A switch is provided. The switch includes an expander configured to couple a server to a set of storage drive bays. The switch also includes a zone manager coupled to the expander and configured to maintain a zoning configuration corresponding to the set of storage drive bays. The zone manager is coupled to the expander through a virtual PHY.

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Номер записи: 59

08-11-2012 дата публикации

Constituting a control system with virtual and physical backplanes and modules as building blocks

Номер: US20120284447A1

Автор: Richard J. Grgic, Subbian Govindaraj

Принадлежит: Rockwell Automation Technologies Inc

A custom control system created based on combinations of software applications and hardware control and communication modules overlaid in a virtual backplane. The user can select the modules of interest and map them together without the loss of communications between the modules while the control system is configured and overlaid. The user can then archive the system design and implement the system with a greater level of confidence in the ability of the design to meet the requirements of the application while reducing the costs of the implementation.

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Номер записи: 60

15-11-2012 дата публикации

Data transfer apparatus and data transfer method

Номер: US20120290746A1

Автор: Akiyoshi Momoi, Chuma Nagao, Daisuke Shiraishi, Takeshi Hiraoka

Принадлежит: Canon Inc

A packet accompanying data valid information is transferred at high efficiency within an integrated circuit or between integrated circuits. A character indicating data enable information is provided and an identifier indicating a data enable character is assigned onto the packet. When the data enable information is valid in series, the data enable characters are eliminated from the packet to be transferred.

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Номер записи: 61

15-11-2012 дата публикации

Managing Bandwidth Allocation in a Processing Node Using Distributed Arbitration

Номер: US20120290756A1

Автор: Abhijeet Ashok Chachad, David Quintin Bell, Dheera Balasubramanian, Raguram Damodaran, Roger Kyle Castille

Принадлежит: Texas Instruments Inc

Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate arbitration point is associated with each target resource. An access priority value is assigned to each requester. An arbitration contest is performed for access to a first target resource by requests from two or more of the requesters using a first arbitration point associated with the first target resource to determine a winning requester. The request from the winning requester is forwarded to a second target resource. A second arbitration contest is performed for access to the second target resource by the forwarded request from the winning requester and requests from one or more of the plurality of requesters using a second arbitration point associated with the second target resource.

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Номер записи: 62

22-11-2012 дата публикации

Method and apparatus of server i/o migration management

Номер: US20120297091A1

Автор: Futoshi Haga

Принадлежит: HITACHI LTD

In an information system, for I/O migration, the migration management module detects a first I/O function associated with a first I/O device to which the OS is connected, selects a second I/O function associated with a second I/O device which is the same type of the first I/O device, and instructs to hot-add the second I/O function to the OS. And the OS sets a teaming for a first virtual MAC address of a first virtual NIC corresponding to the first I/O function and a second virtual MAC address of a second virtual NIC corresponding to the second I/O function, and disconnects the first virtual MAC address of the first virtual NIC corresponding to the first I/O function.

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Номер записи: 63

22-11-2012 дата публикации

Motherboard of computing device

Номер: US20120297132A1

Автор: Bo Tian, Guo-Yi Chen

Принадлежит: Hon Hai Precision Industry Co Ltd, Hongfujin Precision Industry Shenzhen Co Ltd

A motherboard of a computing device includes a dual inline memory module (DIMM), a processor socket, a platform controller hub (PCH), a switch, and a switch controller. The DIMM is connected to the processor socket or the PCH through the switch controller. The switch is connected to the switch controller, and generates a signal when the switch is operated. The switch controller controls the DIMM to connect either to the processor socket or to the PCH according to the signal, so that a solid state disk (SSD) or a memory that is connected to the DIMM can be supported appropriately by the motherboard.

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Номер записи: 64

29-11-2012 дата публикации

Transmission control device, memory control device, and plc including the transmission control device

Номер: US20120303915A1

Автор: Eitarou Hioki

Принадлежит: Mitsubishi Electric Corp

A transmission control device in the present invention includes: a data storage memory in which data are written; a plurality of data copy memories into which the data written in the data storage memory are copied; an unread copy-memory selection unit that selects one of the data copy memories for which reading of data is not performed from among the data copy memories; a memory copy unit that copies the data written in the data storage memory into a data copy memory selected by the unread copy-memory selection unit; a read copy-memory selection unit that selects a data copy memory into which the memory copy unit copies data from among the data copy memories; and a data output unit that reads data from a data copy memory selected by the read copy-memory selection unit and outputs the read data to a transmission unit.

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Номер записи: 65

06-12-2012 дата публикации

Facilitating routing by selectively aggregating contiguous data units

Номер: US20120311180A1

Автор: Howard M. Haynie, Jeffrey M. Turner, Kathy S. BARKEY

Принадлежит: International Business Machines Corp

Aggregation of contiguous data packets, such as contiguous I/O adapter stores, is disclosed. Commensurate with receiving data packets to be written to a memory, multiple contiguous data units of the data packets are aggregated into an aggregated data block. The aggregated data block is validated for writing to memory responsive to either the aggregated data block reaching a size which with inclusion of a next contiguous data unit in the aggregated data block would result in the aggregated data block exceeding a configurable size limit, or a next data unit of the plurality of data units to be written to memory being non-contiguous with the multiple contiguous data units.

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Номер записи: 66

06-12-2012 дата публикации

Avoiding non-posted request deadlocks in devices

Номер: US20120311212A1

Автор: Carl A. Bender, Jeffrey C. Hanscom, Thomas D. Needham

Принадлежит: International Business Machines Corp

Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations.

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Номер записи: 67

06-12-2012 дата публикации

Avoiding non-posted request deadlocks in devices

Номер: US20120311213A1

Автор: Carl A. Bender, Jeffrey C. Hanscom, Thomas D. Needham

Принадлежит: International Business Machines Corp

Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations.

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Номер записи: 68

06-12-2012 дата публикации

Implementing device physical location identification in serial attached scsi (sas) fabric using resource path groups

Номер: US20120311222A1

Автор: Brian L. Bowles, Laurel Scaife, Robert E. Galbraith

Принадлежит: International Business Machines Corp

A method and controller for implementing device physical location identification in a Serial Attached SCSI (SAS) fabric using resource path groups, and a design structure on which the subject controller circuit resides are provided. The device physical location identification includes a Resource Path Group (RPG). Each RPG provides a unique persistent physical locator of a storage device in the system. Each RPG including at least two Resource Paths (RPs) and each RP has a fixed size identifying a type and a series of egress ports. A persistent RPG is stored within the device metadata on the storage device.

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Номер записи: 69

13-12-2012 дата публикации

Storage architecture for backup application

Номер: US20120317379A1

Автор: Abid Ali, Amit Singla, Pankaj Khanzode, Sachin Durge, Vanita Prabhu, Vijay Sen

Принадлежит: Microsoft Corp

Aspects of the subject matter described herein relate to a storage architecture. In aspects, an address provided by a data source is translated into a logical storage address of virtual storage. This logical storage address is translated into an identifier that may be used to store data on or retrieve data from a storage system. The address space of the virtual storage is divided into chunks that may be streamed to the storage system.

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Номер записи: 70

27-12-2012 дата публикации

System and method of processing seismic data on a co-processor device

Номер: US20120331191A1

Автор: Oliver Pell, Raymond Ergas, Tamas Nemeth

Принадлежит: Chevron USA Inc

A system and method for processing seismic data on one or more co-processor devices that are operatively coupled to a host computing system via a communications channel. The compression of input data transmitted to the co-processor device and/or the size of the storage provided on the co-processor device may enhance the efficiency of the processing of the data on the peripheral device by obviating a bottleneck caused by the relatively slow transfer of data between the host computing system and the co-processor device or by the relatively slow transfer of data within the co-processor device between the co-processor information storage and the co-processor.

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Номер записи: 71

27-12-2012 дата публикации

Programmable mechanism for synchronous strobe advance

Номер: US20120331324A1

Автор: Darius D. Gaskins, James R. Lundberg

Принадлежит: Via Technologies Inc

An apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, a core clocks generator, and a synchronous strobe driver. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to advance a synchronous data strobe associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The core clocks generator is coupled to the ratio bus and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount.

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Номер записи: 72

27-12-2012 дата публикации

Delivering Interrupts Directly To A Virtual Processor

Номер: US20120331467A1

Автор: Andrew V. Anderson, Erik C. Cota-Robles, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard A. Uhlig, Sebastian Schoenberg, Sridhar Muthrasanallur, Steven M. Bennett, Udo Steinberg

Принадлежит: Individual

Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

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Номер записи: 73

03-01-2013 дата публикации

System and method for providing remote device driver

Номер: US20130007317A1

Автор: Hyung Su Seo, Jong Ho Kim

Принадлежит: Rsupport Co Ltd

Provided is a system and method for providing a remote device driver. The system includes a first device configured to request device information from a terminal connected through a universal serial bus (USB) interface and transmit device information provided from the terminal in response to the request via a network, and a second device connected with the first device via the network and configured to load a driver for driving the terminal on the basis of the device information on the mobile terminal received from the first device. Accordingly, it is possible to drive and control a mobile terminal at a remote location without installing a function driver directly on a computer that is physically connected with the mobile terminal.

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Номер записи: 74

03-01-2013 дата публикации

System and method for improving ecc enabled memory timing

Номер: US20130007320A1

Автор: Saya Goud Langadi

Принадлежит: Texas Instruments Inc

A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes a memory, and is configured to generate a first ready signal and a second ready signal. The first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves. The second ready signal is generated independent of the error check in each of the plurality of slaves.

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Номер записи: 75

03-01-2013 дата публикации

Requests and data handling in a bus architecture

Номер: US20130007321A1

Автор: Jason Meredith

Принадлежит: Imagination Technologies Ltd

Aspects relate to methods and systems for processing requests and sending data in a bus architecture. At least one master device is connected to at least two slave devices via a bus. An allocator allocates incoming requests from the master device to a target slave device. Incoming requests are buffered for the respective slave device. The master device sends a read request for a first slave device to the bus; the allocator generates a current-state indicator associated with the read request. The allocator generates a priority indicator associated with the read request. If the initial value of the current-state indicator equals the value of the priority indicator, the read request is processed; or if the initial value of the current-state indicator does not equal the value of priority indicator, the read request is deferred until a later time.

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Номер записи: 76

10-01-2013 дата публикации

Data transfer control device and data transfer control method

Номер: US20130013821A1

Автор: Masaki Okada

Принадлежит: Fujitsu Semiconductor Ltd

A data transfer control device that selects one of a plurality of DMA channels and transfers data to or from memory includes a request holding section configured to hold a certain number of data transfer requests of the plurality of DMA channels and a request rearranging section configured to select and rearrange the data transfer requests that are held in a basic transfer order so that the data transfer requests of each of the plurality of DMA channels are successively outputted for a number of successive transfers set in advance.

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Номер записи: 77

10-01-2013 дата публикации

High Speed USB Hub with Full Speed to High Speed Transaction Translator

Номер: US20130013823A1

Автор: Terry R. Altmayer

Принадлежит: Individual

High speed USB hub with full speed to high speed transaction translator. A USB hub may include an upstream port for coupling to a host and one or more downstream ports for coupling to downstream devices. The downstream devices may operate at USB high speed. The USB hub may support hosts which operate at speeds less than high speed (e.g., full speed). Accordingly, when a host operates at a lower speed, a transaction translator may convert the communications from the host from the lower speed to the high speed. Accordingly, the downstream device may still operate at high speed even when the host operates at a lower speed.

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Номер записи: 78

10-01-2013 дата публикации

Bus monitoring device, bus monitoring method, and program

Номер: US20130013832A1

Автор: Akira Ueno, Yoshinobu Tanaka

Принадлежит: Olympus Corp

A bus monitoring device may include a measurement unit configured to measure a bandwidth of data on a common bus for a unit time, which is constant and predetermined, based on transfer information indicating a state of exchange of the data when a plurality of processing blocks connected to the common bus exchange the data via the common bus with a memory including an address space having a plurality of banks.

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Номер записи: 79

10-01-2013 дата публикации

Underlaying device for a computer device

Номер: US20130013837A1

Автор: Yu Chia Liu

Принадлежит: KAIJET Tech INTERNATIONAL Ltd

An underlaying device includes a main signal port, an expanding signal port, a signal process component, and a power connector. The main signal port is receiving and sending a communication signal from/to the computer device by means of a main signal wire. The expanding signal port is receiving and sending the communication signal from/to an external expanding device. The signal process component is coupled between the main signal port and the expanding signal port for transforming the communication signal into a signal which is able to be received and sent between the main signal port and the expanding signal port. The power connector is supplying power by means of a power wire. The underlaying device is suitable for various computer devices and is able to integrate the functionality of connection ports.

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Номер записи: 80

10-01-2013 дата публикации

Hot-swapping active memory for virtual machines with directed i/o

Номер: US20130013877A1

Автор: Kun Tian

Принадлежит: Intel Corp

Embodiments of the invention describe a DMA Remapping unit (DRU) to receive, from a virtual machine monitor (VMM), a hot-page swap (HPS) request, the HPS request to include a virtual address, in use by at least one virtual machine (VM), mapped to a first memory page location, and a second memory page location. The DRU further blocks DMA requests to addresses of memory being remapped until the HPS request is fulfilled, copies the content of the first memory page location to the second memory page location, and ramps the virtual address from the first memory page location to the second memory page location.

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Номер записи: 81

17-01-2013 дата публикации

Apparatus for peer-to-peer communication over a universal serial bus link

Номер: US20130019035A1

Автор: Ming-Te Chang

Принадлежит: Ours Technology Inc

An apparatus for peer-to-peer communication over a Universal Serial Bus (USB) link, the apparatus comprising a USB 3.0 compliant switch to be coupled between a first peer unit and a second peer unit to form a first path, wherein each of the first peer unit and the second peer unit supports a USB type of communication a USB 2.0 compliant bridge to be coupled between the first peer unit and the second peer unit to form a second path a detector to detect the USB type of each of the first peer unit and the second peer unit and a controller to establish the USB type of communication between the first peer unit and the second peer unit over a USB link via the first path or the second path, wherein the controller is configure to selectively switch the USB link to the first path or the second path based on the USB types of the first peer unit and the second peer unit.

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Номер записи: 82

17-01-2013 дата публикации

Multi-partitioning of memories

Номер: US20130019058A1

Автор: Danilo Caraccio, Emanuele Confalonieri, Federico Tiziani

Принадлежит: Individual

Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

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Номер записи: 83

24-01-2013 дата публикации

Multicore processor system, computer product, and control method

Номер: US20130024588A1

Автор: Hiromasa Yamauchi, Hitoshi Ikeda, Kiyoshi Miyazaki, Koichiro Yamashita

Принадлежит: Fujitsu Ltd

A multicore processor system includes a core configured to detect a change in a state of assignment of a multicore processor; obtain, upon detecting the change in the state of assignment, number of accesses of a common resource shared by the multicore processor by each of process that are assigned to cores of the multicore processor; calculate an access ratio based on the obtained number of accesses; and notify an arbitration circuit of the calculated access ratio, the arbitration circuit arbitrating accesses of the common resource by the multicore processor.

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Номер записи: 84

31-01-2013 дата публикации

Using a dma engine to automatically validate dma data paths

Номер: US20130031281A1

Автор: Jane W. Yan, John R. Feehrer, Matthew G. Noel

Принадлежит: Oracle International Corp

The disclosed embodiments provide a system that uses a DMA engine to automatically validate DMA data paths for a computing device. During operation, the system configures the DMA engine to perform a programmable DMA operation that generates a sequence of memory accesses which validate the memory subsystem and DMA paths of the computing device. For instance, the operation may include a sequence of reads and/or writes that generate sufficient data traffic to exercise the computing device's I/O controller interface and DMA data paths to memory to a specified level. The system initiates this programmable DMA operation, and then checks outputs for the operation to confirm that the operation executed successfully.

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Номер записи: 85

28-02-2013 дата публикации

Integrating Intellectual Property (IP) Blocks Into A Processor

Номер: US20130054845A1

Автор: Aimee D. Wood, James A. Beavens, Jeff V. Tran, Lily P. Looi, Marcus W. Song, Prashanth Nimmala, Robert J. Greiner, Rupin H. Vakharwala

Принадлежит: Intel Corp

In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.

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Номер записи: 86

28-02-2013 дата публикации

High Priority Command Queue for Peripheral Component

Номер: US20130054875A1

Автор: Diarmuid P. Ross, Douglas C. Lee

Принадлежит: Apple Inc

In an embodiment, a peripheral component may include a low priority command queue configured to store a set of commands to perform a transfer on a peripheral interface and a high priority command queue configured to store a second set of commands to perform a transfer on the interface. The commands in the low priority queue may include indications which identify points at which the set of commands can be interrupted to perform the second set of commands. A control circuit may be coupled to the low priority command queue and may interrupt the processing of the commands from the low priority queue responsive to the indications, and may process commands from the high priority command queue.

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Номер записи: 87

14-03-2013 дата публикации

Management server, method of managing workform and recording medium

Номер: US20130063772A1

Автор: Hyun-jin BAE

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A management server is provided. The management server includes a user interface to receive an input of a plug-in corresponding to a job of an image forming apparatus to generate a workform, which defines a job performing order of the image forming apparatus, and to receive an input of an execution start condition of the plug-in, a workform generator to generate a workform based on the input plug-in and the execution start condition, and a communication interface to transmit the generated workform to the image forming apparatus.

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Номер записи: 88

14-03-2013 дата публикации

Methods and devices for universal serial bus port event extension

Номер: US20130067128A1

Автор: Terence C. Sosniak

Принадлежит: Individual

Methods and apparatus for implementing a port management protocol which can be used to manage communication between one or more USB devices and a USB host at a distance greater than that allowed by the USB Specifications are provided. In one aspect, a method for prolonging a bus event of a USB device at least until a notification is received that a corresponding bus event has been completed by the USB host is provided; and subsequently exchanging bus traffic between the USB host and USB device upon completion of the bus event by both devices.

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Номер записи: 89

21-03-2013 дата публикации

Low latency, high bandwidth data communications between compute nodes in a parallel computer

Номер: US20130073752A1

Автор: Michael A. Blocksome

Принадлежит: International Business Machines Corp

Methods, systems, and products are disclosed for data transfers between nodes in a parallel computer that include: receiving, by an origin DMA on an origin node, a buffer identifier for a buffer containing data for transfer to a target node; sending, by the origin DMA to the target node, a RTS message; transferring, by the origin DMA, a data portion to the target node using a memory FIFO operation that specifies one end of the buffer from which to begin transferring the data; receiving, by the origin DMA, an acknowledgement of the RTS message from the target node; and transferring, by the origin DMA in response to receiving the acknowledgement, any remaining data portion to the target node using a direct put operation that specifies the other end of the buffer from which to begin transferring the data, including initiating the direct put operation without invoking an origin processing core.

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Номер записи: 90

21-03-2013 дата публикации

NOVEL CIRCUIT AND METHOD FOR COMMUNICATING VIA A SINGLE LINE

Номер: US20130073757A1

Автор: Kalb Franziska, Rettig Rasmus

Принадлежит:

A method for transmitting logical information from a transmitter to a receiver via a single line, the receiver being connected to the transmitter by the line, the receiver placing a first signal on the line and the first signal being made up of alternating recessive and dominant levels, the transmitter placing a second signal on the line and the second signal being superposed on the line by the transmitter at least in the segments in which the first signal has a recessive level, the second signal being made up of a sequence of recessive and dominant levels, and the receiver determining from the second signal the logical information that is to be received. 113-. (canceled)14. A method for transmitting logical information from a transmitter to a receiver via a single line , the receiver being connected to the transmitter by the line , the method comprising:placing, using the receiver, a first signal on the line, the first signal being made up of alternating recessive and dominant levels;placing, using the transmitter, a second signal on the line, the second signal being superposed on the line by the transmitter at least in the segments in which the first signal has a recessive level, the second signal being made up of a sequence of recessive and dominant levels; anddetermining, using the receiver, from the second signal, the logical information that is to be received.15. The method of claim 14 , wherein the transmitted logical information is configuration information for initializing one of a control device claim 14 , a component claim 14 , and a bus connection unit.16. The method of claim 14 , wherein the first signal is made up of a sequence having a prespecified or prespecifiable number of rectangular pulses claim 14 , at least one of the duration of the recessive line level and the duration of the dominant line level within the sequence being approximately constant.17. The method of claim 14 , wherein the transmitter begins the superposition of the second signal ...

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Номер записи: 91

21-03-2013 дата публикации

AS-I COMMUNICATION COMPONENT

Номер: US20130073760A1

Автор: WIESGICKL Bernhard

Принадлежит: SIEMENS AKTIENGESELLSCHAFT

A communication component is disclosed for communication via an AS-i line. In order to provide an improved AS-i communication component for communication via an AS-i line, it is proposed in at least one embodiment that a standard AS-i signal and an extended AS-i communication signal are sent and/or received via an AS-i line using a shared communication component. 1. A communication component for communication by way of an AS-i line , wherein a standard AS-i communication signal and an extended AS-i communication signal are at least one of sendable and receiveable by way of the AS-i line by way of the common communication component , wherein a frequency spectrum of the extended AS-i communication signal , used for at least one of sending and receiving , lies in the range of 1 MHz to 10 MHz.2. The communication component of claim 1 , wherein the communication component is an ASIC or an FPGA chip.3. The communication component of claim 1 , wherein the frequency spectrum of the standard AS-i communication signal used for at least one of sending and receiving lies in the range of 50 kHz to 500 kHz and the frequency spectrum of the extended AS-i communication signal used for at least one of sending and receiving lies in the range of 1 MHz to 10 MHz.4. The communication component of claim 1 , wherein the communication component uses the Orthogonal Frequency Division Multiplex method for at least one of sending and receiving the extended AS-i communication signal.5. The communication component of claim 1 , further comprising:a first analog to digital converter unit for receiving the standard AS-i communication signal; anda second analog to digital converter unit for receiving the extended AS-i communication signal.6. The communication component of claim 1 , further comprising:a shared analog to digital converter unit for receiving the standard AS-i communication signal and the extended AS-i communication signal.7. The communication component of claim 5 , further comprising: ...

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Номер записи: 92

21-03-2013 дата публикации

ASYNCHRONOUS PROTOCOL CONVERTER

Номер: US20130073771A1

Автор: Hanyu Takahiro, Onizawa Naoya

Принадлежит: TOHOKU UNIVERSITY

An asynchronous protocol converter, which is capable of flexibly carrying out communications between tens of IP cores in an asynchronous protocol Network-on-Chip system, and which is multiple input multiple output is provided. In an LSI (), which comprises a plurality of IP cores (), and routers () positioned adjacent to the plurality of IP cores (), an asynchronous protocol converter () is positioned between adjacent routers (). The asynchronous protocol converter () is configured to comprise: a two-to-four-phase converter () that is connected to an adjacent router () within the LSI (); a four-phase pipelined router () that is connected on the output side of the two-to-four-phase converter (); a four-to-two-phase converter () that is connected to the outputs of the four-phase pipelined router (); an input controller () that controls the two-to-four-phase converter (); and an output controller () that controls the four-to-two-phase converter (). 1. An asynchronous protocol converter provided between neighboring routers in an LSI including a plurality of IP cores and a router provided adjacent to the plurality of IP cores , comprising:a two-to-four-phase converter connected to the neighboring router in the LSI;a four-phase pipelined router connected to the output side of the two-to-four-phase converter;a four-to-two-phase converter connected to an output of the four-phase pipelined router;an input controller for controlling the two-to-four-phase converter; andan output controller for controlling the four-to-two-phase converter.2. An asynchronous protocol converter provided between neighboring routers in an LSI including a plurality of IP cores and a router provided adjacent to the plurality of IP cores , comprising:a two-to-four-phase converter connected to the neighboring router in the LSI;a four-phase pipelined router connected to the output side of the two-to-four-phase converter;a four-to-two-phase converter connected to an output of the four-phase pipelined ...

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Номер записи: 93

21-03-2013 дата публикации

SYSTEMS AND METHODS FOR IMAGE STREAM PROCESSING

Номер: US20130073775A1

Автор: Brown Joel, Siewert Charles, Wade Jack

Принадлежит:

Various embodiments relate to systems and methods for simultaneously switching input image streams to output devices, while providing optional image processing functions on the image streams. Certain embodiments may provide vision systems and methods suitable for use in vehicles, particularly windowless vehicles, such as armored ground vehicles, submerged watercraft, and spacecraft. Some embodiments may enable sharing of image streams (e.g., with one or more other vehicles), generation of panoramic views (e.g., from various camera feeds), intelligent encoding of image streams, and implementation of security features based on image streams. 1. A system for image stream processing , comprising:an image stream input interface;an image stream output interface;a first image processing module configured to accept a plurality of image streams, stitch at least two image streams from the plurality of image streams into a contiguous image stream, and output the contiguous image stream, wherein the plurality of image streams comprises an image stream from the image stream input interface or from another image processing module;a second image processing module; and selectively map the image stream from the image stream input interface or from the second image processing module, to the first image processing module, and', 'selectively map the contiguous image stream from the first image processing module to the image stream output interface or to the second image processing module., 'a switching matrix in communication with the image stream input interface, the image stream output interface, the first image processing module, and the second image processing module, wherein the switching matrix is configured to2. The system of claim 1 , further comprising a plurality of image stream input interfaces claim 1 , the plurality of image stream input interfaces being in communication with the switching matrix and including the image stream input interface claim 1 , wherein at least two ...

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Номер записи: 94

28-03-2013 дата публикации

Dynamically Determining A Primary Or Slave Assignment Based On An Order Of Cable Connection Between Two Devices

Номер: US20130080669A1

Автор: Adrian X. Rodriguez, Charles A. Cole, Jared T. Siirila, Phillip D. Jones, Ping Zhou

Принадлежит: International Business Machines Corp

Methods, apparatuses, and computer program products for dynamically determining a primary or slave assignment based on an order of cable connection between two devices are provided. Embodiments include detecting, by a first device, insertion of one end of a cable into a port of the first device; determining, by the first device, whether a power signal is received from the cable at the port of the first device; if the power signal is received, performing, by the first device, a data transfer operation over the cable as a slave device to a second device that is coupled to the other end of the cable; and if the power signal is not received, performing, by the first device, a data transfer operation over the cable as a primary device to the second device that is coupled to the other end of the cable.

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Номер записи: 95

28-03-2013 дата публикации

Source Core Interrupt Steering

Номер: US20130080674A1

Автор: Foong Annie, Veal Bryan E.

Принадлежит:

An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein. 1. At least one machine readable medium comprising instructions that when executed on a computing device cause the computing device to perform a method comprising:receiving a core identifier that corresponds with a source core that is included in a processor;receiving an input/output request, produced and originating from the source core, that is associated with the core identifier;storing the core identifier in a memory coupled to the processor;directing an interrupt, which corresponds to the request, to the source core based on the core identifier;wherein the processor is coupled to an additional core and the request includes the core identifier.2. The at least one medium of claim 1 , the method comprising directing the interrupt to the source core claim 1 , but not the additional core claim 1 , based on the core identifier.3. The at least one medium of claim 2 , the method comprising directing a message-signaled interrupt message to the source core based on the core identifier.4. The at least one medium of claim 1 , the method comprising determining a message-signaled interrupt address based on the core identifier.5. The at least one medium of claim 1 , the method comprising storing the core identifier in the memory before directing the interrupt to the source core.6. At least one machine readable medium comprising instructions that when executed on a computing device cause the computing device to perform a method comprising:receiving an input/output request, produced and originating from a source core, which includes a message-signaled interrupt (MSI) message that corresponds ...

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Номер записи: 96

04-04-2013 дата публикации

Supporting Multiple Channels Of A Single Interface

Номер: US20130086288A1

Автор: Blaise Fanning, Eran Tamari, Joseph Murray, Michael T. Klinglesmith, Mikal C. Hunsaker, Rohit R. Verma, Sridhar Lakshmanamurthy

Принадлежит: Intel Corp

In one embodiment, the present invention includes a method for receiving a request for a transaction from a first agent in a fabric and obtaining an address, a requester identifier, a tag, and a traffic class of the transaction, and determining a channel of a target agent to receive the transaction based on at least two of the address, the requester identifier, the tag, and the traffic class. Based on this channel determination, the transaction can be sent to the channel of the target agent. Other embodiments are described and claimed.

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Номер записи: 97

04-04-2013 дата публикации

INTERRUPTION FACILITY FOR ADJUNCT PROCESSOR QUEUES

Номер: US20130086289A1

Автор: Gainey, JR. Charles W., Meissner Klaus, Osisek Damian L., Werner Klaus

Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions. 1. A method for making a computer program product for facilitating processing of queues of a processing environment , the method comprising:first assembling instructions for causing a computer to determine that a queue of the processing environment has transitioned from a no replies pending state to a reply pending state, wherein the queue is indirectly accessible to user programs, and wherein the no replies pending state is a state in which the queue is empty, and the reply pending state is a state in which the queue is not empty, and storing the first assembling instructions on a tangible computer storage medium;second assembling instructions for causing a computer to enable the queue for interruption, the enabling comprising employing a process adjunct processor queue (PQAP) instruction to enable the queue for interruption, wherein the PQAP instruction employs general registers 0, 1 and 2 for input, and general register 1 for output, and storing the second assembling instructions on a tangible computer storage medium; andthird assembling instructions for causing a computer to initiate, by a processor, an interrupt for the queue, wherein the initiating is based on enabling the queue and determining that the queue has transitioned from the no replies pending state to the reply pending state, wherein the interrupt is initiated based on the queue transitioning from an empty state to a non-empty state, and the interrupt is not initiated based on the queue not transitioning from the empty state to the non-empty state, and storing the third assembling instructions on a tangible computer storage medium. ...

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Номер записи: 98

04-04-2013 дата публикации

COMMUNICATION CONTROL SYSTEM, SWITCHING NODE, COMMUNICATION CONTROL METHOD AND COMMUNICATION CONTROL PROGRAM

Номер: US20130086295A1

Автор: Hayashi Masashi, Hidaka Youichi, Izawa Tetsu, Okamoto Tsugio, Phila Vongh Minaxay, Sato Shihomi, Takashima Masanori, Tsuchiya Koichi, Yokota Takashi

Принадлежит:

In a switching node, high-speed and advanced service protocol processing function is achieved by utilizing an external control server without affecting performance of conventional service protocol processing. Specifically, a forwarding engine has PCI express and an LAN interface. Depending on a type of an input packet, destination of the packet is switched to the PCI express side for conventional network service and to the LAN interface side for extended network service that cooperates with the external control server. A CPU having the PCI express and the LAN interface is provided ahead of the LAN interface. The CPU performs communication of service inquiry with the external control server at high speed via the LAN interface. After response from the control server is obtained, setting of the forwarding engine is performed through the PCI express. 1. A communication control system comprising:a switching node configured to execute conventional network service; anda control server configured to execute extended network service,wherein said switching node comprises:a first internal bus used for forwarding a frame for internal processing;a second internal bus for forwarding a frame for external transmission; anda forwarding engine configured to operate depending on a type of an input frame, to forward a frame regarding said conventional network service to said first internal bus for internal processing in said switching node, and to forward a frame regarding said extended network service to said second internal bus for utilizing said control server.2. The communication control system according to claim 1 ,wherein said switching node further comprises:a first processor configured to receive a frame from said forwarding engine through said first internal bus and to execute said conventional network service; anda second processor configured to receive a frame from said forwarding engine through said second internal bus, to perform processing related to said extended network ...

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Номер записи: 99

11-04-2013 дата публикации

MODULAR INTEGRATED CIRCUIT WITH COMMON INTERFACE

Номер: US20130091316A1

Автор: Bhasin Vinay, Flake Lance Leslie, Fullerton Mark N., Hayek Claude G., III Lawrence J., Kharwa Bhupesh, Liu Sam, Madar, Morris Robert, Nath Joyjit, Zhao Chaoyang

Принадлежит: BROADCOM CORPORATION

A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format. 1. A modular integrated circuit comprising:a plurality of spoke modules; and a power management unit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of power supply signals to the plurality of spoke modules via the plurality of hub interfaces; and', 'a clock control circuit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of clock signals to the plurality of spoke modules via the plurality of hub interfaces;', 'wherein the plurality of hub interfaces provides a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format., 'a hub module that is coupled to the plurality of spoke modules to facilitate inter-spoke communications via a corresponding plurality of hub interfaces, the hub module including2. The modular integrated circuit of wherein the common signaling format for each of the plurality of hub interfaces includes:a clock request signal received from a corresponding one of the plurality of spoke modules; andat least one of the plurality of clock signals.3. The modular integrated circuit of wherein the common signaling format for each of the plurality of hub interfaces includes:a power ...

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