Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement

A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first conductive layer including segments which are conductive, including forming first segments designated for a first reference voltage and second segments designated for a second reference voltage, and interspersing the first and second segments; relative to a first direction; and forming a second conductive layer over the first conductive layer, the second conductive layer including segments that are conductive, including forming third segments designated for the first reference voltage and fourth segments designated for the second reference voltage, interspersing the third and fourth segments relative to a second direction, the second direction being perpendicular to the first direction, and arranging the segments in the second conductive layer substantially asymmetrically including, relative to the first direction, locating each fourth segment substantially asymmetrically between corresponding ...

Extra-large scale integrated circuit detailed wiring method taking advanced technology into consideration

Method for improved cut metal patterning

A system for preparing an integrated circuit device design includes a memory for storing a plurality of preliminary integrated circuit design files; a processor for retrieving a preliminary integrated circuit design file from the memory; locating vertical abutments between adjacent device cell designs, identifying internal metal cuts on the adjacent device cell designs; determining and evaluating a horizontal spacing between the internal metal cuts a spacing threshold; and if the threshold is note met, shifting one cell horizontally relative to the other cell design by a predetermined distance to define a modified device layout, repeating the determining, evaluating, and shifting operations until the spacing threshold is satisfied; and identifying a next vertical abutment between and repeating the identifying, determining, shifting operations until the spacing threshold has been satisfied for all vertical abutments.

CONDUCTOR SCHEME SELECTION AND TRACK PLANNING FOR MIXED-DIAGONAL-MANHATTAN ROUTING

The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

ENGINEERING CHANGE ORDER CELL STRUCTURE HAVING ALWAYS-ON TRANSISTOR

A semiconductor cell structure includes four pairs of conductive segments, a first gate-strip, and a second gate-strip. A first conductive segment is configured to have a first supply voltage, and a second conductive segment is configured to have a second supply voltage. Each of the first gate-strip and the second gate-strip intersects an active zone over a channel region of a transistor. The first gate-strip is conductively connected to the second conductive segment. The semiconductor cell structure also includes a first dummy gate-strip and a second dummy gate-strip. The first dummy gate-strip separates from the first gate-strip by one CPP. The second dummy gate-strip separates from the second gate-strip by one CPP. The first gate-strip and the second gate-strip are separated from each other by two CPPs. The dummy gate-strip and the second dummy gate-strip are separated from each other by four CPPs.

Photoelectronic chip layout wiring method, device and equipment and storage medium

The invention discloses an optoelectronic chip layout wiring method, device and equipment and a storage medium, and relates to the technical field of optoelectronic chip layout automatic design wiring, and the method comprises the following steps: mapping an optoelectronic chip layout to a two-dimensional coordinate system, mapping a parameterization unit PCell port into a point coordinate, and setting the point coordinate as a point coordinate; mapping waveguides needing wiring into link line segments; initializing a photoelectron chip layout and a link, and generating a shortest link path between each group of PCell ports; cross waveguide device symbols are added in links, and/or control points are added to increase the number of bends and/or link line segments, so that the number of cross waveguide devices, the number of bends and the length of all links are consistent; and mapping the completed link path plan into waveguide routing, and mapping the crossed waveguide device symbol into ...

METHOD AND DEVICE FOR DESIGNING PIXEL CIRCUIT, CONTROLLER, AND STORAGE MEDIUM

The present application provides a method and a device for designing a pixel circuit, a controller, and a storage medium. The method includes: calling size information of a standard panel and characteristic label information of a plurality of standard devices, and combining with an architecture type identifier acquired to determine characteristic label information of at least one target device, in order to further determine a target pixel circuit to generate a target pixel circuit matrix comprising a plurality of the target pixel circuits.

Method and device for connecting programmable logic modules in FPGA (Field Programmable Gate Array) and electronic equipment

The invention discloses a method and a device for connecting programmable logic modules in an FPGA (Field Programmable Gate Array) and electronic equipment, which are characterized in that when different programmable logic modules in the FPGA are connected, if the condition of crossing other modules exists, the priority of each signal line is redistributed in the other modules; and arranging each type of signal line in other modules according to the redistributed priority, and finally realizing the connection consistency between different programmable logic modules. Therefore, by implementing the method and the device, the influence on the performance of modules with routing resource competition in other modules and the like is reduced by reasonably adjusting and distributing the routing resources, the connection consistency between different programmable logic modules in the FPGA is guaranteed, and finally, the global optimal effect in the FPGA is achieved.

IC ROUTING FOR SILICON CIRCUITS WITH SMALLER GEOMETRIES

A switch box approach to routing interconnects during the design of an integrated circuit (IC). Processing circuitry (e.g., via an automation tool) may determine a manner in which to interconnect functional blocks of the IC. The signal routes that interconnect the functional blocks can become complicated to comply with design rules for latency, crosstalk, etc. The processing circuitry may divide channels between functional blocks into multiple interconnection blocks, called channel blocks. In this way, the channel blocks may be considered as another block type (e.g., interconnection block) that the processing circuitry can leverage for routing signals between functional blocks.

Automatic routing system workflow

A computer-implementable method, a computing system, and a non-transitory computer-readable medium for automating workflow for routing metal wiring structures on an integrated circuit. The method automates, monitors, and controls all tasks for an auto-routing workflow. The method retrieves the auto-routing rules definition from a centrally stored location for easy maintenance. The method allows entry of wiring auto-routing constraints. The method enables customization per the design application to control signal integrity affected by the intrinsic routing metallization parasitic. The virtual copy of the layout database allows the layout database preparation without modifying the actual project layout. The virtual copy is used as an input for the workflow system. The method keeps the project layout database up to date.

Machine learning-based algorithm to accurately predict detail-route DRVS for efficient design closure at advanced technology nodes

A machine learning (ML) system is trained to predict the number of design rules violations of a circuit design that includes a multitude of Gcells. To achieve this, a netlist associated with the circuit design is placed by a place and route tool. A first list of features associated with the placed netlist is delivered to the ML system. A global route of the circuit design is performed by a global router. Next, a second list of features is delivered from the global router to the ML system. Thereafter, a detailed route of the circuit design is performed by a detailed router. A label associated with each Gcell in the circuit design is delivered to the ML system from the detailed route. The ML system is trained using the first and second list of features and the labels.

Wiring detection method and device for printed circuit board and computer-readable storage medium

Photoelectronic chip layout wiring method, device and equipment and storage medium

The invention discloses an optoelectronic chip layout wiring method, device and equipment and a storage medium, and relates to the technical field of optoelectronic chip layout automatic design wiring, and the method comprises the steps: mapping an optoelectronic chip layout into a grid, mapping a PCell port into a point coordinate, and mapping a waveguide needing wiring into a line segment; taking matts in the grid as basic units, and defining center coordinates of the matts, path crossing conditions and line segment combination modes passing through the center coordinates of the matts as variables; setting a path between the PCell ports and limiting conditions of points and line segments on the path; the length of the path is represented by using a variable, a corresponding variable value is calculated according to the equal-length path to be realized on the basis of a limiting condition so as to determine path planning, the path planning is mapped into waveguide routing, and Crossing ...

Integrated circuit including standard cell and method of manufacturing same

An integrated circuit is provided that includes standard cells arranged on a plurality of rows. The standard cell may include: a plurality of functional cells, each of which is implemented as a logic circuit; and a plurality of filling units including at least one first filling unit and at least one second filling unit, each filling unit including at least one of a back end line (BEOL) pattern, a middle line (MOL) pattern, and a front end line (FEOL) pattern, and wherein the at least one first filling unit and the at least one second filling unit have the same size as each other, and a density of one of the at least one pattern of the at least one first filling unit is different from a density of one of the at least one pattern of the at least one second filling unit.

MACHINE-LEARNING DRIVEN PREDICTION IN INTEGRATED CIRCUIT DESIGN

Training data is collected for each training integrated circuit (IC) design of a set of training IC designs by: extracting a first set of IC design features in a first stage of an IC design flow, and extracting a first set of IC design labels in a second stage of the IC design flow, where the first stage of the IC design flow occurs earlier than the second stage of the IC design flow in the IC design flow. Next, a machine learning model is trained based on the training data.

Relative placement by application of layered abstractions

Various embodiments described herein provide for a method and system for relative placement of components for a circuit layout by retrieving a data structure of a first circuit design, the data structure including a location of each component, determining a component characteristic for each component, and selecting a first group of two or more components having a shared component characteristic. Additionally, the method and system can instantiate a second circuit design and retrieve the data structure after the second circuit design is instantiated. The method and system include, for the second circuit design, calculating a first scaling factor and scaling each of the components of the first group from the first circuit design and placing the first group at a location in the second circuit design corresponding to location of the first group within the first circuit design.

METHOD OF CIRCULAR FRAME GENERATION FOR PATH ROUTING IN A MULTILAYER STRUCTURE, AND A COMPUTING DEVICE

A method of generating a circular frame and a computing device are provided. The method of generating a circular frame according to one embodiment includes identifying a plurality of path connection elements included in each layer of a multilayered structure with a plurality of layers that can have one or more links between adjacent layers; generating, for each layer of the multilayered structure, an embedded frame including the plurality of path connection elements identified in each layer of the multilayered structure; generating a topological frame including an outer boundary surrounding one or more punctures formed by the one or more links among the plurality of path connection elements included in the embedded frame and one or more local path points arranged on a boundary of each of the one or more punctures; and generating a circular frame composed of a single circular closed curve by merging the boundary of each of the one or more punctures and the outer boundary of the topological ...

METHOD OF CIRCULAR FRAME GENERATION FOR PATH ROUTING IN A MULTILAYER STRUCTURE, AND A COMPUTING DEVICE

Reinforcement learning global wiring method based on line generation and sequence selection

The invention discloses a reinforcement learning global wiring method based on line generation and sequence selection. The method comprises the steps that a target chip is divided into a plurality of grids, a grid chart is formed, the grid chart comprises a plurality of nodes, and each node represents a unit; and determining a path for connecting each node in the grid chart by using the constructed reinforcement learning wiring model so as to realize global wiring of the target chip, wherein the reinforcement learning model comprises a first intelligent agent and a second intelligent agent, the first intelligent agent completes preliminary wiring results of all networks according to the grid chart, and the second intelligent agent selects one network from the preliminary wiring results generated by the first intelligent agent to remove the network; the first intelligent agent is used for newly generating a wiring result of the network and calculating an updated reward value, and the second ...

Test line structure, semiconductor structure and method for forming test line structure

Test line structures are provided. A test line structure includes a semiconductor substrate, a plurality of diagnosis units and a plurality of first micro pad units. The diagnosis units are formed over the semiconductor substrate. Each of the diagnosis units includes a first interconnect structure having a first routing pattern. The first interconnect structures of the diagnosis units are connected in series to form a first test chain through the first micro pad units, and each of the first micro pad units is configured to connect the first interconnect structures of two adjacent diagnosis units in the first test chain. The first routing patterns of the first interconnect structures in the diagnosis units are different.

Method and layout of an integrated circuit

A method of manufacturing an integrated circuit includes identifying a first cell of a layout, placing a first pair of conductive patterns on a first set of routing tracks, placing a second pair of conductive patterns on a second set of routing tracks, and forming, by a first mask, a first set of conductive structures based on the first pair or second pair of conductive patterns. The first cell abuts a second cell. The first cell has a first set of routing tracks. The second cell has a second set of routing tracks. The first and second cell have a same cell height that is a non-integer multiple of a minimum pitch. A top and bottom boundary of the first cell overlaps a pair of the first set of routing tracks. A top and bottom boundary of the second cell overlaps a pair of the second set of routing tracks.

Parallel layer distribution method based on through hole perception under ultra-large scale integrated circuit

PARALLEL LAYER ALLOCATION METHOD BASED ON THROUGH-HOLE PERCEPTION UNDER SUPER-LARGE-SCALE INTEGRATED CIRCUIT

Disclosed is a parallel layer allocation method based on through-hole perception under a super-large-scale integrated circuit. A parallel policy based on area division is proposed in the method, wherein the load of each area can be balanced by means of perceiving the number of line networks in each area, thereby improving the efficiency of the parallel policy. A through-hole optimization policy based on line network equivalent wiring scheme perception is proposed in the method, wherein the priority of each line network on the usage of a wiring resource is determined by means of the difference in the number of line network 3D equivalent wiring schemes, thereby effectively reducing the number of through holes in a layer allocation scheme.

Conductor scheme selection and track planning for mixed-diagonal-Manhattan routing

The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

Integrated circuit including standard cells, method of manufacturing the integrated circuit, and computing system for performing the method

An integrated circuit includes a standard cell including a first output pin and a second output pin configured to each output the same output signal, a first routing path connected to the first output pin, and a second routing path connected to the second output pin. The first routing path includes a first cell group including at least one load cell, the second routing path includes a second cell group including at least one load cell, and the first routing path and the second routing path are electrically disconnected from each other outside the standard cell.

Conductor scheme selection and track planning for mixed-diagonal-manhattan routing

The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

DISCRETE DIFFERENTIAL EVOLUTION-BASED MULTI-STRATEGY OPTIMIZATION X-ARCHITECTURE MINIMUM TREE CONSTRUCTION METHOD

A discrete differential evolution-based multi-strategy optimization X-architecture minimum tree construction method, comprising the following steps: step S1, reading pin information of a circuit to be tested; step S2, initializing a population, calculating an individual adaptation value of the initial population, and initializing an adaptive parameter; step S3, determining whether the number of algorithm iterations reaches a threshold; step S4, if the threshold is not reached, randomly selecting a variation strategy from a strategy pool, and obtaining a child individual after variation and crossing; if the threshold value is reached, carrying out variation and crossing operations on the population according to a conventional differential evolution algorithm; step S5, adopting an immune clone selection strategy; step S6, determining whether iteration meets a termination condition, if yes, terminating iteration and outputting a final population, and otherwise, returning to step S3 to continue ...

PIN ACCESS HYBRID CELL HEIGHT DESIGN AND SYSTEM

A method of generating a layout diagram for an integrated circuit includes arranging a plurality of cells in the layout diagram, wherein each cell of the plurality of cells comprises a first power rail along a first boundary and a second power rail along a second boundary, and the first boundary is spaced from the second boundary in a first direction. The method further includes placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells in accordance with a design rule, wherein a first cell pin of the plurality of cell pins has a first end spaced from both the first power rail and the second power rail in the first direction.

Semiconductor device including standard-cell-adapted power grid arrangement and method for generating layout diagram of same

A semiconductor device includes: a power grid (PG) arrangement including: a conductive layer M(i) including segments which are conductive, where i is an integer and i≥0; and a conductive layer M(i+1) over the conductive layer M(i), the conductive layer M(i+1) including segments which are conductive; the M(i) segments including first and second segments designated correspondingly for first and second reference voltages, the first and second segments being interspersed and substantially parallel to a first direction; and the segments in the conductive layer M(i+1) including third and fourth segments designated correspondingly for the first and second reference voltages; the third and fourth segments being interspersed and substantially parallel to a perpendicular second direction; and wherein the segments in the conductive layer M(i+1) are arranged substantially asymmetrically such that each fourth segment is located, relative to the first direction, substantially asymmetrically between corresponding ...

Synchronous interconnection wiring method and system suitable for active substrate

The invention relates to a synchronous interconnection wiring method and system suitable for an active substrate. When the interconnection path is configured, the method comprises the following steps: searching and generating a feasible interconnection wiring path existing between two to-be-interconnected transpose connection circuits based on position distribution of the two to-be-interconnected transpose connection circuits; the feasible interconnection wiring paths generated through searching are corrected, selectable interconnection wiring paths are generated after correction, and all the selectable interconnection wiring paths have the same interconnection delay; optionally selecting a selectable interconnection wiring path, and configuring a signal transmission direction of each cross signal transmission circuit on the selectable interconnection wiring path based on the selected selectable interconnection wiring path, and an interconnection path is formed by using the cross signal ...

METHOD AND STRUCTURE FOR PRE-GUIDING LOGIC OUTPUTS OF MACRO CELLS IN NARROW CHANNEL LAYOUT

A method and structure for pre-guiding logic outputs of macro cells in a narrow channel layout. The method comprises: after the layout of macro cells, performing pre-winding processing on all the macro cells according to output logics of all the macro cells, and determining whether the channel dimensions of a channel between any two adjacent macro cells after layout meets the requirements for wiring track resources (110); if the channel dimensions of a first channel (3) between a first macro cell (1) and a second macro cell (2) that are adjacent do not meet the requirements for wiring track resources, performing pre-guiding processing on the first channel (3) (120); and by means of outputs of buffers in a first buffer array (6) and a second buffer array that are added by means of executing pre-guiding processing, leading the output logics of pins of the first macro cell (1) and the second macro cell (2) out of the first channel (3), so as to perform the layout of corresponding logic function ...

Clock tree optimization by moving instances toward core route

Aspects of the present disclosure address improved systems and methods for core-route-based clock tree wirelength reduction. A method may include accessing an integrated circuit design comprising a clock tree comprising routes that interconnect terminals of a plurality of clock tree instances. The method further includes identifying a core route in the clock tree. The method further includes determining a first offset based on a distance between the first terminal and the core route and determining a second offset based on a distance from the second terminal to the core route. The method further includes determining a target offset based on a combination of the first and second offsets and moving the clock tree instance toward the core route by the target offset.

A data information input method and system based on Via Wizard software

ON-THE-FLY MULTI-BIT FLIP FLOP GENERATION

On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.

Method and structure for pre-guiding logic output of macro cell under narrow channel layout

Chip layout method and device, electronic equipment and storage medium

The invention provides a chip layout method, a chip layout device, electronic equipment and a computer readable storage medium. The method comprises the steps of determining a function module corresponding to a target unit according to the name of the target unit; searching the unit of the chip to find an associated unit associated with the target unit; and arranging the target unit and the associated unit in an area corresponding to the function module. According to the method and the device, the mutually associated units can be arranged in the same area, so that the overall performance is improved, and the delay is reduced.

INTEGRATED CIRCUIT INCLUDING STANDARD CELLS, METHOD OF MANUFACTURING THE INTEGRATED CIRCUIT, AND COMPUTING SYSTEM FOR PERFORMING THE METHOD

An integrated circuit includes a standard cell including a first output pin and a second output pin configured to each output the same output signal, a first routing path connected to the first output pin, and a second routing path connected to the second output pin. The first routing path includes a first cell group including at least one load cell, the second routing path includes a second cell group including at least one load cell, and the first routing path and the second routing path are electrically disconnected from each other outside the standard cell.

Method and layout of an integrated circuit

A method of manufacturing an integrated circuit includes adjusting a first spacing between an adjacent pair of routing tracks in a first set of routing tracks to be equal to a second spacing, adjusting a third spacing between an adjacent pair of routing tracks in a second set of routing tracks to be equal to a fourth spacing, placing a first and second pair of conductive patterns on the corresponding first and second set of routing tracks, forming a first set of conductive structures based on the first pair of conductive patterns, and a second set of conductive structures based on the second pair of conductive patterns. A first and second cell have a same cell height that is a non-integer multiple of a minimum pitch. One spacing of a first set of spacings is different from another spacing of the first set of spacings.

On-the-fly multi-bit flip flop generation

On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.

Pattern-based formal description language for describing a power/ground routing structure in an integrated circuit design

An approach includes a new power and ground structure description language (PSDL) will allow the user to describe the desired routing pattern for each layer and on a user defined region by region basis, including how the pattern will be laid out in the design with respect to other patterns from a different layer. The new PSDL also gives the complete picture of the entire power and ground structure, instead of just a layer-by-layer view from a single command. It also allowed flexibility in alignment especially when dealing with track misalignments, thus avoiding the extensive trial-and-error steps needed to calculate offsets and distances to maintain pattern alignment using previous approaches. Additionally, because PSDL is not tightly dependent on the design size and/or floorplan, transferring the desired power and ground structure from one design to another will be very easy with only few adjustments.

Method and system to implement topology integrity throughout routing implementations

Described is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where an automatic routing mechanism is implemented to generate a complete routing tree. The approach captures users' design intent about the topology, and the routing system adhere to that topology intent throughout the layout process.

MODELING METHOD AND APPARATUS, COMPUTER DEVICE AND STORAGE MEDIUM

A modeling method includes the following: acquiring electrical parameters of each sub-structure in a through silicon via (TSV) structure; obtaining an electrical topology network model according to a connection relationship of each TSV structure between two dies; and obtaining a simulation model for simulation based on the electrical topology network model and the electrical parameters.

Engineering change order cell structure having always-on transistor

A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections.

INTEGRATED CIRCUIT INCLUDING STANDARD CELLS, METHOD OF MANUFACTURING THE INTEGRATED CIRCUIT, AND COMPUTING SYSTEM FOR PERFORMING THE METHOD

An integrated circuit includes a standard cell including a first output pin and a second output pin configured to each output the same output signal, a first routing path connected to the first output pin, and a second routing path connected to the second output pin. The first routing path includes a first cell group including at least one load cell, the second routing path includes a second cell group including at least one load cell, and the first routing path and the second routing path are electrically disconnected from each other outside the standard cell.

Topology-driven structured trunk routing

The computer executable instructions include a command that accepts multiple user input through various command options. The command encapsulates and implements multiple original software algorithms that convert trunking design intent, expressed via the command options, into trunks on multiple layers of a process technology node. Once executed, the command generates shapes of trunks of specified topology on specified layers. The command includes a set of options to generate a simple or complex trunking topology. The command accepts topology, set of zones, nets and many other options that the user provides to the command to yield trunks of a desired topology. The topology description is relative; thus, it can easily adjust as design changes. The command together with its options represents trunk creation intent.

Readout circuit layout

The invention relates to the field of semiconductor circuit design, in particular to a readout circuit layout which comprises a first PMOS layout used for forming a first PMOS tube, the source electrode of the first PMOS tube is connected with a first signal end, and the first signal end is used for receiving a first level signal; the first NMOS layout is used for forming a first NMOS tube, a source electrode of the first NMOS tube is connected with a second signal end, and the second signal end is used for receiving a second level signal; the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected with a bit line, and the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube are connected with a complementary read-out bit line; the second PMOS layout is used for forming a second PMOS tube, and a source electrode of the second PMOS tube is connected with the first signal end; the second NMOS layout is used for forming ...

Systems and methods of aligning sets of wires with minimum spacing rules

Embodiments disclosed herein describe systems, methods, and products for aligning wires in an integrated circuit (IC) design. An illustrative computer may identity multiple references in a first set of wires and multiple targets in a second set of wires in the IC design. The computer may determine reference target pairs from the multiple references and multiple targets. The computer may calculate a path difference for each of the reference target pairs and align the corresponding wires based upon the path difference while obeying minimum spacing rules. The computer may also allow a circuit designer to modify or override the computer selected references, targets, or reference target pairs. Embodiments disclosed herein therefore mitigate the alignment problems of shorting and incorrect spacing.

Layer assignment technique to improve timing in integrated circuit design

Aspects of the present disclosure address improved systems and methods for layer assignment to improve timing in integrated circuit (IC) designs. An initial placement layout of a net of an IC design is accessed. A plurality of buffer insertion candidates is generated using multiple candidate buffer insertion points and multiple layer assignments from among multiple layers of the IC design. Timing characteristics of each buffer insertion candidate are determined, and timing improvements provided by each buffer insertion candidate are determined based on respective timing characteristics. A buffer insertion candidate is selected from the plurality of buffer insertion candidates based on the timing improvement provided by the buffer insertion candidate. A layout instance for the IC is generated based in part on the selected buffer insertion candidate.

Method for improved cut metal patterning

A method of preparing an integrated circuit device design including analyzing a preliminary device layout to identify a vertical abutment between a first cell and a second cell, the locations of, and spacing between, internal metal cuts within the first and second cells, indexing the second cell relative to the first cell by N CPP to define one or more intermediate device layouts to define a modified device layout with improved internal metal cut spacing in order to suppress BGE and LE.

ENGINEERING CHANGE ORDER CELL STRUCTURE HAVING ALWAYS-ON TRANSISTOR

A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections.

CONDUCTOR SCHEME SELECTION AND TRACK PLANNING FOR MIXED-DIAGONAL-MANHATTAN ROUTING

The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

Cross-segmentation restoration method and device, electronic equipment and storage medium

The invention provides a cross-segmentation repairing method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a signal line with cross segmentation in a circuit board and a reference plane corresponding to the signal line, the reference plane is provided with a segmentation region, and the orthographic projection of the signal line in the reference plane is overlapped with the segmentation region; on the basis of the size of the orthographic projection of the signal line in the partition area, closing part or all of the area in the partition area to obtain a closed area; wherein the orthographic projection of the signal line in the partition area is located in the closed area, and the material of the closed area is the same as the material of the reference plane. Since the partition area of the reference plane is partially or completely closed, the orthographic projection of the signal line in the partition area is located in the closed ...

PERFORMING NON-PREFERRED DIRECTION DETAILED ROUTING FOLLOWED BY PREFERRED DIRECTION GLOBAL AND DETAILED ROUTING

Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

RUNTIME EFFICIENT MULTI-STAGE ROUTER FLOW FOR CIRCUIT DESIGNS

Multi-stage routing for a circuit design includes performing, using computer hardware, a global routing of the circuit design using a hybrid routing graph for a target integrated circuit. The hybrid routing graph includes routing nodes and a plurality of coarsened routing nodes. Each coarsened routing node includes a plurality of constituent routing nodes that are treated as a single node during the global routing. A detailed routing of the circuit design is performed using the computer hardware to generate a legal routing solution for the circuit design. The detailed routing is performed by routing, in parallel, the nets of the circuit design that were globally routed using the plurality of coarsened routing nodes.

Constructing via meshes for high performance routing on silicon chips

System and method for configuring via meshes for a semiconductor circuit having at least a bottom layer and a top layer each having a plurality of parallel conductive straps, and vias to interconnect straps in the bottom layer to the top layer to provide conductive routing pathways is disclosed. The method and system include inputting predefined criteria for the via mesh, and configuring feasible straps in the bottom layer of straps using a set of predefined rules and configuring feasible straps for the top layer, and optionally the intermediate layers using the set of predefined rules. The predefined criteria preferably includes one or all of: defining the bottom and top layer connection locations, defining a set of predefined tracks for each layer, defining the number of layers and straps in each layer, and combinations thereof.

Automated equal-resistance routing in compact pattern

Described is technology for automatically generating a routing for an integrated circuit (IC) design. Information describing pin-pairs of an integrated circuit (IC) design is received. An initial routing of the IC design is determined by (i) defining connected wires between each pin-pair in the set of pin-pairs, and (ii) evaluating a target resistance for the pin-pair over the connected wires, wherein each connected wire is routed with other connected wires. A resistance adjustment is applied to adjust wire resistance of the connected wires of the initial routing. The resistance adjustment can be based on a square routing in response to a wire resistance being below the target resistance; or the resistance adjustment can be based on a multi-layer stacking in response to the wire resistance being above the target resistance. The routing is provided in patterns as generated by the initial routing and the resistance adjustment.

Methods, systems, and computer program product for implementing legal routing tracks across virtual hierarchies and legal placement patterns

Disclosed are methods, systems, and articles of manufacture for implementing legal routing tracks across virtual hierarchies and legal placement patterns. These techniques execute a sequence of instructions to identify at least a layout or a portion thereof and identify a plurality of layout devices in the layout or the portion thereof. These techniques further generate a figure group at least by enclosing the plurality of layout devices within a boundary for the figure group. These techniques may modify layout devices in a placement row without disturbing compliance of one or more design rules with which the legal device pattern complies when generated.

Machine-learning driven prediction in integrated circuit design

Training data is collected for each training integrated circuit (IC) design of a set of training IC designs by: extracting a first set of IC design features in a first stage of an IC design flow, and extracting a first set of IC design labels in a second stage of the IC design flow, where the first stage of the IC design flow occurs earlier than the second stage of the IC design flow in the IC design flow. Next, a machine learning model is trained based on the training data.

Multi-module chip top-layer clock tree design method and system

The invention discloses a multi-module chip top-layer clock tree design method and system, and relates to the field of integrated circuit automation design. According to the specific implementation scheme, an EDA tool is used for completing layout of a top layer module, a logic unit and components; according to a clock propagation relationship between the top-layer logic unit and the top-layer module, inserting a buffer unit according to an interconnection line distance, and creating a clock tree between the top-layer module and the top-layer logic unit; using EDA software to replace a buffer unit used for creating a clock tree between a top layer module and a top layer logic unit with an inverter unit; local wiring is carried out on a clock tree between a top layer module and a top layer logic unit, and then global clock tree integration and wiring are completed by utilizing EDA software. According to the method, the delay of a clock reaching a module is reduced, the influence of OCV is ...

Apparatus and architecture of non-volatile memory module in parallel configuration

A non-volatile memory module in parallel architecture is described. It includes memory function and data storage function in a single module. It enables host system to use memory bus to access storage devices and to use the same memory command protocol for storage device access. The parallel architecture enables contents in memory devices and storage devices to be exchanged freely on module under the control of host memory controller to boost performance of computer and to retain data even if power to computer is shut off. The configuration of non-volatile memory module can be partitioned or expanded into multiple independent channels on module seamlessly with or without ECC supports.

Track assignment by dynamic programming

Various embodiments described herein provide for track assignment of wires of a network of a circuit design by dynamic programming. In particular, various embodiments use a dynamic programming process to determine a set of breaking points for a routing wire of a global-routed and layer-assigned circuit design, and to determine track assignments for each of the sub-wires (sub-routes) formed by applying the set of selected breaking points to the routing wire. This results in a set of track-assigned sub-wires (or track-assigned sub-routes), which various embodiments can connect together to generate a connected set of track-assigned sub-wires that can be used in place of the routing wire.

Devices and methods for balanced routing tree structures

Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design with a source and a plurality of sinks, and then using a first bottom-up wavefront analysis to select branch point candidates for the sinks. A branch point cost function is used to select among the branch point candidates. This process may be repeated until a final tier of analysis results in a final wavefront that is within a threshold distance of the source. The selected branch points are then used in generating a routing tree between the source and the sinks. In various different embodiments, different cost point functions may be used, and different operations used to manage obstructions or other specific routing considerations.

Distributed parallel processing routing

Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed on one or more processors, cause the one or more processors to perform operations. The operations include generating a plurality of child processes according to a number of a plurality of partitions in an integrated circuit (IC) design for an IC die, each of the plurality of child processes corresponding to and assigned to a respective one of the plurality of partitions. The operations include transmitting each of the plurality of partitions to a respective one of the plurality of child processes for routing, each of the plurality of partitions comprising a placement of components for the IC design. The operations include receiving a plurality of routings from the plurality of child processes. The operations include merging the plurality of routings into a global routing for the IC design by assembling together to form a global routing.

System and method for routing in an electronic design

Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic design library including a plurality of design rules. Embodiments may include generating a routing graph, based upon, at least in part, the plurality of design rules, wherein the routing graph is a virtual representation of all of the available routing space for all routing layers associated with an electronic design. Embodiments may further include dynamically updating the routing graph at a graphical user interface, based upon, at least in part, a creation of a routing segment or a via at the graphical user interface.

Wafer-scale large programmable device

The embodiments herein rely on cross reticle wires (also referred to as cross die wires) to provide communication channels between programmable dies already formed on a wafer. Using cross reticle wires to facilitate x-die communication can be three to four orders of magnitude faster than using general purpose I/O. With a wafer containing cross reticle wires, various device geometries can be generated at dicing time by cutting across different reticle boundaries. This allows up to full wafer-size devices, or several smaller sub-wafer devices to be derived from one wafer. Although the programmable dies can contain defects, these defects can be identified and avoided when generating a bitstream for configuring programmable features in the programmable dies.

System, method, and computer program product for genetic routing in an electronic circuit design

The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having one or more unoptimized nets. Embodiments may further include applying a genetic algorithm to the electronic design, wherein the genetic algorithm includes a multi-stage routing analysis. A first stage analysis may apply a device-level global routing analysis, a second stage analysis may include an intra-row routing analysis, a third stage may include an inter-row routing analysis, and a fourth stage may include a post-routing optimization analysis. Embodiments may also include generating an optimized routing of the one or more unoptimized nets and displaying the optimized routing at a graphical user interface.

Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement

A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first layer including conductive lines (C_1st lines) which include interspersed alpha C_1st lines and beta C_1st lines designated correspondingly for first and second reference voltages; and forming a second layer over the first layer, the second layer including segments (C_2nd segments) which include interspersed alpha C_2nd segments and beta C_2nd segments designated correspondingly for the first and second reference voltages; and, relative to the first direction, each beta C_2nd segment being substantially asymmetrically between corresponding adjacent ones of the alpha C_2nd segments.

SEGMENTATION METHOD FOR PATH ROUTING IN MULTILAYER STRUCTURE AND APPARATUS USING THE SAME

A segmentation method includes generating an individual multilayer grid map for each of connection target groups corresponding to a multilayer structure and includes an initial probability included in a path routing area of a corresponding connection target group, among connection target groups in the multilayer structure, as a value of a grid cell, updating the individual multilayer grid map, based on routability of the corresponding connection target group, generating an integrated multilayer grid map including, as a value of a grid cell, a probability that each grid cell is included in a path routing area of each of the connection target groups based on the updated individual multilayer grid map for each of the connection target groups, and determining a path routing area of each of the of connection target groups in each layer in the multilayer structure based on the integrated multilayer grid map.

ADAPTIVE ROW PATTERNS FOR CUSTOM-TILED PLACEMENT FABRICS FOR MIXED HEIGHT CELL LIBRARIES

A method includes instantiating a first plurality of rows in a first region of a fabric. The first region has a height corresponding to a sum of heights of the first plurality of rows. The method also includes instantiating a second plurality of rows in a second region of the fabric. The second region is horizontally adjacent to the first region in the fabric. The second region has a height corresponding to a sum of heights of the second plurality of rows. The method further includes determining whether a row of the first plurality of rows is misaligned with a row of the second plurality of rows and adding a transition region between the row of the first plurality of rows and the row of the second plurality of rows in response.

Standard cell layout optimization method, device, system and medium

The invention provides a standard cell layout optimization method, device and system and a medium, and the method comprises the steps: carrying out the electrical simulation according to the actual technological process and structure parameters of an initial standard cell layout, and calculating the simulation performance index of the initial standard cell layout according to a simulation result; when the simulation performance index is consistent with a preset performance index, establishing a layout dependency effect polynomial model according to a layout dependency effect model fitting factor of the initial standard cell layout, and correcting structure parameters of the initial standard cell layout to obtain corrected device structure parameters; and establishing a compact model, and optimizing the initial standard unit layout by adopting a greedy algorithm. A semiconductor process and a device simulation tool are used for modeling based on the layout dependence effect, the test tape-out ...

Methods and apparatuses for concurrent coupling of inter-tier connections

According to one implementation of the present disclosure, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing respective inter-tier connections coupling for first and second networks concurrently on the generated 3D circuit design. The first networks may include power or ground networks, while the second networks may include signal networks. In another implementation, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing inter-tier connections on the generated 3D circuit design during one of a placement stage, a partitioning stage, a clock tree synthesis (CTS) stage, or a routing stage of a physical circuit design procedure.

Multi-strategy optimization X structure minimum tree construction method based on discrete difference evolution

Automatic net grouping and routing

Techniques and systems for automatic net grouping and routing are described. Some embodiments can determine a set of net groups by automatically grouping nets that have (1) a same pin count, (2) a pin direction type that is in a predefined set of pin direction types, and (3) a pin order type that is in a predefined set of pin order types. Next, the embodiments can generate routing guidance by performing trunk planning for each net group. The embodiments can then perform detailed routing for each net in each net group by using the routing guidance.

Method and layout of an integrated circuit

A method of manufacturing an integrated circuit includes generating a layout of a first and a second cell, adjusting a first spacing between an adjacent pair of routing tracks in a first set of routing tracks to be equal to a second spacing, adjusting a third spacing between an adjacent pair of routing tracks in a second set of routing tracks to be equal to a fourth spacing, placing a first pair of conductive patterns on the first set of routing tracks, placing a second pair of conductive patterns on the second set of routing tracks, forming a first set of conductive structures based on the first pair of conductive patterns, and forming a second set of conductive structures based on the second pair of conductive patterns. The first and second cell have a same cell height that is a non-integer multiple of a minimum pitch.

Layer assignment based on wirelength threshold

Various embodiments provide for layer assignment of a network of a circuit design based on a wirelength threshold, which can facilitate consideration of timing and electromigration and which may be part of electronic design automation (EDA) of a circuit design. More particularly, some embodiments determine (e.g., calculate) a wirelength threshold for a net (e.g., each net) of a circuit design based on one or more characteristics of the net, and select a layer for at least a portion of the net based on the wirelength threshold.

Multi-level overall wiring method and system

The invention discloses a multi-level overall wiring method and system, and relates to the technical field of wiring, and the method comprises the steps: carrying out the initial wiring of a to-be-wired circuit through employing a CUGR wiring device, and obtaining an initial wiring network; performing path search on the initial wiring network by adopting an improved multi-level 3D labyrinth wiring algorithm to obtain a wiring scheme of the to-be-wired circuit; in the improved multi-level 3D labyrinth wiring algorithm, when coarsening grid resources are calculated, values are assigned to resource weights of all general wiring units according to the positions of the general wiring units in all coarsening grids. According to the invention, the wiring cost is reduced while the wiring efficiency is improved.

Photoelectronic chip layout wiring method, device and equipment and storage medium

The invention discloses an optoelectronic chip layout wiring method, device and equipment and a storage medium, and relates to the technical field of optoelectronic chip layout automatic design wiring, and the method comprises the following steps: mapping an optoelectronic chip layout to a two-dimensional coordinate system, and mapping a parameterized unit PCell port into a point coordinate, mapping waveguides needing wiring into link line segments; initializing a photoelectron chip layout and a link, and generating a shortest link path between each group of PCell ports; counting the bending number and length of each link, and adding control points in the links to increase the bending number and/or link line segments, so that the bending numbers and lengths of all links are consistent; the link control points are adjusted, so that the links are not crossed, link path planning is completed, and the link path planning is mapped into waveguide routing. According to the invention, a plurality ...

Analysis layout method considering electron beam atomization effect

Layout analysis method and device, electronics, equipment and storage medium

The invention relates to a layout analysis method and device, electronic equipment and a storage medium, and belongs to the field of integrated circuits. The layout analysis method comprises the following steps: segmenting a register array found from a digital circuit to be analyzed; and carrying out integration and layout and wiring analysis on the digital circuit where each storage block is located to obtain an analysis result. According to the invention, when the layout and wiring analysis is carried out, the layout and wiring analysis is not carried out according to a normal layout and wiring mode any more, the found register array is firstly segmented into the N storage blocks, and then the layout and wiring analysis is carried out, so that the wiring length can be reduced, and the problem that the speed of a current chip is not increased can be solved. And the time sequence delay is large.

Incremental routing based pin assignment

The present disclosure relates to a chip design layout process. More specifically, the present disclosure is directed to an incremental routing-based pin assignment technique. One example method generally includes: performing routing and pin assignment for a chip design layout, one or more objects of the chip design layout being associated with a routing engine and a pin assignment engine stored in memory; detecting a change associated with the one or more objects of the chip design layout; updating, via one or more processors, at least one of the routing engine or the pin assignment engine stored in the memory in response to the detected change and based on the association between the one or more objects and the routing engine or pin assignment engine; and performing another routing and pin assignment based on the updated at least one of the routing engine or the pin assignment engine.

Wiring method, device, device and storage medium

Feasibility analysis of engineering change orders

An existing design of an integrated circuit includes existing cells that have already been placed and routed. An engineering change order (ECO) specifies additional new cells (ECO cells) to be inserted into the existing design. The ECO cells are also associated with target locations for their placement among the existing cells, but these target locations may violate design rules. The feasibility of “legalizing” the placement of the ECO cells within the existing design is assessed as follows. The ECO cells are clustered into clusters based on their target locations. Clusters are assessed by determining an ECO placement impact (EPI) index for individual clusters. The EPI index is a measure of the feasibility for legalizing the placement of the ECO cells in that cluster.

Photoelectronic chip layout wiring method, device and equipment and storage medium

The invention discloses an optoelectronic chip layout wiring method, device and equipment and a storage medium, and relates to the technical field of optoelectronic chip layout automatic design wiring, and the method comprises the following steps: mapping an optoelectronic chip layout into a grid, mapping a parameterized unit PCell port into a point coordinate, and mapping a waveguide needing wiring into a line segment; taking matts in the grid as basic units, and defining center coordinates of the matts and a line segment combination mode passing through the center coordinates of the matts as variables; setting a path between the PCell ports and limiting conditions of points and line segments on the path; and the length of the path is represented by using a variable, a corresponding variable value is calculated based on a limiting condition and according to the equal-length path to be realized so as to determine path planning, and finally the path planning is mapped into waveguide routing ...

Circuit design routing based on routing demand adjustment

Various embodiments provide for routing a circuit design based on adjusting a routing demand. More specifically, some embodiments implement routing demand smoothing of a grid cell, routing overflow spreading of a grid cell, or some combination of both prior to detailed routing of a circuit design, which can result in improved detailed routing over conventional routing techniques.

Computer implemented method, system and storage medium for printed circuit board simulation

Engineering change order cell structure having always-on transistor

A semiconductor cell structure includes four pairs of conductive segments, a first gate-strip, and a second gate-strip. A first conductive segment is configured to have a first supply voltage, and a second conductive segment is configured to have a second supply voltage. Each of the first gate-strip and the second gate-strip intersects an active zone over a channel region of a transistor. The first gate-strip is conductively connected to the second conductive segment. The semiconductor cell structure also includes a first dummy gate-strip and a second dummy gate-strip. The first dummy gate-strip separates from the first gate-strip by one CPP. The second dummy gate-strip separates from the second gate-strip by one CPP. The first gate-strip and the second gate-strip are separated from each other by two CPPs. The dummy gate-strip and the second dummy gate-strip are separated from each other by four CPPs.

Pin access hybrid cell height design

A method of generating a layout diagram for an integrated circuit. The method includes arranging a plurality of cells in the layout diagram. The method further includes placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells, wherein at least one cell pin of the plurality of cell pins extends along a routing track of a plurality of routing tracks across a boundary of the first cell and into a second cell of the plurality of cells abutting the first cell.

Integrated circuits including standard cells and methods of forming same

The invention provides an integrated circuit and a forming method thereof, the integrated circuit comprises a first standard cell, and the first standard cell comprises a first metal layer and a second metal layer, the first metal layer includes a plurality of tracks respectively extending in a first horizontal direction and spaced apart from each other in a second horizontal direction, an uneven pattern including a conductive pattern formed on a track selected from the plurality of tracks, and a connection pattern formed away from the plurality of tracks; a plurality of gate lines respectively extending in a second horizontal direction; and a gate contact configured to connect a gate line selected from the plurality of gate lines to the first metal layer to connect the connection pattern to the selected gate line.

Wiring detection method and device PCB printed circuit board

Buffer insertion technique to consider edge spacing and stack via design rules

Aspects of the present disclosure address improved systems and methods for buffer insertion in an integrated circuit (IC) design using a cost function that accounts for edge spacing and stack via constraints associated with cells in the IC design. An integrated circuit (IC) design comprising a routing topology for a net is accessed. A set of candidate insertion locations along the routing topology are identified. A set of buffering candidates is generated based on the candidate insertion locations. A buffering candidate comprises a cell inserted at a candidate insertion location along the routing topology. A cost associated with the buffering candidate is determined based on a number of potential edge spacing conflicts and a number of stack vias associated with the cell. A buffering solution for the net is selected from the buffering candidate based on the cost associated with the buffering candidate.

ON-THE-FLY MULTI-BIT FLIP FLOP GENERATION

On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.

Methods and Apparatuses for Concurrent Coupling of Inter-Tier Connections

According to one implementation of the present disclosure, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing respective inter-tier connections coupling for first and second networks concurrently on the generated 3D circuit design. The first networks may include power or ground networks, while the second networks may include signal networks. In another implementation, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing inter-tier connections on the generated 3D circuit design during one of a placement stage, a partitioning stage, a clock tree synthesis (CTS) stage, or a routing stage of a physical circuit design procedure.

Partition wire assignment for routing multi-partition circuit designs

Performing partition wire assignment for routing a multi-partition circuit design can include performing, using computer hardware, a global assignment phase by clustering a plurality of super-long lines (SLLs) into a plurality of SLL bins, clustering loads of nets of a circuit design into a plurality of load clusters, and assigning the plurality of SLL bins to the plurality of load clusters. For each SLL bin, a detailed assignment phase can be performed wherein each net having a load cluster assigned to the SLL bin is assigned one or more particular SLLs of the SLL bin using the computer hardware.

Engineering change order cell structure having always-on transistor

A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections.

Interactive wiring method following wiring grid points in integrated circuit layout

Integrated circuit global layout method, electronic equipment and storage medium

The invention discloses an automatic layout method of an integrated circuit, electronic equipment and a storage medium. The method comprises the following steps: constructing a first density map of a Fen constraint and a second density map of a Region constraint; constructing a third density map which only allows the buffer and the inverter to enter a soft block region constraint; and constructing a fourth density map of the common units. And performing global layout iteration according to the first density map, the second density map, the third density map and the fourth density map, and finishing the layout when a termination condition is reached or the maximum iteration round number is reached. The automatic layout method of the integrated circuit supports multiple layout constraints, and multiple layout constraints can exist in one design sample at the same time. Under the condition of normal convergence, the algorithm can limit more than 99% of units to enter a specified area according ...

Wiring resource pre-allocation method and device, computing equipment and storage medium

The invention discloses a wiring resource pre-allocation method and device, computing equipment and a storage medium, and belongs to the field of electronic design automation. The method comprises the following steps: determining a target grid in an integrated circuit layout and the total wiring resource amount in the target grid; and taking the target resource demand quantity of each target line network in the target grid as a variable, and inputting the target resource demand quantity and the total wiring resource quantity which are taken as variables into a preset resource pre-allocation model to carry out quadratic programming solution so as to obtain the resource allocation quantity of each target line network in the target grid. According to the wiring resource pre-allocation method, resource pre-allocation is carried out before integrated circuit wiring, the problem of wiring congestion can be greatly avoided, and the utilization rate of integrated circuit layout resources is improved ...

System and Method for Placing Integrated Circuit Functional Blocks According to Dataflow Width

Macroblock placement for an integrated circuit register-transfer level design is enhanced by tagging blocks having a set of functions as usage element definitions that have a minimum input signal width, such as tags added to a netlist of the design. Tagged blocks aid preferred and regular placement of library cells that are morphed to adapt for reduced congestion and improved utilization.

Computing device and crosstalk information detection method

A computing device and a method reads a circuit board layout file from a storage device, and selects a first signal transmission line from circuit board layout file as a target line. The computing device and method computes a distance between the target line and the aggressor line corresponding to each unit sample length. If the distance is more than or equal to a height of a sample region, the computing device and method defines the height of the sample region as a crosstalk space between the target line and the aggressor line corresponding to a unit sample length. Otherwise, if the distance is less than the height of the sample region, the computing device and method defines the distance as the crosstalk space between the target line and the aggressor line corresponding to the unit sample length.

Computing device and method for checking signal transmission lines

A computing device and a method selects a signal transmission line from a circuit board, computes an actual length of each line segment of the selected signal transmission line, and computes an actual distance between each line segment of the selected signal transmission line and a corresponding line segment of each neighboring signal transmission line. If each actual length is less than or equal to a corresponding reference length and each actual distance is more than or equal to a corresponding reference distance, the device and method determines a design of the selected signal transmission line satisfies the design standards. Otherwise, if any actual length is more than a corresponding reference length, or if any actual distance is less than a corresponding reference distance, the device and method determines the design of the signal transmission line does not satisfy the design standards.

Apparatus and system for implementing variable speed scan testing

In an embodiment of the invention, variable test clock circuitry is provided within an integrated circuit desired to be tested. The variable test clock frequency implements a test clock control register that receives serial test data from a device tester and is configured to serially pass the received test data to scan test chains within the integrated circuit. The test clock control register stores test clock information. The test clock information is provided to a test clock generator where the test clock generator then produces test clock signals at a predetermined frequency. The test clock signal is then provided as a test clock frequency for the scan test chains within the integrated circuit. Methods are also disclosed for operating the variable test clock frequency.

Electronic design automation object placement with partially region-constrained objects

A global placer receives a plurality of regions, each region occupying a sub-area of a design area. receives a plurality of movebound objects, each movebound object associated with a region. The global placer receives a plurality of unconstrained objects, each unconstrained object associated with no region. The global placer receives a tolerance, wherein the placement tolerance defines a coronal fringe to at least one region. The global placer initially placing the plurality of movebound objects and unconstrained objects. The global placer iterates over objects without preference to region-affiliation to select an object, wherein the objects are comprised of the plurality of movebound objects and plurality of unconstrained objects. The global placer determines whether movebound object is within the tolerance of a region associated with the movebound object.

Printed circuit board design assisting device, method, and program

A printed circuit board design assisting device includes a frame ground extraction section that extracts a ground pattern that is provided in a surface layer of a printed circuit board and that is to be connected to a metal component from design data on the printed circuit board stored in a design data storage section to store information for specifying the ground pattern in a data storage section, an electrostatic discharge determination section that performs a determination as to electrostatic discharge for the ground pattern specified from the information stored in the data storage section to store a determination result in a determination result storage section, and an output section that outputs the determination result stored in the determination result storage section.

Mask revision recording circuit for a memory circuit

A mask revision recording circuit for a memory circuit includes a mask recording module and a reading unit. The mask recording module includes a plurality of mask recording units, and a layout of each mask recording unit corresponds to all masks of a layout of the memory circuit. The reading unit is coupled to the mask recording module for reading information of the mask recording module corresponding to a mask revision of the memory circuit according to a clock and an enable signal.

Routing g-based pin placement

A method for routing-based pin placement is provided and includes receiving a logical description of a macro of a partitioned circuit with connectivity information and a physical outline, generating an abstracted shape as an abstraction of a generic shape of a pin for providing a connection to the macro in accordance with the connectivity information as a shape conforming to dimensions of the macro, providing a routing tool with freedom to route a net for connection to the pin toward any part of the abstracted shape of the pin to create a routed net and identifying a location where the routed net crosses the physical outline as a chosen location for the pin.

User Guided Short Correction And Schematic Fix Visualization

Techniques for assisting a designer in correcting discrepancies identified in layout design data. A user interface may be provided listing identified shorts and relevant information related to those shorts. Still further, the user interface may allow a designer to selectively choose a subset of the identified shorts, and to designate or otherwise provide correction data for use to correct the shorts before performing a short isolation process on the selected shorts. Alternately or additionally a user interface may provide a designer with graphical images showing the correction that should be made by a designer to address an identified discrepancy in layout design data.

Method For Improving Circuit Design Robustness

Improving circuit design robustness is based on identifying process sensitive and design critical devices. Design critical devices are identified using circuit design information. Various model-based simulations may be performed on the layout areas associated with the identified design critical devices to extract process sensitive and design critical devices. To make the circuit design more robust, various techniques may be employed to treat the extracted process sensitive and design critical devices.

Method and system for double-sided printing of a series of sheets

A method and a system for double-sided printing of a series of sheets is provided. First printing data for being printed onto a first surface of the series of sheets are provided. The first printing data comprise a plurality of first subsets, each first subset for being printed onto one sheet. Second printing data for being printed onto a second surface of the series of sheets are provided. The second printing data comprise a plurality of second subsets. Each second subset is associated with a respective first subset. A first print is printed in dependence upon the first printing data onto the first surface of the series of sheets. A second print is printed in dependence upon the second printing data onto the second surface of the series of sheets. The first print is scanned and first print data in dependence thereupon are provided. The second print is scanned and second print data in dependence thereupon are provided. For each sheet the first print data and the second print data are processed to determine if the second print data are associated with the respective first print data and data indicative thereof are stored in a database.

Relative Positioning of Circuit Elements in Circuit Design

Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed, routed, and optimized circuit design obeys relative positioning rules of a set of the circuit elements. Such relative positioning rules were created specifically for these circuit elements.

Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells

An integrated circuit, a method of generating a layout of such an integrated circuit using standard cells, and a standard cell library providing such standard cells, are disclosed. The method of generating the layout comprises forming a plurality of rows, and populating each row with a plurality of standard cells chosen in dependence on the functional components required by the integrated circuit, each standard cell having its abutment area abutting the abutment area of at least one adjacent standard cell in the row. Within each row, each standard cell in that row is arranged to have a voltage connection area that is aligned with a common routing track, but with each standard cell having its voltage connection area configured so as not to extend across the entire width of the standard cell. Within each row, for each standard cell in the row, the voltage connection area of that standard cell is then connected to one of a plurality of voltage supplies having regards to a voltage requirement of the corresponding functional component defined by the standard cell, and independent of the voltage supply to which each adjacent cell in the row is connected. This provides a particularly flexible mechanism for placing standard cells during the layout operation, since standard cells that are required to run off the same voltage supply no longer need to be placed together.

Integrated circuit design tool apparatus and method of designing an integrated circuit

An integrated circuit design tool apparatus including a processing resource arranged to support a circuit simulator, a circuit simulator interrogator, and a well distance calculator is provided. The circuit simulator interrogator communicates first and second well distance values separately to the circuit simulator and receives first and second performance parameter value back from the circuit simulator interrogator in response. The well distance calculator determines a performance parameter limit value, and projects, substantially linearly, a well distance change value in respect of the performance parameter limit value using the first and second performance parameter values, the performance parameter limit value and a trial well distance change value. Also, a well distance change characterising equation using the well distance change value projected is used in order to obtain the minimum well distance value associated with the performance parameter limit value.

Semiconductor structure and method for fabricating semiconductor layout

A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively.

Optimizing lithographic mask for manufacturability in efficient manner

Mask layout data of a lithographic mask includes polygons that each include horizontal and vertical edges. Each of a number of target edge pairs is defined by two edges of one or more of the polygons. A search box having a boundary coincident with a given edge of the edges of the polygons is specified. Whether the search box includes at least one edge of the edges of the polygons in addition to the given edge is determined. Where the search box includes at least one edge, at least one of the target edge pairs is specified as including the given edge and one of the at least one edge. For each target edge pair that has been specified, a manufacturability penalty value is determined. A dynamic manufacturability constraint table and a non-zero multiplier table are maintained.

DFM Improvement Utility with Unified Interface

A utility includes a design-for-manufacturing (DFM) checker configured to check layout patterns of an integrated circuit, and a layout change instruction generator configured to generate a layout change instruction based on a result generated by the DFM checker. The DFM checker and the layout change instruction generator are embodied on a non-transitory storage media. The layout change instruction specifies an identifier of a layout pattern among the layout patterns, and a respective layout change to be performed on the layout pattern.

Methodology for performing post layer generation check

There is provided a method comprising receiving data corresponding to a layout design for a plurality of input mask layers and generating a layout design for at least one generated mask layer. The relationship between a first geometric element in a first layout pattern comprising one or more of the generated mask layers and a second geometric element in a second layout pattern is then determined and verified to check if they comply with predetermined rules. If the relationship does not conform with the predetermined rules the design of at least one of the generated mask layers associated with the first or second layout pattern is modified.

Electrostatic damage protection circuitry verification

Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to (or beyond) the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process.

System and method for automated real-time design checking

Systems and methods for real-time design checking of an integrated circuit design, include the operations of receiving at a design tool, design elements of an integrated circuit design entered by an integrated circuit designer; the design tool performing real-time design checks on the design elements as they are entered by the integrated circuit designer to determine whether a design element violates a design rule; when the design tool detects a violation of a design rule based on the design checks alerting the integrated circuit designer; and the design tool presenting a correction to correct the violation of the design rule. The real-time design checks can include, comparing each design element to one or more known non-compliant design elements stored in a database to determine whether a non-compliant design element was entered or is being entered by the integrated circuit designer.

Multi-patterning lithography aware cell placement in integrated circuit design

A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.

Power grid mosaicing with deep-sub-tile cells

A computer aided design system can determine coverage of a metal layer mosaic. The system can apply a tile pattern to a design including at least one layer. Then, the system can identify at least one tile of the tile pattern that violates at least one first design rule. After that, the system can apply a sub-tile pattern to an area identified in the identifying the at least one tile of the tile pattern that violates the design rule. The system further can identify at least one sub-tile of the sub-tile pattern that violates at least one second design rule. Finally, the system can apply a deep-sub-tile pattern to an area identified in the identifying the at least one sub-tile of the sub-tile pattern that violates the second design rule.

Integrated semiconductor devices with amorphous silicon beam, methods of manufacture and design structure

Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS processes, methods of manufacture and design structures are disclosed. The method includes forming at least one beam comprising amorphous silicon material and providing an insulator material over and adjacent to the amorphous silicon beam. The method further includes forming a via through the insulator material and exposing a material underlying the amorphous silicon beam. The method further includes providing a sacrificial material in the via and over the amorphous silicon beam. The method further includes providing a lid on the sacrificial material and over the insulator material. The method further includes venting, through the lid, the sacrificial material and the underlying material to form an upper cavity above the amorphous silicon beam and a lower cavity below the amorphous silicon beam, respectively.

Computer aided design system and method

A computer aided design system comprises an interface creating module, a first calculating module, a dividing module and a second calculating module. The interface module creates a parameter setting interface to display the proposed design on the screen of the device formed with nets and cline segments and select at least one net in response to the user's operation. The first calculating module calculates the length of the cline segments of the potential net in order based on the coordinates of the cline segments and generates a dividing signal. The dividing module divides the cline segments into a first team and a second team based on the compared result with a predetermined width according to the dividing signal. The second calculating module adds the calculated cline segments length in the first team and in the second team to obtain a first length and a second length.

Automatic Place and Route Method for Electromigration Tolerant Power Distribution

The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (J max ) for mean time to failures (MTTF) to be increased.

High performance design rule checking technique

Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.

Automated stimulus steering during simulation of an integrated circuit design

A method is contemplated in which the stimulus to an IC design simulation may be automatically manipulated or steered so that the test environment is altered during subsequent simulations of the IC design based upon the simulation results and/or configuration settings of previous simulations of the IC design. More particularly, a stimulation steering tool may analyze the simulation results and/or the test environment, and manipulate the test environment, which may include the test generator output, and the test bench model, for subsequent simulations.

Design system for semiconductor device, method for manufacturing semiconductor device, semiconductor device and method for bonding substrates

The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters.

Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track and Gate Node Connection Through Single Interconnect Layer

A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection formed by linear-shaped conductive structures. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.

Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks

A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a third gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

Thermal Relief Automation

An approach is provided in which a dynamic thermal relief generator retrieves a circuit board file that identifies power plane thru pin locations and a power plane layer. The dynamic thermal relief generator selects one of the power plane thru pin locations and identifies one or more electrical properties corresponding to a component assigned to the selected power plane thru pin location. As such, the dynamic thermal relief generator computes a conductive material exclusion amount based upon the identified electrical properties, which indicates an amount of area to exclude conductive material on the selected power plane layer. In turn, the dynamic thermal relief generator creates a thermal relief pattern based upon the computed conductive material exclusion amount that identifies conductive material voids on the selected power plane layer to exclude the substantially conductive material.

Algorithm of cu interconnect dummy inserting

The present invention disclosed an algorithm of Cu interconnect dummy inserting, including: divide the surface of semiconductor chip into several square windows with an area of A, each of which is non-overlap; perform a logic operation on each square window; and divide the window into two parts: {circle around (1)} the area to-be-inserted; {circle around (2)} the non-inserting area; determine the metal density of the dummy pattern that should be inserted to each square window and the line width; determine the dummy pattern that should be inserted to the windows according to the metal density, line width, the pre-set dummy pattern and the layouting rules. The beneficial effects of the present invention is: avoided the shortcomings of fill density maximization in the rule-based filling method by using reasonable metal density and line width. And with a combination of the influence of line width and density to the copper plating process and chemical mechanical polishing morphology in model-based filling method, it can achieve a better planarization effect.

Decoupling capacitor cell, cell-based ic, cell-based ic layout system and method, and portable device

A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal layers. The decoupling capacitor cell is arranged in an unused region not occupied by basic cells in a cell-based IC and is connected to a power wiring and a ground wiring.

Passive devices for finfet integrated circuit technologies

Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Method of designing pattern layouts

A method of designing a pattern layout includes defining one shot area including a plurality of chip areas, generating an initial common layout in the plurality of chip areas, primarily correcting the initial layout to form a primary corrected layout, and secondarily correcting the primary corrected layout independently to form a plurality of secondary corrected layouts.

Layout of a MOS Array Edge with Density Gradient Smoothing

A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.

Dose-data generating apparatus

According to one embodiment, generating virtual data by mirroring data based on a dimension measurement result in a measurement region on an inner side of a shot region to a non-shot region on an outer side of a shot edge, and calculating dose data of the measurement region and a non-measurement region based on data in the measurement region and the virtual data are included.

Element placement in circuit design based on preferred location

An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.

Copper Feature Design for Warpage Control of Substrates

An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.

Method and apparatus to generate pattern-based estimated rc data with analysis of route information

A method and apparatus for improving physical synthesis of a circuit design is described. In one exemplary embodiment, preliminary routing information of nets in the circuit design is analyzed. The preliminary routing information includes track assignment information. Timing-critical nets are identified based on statistical distribution of the preliminary routing information of the nets. The identified timing-critical nets are assigned to a set of routing layers and removed from future net pattern matching. The remaining nets are clustered into multiple net patterns based on their physical attributes. The scaling factor for each net pattern is updated based on the scaling factor standard deviation and net length of the net pattern. Nets that are outside multiple standard deviations of a net pattern are assigned to routing layers. The scaling factors of the net patterns and the layer assignments are applied to the next phase of placement-based optimizations.

Device for and method of generating wiring data, and imaging system

It is an object to generate wiring data while controlling generation of omission of wiring and shortening process time. In order to achieve this object, a device for generating wiring data includes: an error acquiring part that acquires a configuration error of the semiconductor chip relative to a certain reference position and a certain reference angle on the substrate; an area information acquiring part that acquires enclosing area information indicating an enclosing area enclosing the semiconductor chip on the substrate; and a wiring data generating part that generates enclosing area wiring data indicating an enclosing area wiring pattern based on a reference fan-out line established for a reference chip free from a configuration error and being a part of a reference wiring pattern free from faulty wiring. The enclosing area wiring pattern is a part of the connection wiring pattern and covers the enclosing area. The wiring data generating part generates the enclosing area wiring data such that the position and the angle of the reference fan-out line relative to the reference chip, and the position and the angle of a fan-out line for the semiconductor chip on the substrate relative to this semiconductor chip, agree with each other independently of the configuration error.

Density-based integrated circuit design adjustment

The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are adjusted such that the local density value is preserved. With some implementations, the local density value is preserved if the adjusted local density value is within a threshold amount of the derived local density value.

Group bounding box region-constrained placement for integrated circuit design

Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit.

Current-aware floorplanning to overcome current delivery limitations in integrated circuits

A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.

Method of merging color sets of layout

A method includes determining one or more potential merges corresponding to a color set A i and a color set A j of N color sets, represented by A 1 to A N , used in coloring polygons of a layout of an integrated circuit. N is a positive integer, i and j are integers from 1 to N, and i≠j. One or more potential cuts corresponding to the color set A i and the second color set A j are determined. An index A ij is determined according to the one or more potential merges and the one or more potential cuts. A plurality of parameters F related to the index A ij is obtained based on various values of indices f i and f j . A parameter F is selected among the plurality of parameters F based on a definition of the index A ij .

SEMICONDUCTOR CIRCUIT DESIGN AND UNIT PIN PLACEMENT

A semiconductor circuit design method, system and computer program product for placing a unit pin on a boundary of a unit of a semiconductor circuit to be designed may be provided. Pin position data is received, wherein the pin position data comprises a chip pin position of a chip pin within the chip area and outside of the unit of a semiconductor circuit, to which the unit pin is to be electrically connected. The coordinates of a center point of the unit are determined, as well as a line crossing the center point and the chip pin position. The unit pin is placed on an intersection of the boundary of the unit and the line crossing the center point. 1. A method for designing a semiconductor circuit comprising:determining a center point of a unit;determining a position of one or more pin lines extending from the center point of the unit to a chip pin position;assigning the one or more pin lines to length-based buckets;sorting the length-based buckets either top-down or bottom up, according to length of the one or more pin lines;selecting a first pin line from a first bucket of the length-based buckets sorted according to the length of the one or more pin lines; andplacing a unit pin on a boundary of the unit where the pin line extending from the center point of the unit to the chip pin position intersects the boundary of the unit.2. The method according to claim 1 , further comprising:iteratively selecting pin lines of the first bucket and placing unit pins on the boundary of the unit where the pin lines intersect with the boundary of the unit, until all pin lines of the first bucket have completed.3. The method according to claim 2 , further comprising:wherein upon completion of placing unit pins for all of the pin lines of the first bucket, selecting a next bucket from the length-based buckets sorted according to length; andselecting a first pin line of the next bucket.4. The method according to claim 1 , wherein the unit has a convex geometry.5. The method ...

OUT-OF-BOUNDS RECOVERY CIRCUIT

Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic. 1. An out-of-bounds recovery circuit for an electronic device having at least a first operating state having first non-allowable memory addresses and a second operating state having second non-allowable memory addresses , the out-of-bounds recovery circuit comprising: monitor one or more control and/or data signals of the electronic device,', 'detect an out-of-bounds violation in the electronic device, when the detection logic determines, based on the one or more control and/or data signals of the electronic device, that the electronic device is in the first operating state and a processing element of the electronic device has fetched an instruction from one of the first non-allowable memory addresses, and', 'detect an out-of-bounds violation in the electronic device, when the detection logic determines, based on the one or more control and/or data signals of the electronic device, that the electronic device is in the second operating state and the processing element of the electronic device has fetched an instruction from one of the second non-allowable memory addresses; and, 'detection logic configured totransition logic configured to, in response to the detection logic detecting an out-of-bounds violation, cause the electronic device to transition to a predetermined ...

Integrated circuit and method of manufacturing same

A method includes positioning a first set of conductive traces in a first direction, manufacturing a second set of conductive traces by a first mask pattern, and electrically coupling, by at least a first via, at least one conductive trace of the first set of conductive traces to at least one conductive trace of the second set of conductive traces. The first set of conductive traces is in a first layer of an integrated circuit. The second set of conductive traces is in a second direction different from the first direction. The second set of conductive traces is in a second layer of the integrated circuit. The second layer is different from the first layer. A conductive trace of the second set of conductive traces is part of a first dummy transistor.

METHOD FOR IMPROVED CUT METAL PATTERNING

A system for preparing an integrated circuit device design includes a memory for storing a plurality of preliminary integrated circuit design files; a processor for retrieving a preliminary integrated circuit design file from the memory; locating vertical abutments between adjacent device cell designs, identifying internal metal cuts on the adjacent device cell designs; determining and evaluating a horizontal spacing between the internal metal cuts a spacing threshold; and if the threshold is note met, shifting one cell horizontally relative to the other cell design by a predetermined distance to define a modified device layout, repeating the determining, evaluating, and shifting operations until the spacing threshold is satisfied; and identifying a next vertical abutment between and repeating the identifying, determining, shifting operations until the spacing threshold has been satisfied for all vertical abutments. 1. A system for preparing an integrated circuit device design comprising:a first memory configured for storing a plurality of preliminary integrated circuit design files; retrieving a preliminary integrated circuit design file from the first memory;', {'sup': th', 'th', 'th', 'th, 'locating a first vertical abutment between an mdevice cell design and an ndevice cell design from the preliminary integrated circuit design file; Подробнее

PLANNING METHOD FOR POWER METAL LINES

A planning method for power metal lines is provided. The planning method includes selecting a block to plan, the block including a first metal layer and a second metal layer therebelow. The first metal layer includes a plurality of first metal lines along a first direction and the second metal layer includes a plurality of second metal lines along a second direction. The block includes a length in the first direction and a width in the second direction. According to a ratio of the length and the width of the block, a line width adjustment procedure is performed to adjust a first line width of each of the first metal lines and a second line width of each of the second metal lines, so that routing congestion can be avoided without affecting the IR drop. 1. A planning method for power metal lines , adapted for a plurality of blocks on a chip , the planning method for power metal lines comprising:selecting a block to plan, wherein the block comprises a first metal layer and a second metal layer therebelow, the first metal layer comprises M first metal lines along a first direction, each of the first metal lines comprises a first line with, the second metal layer comprises N second metal lines along a second direction, each of the second metal lines comprises a second line width, and the block comprises a length in the first direction and a width in the second direction; and when the length is greater than the width, reducing the first line width of each of the first metal lines and increasing the second line width of each of the second metal lines; and', 'when the length is less than the width, reducing the second line width of each of the second metal lines and increasing the first line width of each of the first metal lines., 'performing a line width adjustment procedure according to a ratio of the length and the width of the block to adjust the first line width of each of the first metal lines and the second line width of each of the second metal lines, wherein the ...

Hotspot Avoidance Method for Manufacturing Integrated Circuits

A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout. 1. A method comprising:cropping a plurality of images from a layout of an integrated circuit;generating a first plurality of hash values, each from one of the plurality of images, wherein each of the first plurality of hash values comprises a series of digits and letters;loading a second plurality of hash values stored in a hotspot library;comparing each of the first plurality of hash values with each of the second plurality of hash values, wherein the comparing comprises calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values;comparing the similarity value with a pre-determined threshold similarity value; andin response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result, wherein the position is the position of the corresponding image in the layout.2. The method of claim 1 , wherein the plurality of images form an array claim 1 , and the position comprises a row number and a column number of the ...

Method of manufacturing semiconductor device and system for same

A method is disclosed for storing and reusing the PC description of layout cells. A database stores predefined cells and PC descriptions that were previously calculated by a 3D field solver. Regarding a candidate cell from the layout diagram, the database is searched for a substantial match amongst the predefined cells. . If there is a match, then the stored PC description of the matching predefined cell is assigned to the candidate cell in the layout diagram, which avoids having to make a discrete calculation for the PC description. If there is no match, then the 3D field solver is applied to the candidate cell in order to calculate the PC description of the candidate cell. To facilitate reusing the newly calculated PC description, the candidate cell and the newly calculated PC description are stored in the database as a new predefined cell and its corresponding PC description.

METHOD OF MANUFACTURING INTEGRATED CIRCUIT HAVING THROUGH-SUBSTRATE VIA

A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction. 1. A method , comprising: generating a pattern of a first isolation region;', 'generating a pattern of a through-substrate via (TSV) region within the first isolation region;', 'generating a pattern of a second isolation region surrounding the first isolation region, the second isolation region comprising an inner layout region and an outer layout region, and the outer layout region being separated from the first isolation region by the inner layout region;', 'generating a pattern of first channel regions of dummy transistors, the pattern of first channel regions being within the inner layout region;', 'generating a pattern of second channel regions of active transistors, the pattern of second channel regions being within the outer layout region;', 'generating a pattern of first gates of the dummy transistors in the inner layout region, the first gates overlapping with the first channel regions, and the first channel regions being substantially identical in channel width;', 'generating a pattern of second gates of the active transistors in the outer layout ...

IMAGE MATCHING METHOD AND ARITHMETIC SYSTEM FOR PERFORMING IMAGE MATCHING PROCESS

The present invention relates to an image matching process for aligning a pattern on design data with a pattern on an image, and particularly to an image matching process using a model constructed by machine learning. The method includes: converting a designated CAD pattern on design data into a CAD image (); inputting the CAD image () into a model constructed by machine learning; outputting a pseudo image () from the model by performing calculations according to an algorithm defined by the model; and determining a pattern having a shape closest to a shape of a CAD pattern () on the pseudo image (). The determined pattern is one of patterns on an image generated by an image generating device (). 1. A method comprising:converting a designated CAD pattern on design data into a CAD image;inputting the CAD image into a model constructed by machine learning;outputting a pseudo image from the model by performing calculations according to an algorithm defined by the model;determining a pattern having a shape closest to a shape of a CAD pattern on the pseudo image, the determined pattern being one of patterns on an image generated by an image generating device; andperforming machine learning to adjust parameters of the model such that a CAD pattern on a pseudo image output from the model matches a corresponding pattern on an image generated by the image generating device within a predetermined allowable range.2. A method comprising:converting a designated CAD pattern on design data into a CAD image;inputting the CAD image into a model constructed by machine learning;outputting a pseudo image from the model by performing calculations according to an algorithm defined by the model; anddetermining a pattern having a shape closest to a shape of a CAD pattern on the pseudo image, the determined pattern being one of patterns on an image generated by an image generating device,wherein the model comprises a model constructed by the machine learning using training data containing at ...

Method and system of revising a layout diagram

A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.

TASK ACTIVATING FOR ACCELERATED DEEP LEARNING

Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements performs flow-based computations on wavelets of data. Each processing element has a compute element and a routing element. Each router enables communication via wavelets with at least nearest neighbors in a 2D mesh. Routing is controlled by virtual channel specifiers in each wavelet and routing configuration information in each router. Execution of an activate instruction or completion of a fabric vector operation activates one of the virtual channels. A virtual channel is selected from a pool comprising previously activated virtual channels and virtual channels associated with previously received wavelets. A task corresponding to the selected virtual channel is activated by executing instructions corresponding to the selected virtual channel. 1. A method comprising:exchanging fabric packets selectively over a plurality of virtual channels between a plurality of processing elements interconnected as a fabric, each fabric packet comprising a virtual channel specifier identifying one of the virtual channels, each processing element comprising a fabric router and a compute element enabled to perform dataflow-based and instruction-based processing associated with each of the virtual channels, each compute element comprising a memory enabled to store one or more associated instructions for each of the virtual channels and further enabled to provide at least one of the one or more associated instructions to the compute element for execution;in each processing element, managing a local respective virtual queue for each of the virtual channels;in each processing element and in accordance with predetermined criteria, picking ones of the virtual channels for associated processing, the predetermined criteria comprising selecting from a pool of local currently active ones of the virtual channels;in a first processing element ...

Chip cross-section identification and rendering during failure analysis

A defective integrated circuit (IC) is analyzed to identify a portion of the integrated circuit possibly containing an electrical defect. A computer is used to process the design information of the integrated circuit and to navigate to the physical portion of the integrated circuit where potential electrical defect might be found. The design information includes information on the layout and the technology used to fabricate the integrated circuit. A three-dimensional view of the portion of the design of integrated circuit where the electrical defect might be found is rendered, based on the design information for the integrated circuit.

Method of Modeling a Mask Having Patterns With Arbitrary Angles

A mask layout containing a non-Manhattan pattern is received. The received mask layout is processed. An edge of the non-Manhattan pattern is identified. A plurality of two-dimensional kernels is generated based on processed pre-selected mask layout samples. The two-dimensional kernels each have a respective rotational symmetry. The two-dimensional kernels are applied to the edge of the non-Manhattan pattern to obtain a correction field for the non-Manhattan pattern. A thin mask model is applied to the non-Manhattan pattern. The thin mask model contains a binary modeling of the non-Manhattan pattern. A near field of the non-Manhattan pattern is determined by applying the correction field to the non-Manhattan pattern having the thin mask model applied thereon. An optical model is applied to the near field to obtain an aerial image on a wafer. A resist model is applied to the aerial image to obtain a final resist image on the wafer. 1. A method , comprising:receiving a mask layout that contains a layout pattern;identifying a plurality of edge pixels of the layout pattern, the edge pixels each containing an edge segment of the layout pattern, respectively;determining an orientation angle of the edge segment in each of the edge pixels, respectively; andgenerating a rotated multi-dimensional kernel for each of the edge segments, respectively, wherein each rotated multi-dimensional kernel is generated based at least in part on the orientation angle of the respective edge segment.2. The method of claim 1 , wherein the layout pattern includes a non-Manhattan pattern.3. The method of claim 1 , wherein the identifying the edge pixels includes taking a gradient magnitude of the layout pattern.4. The method of claim 1 , wherein the rotated multi-dimensional kernel is generated to include two dimensions.5. The method of claim 1 , wherein the generating the rotated multi-dimensional kernel includes:providing an unrotated multi-dimensional kernel having a 0 degree rotation, the ...

METHOD, APPARATUS AND ELECTRONIC DEVICE FOR PHOTOLITHOGRAPHIC MASK OPTIMIZATION OF JOINT OPTIMIZATION OF PATTERN AND IMAGE

The present invention relates generally to the technical field of integrated circuit mask design, and more particularly to a method, an apparatus and an electronic device for photolithographic mask optimization of joint optimization of pattern and image. The method includes steps: inputting the main pattern; dividing edges of each main pattern into short edges, and regarding the short edges as a first variable for optimizing the main pattern; generating same or similar assistant feature sample points around same or similar main patterns, and regarding the assistant feature sample points as a second variable for optimizing the main pattern; and forming an objective function with the first variable and the second variable as optimization variables. The rules for generating assistant feature sample points around each main pattern are consistent, which are not limited to specific locations of the main pattern and ensures the consistency of final results for optimizing each main pattern. 1. A method for photolithographic mask optimization of joint optimization of pattern and image , for optimizing an initial mask which comprises at least one main pattern comprising the following steps:{'b': '1', 'S, inputting the main pattern;'}{'b': '2', 'S, dividing edges of each main pattern into short edges, and regarding the short edges as a first variable for optimizing the main pattern;'}{'b': '3', 'S, generating same or similar assistant feature sample points around same or similar main patterns, and regarding the assistant feature sample points as a second variable for optimizing the main pattern;'}{'b': '4', 'S, forming an objective function with the first variable and the second variable as optimization variables.'}3. The method for photolithographic mask optimization of joint optimization of pattern and image according to claim 2 , wherein obtaining the RI comprises the following steps:{'b': '41', 'S, gridding the mask to be optimized to obtain a gridded mask image MI; the ...

Methods of detecting stresses, methods of training compact models, methods of relaxing stresses, and computing systems

A method of detecting stress of an integrated circuit including first and second patterns formed from different materials may comprise: determining one or more stress detection points of the first pattern; dividing a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions; calculating areas of the second pattern at the divided regions; and/or detecting a stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.

Methods of determining scattering of radiation by structures of finite thicknesses on a patterning device

A method including: obtaining a characteristic of a portion of a design layout; determining a characteristic of M3D of a patterning device including or forming the portion; and training, by a computer, a neural network using training data including a sample whose feature vector includes the characteristic of the portion and whose supervisory signal includes the characteristic of the M3D. Also disclosed is a method including: obtaining a characteristic of a portion of a design layout; obtaining a characteristic of a lithographic process that uses a patterning device including or forming the portion; determining a characteristic of a result of the lithographic process; training, by a computer, a neural network using training data including a sample whose feature vector includes the characteristic of the portion and the characteristic of the lithographic process, and whose supervisory signal includes the characteristic of the result.

FIELD PROGRAMMABLE GATE ARRAY (FPGA) HAVING DISSIMILAR CORES

A field programmable gate array (FPGA) having at least first and second processing circuits implemented thereon. Each of the first and second processing circuits comprises a numerical core and associated peripheral components. The numerical core in the first processing circuit is dissimilar to the numerical core in the second processing circuit. The first and second processing circuits are segregated from each other in floorplan view. 1. A field programmable gate array (FPGA) having at least first and second processing circuits implemented thereon , wherein each of the first and second processing circuits comprises a numerical core and associated peripheral components , wherein the numerical core in the first processing circuit is dissimilar to the numerical core in the second processing circuit , and wherein the first and second processing circuits are segregated from each other in floorplan view.2. The FPGA of claim 1 , wherein communication between the first and second processing circuits is made externally to the FPGA.3. The FPGA of claim 1 , wherein the first processing circuit includes a soft numerical core claim 1 , and wherein the second processing circuit includes a hard coded numerical core.4. The FPGA of claim 1 , wherein the first and second processing circuits both include a soft numerical core.5. The FPGA of claim 1 , wherein the first and second processing circuits are implemented on different areas of a single substrate defining the FPGA.6. The FPGA of claim 1 , wherein each processing circuit further comprises one or more of: (i) a serial interface; (ii) an external memory interface; (iii) an external bus interface; (iv) a general purpose input/output module; and (v) a power bridge controller.7. (canceled)8. (canceled)9. A method of operating the field programmable gate array (FPGA) of claim 1 , comprising:transmitting data to at least one of the numerical cores; andfor each numerical core to which data has been transmitted, performing an operation ...

SYSTEM FOR DESIGNING SEMICONDUCTOR CIRCUIT AND OPERATING METHOD OF THE SAME

Provided are a system for designing a semiconductor circuit and an operating method of the same. The system includes a working memory loading a clustering application for generating a cluster, based on instances respectively corresponding to cells of the semiconductor circuit, and loading a design tool for placing the cells. The clustering application, when an output terminal of a first instance is connected to a second instance and the number of instances connected to the output terminal of the first instance is one, classifies the first instance and the second instance into a candidate group pair. The clustering application, when all instances connected to an input terminal of the second instance are classified into the candidate group pair with the second instance, generates the cluster including the first instance and the second instance. 1. A system for designing a semiconductor circuit , the system comprising:a working memory configured to load machine-readable instructions for generating a cluster, based on instances respectively corresponding to cells of the semiconductor circuit, and for placing the cells; anda central processing unit configured to execute the machine-readable instructions for clustering and placing that, when executed by the central processing unit, cause the system to,in response to an output terminal of a first instance being connected to a second instance and a number of instances connected to the output terminal of the first instance being one, classify the first instance and the second instance into a candidate group pair, andin response to all instances connected to an input terminal of the second instance being classified into the candidate group pair with the second instance, generate the cluster including the first instance and the second instance and provide a design tool with the cluster.2. The system of claim 1 , wherein claim 1 , in response to an output terminal of a third instance being connected to the second instance and ...

Method and apparatus to determine a patterning process parameter

A method of determining a parameter of a patterning process, the method including: obtaining a detected representation of radiation redirected by a structure having geometric symmetry at a nominal physical configuration, wherein the detected representation of the radiation was obtained by illuminating a substrate with a radiation beam such that a beam spot on the substrate was filled with the structure; and determining, by a hardware computer system, a value of the patterning process parameter based on optical characteristic values from an asymmetric optical characteristic distribution portion of the detected radiation representation with higher weight than another portion of the detected radiation representation, the asymmetric optical characteristic distribution arising from a different physical configuration of the structure than the nominal physical configuration.

WAFER SENSITIVITY DETERMINATION AND COMMUNICATION

A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors, a wafer image and a wafer target from the IC chip design. The method further comprises generating, by the one or more processors, sensitivity information based on a determination that the wafer image and the wafer target converge, and outputting the sensitivity information. The sensitivity information is associated with writing a mask written for the IC chip design. 1. A method comprising:receiving an integrated circuit (IC) chip design;generating, by one or more processors, a wafer image and a wafer target from the IC chip design;generating, by the one or more processors, sensitivity information based on a determination that the wafer image and the wafer target converge; andoutputting the sensitivity information, wherein the sensitivity information is associated with writing a mask written for the IC chip design.2. The method of further comprising:determining a mask design file from the IC chip design; andoutputting the mask design file from a mask synthesis engine to a mask writing device.3. The method of further comprising:generating a mask representation from the IC chip design; andsimulating the mask representation to generate the wafer image.4. The method of further comprising modifying the mask representation based on a determination that the wafer image and the wafer target do not converge.5. The method of claim 1 , wherein generating the sensitivity information comprises:determining a sensitivity value at one or more points along a polygon within the IC chip design by perturbing one or more edges within a mask representation corresponding to the wafer image.6. The method of claim 5 , wherein generating the sensitivity information further comprises altering a size of the polygon based on the sensitivity value.7. The method of claim 1 , wherein generating the sensitivity information comprises determining one of sensitivity bands of a polygon within ...

SARO: SCALABLE ATTACK-RESISTANT OBFUSCATION OF LOGIC CIRCUITS

A method of obfuscating a circuit design includes, in part, receiving a netlist of the circuit design, splitting the circuit design into a multitude of partitions, transforming each partitions so as to obfuscate each partition, and stitching the multitude of transformed partitions to form the obfuscated circuit. The netlist may be a register transfer level netlist. The number and the size of partitions may vary. The partitions may be distributed throughout the entirety of the design. The method may further include generating a randomized circuit associated with at least a subset of the partitions, and merging each partition with the partition's associated randomized circuit. The method may further include quantifying the amount of transformation associated with each partition. The method may further include adding a first key to at least one of the obfuscated partitions, and adding a second key to the partition's associated randomized circuit. 1. A method of obfuscating a circuit design , the method comprising:receiving a netlist of the circuit design;splitting the circuit design into a plurality of partitions;transforming each of the plurality of partitions thereby to obfuscate each partition; andstitching the plurality of transformed partitions to form the obfuscated circuit design.2. The method of further comprising:shuffling the transformed partitions.3. The method of wherein said netlist is a register transfer level netlist.4. The method of further comprising:varying a number of the plurality of partitions.5. The method of further comprising:varying a size of at least a subset of the plurality of partitions.6. The method of wherein the plurality of partitions are distributed throughout an entirety of the design.7. The method of further comprising:generating a randomized circuit associated with at least a subset of each of the plurality of partitions, each randomized circuit substantially matching a shape and a size of the associated partition; andmerging each ...

Capacitance extraction

An effective spacing is calculated for each physical spacing between two or more neighbor nets of a target net. Segment boundaries are determined based on the calculated effective spacing to define segments for the target net and one of the segments is selected. A metal configuration for the selected segment is identified and a table of capacitance per-unit-length is accessed for the identified metal configuration to return an above capacitance value, a below capacitance value, a left-side capacitance value, and a right-side capacitance value for the corresponding segment, the table comprising at least a two-dimensional (2D) table. The capacitance values are scaled based on a corresponding segment length determined from the calculated effective spacing. The selecting, identifying, accessing and scaling operations are repeated for each remaining segment of the target net. Optionally, the above, below, left, and right capacitance values for all segments of the target net are summed.

METHODS OF ESTIMATING WARPAGE OF INTERPOSERS AND METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGE BY USING THE SAME

A method of estimating warpage of an interposer and a method of manufacturing a semiconductor package by using the same are disclosed. The interposer includes a through electrode passing through a substrate, and a plurality of metal wiring layers and a plurality of insulating layers on the substrate, and the method of estimating warpage of an interposer includes: performing a temperature sweep test by using sample interposers, and measuring warpages according to temperatures; deriving a warpage slope, as a function of temperature, of each of the sample interposers; deriving a warpage model by linearly fitting the warpage slope with respect to an average pattern density of metal wiring layers in each of the sample interposers; and calculating a room temperature warpage reference value of the interposer based on the warpage model. 1. A method of estimating warpage of an interposer , the interposer comprising a through electrode passing through a substrate , and a plurality of metal wiring layers and a plurality of insulating layers on the substrate , the method comprising:performing a temperature sweep test at a plurality of temperatures by using sample interposers, and measuring warpages of the sample interposers according to the plurality of temperatures;deriving a warpage slope, as a function of temperature, of each of the sample interposers;deriving a warpage model by linearly fitting the warpage slope with respect to an average pattern density of the metal wiring layers in each of the sample interposers; andcalculating a room temperature warpage reference value of the interposer based on the warpage model.2. The method of claim 1 , wherein the deriving of the warpage model comprises linearly fitting the warpage slope with respect to the average pattern density of the metal wiring layers according to a first equation:{'br': None, 'i': a', 'b,, 'WS=*PD+'}wherein WS is the warpage slope, PD is the average pattern density, a is a first constant, and b is a second ...

POINT-TO-POINT MODULE CONNECTION INTERFACE FOR INTEGRATED CIRCUIT GENERATION

Systems and methods are disclosed for generation and testing of integrated circuit designs with point-to-point connections between modules. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. For example, type parameterization may be used to generate point-to-point connections in a flexible manner. For example, a point-to-point connection between the source module and the sink module that includes one or more named wires specified by bundle type may be automatically generated based on using the bundle type as a type parameterization input. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design. 1. A method comprising:accessing an indication of a source module of an integrated circuit design;accessing an indication of a sink module of the integrated circuit design;accessing an indication of a bundle type, wherein the bundle type specifies one or more named wires;automatically generating, based on using the bundle type as a type parameterization input, a point-to-point connection between the source module and the sink module that includes the one or more named wires specified by the bundle type; andgenerating a register-transfer level data structure for the integrated circuit design including the source module, the sink module, and the point-to-point connection.2. The method of claim 1 , wherein automatically generating the point-to-point connection between the source module and the sink module comprises:automatically generating input/output ports for modules between the source module and the sink module at multiple levels of a register-transfer level module hierarchy of the integrated circuit design.3. The method of claim 1 , wherein automatically generating the point-to-point connection between the source module and the sink module ...

SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING SEMICONDUCTOR DEVICE

A semiconductor device includes a first integrated circuit and a second integrated circuit disposed on a semiconductor substrate and spaced apart from each other. A wiring structure is disposed on the semiconductor substrate and electrically connects the first integrated circuit and the second integrated circuit. A first TSV area and a second TSV area are disposed between the first integrated circuit and the second integrated circuit The first and second TSV areas include a plurality of first and second TSV structures penetrating through the semiconductor substrate, respectively. The wiring structure passes between the first TSV area and the second TSV area. 1. A semiconductor device comprising:a first integrated circuit and a second integrated circuit disposed on a semiconductor substrate and spaced apart from each other;a wiring structure disposed on the semiconductor substrate and configured to electrically connect the first integrated circuit and the second integrated circuit; anda first TSV area and a second TSV area disposed between the first integrated circuit and the second integrated circuit, and including a plurality of first and second TSV structures penetrating through the semiconductor substrate, respectively,wherein the wiring structure passes between the first TSV area and the second TSV area.2. The semiconductor device of claim 1 , wherein:the first TSV area and the second TSV area are spaced apart in a first direction parallel to an upper surface of the semiconductor substrate;the plurality of first TSV structures are arranged in an m×n matrix form; andthe plurality of second TSV structures are arranged in an i×j matrix form,wherein the m and the i are a number of the plurality of first TSV structures and a number of the plurality of second TSV structures arranged in the first direction, andwherein the n and the j are a number of the plurality of first TSV structures and a number of the plurality of second TSV structures arranged in a second ...

INTEGRATED CIRCUIT DEVICE, METHOD, LAYOUT, AND SYSTEM

An IC device includes a transistor including a gate structure between first and second active areas, a first S/D metal portion overlying the first active area, and a second S/D metal portion overlying the second active area. A load resistor including a third S/D metal portion is positioned on a dielectric layer and in a same layer as the first and second S/D metal portions. A first via overlies the first S/D metal portion, second and third vias overlie the third S/D metal portion, and a first conductive structure is configured to electrically connect the first via to the second via. 1. An integrated circuit (IC) device comprising: a gate structure between first and second active areas;', 'a first source/drain (S/D) metal portion overlying the first active area; and', 'a second S/D metal portion overlying the second active area;, 'a transistor comprisinga load resistor comprising a third S/D metal portion positioned on a dielectric layer and in a same layer as the first and second S/D metal portions;a first via overlying the first S/D metal portion;second and third vias overlying the third S/D metal portion; anda first conductive structure configured to electrically connect the first via to the second via.2. The IC device of claim 1 , wherein the gate structure comprises a high-k dielectric material.3. The IC device of claim 1 , wherein the dielectric layer is adjacent to the first active area.4. The IC device of claim 1 , wherein the first S/D metal portion claim 1 , the third S/D metal portion claim 1 , and the conductive structure are aligned along a first direction.5. The IC device of claim 1 , whereinthe gate structure is one gate structure of a first row of gate structures, andthe third S/D metal portion is located between adjacent gate structures of a second row of gate structures adjacent to the first row of gate structures.6. The IC device of claim 5 , wherein the third S/D metal portion is further located between adjacent gate structures of the first row of ...

INTEGRATED CIRCUIT DEVICE, METHOD, AND SYSTEM

An integrated circuit (IC) device includes a plurality of TAP cells arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of TAP cells includes at least one first TAP cell. The first TAP cell includes two first end areas and a first middle area arranged consecutively in the second direction. The first middle area includes a first dopant of a first type implanted in a first well region of the first type. The first end areas are arranged on opposite sides of the first middle area in the second direction. Each of the first end areas includes a second dopant of a second type implanted in the first well region, the second type different from the first type. 1. An integrated circuit (IC) device , comprising:a plurality of TAP cells arranged at intervals in a first direction and a second direction transverse to the first direction,the plurality of TAP cells comprising at least one first TAP cell, and the first middle area comprising a first dopant of a first type implanted in a first well region of the first type, and', 'the first end areas arranged on opposite sides of the first middle area in the second direction, each of the first end areas comprising a second dopant of a second type implanted in the first well region, the second type different from the first type., 'the first TAP cell comprising two first end areas and a first middle area arranged consecutively in the second direction,'}2. The IC device of claim 1 , whereinthe plurality of TAP cells further comprises at least one second TAP cell, the second middle area comprising the second dopant implanted in a second well region of the second type, and', 'the second end areas arranged on opposite sides of the second middle area in the second direction, each of the second end areas comprising the first dopant implanted in the second well region., 'the second TAP cell comprising two second end areas and a second middle area arranged consecutively in the ...

ENSURING MINIMUM DENSITY COMPLIANCE IN INTEGRATED CIRCUIT INDUCTORS

In one aspect, an inductor may include at least one loop formed on a first metal layer and a non-uniform introduced pattern formed on the first metal layer and circumscribed by the at least one loop. The non-uniform introduced pattern may be formed of a plurality of structures and may have a maximum density at an interior portion thereof and a minimum density at a peripheral portion thereof, where at least some of the plurality of structures have different sizes. 1. An apparatus comprising: at least one loop formed on a first metal layer; and', 'a non-uniform introduced pattern formed on the first metal layer and circumscribed by the at least one loop, wherein the non-uniform introduced pattern is formed of a plurality of structures and has a maximum density at an interior portion thereof and a minimum density at a peripheral portion thereof, wherein at least some of the plurality of structures have different sizes., 'an inductor formed on a semiconductor die, the inductor comprising2. The apparatus of claim 1 , wherein the non-uniform introduced pattern comprises a fractal pattern.3. The apparatus of claim 2 , wherein the fractal pattern comprises:a first plurality of structures having a first size; anda second plurality of structures having a second size, the second size smaller than the first size.4. The apparatus of claim 3 , wherein the fractal pattern further comprises:a third plurality of structures having a third size, the third size smaller than the second size, and wherein an edge portion of each of the third plurality of structures at least substantially aligns with an edge portion of at least one of the second plurality of structures.5. The apparatus of claim 3 , wherein a spacing between a first structure of the first plurality of structures and a first structure of the second plurality of structures is at least substantially of a minimum spacing according to according to design rule checking (DRC) requirements.6. The apparatus of claim 3 , wherein at ...

ENFORCING MASK SYNTHESIS CONSISTENCY ACROSS RANDOM AREAS OF INTEGRATED CIRCUIT CHIPS

A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties enforced include symmetry within circuit patterns and similarity across circuit patterns. The system combines mask patterns in different regions of the circuit and resolves conflicts that occur when there are multiple masks within a region. 1. A method to perform mask synthesis for a circuit design , the method comprising:receiving the circuit design representing a physical layout of a circuit;identifying a circuit pattern from the circuit design based on a search window placed at a location in the circuit design, the circuit pattern comprising one or more geometric shapes within the search window;determining that the circuit pattern does not correspond to a prior identified circuit pattern from the circuit design;responsive to determining that the circuit pattern does not correspond to a prior identified circuit pattern, generating , by a processing device, a mask pattern for the circuit pattern from the circuit design; andgenerating a mask for the circuit design using the mask pattern.2. The method of claim 1 , wherein the circuit design specifies hierarchical units and a circuit pattern represents a portion of the circuit design that is smaller than the smallest hierarchical unit of the circuit design.3. The method of claim 1 , further comprising:generating a mask solutions database configured to map circuit patterns to mask patterns, the mask solutions database storing each mask pattern indexed to the circuit pattern used to generate the mask pattern.4. The method of claim 3 , wherein ...

Computer Implemented System and Method for Generating a Layout of a Cell Defining a Circuit Component

A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell. 1. A method comprising:providing a tile database with multiple tiles that define one or more first component sections for a memory device;defining an array of storage elements having a specified memory array width;defining one or more second component sections having at least part of a standard cell based tile with standard cells arranged in multiple standard cell rows; andgenerating a memory instance by defining a layout for the memory device with the multiple tiles selected from the tile database based on matching the multiple standard cell rows to the specified memory array width of the array of storage elements.2. The method of claim 1 , wherein the tile database includes a memory array custom tile that defines the array of storage elements with the specified memory array width.3. The method of claim 2 , wherein the multiple standard cell rows are configured ...

HIERARCHICAL DENSITY UNIFORMIZATION FOR SEMICONDUCTOR FEATURE SURFACE PLANARIZATION

The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density. 1. A method , comprising:receiving a first layout data of a plurality of features formed on a surface of a wafer, the surface including a plurality of grid regions under a first partition level;determining an initial pattern density value for each of the plurality of grid regions under the first partition level;obtaining a planned pattern density value of a first grid region of the plurality of grid regions by adjusting an initial pattern density value of the first grid region based on an initial pattern density value of a second grid region of the plurality of grid regions under the first partition level;determining a second layout data of the first grid region based on the planned pattern density value; andforming the plurality of features on the surface of the wafer based at least in part on the second layout data of the first grid region.2. The method of claim 1 , wherein the initial pattern density value is determined based on the first layout data.3. The method of claim 2 , wherein the initial pattern density value is determined based on the first layout data with respect to the first grid region and a peripheral area adjacent to the first grid region.4. The method of claim 1 , wherein the initial pattern density value is determined based on a pattern density value of a third grid region under a second partition level claim 1 , and the third grid region overlaps with the first grid region.5. The method ...

METHOD OF MANUFACTURING PHOTOMASKS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

In a method of manufacturing a photomask, a layout of a circuit mask pattern in a mask region corresponding to a chip region of a substrate is designed. A layout of a monitoring mask pattern representing a critical dimension (CD) of the circuit mask pattern in the mask region is designed. The monitoring mask pattern includes a mask-critical dimension uniformity (CDU) detection pattern configured to detect CDU in mask and a wafer-CDU detection pattern configured to detect CDU in wafer. A first optical proximity correction (OPC) is performed on the mask-CDU detection pattern. A second optical proximity correction is performed on the wafer-CDU detection pattern. A photomask having the circuit mask pattern and the monitoring mask pattern is formed. 1. A method , comprising:designing a layout of a circuit mask pattern in a mask region corresponding to a chip region of a substrate;designing a layout of a monitoring mask pattern representing a critical dimension (CD) of the circuit mask pattern in the mask region, the monitoring mask pattern comprising a mask-critical dimension uniformity (CDU) detection pattern configured to detect CDU in mask and a wafer-CDU detection pattern configured to detect CDU in wafer;performing a first optical proximity correction (OPC) on the mask-CDU detection pattern;performing a second optical proximity correction on the wafer-CDU detection pattern; andforming a photomask comprising the circuit mask pattern and the monitoring mask pattern.2. The method of claim 1 , wherein designing the layout of the monitoring mask pattern comprises:locating a monitoring mask region within the mask region in a position that is not occupied by the circuit mask pattern; anddesigning the monitoring mask pattern within the monitoring mask region.3. The method of claim 1 , wherein the monitoring mask pattern has about a same dimension as at least a portion of the circuit mask pattern.4. The method of claim 1 , wherein designing the layout of the monitoring mask ...

INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM

A method of generating an integrated circuit (IC) layout diagram of an IC device includes receiving the IC layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region. The width is divided into a plurality of width segments based on a location of a gate via, and a simulation is performed based on the IC layout diagram and including an effective resistance calculated using at least one width segment of the plurality of width segments. 1. A method of generating an integrated circuit (IC) layout diagram of an IC device , the method comprising:receiving the IC layout diagram of the IC device, the IC layout diagram comprising a gate region having a width across an active region;dividing the width into a plurality of width segments based on a location of a gate via; andperforming a simulation based on the IC layout diagram including an effective resistance calculated using at least one width segment of the plurality of width segments.2. The method of claim 1 , wherein the dividing the width into the plurality of width segments comprises dividing the width into four width segments.3. The method of claim 2 , whereina first width segment extends from a first edge of the active region to the location of the gate via,a second width segment extends from the location of the gate via to a second location midway along the width,a third width segment extends from the second location to a third location between the second location and a second edge of the active region, anda fourth width segment extending from the third location to the second edge of the active region.4. The method of claim 3 , wherein the location of the gate via and the third location are symmetric about the second location.5. The method of claim 1 , further comprising calculating the effective resistance by applying a distributed resistance model to the plurality of width segments.6. The method of claim 5 , wherein the calculating the effective resistance ...

INTEGRATED CIRCUIT HAVING FUNCTIONAL CELLS AND RECONFIGURABLE GATE-BASED DECOUPLING CELLS

Disclosed is a method for designing an integrated circuit, wherein the integrated circuit is to be structured in cells, wherein the cells are to comprise functional cells and spare cells. The method comprises: a) designing at least one functional cell; and b) placing a plurality of functional cells on associated pattern positions of an, in particular regular, pattern matrix designed for the functional cells. The method further comprises c) placing, on at least one of the remaining pattern positions of the pattern matrix and instead of at least one spare cell conceivable for the at least one of the remaining pattern positions of the pattern matrix, a gate-based decoupling cell, and alternatively or in addition, d) placing, in at least one gap between pattern positions of the matrix pattern and instead of at least one filler cell conceivable for the at least one gap between pattern positions of the pattern matrix, a gate-based decoupling cell. 115-. (canceled)16. A method for designing an integrated circuit , wherein the integrated circuit is to be structured in cells , wherein the cells are to comprise functional cells and spare cells , the method comprising:designing at least one functional cell;placing a plurality of functional cells on associated pattern positions of a, in particular regular, pattern matrix designed for the functional cells; andplacing, on at least one of the remaining pattern positions of the pattern matrix and instead of at least one spare cell conceivable for the at least one of the remaining pattern positions of the pattern matrix, a gate-based decoupling cell, and/orplacing, in at least one gap between pattern positions of the matrix pattern and instead of at least one filler cell conceivable for the at least one gap between pattern positions of the pattern matrix, a gate-based decoupling cell.17. The method according to claim 16 , further comprising placing claim 16 , on a plurality of remaining pattern positions of the pattern matrix and ...

Mask pattern correcting method

A mask pattern correcting method according to an embodiment is a correcting method of a mask pattern to be used in a semiconductor device manufacturing process. In the correcting method, a plurality of kernels calculated based on an optical system of an exposure tool is prepared. Weight coefficients for weighting the kernels, respectively, to be used when the kernels are synthesized, are calculated. The kernels are synthesized using the calculated weight coefficients. The mask pattern is corrected using the synthesized kernels.

Updating pin locations in a graphical user interface of an electronic design automation tool

Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.

GENERATING INTEGRATED CIRCUIT FLOORPLANS USING NEURAL NETWORKS

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution. 1. (canceled)2. A method performed by one or more computers , the method comprising:obtaining netlist data for a computer chip, wherein the netlist data specifies a connectivity on a computer chip between a plurality of nodes that each correspond to one or more of a plurality of integrated circuit components of the computer chip;generating a computer chip floorplan that places each node in the netlist data at a respective position on the surface of the computer chip using a node placement neural network that comprises (i) an input subnetwork configured to, at each of a plurality of time steps, process an input representation for the time step to generate an embedding of the input representation;and (ii) a policy subnetwork configured to, at each of the plurality of time steps, process the embedding of the input representation for the time step to generate a score distribution over a plurality of positions on the surface of the computer chip;generating, using a reward function that measures a quality of the computer chip floorplan, ...

AUTOMATED CIRCUIT GENERATION

Automated circuit and layout generation is disclosed. Various embodiments may include a computer system and/or method for generating a circuit layout comprising specifying a circuit schematic to be converted to a circuit layout, receiving a layout script associated with the circuit schematic, the layout script configured to position a plurality of layout instances generated from the circuit schematic, converting the circuit schematic into the plurality of layout instances; and positioning the plurality of layout instances based on the layout script to produce the circuit layout. A circuit may be produced by fabricating a circuit using the layout. 1. A computer-implemented method of generating a circuit layout comprising:specifying a circuit schematic to be converted to said circuit layout;receiving a layout script associated with the circuit schematic, the layout script configured to position a plurality of layout instances generated from the circuit schematic;converting the circuit schematic into the plurality of layout instances; andpositioning the plurality of layout instances based on the layout script to produce said circuit layout.2. The method of wherein the circuit schematic is a transistor level circuit schematic for an analog circuit or mixed signal circuit.3. The method of wherein one or more of the plurality of layout instances are predefined layouts for sub-circuit schematics.4. The method of wherein the layout script comprising a reference to a library where a particular layout instance is stored.5. The method of wherein a first subset of the plurality of layout instances correspond to a plurality of resistors.6. The method of wherein a first subset of the plurality of layout instances correspond to a plurality of capacitors.7. The method of wherein the layout script specifies a particular placement for each of the plurality of layout instances.8. The method of wherein the circuit schematic corresponds to a first circuit schematic of a plurality of ...

METHODS FOR ENGINEERING INTEGRATED CIRCUIT DESIGN AND DEVELOPMENT

Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods. 1. A method for accommodating a plurality of designs on a shuttle , comprising:receiving a first design of a first system-on-chip (SoC) from a first user account with a request to fabricate the first SoC;receiving a second design of a second SoC with a request to fabricate the second SoC;determining that the first and second designs are to be fabricated on a semiconductor wafer;providing the first and second designs to a shuttle manager tool to reserve spots of the first and second designs on the semiconductor wafer; andsending a request to a fabrication entity to fabricate the first and second designs on the semiconductor wafer.2. The method of claim 1 , wherein the first design includes a third design and an integrated circuit design claim 1 , wherein the third design is coupled to the integrated circuit design to generate the first design claim 1 , wherein the second design includes a fourth design and the integrated circuit design claim 1 , wherein the fourth design is coupled to the integrated circuit design to generate the second design.3. The method of claim 2 , further comprising:providing access, via a computer network, to a layout design tool to facilitate generation of the third design and the fourth ...

METHOD AND APPARATUS FOR VERIFYING ELECTRONIC CIRCUITS

A method, system and computer program product, the method comprising: obtaining circuit information, comprising description of groups of pins of electronic chips; obtaining a description of a test comprising a plurality of rules specifying: an identifier, a first group of pins, a second group of pins, a first action to take upon successful interconnection of the first and second groups, and a second action to take upon failure, wherein the first action and second actions are one of: finish with success, finish with failure, and a rule ID of a subsequent rule to check; checking the plurality of rules, comprising checking a sequence of rules starting with a first rule, and wherein each subsequent rule is selected as the first or second action of a preceding rule, in accordance with whether the preceding rule succeeded or failed, respectively; and outputting a result of the plurality of rules. 1. A method , comprising:obtaining information of a circuit being designed, the information comprising description of at least two groups of identified pins, of at least one electronic chip; a rule identifier,', 'a first group of pins from the at least two groups of identified pins, the first group having a first ordering,', 'a second group of pins from the at least two groups of identified pins, the second group having a second ordering,', 'a first action to be taken upon successful interconnection of the first group and the second group, wherein the successful interconnection is in accordance with the first ordering and the second ordering, and', 'a second action to be taken upon failed interconnection of the first group and the second group, wherein the failed interconnection is in accordance with the first ordering and the second ordering, wherein each of the first action and the second action is one of: finish with success, finish with failure, and a rule ID of a subsequent rule to be checked;, 'obtaining a description of at least one test, the at least one test comprising a ...

METHOD, APPARATUS AND SYSTEM FOR WIDE METAL LINE FOR SADP ROUTING

At least one method, apparatus and system disclosed involves a circuit layout for an integrated circuit device comprising a plurality of wider-than-default metal formations for a functional cell. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first pair of wide metal formations are provided. The first pair of wide metal formations comprise a first metal formation and a second metal placed about a first cell boundary of the functional cell for providing additional space for routing, for high-drive routing, and/or for power routing. 120.-. (canceled)21. An integrated circuit device , comprising:at least one functional cell, wherein the functional cell has a default metal line width, and the functional cell comprises:a first pair of wide metal formations comprising a first metal formation and a second metal formation placed about a first cell boundary of the functional cell, wherein both the first metal formation and the second metal formation have a width greater than the default metal line width and less than about five times the default metal line width, and the distance between the first metal formation and the second metal formation is equal to the default metal line width.22. The integrated circuit device of claim 21 , wherein the first metal formation comprises a mandrel metal Metal-2 (M2) formation and wherein the second metal formation comprises a non-mandrel metal M2 formation.23. The integrated circuit device of claim 22 , wherein the first and second metal formations are formed on a top edge and a bottom edge of the functional cell.24. The integrated circuit device of claim 23 , wherein the first metal formation is on a top edge of the functional cell and the second metal formations is on a bottom edge of the functional cell.25. The integrated circuit device of claim 21 , further comprising a second pair of wide metal formations comprising a third metal formation and a fourth metal formation ...

DESIGN PARAMETER EXTRACTION FROM DIGITIZED IMAGE OF A SCHEMATIC OR BLOCK DIAGRAM FOR ELECTRICAL DESIGNS

Capturing and processing a digital image of a pictorial (e.g., hand-drawn) representation of a schematic or block diagram as a digital image to aid in creation and maintenance of electrical designs is disclosed. Processing of the digital image includes processing to determine design parameters to create an informational format useful as input to other design software. Design parameters may include schematic layout and attributes such as maximum output voltage, minimum input voltage, ambient temperature, etc. The method and system also include storage of information accessible to refine designs and perform simulations of designs as part of an overall electrical design process. Associated devices and methods are disclosed as well. 1. A device comprising:a processing device; and receive an image that includes a set of electrical design symbols;', 'for each symbol of the set of electrical design symbols, determine a corresponding circuit element to determine a set of circuit elements associated with the image;', 'generate a circuit that includes the set of circuit elements based on the image; and', 'provide a schematic of the circuit., 'a non-transitory computer-readable memory coupled to the processing device and storing instructions that when executed cause the processing device to2. The device of claim 1 , wherein the non-transitory computer-readable memory stores instructions that cause the processing device to:determine a bill of materials associated with the circuit; andprovide the bill of materials.3. The device of claim 1 , wherein:the image includes a representation of a set of design parameters; and determine the set of design parameters from the representation; and', 'generate the circuit based on the set of design parameters., 'the non-transitory computer-readable memory stores instructions that cause the processing device to4. The device of claim 3 , wherein the set of design parameters includes at least one of: a minimum input voltage claim 3 , a maximum ...

Method and system for adjusting a circuit symbol

A method includes obtaining first data representing a first circuit symbol and second data representing a second circuit symbol. The first circuit symbol has a plurality of first pins having a first position vector associated therewith. The second circuit symbol has a plurality of second pins having a second position vector associated therewith, and each of the plurality of second pins corresponds to a respective one of the plurality of first pins. An adjustment transformation mapping position vectors to transform the position vectors is determined. The adjustment transformation minimizes an error measure that is based on one or more deviations. Each deviation is a deviation between a transformed position vector and the first position vector associated with one of the first pins. The transformed position vector is obtained by applying the adjustment transformation to the second position vector associated with the second pin corresponding to the first pin.

METHOD FOR DETERMINING PATTERNING DEVICE PATTERN BASED ON MANUFACTURABILITY

A method for determining a patterning device pattern. The method includes obtaining (i) an initial patterning device pattern having at least one feature, and (ii) a desired feature size of the at least one feature, obtaining, based on a patterning process model, the initial patterning device pattern and a target pattern for a substrate, a difference value between a predicted pattern of the substrate image by the initial patterning device and the target pattern for the substrate, determining a penalty value related the manufacturability of the at least one feature, wherein the penalty value varies as a function of the size of the at least one feature, and determining the patterning device pattern based on the initial patterning device pattern and the desired feature size such that a sum of the difference value and the penalty value is reduced. 1. A method comprising:obtaining (i) an initial patterning device pattern having at least one feature, and (ii) a desired feature size of the at least one feature;detecting a pattern of the initial patterning device pattern having features with sizes around the desired feature size;obtaining, based on a patterning process model, on the initial patterning device pattern and on a target pattern for a substrate, a difference value between a predicted pattern of a substrate image using the initial patterning device pattern and the target pattern for the substrate;determining a penalty value related to the manufacturability of the at least one feature, wherein the penalty value varies as a function of the size of the at least one feature; anddetermining, by a hardware computer, a patterning device pattern based on the initial patterning device pattern and on the desired feature size such that a sum of the difference value and the penalty value is reduced.2. The method of claim 1 , wherein the determining the patterning device pattern is an iterative process claim 1 , an iteration comprises:modifying the size of the at least one ...

STANDARD CELL ESTABLISHMENT METHOD

A standard cell establishment method is disclosed. The standard cell establishment method includes the following operations: setting a first implant split case; obtaining a plurality of characteristic parameters according to the first implant split case; applying the plurality of characteristic parameters to a device delay metric so as to obtain a speed parameter; optimizing a channel parameter if the speed parameter is better than a previous speed parameter; and establishing a standard cell if the channel parameter is optimized successfully. 1. A standard cell establishment method , comprising:setting a first implant split case;obtaining a plurality of characteristic parameters according to the first implant split case;applying the plurality of characteristic parameters to a device delay metric so as to obtain a speed parameter;optimizing a channel parameter if the speed parameter is better than a previous speed parameter; andestablishing a standard cell if the channel parameter is optimized successfully;wherein if the speed parameter is not better than the previous speed parameter or the channel parameter is not optimized successfully, a second implant split case is set before establishing the standard cell.2. The standard cell establishment method of claim 1 , further comprising:obtaining the plurality of characteristic parameters according to the second implant split case; andapplying the plurality of characteristic parameters to the device delay metric so as to obtain the speed parameter.3. The standard cell establishment method of claim 1 , further comprising:collecting at least one cell data after setting the first implant split case.4. The standard cell establishment method of claim 1 , wherein obtaining the plurality of characteristic parameters according to the first implant split case further comprising:obtaining a saturation current value by operating under a DC mode.5. The standard cell establishment method of claim 1 , wherein obtaining the plurality ...

LAYOUT METHOD OF A CHIP AND ELECTRONIC EQUIPMENT

A layout method of a chip includes: determining a logic diagram corresponding to a chip to be laid out and a device list corresponding to the logic diagram; and determining a layout diagram of the chip to be laid out, according to the logic diagram, the device list, and a pre-trained layout mode. The layout diagram includes at least an arrangement position, in the chip to be laid out, of each device in the device list. 1. A layout method of a chip , comprising:determining a logic diagram corresponding to a chip to be laid out and a device list corresponding to the logic diagram; anddetermining a layout diagram of the chip to be laid out, according to the logic diagram, the device list, and a pre-trained layout model; wherein the layout diagram includes at least an arrangement position, in the chip to be laid out, of each device in the device list.2. The method according to claim 1 , wherein the determining a layout diagram of the chip to be laid out claim 1 , according to the logic diagram claim 1 , the device list claim 1 , and the pre-trained layout model includes:obtaining first attribute data of the chip to be laid out, second attribute data of each device in the device list, and wiring rules; anddetermining the layout diagram of the chip to be laid out, according to the pre-trained layout model, the logic diagram, the device list, the first attribute data, the second attribute data, and the wiring rules; whereinthe first attribute data includes at least an area of the chip to be laid out; second attribute data of a device includes at least power consumption of the device, performance of the device, and a size of the device; and the wiring rules includes at least a wiring density, an interconnection principle, and a non-crossing principle.3. The method according to claim 2 , wherein the determining the layout diagram of the chip to be laid out claim 2 , according to the pre-trained layout model claim 2 , the logic diagram claim 2 , the device list claim 2 , the ...

SEMICONDUCTOR DEVICE INCLUDING REGIONS FOR REDUCING DENSITY GRADIENT EFFECT AND METHOD OF FORMING THE SAME

A method includes: generating a design layout according to a circuit design by placing first and second components; identifying a first area and a second area between the first component and the second component; and determining a first cell configuration of the first component according to the first component and a second cell configuration of the second component according to the second component. The method further includes selecting a first cell comprising a first capacitor from a cell library, wherein the first cell has a third cell configuration identical to the first cell configuration: selecting a second cell comprising a second capacitor from the cell library, wherein the second cell has a fourth cell configuration identical to the second cell configuration; placing a first cell array formed of the first cell in the first area; and placing a second cell array formed of the second cell in the second area. 1. A method , comprising:receiving a circuit design;generating a design layout according to the circuit design by placing a first component and a second component adjacent to the first component;determining a first area and a second area between the first component and the second component;determining a first cell configuration of the first component according to the first component and a second cell configuration of the second component according to the second component;selecting a first cell comprising a first capacitor from a cell library, wherein the first cell has a third cell configuration identical to the first cell configuration of the first component;selecting a second cell comprising a second capacitor from the cell library, wherein the second cell has a fourth cell configuration identical to the second cell configuration of the second component;placing a first cell array formed of the first cell in the first area; andplacing a second cell array formed of the second cell in the second area,wherein at least one of the receiving, generating, ...

TECHNIQUES FOR DETERMINING AND USING STATIC REGIONS IN AN INVERSE DESIGN PROCESS

In some embodiments, logic stored on a computer-readable medium, in response to execution, causes a computing system to conduct an inverse design process to generate a plurality of segmented designs corresponding to a plurality of device specifications, determine at least one highly impactful design area based on the plurality of segmented designs; and designate the at least one highly impactful design area as a static design area. In some embodiments, a product line comprising a plurality of physical devices is provided. Each physical device of the plurality of physical devices includes a design region that includes a static design area and a customized design area. The static design area for each physical device is the same for each physical device of the plurality of physical devices, and the customized design area for each physical device is different for each physical device of the plurality of physical devices. 1. A non-transitory computer-readable medium having logic stored thereon that , in response to execution by one or more processors of a computing system , causes the computing system to perform actions comprising:conducting an inverse design process to generate a plurality of segmented designs corresponding to a plurality of device specifications;determining at least one highly impactful design area based on the plurality of segmented designs; anddesignating the at least one highly impactful design area as a static design area.2. The non-transitory computer-readable medium of claim 1 , wherein determining the at least one highly impactful design area based on the plurality of segmented designs includes analyzing field magnitudes in corresponding regions of the plurality of segmented designs.3. The non-transitory computer-readable medium of claim 2 , wherein the corresponding regions of the plurality of segmented designs include at least one region near at least one input port and at least one region near at least one output port.4. The non-transitory ...

Guided power grid augmentation system and method

A method and system for guided power grid augmentation determines a minimum resistance path for cells within an integrated circuit (IC) design. The minimum resistance path traces a conducting wire connecting a pin of a cell to an IC tap within the IC design. A voltage drop value for each of the cells is determined so as to identify target cells having a voltage drop value that satisfies a voltage drop criteria. Polygons have defined size characteristics are defined around the minimum resistance paths of the target cells, and conductors, such as additional conductors, are generated within the defined polygons.

POWER SUPPLY CONDUCTIVE TRACE STRUCTURE OF SEMICONDUCTOR DEVICE AND POWER SUPPLY CONDUCTIVE TRACE LAYOUT METHOD OF SEMICONDUCTOR DEVICE

A power supply conductive trace structure of a semiconductor device includes a first power supply conductive trace in a mesh form provided in a first power supply conductive trace layer, and a second power supply conductive trace provided in a redistribution layer located on or above the first power supply conductive trace to correspond in position to a conductive trace area that is a portion of the first power supply conductive trace and to be connected to the first power supply conductive trace. 1. A power supply conductive trace structure of a semiconductor device , comprising:a first power supply conductive trace in a mesh form provided in a first power supply conductive trace layer; anda second power supply conductive trace provided in a redistribution layer located on or above the first power supply conductive trace to correspond in position to a conductive trace area that is a portion of the first power supply conductive trace and to be connected to the first power supply conductive trace.2. The power supply conductive trace structure of the semiconductor device according to claim 1 , further comprising:a third power supply conductive trace provided in a second power supply conductive trace layer located at a position on a lower side of the first power supply conductive trace layer;wherein the first power supply conductive trace is connected to the third power supply conductive trace through vias, anda density of the vias provided, between the first power supply conductive trace layer and the second power supply conductive trace layer, in a first area located around the conductive trace area is configured to be higher than a density of vias provided in an area other than the first area.3. The power supply conductive trace structure of the semiconductor device according to claim 2 , wherein a density of the vias provided claim 2 , between the first power supply conductive trace layer and the second power supply conductive trace layer claim 2 , in a second area ...

SYSTEMS AND METHODS FOR IMPROVING RESIST MODEL PREDICTIONS

A method, involving computing a first intensity of a first aerial image and a second intensity of a second aerial image, the first aerial image corresponding to a first location within a resist layer and the second aerial image corresponding to a second location within the resist layer. The method further involving performing, using a resist model, a computer simulation of the resist layer to obtain a value of a parameter for a resist layer feature based on a difference between the first and second intensities or on a difference between a resist model result for the first intensity and a resist model result for the second intensity. 1. A method comprising:computing a first intensity of a first aerial image and a second intensity of a second aerial image, the first aerial image corresponding to a first location within a resist layer and the second aerial image corresponding to a second location within the resist layer; andperforming, by a hardware computer system using a resist model, a computer simulation of the resist layer to obtain a value of a parameter for a resist layer feature based on a difference between the first and second intensities or on a difference between a resist model result for the first intensity and a resist model result for the second intensity.2. The method of claim 1 , comprising obtaining the value of the parameter for the resist layer based on the difference between the first and second intensities.3. The method of claim 1 , comprising obtaining the value of the parameter based on the difference between the resist model result for the first intensity and the resist model result for the second intensity.4. The method of claim 1 , wherein the first location is at a first depth within the resist layer and the second location is at a second depth within the resist layer claim 1 , different from the first depth claim 1 , the first depth and the second depth being measured with respect to a top surface of the resist layer.5. The method of claim ...

Methods and systems for designing and manufacturing optical lithography masks

A method of designing an optical photomask includes providing a target pattern, correcting the target pattern with an OPC model, adjusting the target pattern and/or the OPC model, and correcting a first corrected pattern. The target pattern indicates a target shape of a pre-pattern opening in a photoresist layer on a semiconductor substrate. Correcting the target pattern includes using an optical proximity correction (OPC) model to generate OPC output information that includes edge placement error (EPE) information, a first corrected pattern, and/or a simulated contour of the pre-pattern opening. Adjusting the target pattern and/or the OPC model includes adjusting with OPC based adjustments that are based on the OPC output information. Correcting the first corrected pattern includes using the OPC model in response to the OPC based adjustments to generate a second corrected pattern.

System and method for decomposition of a single photoresist mask pattern into 3 photoresist mask patterns

A system and method of decomposing a single photoresist mask pattern to three photoresist mask patterns. The system and method assign nodes to polygon features on the single photoresist mask pattern, designate nodes as being adjacent nodes for those nodes that are less than a predetermined distance apart, iteratively remove nodes having 2 or less adjacent nodes until no nodes having 2 or less adjacent nodes remain, identify one or more internal nodes, map photoresist mask pattern designations (colors) to the internal nodes, and replace and map a color to each of the nodes removed by the temporarily removing nodes, such that each node does not have an adjacent node of the same color.

REFINING MULTI-BIT FLIP FLOPS MAPPING WITHOUT EXPLICIT DE-BANKING AND RE-BANKING

Refining multi-bit flip flops mapping without explicit de-banking and re-banking is provided by identifying a set of equivalent flops in a layout, that include a first flop having a first logic routing and a first location in the layout and a second flop having a second logic routing and a second location in the layout; and remapping the first logic of the first flop from the first location to the second location and the second logic of the second flop from the second location to the first location. 1. A method , comprising:identifying a set of equivalent flops in a layout including a first flop having a first logic routing and a first location in the layout and a second flop having a second logic routing and a second location in the layout; andremapping the first logic of the first flop from the first location to the second location and the second logic of the second flop from the second location to the first location.2. The method of claim 1 , wherein remapping the first logic routing to the second location and the second logic routing to the first location is performed in parallel with one or more additional remapping operations of additional equivalent flops in the set of equivalent flops.3. The method of claim 1 , further comprising: wiring congestion in a layout;', 'wire load in the layout;', 'wire length in the layout;', 'clock timing for the first flop and the second flop; and', 'power consumption in the layout., 'identifying the set of equivalent flops in response to triggering a remapping condition in a layout that includes the set of equivalent flops, wherein the remapping condition includes a cost function based on at least one of4. The method of claim 3 , wherein the set of equivalent flops further includes a third flop having a third logic routing and a third location claim 3 , and wherein remapping is performed in response to determining that a first remapping of the first flop and the second flop exceeds a second mapping of the first flop and the ...

METHOD AND APPARATUS FOR AUTOMATIC EXTRACTION OF STANDARD CELLS TO GENERATE A STANDARD CELL CANDIDATE LIBRARY

Methods and apparatus are provided for automatically extracting standard cells to form a standard cell library using raw multi-layer images of an IC. Accordingly, various embodiments involve: extracting the raw contact layer image from the raw multi-layer images; binarizing the raw contact layer image to generate a binarized contact layer image identifying a plurality of contact rows and a plurality of contact columns; determining a plurality of Vlines based on a subset of the plurality of contact rows having a periodic nature; extracting a plurality of binarized contact layer image strips from the binarized contact layer image; encoding each binarized contact layer image strip using feature vectors and column distance values; applying a model rule set to each encoded binarized contact layer image strip for detecting cell boundaries; extracting the standard cells based on the cell boundaries; and storing the extracted cells to form a standard cell candidate library. 1. A computer-implemented method for automatically extracting one or more standard cells of an integrated circuit (“IC”) using raw multi-layered images of the IC acquired using an imaging modality , the method comprising:extracting a raw contact layer image from the raw multi-layered images;binarizing the raw contact layer image to generate a binarized contact layer SEM image displaying a plurality of contacts forming a plurality of contact rows and a plurality of contact columns, in which each contact of the plurality of contacts represents an electronic connection between a metal layer and one of a poly-silicon layer or an active layer of the IC;{'sub': 'cc', 'determining a plurality of common collector supply voltage (“V”) lines based at least in part on a contact row subset of the plurality of contact rows, wherein each contact row of the contact row subset comprises a periodic nature of contacts and each two adjacent contact rows comprises a constant distance representing as a cell height;'}{'sub': ...