ПОЛУПРОВОДНИКОВЫЙ МОДУЛЬ И СПОСОБ ИЗГОТОВЛЕНИЯ ПОЛУПРОВОДНИКОВОГО МОДУЛЯ

Изобретение относится к силовой полупроводниковой технике. Сущность изобретения: полупроводниковый модуль содержит базовый элемент, изоляционный элемент с двухсторонним металлизированным покрытием, расположенный с помощью первого из обоих металлизированных покрытий на базовом элементе, и по меньшей мере один полупроводниковый элемент, расположенный на другом из обоих металлизированных покрытий. На краевом участке изоляционного элемента расположен электроизоляционный слой, причем поверхность этого изоляционного слоя образует с поверхностью второго металлизированного покрытия общую плоскую поверхность. Предложен также способ изготовления полупроводникового модуля. Техническим результатом изобретения является создание полупроводникового модуля, характеризующегося повышенной диэлектрической прочностью и одновременно простотой изготовления. 2 н. и 8 з.п. ф-лы, 5 ил.

СПОСОБ И УСТРОЙСТВО ДЛЯ ОЧИСТКИ, РАЗДЕЛЕНИЯ, МОДИФИКАЦИИ И/ИЛИ ИММОБИЛИЗАЦИИ ХИМИЧЕСКИХ ИЛИ БИОЛОГИЧЕСКИХ ОБЪЕКТОВ, НАХОДЯЩИХСЯ В ТЕКУЧЕЙ СРЕДЕ, И ОПОРА ИЗ МИКРОПРОВОЛОКИ

... 1. Устройство для очистки, разделения, модификации и/или иммобилизации химических или биологических объектов, находящихся в текучей среде, посредством связывания химического или биологического объекта с функциональным покрытием или лигандами, находящимися на поверхности опор из микропроволоки при отсутствии воздействия магнитного поля, создаемого между опорами из микропроволоки и частицами, находящимися в текучей среде, на разделение названных частиц, которое содержит по меньшей мере одну опору из микропроволоки, закрепленную своими концами и имеющую многослойную структуру, состоящую из центрального стержня и по меньшей мере одного покрывающего слоя и пригодную для связывания химических или биологических объектов, при этом поверхность микропроволоки модифицирована путем присоединения лигандов или нанесением на нее функционального покрытия. ! 2. Устройство по п.1, в котором центральный стержень и покрывающие слои выполнены из материала, выбранного из группы, включающей стеклянный, металлический ...

Von der Peripherie-unabhängiges präzises Positionsglied für einen Halbleiterchip und Herstellungsverfahren dafür

Mounting for at least one semiconductor component

The invention relates to a low-capacitance mounting, in particular for lossy semiconductor components, for example IMPATT diodes, which can be manufactured inexpensively. This is achieved with the aid of a diamond body (heat sink) having a trench-like recess containing the connected semiconductor component.

ISOLIERTES WÄRMEABLEITUNGSSUBSTRAT

Ein isoliertes Wärmeableitungssubstrat, das Folgendes einschließt: ein Keramiksubstrat; und eine Leiterschicht, die auf mindestens eine der Hauptoberflächen des Keramiksubstrats aufgeklebt ist, wobei die Leiterschicht Folgendes einschließt: eine obere Oberfläche; eine untere Oberfläche; und eine Seitenoberfläche 1, die die obere Oberfläche mit der unteren Oberfläche verbindet; wobei das Keramiksubstrat Folgendes einschließt: einen untersten Abschnitt; eine Seitenoberfläche 2, die den untersten Abschnitt mit der Seitenoberfläche 1 der Leiterschicht verbindet; und eine Klebeoberfläche in einer höheren Position als die des untersten Abschnitts, wobei die Klebeoberfläche mit der unteren Oberfläche der Leiterschicht verklebt ist; wobei ein Absolutwert (|α - β|) 20° oder weniger im Durchschnitt beträgt; und die Seitenoberfläche 1 einen eingelassenen Abschnitt von einem Ende der oberen Oberfläche in Normalrichtung relativ zur Tangentiallinie der Kontur der Leiterschicht, wie in der Ebene betrachtet ...

MODUL-AUFBAU MIT INTEGRIERTEM HALBLEITERCHIP UND CHIPTRAEGER

Mehrchip-Halbleitermodul und Herstellungsverfahren dafür

Ein Mehrchip-Halbleitermodul weist auf: ein Chipmontageteil mit einem ersten und zweiten Substrat, wobei das erste Substrat hat: eine entgegengesetzte erste und zweite Oberfläche, mehrere erste leitende Kontaktlöcher, die sich durch die erste und zweite Oberfläche erstrecken, und eine erste Schaltungsanordnung, die auf der zweiten Oberfläche strukturiert und mit den ersten leitenden Kontaktlöchern elektrisch verbunden ist, wobei das zweite Substrat hat: eine entgegengesetzte erste und zweite Oberfläche, mehrere zweite leitende Kontaktlöcher, die sich durch die erste und zweite Oberfläche des zweiten Substrats erstrecken, eine zweite Schaltungsanordnung, die auf der zweiten Oberfläche des zweiten Substrats strukturiert und mit den zweiten leitenden Kontaktlöchern elektrisch verbunden ist, und eine darin ausgebildete erste Chipaufnahmeöffnung, wobei die erste Oberfläche des zweiten Substrats auf der zweiten Oberfläche des ersten Substrats verbunden ist, so daß die zweite Schaltungsanordnung ...

Verdrahtungssubstrat

Ein Verdrahtungssubstrat umfasst ein Substrat mit einem Verdrahtungsmuster und ein linienförmiges Isoliermuster, das auf dem Substrat derart gebildet ist, daß es das Verdrahtungsmuster schneidet und einen Teil des Verdrahtungsmusters für eine Anschlußbereichselektrode definiert. Das Isoliermuster umfasst eine Mehrzahl von linienförmigen Abschnitten, die miteinander verbunden sind, um eine rahmenartige Struktur zu bilden.

Halbleiter-Modul

Connection between sensor terminal and conductor path applied to glass plate uses conductive connection element ultrasonically welded to conductor path

Connection is provided by electrically conductive connection element (11), e.g. bonding wire, which is ultrasonically welded to conductor path (5) applied to surface of glass plate (1) and which is coupled to sensor terminal (13) mounted on glass plate. Surface (3) of glass plate is ridged at point of connection between conductor path and connection element, ultrasonic welding position lying in furrow between 2 ridges (4). An Independent claim for an application of a sensor terminal connection for a ceramic glass cooking hob surface is also included.

Packung mit aufgerauter verkapselter Oberfläche zur Förderung einer Haftung

Eine Packung (100), die mindestens einen elektronischen Chip (102), einen ersten wärmeabführenden Körper (104), der thermisch mit einer Hauptoberfläche des mindestens einen elektronischen Chips (102) gekoppelt ist und dafür ausgelegt ist, Wärmeenergie von dem mindestens einen elektronischen Chip (102) abzuführen, ein Kapselungsmittel (108), das mindestens einen Teil des mindestens einen elektronischen Chips (102) und einen Teil des ersten wärmeabführenden Körpers (104) verkapselt, wobei mindestens ein Teil einer Oberfläche des ersten wärmeabführenden Körpers (104) aufgeraut ist.

PACKAGES FOR ENCLOSING SEMICONDUCTOR ELEMENTS

Leistungsmodul

Ein Leistungsmodul umfasst eine Leistungshalbleitervorrichtung und eine Chip-Komponente, die auf einem ersten und einem zweiten Schaltungsmuster angeordnet ist, welche elektrisch mit der Leistungshalbleitervorrichtung verbunden sind, und die derart angeordnet ist, dass sie das erste und das zweite Schaltungsmuster überbrückt. Die Chip-Komponente ist derart angeordnet, dass jeweils eine erste und eine zweite Elektrode auf dem ersten und dem zweiten Schaltungsmuster positioniert sind, und die erste und die zweite Elektrode und das erste und das zweite Schaltungsmuster sind jeweils mit Lotschichten verbunden. Zwischen einer unteren Fläche der Chip-Komponente und dem ersten Schaltungsmuster und zwischen der unteren Fläche der Chip-Komponente und dem zweiten Schaltungsmuster sind zwei Abstandhalter vorgesehen, die an Positionen nahe der ersten und der zweiten Elektrode jeweils parallel zueinander liegen. Die Lotschichten existieren nicht auf einer inneren Seite der beiden parallel zueinander ...

SEMICONDUCTOR PACKAGE

Halbleiterbauelement

The invention relates to a semiconductor component comprising two semiconductor bodies (3, 11), which are spatially separated from one another and electrically interconnected. According to the invention, a compensation MOS field effect transistor (23) is provided as the first semiconductor body (3), and a silicon carbide Schottky diode is provided as the second semiconductor body (11).

Halbleiterbauelement und Verfahren zum Herstellen eines Halbleiterbauelements

Die Erfindung betrifft ein Halbleiterbauelement (4) mit zumindest einem Chip (2) und einem Substrat (7), wobei der Chip (2) eine Rückseite (6) aufweist, welche mit einer ersten Oberfläche (8) des Substrats (7) mittels Diffusionslöten verbunden ist, wobei in der ersten Oberfläche (8) des Substrats (7) Vertiefungen (11) ausgebildet sind, welche intermetallische Phasen enthalten, die während des Diffusionslötens gebildet werden. Die Erfindung betrifft weiterhin Verfahren zum Herstellen eines Halbleiterbauelements (4), welches die Schritte umfasst: Beschichten einer Rückseite (6) eines Chips (2) mit einem Lotmetall, welches zum Diffusionslöten geeignet ist; Anfertigen eines Substrats (7) mit einer ersten Oberfläche (8), die aus einem Material besteht, welches zum Diffusionslöten geeignet ist; Bilden von Vertiefungen (11) in der ersten Oberfläche (8) des Substrats (7); und Verbinden der Rückseite (6) des Chips (2) mit der ersten Oberfläche (8) des Substrats (7) durch Diffusionslöten.

GEHAEUSETEIL FUER HALBLEITERBAUELEMENTE

Leistungsmodul

The invention relates to a power module having a simple and cost-effective arrangement and ensuring reliable operation. To this end, a circuit comprising at least one electronic component is arranged on a carrier body. A conductor pattern is embodied on the upper side of said carrier body, and a structured cooler element consisting of the material of the carrier body is provided on the lower side of the same. The invention also relates to the use of the power module as a power converter for electric motors.

Polymer Stud Grid Array und Verfahren zur Herstellung eines derartigen Polymer Stud Grid Arrays

Auf einem Substrat (S) werden eine erste Verdrahtungslage (V1) und metallisierte Durchkontaktierungslöcher (D) gebildet. Auf die Oberseite (O1) des Substrats (S) wird dann durch Spritzgießen eine Substratlage (SL) aufgebracht, wobei das Material durch die Durchkontaktierungslöcher (D) hindurchtritt und auf der Unterseite (U) des Substrats (S) Polymerhöcker (PS) entstehen. Eine auf der Substratlage (SL) gebildete zweite Verdrahtungslage (V2) ist über Sackloch-Durchkontaktierungen (SD) mit der ersten Verdrahtungslage (V1) und damit über die Durchkontaktierungslöcher (D) mit Außenanschlüssen (AA) auf den Polymerhöckern (PS) elektrisch leitend verbunden.

A method of manufacturing an integrated circuit package and an integrated circuit package

A method of manufacturing an integrated circuit package

Ball grid array package

IC device with a metal thermal conductive layer having an opening for evacuating air

An IC device comprises an interconnection substrate 50 having at least one conductive layer 70 and at least one insulating layer 32, a first metal thermal conductive layer 70 and a second metal thermal conductive layer 83 having a surface exposed to an exterior. This second layer 83 has an opening 84 formed at a central portion, and a hole region 36 is formed within the interconnection substrate 50 and the first metal thermal conductive layer 70. An IC chip 40 is positioned with a first surface disposed at a central portion of the hole region 36. A second surface of the IC chip 40 has a plurality of bond pads 41. The chip 40 has a width larger than the diameter of the opening 84 in the second thermal conductive later 83 and is in contact with the second thermal conductive layer 83. A plurality of bond wires 9 electrically connect the bond pads 41 on the IC chip 40 with the first conductive trace layer 70, and an encapsulation material 42 fills the hole region 36 and encloses the bond wires ...

Hybrid integrated circuit module

Assemblies of an IC module and a carrier

A carrier element for an IC module (integrated circuit) comprising leads which are connected at one end with the corresponding terminals of the module and at the other end have a contact surface. The ends of the leads running into the contact surfaces extend unsupported beyond the edge of the carrier so that they can be bent into the desired position according to the intended purpose of the carrier element. When the leads are bent around the carrier plane towards the back surface of the module and united by using a castable material in a casting the result is a compact carrier element well adapted to the dimensions of the IC module. For the incorporation of the carrier element according to the invention into an identification card the free ends of the leads can be directed through corresponding recesses in the cover film of the card. During lamination of the layers of the identification card the ends of the leads are bent onto the cover film and thus pressed into the film material.

Liquid crystal display

Production of large scale integrated circuit chips

A connection network for an integrated circuit comprises two intersecting (preferably orthogonal) sets of grooves (8, 9) in a substrate 1, with the grooves of one set (8) deeper than those of the other set (9) and with conductive strips (18, 19, 22, 24 to 27, 29) at the bottoms of the grooves interconnected by further strips (20, 21, 23, 28) at selected regions of the groove side walls to provide a desired pattern of interconnections. The substrate may be of silicon with V-grooves (8, 9) formed by etching. The grooves may be filled with a dielectric material and conductive bridges (30) deposited to join the conductive strips in the shallower grooves. Semiconductor devices may be mounted on the mesas between the grooves and wire bonded to pads forming part of the connection network. ...

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SELECTIVE CONNECTION DURING THE IC PACKAGING

PROCEDURE FOR THE PRODUCTION OF A PRINTED CIRCUIT BOARD WITH A CAVITY FOR THE INTEGRATION OF CONSTRUCTION UNITS

BALL MATRIX HOUSING WITH HEAT DISTRIBUTOR AND ITS PRODUCTION

CHIP MODULE

SEMICONDUCTOR CHIP ARRANGEMENTS, MANUFACTURING METHODS AND COMPONENTS FOR THE SAME

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

HERMETIC PACKAGE FOR INTEGRATED CIRCUIT CHIPS

Semi Conductor Device and Method for Fabricating The Same

METHOD FOR CONTACT BONDING ELECTRONIC COMPONENTS ON AN INSULATING SUBSTRATE AND COMPONENT MODULE PRODUCED ACCORDING TO SAID METHOD

A SUBSTRATE FOR A SEMICONDUCTOR DEVIE

HYBRID SEMICONDUCTOR CIRCUIT

Tab tape ball grid array package with vias laterally offset from solder ball bond sites

MOUNTING A SEMICONDUCTOR ELEMENT ON A FLEXIBLE INTEGRATING SUBSTRATE

Semiconductor device fabrication method and semiconductor device fabrication device

Packaging for a semiconductor chip

A thin multichip module

FLEXIBLE CIRCUIT DESIGN FOR MONITORING PHYSICAL BODIES

A flexible circuit may be provided that allows for the monitoring of a physical object. The flexible circuit includes a plurality of flexible conductive segments that are disposed in a geometric pattern. The flexible conductive segments include nodes, and the physical object is monitored by analyzing changes in electrical resistance in the conductive segments between the nodes. The flexible circuit may also include sensors disposed on the nodes for monitoring additional conditions. A processor monitors the flexible conductive segments and sensors, and may provide an output regarding the status of the physical object.

INTERCONNECTION SYSTEM FOR INTEGRATED CIRCUIT CHIPS

A novel packaging system for VLSI circuits allows low-cost construction and maintenance of complex high density highperformance devices with low power requirements. The devices can be individually created by software means from a small selection of standardizable IC chips by disposing a plurality of chips in leadless chip carriers in a mosaic on a substrate, and configuring them by software to selectively communicate with other chips of the mosaic or even to individually change their operating function. The immediate juxtaposition of the chip carries in the mosaic eliminates transmission line data skew, and also allows considerable savings in chip space and power requirements by dispensing with interconnection drivers, receivers and bonding pads. The chip carrier mosaics may be assembled into modules suitable for plug-in connection to an interconnecting backplane to create even larger devices, and individual modules can be dynamically tested in their high-performance mode by configuring ...

MODULAR INTEGRATED CIRCUIT DEVICE

A novel packaging system for VLSI circuits allows low-cost construction and maintenance of complex high density highperformance devices with low power requirements. The devices can be individually created by software means from a small selection of standardizable IC chips by disposing a plurality of chips in leadless chip carriers in a mosaic on a substrate, and configuring them by software to selectively communicate with other chips of the mosaic or even to individually change their operating function. The immediate juxtaposition of the chip carriers in the mosaic eliminates transmission line data skew, and also allows considerable savings in chip space and power requirements by dispensing with interconnection drivers, receivers and bonding pads. The chip carrier mosaics may be assembled into modules suitable for plug-in connection to an interconnecting backplane to create even larger devices, and individual modules can be dynamically tested in their high-performance mode by configuring ...

METHOD OF BUILDING A VARIETY OF COMPLEX INTEGRATED CIRCUITS FROM STANDARDIZABLE COMPONENTS

METALLIZED CERAMIC SUBSTRATE HAVING SMOOTH PLATING LAYER AND METHOD FOR PRODUCING THE SAME

A metallized ceramic substrate having a smooth plating layer, comprising a ceramic substrate comprising aluminum nitride as a main component; a tungsten- and/or molybdenum-based metallized layer formed on at least one face of the ceramic substrate and a nickel-based plating layer which is formed on the metallized layer and has a thickness of not greater than 2 .mu.m and a surface roughness (Ra) of not greater than 2 .mu.m. In another aspect, the plating layer may be constituted of a first nickel-based plating layer and a second gold-based plating layer in which the first plating layer and the second plating layer have a thickness of not greater than 2 .mu.m and a thickness of not greater than 1 .mu.m, respectively, and the surface roughness (Ra) of the second layer should be 2 .mu.m or less. These metallized substrates are produced by applying a metallizing paste of W and/or Mo onto a green A1N ceramic substrate, flattening, firing and forming the foregoing plating layer or layers.

TAB TAPE BALL GRID ARRAY PACKAGE WITH VIAS LATERALLY OFFSET FROM SOLDER BALL BOND SITES

A ball grid array (BGA) package is provided in which the stiffener of the BGA may also be utilized as a conductive layer. A TAB tape is adhered to the stiffener by an adhesive and both the TAB tape and the adhesive may have vias which open to the stiffener. Conductive plugs which may be formed of solder paste, conductive adhesives, or the like may then be filled in the vias to provide electrical connection from the TAB tape to the stiffener. The vias may be located adjacent to solder ball locations. The TAB tape may include multiple conductor layers or multiple layers of single conductive layer TAB tape may be stacked upon each other to provide additional circuit routing. Further, the TAB tape layers may also be combined with the use of metal foil layers.

METHOD TO CONTROL CAVITY DIMENSIONS OF FIRED MULTILAYER CIRCUIT BOARDS ON A SUPPORT

Patterned laminated green tape multilayer stacks (130) can be fired while maintaining the dimensions of the pattern (120) by applying, as by screen printing or spraying, a ceramic ink (108) over surface portions of the green tape stack. Complex patterns can be formed in the green tapes by punching openings (120) in one or more of the green tape stacks (100) before laminating them together.

Circuit board and method for its production

The circuit board comprises a substrate consisting of an electrically insulating material. On its top, the substrate has an inwardly tapering depression (10') and a recess (10''') which extends from the base (10'') of the depression into the substrate. Arranged in the recess is a semiconductor element (A) which is electrically connected to leads (20) on the top of the substrate. The leads extend over the inclined wall of the depression to the edge of the recess. The semiconductor element is surrounded by synthetic resin (P) which fills the recess and the depression. The free surface of the plastic is coplanar with the top of the substrate. The lead pattern (20) is produced with the aid of a photomask and of a photoresist layer which is applied onto the substrate. The photomask is in this case arranged at a distance from the substrate and is imaged on the photoresist layer of the substrate with the aid of an objective lens which is arranged between the photomask and the substrate. If the ...

CARRIER ELEMENT WITH A IC COMPONENT AND A BADGE.

Semiconductor device and radiation detector employing it

Chip encapsulation structure capable of realizing electrical connection without routing and manufacture method thereof

The invention provides a chip encapsulation structure capable of realizing electrical connection without routing. The structure comprises an insulating substrate unit, an encapsulation unit, a semiconductor chip, a first conductive unit, an insulating unit and a second conductive unit, wherein the encapsulation unit is arranged on the insulating substrate unit to form an accommodating groove; the semiconductor chip is accommodated in the accommodating groove, and is provided with a plurality of conductive solder pads; the first conductive unit is provided with a plurality of first conductive layers formed on the encapsulation unit, and one end of each first conductive layer is electrically connected with the corresponding conductive solder pad; the insulating unit is provided with an insulating layer formed among a plurality of first conductive layers; and the second conductive unit is provided with a plurality of second conductive layers formed on the opposite end of a plurality of the ...

Lead frame and base island structure in integrated circuit package

Semiconductor device and packaging method thereof

PACKAGING SUBSTRATE AND PACKAGE STRUCTURE

Semiconductor device packages with electromagnetic interference shielding

Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit defining a cut-out portion disposed adjacent to a periphery of the substrate unit; (2) a grounding element disposed in the cut-out portion and at least partially extending between an upper surface and a lower surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device and the grounding element; and (5) an EMI shield disposed adjacent to exterior surfaces of the package body. The EMI shield is electrically connected to a connection surface of the grounding element, such that the grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.

Multiple -chip packaging structure

Power semiconductor module

Large power crimping type IGBT device

Stack packaging device

A used for chip ultrasonic aluminum wire welding wire

Package for optical device and method of manufacturing the same

A package for an optical device includes a plurality of ceramic layers 101, 102 and 103 stacked on a base 2 and a recessed portion 18 formed to mount an optical element at the center. Reversely rounded portions 11 are formed on the corners of the ceramic layers 100, 101 and 102 such that at least one of the four corners of the top ceramic layer 103 has an outside shape placed outside the outside shapes of the corners of the ceramic layers 100, 101 and 102 with respect to the center.

Light source device

Top-side cooled semiconductor package with stacked interconnection plates and method

A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate ...

Multi-level light emitting diode array

A base plate for mounting the pick-up element and the imaging device

Micro and millimeter wave circuit

The embodiment of the invention provides a micro and millimeter wave circuit, which comprises a multilayer circuit board, a hot substrate and a circuit module, wherein the multilayer circuit board is provided with a window; the hot substrate comprises a pedestal; the multilayer circuit board is attached to the pedestal; the hot substrate further comprises a lug boss extended to the interior of the window of the multilayer circuit board from the pedestal; and the circuit module is embedded into the window, positioned on the lug boss and electrically connected with an outer conductor layer of the multilayer circuit board.

Method for manufacturing photoelectric element, encapsulation structure and encapsulation device thereof

The invention relates to a method for manufacturing a photoelectric element, an encapsulation structure and an encapsulation device thereof. The method for manufacturing the photoelectric element comprises the following steps of: firstly, providing a ceramic substrate, and arranging a plurality of photoelectric element grains on the upper surface of the ceramic substrate; then forming a first encapsulation layer on the upper surface of the plurality of photoelectric element grains, positioning the ceramic substrate between a lower die and an upper die, and placing a buffer layer between the lower die and the ceramic substrate; and finally, forming a plurality of lenses on the upper surface of the first encapsulation layer in a mode of injection molding or transfer molding.

In the power semiconductor module substrate of the flexible connection

Chip card mould board

Semiconductor device

Multi-layer ceramic components and manufacturing thereof

半导体封装结构及其制造方法

... 一种半导体封装的结构及其制造方法，该结构包括：具有导体片的构架，每个导体片皆掩埋在通过该构架敞开且按一定间隔设置的数个小孔中的一个中；具有固定于夹具上并在四个方向上延伸的引线的TAB，每根引线用于电连接一个导体片。所说方法包括以下步骤：根据封装的形状提供构架；把引线贴装在夹具上，使之在四个方向上延伸，构成TAB；在构架上按一定间隔形成小孔；在每个小孔中掩埋一个导体片；回流TAB上的引线，电连接引线与各导体片，并把引线贴装到构架上。 ...

Display device

A display device is provided. The display device includes: a light emitting area and a sub-area spaced apart from the light emitting area in a first direction; electrodes extending in a first direction to be disposed over the light emitting region and the sub-region, and spaced apart from each other in a second direction; a first bank disposed to surround the light emitting region and the sub-region; and a light emitting element disposed on the electrodes spaced apart from each other in the second direction in the light emitting region, in which the first bank has a portion recessed in an upper surface thereof, and includes a trench portion disposed between the light emitting region and the sub-region.

Board-level structure and communication equipment

The invention provides a board-level structure and communication equipment. Comprising an upper-layer substrate, a lower-layer substrate and a plurality of supporting pieces capable of being supported between the upper-layer substrate and the lower-layer substrate; a gap is formed between the upper layer substrate and the lower layer substrate and comprises at least one first gap area and at least one second gap area, the first gap area and the second gap area are spaced, and the spacing area between the first gap area and the second gap area does not comprise the first gap area or the second gap area. The maximum vertical distance between the upper-layer substrate and the lower-layer substrate in the first gap area is smaller than the minimum vertical distance between the upper-layer substrate and the lower-layer substrate in the second gap area, and the difference value between the maximum vertical distance and the minimum vertical distance is larger than or equal to 100 micrometers; ...

Bonded body, ceramic circuit board, and semiconductor device

A bonded body according to an embodiment includes a ceramic substrate, a copper plate, and a bonding layer. The bonding layer is disposed on at least one surface of the ceramic substrate and bonds the ceramic substrate and the copper plate. The bonding layer contains a Ti reaction layer and a plurality of first alloys. The Ti reaction layer contains titanium nitride or titanium oxide as a main component. The plurality of first alloys are located between the Ti reaction layer and the copper plate. Each of the plurality of first alloys contains at least one type of alloy selected from the group consisting of a Cu-Sn alloy and a Cu-In alloy. The plurality of first alloys have mutually different Sn concentrations or In concentrations. According to the embodiment, the warping amount can be reduced, and the temperature rising speed and the temperature falling speed of the bonding process can be improved. In an embodiment, a silicon nitride substrate is suitable as a ceramic substrate.

PROCESS FOR the REALIZATION Of a SUBSTRATE DIAMOND AND SUBSTRATE DIAMOND OBTENUPAR SUCH a PROCESS

HYBRID CIRCUITS

PROCESS Of ASSEMBLY Of a MICROCIRCUIT ON a PLASTIC SUPPORT

SUPPORT INSULATING FOR SEMICONDUCTOR ELEMENTS HAS HIGH VOLTAGE

PROCEDE DE FABRICATION DE BOSSAGES METALLIQUES CALIBRES SUR UN FILM SUPPORT ET FILM SUPPORT COMPORTANT DE TELS BOSSAGES

L'INVENTION SE RAPPORTE AUX CIRCUITS SUR FILMS-SUPPORTS. L'INVENTION A POUR OBJET UN PROCEDE DE FABRICATION DE BOSSAGES METALLIQUES CALIBRES SUR FILM-SUPPORT PLASTIQUE CONSISTANT A FORMER DANS CE FILM DES FENETRES, A COLLER SUR UNE FACE DU FILM PLASTIQUE UN FILM METALLIQUE, A REVETIR LE FILM METALLIQUE AFFLEURANT AU FOND DES ALVEOLES AINSI FORMEES D'UN MATERIAU DE SOUDURE, PUIS A PLACER DANS LES ALVEOLES DES BILLES METALLIQUES CALIBREES. L'ENSEMBLE PEUT ETRE PRESSE DE MANIERE A FORMER DES MEPLATS SUR LA BILLE, AU NIVEAU DU MATERIAU DE SOUDURE ET DANS UNE ZONE DIAMETRALEMENT OPPOSEE. LE FILM PORTANT LES BILLES EST ENSUITE PORTE A LA TEMPERATURE DE SOUDURE. APPLICATION, NOTAMMENT, A LA FABRICATION DE BOSSAGES ALIGNES AYANT UN ESPACEMENT DE L'ORDRE DE 1MM FORMANT DES POINTES DESTINEES A L'IMPRESSION ELECTROCATALYTIQUE.

ELECTRONIC CIRCUIT HAS WASTEFUL HEAT OF EASY INSTALLATION AND HAS SURFACED' EXCHANGES WIDE

MECHANICAL OR ELECTRIC THERMIC SYSTEMS

Ce support est évidé (1), et comprend deux faces d'appui, sensiblement parallèles l'une par rapport à l'autre, et séparées l'une de l'autre par une face latérale définissant un périmètre. Ladite face latérale comprend des orifices traversants (2), répartis sur au moins une rangée (4) sensiblement parallèle audites faces d'appui. Le support (1) comporte au moins une bride de renfort (3), en contact avec ladite face latérale dudit support (1), tout le long dudit périmètre de ladite face latérale, sur ou au voisinage de la ou de chaque rangée (4) d'orifices traversants (2).

Method for industrial production of thermal dissipation elements from a strip of metal for supporting semiconductors

Selon le procédé : - on soumet la bande (1) à au rnoins une opération apte à enlever de la matière selon son épaisseur; - on enlève la matière selon au moins deux rainures (1a) et (1b) formées parallèlement et/ ou perpendiculairement à l'axe longitudinal de la bande, de manière à délimiter une partie en surépaisseur qui fait office de radiateur thermique apte à recevoir directement l'élément semi-conducteur.

MECHANICAL OR ELECTRIC THERMIC SYSTEMS

A method of making a hybrid module

L'invention concerne les modules hybrides dans lesquels une pluralité de puces de circuits intégrés (20) sont logées dans des alvéoles (18) creusées dans une tranche de silicium ( 10). Selon ce procédé, un réseau d'interconnexions (13) des puces (20) est d'abord réalisé sur une face du substrat (10): il comprend au moins une couche de polymère. Puis les alvéoles (18) sont gravées à partir de l'autre face du substrat (10), jusqu'à rencontrer le réseau d'interconnexions (13). Les puces sont disposées dans les alvéoles (18) et interconnectées (26). Application à la réalisation de Structures en trois dimensions.

SEMICONDUCTOR INTERPOSER, INTEGRATED CIRCUIT PACKAGE, AND METHOD FOR IMPROVING THE RELIABILITY OF A CONNECTION TO A VIA IN A SUBSTRATE

Electronic module with vertical connector between conductor patterns

The present invention generally relates to a new structure to be used with electronic modules such as printed circuit boards and semiconductor package substrates. Furthermore there are presented herein methods for manufacturing the same. According to an aspect of the invention, the aspect ratio of through holes is significantly improved. Aspect ratio measures a relationship of a through hole or a micro via conductor in the direction of height divided width. According to the aspect of the invention, the aspect ratio can be increased over that of the prior art solution by a factor of ten or more.

Gain Enhanced LTCC System-on-Package for UMRR Applications

An apparatus, system, and method for Gain Enhanced LTCC System-on-Package radar sensor. The sensor includes a substrate and an integrated circuit coupled to the substrate, where the integrated circuit is configured to transmit and receive radio frequency (RF) signals. An antenna may be coupled to the integrated circuit and a lens may be coupled to the antenna. The lens may be configured to enhance the gain of the sensor.

Flexible circuit structure with stretchability and method of manufacturing the same

In one example embodiment, a flexible circuit structure with stretchability is provided that includes a flexible substrate, a plurality of flexible bumps formed on the flexible substrate, and a metal layer formed on the plurality of flexible bumps and the flexible substrate.

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

Semiconductor device having semiconductor member and mounting member

A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.

Semiconductor device and test system for the semiconductor device

A semiconductor package including a stress mitigation unit that mitigates stress to the semiconductor chip. The semiconductor package includes a substrate, a semiconductor chip on the substrate, an encapsulation member formed on the substrate and covering the first semiconductor chip, and the stress mitigation unit mitigating stress from a circumference of the first semiconductor chip to the first semiconductor chip. The stress mitigation unit includes at least one groove formed in the encapsulation member.

Semiconductor package module

There is provided a semiconductor package module capable of minimizing a thickness of the module in spite of including an electronic element having a large size. The semiconductor package module includes: a semiconductor package having a shield formed on an outer surface and a side thereof and at least one receiving part provided in a lower surface thereof, the receiving part having a groove shape; and a main substrate having at least one large element and the semiconductor package mounted on one surface thereof, wherein the large element is received in the receiving part of the semiconductor package and is mounted on the main substrate.

Base plate

The present disclosure relates to a base plate, for example, for a power module, including a matrix formed of metal, for example, aluminium, wherein at least two reinforcements are provided in the matrix next to each other, and wherein the reinforcements are spaced apart from each other.

Semiconductor Device And Method Of Manufacturing Semiconductor Device

A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

Microelectronic devices and methods for manufacturing microelectronic devices

Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in a substrate with the apertures arranged in an array, and, after forming the apertures, attaching the substrate to a lead frame having a plurality of pads with the apertures in the substrate aligned with corresponding pads in the lead frame. Another method includes providing a partially cured substrate, coupling the partially cured substrate to a plurality of leads, attaching a microelectronic die to the leads, and electrically connecting the microelectronic die to the leads.

Magnetic shielding for multi-chip module packaging

A system comprises a plurality of stacked integrated circuit dice, each integrated circuit die comprising at least one circuit, a package enclosing the plurality of dice, and at least two magnetic shields configured to magnetically shield the at least one circuit of each of the plurality of integrate circuit dice. At least one of the magnetic shields is within the package, and at least two of the plurality of stacked integrated circuit dice are positioned between the at least two magnetic shields.

Laminated wiring board

In a multilayer wiring board 1, a low resistance silicon substrate 2 having a predetermined resistivity and a high resistance silicon substrate 4 having a resistivity higher than the predetermined resistivity are stacked while interposing an insulating layer 3 therebetween. The low resistance silicon substrate 2 is provided with an electric passage part 6 surrounded by a ring-shaped groove 5, while a wiring film 13 electrically connected to the electric passage part 6 through an opening 8 of the insulating layer 3 is disposed on a rear face 4 b of the high resistance silicon substrate 4 and an inner face 11 a of a recess 11. Since the high resistance silicon substrate 4 is thus provided with the wiring film 13, an optical semiconductor element 20 and an electronic circuit element 30 which differ from each other in terms of the number and positions of electrode pads can be electrically connected to each other on the front and rear face sides of the multilayer wiring board 1.

Microelectronic package and method of manufacturing same

A microelectronic package includes a substrate ( 110, 210 ), an interposer ( 120, 220 ) having a first surface ( 121 ) and an opposing second surface ( 122 ), a microelectronic die ( 130, 230 ) attached to the substrate, and a mold compound ( 140 ) over the substrate. The interposer is electrically connected to the substrate using a wirebond ( 150 ). The first surface of the interposer is physically connected to the substrate with an adhesive ( 160 ), and the second surface has an electrically conductive contact ( 126 ) formed therein. The mold compound completely encapsulates the wirebond and partially encapsulates the interposer such that the electrically conductive contact in the second surface of the interposer remains uncovered by the mold compound.

Low cost thermally enhanced hybrid bga and method of manufacturing the same

A semiconductor package is formed having a substrate juxtaposed on at least two sides of a semiconductor die. Both the substrate and the semiconductor die are affixed to a conductive layer that draws heat generated during use of the semiconductor package away from the semiconductor die and the substrate. There are also electrical contacts affixed to the substrate and the semiconductor die. The electrical contacts facilitate electrical connection between the semiconductor die, the substrate, and any external devices or components making use of the semiconductor die. The substrate, semiconductor die, and at least a portion of some of the electrical contacts are enclosed by an encapsulating layer insulating the components. Portions of the electrical contacts not enclosed by the encapsulating layer are affixed to an outside device, such as a printed circuit board.

Packaged semiconductor device for high performance memory and logic

A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.

Compliant spring interposer for wafer level three dimensional (3d) integration and method of manufacturing

The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Signal routing Optimized IC package ball/pad layout

This invention provides layout schemes for ball/pad regions on a printed circuit board for a small regular ball/pad region grid that provides additional space between ball/pad regions for increased wiring capability. The layout scheme is consistent with printed circuit board manufacturing requirements and minimum wiring channel requirements demanded by high density integrated circuit chips.

System and method for improving frequency response

An electrical system and method for making the same includes a main circuit board and a plurality of contact pads located on a surface of the main circuit board. The contact pads are electrically conductive. Additionally, an integrated circuit package having at least one electrical device is attached to the surface of the main circuit board. A ball grid array made from a plurality of solder balls is located on a bottom side of the integrated circuit package. The ball grid array has a plurality of solder balls being electrically conductive and in electrical communication with the at least one electrical device. The solder balls further include solder balls of different material properties.

Coreless layer laminated chip carrier having system in package structure

A substrate for use in a laminated chip carrier (LCC) and a system in package (SiP) device having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can include thermoset and thermoplastic resin.

Enhanced Modularity in Heterogeneous 3D Stacks

A computer program product for generating and implementing a three-dimensional (3D) computer processing chip stack plan. The computer readable program code includes computer readable program code configured for receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to at least one layer in the 3D computer processing chip stack plan. The computer readable program code is also configured for identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The computer readable program code is further configured for determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment forms the 3D computer processing chip stack.

Chip-packaging module for a chip and a method for forming a chip-packaging module

A chip-packaging module for a chip is provided, the chip-packaging module including an isolation material configured to cover a chip on at least one side, the isolation material having a first surface proximate to a first side of a chip, and said isolation material having a second surface facing an opposite direction to the first surface; and at least one layer in connection with the chip first side, the at least one layer further configured to extend from the chip first side to the second surface of the isolation material.

Package carrier and method of manufacturing the same

A method of manufacturing a package carrier is provided. An insulation cover is provided. The insulation cover has an inner surface and an outer surface opposite to each other, a plurality of openings, and a containing space. A patterned metal layer is foamed on the outer surface of the insulation cover. A surface treatment layer is formed on the patterned metal layer. A heat dissipation element is formed in the containing space of the insulation cover and structurally connected to the insulation cover. A thermal-conductive layer is formed on a surface of the heat dissipation element, and a portion of the thermal-conductive layer is exposed by the openings of the insulation cover.

Stacked semiconductor package

A stacked semiconductor package includes a substrate having an upper surface and a lower surface, and divided into a first region and a second region that adjoins the first region; a support member formed in the second region on the upper surface of the substrate; and a semiconductor chip module including a plurality of semiconductor chips each of which has bonding pads near one edge of a first surface thereof and which are stacked on the support member in a step-like shape such that their bonding pads face the first region and are bent such that the bonding pads are electrically connected with the substrate.

Construction of reliable stacked via in electronic substrates - vertical stiffness control method

A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 μm. The platted through hole landing includes an etched pattern and a copper top surface.

Impedence controlled packages with metal sheet or 2-layer rdl

A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces.

Circuit board, semiconductor device, process for manufacturing circuit board and process for manufacturing semiconductor device

A circuit board ( 1 ) exhibits an average coefficient of thermal expansion (A) of the first insulating layer ( 21 ) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point of equal to or higher than 3 ppm/degrees C. and equal to or lower than 30 ppm/degrees C. Further, an average coefficient of thermal expansion (B) of the second insulating layer ( 23 ) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point is equivalent to an average coefficient of thermal expansion (C) of the third insulating layer ( 25 ) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point. (B) and (C) are larger than (A), and a difference between (A) and (B) and a difference between (A) and (C) are equal to or higher than 5 ppm/degrees C. and equal to or lower than 35 ppm/degrees C.

Memory module in a package

A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals.

Semiconductor assemblies with multi-level substrates and associated methods of manufacturing

Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate.

Fabrication method of packaging substrate having through-holed interposer embedded therein

A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.

High io substrates and interposers without vias

An interconnection component includes a substrate having first and second opposed major surfaces defining a thickness of less than 1000 microns and a first slot extending between the first and second surfaces, the first slot being enclosed by the substrate at the first and second surfaces. The first slot defines an edge surface between the first surface and the second surface. First conductive traces extend along the first surface and are electrically connected with first contact pads that overlie the first surface. Second conductive traces extend along the second surface and electrically connected with second contact pads that overlie the second surface. Interconnect traces extend along the edge surface of the first slot. Each interconnect trace directly connects at least one first trace with at least one second trace.

Wiring substrate and method of manufacturing the same

Embodiments of the present invention provide a wiring substrate which is excellent in terms of the reliability of connection between the wiring substrate and a semiconductor chip. In some embodiments the wiring substrate comprises a first build-up layer in which resin insulation layers and conductor layers are laminated alternately. The outermost conductor layer can include a plurality of connection terminal portions to which a semiconductor chip is flip-chip connected. The plurality of connection terminal portions can be exposed through openings of a solder resist layer. Each of the connection terminal portions includes a connection region to which a connection terminal of the semiconductor chip is to be connected, and a wiring region which extends in a planar direction from the connection region and which is narrower than the connection region. The surface of the wiring region has a solder wettability lower than that of the surface of the connection region.

Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate

A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with at least one external component. The substrate can have substrate contacts on the first surface facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid.

SEMICONDUCTOR DEVICE

A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided at the support substrate in relation to the high frequency electrode, and an external connection electrode that is provided on the other side of the support substrate in relation to the via hole. 1. A semiconductor device comprising:a substrate;a first semiconductor element that is mounted on one side of the substrate;a second semiconductor element including a first electrode that is mounted on the one side of the substrate;a second electrode that is provided on the other side of the substrate connects to the first electrode with a via hole that penetrates through the substrate;wherein the first electrode is positioned within a periphery of the via hole;the second semiconductor element includes rewiring that forms a passive element; andthe substrate and the first semiconductor and the second semiconductor are integrally sealed by molded resin.2. The semiconductor device as claimed in claim 1 , whereinthe first semiconductor element is stacked on the second semiconductor element.3. The semiconductor device as claimed in claim 1 , whereinthe second semiconductor element includes a shield member that is set to ground potential.4. The semiconductor device as claimed in claim 1 , whereinthe second semiconductor element includes a pair of re-wiring structures that include portions that are parallel to each other.5. The semiconductor device as claimed in claim 1 , whereinthe second semiconductor element includes a set of re-wiring structures that have substantially equivalent wiring lengths.6. The semiconductor device as claimed in claim 1 , wherein the via hole related to the first electrode has a diameter larger than a diameter of a second via hole connected to a ...

Ball Grid Array with Improved Single-Ended and Differential Signal Performance

An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns. 13-. (canceled)4. An integrated circuit package comprising a plurality of pins comprising:a plurality of pins, the plurality of pins comprising a first pin, a second pin, a third pin, and a fourth pin, each of the first, second, third, and fourth extending externally to the integrated circuit package, being linearly arranged in a first row and being equally spaced from each other;a fifth pin, a sixth pin, a seventh pin, an eighth pin and a ninth pin extending externally to the integrated circuit package, linearly arranged in a second row separated vertically from the first row and offset horizontally from the first row such that sixth, seventh, eighth and ninth pins are offset from the pins in the first row;wherein said third and seventh pins comprise power/ground pins; andwherein the remaining pins are configured for use as signal pins.5. The integrated circuit package of wherein:an arrangement of the plurality of pins is repeated within the integrated circuit package;the arrangement of the plurality of pins provides equally spaced sets of the plurality of pins.6. The integrated circuit package of wherein:the arrangement of the plurality of pins provides power/ground pins positioned substantially zigzagged across a plurality of rows.7. The integrated circuit package of wherein:the arrangement of the plurality of pins provides power/ground pins positioned substantially diagonally across a plurality of rows.8. The integrated circuit package of wherein:the arrangement of the plurality of pins provides power/ground pins positioned such that each power/ground pin is offset from a group of hexagonally configured signal pins.9. An integrated circuit package comprising: a first ...

MULTIMEDIA PROVIDING SERVICE

Provided is a semiconductor device of higher density, thin thickness and low cost not plagued with low reliability ascribable to concentration of internal stress in an ultimate product. The semiconductor device includes a semiconductor element, and a support substrate arranged on a surface of the semiconductor element opposite to its surface provided with a pad. The support substrate is wider in area than the semiconductor element. The semiconductor device also includes a burying insulating layer on the support substrate for burying the semiconductor element in it, and a fan-out interconnection led out from the pad to an area on the burying insulating layer lying more peripherally outwardly than the semiconductor element; and a reinforcement portion arranged in a preset area above the outer periphery of the semiconductor element for augmenting mechanical strength of the burying insulating layer and the fan-out interconnection (FIG. ). 1. A semiconductor device comprising:a semiconductor element;a support substrate arranged on a surface of said semiconductor element opposite to a surface thereof provided with a pad; said support substrate being bigger in area than said semiconductor element;a burying insulating layer on said support substrate for burying said semiconductor element therein;a fan-out interconnection led out from said pad to an area on said burying insulating layer extending to an area lying more peripherally outwardly than said semiconductor element; anda reinforcement portion via interconnection connected to at least one end of said semiconductor element without being connected to said fan-out interconnection.2. The semiconductor device according to claim 1 , whereinsaid reinforcement portion via interconnection is formed of the same material as that of said fan-out interconnection.3. The semiconductor device according to claim 1 , whereinsaid reinforcement portion via interconnection has a modulus of elasticity higher than that of said fan-out ...

ELECTRONIC, OPTICAL AND/OR MECHANICAL APPARATUS AND SYSTEMS AND METHODS FOR FABRICATING SAME

Flexible electronic structure and methods for fabricating flexible electronic structures are provided. An example method includes applying a first layer to a substrate, creating a plurality of vias through the first layer to the substrate, and applying a second polymer layer to the first layer such that the second polymer forms anchors contacting at least a portion of the substrate. At least one electronic device layer is disposed on a portion of the second polymer layer. At least one trench is formed through the second polymer layer to expose at least a portion of the first layer. At least a portion of the first layer is removed by exposing the structure to a selective etchant to providing a flexible electronic structure that is in contact with the substrate. The electronic structure can be released from the substrate. 155-. (canceled)56. A flexible electronic structure , comprising:a base polymer layer having a first surface and a second surface, wherein the first surface comprises a plurality of anchors; andat least one electronic device layer disposed above a portion of the second surface of the base polymer.57. The flexible electronic structure of claim 56 , wherein an average width of the plurality of anchors is in a range from about 10 μm to about 50 μm.58. The flexible electronic structure of claim 56 , wherein an average width of the plurality of anchors is in a range from about 0.1 μm to about 1000 μm.59. The flexible electronic structure of claim 56 , wherein at least some of the plurality of anchors have a substantially circular cross-section claim 56 , a substantially hexagonal cross-section claim 56 , a substantially oval cross-section claim 56 , a substantially rectangular cross-section claim 56 , a polygonal cross-section claim 56 , or a non-polygonal cross-section.60. The flexible electronic structure of claim 56 , wherein the plurality of anchors are formed in a two-dimensional array.61. The flexible electronic structure of claim 56 , wherein an ...

Chip carriers, semiconductor devices including the same, semiconductor packages including the same, and methods of fabricating the same

Chip carriers are provided. The chip carrier includes a carrier body having a cavity therein and at least one conductive through silicon via (TSV) penetrating the carrier body under the cavity. The cavity includes an uneven sidewall surface profile. The at least one conductive through silicon via (TSV) is exposed at a bottom surface of the carrier body opposite to the cavity. Related methods are also provided.

PACKAGE OF ELECTRONIC DEVICE INCLUDING CONNECTING BUMP, SYSTEM INCLUDING THE SAME AND METHOD FOR FABRICATING THE SAME

A package of an electronic device, a system including the same and a method for fabricating the same are provided. The package of the electronic device includes a substrate, a step difference layer and a connecting bump. The substrate allows a connecting contact part to be exposed on a surface thereof. The step difference layer covers the substrate so as to leave the connecting contact part exposed. The connecting bump is connected to the connecting contact part so that one end part of the connecting bump is extended on the step difference layer, and has a sloped upper surface formed by a step difference formed by the step difference layer. 1. A package of an electronic device , comprising:a substrate configured to allow a connecting contact part to be exposed on a surface thereof;a step difference layer configured to cover the substrate so as leave the connecting contact part exposed; anda connecting bump configured to be connected to the connecting contact part so that one end part of the connecting bump is extended on the step difference layer, and have a sloped upper surface formed by a step difference formed by the step difference layer.2. The package of claim 1 , wherein the substrate is a semiconductor substrate of a semiconductor chip claim 1 , on which an integrated circuit is integrated claim 1 , a printed circuit board (PCB) on which the semiconductor chip is to be mounted claim 1 , or a package substrate including an interposer substrate.3. The package of claim 2 , wherein the semiconductor substrate comprises a through electrode providing the connecting contact part as an exposed surface.4. The package of claim 3 , further comprising a conductive layer configured to be connected to the exposed surface of the through electrode on the substrate so as to be used as a contact pad or redistribution layer (RDL).5. The package of claim 1 , wherein the step difference layer comprises an insulating layer having an opening through which the connecting contact ...

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Multiple die stacking for two or more die

A microelectronic package can include a substrate having first and second opposed surfaces, and first and second microelectronic elements having front surfaces facing the first surface. The substrate can have a plurality of substrate contacts at the first surface and a plurality of terminals at the second surface. Each microelectronic element can have a plurality of element contacts at the front surface thereof. The element contacts can be joined with corresponding ones of the substrate contacts. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. The element contacts of the first microelectronic element can be arranged in an area array and are flip-chip bonded with a first set of the substrate contacts. The element contacts of the second microelectronic element can be joined with a second set of the substrate contacts by conductive masses.

Semiconductor Device and Method of Forming Conductive Posts and Heat Sink Over Semiconductor Die Using Leadframe

A semiconductor device has a prefabricated multi-die leadframe with a base and integrated raised die paddle and a plurality of bodies extending from the base. A thermal interface layer is formed over a back surface of a semiconductor die or top surface of the raised die paddle. The semiconductor die is mounted over the raised die paddle between the bodies of the leadframe with the TIM disposed between the die and raised die paddle. An encapsulant is deposited over the leadframe and semiconductor die. Vias can be formed in the encapsulant. An interconnect structure is formed over the leadframe, semiconductor die, and encapsulant, including into the vias. The base is removed to separate the bodies from the raised die paddle. The raised die paddle provides heat dissipation for the semiconductor die. The bodies are electrically connected to the interconnect structure. The bodies operate as conductive posts for electrical interconnect. 1. A method of making a semiconductor device , comprising:providing a substrate including a raised die area and a plurality of conductive bodies extending from the substrate;disposing a semiconductor die over the raised die area between the conductive bodies of the substrate;depositing an encapsulant over the substrate and semiconductor die;forming an interconnect structure over the encapsulant, the interconnect structure being electrically connected to the conductive bodies; andremoving a portion of the substrate to separate the conductive bodies from the raised die area.2. The method of claim 1 , wherein the raised die area provides heat dissipation for the semiconductor die.3. The method of claim 1 , further including disposing a thermal interface material between the semiconductor die and raised die area.4. The method of claim 1 , further including forming a plurality of bumps over the semiconductor die.5. The method of claim 1 , further including:forming a plurality of vias in the encapsulant extending to the conductive bodies; ...

SEMICONDUCTOR PACKAGE FEATURING FLIP-CHIP DIE SANDWICHED BETWEEN METAL LAYERS

Embodiments in accordance with the present invention relate to flip-chip packages for semiconductor devices, which feature a die sandwiched between metal layers. One metal layer comprises portions of the lead frame configured to be in electrical and thermal communication with various pads on a first surface of the die (e.g. IC pads or MOSFET gate or source pads) through a solder ball contact. The other metal layer is configured to be in at least thermal communication with the opposite side of the die. Embodiments of packages in accordance with the present invention exhibit superior heat dissipation qualities, while avoiding the expense of wire bonding. Embodiments of the present invention are particularly suited for packaging of power devices. 1. A package for a semiconductor device , the package comprising:a first metal layer configured to be in thermal and electrical communication with a power device die; anda second metal layer disposed on an opposite side of the power device die from the first metal layer, the second metal layer configured to be in electrical and thermal communication with a pad on a surface of the power device die through physical contact with a solder ball contact, the first metal layer comprising integral leads projecting from a plastic package body encapsulating the power device die, the solder ball contact, and at least a part of the first and second metal layers;wherein the first metal layer is configured to be in electrical communication with the power device die through a second solder ball contact.2. A package for a semiconductor device , the package comprising:a first metal layer configured to be in thermal and electrical communication with a MOSFET die; a first portion configured to be in electrical communication with a gate pad on a surface of the MOSFET die, and', 'a second portion configured to be in electrical and thermal communication with a source pad on the surface of the MOSFET die through physical contact with a solder ball ...

Semiconductor package including semiconductor chip with through opening

A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.

High strength through-substrate vias

A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter.

Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected through Conductive Vias Formed in Encapsulant Around Die

A semiconductor device has a first semiconductor die and first encapsulant deposited around the first semiconductor die. A first insulating layer is formed over the first semiconductor die and first encapsulant. A first conductive layer is formed over the first insulating layer and electrically connected to a contact pad of the first semiconductor die. A second semiconductor die is mounted to the first insulating layer and first conductive layer. A second encapsulant is deposited around the second semiconductor die. A second insulating layer is formed over the second semiconductor die and second encapsulant. A second conductive layer is formed over the second insulating layer and electrically connected to a contact pad of the second semiconductor die. A plurality of conductive vias is formed continuously through the first and second encapsulants outside a footprint of the first and second semiconductor die electrically connected to the first and second conductive layers. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;depositing a first encapsulant around the first semiconductor die;forming a first conductive layer over the first encapsulant;disposing a second semiconductor die over the first semiconductor die;depositing a second encapsulant around the second semiconductor die; andforming a second conductive layer over the second encapsulant.2. The method of claim 1 , further including forming a plurality of conductive vias through the first encapsulant and second encapsulant and electrically connected to the first conductive layer and second conductive layer.3. The method of claim 1 , further including:disposing a third semiconductor die over the second semiconductor die;depositing a third encapsulant around the third semiconductor die; andforming a third conductive layer over the third encapsulant.4. The method of claim 1 , further including forming an interconnect structure over the first semiconductor die or second ...

Semiconductor package and semiconductor package module having the same

Disclosed herein is a semiconductor package including: a semiconductor chip having a bonding pad; and a first substrate including a rerouting layer having short type rerouting patterns electrically connected with the bonding pad and formed to be seamlessly connected with each other and a plurality of open type rerouting patterns separately formed on the same layer as the short type rerouting patterns and connection terminals for signal connection each formed on the open type rerouting patterns.

STACKED-CHIP PACKAGES IN PACKAGE-ON-PACKAGE APPARATUS, METHODS OF ASSEMBLING SAME, AND SYSTEMS CONTAINING SAME

A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer. 125-. (canceled)26. An apparatus comprising:a package substrate including a die side and a land side;a chip stack disposed on the die side, wherein the chip stack includes a bottom chip disposed on the die side and a top chip disposed above the bottom chip, wherein the bottom chip is a flip-chip, wherein the top chip is a wire-bond chip, and wherein the chip stack has an offset height; andan interposer disposed on the die side, the interposer including an opening extending therethrough, the chip stack positioned on the package substrate within the opening, the interposer surrounding the chip stack, wherein the interposer accommodates the offset height of the chip stack.271. The apparatus of claim , wherein the interposer includes a bottom side ball-grid array and a top side ball grid array , the apparatus further including:a top package, wherein the top package includes at least one microelectronic device, wherein the top package is mated to the interposer top side ball-grid array; andwherein the interposer bottom side ball-grid array is mated to the die side of the package substrate.28. The apparatus of claim 26 , wherein the chip stack includes a wire-bond second chip disposed between the bottom chip and the top chip.29. The apparatus of claim 26 , wherein the chip stack includes a structure wherein:the bottom chip includes through-silicon vias extending therethrough;a through-silicon via (TSV) coupled second chip disposed on the flip chip, the TSV-coupled second chip being electrically coupled to the substrate using the through-silicon vias of the bottom chip; andthe top chip is disposed on the TSV-coupled second chip.30. The apparatus of claim 26 , wherein the chip stack includes a structure wherein:the bottom chip includes ...

INTEGRATED CIRCUIT ASSEMBLY AND METHOD OF MAKING

An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate. 1. An integrated circuit assembly comprising:an insulating layer having a first surface and a second surface;a first active layer contacting the first surface of the insulating layer;a metal bond pad formed on the second surface of the insulating layer;wherein the metal bond pad is electrically connected to the first active layer;a substrate having a first surface and a second surface, the first active layer being coupled to the second surface of the substrate; anda second active layer formed on the first surface of the substrate.2. The integrated circuit assembly of further comprising:a printed circuit board, the printed circuit board being electrically connected to the metal bond pad.3. The assembly of claim 1 , wherein the substrate is less than 100 microns thick.4. The assembly of claim 1 , wherein the substrate is less than 50 microns thick.5. The assembly of claim 1 , wherein the substrate is less than 30 microns thick.6. The assembly of claim 1 , wherein the first active layer or the second active layer includes passive devices.7. The assembly of claim 2 , wherein the printed circuit board is electrically connected with a solder bump to the first active layer.8. The assembly of wherein the printed circuit board is electrically connected to the second active layer through a wire bond.9. The assembly of claim 2 , wherein the printed circuit board is electrically connected with a solder bump to the second active layer.10. The assembly of claim 2 , ...

Chip on film, and method of manufacture thereof

A chip on film includes a plastic film approximately rectangular in flat view, a designated wiring pattern having approximately rectangular electrodes arrayed longitudinally formed on a mounting surface of the plastic film, and an LSI chip mounted on the mounting surface of the plastic film and connected to the designated wiring pattern. At least one cutout part is formed on each short side of the approximate rectangle of the plastic film.

SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE

A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate. 1. An apparatus , comprising:a first die;a second die including one or more through-silicon vias disposed therein (TSV die), the first die electrically coupled to the TSV die through the one or more through-silicon vias; anda coreless substrate, wherein both the first die and the TSV die are embedded in the coreless substrate, and wherein no surface of the first die protrudes from a surface of the coreless substrate.2. The apparatus of claim 1 , wherein the coreless substrate comprises an encapsulation layer claim 1 , and wherein both the first die and the TSV die are embedded in the encapsulation layer.3. The apparatus of claim 1 , wherein the first die is electrically coupled to the TSV die through the one or more through-silicon vias by one or more corresponding conductive bumps disposed on the first die and by one or more bond pads disposed on the TSV die.4. The apparatus of claim 1 , further comprising:a layer of epoxy flux material disposed between the first die and the TSV die.5. The apparatus of claim 1 , wherein the coreless substrate is free from routing layers between the first die and the TSV die.6. The apparatus of claim 1 , further comprising:a die-bonding film disposed on the first die.7. The apparatus of claim 1 , wherein the first die is fully embedded by the coreless substrate claim 1 , and wherein the TSV die is fully embedded and surrounded in the coreless substrate.8. An apparatus claim 1 , comprising:a memory die comprising a device side and a backside;a logic die including one or more through-silicon vias ...

MULTI-CHIP PACKAGE HAVING A STACKED PLURALITY OF DIFFERENT SIZED SEMICONDUCTOR CHIPS, AND METHOD OF MANUFACTURING THE SAME

Provided is a multi-chip package in which a plurality of semiconductor chips having different sizes are stacked. A multi-chip package may include a substrate, and a plurality of semiconductor chips stacked on the substrate, each of the plurality of semiconductor chips having a different size. Each of the plurality of semiconductor chips including a pad group and a reference region associated with the pad group, each pad group having a plurality of pads, and the plurality of pads in each pad group located at same coordinates with respect to the associated reference region, and each of the plurality of semiconductor chips having their reference regions vertically aligned. 1. A semiconductor device comprising:a first chip; andat least one chip stacked on the first chip, the at least one chip having a different size from the first chip,wherein each of the first chip and the at least one chip has a plurality of pads at center portion, and the first chip and the at least one chip are electrically connected to each other using the pads vertically aligned.2. The semiconductor device of claim 1 , wherein the plurality of pads are formed in a through via hole.3. The semiconductor device of claim 1 , wherein the at least one chip comprises a plurality of chips claim 1 , and the plurality of chips have a different size from each other.4. The semiconductor device of claim 1 , wherein at least a portion of the plurality of pads is arranged at a same distance from each other.5. The semiconductor device of claim 1 , wherein the plurality of pads are arranged in the same arrangement order in each of the first chip and the at least one chip.6. The semiconductor device of claim 1 , wherein the first chip and the at least one chip are electrically connected to each other by bumps disposed on the plurality of pads.7. The semiconductor device of claim 1 , further comprising:a substrate on which the first chip and the at least one chip are stacked.8. The semiconductor device of claim 7 , ...

Integrated circuit devices including electrode support structures and methods of fabricating the same

A semiconductor device includes a plurality of electrode structures perpendicularly extending on a substrate, and at least one support unit extending between the plurality of electrode structures. The support unit includes at least one support layer including a noncrystalline metal oxide contacting a part of the plurality of electrode structures. Related devices and fabrication methods are also discussed.

SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIPS

Disclosed herein is a device that including a first chip having first to fourth terminals and a second chip having fifth to seventh terminals. The first chip further includes a penetration electrode connected between the first and fourth electrodes and a first internal node coupled to of which an electrical potential being changed in response to an electrical potential of the first terminal. The second chip further includes a second internal node coupled to of which an electrical potential being changed in response to an electrical potential of the fifth terminal. The first internal node is electrically coupled to both the second terminal and the sixth terminal. The second internal node is electrically coupled to both the third terminal and the seventh terminal. 1. A semiconductor device comprising:a first chip including first and second surfaces opposed to each other, first, second and third terminals on the first surface, and a fourth terminal on the second surface, the first and fourth terminals being electrically coupled to each other through a penetration electrode penetrating a semiconductor substrate of the first chip, and a first internal node of which an electrical potential being changed in response to an electrical potential of the first terminal; anda second chip stacked with the first chip, the second chip including a third surface facing to the second surface of the first chip, a fourth surface opposed to the third surface, a fifth terminal on the third surface electrically coupled to the fourth terminal of the first chip, sixth and seventh terminals on the third surface, and a second internal node of which an electrical potential being changed in response to an electrical potential of the fifth terminal;the first internal node of the first chip being electrically coupled to both the second terminal of the first chip and the sixth terminal of the second chip, the second internal node of the second chip being electrically coupled to both the third ...

Semiconductor device, semiconductor package, and method for manufacturing semiconductor device

A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first surface, a second surface, and a through hole that extends through the semiconductor substrate from the first surface to the second surface. An insulating layer covers the first surface and includes an opening at a location facing the through hole. An insulating film covers an inner wall of the through hole and an inner wall of the opening. A through electrode is formed in the through hole and the opening that are covered by the insulating film. A first connecting terminal is formed integrally with the through electrode to cover one end of the through electrode exposed from the insulating layer. The first connecting terminal has a larger size than the through electrode as viewed from above.

SEMICONDUCTOR PACKAGE

The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least on opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors. Whereby, the solder mask contacts the first pads directly, and thus results in higher bonding strength, so as to avoid the bridge between the first conductors caused by the first conductors permeating into the interface between the solder mask and the first pads. 1. A semiconductor package , comprising:a substrate comprising a top surface, a pad, an anti-oxidation layer, and a solder mask, wherein the pad is disposed adjacent to the top surface of the substrate, the solder mask overlies and directly contacts a part of the pad and defines a solder mask opening so as to expose a remaining part of the pad, and the anti-oxidation layer is disposed over the remaining part of the pad exposed by the solder mask opening;a chip mounted on the substrate;a plurality of conductive elements electrically connecting the chip and the substrate;a conductor disposed over the anti-oxidation layer; anda molding compound disposed over the top surface of the substrate, wherein the molding compound comprises a first top surface and a second top surface, a first height of the first top surface of the molding compound is ...

WAFER-TO-WAFER STACK WITH SUPPORTING POST

A wafer stack includes: a first wafer having a first substrate and a first device layer having therein at least a chip; a second wafer having a second substrate disposed above the first wafer; and at least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip. 1. A wafer stack , comprising:a first wafer having a first substrate and a first device layer having therein at least a chip;a second wafer having a second substrate disposed above the first wafer; andat least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip.2. The wafer stack according to claim 1 , wherein the second wafer has a second device layer and the metal post has a part in the first device layer and being vertically aligned with that formed in the second device layer.3. The wafer stack according to claim 2 , wherein the first and the second device layers are adjacent to each other claim 2 , so as to configure the first and the second wafers as a face to face wafer stack.4. The wafer stack according to claim 1 , wherein the first device layer is adjacent to the second substrate claim 1 , so as to configure the first and the second wafers as a back to face wafer stack.5. The wafer stack according to claim 1 , wherein the first substrate is adjacent to the second substrate claim 1 , so as to configure the first and the second wafers as a back to back wafer stack.6. The wafer stack according to claim 1 , wherein a second substrate includes a rigid layer claim 1 , and the rigid layer is made up by one selected from the group consisting of silicon substrate claim 1 , silicon dioxide on silicon substrate and silicon nitride/silicon dioxide on silicon substrate.7. The wafer stack according to claim 6 , wherein the first metal post stands on a solid foundation layer of the first substrate.8. ...

Semiconductor Interposer Having a Cavity for Intra-Interposer Die

A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.

SEMICONDUCTOR MODULE

According to one embodiment, a semiconductor module includes a semiconductor chip that is mounted on a printed substrate, a terminal electrode that is formed on the printed substrate so as to be electrically connected to the semiconductor chip, a metal coating layer that is formed on the terminal electrode, a plating lead wire that is electrically connected to the terminal electrode, and a gap that is formed in the plating lead wire. 1. A semiconductor module comprising:a semiconductor chip that is mounted on a printed substrate;a terminal electrode that is formed on the printed substrate so as to be electrically connected to the semiconductor chip;a metal coating layer that is formed on the terminal electrode;a lead wire that is electrically connected to the terminal electrode; anda gap that divides the lead wires in a wiring direction.2. The semiconductor module according to claim 1 , whereinthe lead wire is disposed so that end portions of the divided parts thereof face each other in the gap.3. The semiconductor module according to claim 1 , whereinthe metal coating layer is a plated layer, and the lead wire is a plating lead wire.4. The semiconductor module according to claim 1 , further comprisinga constant-voltage pattern that is formed on the printed substrate so as to face the end portion of the lead wire via the gap.5. The semiconductor module according to claim 4 , whereinthe constant-voltage pattern is a voltage source pattern or a ground pattern.6. The semiconductor module according to claim 4 , whereinthe constant-voltage pattern is disposed continuously around the printed substrate at an outer side of the lead wire.7. The semiconductor module according to claim 6 , whereinthe constant-voltage pattern is disposed so as to surround the lead wire.8. The semiconductor module according to claim 1 , further comprisinga solder ball that is formed on the terminal electrode.9. The semiconductor module according to claim 1 , further comprising:a solder resist ...

BALL GRID ARRAY PACKAGE SUBSTRATE WITH THROUGH HOLES AND METHOD OF FORMING SAME

In accordance with an embodiment, there is provided a substrate of a ball grid array package that includes a first layer including reinforcement fibers. The reinforcement fibers reinforce the first layer such that the first layer has a higher tensile strength relative to a layer in the ball grid array package that is free of reinforcement fibers. In an embodiment, the substrate comprises a second layer disposed adjacent to the first layer with the second layer being free of reinforcement fibers. In an embodiment, the substrate also includes a through hole penetrating each of the first layer and the second layer. The through hole penetrates each of the first layer and the second layer based on each of the first layer and the second layer having been drilled in accordance with a mechanical drilling process. 1. A substrate of a ball grid array package , the substrate comprising:a first layer including reinforcement fibers, wherein the reinforcement fibers reinforce the first layer such that the first layer has a higher tensile strength relative to a layer in the ball grid array package that is free of reinforcement fibers;a second layer disposed adjacent to the first layer, wherein the second layer is free of reinforcement fibers; anda through hole penetrating each of the first layer and the second layer, wherein the through hole penetrates each of the first layer and the second layer based on each of the first layer and the second layer having been drilled in accordance with a mechanical drilling process.2. The substrate of claim 1 , wherein:each of the first layer and the second layer respectively includes a circuit pattern; and; andthe through hole permits the circuit pattern of the first layer to be electrically coupled to the circuit pattern of the second layer.3. The substrate of claim 1 , wherein a diameter of the through hole is at least 80 microns.4. The substrate of claim 1 , wherein a diameter of the through hole is within a range of 100 microns to 150 ...

SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES AND METHODS FOR FABRICATING THE SAME

Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode. 1. A semiconductor device , comprising:a substrate including a via hole therethrough;a through electrode filling the via hole;a via-insulating layer disposed between the through electrode and the substrate; anda buffer layer disposed between the through electrode and the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer.2. The device of claim 1 , wherein the buffer layer includes: tetraethylorthosilicate (TEOS) oxide; low-k dielectric containing a SiO-based material claim 1 , in which C claim 1 , CH claim 1 , CH claim 1 , CHor any combination thereof is added as a ligand; a porous layer of the low-k dielectrics; or any combination thereof.3. The device of claim 2 , wherein the low-k dielectric comprises octamethylcyclotetrasiloxane (OMCTS) claim 2 , dimethyldimethoxysilane (DMDMOS) claim 2 , tetramethylcyclotetrasiloxane (TMCTS) claim 2 , diethoxymethylsilane (DEMS) claim 2 , AURORA™ (ethyl 2-chloro-3-[2-chloro-4-fluoro-5-[4-(difluoromethyl)-4 claim 2 ,5-dihydro-3-methyl-5-oxo-1H-1 claim 2 ,2 claim 2 ,4triazol-1-yl]phenyl]propanoat) claim 2 , or any combination thereof claim 2 , and{'sub': '2', 'the porous layer comprises an insulating layer including the low-k ...

Semiconductor Device Package with Slanting Structures

A semiconductor device package structure includes a substrate with a via contact pad on top surface of the substrate, a terminal pad on bottom surface of the substrate and a conductive through hole through the substrate, wherein the conductive through hole electrically couples the via contact pad and the terminal pad on the substrate; a die having bonding pads thereon, wherein the die is formed on the top surface of the substrate; a slanting structure formed adjacent to at least one side of the die for carrying conductive traces; and a conductive trace formed on upper surface of the slanting structure to offer path between the bonding pads and the via contact pad. 1. A semiconductor device package structure , comprising:a substrate with a via contact pad on a top surface of said substrate, a terminal pad on a bottom surface of said substrate and a conductive through hole through said substrate, wherein said conductive through hole is electrically coupled to said via contact pad and said terminal pad on said substrate;a die having bonding pads thereon, wherein said die is formed on said top surface of said substrate;a slanting structure formed adjacent to at least one side of said die for carrying conductive traces; anda conductive trace formed on a upper surface of said slanting structure to offer electrical path between said bonding pads and said via contact pad.2. The structure of claim 1 , further comprising a refilling material within said conductive through hole.3. The structure of claim 2 , wherein said refilling material comprises aluminum claim 2 , titanium claim 2 , copper claim 2 , nickel claim 2 , silver or the combination thereof.4. The structure of claim 2 , wherein said refilling material comprises Cu/Ni/Au.5. The structure of claim 1 , further comprising an adhesive layer formed between backside surface of said die and said top surface of said substrate.6. The structure of claim 5 , further comprising:a cavity formed from said bottom surface of said ...

SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT

Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via. 1. A semiconductor device comprising:a silicon substrate having a first side and a second side;active circuitry fabricated on the first side of the silicon substrate and including multiple metal routing structures;a conductive interconnect extending vertically through the silicon substrate to the second side such that at least one of the multiple routing structures is located in a horizontal plane located above a top region of the conductive interconnect; andan external electrical interconnect coupled to the conductive interconnect at the second side of the silicon substrate.2. The semiconductor device of wherein the external electrical interconnect comprises a conductive redistribution structure located at the second side of the silicon substrate claim 1 , wherein the conductive redistribution structure is electrically coupled to the conductive interconnect.3. The semiconductor device of wherein the conductive redistribution structure comprises a conductive ball bond pad.4. The semiconductor device of wherein the conductive interconnect has a length to width ratio of about 5:1 to 10:1.5. The semiconductor device of wherein one of the multiple metal routing structures has an electrical connection with the conductive interconnect.6. A semiconductor device comprising:a silicon substrate having a first side and a second side;a conductive interconnect extending from a ...

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS

A semiconductor device is provided in the present invention. The semiconductor device includes a silicon substrate, configured to bear a chip; a power management module arranged inside the silicon substrate, configured to convert a power supply voltage to an input voltage required by the chip; and an interconnecting system, configured to receive the power supply voltage, transmit the power supply voltage to the power management module, and transmit the input voltage to the chip. With the semiconductor device according to the embodiments of the present invention, the power supply voltage can be directly sent from the silicon substrate to the chip after being generated, thereby shortening the power supply link and reducing the power supply/ground noise. 1. A semiconductor device , comprising:a silicon substrate, configured to bear a chip;a power management module arranged inside the silicon substrate, configured to convert a power supply voltage to an input voltage required by the chip; andan interconnecting system, configured to receive the power supply voltage, transmit the power supply voltage to the power management module, and transmit the input voltage to the chip.2. The semiconductor device according to claim 1 , wherein the interconnecting system comprises a through silicon via claim 1 , the through silicon via is arranged in the silicon substrate claim 1 , and an electric path is arranged in the through silicon via to transmit the power supply voltage and the input voltage.3. The semiconductor device according to claim 2 , wherein the interconnecting system further comprises a solder pad arranged on the upper surface of the silicon substrate claim 2 , the solder pad is configured to electrically connect to the chip claim 2 , and the solder pad is electrically connected to the electric path in the through silicon via.4. The semiconductor device according to claim 2 , wherein the interconnecting system further comprises a solder pad arranged on the lower ...

Flexible circuit board

A flexible circuit board includes a base film formed by a metallic material, a first protective film formed on a first surface of the base film, and a circuit pattern adhered to the first protective film through an adhesive film. Projections and recesses for heat release are formed on a second surface that is a surface on the opposite side of the first surface of the base film.

SEMICONDUCTOR APPARATUS MANUFACTURING METHOD AND SEMICONDUCTOR APPARATUS

There is provided a method of manufacturing the semiconductor apparatus, including: forming through-hole which penetrates a semiconductor substrate at a point that corresponds to a location of an electrode pad; forming an insulating film on a rear surface of the semiconductor substrate, including the interior of the through-hole; forming an adhesion securing layer from a metal or an inorganic insulator on a surface of the insulating film at least in an opening portion of the through-hole; forming a resist layer to serve as a mask in bottom etching on the adhesion securing layer; performing bottom etching to expose the electrode pad; removing the resist layer to obtain the insulating film free of surface irregularities that would otherwise have been created by bottom etching; forming a barrier layer, a seed layer, and a conductive layer by a low-temperature process; and performing patterning. 1. A semiconductor apparatus , comprising:a semiconductor substrate;an electrode pad formed on a front surface of said semiconductor substrate;a through-hole which has an opening portion on a rear surface of said semiconductor substrate that corresponds to a location of said electrode pad and which penetrates said semiconductor substrate;an insulating film formed on an inner wall of said through-hole;a layer formed on said insulating film; anda conductive layer formed on said layer, or on said layer and said insulating film, and on said electrode pad,wherein said electrode pad is in contact with said conductive layer.2. The semiconductor apparatus according to claim 1 , wherein said layer formed on said insulating film is made from one of a metal and an inorganic insulator.3. The semiconductor apparatus according to claim 1 , wherein said layer formed on the insulating film is 0.01 μm to 0.1 μm in thickness.4. The semiconductor apparatus according to claim 1 , wherein said layer formed on said insulating film comprises titanium claim 1 , tungsten or chromium.5. The semiconductor ...

SEMICONDUCTOR DEVICE HAVING SIGNAL LINE AND POWER SUPPLY LINE INTERSECTING WITH EACH OTHER

Disclosed herein is a semiconductor device includes: a plurality of first power supply wirings provided on a first wiring layer and extending in a first direction; a plurality of second power supply wirings provided on a second wiring layer different from the first wiring layer and extending in a second direction intersecting the first direction; a signal wiring provided on the second wiring layer and extending in the second direction; and a plurality of through-hole conductors each electrically connecting an associated one of the first power supply wirings to an associated one of the second power supply wirings. At least a part of the first power supply wirings have a notch in a portion intersecting the signal wiring. 1. A semiconductor device comprising:a plurality of first power supply wirings provided on a first wiring layer and extending in a first direction;a plurality of second power supply wirings provided on a second wiring layer different from the first wiring layer and extending in a second direction intersecting the first direction;a signal wiring provided on the second wiring layer and extending in the second direction; anda plurality of through-hole conductors each electrically connecting an associated one of the first power supply wirings to an associated one of the second power supply wirings,wherein at least a part of the first power supply wirings have a notch in a portion intersecting the signal wiring.2. The semiconductor device as claimed in claim 1 , whereineach of the first power supply wirings whose wiring width in the second direction is smaller than a first width among the first power supply wirings does not have the notch in the portion intersecting the signal wiring, andeach of the first power supply wirings whose wiring width in the second direction is equal to or larger than the first width among the first power supply wirings has the notch in the portion intersecting the signal wiring.3. The semiconductor device as claimed in claim 2 , ...

STRUCTURES AND METHODS TO REDUCE MAXIMUM CURRENT DENSITY IN A SOLDER BALL

Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance. 1. A semiconductor structure , comprising:a contact pad in a last wiring level of a chip; anda plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias,wherein each one of the plurality of wires has substantially the same electrical resistance.2. The semiconductor structure of claim 1 , wherein the plurality of wires are formed from the contact pad.3. The semiconductor structure of claim 1 , wherein:a first one of the plurality of wires has a first length and a first width,a second one of the plurality of wires has a second length and a second width,the first width is different from the second width, andthe first length is different from the second length.4. The semiconductor structure of claim 3 , further comprising:a capping layer on the last wiring level of the chip;a passivation layer on the capping layer;at least one final via in the passivation layer;a ball limiting metallurgy (BLM) layer on the at least one final via and the passivation layer; anda solder bump on the BLM layer.5. The semiconductor structure of claim 4 , wherein:the plurality of vias are disposed in the capping layer;the plurality of vias and the capping layer have substantially coplanar upper surfaces; andthe at least one final vias and the passivation layer have substantially coplanar upper surfaces.6. The semiconductor structure of claim 1 , wherein at least two of the plurality of wires comprise different widths and different lengths.7. The semiconductor structure of claim 1 , wherein at least one of the plurality of wires widens at a location adjacent ...

PACKAGED MICROELECTRONIC DEVICES RECESSED IN SUPPORT MEMBER CAVITIES, AND ASSOCIATED METHODS

Packaged microelectronic devices recessed in support member cavities, and associated methods, are disclosed. Method in accordance with one embodiment includes positioning a microelectronic device in a cavity of a support member, with the cavity having a closed end with a conductive layer, and an opening through which the cavity is assessable. The microelectronic device can have bond sites, a first surface, and a second surface facing opposite from the first surface. The microelectronic device can be positioned in the cavity so that the second surface faces toward and is carried by the conductive layer. The method can further include electrically coupling the bond sites of the microelectronic device to the conductive layer. In particular embodiments, the microelectronic device can be encapsulated in the cavity without the need for a releasable tape layer to temporarily support the microelectronic device. 1. A microelectronic package , comprising:a first support member comprising a first conductive material, a second conductive material, and a first insulating material between the first conductive material and the second conductive material;an intermediate member having a first side facing the second conductive material of the first support member and a second side facing away from the first side;a second support member comprising a third conductive material, a fourth conductive material, and a second insulating material between the third conductive material and the fourth conductive material, the third conductive material having a first side facing the intermediate member and the second side facing away from the first side, the forth conductive material having a first side facing the second insulating material and a second side facing away from the second insulating material;wherein the package has a cavity extending generally vertically from the first side of the fourth conductive material through the first conductive material of the first support member.2. The ...

SEMICONDUCTOR DEVICE

A semiconductor device has a semiconductor substrate which has a plurality of pad electrodes provided on a top surface thereof and has an approximately rectangular shape; a rewiring layer which is provided with a plurality of contact wiring lines connected to the plurality of pad electrodes, is disposed on the semiconductor substrate through an insulating film, and has an approximately rectangular shape; and a plurality of ball electrodes which are provided on the rewiring layer. 1. A semiconductor device , comprising:a semiconductor substrate which has a plurality of pad electrodes provided on a top surface thereof;a rewiring layer which is provided with a plurality of rewiring lines connected to the plurality of pad electrodes, is disposed on the semiconductor substrate through an insulating film;a plurality of ball electrodes which are provided on the rewiring layer, wherein a plurality of first ball electrodes among the plurality of ball electrodes are arranged on an outer circumference of the rewiring layer to be along a first side; andan outer circumference wiring line which is disposed on the outercircumference of the rewiring layer along the first side and outside from the first ball electrodes towards the first side.2. The semiconductor device of claim 1 , further comprising;a plurality of first pad electrodes among the plurality of pad electrodes which are arranged on an outer circumference of the rewiring layer to be along the first side.3. The semiconductor device of claim 2 , further comprising;a second ball electrode which is provided in a central region on the semiconductor substrate,wherein a pad electrode applied with a first voltage, among the plurality of first pad electrodes, is connected to the outer circumference wiring line, the circumference wiring line being connected to the second ball electrode through a first rewiring line of the rewiring layer.4. The semiconductor device of claim 1 ,the outer circumference wiring line extended to sides ...

SUBSTRATE DEVICE

A substrate device includes: a plurality of substrates stacked one on another including a substrate on which electronic components are mounted; and a coupling member connecting mechanically and electrically the two opposed substrates, and the coupling member includes: a plurality of core-less solder balls connecting mechanically and electrically the two opposed substrates; and a plurality of spacers configured to keep a clearance between the two opposed substrates wider than a mounting height of the electronic component between the substrates. 1. A substrate device , comprising:a plurality of substrates stacked one on another including a substrate on which electronic components are mounted; anda coupling member connecting mechanically and electrically the two opposed substrates, whereinthe coupling member includes:a plurality of core-less solder balls connecting mechanically and electrically the two opposed substrates; anda plurality of spacers configured to keep a clearance between the two opposed substrates wider than a mounting height of the electronic component between the substrates.2. The substrate device according to claim 1 , wherein the spacers include core solder balls.3. The substrate device according to claim 2 , wherein an amount of solder in the core-less solder balls is larger than an amount of solder in the core solder balls.4. The substrate device according to claim 2 , wherein a diameter of the core solder balls is larger than the mounting height of the electronic components.5. The substrate device according to claim 2 , wherein the core solder balls include at least one of resin core solder balls and copper core solder balls.6. The substrate device according to claim 1 , wherein the spacers include stud having end surfaces fixed by an adhesive member to the substrates.7. The substrate device according to claim 1 , wherein the two opposed substrates include a module substrate on which electronic components are mounted and a mother substrate.8. The ...

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, CIRCUIT BOARD AND ELECTRONIC APPARATUS

A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings. 1. A semiconductor device comprising:a first wiring being connected to an electrode;a first resin layer on the first wiring having a through hole;a second wiring on the first resin layer being connected to the first wiring via the through hole;a terminal being provided on the second wiring;a second resin layer on the first resin layer and the second wiring having a lower elasticity than the first resin layer; anda third resin layer on the second resin layer having a lower elasticity than the second resin layer.2. The semiconductor device according to claim 1 , wherein the terminal is provided nearer a circumferential region of the semiconductor device than the through hole.3. The semiconductor device according to claim 1 , wherein the terminal is protruded from the second resin layer and the second resin layer.4. The semiconductor device according to claim 1 , wherein the terminal comprises a solder ball.5. A circuit substrate including the semiconductor device according to .6. An electronic apparatus including the semiconductor device according to . This is a continuation application of U.S. Ser. No. 13/156,686 filed Jun. 9, 2011, which is a continuation application of U.S. Ser. No. 12/569,478 filed Sep. 29, 2009, now U.S. Pat. No. 7,982,310 issued Jul. 19, 2011, which is a divisional application of U.S. Ser. No. 11/016,504 filed Dec. 17, 2004, now U.S. Pat. No. 7,615,864 issued Nov. 10, 2009, which claims priority to Japanese Patent Application No. 2003-419406 ...

Many-up wiring substrate, wiring board, and electronic device

A many-up wiring substrate includes an insulating base substrate in which a plurality of wiring board regions are arranged in at least one of a vertical direction and a horizontal direction; a hole disposed in one main surface of the insulating base substrate, and straddling adjacent wiring board regions of the plurality of wiring board regions or straddling the wiring board regions and a dummy region; a conductor disposed on an inner surface of the hole; and a through hole disposed so as to extend from the inner surface of the hole of the wiring board regions to the other main surface of the insulating base substrate.

Semiconductor device

A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.

Thermally Enhanced Structure for Multi-Chip Device

A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved. 1. A method comprising:attaching a heat sink block to a first side of a first semiconductor die;bonding a second side of the first semiconductor die to an interposer; andbonding the interposer to a substrate, wherein the first semiconductor die is located between the interposer and the substrate.2. The method of claim 1 , wherein:the heat sink block is attached to a backside surface of the first semiconductor die; andthe heat sink block has a plurality of openings.3. The method of claim 1 , further comprising:placing one additional heat sink between the heat sink block and the top surface of the substrate.4. The method of claim 1 , further comprising:coupling the first semiconductor die to the interposer through a plurality of micro bumps placed between the first semiconductor die and the interposer.5. The method of claim 1 , further comprising:coupling the interposer to the substrate through a plurality of solder balls placed between the substrate and the interposer.6. The method of claim 1 , further comprising:forming a solder joint structure between the heat sink block and the top surface of the substrate.7. The method of claim 1 , wherein:the heat sink block has a first side attached to the first side of the first semiconductor die; andthe heat sink block has a second side in direct contact with a top ...

Apparatus For Dicing Interposer Assembly

Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon. An apparatus includes a wafer carrier mounted in a frame and having a size corresponding to a silicon interposer, a fixture mounted to the wafer carrier and comprising a layer of material to provide mechanical support to the die side of the silicon interposer, the fixture being patterned to fill spaces between integrated circuit dies mounted on an interposer; and an adhesive tape disposed on a surface of the fixture for adhering to the surface of a silicon interposer. Additional alternative apparatuses are disclosed. 1. An apparatus , comprising:a plurality of integrated circuit dies mounted on a die side surface of an interposer, the integrated circuit dies having gaps between them;external connectors mounted on an opposite side of the interposer; andspacers disposed in the gaps between the integrated circuit dies on the die side of the interposer.2. The apparatus of claim 1 , further comprising a tape layer between the spacers and the interposer.3. The apparatus of claim 1 , wherein the interposer is one selected from the group consisting of a silicon substrate and a glass substrate.4. The apparatus of claim 3 , wherein the interposer further comprises through silicon vias extending from the die side surface to an opposite surface of the interposer.5. The apparatus of claim 1 , wherein the interposer further comprises a plurality of board level connections formed on a surface on a surface of the interposer opposite the die side surface.6. The apparatus of claim 5 , wherein the plurality of board level connections further comprises a plurality of solder balls.7. The apparatus of claim 6 , wherein the plurality of board level connections further comprises copper posts.8. The apparatus of claim 7 , wherein the copper posts further comprise a plating on an exterior surface.9. The ...

Semiconductor device and production method of the same

A semiconductor device capable of performing sufficient power supply while suppressing an increase in a manufacturing cost. The semiconductor device has a semiconductor substrate, a multilayer interconnection layer provided over the semiconductor substrate, an Al wiring layer that is provided over the multilayer interconnection layer and has pad parts, and a redistribution layer that is provided over the Al wiring layer and is coupled with the Al wiring layer, in which the redistribution layer is comprised of a metal material whose electric resistivity is lower than that of Al and is not formed over the pad parts.

Pillar Structure having a Non-Planar Surface for Semiconductor Devices

A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer. 1. A semiconductor structure comprising:a substrate comprising a first conductive layer;a pillar electrically coupled to the first conductive layer, the pillar having a non-planar upper surface; andsolder material overlying the pillar and in electrical contact with the first conductive layer, wherein a distance between an uppermost point of the non-planar upper surface and a lowermost point of the non-planar upper surface is about 6% or greater of a width of the pillar.2. The semiconductor structure of claim 1 , wherein the non-planar upper surface is a convex surface.3. The semiconductor structure of claim 1 , wherein the non-planar upper surface is a concave surface.4. The semiconductor structure of claim 1 , wherein the non-planar upper surface has a wave shape.5. The semiconductor structure of claim 1 , further comprising a capping layer interposed between the pillar and the solder material.6. The semiconductor structure of claim 5 , wherein the capping layer is formed of Ni claim 5 , Pt claim 5 , Au claim 5 , or Ag.7. The semiconductor structure of wherein the capping layer is formed from a first material selected to result in an IMC stronger than a second IMC resulting from a second material forming the pillar.8. The semiconductor structure of claim 1 , further comprising an inter-metallic compound (IMC) layer interposed between the pillar and the solder material claim 1 , a thickness of the IMC layer being less than about the distance between the uppermost point of the non-planar upper surface ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device may include a lower semiconductor package including at least one lower semiconductor chip, at least one upper semiconductor package mounted on the lower semiconductor package to include at least one upper semiconductor chip, a molding layer provided between the lower and upper semiconductor packages, and connection solder balls provided in the molding layer to electrically connect the lower and upper semiconductor packages to each other. Each of the connection solder balls may include a portion protruding upward from the molding layer, and there may be no gap between the connection solder balls and the molding layer. 1. A semiconductor device , comprising:a lower semiconductor package including at least one lower semiconductor chip;at least one upper semiconductor package mounted on the lower semiconductor package to include at least one upper semiconductor chip;a molding layer provided between the lower and upper semiconductor packages; andconnection solder balls provided in the molding layer to electrically connect the lower and upper semiconductor packages to each other,wherein each of the connection solder balls comprises a portion protruding upward from the molding layer, and there is no gap between the connection solder balls and the molding layer.2. The device of claim 1 , wherein each of the connection solder balls has a side surface that is positioned between top and bottom surfaces of the lower molding layer and is directly covered with the lower molding layer.3. The device of claim 1 , wherein each of the connection solder balls comprises an upper region and a lower region claim 1 , and the maximum width of the lower region is greater than that of the upper region.4. The device of claim 3 , wherein the upper regions of the connection solder balls have substantially the same width.5. The device of claim 1 , wherein the lower semiconductor package comprises a lower package substrate and the at least one lower semiconductor chip ...

CHIP-ON-FILM PACKAGE AND DEVICE ASSEMBLY INCLUDING THE SAME

Chip-on-film packages and device assemblies including the same may be provided. The device assembly includes a film package including a semiconductor chip, a panel substrate connected to one end of the film package, a display panel disposed on the panel substrate, and a controlling part connected to another end of the film package. The film package includes a film substrate, a first wire disposed on a top surface of the film substrate, and a second wire disposed on a bottom surface of the film substrate. 1. A device assembly comprising: a semiconductor chip,', 'a film substrate,', 'a first wire on a top surface of the film substrate, and', 'a second wire on a bottom surface of the film substrate;, 'a film package including,'}a panel substrate connected to one end of the film package; anda display panel on the panel substrate.2. The device assembly of claim 1 , wherein the panel substrate is electrically connected to the first wire.3. The device assembly of claim 1 , wherein the film package includes at least one through-wire electrically connecting the first wire to the second wire.4. The device assembly of claim 1 , further comprising:a controlling part connected to another end of the film package, wherein the semiconductor chip and the controlling part are disposed on the first wire and are electrically connected to each other through the first wire.5. The device assembly of claim 3 , wherein the semiconductor chip and the controlling part are on the second wire and are electrically connected to each other through the second wire.6. The device assembly of claim 3 , wherein the semiconductor chip is on the first wire and is electrically connected to the first wire; andwherein the controlling part is on the second wire and is electrically connected to the second wire.7. The device assembly of claim 1 , further comprising:a controlling part connected to another end of the film package, the controlling part including at least one of a circuit substrate and an electric ...

WIRING BOARDS AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME

A wiring board and a semiconductor package are provided. The wiring board includes: a metal core including a first surface and a second surface opposite the first surface; a first buildup portion and a second buildup portion including an insulating layer and a pad pattern sequentially stacked, the first and second buildup portions being provided on the first surface and the second surface, respectively; a mask pattern including an opening exposing the pad pattern, the mask pattern being provided on the second buildup portion; and a bather pattern in an area in which a region of the metal core which overlaps with the pad pattern of the second buildup portion is removed, wherein a minimum width of an outer circumference of the barrier pattern is greater than a maximum width of the pad pattern of the second buildup portion. 1. A wiring board comprising:a metal core comprising a first surface and a second surface opposite the first surface;a first buildup portion comprising a first insulating layer and a first pad pattern sequentially stacked, the first buildup portion being on the first surface;a second buildup portion comprising a second insulating layer and a second pad pattern sequentially stacked, the second buildup portion being on the second surface;a mask pattern comprising an opening exposing the second pad pattern, the mask pattern being on the second buildup portion; anda barrier pattern in an area in which a region of the metal core which overlaps with the second pad pattern is removed,wherein a minimum width of an outer circumference of the barrier pattern is greater than a maximum width of the second pad pattern.2. The wiring board of claim 1 , wherein a shape of the outer circumference of the barrier pattern is a circle or a polygon.3. The wiring board of claim 1 , wherein the barrier pattern comprises copper.4. The wiring board of claim 1 , wherein a maximum width of the outer circumference of the barrier pattern is greater than a maximum width of the ...

PROTRUDING TERMINALS WITH INTERNAL ROUTING INTERCONNECTIONS SEMICONDUCTOR DEVICE

A semiconductor package includes terminals extending from a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. Each terminal includes a first plated section, a second plated section, and a portion of a sheet carrier from which the semiconductor package is built upon, wherein the portion is coupled between the first and second plated sections. Each interconnection routing is electrically coupled with a terminal and can extend planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes at least one intermediary layer, each including a via layer and an associated routing layer. The semiconductor package includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals. 1. A semiconductor package comprising:a. interconnection routings forming an interconnection routing layer;b. a die electrically coupled with the interconnection routing layer;c. terminals in communication with the interconnection routing layer and protruding from a bottom surface of the semiconductor package, each terminal including a first plated region, a second plated region, and a metallic strip separating the first plated region and the second plated region; and i. a top molding compound encapsulating the interconnection routings and the die; and', 'ii. a bottom molding compound surrounding the first plated region of each terminal., 'd. a package compound including2. The semiconductor package of claim 1 , wherein the metallic strip is a section of a sheet carrier from which the semiconductor package is built upon.3. The semiconductor package of claim 2 , wherein the sheet carrier is a Cu leadframe strip.4. The semiconductor package of claim 1 , wherein a width of the second plated region of each terminal is nonuniform.5. The semiconductor package ...

Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die

A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die. 1. A method of making a semiconductor device , comprising:providing a carrier;forming an interface layer over the carrier;disposing a first substrate over the carrier;disposing a second substrate over the carrier;disposing a first semiconductor die over the first and second substrates electrically connected to the first and second substrates;depositing an encapsulant over the first semiconductor die and over the first and second substrates; andremoving the carrier and interface layer.2. The method of claim 1 , further including forming a plurality of bumps over the first and second substrates.3. The method of claim 1 , wherein disposing the first and second substrates includes simultaneously disposing the first and second substrates over the carrier.4. The method of claim 1 , further including forming an electrical connection between the first and second substrates.5. The method of claim 1 , further including forming an interconnect structure over a surface of the first substrate opposite the first semiconductor die.6. The method of claim 1 , further including ...

Protected Solder Ball Joints in Wafer Level Chip-Scale Packaging

Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress. 1. A semiconductor device comprising:one or more re-distribution layers on a first surface of a semiconductor wafer, wherein the one or more re-distribution layers do not extend beyond the first surface of the semiconductor wafer;one or more electrode posts on respective ones of the one or more re-distribution layers, wherein each of said one or more electrode posts comprises an array of two or more columns, said one or more electrode posts electrically connected to a wiring layer of said semiconductor wafer;a buffer layer over the first surface, the buffer layer encapsulating said array and being in physical contact with a conductive portion of at least one of said one or more re-distribution layers, wherein a top surface of one or more electrode posts are below a top surface of the buffer layer;a conductive capping layer over the top surface of one or more electrode posts, wherein a top surface of the conductive capping layer is below the top surface of the buffer layer; anda solder ball on the conductive capping layer, wherein a solder joint between the solder ball and the conductive capping layer resides below the top surface of the buffer layer, and wherein the solder ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a first insulating layer; a wiring layer formed on a first surface of the first insulating layer and including a first electrode pad; a semiconductor chip; a second insulating layer including a semiconductor chip accommodating portion; a third insulating layer on the second insulating layer; and a passive element including an electrode and formed of an embedded portion and a protruding portion on a second surface of the first insulating layer, wherein an end surface of the embedded portion is coated by the insulating layer, the electrode of the passive element is electrically connected to the wiring layer through a via wiring formed in the insulating layers, the first electrode pad is electrically connected to another semiconductor device through a joining portion, and a protruding amount of the protruding portion is less than a gap between the second surface and the another semiconductor device. 1. A semiconductor device comprising:a first insulating layer being an outermost layer of the semiconductor device;a wiring layer that is formed on a first surface of the first insulating layer and includes a first electrode pad;a semiconductor chip having a circuit forming surface positioned on a surface of the semiconductor chip opposite to the first insulating layer;a second insulating layer that is formed on the first surface of the first insulating layer, coats the wiring layer, and includes a semiconductor chip accommodating portion for accommodating the semiconductor chip;a third insulating layer that is arranged on the second insulating layer and coats the circuit forming surface and side surfaces of the semiconductor chip; anda passive element that includes an electrode and is formed of an embedded portion embedded in at least the first insulating layer and a protruding portion protruding from a second surface opposite to the first surface of the first insulating layer,wherein an end surface of the embedded portion is coated by one ...

Three-Dimensional Integrated Circuit (3DIC)

An embodiment 3DIC device includes a semiconductor chip, a die, and a polymer. The semiconductor chip includes a semiconductor substrate, wherein the semiconductor substrate comprises a first edge, and a low-k dielectric layer over the semiconductor substrate. The die is disposed over and bonded to the semiconductor chip. The polymer is molded onto the semiconductor chip and the die. The polymer includes a portion level with the low-k dielectric layer, wherein the portion of the polymer comprises a second edge vertically aligned to the first edge of the semiconductor substrate and a third edge contacting the low-k dielectric layer, wherein the second and the third edges are opposite edges of the portion of the polymer. 1. A device comprising: a semiconductor substrate, wherein the semiconductor substrate comprises a first edge; and', 'a low-k dielectric layer over the semiconductor substrate;, 'a semiconductor chip comprisinga die over and bonded to the semiconductor chip; and a second edge vertically aligned to the first edge of the semiconductor substrate; and', 'a third edge contacting the low-k dielectric layer, wherein the second and the third edges are opposite edges of the portion of the polymer., 'a polymer molded onto the semiconductor chip and the die, wherein the polymer comprises a portion level with the low-k dielectric layer, and wherein the portion of the polymer comprises2. The device of claim 1 , wherein the portion of the polymer comprises an end in physical contact with the semiconductor substrate.3. The device of claim 1 , wherein an interface between the portion of the polymer and the semiconductor substrate is substantially level with a surface of the semiconductor substrate that is directly underlying the low-k dielectric layer.4. The device of claim 1 , wherein an interface between the portion of the polymer and the semiconductor substrate is lower than a surface of the semiconductor substrate that is directly underlying the low-k dielectric ...

WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME

A wiring board includes a first insulation layer, a first conducive layer having first conductive patterns formed on the first insulation layer, a wiring structure positioned on the first insulation layer and including a second insulation layer and a second conductive layer having second conductive patterns formed on the second insulation layer, multiple conductive patterns formed on the wiring structures such that the conductive patterns are connected to the second conductive patterns, respectively, multiple first electrodes formed on the first conductive patterns, respectively, and multiple second electrodes formed on the conductive patterns connected to the second conductive patterns of the wiring structure, respectively. The first electrodes and the second electrodes have top surfaces which form the same plane. 1. A wiring board , comprising:a first insulation layer;a first conducive layer comprising a plurality of first conductive patterns formed on the first insulation layer;a wiring structure positioned on the first insulation layer and comprising a second insulation layer and a second conductive layer comprising a plurality of second conductive patterns formed on the second insulation layer;a plurality of conductive patterns formed on the wiring structures such that the conductive patterns are connected to the second conductive patterns, respectively;a plurality of first electrodes formed on the plurality of first conductive patterns, respectively; anda plurality of second electrodes formed on the conductive patterns connected to the second conductive patterns of the wiring structure, respectively,wherein the first electrodes and the second electrodes have top surfaces which form a same plane.2. The wiring board according to claim 1 , wherein the plurality of second conductive patterns has a pattern width which is set smaller than a pattern width of the plurality of first conductive patterns.3. The wiring board according to claim 1 , wherein the second ...

Stacked Through-Silicon Via (TSV) Transformer Structure

A distributed active transformer is provided comprising a primary and a secondary winding. The primary winding comprises a first set of conductive vias extending in a direction between a first surface and a second surface of an element, a first set of first electrically conductive lines extending along the first surface, and a first set of second electrically conductive lines extending along the second surface. The secondary winding comprises a second set of conductive vias extending in a direction between the first surface and the second surface, a second set of first electrically conductive lines extending along the first surface, and a second set of second electrically conductive lines extending along the second surface. When energized, the primary winding generates magnetic flux extending in a direction parallel to the first surface and the second surface. The secondary winding receives energy transferred by the magnetic flux generated by the primary winding.

THROUGH-SILICON VIA (TSV) SEMICONDUCTOR DEVICES HAVING VIA PAD INLAYS

A semiconductor device includes an insulating layer on a surface of a substrate, a through-via structure vertically passing through the substrate and the insulating layer and being exposed on the insulating layer, and a via pad on a surface of the exposed through-via structure. The via pad includes a via pad body, and a via pad inlay below the via pad body and protruding into the insulating layer and surrounding the through-via structure. The via pad body and the via pad inlay include a via pad barrier layer directly on the insulating layer and a via pad metal layer on the via pad barrier layer. 1. A semiconductor device , comprising:a through-via structure vertically passing through a substrate, an end surface of the through-via structure being exposed on a surface of the substrate; anda via pad on the through-via structure, wherein the via pad comprises:a via pad body; anda via pad inlay below the via pad body and located at a lateral sides of the through-via structure.2. The semiconductor device of claim 1 , further comprising:a surface insulating layer located between the substrate and the via pad, wherein the via pad is directly in contact with the surface insulating layer.3. The semiconductor device of claim 2 , wherein the surface insulating layer includes a recess configured to surround the via pad inlay.4. The semiconductor device of claim 3 , wherein the via pad inlay includes a sidewall and a bottom claim 3 , and the sidewall is directly in contact with the through-via structure.5. The semiconductor device of claim 4 , wherein the via pad body comprises:a via pad barrier layer on the surface insulating layer; anda via pad metal layer on the via pad barrier layer, the via pad barrier layer being directly in contact with the through-via structure.6. The semiconductor device of claim 5 , wherein the via pad barrier layer extends onto a surface of the recess claim 5 , and the via pad metal layer extends on the via pad barrier layer on the surface of the ...

Ultra-thin near-hermetic package based on rainier

A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a metallic lid bonded to the wall and extending over the region of the top surface so that the lid, the wall and the dielectric layer cooperatively define an enclosed space; and a microelectronic element disposed within the space and electrically connected to the terminals.

SYSTEM-LEVEL PACKAGING METHODS AND STRUCTURES

A system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least two package layers on the first functional surface of the packaging substrate, wherein each package layer is formed by subsequently forming a mounting layer, a sealant layer, and a wiring layer. Further, the method includes forming a top sealant layer and planting connection balls on the second functional surface of the packaging substrate. 1. A system-level packaging method , comprising:providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface;forming at least two package layers on the first functional surface of the packaging substrate, wherein each package layer is formed by subsequently forming a mounting layer, a sealant layer, and a wiring layer;forming a top sealant layer; andplanting connection balls on the second functional surface of the packaging substrate.2. The method according to claim 1 , wherein forming at least two package layers further includes:attaching a first mounting layer on the packaging substrate;forming a first sealant layer on the packaging substrate at a same side attached with the first mounting layer;forming a first wiring layer on the first sealant layer;stacking a second mounting layer on the first wiring layer;forming a second sealant layer on the first sealant layer and covering the second mounting layer; andforming a second wiring layer on the second sealant layer.3. The method according to claim 2 , wherein attaching the first mounting layer further include:forming a glue layer on the first functional surface of the packaging substrate; andattaching the first mounting layer using the glue layer.4. ...

AVD HARDMASK FOR DAMASCENE PATTERNING

A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point. 1. A method comprising:forming a dielectric layer on a contact point of an integrated circuit structure;forming a hardmask comprising a dielectric material on a surface of the dielectric layer; andforming at least one via in the dielectric layer to the contact point using the hardmask as a pattern.2. The method of claim 1 , wherein the dielectric material of the hardmask comprises a dielectric constant greater than a dielectric constant of silicon dioxide.3. The method of claim 1 , wherein the dielectric material of the hardmask has a density that is greater than a dielectric material of the dielectric layer.4. The method of claim 2 , wherein the dielectric material of the hardmask is selected from the group consisting of silicon oxynitride claim 2 , hafnium oxide claim 2 , zirconium oxide claim 2 , hafnium silicate claim 2 , hafnium oxynitride and lanthanum oxide.5. The method of claim 2 , wherein a material of the dielectric layer comprises a dielectric constant less than a dielectric constant of silicon dioxide.6. The method of claim 2 , wherein a material of the dielectric layer is porous.7. The method of claim 1 , wherein the hardmask is a first hardmask claim 1 , the method further comprising:forming a second hardmask comprising a conductive material on the first hardmask; ...

SEMICONDUCTOR DEVICE

Provided is a semiconductor device capable of increasing the number of signals. A semiconductor device according to an embodiment of the invention includes memories; a controller that designates addresses of the memories; a mounting board having lines formed thereon, the lines connecting the controller with the memories; and a first ball group that connects the controller with the lines of the mounting board. A plurality of address lines formed on the mounting board includes an address line formed of a front surface wiring layer, and an address line formed of a back surface wiring layer. In each of the front surface wiring layer and the back surface wiring layer, each of the address lines from first balls of the first ball group is routed in order from a first memory to a fourth memory. 1. A semiconductor device comprising:first to n-th (n is an integer equal to or greater than 2) memories;a controller that designates addresses of the n number of memories;a multi-layer wiring board having lines formed thereon, the lines connecting the controller with the memories; anda solder ball group including a plurality of solder balls arranged in an array, and connecting the controller with the lines of the multi-layer wiring board, whereina plurality of address lines formed on the multi-layer wiring board includes a first address line formed of a first wiring layer of the multi-layer wiring board,a plurality of address lines formed on the multi-layer wiring board includes a second address line formed of a second wiring layer of the multi-layer wiring board, andin each of the first and second wiring layers, each of the first and second address lines from the solder balls of the solder ball group is routed in order from the first memory to the n-th memory.2. The semiconductor device according to claim 1 , whereinthe first wiring layer is formed on a mounting surface of each of the solder balls, andin the solder ball group, solar balls connected to the first address line are ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF

A semiconductor device includes a substrate, a plurality of signal lines, and at least one power line. The substrate includes an integrated circuit unit. The signal lines are disposed on the substrate and are configured to provide the integrated circuit unit with signals. The power line is disposed on the substrate and is configured to provide the integrated circuit unit with power supply on the substrate. The power line includes a stacked structure including a first power line and a second power line stacked on the first power line. 1. A semiconductor device comprising:a substrate comprising an integrated circuit unit;a plurality of signal lines disposed on the substrate and configured to provide the integrated circuit unit with signals; andat least one power line disposed on the substrate and configured to provide power to the integrated circuit unit, wherein the at least one power line includes a stacked structure comprising a first power line and a second power line stacked on the first power line.2. The semiconductor device of claim 1 , wherein a height of the at least one power line is higher than heights of the plurality of signal lines.3. The semiconductor device of claim 1 , wherein a height of the first power line is substantially equal to heights of the plurality of signal lines.4. The semiconductor device of claim 1 , wherein a width of the second power line is less than or equal to a width of the first power line.5. The semiconductor device of claim 4 , wherein a bottom surface of the second power line contacts a top surface of the first power line.6. The semiconductor device of claim 1 , further comprising an insulating interlayer disposed on the substrate and covering the plurality of signal lines and side walls of the first and second power lines.7. The semiconductor device of claim 6 , wherein a top surface of the second power line is substantially level with a top surface of the insulating interlayer.8. A semiconductor device comprising:a plurality ...

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package includes: a semiconductor chip: a first insulating layer, wherein the semiconductor chip is embedded in the first insulating layer such that the first surface and the side surface of the semiconductor chip are covered by the first insulating layer; a wiring structure on the first surface of the first insulating layer and comprising an insulating layer and a wiring layer; an outermost wiring layer on the wiring structure and having: a reinforcing wiring pattern; and a via wiring which penetrates the reinforcing wiring pattern and electrically connected to the reinforcing wiring pattern, wherein the via wiring is formed through the insulating layer of the wiring structure and electrically connected to the wiring layer of the wiring structure; a second insulating layer on the wiring structure to cover the outermost wiring layer. 1. A semiconductor package comprising: a first surface on which a first electrode pad is provided;', 'a second surface opposite to the first surface; and', 'a side surface between the first surface and the second surface,, 'a semiconductor chip comprisinga first insulating layer comprising a first surface and a second surface opposite to the first surface, wherein the semiconductor chip is embedded in the first insulating layer such that the first surface and the side surface of the semiconductor chip are covered by the first insulating layer;a wiring structure on the first surface of the first insulating layer and comprising an insulating layer and a wiring layer; a reinforcing wiring pattern; and', 'a via wiring which penetrates the reinforcing wiring pattern and electrically connected to the reinforcing wiring pattern, wherein the via wiring is formed through the insulating layer of the wiring structure and electrically connected to the wiring layer of the wiring structure;, 'an outermost wiring layer on the wiring structure and comprisinga second insulating layer on the wiring structure to cover the outermost wiring ...

WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

A wiring substrate includes a core substrate including a first wiring layer, an interlayer insulating layer formed by a resin layer containing fiber reinforcement material formed on the core substrate and a primer layer formed on the resin layer containing fiber reinforcement material, and the interlayer insulating layer having a via hole reaching the first wiring layer, and a second wiring layer formed on the primer layer, and connected to the first wiring layer through the via hole. 1. A wiring substrate , comprising:{'b': 10', '20, 'a core substrate () including a first wiring layer ();'}{'b': 40', '30', '32', '30', '40', '1', '20, 'an interlayer insulating layer () formed by a resin layer containing fiber reinforcement material () formed on the core substrate and a primer layer () formed on the resin layer containing fiber reinforcement material (), and the interlayer insulating layer () having a via hole (VH) reaching the first wiring layer (); and'}{'b': 22', '32', '20', '1, 'a second wiring layer () formed on the primer layer (), and connected to the first wiring layer () through the via hole (VH).'}210. A wiring substrate according to claim 1 , wherein a thickness of the core substrate () is 100 μm to 200 μm.33222. A wiring substrate according to claim 1 , wherein a surface of the primer layer () is formed as a roughened surface (R) claim 1 , and the second wiring layer () is formed on the roughened surface (R).4201010. A wiring substrate according to claim 1 , wherein the first wiring layer () is formed on both surface sides of the core substrate () claim 1 , and is connected mutually through a conductive layer (TE) formed in a through hole (TH) of the core substrate () claim 1 , and{'b': 00', '22', '10, 'the interlayer insulating layer ) and the second wiring layer () are formed on the both surface sides of the core substrate () respectively.'} This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. ...

Contact and Method of Formation

A system and method for forming contacts is provided. An embodiment comprises forming the contacts on a substrate and then coining the contacts by physically shaping them using, e.g., a molding chamber. The physical shaping of the contacts may be performed using a patterned portion of the molding chamber or else by placing a patterned stencil around the contacts prior before a force is applied to physically reshape the contacts. The contacts may be reshaped into a cylindrical, oval, cuboid, or rectangular shape, for example.

Shaped and oriented solder joints

The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic substrate with a plurality of shaped and oriented solder joints. The shaped and oriented solder joints may be substantially oval, wherein the major axis of the substantially oval solder joints may be substantially oriented toward a neutral point or center of the microelectronic device. Embodiments of the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stresses between the microelectronic device and the microelectronic substrate.

INTERCHANGEABLE CONNECTION ARRAYS FOR DOUBLE-SIDED DIMM PLACEMENT

A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate. Other embodiments are also disclosed and claimed. 1. A first memory device , comprising:a first ball grid array (BGA) that electrically couples the memory device to a set of signal lines in a memory module, wherein each ball in the BGA transfers an individual signal in the set of signals between the memory device and the memory module, and wherein at least a first signal routed through a first ball in the first ball grid array and a second signal routed through a second ball in the first ball grid array may be a mirrored signal pair, wherein being the mirrored signal pair causes the first signal to be routed through the second ball and the second signal to be routed through the first ball.2. The memory device of claim 1 , wherein the first memory device is coupled to a first side of the memory module and a second memory device is coupled to the second side of the memory module claim 1 , and wherein the second memory device has a second BGA claim 1 , the second BGA routing the same set of signals as the first BGA claim 1 , the first and second BGAs being substantially at the same locations on the opposite sides of the memory module claim 1 , wherein the second memory device does not have a mirrored signal pair.3. The memory device of claim 2 , wherein the mirrored signal pair in the first memory device causes a route in the memory module of a signal line transmitting the first signal to have a closer proximity to a route in the memory module of a signal line transmitting the second signal than if the first memory device did not have the mirrored signal pair.4. The memory device of claim 3 , wherein a distance from each ball associated with a given signal claim 3 , when implementing the ...

SOLID HOLE ARRAY AND MANUFACTURE METHOD THEREOF

A solid hole array and a manufacture method thereof are provided. The method for manufacturing the solid hole array comprises: forming a top hole array base and a bottom hole array base on a top surface and a bottom surface of a substrate respectively; forming a front hole in the top hole array base; forming a top protection layer on the substrate with the top hole array base, and forming a bottom protection layer on the bottom hole array base; forming a rear window in the bottom hole array base and the bottom protection layer; and etching through the substrate by alkali corrosion to connect the front hole with the rear window. In addition, the present disclosure also provides a solid hole array. Using the method of the present disclosure, the intensity of the front film is enhanced, the process steps are simplified, the cost is decreased, and a large scale manufacture is more likely. 1. A method for manufacturing a solid hole array , comprises:forming a top hole array base and a bottom hole array base on a top surface and a bottom surface of a substrate respectively;forming a front hole in the top hole array base;forming a top protection layer on the substrate with the top hole array base, and forming a bottom protection layer on the bottom hole array base;forming a rear window in the bottom hole array base and the bottom protection layer; andetching through the substrate by alkali corrosion to connect the front hole with the rear window.2. The method according to claim 1 , wherein the step of forming the front hole in the hole array base deposited on the top surface of the substrate further comprises:coating a photoresist on the top hole array base, and forming the front hole in the top hole array base by a photolithography and a reactive ion etching to expose the substrate.3. The method according to claim 1 , wherein the step of forming the rear window in the protection layer deposited on the bottom surface of the substrate further comprises:coating a photoresist ...