СПОСОБ ИЗГОТОВЛЕНИЯ НЕСУЩЕГО ЭЛЕМЕНТА ДЛЯ ПОЛУПРОВОДНИКОВЫХ ЧИПОВ

Изобретение относится к области крепления на твердом теле полупроводниковых приборов и может быть использовано для крепления полупроводниковых чипов на несущем элементе. Несущий элемент для полупроводникового чипа (23), в частности, для монтажа в чип-карте содержит подложку (15), несущую чип (23), и пленку (10) жесткости, ламинированную на несущую чип (23) сторону подложки (15), имеющую выемку (14), размещающую чип (23) и его выводы (24), край которой снабжен рамкой (12), выполненной за одно целое с пленкой (10). Техническим результатом изобретения является упрощение способа изготовления несущего элемента для полупроводниковых чипов. 7 з.п. ф-лы, 5 ил.

Полупроводниковое устройство

Einkapselungsverfahren

Verfahren zum Einkapseln eines Halbleiterbauelements, mit den folgenden Schritten: Bereitstellen eines Systemträgers (12), der eine erste Chippadzone und eine zweite Chippadzone aufweist, wobei jede Chippadzone eine erste Seite (60, 62) und eine zweite Seite (70, 72) aufweist, wobei die erste Chippadzone relativ zu der zweiten Chippadzone in der Höhe versetzt ist und wobei die erste Chippadzone und die zweite Chippadzone zusammenhängend sind; Befestigen eines ersten Chips (16) an der ersten Seite (62) der ersten Chippadzone; Befestigen eines zweiten Chips (14) an der ersten Seite (60) der zweiten Chippadzone; Drahtbonden von Drähten an den ersten und zweiten Chip (16, 14); Anordnen eines Gussrahmens gegenüber dem Systemträger (12), um eine Lücke zwischen den zweiten Seiten (72, 70) der ersten und der zweiten Chippadzonen und einer Oberfläche des Gussrahmens zu bilden; und Einkapseln mit einem den ersten Chip (16) und den zweiten Chip (14) überdeckenden Einkapselungsmaterial, das in die ...

Halbleiteranordnung

Verfahren zum Montieren von Halbleiterchips und entsprechende Halbleiterchipanordnung

Die vorliegende Erfindung schafft ein Verfahren zum Montieren von Halbleiterchips mit den Schritten: Bereitstellen eines Halbleiterchips (4) mit einer Vorderseite (VS), die einen Membranbereich (4a) und einen Peripheriebereich (5) aufweist, und einer Rückseite (RS), die eine an den Membranbereich (4a) angrenzende Kaverne (4c) aufweist; Vorsehen eines Substrats (1), welches eine Durchgangsöffnung (1a) aufweist; Montieren der Rückseite (RS) des Halbleiterchips (4) auf dem Substrat (1), derart, dass die Kaverne (4c) mit der Durchgangsöffnung (1a) in Fluidverbindung steht; und zumindest teilweises Befüllen der Kaverne (4c) mit einem Passivierungsgel (10) durch die Durchgangsöffnung (1a). Die Erfindung schafft ebenfalls eine entsprechende Halbleiterchipanordnung.

Halbleiterbauteil mit Korrosionsschutzschicht und Verfahren zur Herstellung desselben

Halbleiterbauteil (1; 23), das die folgenden Merkmale aufweist: - ein Schaltungsträger (2) mit mehreren Innenkontaktflächen (5), die ein erstes Material mit einem ersten elektrochemischen Potential aufweisen, - ein Halbleiterchip (3) mit einer aktiven Oberfläche (13) und einer Rückseite (11), wobei die aktive Oberfläche (13) mehrere Chipkontaktflächen (14) aufweist, die ein zweites Material mit einem zweiten elektrochemischen Potential aufweisen, und - Bonddrahtverbindungen (15) zwischen den Chipkontaktflächen (14) und den Innenkontaktflächen (5) des Schaltungsträgers (2), wobei die Bonddrähte (15) ein drittes Material mit einem dritten elektrochemischen Potential aufweisen, wobei die Verbindungsstellen (16) zwischen den Chipkontaktflächen (14) und den Bonddrähten (15) und die Verbindungsstellen (17) zwischen den Innenkontaktflächen (5) und den Bonddrähten (15) mit einer Korrosionsschutzschicht (20; 24) beschichtet sind, wobei Mittelbereiche (21) der Bonddrähte (15) frei von der Korrosionsschutzschicht ...

Leistungshalbleitermodul

Es wird ein Leistungshalbleitermodul offenbart. Eine Ausführungsform enthält ein Mehrschichtsubstrat mit mehreren Metallschichten und mehreren Keramikschichten, wobei die Keramikschichten zwischen den Metallschichten liegen.

THYRISTOR ASSEMBLIES

... 1,262,642. Thyristors. JOSEPH LUCAS (INDUSTRIES) Ltd. 5 May, .1969 [10 May 1968], No. 22232/68. Heading H1K. A thyristor element 14 is hermetically sealed in .a housing comprising a copper cup 11 sealed by glass-metal member 26. Copper contact plates 14, 15 are stacked with the element in a matching non-circular hole in insulating member 12. The contacting elements are urged together by annular spring washer 33 which acts through insulating member 16 which is so shaped as to interlock with flanged member 12 in only one angular position. Apertures 18 19 in member 16 are shaped as shown to press contact stud 25 against the cathode plate 15 of the thyristor and to form a seating for coil spring 22 which urges a stud 21 in the form of a car tridge resistor against the thyristor gate. After welding flange 28 to the rim of cup 11 the enclosure is evacuated and back-filled with inert gas via metal tubes 31, 32 which are then crimped on their respective conductors to seal the enclosure.

SEMICONDUCTOR DEVICES

... 1299514 Semi-conductor devices GENERAL ELECTRIC CO 3 Feb 1970 [3 Feb 1969 (2)] 5182/70 Heading H1K In a semi-conductor device adapted to be mounted under compression one major surface of a semi-conductor wafer 102 carries a thin Al coating 148, and a low thermal expansion coefficient (less than 10-5 per ‹C.) "back-up plate" 152 is mounted between, but not bonded to, the Al coating 148 and a terminal member 158 forming part of one end wall of a housing for the device. The housing includes a ceramic or glass ring 122 sealed at both ends by metal diaphragms 120, 168 carrying the terminal members 118, 158, which may be made of brass, Cu or Al. The back-up plate 152 may be of W or Mo carrying a malleable layer 154. The device shown is a Si thyristor having a central gate region 106a connected to a sprung lead 142 which passes through a slot 160 in the terminal member 158 and is insulated therefrom by an insulating lining 162 in the slot 160. An insulating ring 164 surrounds the end ...

A semi-conductor device

... 969,587. Semi-conductors. SIEMENSSCHUCKERTWERKE A.G. Aug. 13, 1962 [Aug. 12, 1961], No. 31045/62. Heading H1K. A semi-conductor device has a semi-conductor body adjacent a further body of different thermal coefficient of expansion with means for urging the bodies together so that on heating one body slides with respect to the other, the contacting and mutually sliding surfaces being of silver and nickel respectively. In the embodiment a semi-conductor rectifier element 7, e.g. of silicon, having a layer of silicon and a layer of nickel on each surface, rests on the silvered base4 of a copper container 1. The domed end 9b of a copper terminal member is urged against the element by the dished springs 12-14 mounted on an insulating body 10 and the apparatus is heated for a period causing the outer silver layer 8 on the element 7 to fuse into the surface of the dome 9b so that sliding occurs between the silver and nickel layer on the element 7. The coatings on the element 7 may be applied by ...

Encapsulating method and the product thereof

... 997,994. Welding by pressure. TEXAS INSTRUMENTS Inc. Dec. 29, 1961 [Dec. 29, 1960], No. 46763/61. Heading B3R. [Also in Division H1] Flanges 3, 10 of a cover and header of a semiconductor capsule are solid phase bonded together over areas 29 surrounding islands 28 comprising a metal which before bonding extended as an unbroken protective layer on one of the flanges. The cover flange 3 is of or is plated with copper or aluminium. The flange 10 of an alloy consisting of 20% nickel, 17% cobalt, 0.2% manganese, balance iron is provided with a layer 23 of copper or aluminium, a layer 25 of a frangible metal, e.g. nickel or chromium and a protective layer 27 of etch-resistant metal, e.g. gold, silver or platinum. The flange 3 may have a similar protective coating. When pressure is applied the protective layer 27 bonds to the frangible layer 25 which breaks up carrying the layer 27 with it to form the islands 28 between exposed copper or aluminium surfaces which solid phase bond. Specifications ...

High current rectifier

... 1,088,139. Semi-conductor devices. MOTOROLA Inc. June 18, 1965 [July 17, 1964], No. 25926/65. Heading H1K. A high current rectifier consists of a plurality of matched solid state rectifier cells each having one terminal in the form of a cap or can 12 and one in the form of a wire 15, the cells being connected in parallel by soldering between two terminal plates 14 and 17. Each cell (Figs. 2 and 3, not shown) consists of a diffused junction silicon disc coated with gold-over-nickel and soldered between copper discs which are in turn soldered to the steel can 12 and the wire 15 respectively, the solder being an alloy of silver, indium and lead. The cells are sealed by cover-plates welded to the can and contain calcium aluminium silicate to absorb moisture and deleterious gases. The cells are mass produced, are tested after encapsulation and sorted into matched groups. A matched group is then soldered between the plates 14 and 17-by discs 50 and rings 60 of a silver-tin alloy of lower melting ...

A process for dyeing polyolefine or polyvinylidene chloride filaments

Polyolefine or polyvinylidene chloride filaments are dyed with a monoazo dyestuff, the aromatic nucleus or nuclei of which is or are substituted by one or more straight- or branched-aliphatic side-chains with at least seven carbon atoms. The dye may be applied from aqueous suspension, or may be produced in situ by applying, separately and successively, the diazotized amine and the coupling component and then effecting coupling on the fibre. The dyestuffs employed in the examples are: (1) p-cetyl-aniline --> p-nonyl phenol, formed on the fibre; (2) p-amino-octyl-benzene --> b -naphthol, applied from aqueous suspension; (3) p-cetyl-aniline --> p-cetyl-phenol, applied from aqueous suspension; and (4) p-octadecyl-aniline --> b -naphthol, applied from aqueous suspension.

Improvements in or relating to semi-conductive devices

... 902,153. Semi-conductor devices. PHILIPS ELECTRICAL INDUSTRIES Ltd. Sept. 19, 1958 [Sept. 23, 1957], No. 30047/58. Class 37. A semi-conductive device having a vacuum-tight envelope 2, 3, has arsenic in the space between the envelope and the system 1 consisting of the semiconductive body with such associated parts as have been provided in manufacture to provide connections to the body and for diffusion and/or alloying completely or in part to form zones in the body, so that the system is capable of fulfilling its function. The arsenic may be in its free form and it may be carried in a finely divided state in a binder such as a silicone " grease " or " oil." After sealing, the device may be heated at a temperature between 80‹ C. and the lowest electrode melting point for 100 hours; though this melting point may sometimes be exceeded if the system is lacquered. Any space remaining in the envelope may be filled with, say, nitrogen, a rare gas, or hydrogen, or even air. Examples are given of ...

Package for electric device

A package for an electric device such as a surface acoustic wave filter or a semi-conductor device comprises a metallic cap 6 which is hermetically sealed to a base 2 with an insulating (plastics) liner 5 or inner cover 7 within the cap 6 so that any minute metallic fragments which might drop off the cap as the result of mechanical shocks do not affect the characteristics of the device. ...

Improvements in or relating to the manufacture of semi-conductor devices

... 775,191. Welding by pressure. GENERAL ELECTRIC CO., Ltd. Aug. 19, 1955 [Aug. 23, 1954], No. 24500/54. Class 83 (4). [Also in Group XXXVI] In the manufacture of a semi-conductor device in a sealed envelope, at least one seal is made by cold pressure welding, after the operative part of the device is mounted in the envelope. Fig. 1 shows a PN junction rectifier comprising a germanium wafer 3 on an oxygen-free high conductivity copper base I and having an alloy electrode comprising a bead of indium 5 and lead wire 7. The assembly is completed by placing a copper cover-plate 8 on to base 1 and cold welding the flanges 11 and 12. The lead wire 7 which may be of nickel, passes through, and is cold welded to, nickel tube 10 which is insulated from cover 8 by a glass region 9. In Fig. 2, which shows the apparatus for the cold welding, steel punches 15 and 16 sliding in tube 13, compress the flanges 11 and 12 together. A groove 12 in the base 1 accommodates the flow of metal. Wire 7 is welded to ...

VERFAHREN UND VORRICHTUNG ZUM HERSTELLEN EINER, INSBESONDERE VERTIKALEN, ANORDNUNG AUS MINDESTENS ZWEI ELEKTRONISCHEN KOMPONENTEN

PLAKSTIKVERKAPSELTE SEMICONDUCTOR DEVICES WITH IMPROVED CORROSION RESISTANCE

ELECTRICAL CONDENSER

Photoelectric cell with an isolating flat covering and procedure for the production the same

PROCEDURE FOR THE PRODUCTION OF A CARRIER ELEMENT FOR SEMICONDUCTOR CHIPS

An apparatus (WSM06)

Dispensing process for fabrication of microelectronic packages

Arrangement for encasing a functional device, and a process for the production of same

ARRANGEMENT FOR ENCASING A FUNCTIONAL DEVICE, AND A PROCESS FOR THE PRODUCTION OF SAME

METHOD AND APPARATUS FOR PACKAGING AND COOLING INTEGRATED CIRCUIT CHIPS

A packaging and cooling assembly for integrated circuit chips includes a base for reception of one or more circuit chips, and a combination heat sink and cover for attachment to the base. The circuit chips are mounted circuit side down on the base, and include flexible lead frames for attachment to bonding pads on the base. Compliant cushions that generally conform to the shape and size of the chips are held loosely between the circuit sides of the chips, and the base. The heat sink engages the back sides of the circuit chips when it is attached to the base. This causes the chips to compress the compliant cushions, thereby holding the chips firmly in position, and forming a high thermal conductivity interface between the chips and the heat sink. To further enhance the heat transfer characteristics of the interface, a thin film of fluid is coated on the back sides of each chip to fill in the microvoids which result from asperity contact of the heat sink and chip mating surfaces. A sealing ...

THYRISTOR WITH DISCOID HOUSING

EXPLOSION-PROOF SEMICONDUCTOR DEVICE

Einstellvorrichtung an Körnerreinigungsvorrichtungen, insbesondere für Dreschmaschinen.

Halbleiteranordnung, bei der der Halbleiterkörper in einem metallischen Behälter hermetisch eingeschlossen ist

Halbleiteranordnung

Elément de circuit pour hyperfréquences, comprenant une diode constituée par un semi-conducteur et une pointe de contact.

Verfahren zur Herstellung einer Halbleiteranordnung mit mindestens einer Sperrschicht, bei welcher der halbleitende Körper in einen aus wenigstens zwei Teilen bestehenden Glaskolben eingeschlossen ist, und nach diesem Verfahren hergestellte Halbleiteranordnung

Verfahren zur Herstellung einer mit einer hermetisch verschlossenen Ummantelung versehenen Halbleiter-Vorrichtung und gemäss dem Verfahren hergestellte Halbleiter-Vorrichtung

Punktkontakt-Halbleitervorrichtung

Halbleiteranordnung

Verfahren zur Herstellung eines Punktkontakt-Gleichrichters.

Halbleiteranordnung

Verfahren zur Herstellung einer eine Legierungselektrode aufweisenden Halbleitervorrichtung und nach dem Verfahren hergestellte Halbleitervorrichtung

Halbleiteranordnung

Halbleiteranordnung und Verfahren zu ihrer Herstellung

Verfahren zur Herstellung von mehrschichtigen Halbleiteranordnungen

Diode à semi-conducteur et son procédé de fabrication

Halbleiterbauelement

Halbleiteranordnung und Verfahren zu deren Herstellung

Steuerbare Halbleiteranordnung

Redresseur pour grandes intensités et son procédé de fabrication

Verfahren zur Herstellung einer Halbleiter-Vorrichtung

Verfahren zur Herstellung einer Halbleiter-Vorrichtung

Halbleiteranordnung vom Flächentyp

Verfahren zur Herstellung elektrischer Bauelemente und Anwendung dieses Verfahrens zur Herstellung von Halbleiterbauelementen

Halbleitervorrichtung

Verfahren zum Härten von Epoxyharzen durch stickstoffhaltige organische Borverbindungen

Halbleiteranordnung, Verfahren zu ihrer Herstellung und Vorrichtung zur Durchführung des Verfahrens

Halbleiterbauelement

Halbleiteranordnung

Verfahren zum Herstellen einer Halbleiteranordnung und zum Stabilisieren der pn-Übergänge an ihrem Halbleiterkörper

Halbleiteranordnung und Verfahren zur Herstellung einer solchen

Halbleiterbauelement

Vakuumdichter Verschluss für Halbleiterelemente

Procédé de fabrication d'un composant semiconducteur

Halbleiteranordnung

Halbleiterbauelement in Form einer Halbleiterdiode, insbesondere für niedrige Ströme, Verfahren zum Herstellen eines solchen und Mittel zur Ausführung dieses Verfahrens

Capsule plate pour composant semiconducteur commandé

Dispositif redresseur à semi-conducteur

Halbleiterbauelement

Dispositif de support

Kristalldiode, insbesondere Siliziumdiode mit scharf definierter Durchbruchsspannung in Sperrichtung

Halbleiteranordnung und Verfahren zu ihrer Herstellung

Halbleitende Sperrschichtvorrichtung in vakuumdichter Hülle und Verfahren zu ihrer Herstellung

Leitungsdurchführung für das Gehäuse einer Halbleiteranordnung und Verfahren zu ihrer Herstellung

Halbleiterbauelement mit Kunststoffüllung

Halbleiterbauelement

Halbleiteranordnung

Steuerbares Halbleiterbauelement

Halbleiteranordnung

Halbleiterbauelement mit gas- und feuchtigkeitsdichtem Gehäuse

Gekapseltes Halbleiterbauelement mit wenigstens teilweise aus Sintermetall und Kunststoff bestehenden Bauteilen und Verfahren zu seiner Herstellung

Procedimento di montaggio di uno o più circuiti elettronici integrati in un contenitore

HOUSING FOR A SEMICONDUCTOR HIGH SPEED ELEMENT.

СПОСОБ ИЗГОТОВЛЕНИЯ НЕСУЩЕГО ЭЛЕМЕНТА ДЛЯ ПОЛУПРОВОДНИКОВОГО ЧИПА

Задачей изобретения является разработка простого способа изготовления несущего элемента. Задача решена путём реализации способа изготовления несущего элемента согласно с п.1 формулы изобретения. Выгодные усовершенствования изобретения отображены в дополнительных пунктах формулы изобретения. Преимущество найденного способа состоит в том, что выполняются те же самые или схожие технологические операции, что и при изготовлении подложки или известных несущих элементов. Этими операциями являются операция высечки и нанесения слоёв. Кроме того, поскольку укрепляющая пластинка имеет такие же наружные размеры, чти и несущий элемент, для её нанесения может быть использовано то же оборудование, что и для нанесения медной фольги, из которой образуют контактные площадки.

СПОСІБ ВИКОНАННЯ СТРУМОПРОВІДНОГО ЕЛЕМЕНТА

Спосіб виготовлення струмопровідного елемента з матеріалу з попередньо заданою магнітною проникністю полягає в тому, що поверхню струмопровідного елемента покривають твердою оболонкою, яка складається з одного або декількох шарів парамагнітного діелектричного матеріалу, магнітна проникність якого в декілька разів перевищує магнітну проникність матеріалу струмопровідного елемента. Оболонку закріплюють на струмопровідному елементі на відстані від поверхні елемента, яка не перевищує довжини хвилі електромагнітного випромінювання, що відповідає частоті змінного струму, який проходить через елемент.

Power semiconductor module

Chip package and method for forming the same

The present invention provides a chip package and a method for forming the same. The chip package includes a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface; and a conducting pad structure disposed in the dielectric layer and electrically connected to the device region; a cover substrate disposed between the chip and the cover substrate, wherein the spacer layer, a cavity is created an surrounded by the chip and the cover substrate on the device region, and the spacer layer is in direct contact with the chip without any adhesion glue disposed between the chip and the spacer layer. The chip package technology provided in the invention can reduce the size of the chip package, facilitate large-scale production of chip packages, and ensure the quality of the chip packages, and/or reduce the process cost and time.

Heap semiconductor packaging pieces

Integrated circuit package's antidetonation system

Semiconductor package and manufacturing method thereof

For flip chip package structure

Semiconductor device and method of fabricating the same

High withstand voltage power semiconductor

Underfill adhesive, preparation method thereof and chip packaging structure

The invention relates to the technical field of chip packaging, in particular to an underfill adhesive, a preparation method thereof and a chip packaging structure. Comprising the following raw materials in percentage by mass: 20-36.5 wt% of bisphenol F type epoxy resin; 0.7 wt%-3 wt% of naphthalene epoxy resin; 0.7 wt%-3 wt% of polyfunctional epoxy resin; 0.5 wt% to 3 wt% of a reactive diluent; 1 wt%-8 wt% of a latent dicyandiamide curing agent; 0.3 wt% to 0.5 wt% of an imidazole accelerator; 55 wt%-75 wt% of an inorganic filler; 0.5 wt% to 2 wt% of a functional auxiliary agent; the inorganic filler comprises a first inorganic filler and a second inorganic filler, and the particle size D50 of the first inorganic filler is smaller than the particle size D50 of the second inorganic filler. The underfill adhesive disclosed by the invention has the properties of low viscosity, high glass transition temperature, high heat resistance, high bending modulus and high elastic modulus at the same ...

Semiconductor device and test system for the semiconductor device

A semiconductor package including a stress mitigation unit that mitigates stress to the semiconductor chip. The semiconductor package includes a substrate, a semiconductor chip on the substrate, an encapsulation member formed on the substrate and covering the first semiconductor chip, and the stress mitigation unit mitigating stress from a circumference of the first semiconductor chip to the first semiconductor chip. The stress mitigation unit includes at least one groove formed in the encapsulation member.

Underfill method and chip package

A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.

Unitary housing for electronic device

An electronic device having a unitary housing is disclosed. The device can include a first housing component having an open cavity, an internal electronic part disposed within the cavity, a second housing component disposed across the cavity, and a support feature disposed within the cavity and arranged to support the second housing component. The first housing component can be formed from metal, while the second housing component can be formed from a plurality of laminated foil metal layers. The second housing component can be attached to the first housing component via one or more ultrasonic welds, such that a fully enclosed housing is created. The fully enclosed housing can be hermetically sealed, and the outside surfaces thereof can be machined or otherwise finished after the ultrasonic welding.

Die Seal for Integrated Circuit Device

Disclosed herein is a semiconductor device having a novel stress reduction structures that are employed in an effort to eliminate or at least reduce undesirable cracking or chipping of semiconductor die. In one example, the device includes a die comprising a semiconducting substrate, wherein the die includes a cut surface. The device also includes a first die seal that defines a perimeter, and at least one stress reducing structure, at least a portion of which is positioned between the perimeter defined by the first die seal and the cut surface, wherein the cut surface exposes at least a portion of the stress reducing structure.

Semiconductor light emitting device, method of manufacturing the same, and lighting apparatus and display apparatus using the same

The present invention aims to provide a semiconductor light emitting device that may be firmly attached to a substrate with maintaining excellent light emitting efficiency, and a manufacturing method of the same, and a lighting apparatus and a display apparatus using the same. In order to achieve the above object, the semiconductor light emitting device according to the present invention includes a luminous layer, a light transmission layer disposed over a main surface of the luminous layer, and having depressions on a surface facing away from the luminous layer, and a transmission membrane disposed on the light transmission layer so as to follow contours of the depressions, and light from the luminous layer is irradiated so as to pass through the light transmission layer and the transmission membrane.

Flip chip assembly process for ultra thin substrate and package on package assembly

In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.

Semiconductor package and stacked semiconductor package

A semiconductor package includes a semiconductor chip having a plurality of bonding pads, dielectric members formed over the semiconductor chip in such a way as to expose portions of respective bonding pads and having a trapezoidal sectional shape, and bumps formed to cover the exposed portions of the respective bonding pads and portions of the dielectric members and having a step-like sectional shape.

Method for Forming Chip-on-Wafer Assembly

A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

SEMICONDUCTOR INTEGRATED DEVICE WITH MECHANICALLY DECOUPLED ACTIVE AREA AND RELATED MANUFACTURING PROCESS

A semiconductor integrated device is provided with: a die having a body of semiconductor material with a front surface, and an active area arranged at the front surface; and a package having a support element carrying the die at a back surface of the body, and a coating material covering the die. The body includes a mechanical decoupling region, which mechanically decouples the active area from mechanical stresses induced by the package; the mechanical decoupling region is a trench arrangement within the body, which releases the active area from an external frame of the body, designed to absorb the mechanical stresses induced by the package. 1. A semiconductor integrated device comprising:a die having a body of semiconductor material with a front surface and a back surface, an active area arranged at the front surface, a coating material covering a portion of the front surface, the body including a mechanical decoupling region configured to mechanically decouple the active area from stresses; anda package that includes mold compound and a support element, the back surface of the die being located on the support element, wherein the package is configured to the stresses.2. The semiconductor integrated device according to claim 1 , wherein the mechanical decoupling region includes a trench arrangement within the body claim 1 , the trench arrangement being configured to release the active area from an external frame of the body claim 1 , the external frame being configured to absorb the stresses induced by the package.3. The semiconductor integrated device according to claim 2 , wherein the trench arrangement defines within the body a mechanically released structure having a mushroom shape claim 2 , the mushroom shape includes a head portion and a stem portion claim 2 , the head portion includes the active area and the stem portion has a base that is configured to be attached to the support element of the package.4. The semiconductor integrated device according to ...

Semiconductor package substrate and method, in particular for mems devices

A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.

Semiconductor chips including passivation layer trench structure

An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.

TSV SUBSTRATE STRUCTURE AND THE STACKED ASSEMBLY THEREOF

The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively. 1. A substrate structure comprising:a substrate comprising a first surface, a corresponding second surface, and a through-silicon via (TSV) communicating the first surface with the second surface through the substrate; anda conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a side surface, a first endface corresponding to the first surface of the substrate, and a second endface corresponding to the second surface of the substrate.2. The substrate structure of claim 1 , wherein the conductor unit further comprises a first extensional part formed on the side surface of the conductor body in proximity to the first endface.3. The substrate structure of claim 2 , wherein the first extensional part surrounds the conductor body.4. The substrate structure of claim 2 , wherein the conductor unit further comprises a second extensional part formed on the side surface of the conductor body in proximity to the second endface.5. The substrate structure of claim 4 , wherein the second extensional part surrounds the conductor body.6. (canceled)7. The substrate structure of claim 1 , wherein the conductor unit further comprises:a first protrusion formed on the base surface of the conductor body at the first endface; anda second protrusion formed on the second endface of the conductor body.8. The substrate structure of claim 1 , wherein the conductor further comprises:a first protrusion formed on the base surface of ...

Semiconductor Device and Method of Forming Base Leads from Base Substrate as Standoff for Stacking Semiconductor Die

A semiconductor device has a base substrate with first and second opposing surfaces. A first etch-resistant conductive layer is formed over the first surface of the base substrate. A second etch-resistant conductive layer is formed over the second surface of the base substrate. A first semiconductor die has bumps formed over contact pads on an active surface of the first die. The first die is mounted over a first surface of the first conductive layer. An encapsulant is deposited over the first die and base substrate. A portion of the base substrate is removed to form electrically isolated base leads between opposing portions of the first and second conductive layers. A second semiconductor die is mounted over the encapsulant and a second surface of the first conductive layer between the base leads. A height of the base leads is greater than a thickness of the second die. 1. A semiconductor device , comprising:a base substrate including first and second opposing surfaces;a first conductive layer formed over the first surface of the base substrate;a second conductive layer formed over the second surface of the base substrate, wherein portions of the base substrate are electrically isolated to form base leads between the first conductive layer and second conductive layer;a first semiconductor die disposed over the first conductive layer;an encapsulant deposited over the first semiconductor die and first conductive layer; anda second semiconductor die disposed over the first conductive layer between the base leads.2. The semiconductor device of claim 1 , wherein the first semiconductor die and second semiconductor die are electrically coupled to opposite sides of a portion of the first conductive layer.3. The semiconductor device of claim 1 , wherein a height of the base leads is greater than a thickness of the second semiconductor die.4. The semiconductor device of claim 1 , wherein the first conductive layer and second conductive layer include an etch-resistant ...

LAMINATE AND METHOD FOR SEPARATING THE SAME

A laminate including a supporting member which is light transmissive; a supported substrate supported by the supporting member; an adhesive layer provided on a surface of the supported substrate which surface faces toward the supporting member; and a release layer which is made of a fluorocarbon and is provided between the supporting member and the supported substrate, the release layer having a property that changes when it absorbs light coming through the supporting member. 1. A laminate comprising:a supporting member which is light transmissive;a supported substrate supported by the supporting member;an adhesive layer provided on a surface of the supported substrate, wherein said surface faces toward the supporting member; anda release layer which is made of a fluorocarbon and is provided between the supporting member and the supported substrate,the release layer has a property that changes when it absorbs light coming through the supporting member.2. The laminate as set forth in claim 1 , wherein the release layer is formed by plasma CVD.3. The laminate as set forth in claim 1 , wherein the supporting member is made of glass or silicon.4. The laminate as set forth in claim 1 , further comprising at least one layer provided between the supporting member and the release layer.5. A method for separating the supported substrate and the supporting member from each other which are included in a laminate as set forth in claim 1 ,said method comprising changing a property of the release layer by irradiating the release layer with light through the supporting member. The present invention relates to (i) a laminate produced by adhering together a supporting member and a supported substrate supported by the supporting member and (ii) a method for separating the laminate.As mobile phones, digital AV devices, IC cards and the like are highly functionalized, it is more demanded that a semiconductor silicon chip (hereafter referred to as “chip”) be highly integrated in a ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. 115-. (canceled)16. A semiconductor device comprising:a wiring substrate including a plurality of build-up substrates stacked with one another, each of the plurality of build-up substrates having an insulating layer with through holes and conductive wirings, the wiring substrate having a first surface and a second surface opposite to each other;a semiconductor chip comprising a silicon substrate having a main surface and a rear surface opposite to each other, semiconductor elements on the main surface, insulating films over the semiconductor elements including a silicon oxide film and an interlayer dielectric film with a dielectric constant lower than that of the silicon oxide film, pad electrodes over the insulating films, and internal wiring layers electrically connecting to the semiconductor elements and the pad electrodes,the semiconductor chip being mounted on the wiring substrate via first bump electrodes such that the main surface of the silicon substrate faces the first surface of the wiring substrate, and such that the pad electrodes of the semiconductor chip are electrically connected to conductive wirings of a first one of the plurality of build-up substrates of the wiring substrate via the first bump electrodes, respectively;a resin layer between the semiconductor chip and the first one of build-up substrates and between the first bump electrodes; andsecond bump electrodes being on the second surface of the wiring substrate, and being electrically connected to conductive wirings of a second one of the plurality of build-up substrates of the wiring substrate,wherein each of the insulating layers of the plurality of build-up substrates contains glass cloths, respectively.17. The semiconductor device according to claim 16 , wherein a thickness of each of the plurality of build-up substrates is the same ...

SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME

A semiconductor apparatus comprises of a first semiconductor chip having a through silicon via (TSV) and a second semiconductor chip also having a TSV, wherein the respective semiconductor chips are stacked vertically and are connected through a conductive connection member without the assistance of an additional bump between the conductive connection member and the second semiconductor chip. 1. A semiconductor apparatus comprising:a first semiconductor chip having a through silicon via (TSV); anda second semiconductor chip also having a TSV,wherein the respective semiconductor chips are stacked vertically and are connected through a conductive connection member without the assistance of an additional bump between the conductive connection member and the second semiconductor chip.2. The semiconductor apparatus according to claim 1 , wherein the first semiconductor chip having the TSV comprises:a first bump to enable signal exchange with the TSV of the second semiconductor chip.3. The semiconductor apparatus according to claim 2 , wherein the conductive connection member is formed between the first bump of the first semiconductor chip and the TSV of the second semiconductor chip.4. The semiconductor apparatus according to claim 3 , wherein the conductive connection member is made as a single unit of one or more conductive materials.5. The semiconductor apparatus according to claim 3 , wherein the conductive connection member is a solder ball.6. A semiconductor apparatus comprising:a first semiconductor chip comprising:a first TSV; anda first bump to enable the first semiconductor chip to exchange signal with the outside through the first TSV;a second semiconductor chip comprising:a second TSV; anda second bump to enable the second semiconductor chip to exchange signal with the first semiconductor chip through the second TSV; anda conductive connection member having no bump formed between the first bump and the second TSV.7. The semiconductor apparatus according to ...

Multi-Chip Packages and Methods of Manufacturing the Same

Multi-chip packages are provided having a first semiconductor chip arranged on a package substrate. The first semiconductor chip includes a first bonding pad connected to the package substrate. A second semiconductor chip is arranged on the first semiconductor chip. The second semiconductor chip has an overhang that protrudes from a side surface of the first semiconductor chip, and a second bonding pad arranged on the overhang. A third semiconductor chip is arranged on the second semiconductor chip to expose the overhang. The third semiconductor chip has a third bonding pad. A first conductive wire may be connected between the second bonding pad and the third bonding pad. A second conductive wire may be connected between the third bonding pad and the package substrate. 1. A multi-chip package comprising:a package substrate;a first semiconductor chip on a first surface of the package substrate, the first semiconductor chip having a first bonding pad that is electrically coupled to the package substrate;a second semiconductor chip arranged on a first surface of the first semiconductor chip, the second semiconductor chip having an overhang that protrudes from a side surface of the first semiconductor chip and a second bonding pad on the overhang;a third semiconductor chip arranged on a first surface of the second semiconductor chip to expose the overhang, the third semiconductor chip having a third bonding pad;a first conductive wire that electrically connects the second bonding pad and the third bonding pad; anda second conductive wire that electrically connects the third bonding pad and the package substrate.2. The multi-chip package of claim 1 , further comprising:a fourth semiconductor chip between the package substrate and the first semiconductor chip, the fourth semiconductor chip having a fourth bonding pad;a third conductive wire that electrically connects the first bonding pad and the fourth bonding pad; anda fourth conductive wire that electrically connects ...

Fully molded fan-out

A method for manufacturing a device package may include constructing a spacer element coupled with a surface of a semiconductor die unit, where the spacer element is configured to create a gap between the semiconductor die unit and a surface of a carrier, and encapsulating the semiconductor die unit within a mold compound, where the encapsulating includes introducing the mold compound into the gap.

STACKED WAFER STRUCTURE AND METHOD FOR STACKING A WAFER

A stacked wafer structure includes a substrate; dams provided on the substrate and having protrusions on a surface thereof; and a wafer with recesses provided on the dam. The protrusions on the surface of the dams are wedged into the recesses of the wafer, preventing air chambers from forming between the recesses of the wafer and the dams, so that the wafer is not separated from the dams due to the presence of air chambers during subsequent packaging process. A method for stacking a wafer is also provided. 1. A stacked wafer structure , comprising:a substrate;at least a dam provided on the substrate and having protrusions on a surface thereof; anda wafer provided on the dam, with the protrusions embedded into the wafer.2. The stacked wafer structure of claim 1 , wherein the substrate is a silicon substrate or a glass substrate.3. The stacked wafer structure of claim 1 , wherein the protrusions are wedged into the wafer.4. The stacked wafer structure of claim 1 , wherein the dam at least includes a first layer coupled to the substrate and a second layer coupled to the wafer.5. The stacked wafer structure of claim 4 , wherein the first layer and the second layer are made of the same or different material.6. The stacked wafer structure of claim 4 , wherein the first layer and the substrate are made of the same material claim 4 , and the second layer and the wafer are made of the same material.7. The stacked wafer structure of claim 4 , wherein the first layer is the protrusions.8. The stacked wafer structure of claim 4 , wherein the second layer is the protrusions.9. A method for stacking a wafer claim 4 , comprising:forming on a substrate at least a dam having protrusions thereon, andcombining a wafer onto the dam, with the protrusions embedded into the wafer.10. The method of claim 9 , wherein the substrate is a silicon substrate or a glass substrate.11. The method of claim 9 , wherein the protrusions are wedged into the wafer.12. The method of claim 9 , wherein the ...

DICING TAPE-INTEGRATED WAFER BACK SURFACE PROTECTIVE FILM

The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device. 1. A dicing tape-integrated wafer back surface protective film comprising:a dicing tape comprising a base material and a pressure-sensitive adhesive layer formed on the base material; anda wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape,wherein the wafer back surface protective film is colored, andwherein the wafer back surface protective film has a moisture absorbance of 1% by weight or less after the wafer back surface protective film is allowed to stand under an atmosphere of a temperature of 85° C. and a humidity of 85%RH for 168 hours.2. The dicing tape-integrated wafer back surface protective film according to claim 1 , wherein said colored wafer back surface protective film has a laser marking ability.3. The dicing tape-integrated wafer back surface protective film according to claim 1 , which is used for a flip chip-mounted semiconductor device.4. A process for producing a semiconductor device using a dicing tape-integrated wafer back surface protective film claim 1 , said process comprising steps of:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'attaching a workpiece onto said colored wafer back surface protective film of the dicing tape-integrated wafer back surface protective film according to ,'}dicing the workpiece to form a chip-shaped workpiece,peeling the chip-shaped workpiece from the pressure- ...

SEMICONDUCTOR DEVICE

A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening. 113-. (canceled)14. A semiconductor device , comprising:a substrate including a chip region;a plurality of dielectric films formed over the substrate;seal rings formed in a peripheral part of a chip region, the seal rings including a first seal ring and a second seal ring, the first seal ring surrounding the second seal ring, the first seal ring and the second seal ring both provided through at least one of the plurality of dielectric films in the peripheral part of the chip region;an interconnect formed in the plurality of dielectric films in the chip region;a first dielectric film included in the plurality of dielectric films and being in contact with an upper surface of the interconnect;a first opening provided in the first dielectric film and formed on the first seal ring;a second opening provided in the first dielectric film and formed on the second seal ring;a third opening provided in the first dielectric film and formed on the interconnect;a first cap layer disposed in the first opening and being in contact with the first seal ring;a second cap layer disposed in the second opening and being in contact with the second seal ring; anda pad electrode disposed in the third opening and being in contact with the interconnect.15. The semiconductor device of claim 14 , wherein a thickness of a center of the first cap layer in a depth direction is larger ...

Seal rings in electrochemical processors

A seal ring for an electrochemical processor does not slip or deflect laterally when pressed against a wafer surface. The seal ring may be on a rotor of the processor, with the seal ring having an outer wall joined to a tip arc through an end. The outer wall may be a straight wall. A relatively rigid support ring may be attached to the seal ring, to provide a more precise sealing dimension. Knife edge seal rings that slip or deflect laterally on the wafer surface may also be used. In these designs, the slipping is substantially uniform and consistent, resulting in improved performance.

SEMICONDUCTOR ELEMENT HOUSING PACKAGE AND SEMICONDUCTOR DEVICE EQUIPPED WITH THE SAME

A semiconductor element housing package includes a substrate, a frame body disposed on the substrate; an insulating substrate disposed in a frame-body-surrounded region of the substrate; a first mounting member disposed on the insulating substrate, for mounting a power semiconductor element thereon; a second mounting member disposed on the insulating substrate so as to be spaced away from the first mounting member; a first lead member having a first bend; and a second lead member having a second bend. The first lead member is disposed so as to pass through the frame body from an exterior thereof and extend over the first mounting member and makes connection therewith through the first bend. The second lead member is disposed so as to pass through the frame body from the exterior thereof and extend over the second mounting member and makes connection therewith through the second bend. 1. A semiconductor element housing package , comprising:a substrate;a frame body disposed on the substrate;an insulating substrate disposed in a region of the substrate, the region being surrounded with the frame body;a first mounting member disposed on the insulating substrate, for mounting a power semiconductor element thereon;a second mounting member disposed on the insulating substrate being spaced away from the first mounting member;a first lead member passing through the frame body from an exterior thereof, comprising a first bend and making connection with the first mounting member through the first bend; anda second lead member passing through the frame body from the exterior thereof, comprising a second bend and making connection with the second mounting member through the second bend.2. The semiconductor element housing package according to claim 1 ,wherein the first mounting member and the second mounting member are configured to be a rectangular plate-like body, andthe first lead member extends in a longitudinal direction of the first mounting member, and the second lead ...

STACKED SEMICONDUCTOR DEVICE

A first semiconductor package which is located on an upper side includes a first printed wiring board and an encapsulation resin for encapsulating a first semiconductor chip. A second semiconductor package which is located on a lower side includes a second printed wiring board. The first printed wiring board includes first lands and a first solder resist having first openings for exposing the first lands. The second printed wiring board includes second lands opposed to the first lands, respectively, and a second solder resist having second openings for exposing the second lands and opposed to the first openings, respectively. The first lands and the second lands are solder joined to each other through the first openings and the second openings, respectively. The opening area of the first opening is set to be smaller than the opening area of the second opening. This improves joint reliability. 1. A stacked semiconductor device , comprising: a first semiconductor element;', 'a first printed wiring board having the first semiconductor element mounted on one surface thereof and having multiple first lands formed on another surface thereof, the multiple first lands each having a solder portion formed thereon; and', 'a first resin for encapsulating the first semiconductor element; and, 'a first semiconductor package comprising a second semiconductor element; and', 'a second printed wiring board having the second semiconductor element mounted on one surface thereof and a second land to be joined to the solder portion formed on the one surface thereof, and having multiple terminals for external connection for electrical connection to an outside formed on another surface thereof, wherein:, 'a second semiconductor package comprisingthe first semiconductor package is stacked on the one surface of the second semiconductor package;the first printed wiring board has a first solder resist formed on the another surface thereof, each of the multiple first lands having a part exposed ...

Semiconductor device and manufacturing method for semiconductor device

An image pickup apparatus includes a semiconductor chip including a light receiving section, a frame-like spacer arranged on the semiconductor chip to surround the light receiving section, a transparent flat plate section arranged on the semiconductor chip via the spacer and having a plan view dimension larger than a plan view dimension of the spacer and smaller than a plan view dimension of the semiconductor chip, and a reinforcing member for filling a gap between the semiconductor chip and the transparent flat plate section on the outer side of the spacer and having a plan view dimension larger than the plan view dimension of the transparent flat plate section and smaller than the plan view dimension of the semiconductor chip.

PLASMA-ENHANCED ATOMIC LAYER DEPOSITION OF CONDUCTIVE MATERIAL OVER DIELECTRIC LAYERS

Methods of forming a conductive metal layer over a dielectric layer using plasma enhanced atomic layer deposition (PEALD) are provided, along with related compositions and structures. A plasma barrier layer is deposited over the dielectric layer by a non-plasma atomic layer deposition (ALD) process prior to depositing the conductive layer by PEALD. The plasma barrier layer reduces or prevents deleterious effects of the plasma reactant in the PEALD process on the dielectric layer and can enhance adhesion. The same metal reactant can be used in both the non-plasma ALD process and the PEALD process. 1. An integrated circuit device comprising:a dielectric layer;a plasma barrier over the dielectric layer comprising a first metal, wherein the plasma barrier is between about 0.25 nm and about 1.75 nm thick; anda conductive layer over the plasma barrier comprising a second metal.2. The integrated circuit device of claim 1 , wherein first and second metal are the same.3. The integrated circuit device of claim 1 , wherein the plasma barrier is between about 0.125 nm and about 0.875 nm thick.4. The integrated circuit device of claim 3 , wherein the plasma barrier is between about 0.05 nm and about 0.35 nm thick.5. The integrated circuit device of claim 1 , wherein the plasma barrier is amorphous and the conductive layer is crystalline.6. The integrated circuit device of claim 1 , wherein the first metal has a first structure and the second metal has a second structure and wherein the first structure and the second structure substantially align.7. The integrated circuit device of claim 1 , wherein the dielectric layer is chosen from the group consisting of TaO claim 1 , TiO claim 1 , HfO claim 1 , ZrO claim 1 , AlO claim 1 , LaO claim 1 , HfSiO claim 1 , HfZrO claim 1 , HfAlO claim 1 , and LnAlO.8. The integrated circuit device of claim 7 , wherein the dielectric layer is AlO.9. The integrated circuit device of claim 1 , wherein the plasma barrier comprises an elemental metal ...

Laser Processing Method and Semiconductor Device

A laser processing method which can reliably form a modified region within an object to be processed along a desirable part in a line to cut is provided. 18-. (canceled)9. A semiconductor apparatus , comprising:a substrate having a front face, a rear face, and a side wall;a laminate formed on the front face of the substrate, the laminate having a side wall, the side wall of the laminate being flush with the side wall of the substrate;a metal film embedded in the laminate, the metal film extending substantially in parallel to the front face of the substrate and a side of the metal film being exposed at the side wall of the laminate; anda modified region having a longitudinal shape extending substantially in parallel to the front face of the substrate and arranged along the side wall of the substrate, the modified region not being formed at an area in the substrate,wherein the metal film is arranged above the area in the substrate where the modified region is not formed.10. The semiconductor apparatus according to claim 9 ,wherein the semiconductor apparatus has a rectangular shape, and the substrate and the laminate each have four side walls that are flush with respect to each other, andwherein the modified region is located on each of the sidewalls of the substrate.11. The semiconductor apparatus according to claim 10 ,wherein the area is located at a central area of the side wall of the substrate, and the modified region is firmed at the edges of the side wall of the substrate.12. The semiconductor apparatus according to claim 9 ,wherein the modified region is at least one of a molten processed region of the substrate, a phase change region of the substrate, and a region having a changed crystal structure.13. The semiconductor apparatus according to claim 9 ,wherein the modified region is a region in the substrate that has changed from a first structure into a second structure, the first structure being at least one of a monocrystalline structure, an amorphous ...

Low Stress Package For an Integrated Circuit

A package that electrically connects an integrated circuit to a printed circuit board includes a frame and a package body that encases a portion of the frame and the integrated circuit. The frame includes a mounting region that is connected to the printed circuit board, and a cantilevering region that cantilevers away from the mounting region. The cantilevering region retains the integrated circuit in a flexible fashion. 1. A package for electrically connecting an integrated circuit to a printed circuit board , the package comprising:a first frame that includes a first mounting region that is adapted to be connected to the printed circuit board, and a first cantilevering region that cantilevers away from the first mounting region;a first connector that connects the integrated circuit to the first cantilevering region; anda package body that encases at least a portion of the first frame and the integrated circuit.2. The package of further comprising (i) a second frame that includes a second cantilevering region claim 1 , and a second mounting region that is adapted to be electrically connected to the printed circuit board claim 1 , the second frame being spaced apart from the first frame; and (ii) a second connector that connects the integrated circuit to the second cantilevering region; wherein the package body encases at least a portion for the second frame.3. The package of further comprising (i) a third frame that includes a third cantilevering region claim 2 , and a third mounting region that is adapted to be electrically connected to the printed circuit board claim 2 , the third frame being spaced apart from the first frame and the second frame; and (ii) a third connector that connects the integrated circuit to the third cantilevering region; wherein the package body encases at least a portion for the third frame.4. The package of further comprising (i) a fourth frame that includes a fourth cantilevering region claim 3 , and a fourth mounting region that is ...

SEMICONDUCTOR DEVICE HAVING CRACK-RESISTING RING STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor device an interlayer insulating layer disposed over a semiconductor substrate, and including a plurality of wiring layers; a seal ring disposed in the interlayer insulating layer, and surrounding a circuit region of the semiconductor substrate; a crack lead ring disposed in the interlayer insulating layer, and surrounding the seal ring; and a protective film disposed over the interlayer insulating layer, and covering the crack lead ring and the seal ring. The crack lead ring includes an uppermost wiring layer in an uppermost layer of a plurality of wiring layers. When the crack lead ring has a wiring in an underlayer below the uppermost layer, the uppermost layer wiring extends towards the outside of the device, relative to the wiring in the underlayer. The protective film has an end overlapped with an end of the uppermost layer wiring to form a step over the interlayer insulating layer. 1. A semiconductor device , comprising:a semiconductor substrate;an interlayer insulating layer disposed over the semiconductor substrate and including a plurality of wiring layers;a seal ring disposed in the interlayer insulating layer, and surrounding a circuit region of the semiconductor substrate;a crack lead ring disposed in the interlayer insulating layer, and surrounding the seal ring; anda protective film disposed over the interlayer insulating layer, and covering the crack lead ring and the seal ring,wherein the crack lead ring includes an uppermost layer wiring in an uppermost layer of a plurality of wiring layers,wherein when the crack lead ring has a wiring in an underlayer below the uppermost layer, the uppermost layer wiring extends in a direction away from the circuit region towards an outside of the device, relative to the wiring in the underlayer, andwherein the protective film has an end overlapped with an end of the uppermost layer wiring to form a step over the interlayer insulating layer.2. The semiconductor device according to claim 1 ,wherein ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME

An semiconductor device includes a semiconductor substrate; a metal layer arranged above the semiconductor substrate; a first passivation film that contacts at least a portion of one side surface of the metal layer; and a second passivation film that is arranged extending from the first passivation film to the metal layer, and contacts an upper surface of the first passivation film, and contacts at least a portion of an upper surface of the metal layer. 1. An semiconductor device comprising:a semiconductor substrate;a metal layer arranged above the semiconductor substrate;a first passivation film that contacts at least a portion of one side surface of the metal layer; anda second passivation film that is arranged extending from the first passivation film to the metal layer, and contacts an upper surface of the first passivation film, and contacts at least a portion of an upper surface of the metal layer.2. The semiconductor device according to claim 1 , wherein a linear expansion coefficient of the metal layer is larger than a linear expansion coefficient of the second passivation film claim 1 , and a linear expansion coefficient of the first passivation film is larger than the linear expansion coefficient of the second passivation film.3. The semiconductor device according to claim 1 , wherein the first passivation film includes a polyimide.4. The semiconductor device according to claim 1 , wherein the second passivation film is semiconductive.5. The semiconductor device according to claim 1 , further comprising a peripheral voltage-resistant region formed on an outer peripheral portion of the semiconductor substrate claim 1 , wherein the second passivation it is positioned in the peripheral voltage-resistant region.6. A semiconductor device manufacturing method comprising:forming a metal layer above a semiconductor substrate;forming a first passivation film that contacts at least a portion of one side surface of the metal layer; andforming a second passivation ...

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME

Semiconductor packages are disclosed. In a semiconductor package, a package board may include a hole. A mold layer may cover an upper portion of the package board and extend through the hole to cover at least a portion of a bottom surface of the package board. Each of the sidewalls of a lower mold portion may have a symmetrical structure with respect to the hole penetrating the package board, such that a warpage phenomenon of the semiconductor package may be reduced. 1. A semiconductor package comprising:a package board including at least one hole;at least one semiconductor chip mounted on the package board by a flip chip bonding method;a mold layer having an upper mold portion covering the at least one semiconductor chip and the package board and a lower mold portion connected to the upper mold portion through the hole, the lower mold portion covering at least a portion of a bottom surface of the package board; andlower solder balls disposed on the bottom surface of the package board, wherein the lower solder balls are not covered by the lower mold portion, andwherein a plurality of outermost sidewalls of the lower mold portion are disposed at a substantially equal distance from a center of the hole.2. The semiconductor package of claim 1 , wherein each of the plurality of outermost sidewalls of the lower mold portion are disposed at an equal distance from corresponding sidewalls of the package board.3. The semiconductor package of claim 1 , wherein the lower mold portion comprises:a center pattern overlapped by the hole;at least one edge pattern spaced apart from the center pattern with at least one of the lower solder balls disposed therebetween; anda plurality of connection patterns connecting the center pattern to the edge pattern, wherein each of said connection patterns is disposed between adjacent ones of the lower solder balls.4. The semiconductor package of claim 3 , wherein the center pattern has a circular or polygonal shape having a width equal to or ...

TOP CORNER ROUNDING OF DAMASCENE WIRE FOR INSULATOR CRACK SUPPRESSION

A structure and method for fabricating the structure that provides a metal wire having a first height at an upper surface. An insulating material surrounding said metal wire is etched to a second height below said first height of said upper surface. The metal wire from said upper surface, after etching said insulating material, is planarized to remove sufficient material from a lateral edge portion of said metal wire such that a height of said lateral edge portion is equivalent to said second height of said insulating material surrounding said metal wire. 1. A structure comprising:a metal wire having a first height at a central portion, a second height at a first distal edge less than said first height, and a radius defined from said second height at said first distal edge to said first height at said central portion; andan insulating material surrounding said metal wire to said second height at said first distal edge of said metal wire,said first height of said metal wire extending above said second height of said first distal edge and said insulating material.2. The structure according to claim 1 , said metal wire comprising a non-planar damascene metal wire.3. The structure according to claim 2 , said non-planar metal wire comprising Cu.4. The structure according to claim 1 , said insulating material comprising an oxide material.5. The structure according to claim 4 , said oxide material comprising SiO.6. The structure according to claim 1 , a coefficient of thermal expansion of said metal wire being greater than 10 times a coefficient of thermal expansion of said insulating material.7. The structure according to claim 1 , said metal wire having a second distal edge equal to said second height and a second radius defined from said second height at said second distal edge to said first height at said central portion.8. A structure comprising:a non-planar damascene metal wire having a first height at a central portion, a second height at a first distal edge less ...

SEMICONDUCTOR DEVICE

The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented. 1. (canceled)2. A semiconductor device comprising:an interlayer insulating film having a specific dielectric constant of 3 or less;a seal ring formed within said interlayer insulating film in the vicinity of an edge of a semiconductor chip so as to surround a circuit formation region of said semiconductor chip; anda plurality of conductive members formed within said interlayer insulating film between a dicing cut surface of said semiconductor chip and said seal ring, whereinsaid conductive members are arranged along a plurality of columns in the plan view in such a manner that said conductive members form a zigzag arrangement where said conductive members that are arranged in adjacent columns are arranged alternately.3. The semiconductor device according to claim 2 , wherein said conductive members include a plurality of dummy vias.4. The semiconductor device according to claim 3 , wherein: a first interlayer insulating film having a specific dielectric constant of 3 or less; and', 'a second interlayer insulating film formed on said first interlayer insulating film and having a specific dielectric constant of 3 or less,, 'said interlayer insulating film includes a first dummy metal formed within said first interlayer insulating film; and', 'a second dummy metal formed ...

SEMICONDUCTOR SUBSTRATE HAVING CRACK PREVENTING STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Disclosed herein is a semiconductor substrate having a crack preventing structure, the semiconductor substrate including: a plurality of wiring layers and a plurality of insulating layers sequentially stacked on a device divided into integrated circuit device areas and a cutting area separating the device areas from each other; opening parts formed to spatially separate the insulating layers in the device areas and the insulating layers in the cutting area from each other; and chamfering parts formed at outer sides of the insulating layers in the device areas contacting the opening parts, wherein the plurality of wiring layers are formed between the insulating layers in the cutting area and the device. 1. A semiconductor substrate having a crack preventing structure , the semiconductor substrate comprising:a plurality of wiring layers and a plurality of insulating layers sequentially stacked on a device divided into integrated circuit device areas and a cutting area separating the device areas from each other;opening parts formed to spatially separate the insulating layers in the device areas and the insulating layers in the cutting area from each other; andchamfering parts formed at outer sides of the insulating layers in the device areas contacting the opening parts,wherein the plurality of wiring layers are formed between the insulating layers in the cutting area and the device.2. The semiconductor substrate according to claim 1 , wherein the opening parts are formed at sides of the insulating layers in the device areas and sides of the insulating layers in the cutting area so as to have a minimum interval of 400 μm or less.3. The semiconductor substrate according to claim 2 , wherein the opening parts are formed in a closed loop form in which they enclose a circumference of the device area claim 2 , when viewed in a plane.4. The semiconductor substrate according to claim 1 , further comprising a wiring layer and an insulating layer stacked in the cutting area in ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a semiconductor substrate, an insulator film that is arranged above the semiconductor substrate, a first passivation film that is arranged above the insulator film, a second passivation film that is arranged above the first passivation film, a stress relaxation layer that is arranged above the second passivation film, an organic coated film that is arranged above the stress relaxation layer, and a resin layer that is arranged above the organic coated film, wherein a Young's modulus of the stress relaxation layer is smaller than a Young's modulus of the organic coated film, and is smaller than a Young's modulus of the second passivation film. 1. A semiconductor device comprising:a semiconductor substrate;an insulator film that is arranged above the semiconductor substrate;a first passivation film that is arranged above the insulator film;a second passivation film that is arranged above the first passivation film;a stress relaxation layer that is arranged above the second passivation film;an organic coated film that is arranged above the stress relaxation layer; anda resin layer that is arranged above the organic coated film, whereina Young's modulus of the stress relaxation layer is smaller than a Young's modulus of the organic coated film, and is smaller than a Young's modulus of the second passivation film.2. The semiconductor device according to claim 1 , whereinan adhesiveness between the organic coated film and the resin layer is higher than an adhesiveness between the second passivation film and the resin layer.3. The semiconductor device according to claim 1 , whereinthe first passivation film is semi-conductive.4. The semiconductor device according to claim 1 , further comprising a peripheral withstand voltage region claim 1 , whereinthe first passivation film is located in the peripheral withstand voltage region.5. The semiconductor device according to claim 1 , whereinthe organic coated film contains polyamide.6. The ...

SEMICONDUCTOR CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

Disclosed herein are a semiconductor chip package and a manufacturing method thereof. The manufacturing method of the semiconductor chip package includes: a) mounting a semiconductor chip on a printed circuit board (PCB); b) inserting a warpage suppressing reinforcement member into an inner ceiling of a mold manufactured in order to package the PCB having the semiconductor chip mounted thereon; c) combining the mold having the warpage suppressing reinforcement member inserted into the ceiling thereof with the upper surface of the PCB so as to surround the PCB having the semiconductor chip mounted thereon; d) injection-molding and filling a molding material in the mold, and hardening the molding material by applying heat, and e) hardening the molding material and then removing the mold to complete the semiconductor chip package. 1. A semiconductor chip package comprising:a printed circuit board (PCB) forming a base of the package;a semiconductor chip mounted on the PCB;a molding part molding the entire upper surface of the PCB including the semiconductor chip to protect the semiconductor chip from external environment; anda warpage suppressing reinforcement member bonded to an upper surface of the molding part and suppressing warpage of the package generated due to a difference in a thermal expansion coefficient among the PCB, the semiconductor chip, and a molding material at the time of hardening the molding material of the molding part.2. The semiconductor chip package according to claim 1 , wherein the molding material of the molding part is a thermosetting resin.3. The semiconductor chip package according to claim 2 , wherein the thermosetting resin is any one of an epoxy resin claim 2 , a phenol resin claim 2 , a urea resin claim 2 , a melamine resin claim 2 , an unsaturated polyester resin claim 2 , a polyurethane resin claim 2 , and a polyimide resin.4. The semiconductor chip package according to claim 1 , wherein the warpage suppressing reinforcement member ...

Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP

A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;depositing an encapsulant over the semiconductor die;forming a recess in the encapsulant;forming an interconnect structure over the semiconductor die; andremoving a first portion of the encapsulant.2. The method of claim 1 , wherein forming the recess further includes removing a second portion of the encapsulant while leaving the first portion of the encapsulant.3. The method of claim 1 , further including:disposing a support structure within the recess prior to forming the interconnect structure; andremoving the support structure after forming the interconnect structure.4. The method of claim 1 , further including forming the recess over the first semiconductor die and outside a footprint of the semiconductor die.5. The method of claim 1 , further including:providing a second semiconductor die; andforming the recess over the first and second semiconductor die.6. The method of claim 1 , further including disposing a support member ...

DEVICE SUBSTRATE AND FABRICATION METHOD THEREOF

A fabricating method of a device substrate including the following procedures is provided. First, a substrate is provided and a patterned structure is formed on the substrate, wherein the patterned structure includes a plurality of openings. Then, a protective layer is formed on the patterned structure, wherein the protective layer does not fully fill the openings of the patterned structure such that a gap is existed between the protective layer and the patterned structure. Later, a device layer is formed on the protective layer. 1. A method for fabricating a device substrate , the method comprising:providing a substrate;forming a patterned structure on the substrate, and the patterned structure comprising a plurality of openings;forming a protective layer on the patterned structure, wherein the protective layer does not completely fill the plurality of openings of the patterned structure for the protective layer and the patterned structure to comprise air gaps there-between; andforming a device layer on the protective layer.2. The method of claim 1 , wherein an aspect ratio of the plurality of openings of the patterned structure is greater than 1.3. The method of claim 1 , wherein the step of forming the protective layer comprises performing a plasma enhanced chemical vapor deposition method claim 1 , and the plasma enhanced chemical vapor deposition method is performed at a gas flow of 200 sccm to 1000 sccm claim 1 , a radio frequency power of about 2000 watts to 4000 watts claim 1 , and a deposition temperature between about 170° C. to 400° C.4. The method of claim 1 , wherein the step of forming the patterned structure comprises:performing a patterning process on the substrate to provide a surface of the substrate with the patterned structure.5. The method of claim 1 , wherein the step of forming the patterning structure comprises:forming a material layer on the substrate; andperforming a patterning process on the material layer to provide the material with the ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface. 1. A semiconductor device comprising;a semiconductor chip having a passivation film on part of a front surface thereof which is a functional surface;a stress relieving layer having an upper surface and a side surface provided on the passivation film;a sealing resin layer provided on the stress relieving layer for sealing the front surface of the semiconductor chip, the sealing resin layer extending to a side surface of the stress relieving layer; anda rewiring provided on the upper surface of the stress relieving layer, the rewiring having a side surface positioned inside of the stress relieving layer such that the upper surface of the stress relieving layer is partly exposed;wherein the sealing resin layer is in direct contact with the semiconductor chip without the passivation film and in contact with the upper surface of the stress relieving layer, andthe sealing resin layer entirely covers the stress relieving layer, the passivation film and the rewiring.2. The semiconductor device according to claim 1 , further comprising a metal ball disposed on the sealing resin layer.3. The semiconductor device according to claim 1 , wherein the semiconductor chip includes a semiconductor substrate of silicon.4. The semiconductor device according to claim 1 , wherein the semiconductor chip has a rectangular shape as seen in plan.5. The semiconductor device according to claim 1 , wherein the passivation film contains at least one of silicon oxide and silicon nitride.6. The semiconductor device according to claim 1 , wherein the passivation film has a pad opening to expose an electrode pad.7. The semiconductor device according to claim 6 , wherein the pad opening exposes a part ...

Semiconductor Device with Protective Structure Around Semiconductor Die for Localized Planarization of Insulating Layer

A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die. 1. A semiconductor device , comprising:a semiconductor die;a conductive layer formed over a surface of the semiconductor die;a protective pattern formed over the surface of the semiconductor die and separated from the conductive layer; anda first insulating layer formed over the surface of the semiconductor die, wherein the protective pattern maintains the first insulating layer between the conductive layer and protective pattern.2. The semiconductor device of claim 1 , further including an exposed portion of the conductive layer claim 1 , wherein the protective pattern reduces erosion of the first insulating layer adjacent to the conductive layer.3. The semiconductor device of claim 1 , wherein the protective pattern includes a metal layer.4. The semiconductor device of claim 1 , wherein the protective pattern is segmented.5. The semiconductor device of claim 1 , further including an encapsulant formed over the semiconductor die.6. The semiconductor device of claim 1 , further including a second insulating layer formed over the surface of the semiconductor die with an opening to the ...

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a semiconductor chip mounted on the substrate, a plate-like member that is fixed on the semiconductor chip and has a thermal expansion coefficient different from that of the substrate, and a first adhesive that is provided between the substrate and the plate-like member, the first adhesive being connected to the plate-like member and separated from the substrate, or being separated from the plate-like member and connected to the substrate. 1. A semiconductor device comprising:a substrate;a semiconductor chip mounted on the substrate;a plate-like member that is fixed on the semiconductor chip and has a thermal expansion coefficient different from that of the substrate; anda first adhesive that is provided between the substrate and the plate-like member, the first adhesive being connected to the plate-like member and separated from the substrate, or being separated from the plate-like member and connected to the substrate.2. The semiconductor device according to claim 1 , wherein the first adhesive is separated from the substrate or the plate-like member at a first temperature.3. The semiconductor device according to claim 1 , wherein the first adhesive is separated from the substrate or the plate-like member by a current flow through the first adhesive.4. The semiconductor device according to claim 1 , wherein the first adhesive includes a first surface which faces the substrate and a second surface which faces the plate-like member claim 1 , and an area of the first surface is different from an area of the second surface.5. The semiconductor device according to claim 1 , wherein a first roughness of a part of the substrate which faces the first adhesive is different from a second roughness of a part of the plate-like member which faces the first adhesive.6. The semiconductor device according to claim 5 , wherein a second roughness is larger than the second roughness claim 5 , and the first adhesive is separated from the ...

SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF

A semiconductor package is provided, which includes: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top surface of the interposer; a redistribution layer formed on the encapsulant and the top surface of the interposer; and at least a semiconductor element disposed on the redistribution layer. The top surface of the interposer is flush with a surface of the encapsulant so as for the redistribution layer to have a planar surface for disposing the semiconductor element, thereby preventing warpage of the interposer and improving the reliability of electrical connection between the redistribution layer and the semiconductor element. 1. A semiconductor package , comprising:a carrier;at least an interposer having opposite first and second surfaces and disposed on the carrier through the first surface thereof;an encapsulant formed on the carrier for encapsulating the interposer, wherein the second surface of the interposer is exposed from the encapsulant;a redistribution layer formed on the second surface of the interposer and the encapsulant and electrically connected to the interposer; andat least a semiconductor element disposed on and electrically connected to the redistribution layer.2. The package of claim 1 , wherein the carrier is a circuit board or a packaging substrate.3. The package of claim 1 , wherein the interposer is a substrate body made of a silicon-containing material.4. The package of claim 1 , further comprising a plurality of conductive through holes penetrating the first and second surfaces of the interposer and electrically connected to the redistribution layer.5. The package of claim 4 , wherein the conductive through holes are further electrically connected to the carrier.6. The package of claim 5 , further comprising at least a circuit layer formed on the first surface of the interposer for electrically connecting the conductive through holes and the ...

DICING TAPE-INTEGRATED WAFER BACK SURFACE PROTECTIVE FILM

The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device. 1. A dicing tape-integrated wafer back surface protective film comprising:a dicing tape comprising a base material and a pressure-sensitive adhesive layer formed on the base material; anda wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape,wherein the wafer back surface protective film is colored,wherein said colored wafer back surface protective film has an elastic modulus at 23° C. of 1 GPa or more, andwherein said colored wafer back surface protective film has a ratio of weight decrease of 1% by weight or less after heating at a temperature of 250° C. for 1 hour.2. The dicing tape-integrated wafer back surface protective film according to claim 1 , wherein said colored wafer back surface protective film has a laser marking ability.3. The dicing tape-integrated wafer back surface protective film according to claim 1 , which is used for a flip chip-mounted semiconductor device.4. A process for producing a semiconductor device using a dicing tape-integrated wafer back surface protective film claim 1 , said process comprising steps of:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'attaching a workpiece onto said colored wafer back surface protective film of the dicing tape-integrated wafer back surface protective film according to ,'}dicing the workpiece to form a chip-shaped workpiece,peeling the chip-shaped ...

SEMICONDUCTOR UNIT AND METHOD FOR MANUFACTURING THE SAME

A semiconductor unit includes a base, an insulating substrate bonded to the base, a conductive plate made of a metal of poor solderability, a semiconductor device mounted to the insulating substrate through the conductive plate, and a metal plate interposed between the conductive plate and the semiconductor device and made of a metal of good solderability as compared to the metal used for the conductive plate. The base, the insulating substrate, the conductive plate and the metal plate are brazed together, and the semiconductor device is soldered to the metal plate. 1. A semiconductor unit , comprising:a base;an insulating substrate bonded to the base;a conductive plate made of a metal of poor solderability;a semiconductor device mounted to the insulating substrate through the conductive plate; anda metal plate interposed between the conductive plate and the semiconductor device and made of a metal of good solderability as compared to the metal used for the conductive plate,wherein the base, the insulating substrate, the conductive plate and the metal plate are brazed together, and the semiconductor device is soldered to the metal plate.2. The semiconductor unit of claim 1 , wherein the metal plate has a solder holding portion where the semiconductor device is bonded.3. The semiconductor unit of claim 2 , wherein part of an oxide layer formed on the metal plate during the brazing is removed to form a recess that serves as the solder holding portion.4. The semiconductor unit of claim 1 , wherein the metal plate is disposed only on the part of the conductive plate where the semiconductor device is mounted.5. The semiconductor unit of claim 1 , further comprising a stress relief member between the base and the insulating substrate.6. The semiconductor unit of claim 1 , wherein the base is a heat sink.7. A method for manufacturing the semiconductor unit of claim 1 , comprising the steps of:brazing the base, the insulating substrate, the conductive plate and the metal ...

SEMICONDUCTOR DEVICE COMPRISING A CRACK STOP STRUCTURE

A semiconductor device may include at least one pad adjacent a top surface of the device, and a metal crack stop structure below the at least one pad. The metal crack structure may have an inner envelope and an outer envelope, and may be configured to be vertically aligned with the at least one pad so that an edge of the at least one pad is between the inner and outer envelopes. 110-. (canceled)11. A semiconductor device comprising:at least one pad exposed at a top surface of the semiconductor device; anda metal crack stop structure below said at least one pad and having an inner envelope and an outer envelope, and configured to be vertically aligned with said at least one pad so that an edge of the at least one pad is between the inner and outer envelopes.12. The semiconductor device according to claim 11 , wherein said at least one pad has a circular shape; and wherein said metal crack stop structure has an annular shape.13. The semiconductor device according to claim 12 , wherein a top of said metal crack stop structure has an inner diameter and an outer diameter that are outside a ±10° downward facing angle from the edge of the at least one pad.14. The semiconductor device according to claim 12 , wherein said metal crack stop structure has an average diameter equal to a diameter of said at least one pad.15. The semiconductor device according to claim 11 , further comprising a dielectric layer having a plurality of electrical connection elements therein and carrying said metal crack stop structure; and wherein said metal crack stop structure and said plurality of electrical connection elements each comprises a same material.16. The semiconductor device according to claim 15 , wherein the material of said metal crack stop structure comprises at least one of copper and aluminum.17. The semiconductor device according to claim 11 , wherein said metal crack stop structure comprises radial walls extending outwardly from a top surface.18. The semiconductor device ...

DIE WARPAGE CONTROL FOR THIN DIE ASSEMBLY

Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating. 1. A method comprising:forming a device having a substrate on a back side and components in front side layers;forming a backside layer over the semiconductor substrate, the layer resisting warpage of the device when the device is heated; andattaching the device to a substrate by heating.2. The method of claim 1 , wherein the substrate has a coefficient of thermal expansion that is different from the front side layers so that the device warps when heated.3. The method of claim 1 , wherein the substrate is a semiconductor substrate and the components comprise microelectronic circuitry.4. The method of claim 1 , further comprising cutting the device from a wafer after forming a layer and before attaching the device.5. The method of claim 1 , wherein forming a layer comprises forming a bonding layer over the substrate to bond to the substrate and forming a metallic layer over the bonding layer to bond to the bonding layer.6. The method of claim 5 , wherein the bonding layer is a silicon nitride.7. The method of claim 5 , wherein the metallic layer is copper.8. The method of claim 5 , wherein the metallic layer is TiW.9. The method of claim 1 , wherein forming a layer comprises forming a layer by sputtering.10. The method of claim 1 , wherein forming a layer comprises forming a pre-stressed layer by applying a plasma to the device during sputtering.11. The method of claim 1 , further comprising attaching the device to a package substrate using a solder reflow oven.12. An apparatus comprising:a die having a substrate on a backside and components in layers on a front side;a layer over the backside to resist warpage of the die when heated; anda ...

DICING TAPE-INTEGRATED WAFER BACK SURFACE PROTECTIVE FILM

The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device. 1. A dicing tape-integrated wafer back surface protective film comprising:a dicing tape comprising a base material and a pressure-sensitive adhesive layer formed on the base material; anda wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape,wherein the wafer back surface protective film is colored with a dye, andwherein said colored wafer back surface protective film has a ratio of weight decrease of 1% by weight or less after heating at a temperature of 250° C. for 1 hour.2. The dicing tape-integrated wafer back surface protective film according to claim 1 , wherein said colored wafer back surface protective film has a laser marking ability.3. The dicing tape-integrated wafer back surface protective film according to claim 1 , which is used for a flip chip-mounted semiconductor device.4. A process for producing a semiconductor device using a dicing tape-integrated wafer back surface protective film claim 1 , said process comprising steps of:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'attaching a workpiece onto said colored wafer back surface protective film of the dicing tape-integrated wafer back surface protective film according to ,'}dicing the workpiece to form a chip-shaped workpiece,peeling the chip-shaped workpiece from the pressure-sensitive adhesive layer of the dicing tape together with said colored ...

SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress. 1. A semiconductor device comprising:a semiconductor layer having a first surface;an electrode provided on the first surface of the semiconductor layer; andan insulating portion including a first layer and a second layer, the first layer covering the electrode on the first surface of the semiconductor layer and having a first internal stress along the first surface, the second layer provided on the first layer and having a second internal stress in a reverse direction of the first internal stress.2. The device according to claim 1 , whereina thickness of the second layer is thinner than a thickness of the first layer, andthe second internal stress is larger than the first internal stress.3. A semiconductor device comprising:a semiconductor layer having a first surface;an electrode provided on the first surface of the semiconductor layer; andan insulating portion having a first layer and a second layer, the first layer covering the electrode on the first surface of the semiconductor layer, the second layer being provided on the first layer,a thickness of the second layer being thinner than a thickness of the first layer, andwarping of the semiconductor layer by the first layer being suppressed by the second layer.4. The device according to claim 1 , wherein a material composition of the second layer is different from a material composition of the first layer.5. The device according to claim ...

Bonded Wafer Edge Protection Scheme

A method includes holding bonded wafers by a wafer holding module. A gap between the bonded wafers along an edge is filled with a protection material. 1. A method , comprising:holding bonded wafers by a wafer holding module; andfilling a gap between the bonded wafers along an edge with a protection material.2. The method of claim 1 , further comprising preheating the bonded wafers.3. The method of claim 2 , wherein the bonded wafers are heated to a temperature ranging from 50° C. to 200° C.4. The method of claim 2 , wherein the bonded wafers are heated by the wafer holding module.5. The method of claim 1 , further comprising performing a thermal process after the gap is filled.6. The method of claim 1 , further comprising rotating the bonded wafers by the wafer holding module.7. The method of claim 1 , wherein the gap is filled by spraying the protection material by a jet nozzle.8. The method of claim 1 , wherein the protection material comprises epoxy or underfill material.9. The method of claim 1 , wherein the protection material comprises carbon claim 1 , silicon claim 1 , and oxygen.10. The method of claim 1 , wherein the protection material comprises carbon claim 1 , alumina claim 1 , and oxygen.11. A wafer assembly claim 1 , comprising:two wafers bonded together; andan edge seal comprising a protective material filled in a gap between the two wafers along an edge.12. The wafer assembly of claim 11 , wherein the protection material comprises epoxy or underfill material.13. The wafer assembly of claim 11 , wherein the protection material comprises carbon claim 11 , silicon claim 11 , and oxygen.14. The wafer assembly of claim 11 , wherein the protection material comprises carbon claim 11 , alumina claim 11 , and oxygen.15. The wafer assembly of claim 11 , wherein the gap has a distance up to 4 mm from the edge of the bonded wafers.16. An apparatus claim 11 , comprising:a wafer holding module, wherein the wafer holding module is configured to hold bonded wafers; ...

Wafer edge protection structure

Among other things, one or more wafer edge protection structures and techniques for forming such wafer edge protection structures are provided. A substrate of a semiconductor wafer comprises an edge, such as a beveled wafer edge portion, that is susceptible to Epi growth which results in undesirable particle contamination of the semiconductor wafer. Accordingly, a wafer edge protection structure is formed over the beveled wafer edge portion. The wafer edge protection structure comprises an Epi growth resistant material, such as an amorphous material, a non-crystalline material, oxide, or other material. In this way, the wafer edge protection structure mitigates Epi growth on the beveled wafer edge portion, where the Epi growth increases a likelihood of particle contamination from cracking or peeling of an Epi film resulting from the Epi growth. The wafer edge protection structure thus mitigates at least some contamination of the wafer.

SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE

To obtain a semiconductor module that can fix itself onto a fixing object while enabling further miniaturization, in addition to alleviating load applied on a molded resin, a semiconductor module includes: a semiconductor element; a placing frame on which the semiconductor element is placed; a control substrate onto which a control component for controlling the semiconductor element is mounted; and a molded resin in which the semiconductor element, the placing frame, and the control substrate are integrally molded. Fixing bases exposed from the molded resin are provided on the control substrate for fixing the semiconductor module onto a chassis. 1. A semiconductor module comprising:a semiconductor element;a placing frame on which the semiconductor element is placed;a control substrate onto which a control component for controlling the semiconductor element is mounted; anda molded resin in which the semiconductor element, the placing frame, and the control substrate are integrally molded, whereina fixing base exposed from the molded resin is provided on the control substrate for fixing the semiconductor module onto a chassis.2. The semiconductor module according to claim 1 , whereinthe fixing bases are provided in plurality at least on one side and another side of the molded resin and are exposed from the molded resin.3. The semiconductor module according to claim 1 , whereina threaded hole is formed through the fixing base.4. The semiconductor module according to claim 1 , whereinthe semiconductor element is a wide-bandgap semiconductor element.5. The semiconductor module according to claim 1 , whereinthe placing frame is arranged on an opposite surface side of a surface of the control substrate onto which the control component is mounted, whereina solid pattern is formed on the opposite surface of a surface of the control substrate onto which the control component is mounted.6. The semiconductor module according to claim 5 , whereinthe solid pattern is connected to ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a base substrate on which a substrate electrode is arranged, and a semiconductor element which includes a chip electrode electrically connected via solder to the substrate electrode and in which a light absorbing layer is formed on a lower surface side. 1. A semiconductor device comprising:a base substrate on which a substrate electrode is arranged; anda semiconductor element which includes a chip electrode electrically connected via solder to the substrate electrode and in which a light absorbing layer is formed on a lower surface side.2. The semiconductor device according to claim 1 ,wherein a heat diffusing layer which is in contact with the light absorbing layer is formed on a lower surface side of the semiconductor element.3. The semiconductor device according to claim 1 ,wherein a light reflecting layer is formed on an upper surface side of the base substrate.4. The semiconductor device according to claim 3 ,wherein the light reflecting layer is electrically connected to the substrate electrode.5. The semiconductor device according to claim 3 ,wherein a protection layer which is in contact with the light reflecting layer is formed on a lower surface side of the light reflecting layer.6. The semiconductor device according to claim 3 ,wherein the semiconductor element has a void portion in which the light absorbing layer is not formed on the lower surface side, andwherein the light reflecting layer is formed on a portion which is opposed to the void portion, in the upper surface side of the base substrate.7. The semiconductor device according to claim 1 ,wherein the light absorbing layer is formed by including any one of Ti, Ni, Sn, Pt and W.8. The semiconductor device according to claim 2 ,wherein the heat diffusing layer is formed by including any one of Al, Cu, Au and Ag.9. The semiconductor device according to claim 3 ,wherein the light reflecting layer is formed by including any one of Al, Cu, Au and Ag.10. The semiconductor ...

Semiconductor Device and Method of Forming Trench and Disposing Semiconductor Die Over Substrate to Control Outward Flow of Underfill Material

A semiconductor device has a substrate including an opening. A trench is formed over the substrate around the opening. An interconnect structure is formed in the trench. An underfill material is disposed over the interconnect structure. A first semiconductor die is disposed over the underfill material prior to curing the underfill material. An active region of the first semiconductor die is disposed over the opening in the substrate. The trench contains the outward flow of underfill material. Underfill material is blocked from flowing over unintended areas on the surface of substrate, into the opening in the substrate, and over sensors of the first semiconductor die. A second semiconductor die is disposed over the substrate. The trench is formed by a first and second dam or a first insulating layer. A second insulating layer is formed over the first insulating layer. A dam is formed over the second insulating layer.

STRESSED DECOUPLED MICRO-ELECTRO-MECHANICAL SYSTEM SENSOR

A semiconductor device may include a stress decoupling structure to at least partially decouple a first region of the semiconductor device and a second region of the semiconductor device. The stress decoupling structure may include a set of trenches that are substantially perpendicular to a main surface of the semiconductor device. The first region may include a micro-electro-mechanical (MEMS) structure. The semiconductor device may include a sealing element to at least partially seal openings of the stress decoupling structure. 1. A semiconductor device , comprising: wherein the stress decoupling structure includes a set of trenches that are substantially perpendicular to a main surface of the semiconductor device, and', 'wherein the first region includes a micro-electro-mechanical (MEMS) structure; and, 'a stress decoupling structure to at least partially decouple a first region of the semiconductor device and a second region of the semiconductor device,'}a sealing element to at least partially seal openings of the stress decoupling structure.2. The semiconductor device of claim 1 , wherein the stress decoupling structure further includes a cavity that at least partially separates the first region from the second region.3. The semiconductor device of claim 1 , wherein the sealing element includes a cap that at least partially seals the openings of the stress decoupling structure.4. The semiconductor device of claim 3 , wherein the cap includes a stress decoupling structure to decouple the first region and the second region.5. The semiconductor device of claim 3 , wherein the cap is formed from silicon or glass.6. The semiconductor device of claim 3 , wherein the cap is affixed to the first region and the second region using a wafer bonding process.7. The semiconductor device of claim 3 , wherein the cap is formed from an elastic material.8. The semiconductor device of claim 7 , wherein the elastic material at least partially fills the set of trenches of the stress ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM

It is an object of the present invention to provide a semiconductor device which is easily replaceable and a semiconductor system using the semiconductor device. The semiconductor device of the present invention includes a semiconductor chip, a cooler that cools the semiconductor chip, a housing that houses the semiconductor chip and the cooler, a transfer resin that seals the semiconductor chip and the cooler inside the housing, electrodes connected to the semiconductor chip, and a joining pipe attached to the cooler, the joining pipe letting in and out a flow of a refrigerant from and to the cooler. The electrodes and the joining pipe are formed to protrude from the same surface of the housing in substantially the same direction. 1. A semiconductor device , comprising:a semiconductor chip;a cooler that cools said semiconductor chip;a housing that houses said semiconductor chip and said cooler;a sealing resin that seals said semiconductor chip and said cooler inside said housing;an electrode connected to said semiconductor chip; anda joining pipe attached to said cooler, said joining pipe letting in and out a flow of a refrigerant from and to said cooler,wherein said electrode and said joining pipe are formed to protrude from the same surface of said housing in substantially the same direction.2. The semiconductor device according to claim 1 , wherein said joining pipe of said cooler is formed of a resin or a surface thereof is coated with a resin layer.3. The semiconductor device according to claim 1 , further comprising a communication cable for communication of a control signal between an external source and said semiconductor chip claim 1 ,wherein said communication cable is formed to protrude from a surface facing the same surface of said housing, from which said electrode and said joining pipe protrude.4. The semiconductor device according to which is configured to be removable from a semiconductor container formed of a connection electrode and a cooling ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

The present invention is to provide a semiconductor device in which an insulating material layer contains no reinforced fibers such as a glass cloth or a nonwoven cloth and which enables miniaturization of metal thin-film wiring layers, a reduction in the diameter of metal vias, and a reduction in interlayer thickness. The semiconductor device includes an insulating material layer including one or more semiconductor elements sealed with an insulating material containing no reinforced fibers, a plurality of metal thin-film wiring layers, metal vias that electrically connect the metal thin-film wiring layers together and electrodes of the semiconductor elements and the metal thin-film wiring layers together, and a warpage adjustment layer arranged on one principal surface of the insulating material layer to offset warpage of the insulating material layer to reduce warpage of the semiconductor device. 1. A semiconductor device including:an insulating material layer including one or more semiconductor elements sealed with an insulating material containing no reinforced fibers, a plurality of metal thin-film wiring layers, and metal vias that electrically connect the metal thin-film wiring layers together and electrodes of the semiconductor elements and the metal thin-film wiring layers together; anda warpage adjustment layer arranged on one principal surface of the insulating material layer to offset warpage of the insulating material layer to reduce warpage of the semiconductor device.2. The semiconductor device according to claim 1 , in which the semiconductor elements are mounted claim 1 , via an adhesive claim 1 , on a back side of the surface of the insulating material layer on which an external terminal is mounted claim 1 , the semiconductor elements being mounted such that element circuit surfaces of the semiconductor elements face upward.3. The semiconductor device according to claim 1 , in which the warpage adjustment layer is a layer made of an insulating ...

SEMICONDUCTOR PACKAGE

Disclosed is a semiconductor package including a base film that has a first surface and a second surface opposite to the first surface, a plurality of input/output lines on the first surface of the base film, a semiconductor chip disposed on the first surface of the base film and connected to the input/output lines and including a central portion and end portions on opposite sides of the central portion, and a heat radiation pattern on the second surface of the base film The heat radiation pattern corresponds to the semiconductor chip and has a plurality of openings that correspond to the end portions of the semiconductor chip and that vertically overlap the end portions of the semiconductor chip. 1. A semiconductor package , comprising:a base film having a first surface and a second surface opposite to the first surface;a plurality of input/output lines on the first surface of the base film;a semiconductor chip disposed on the first surface of the base film and connected to the input/output lines, the semiconductor chip including a central portion and end portions on opposite sides of the central portion; anda heat radiation pattern on the second surface of the base film, the heat radiation pattern corresponding to the semiconductor chip and having a plurality of openings that correspond to the end portions of the semiconductor chip and that vertically overlap the end portions of the semiconductor chip.2. The semiconductor package of claim 1 , wherein the semiconductor chip includes a plurality of first chip pads on the central portion and a plurality of second chip pads on the end portions claim 1 ,wherein the second chip pads of the semiconductor chip vertically overlap the openings of the heat radiation pattern.3. The semiconductor package of claim 2 , further comprising a plurality of connection terminals between the input/output lines and the first and second chip pads.4. The semiconductor package of claim 1 , first and second edges opposite to each other; and ...

SEMICONDUCTOR PACKAGE

Disclosed is a semiconductor package comprising a package substrate, a substrate on the package substrate, a first semiconductor chip mounted on the substrate, and a stiffener structure on the package substrate and having a hole. The stiffener structure is laterally spaced apart from the substrate. The hole penetrates a top surface of the stiffener structure and a bottom surface of the stiffener structure. When viewed in plan, the hole overlaps a corner region of the package substrate. 1. A semiconductor package , comprising:a package substrate;a substrate on the package substrate;a first semiconductor chip mounted on the substrate; anda stiffener structure on the package substrate, the stiffener structure having a hole,wherein the stiffener structure is laterally spaced apart from the substrate,wherein the hole penetrates a top surface of the stiffener structure and a bottom surface of the stiffener structure, andwherein, when viewed in plan, the hole overlaps a corner region of the package substrate.2. The semiconductor package of claim 1 , further comprising:an adhesive layer between the package substrate and the stiffener structure,wherein the adhesive layer extends into the hole of the stiffener structure and covers at least a portion of a sidewall of the hole.3. The semiconductor package of claim 2 , wherein the adhesive layer has a stiffness less than a stiffness of the stiffener structure.4. The semiconductor package of claim 3 , wherein a Young's modulus of the adhesive layer is about 1/3000 to about 1/100 of a Young's modulus of the stiffener structure.5. The semiconductor package of claim 4 ,wherein the Young's modulus of the adhesive layer ranges from about 0.01 GPa to about 1 GPa, andwherein the Young's modulus of the stiffener structure ranges from about 100 GPa to about 300 GPa.6. The semiconductor package of claim 1 , further comprising:a plurality of second semiconductor chips stacked on the substrate,wherein the first semiconductor chip is of a ...

PACKAGE STRUCTURES HAVING UNDERFILLS

A package structure includes a lower substrate, substrate connection terminals on the lower substrate, a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate, first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals, and a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in a plan view. 1. A package structure , comprising:a lower substrate;substrate connection terminals on the lower substrate;a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate;first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, respectively, as viewed in a plan view, and covering at least one of the substrate connection terminals; anda second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in the plan view.2. The package structure as claimed in claim 1 , wherein each of the first underfills includes:an inner portion overlapping the semiconductor package in a vertical direction, the inner portion covering the substrate connection terminals; andan outer portion not overlapping the semiconductor package in the vertical direction.3. The package structure as claimed in claim 2 , wherein the outer portion covers side surfaces of the package substrate and the first encapsulant.4. The package structure as claimed in claim 3 , wherein a height of a portion of the semiconductor package covered by the ...

Semiconductor device

A semiconductor device includes a supporting plate including a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; and a semiconductor unit fixed to the first surface. The semiconductor unit includes an insulating plate, a circuit plate fixed to a front surface of the insulating plate, a semiconductor chip fixed to the circuit plate, and a protruding metal block fixed to a rear surface of the insulating plate and penetrating through the through hole to extend to the second surface.

SEMICONDUCTOR PACKAGES HAVING RESIDUAL STRESS LAYERS AND METHODS OF FABRICATING THE SAME

A semiconductor package is provided. The semiconductor includes a lower package and an upper package stacked on the lower package. The lower package includes a package substrate, a semiconductor chip, a mold layer and a residential stress layer. The package substrate has upper and lower surfaces. The semiconductor chip is disposed on the upper surface of the package substrate. The mold layer encapsulates the semiconductor chip. The residual stress layer is disposed on the semiconductor chip. The residual stress layer includes a plastically deformed surface. The residual stress layer has a residual stress to counterbalance warpage of the lower package. 1. A semiconductor package comprising a lower package and an upper package stacked on the lower package , wherein the lower package includes:a package substrate having upper and lower surfaces;a semiconductor chip disposed on the upper surface of the package substrate;a mold layer encapsulating the semiconductor chip; anda residual stress layer disposed on the semiconductor chip, wherein the residual stress layer includes a plastically deformed surface,wherein the residual stress layer has a residual stress to counterbalance warpage of the lower package.2. The semiconductor package of claim 1 , wherein the semiconductor chip includes an exposed surface not covered by the mold layer claim 1 , and the residual stress layer is in contact with the exposed surface of the semiconductor chip.3. The semiconductor package of claim 2 , wherein the plastically deformed surface of the residual stress includes a plurality of first dents.4. The semiconductor package of claim 3 , wherein the plastically deformed surface of the residual stress layer has first roughness claim 3 , and an upper surface of the mold layer has second roughness less than the first roughness.5. The semiconductor package of claim 3 , wherein the upper surface of the mold layer includes a plurality of second dents.6. The semiconductor package of claim 5 , ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

The method includes the steps of: providing a lead frame, including providing a concaved part in an upper face of a joint part of a die-pad-support lead of a lead frame for setting down a die pad and a tie-bar; bonding a semiconductor chip to a first principal face of the die pad via an adhesive-member layer; then, setting the lead frame between first and second molding dies having first and second cavities respectively so that the first and second cavities are opposed to each other, and the second principal face of the die pad faces toward the second cavity; and forming first and second resin sealed bodies on the sides of the first and second principal faces of the die pad respectively by resin sealing with the first and second molding dies clamping the tie-bar and a part of the lead frame surrounding the tie-bar. 1. A semiconductor device , comprising:a die pad; a first surface,', 'a second surface opposite to said first surface,', 'a first end face located between said first surface and said second surface in cross-section view,', 'a second end face located between said first surface and said second surface in cross-section view, and also located closer to said die pad than said first end face, and', 'a third surface located between said first surface and said second surface in cross-section view, and also located between said first end face and said second end face in cross-section view;, 'a die-pad-support lead supporting said die pad, said die-pad-support lead includinga semiconductor chip mounted over said die pad, said semiconductor chip including a plurality of bonding pads;a plurality of leads electrically connected with said bonding pads via a plurality of wires, respectively; anda resin-sealing-body sealing said semiconductor chip, said wires and a part of each of said leads,wherein said first end face of said die-pad-support lead is exposed from said resin-sealing-body, andwherein said first surface, said second surface, said second end face and said ...

Electronic assembly having multiple substrate segments

An electronic assembly (100) includes a mechanical carrier (102), a plurality of integrated circuits (104A, 104B) disposed on the mechanical carrier, a fan out package (108) disposed on the plurality of integrated circuits, a plurality of singulated substrates (112A, 112B) disposed on the fan out package, a plurality of electronic components (114A, 114B) disposed on the plurality of singulated substrates, and at least one stiffness ring (116A, 116B, 116C) disposed on the plurality of singulated substrates. A method for constructing an electronic assembly includes identifying a group of known good singulated substrates, joining the group of known good singulated substrates into a substrate panel, attaching at least one bridge to the substrate panel that electrically couples at least two of the known good singulated substrates, and mounting a plurality of electronic components onto the substrate panel, each electronic component of the plurality of electronic components corresponding to a respective known good singulated substrate.

MICRO-ELECTRONIC PACKAGE WITH BARRIER STRUCTURE

A structure including a barrier is described. In embodiments, a micro-electronic component may have a first face and a second face, wherein the second face includes interconnect structures and is opposite the first face. A fill material, such as a capillary underfill material (CUF), may fill a gap between the micro-electronic component and the substrate and substantially surround the interconnect structures. In embodiments, a barrier structure may be located on the surface of the substrate and along a perimeter or outside perimeter of the micro-electronic component, wherein a height of the barrier structure exceeds a height of the fill material in at least a portion of an open region of the substrate to confine the fill material to an area bordered by the barrier structure. 1. An apparatus , comprising:a micro-electronic component having a first face and a second face, wherein the second face includes interconnect structures and is opposite the first face;a fill material that fills a gap between the micro-electronic component and a substrate and substantially surrounds the interconnect structures; anda barrier structure located on a surface of the substrate and along a perimeter of the micro-electronic component, wherein a height of the barrier structure exceeds a height of the fill material in at least a portion of an open region of the substrate to confine the fill material to an area bordered by the barrier structure.2. The apparatus of claim 1 , wherein the barrier structure is formed from a different material than from that of the substrate and the barrier structure is located along an outside perimeter of the micro-electronic component.3. The apparatus of claim 1 , wherein the barrier structure comprises an epoxy material including one or more of amines claim 1 , anhydrides claim 1 , urethanes claim 1 , cyanos claim 1 , cationic epoxies claim 1 , and/or an acrylate material.4. The apparatus of claim 1 , wherein the fill material comprises a capillary underfill ...

Semiconductor module

A semiconductor module includes: a dielectric film that has a first surface and a second surface opposed to the first surface; a plurality of circuit parts mounted on the first surface; an electrode layer that is disposed on the second surface and includes a plurality of electrode portions to be electrically connected to the plurality of circuit parts, at least a part of the plurality of electrode portions including a base that is long in one axis direction; a rigid member that is disposed on the first surface, includes, at least one shaft portion, and faces the base with the dielectric layer sandwiched therebetween, the at least one shaft axis extending along the one axis direction; and a sealing layer that is provided on the first surface and covers the plurality of circuit parts and the rigid member.

MODULE

A module with a high degree of design flexibility and excellent radiation characteristics is provided. The module includes a multilayer wiring substrate, mounting components mounted on an upper surface of the multilayer wiring substrate, a sealing resin layer sealing the mounting components, a plurality of depressions in an upper surface of the sealing resin layer, and radiators set in the depressions. The mounting components are components whose amounts of heat generated are smaller than those of the mounting components. A gap between a bottom of each of the depressions arranged in a region overlapping each of the mounting components and the mounting component is shorter than a gap between the bottom of each of the depressions arranged in a region overlapping each of the mounting components and the mounting component as seen from a direction perpendicular to the upper surface of the multilayer wiring substrate. 1. A module comprising:a wiring substrate;a first component and a second component mounted on a principal surface of the wiring substrate;a sealing resin layer having a contact surface in contact with the wiring substrate and an opposed surface opposed to the contact surface, the sealing resin layer sealing the first component and the second component;at least two depressions at the opposed surface of the sealing resin layer; anda radiating member set in each of the depressions, each radiating member including at least one radiator element,wherein an amount of heat generated from the second component is smaller than an amount of heat generated from the first component,the radiating member has a first region overlapping the first component and a second region overlapping the second component as seen from a direction perpendicular to the principal surface of the wiring substrate,the depressions reach neither the first component nor the second component, anda distance from a bottom of the depression in the first region to the first component is shorter than a ...

SEMICONDUCTOR DEVICE, CHIP-SHAPED SEMICONDUCTOR ELEMENT, ELECTRONIC DEVICE PROVIDED WITH SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a wiring board and a chip-shaped semiconductor element flip-chip mounted on the wiring board, in which a plurality of solder bumps and a plurality of protrusions including an insulating material are provided on a surface of the chip-shaped semiconductor element on a side facing the wiring board, and the chip-shaped semiconductor element is arranged so as to face the wiring board via an underfilling material in a state in which the underfilling material having a characteristic that viscosity decreases with an increase in temperature is applied to the wiring board and then subjected to reflow treatment to be flip-chip mounted on the wiring board. 1. A semiconductor device comprising:a wiring board; anda chip-shaped semiconductor element flip-chip mounted on the wiring board,wherein a plurality of solder bumps and a plurality of protrusions including an insulating material are provided on a surface of the chip-shaped semiconductor element on a side facing the wiring board, andthe chip-shaped semiconductor element is arranged so as to face the wiring board via an underfilling material in a state in which the underfilling material having a characteristic that viscosity decreases with an increase in temperature is applied to the wiring board and then subjected to reflow treatment to be flip-chip mounted on the wiring board.2. The semiconductor device according to claim 1 ,wherein the chip-shaped semiconductor element includes a protrusion formed so that a tip end does not reach the wiring board in a state in which the chip-shaped semiconductor element is flip-chip mounted.3. The semiconductor device according to claim 1 ,wherein the chip-shaped semiconductor element is mounted in a state positioned with respect to the wiring board by fusion of a solder bump provided on the wiring board with the solder bumps provided on the chip-shaped semiconductor element by the reflow treatment.4. The semiconductor device according to claim 1 ,wherein the ...

SEMICONDUCTOR STRUCTURE

A semiconductor structure includes a first die, a molding at least partially surrounding the first die, a via extended through the molding, a second die disposed over the molding, a connector dispose between the second die and the via, and an underfill at least partially surrounding the connector. The first die includes a first surface and a second surface opposite to the first surface. The second die includes a third surface facing the first die, a fourth surface opposite to the third surface, and a sidewall between the third surface and the fourth surface. The connector is in contact with the third surface of the second die and the via. The second die is electrically connected to the via. The underfill covers a portion of the sidewall of the second die and a portion of the second surface of the first die. 1. A semiconductor structure , comprising:a first die including a first surface and a second surface opposite to the first surface;a molding at least partially surrounding the first die;a via extended through the molding;a second die disposed over the molding and including a third surface facing the first die, a fourth surface opposite to the third surface and a sidewall between the third surface and the fourth surface;a connector disposed between the second die and the via and being in contact with the third surface of the second die and the via; andan underfill at least partially surrounding the connector,wherein the second die is electrically connected to the via, and the underfill covers a portion of the sidewall of the second die and a portion of the second surface of the first die.2. The semiconductor structure of claim 1 , wherein the second die overlaps a portion of the first die.3. The semiconductor structure of claim 1 , wherein the underfill is in contact with a portion of the molding.4. The semiconductor structure of claim 1 , wherein the first die is disposed adjacent to the via.5. The semiconductor structure of claim 1 , further comprising an ...

STIFFENER-INTEGRATED INTERCONNECT BYPASSES FOR CHIP-PACKAGE APPARATUS AND METHODS OF ASSEMBLING SAME

A stiffener includes an integrated cable-header recess that couples a semiconductor package substrate flexible cable. The flexible cable connects to a device on a board without using interconnections that are arrayed through the board. A semiconductive die is coupled to the semiconductor package substrate and flexible cable through the cable-header recess. 1. A semiconductor package frame stiffener , comprising:a frame stiffener body including a top surface and a die-side ledge that is opposite the top surface, further including a die-side interconnect surface that is opposite the top surface, and further including a land-side interconnect surface that is parallel planar with the die-side interconnect surface;a through hole that communicates from the top surface to the die-side ledge, and from the top surface to the die-side interconnect surface:an integrated cable-header recess that communicates to the top surface, wherein the integrated cable-header recess is adjacent to the die-side interconnect surface and adjacent to the land-side interconnect surface; anda through-frame-stiffener interconnect (TFSI) that communicates from the land-side interconnect surface, through the frame stiffener and into the integrated cable-header recess.2. The semiconductor package frame stiffener of claim 1 , further including a cable header electrically coupled to the TFSI.3. The semiconductor package frame stiffener of claim 1 , further including:a cable header electrically coupled to the TFSI; anda flexible cable coupled to the cable header.4. The semiconductor package frame stiffener of claim 1 , further including:a cable header electrically coupled to the TFSI;a flexible cable coupled to the cable header;a passive device opposite the integrated cable-header recess, wherein the passive device is coupled to a folded redistribution layer at the land-side interconnect surface;a semiconductor package substrate including a die side and a land side, wherein the die side is in contact ...

PACKAGE STIFFENING MAGNETIC CORE

An apparatus may include a substrate, one or more integrated circuit dies on the substrate, and a stiffener affixed to one or more sides of the substrate. One or more sections of the stiffener may include a magnetic material. The apparatus may further include an inductive circuit element comprising one or more conductive structures wrapped around the magnetic material. 1. An apparatus comprising:a substrate;one or more integrated circuit dies on the substrate;a stiffener affixed to one or more sides of the substrate, wherein one or more sections of the stiffener comprises a magnetic material; andan inductive circuit element comprising one or more conductive structures wrapped around the magnetic material.2. The apparatus of claim 1 , wherein the stiffener comprises:a plurality of intersecting segments, wherein an individual segment of the stiffener is along a corresponding side of the one or more sides of the substrate.3. The apparatus of claim 1 , wherein the stiffener comprises:a first segment adjacent to a first side of the substrate;a second segment adjacent to a second side of the substrate;a third segment adjacent to a third side of the substrate; anda fourth segment adjacent to a fourth side of the substrate,wherein an individual segment of the stiffener has a length that is at least 50% of a length of a corresponding side of the substrate.4. The apparatus of claim 3 , wherein:the first segment intersects with, and is substantially perpendicular to, the second and fourth segments;the second segment intersects with, and is substantially perpendicular to, the third segment; andthe third segment intersects with, and is substantially perpendicular to, the fourth segment.5. The apparatus of claim 3 , wherein:the first, second, third, and fourth segments form an unbroken closed loop along the perimeter of the substrate, surrounding the one or more integrated circuit dies.6. The apparatus of claim 1 , wherein:the inductive circuit element is a first inductive ...

Supporting InFO Packages to Reduce Warpage

A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die. 18.-. (canceled)9. A method comprising:encapsulating a first device die and a second device die in an encapsulating material;forming redistribution lines over the first device die and the second device die;forming electrical connectors overlying and electrically coupling to the first device die and the second device die through the redistribution lines;performing a singulation on the encapsulating material, wherein the first device die and the second device die are sawed into a package; andattaching the package to a dummy support die, wherein the dummy support die extends beyond edges of the package in each of four lateral directions.1011-. (canceled)12. The method of further comprising bonding a bridge die to the package claim 9 , wherein the bridge die is on an opposite side of the redistribution lines than the first device die and the second device die.13. The method of claim 12 , wherein the dummy support die is bonded to have a first portion overlapped by the first device die claim 12 , and a second portion overlapped by the second device die.1420.-. (canceled)21. A method comprising: a first device die;', 'a second device die;', 'an encapsulating material encapsulating the first device die and the second device die therein, wherein opposite sides of the adhesive film are in physical contact with the encapsulating material and the blank die; and', 'a plurality of redistribution lines over and ...

Dummy Dies for Reducing Warpage in Packages

A method includes placing a plurality of functional dies over a carrier, placing a plurality of dummy dies over the carrier, encapsulating the plurality of functional dies and the plurality of dummy dies in an encapsulant, and forming redistribution lines over and interconnecting the plurality of functional dies. The redistribution lines, the plurality of functional dies, the plurality of dummy dies, and the encapsulant in combination form a reconstructed wafer. The plurality of functional dies are in a center region of the reconstructed wafer, and the plurality of dummy dies are in a peripheral region of the reconstructed wafer, with the peripheral region encircling the center region. The reconstructed wafer is de-bonded from the carrier. The reconstructed wafer is bonded to a package component selected from the group consisting essentially of an interposer, a package substrate, a printed circuit board, a thermal module, and combinations thereof. 1. A method comprising:placing a plurality of functional dies over a carrier;placing a plurality of dummy dies over the carrier;encapsulating the plurality of functional dies and the plurality of dummy dies in an encapsulant;forming redistribution lines over and interconnecting the plurality of functional dies, wherein the redistribution lines, the plurality of functional dies, the plurality of dummy dies, and the encapsulant in combination form a reconstructed wafer, wherein the plurality of functional dies are in a center region of the reconstructed wafer, and the plurality of dummy dies are in a peripheral region of the reconstructed wafer, with the peripheral region encircling the center region;de-bonding the reconstructed wafer from the carrier; andbonding the reconstructed wafer to a package component selected from the group consisting essentially of an interposer, a package substrate, a printed circuit board, a thermal module, and combinations thereof.2. The method of claim 1 , wherein the plurality of dummy dies ...

STIFFENER BUILD-UP LAYER PACKAGE

To maintain the integrity of electrical contacts at a build-up layer of a chip package, while reducing electrical interference caused by a chip connected to the build-up layer, the chip package can include a stiffener formed from an electrically conductive material and positioned between the chip and the build-up layer. The chip can electrically connect to the build-up layer through electrical connections that extend through the stiffener. Compared with a stiffener that extends only over a single chip of the chip package, the present stiffener can help prevent warpage or other mechanical deformities that can degrade electrical contacts away from the chip at the build-up layer. Compared with a stiffener that extends only over an area away from the chip, such as a peripheral area, the present stiffener can help reduce electrical interference in an area of the build-up layer near the chip. 1. A chip package , comprising:a stiffener having a first side and a second side opposite the first side;a first electrical component positioned on the first side of the stiffener; anda build-up layer positioned on the second side of the stiffener and electrically connected to the first electrical component through the stiffener;wherein the stiffener is formed from an electrically conductive material that at least partially shields the build-up layer from at least one of electromagnetic interference or radio-frequency interference from the first electrical component.2. The chip package of claim 1 , wherein the first electrical component is electrically connected to the build-up layer via a plurality of electrical connections that extend through the stiffener from the first side of the stiffener to the second side of the stiffener.3. The chip package of claim 2 , wherein each electrical connection in the plurality of electrical connections includes a vertically-extending member formed from electrically conducting material and laterally surrounded by a dielectric material claim 2 , the ...

MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

A die bonding process for assembling a semiconductor device includes the steps of applying a sintered-silver-use paste to each of a plurality of first regions on an upper surface of a chip mounting part, drying the sintered-silver-use paste and applying a silver paste to a second region located between/among the respective first regions. Further, the process includes the step of mounting a semiconductor chip onto the chip mounting part in such a manner that a rear surface of the semiconductor chip faces an upper surface of the chip mounting part with the sintered-silver-use paste and the silver paste being interposed. After mounting the chip, part of each of first, second, third and fourth corners of a principal surface of the semiconductor chip is located in each of the first regions. 1. A manufacturing method for semiconductor device comprising the steps of:(a) providing a semiconductor chip having a first front surface and a first rear surface which is located on the opposite side of the first front surface;(b) providing a lead frame which includes a chip mounting part having a second front surface and a second rear surface which is located on the opposite side of the second front surface;(c) after the step (a) and the step (b), applying a first bonding material to each of a plurality of first regions on the second front surface of the chip mounting part;(d) after the step (c), drying the first bonding material;(e) after the step (d), applying a second bonding material to a second region which is located between/among the respective first regions;(f) after the step (e), mounting the semiconductor chip over the chip mounting part in such a manner that the first rear surface of the semiconductor chip faces the second front surface of the chip mounting part with the first bonding material and the second bonding material being interposed; and(g) after the step (f), applying heat and pressure to the semiconductor chip and thereby bonding the first rear surface of the ...

Enhanced Thermal Transfer in a Semiconductor Structure

A semiconductor device having enhanced thermal transfer includes at least one die, including a device layer in which one or more functional circuit elements are formed and a substrate supporting the device layer, and a support structure. The die is disposed on the support structure using at least one connection structure coupled between the device layer and the support structure. A back surface of the substrate is textured so as to increase a surface area of the back surface to thereby enhance thermal transfer between the substrate and an external environment. 1. A method for fabricating a semiconductor device have enhanced thermal transfer , the method comprising:providing at least one die including a device layer formed on a front side of a semiconductor substrate, the device layer including one or more functional circuit elements formed therein;attaching the die to a support structure such that the front side of the die is disposed on at least a portion of the support structure; andtexturing a back side of the substrate so as to increase a surface area of the back side of the substrate thereby enhancing thermal transfer between the substrate and an external environment.2. The method of claim 1 , wherein the die is attached to the support structure using at least one connection structure coupled between the device layer and the support structure.3. The method of claim 1 , wherein texturing the back side of the substrate comprises at least one of forming periodic structures in or on the back side of the substrate and forming non-periodic structures in or on the back side of the substrate.4. The method of claim 1 , wherein texturing comprises forming a plurality of trenches in the back side of the substrate claim 1 , a portion of the substrate remaining between adjacent trenches forming periodic fingered structures claim 1 , a surface area of the back side of the substrate being controlled as a function of an aspect ratio of the fingered structures.5. The method of ...

STIFFENER FOR A PACKAGE SUBSTRATE

Stiffener technology for electronic device packages is disclosed. A stiffener for a package substrate can include a top portion configured to be affixed to a top surface of a package substrate. The stiffener for a package substrate can also include a lateral portion extending from the top portion and configured to be disposed about a lateral side of the package substrate. An electronic device package and associated systems and methods are also disclosed. 1. An electronic device package , comprising:a package substrate having a top surface and a lateral side;an electronic component operably coupled to the top surface of the package substrate; and a top portion affixed to the top surface of the package substrate, and', 'a lateral portion extending from the top portion and disposed about the lateral side of the package substrate., 'a stiffener having'}2. The electronic device package of claim 1 , wherein the lateral portion of the stiffener is in contact with the lateral side of the package substrate.3. The electronic device package of claim 1 , wherein the lateral portion of the stiffener extends at least partially about the lateral side between the top surface and a bottom surface of the package substrate.4. The electronic device package of claim 1 , wherein the lateral portion of the stiffener extends about the lateral side from the top surface to a bottom surface of the package substrate.5. The electronic device package of claim 1 , wherein the lateral portion of the stiffener is disposed about greater than or equal to 20% of an area of the lateral side of the package substrate.6. The electronic device package of claim 1 , wherein the top portion of the stiffener is affixed to the top surface of the package substrate with an adhesive.7. The electronic device package of claim 6 , wherein the adhesive is an electrically non-conductive adhesive.8. The electronic device package of claim 6 , wherein the adhesive is an electrically conductive adhesive.9. The electronic ...

SUBSTRATE WARPAGE CONTROL USING EXTERNAL FRAME STIFFENER

A chip package and methods of manufacturing the same are disclosed. In particular, a chip package comprising a ball grid array is disclosed in which the chip package includes a package substrate supporting the ball grid array and in which the chip package further includes a warpage control frame that helps to minimize or mitigate warpage of the chip package. 1. A semiconductor package , comprising:a substrate having a first major surface and an opposing second major surface;a semiconductor chip connected to the first major surface of the substrate via a plurality of electrically-conductive bumps;a lid connected to the first major surface of the substrate, wherein a connection between the lid and the first major surface of the substrate at least partially surrounds the chip and the plurality of electrically-conductive bumps;a ball grid array established on the second major surface of the substrate; anda warpage control frame established on the second major surface of the substrate, the warpage control frame comprising a perimeter section that at least partially surrounds the ball grid array.2. The semiconductor package of claim 1 , wherein the perimeter section of the warpage control frame is continuous and completely surrounds the ball grid array.3. The semiconductor package of claim 2 , wherein the perimeter section of the warpage control frame is connected to the second major surface via an adhesive and wherein the perimeter section is established at outer extremes of the substrate.4. The semiconductor package of claim 3 , wherein the lid completely surrounds the chip and is attached to the substrate in substantial opposition to the perimeter section of the warpage control frame.5. The semiconductor package of claim 4 , wherein the lid hermetically seals the chip claim 4 , wherein the lid comprises at least one of copper claim 4 , tin claim 4 , steel claim 4 , aluminum claim 4 , silver claim 4 , and gold claim 4 , and wherein the lid is in thermal communication ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a chip stack comprising semiconductor chips vertically stacked on a substrate in a first direction perpendicular to a top surface of the substrate, pillars between the substrate and the chip stack, an adhesive layer on a bottom surface of a lowermost semiconductor chip of the semiconductor chips, a first lower protective layer between the adhesive layer and the pillars, a second lower protective layer between the first lower protective layer and the adhesive layer, and a mold layer covering the chip stack and filling a space between the pillars. A thickness of the second lower protective layer in the first direction is greater than a thickness of the adhesive layer in the first direction. 1. A semiconductor package comprising:a chip stack comprising semiconductor chips vertically stacked on a substrate in a first direction perpendicular to a top surface of the substrate;pillars between the substrate and the chip stack;an adhesive layer on a bottom surface of a lowermost semiconductor chip of the semiconductor chips;a first lower protective layer between the adhesive layer and the pillars;a second lower protective layer between the first lower protective layer and the adhesive layer; anda mold layer covering the chip stack and filling a space between the pillars,wherein a thickness of the second lower protective layer in the first direction is greater than a thickness of the adhesive layer in the first direction.2. The semiconductor package of claim 1 , wherein the second lower protective layer has a tensile strength higher than that of the first lower protective layer.3. The semiconductor package of claim 1 , wherein the thickness of the second lower protective layer in the first direction ranges from 3 times to 6 times the thickness of the adhesive layer in the first direction.4. The semiconductor package of claim 1 , wherein the thickness of the second lower protective layer in the first direction is less than a thickness of the ...

System and Method for a High Retention Module Interface

A device includes a substrate, a first antenna connection, and a first retention mechanism. The substrate has atop surface and a bottom surface. The first antenna connection is mounted directly to the top surface of the substrate, and is configured to connect with a first antenna. The first retention mechanism is connected at a first location of the bottom surface of the substrate to provide support for the substrate at the first antenna connection when the first antenna connection is connected to the first antenna. The first location of the first retention mechanism is selected to be directly below the first antenna connection.

SEMICONDUCTOR DEVICE STRUCTURES AND METHODS FOR MANUFACTURING THE SAME

Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a die and a stiffener. The substrate has an upper surface. The die is disposed on the upper surface of the substrate. The stiffener is disposed on the upper surface of the substrate and surrounds the die. The stiffener has a first upper surface adjacent to the die, a second upper surface far from the die and a lateral surface extending from the first upper surface to the second upper surface. A first distance between the first upper surface of the stiffener and the upper surface of the substrate is less than a second distance between the second upper surface of the stiffener and the upper surface of the substrate. 1. A semiconductor device structure , comprising:a substrate having an upper surface;a die disposed on the upper surface of the substrate; anda stiffener disposed on the upper surface of the substrate and surrounds the die, wherein the stiffener comprises a first portion, a second portion on the first portion and a third portion extending from a lateral surface of the first portion toward the die, and the third portion has a lateral surface substantially perpendicular to the lateral surface of the first portion.2. The semiconductor device structure of claim 1 , wherein the stiffener has a first upper surface adjacent to the die claim 1 , a second upper surface farther from the die than the first upper surface claim 1 , and a lateral surface extending from the first upper surface to the second upper surface claim 1 , and an angle constituted by the first upper surface and the lateral surface of the stiffener ranges from about 90° to about 115°.3. The semiconductor device structure of claim 1 , wherein the stiffener has a first upper surface adjacent to the die claim 1 , a second upper surface farther from the die than the first upper surface claim 1 , and a lateral surface extending from the first upper surface to the ...

GUARD RING METHOD FOR SEMICONDUCTOR DEVICES

A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells. 1. A method for fabricating an integrated circuit , comprising:fabricating at least one semiconductor device; andfabricating a seal ring surrounding the at least one semiconductor device in a plurality of metal layers, the seal ring comprising first seal ring cells, second seal ring cells, and corner cells, the corner cells located at respective corners of the seal ring, wherein a sequence of abutting first seal ring cells and second seal ring cells extends an entire distance between at least two adjacent corner cells,each of the first seal ring cells including an inner portion having metal vias in each of a plurality of metal layers, said first cells not coupled to ground, and each of the second seal ring cells including an inner portion having a ground connection in at least one of the plurality of metal layers, and metal vias in each of the plurality of metal layers excluding the at least one of the plurality of metal layers having the ground connection.2. The method as in claim 1 , wherein said first seal ring cells and said second seal ring cells are of a same dimension and include substantially identical outer portions.3. The method as in claim 1 , wherein said fabricating includes forming said first and second seal ring cells ...

ARRAY SUBSTRATE AND ORGANIC LIGHT-EMITTING DISPLAY INCLUDING THE SAME

An array substrate includes a substrate, a barrier layer disposed on the substrate, a buffer layer disposed on the barrier layer, a first insulating layer disposed on the buffer layer, a second insulating layer disposed on the first insulating layer, a plurality of wiring patterns disposed between the first insulating layer and the second insulating layer and/or on the second insulating layer. In addition, the wiring patterns are separated from each other, and extend toward a side of the substrate. The array substrate further includes a recess pattern disposed adjacent the wiring patterns and recessed from a top surface of the second insulating layer to expose at least part of a top surface of the substrate, and an organic insulating layer disposed on the second insulating layer and exposing at least part of a portion of the top surface of the substrate which is exposed by the recess pattern. 1. An array substrate comprising:a substrate;an insulating layer disposed on the substrate;a plurality of wiring patterns disposed on the insulating layer, and wherein the wiring patterns are separated from each other, and extend toward a side of the substrate; anda recess pattern disposed adjacent to the plurality of wiring patterns.2. The array substrate of claim 1 , wherein the recess pattern exposes at least part of the top surface of the substrate.3. The array substrate of claim 2 , further comprising an organic layer disposed on the insulating layer.4. The array substrate of claim 3 , wherein the organic layer exposes at least part of a portion of the top surface of the substrate which is exposed by the recess pattern.5. The array substrate of claim 3 , wherein the organic insulating layer covers the portion of the top surface of the substrate which is exposed by the recess pattern.6. The array substrate of claim 1 , further comprising a plurality of recess pattern and the plurality of recess patterns are disposed between plurality of the wiring patterns.7. The array ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first main surface side of the first semiconductor substrate and a first main surface side of the second semiconductor substrate being bonded to each other; and a warpage correction layer which is formed on at least one or more selected from the first main surface side of the first semiconductor substrate, the first main surface side of the second semiconductor substrate, a second main surface side of the first semiconductor substrate, and a second main surface side of the second semiconductor substrate. 110-. (canceled)11. A semiconductor device comprising:a first semiconductor substrate including a pixel region in which a pixel array is formed;a first wiring layer formed on a first main surface side of the first semiconductor substrate;a first material layer between the first wiring layer and a bonding layer;a second semiconductor substrate;a second wiring layer formed on a first main surface side of the second semiconductor substrate;a second material layer between the second wiring layer and the bonding layer,wherein the first main surface side of the first semiconductor substrate and the first main surface side of the second semiconductor substrate are bonded to face each other;the first and second material layers include a silicon compound; andthe bonding layer includes a silicon compound.12. The semiconductor device according to claim 11 , wherein the first and second material layers include one or more of SiN claim 11 , SiO claim 11 , SiO2 claim 11 , SiOC claim 11 , SiC claim 11 , SiCN claim 11 , FSG claim 11 , and FTEOS13. The semiconductor device according to claim 11 , wherein the bonding layer includes one or more of SiO claim 11 , SiN claim 11 , SiON claim 11 , SiOC claim 11 , and SiOCH.14. The semiconductor device according to claim 11 , further comprising a first planarizing layer formed between the first wiring layer and the bonding layer.15. The ...

Semiconductor Structure and Method of Fabricating the Same

A semiconductor structure and a method of fabricating the same. The semiconductor structure comprises: a layer element, one or more supporting elements disposed on a first surface of the layer element, and one or more anchoring elements disposed within the layer element and connected to the one or more supporting elements to couple the one or more supporting elements to the layer element to strengthen the layer element. 1. A semiconductor structure , comprising:a layer element;one or more supporting elements disposed on a first surface of the layer element, andone or more anchoring elements disposed within the layer element and connected to the one or more supporting elements to couple the one or more supporting elements to the layer element to strengthen the layer element.2. The semiconductor structure as claimed in claim 1 , wherein a portion of at least one of the one or more anchoring elements is exposed on a second surface of the layer element claim 1 , the second surface being opposite the first surface.3. The semiconductor structure as claimed in claim 2 , further comprising one or more reinforcement elements disposed on at least a portion of the second surface of the layer element claim 2 , wherein the one or more anchoring elements are connected to the one or more reinforcement elements to couple the one or more reinforcement elements to the layer element to further strengthen the layer element.4. The semiconductor structure as claimed in claim 1 , further comprising one or more reinforcement elements disposed on at least a portion of the one or more supporting elements to further strengthen the layer element.5. The semiconductor structure as claimed in claim 1 , wherein the one or more supporting elements comprise a magnetic material.6. The semiconductor structure as claimed in claim 5 , wherein the one or more supporting elements further comprise a coating claim 5 , the coating being disposed over at least a portion of the magnetic material.7. The ...

SEMICONDUCTOR MODULE

A semiconductor module includes a wiring substrate and two semiconductor devices mounted on the wiring substrate. The semiconductor module includes a housing having a rectangular frame body including four side walls. The housing includes a beam that bridges first side walls. A bus bar includes two end portions, upright portions each extending from one of the end portions in the thickness direction of an insulating substrate, bent portions each extending continuously with one of the upright portions, and an extension extending continuously with the bent portions. A section of the extension is embedded in the housing. 1. A semiconductor module comprising:a wiring substrate having a wiring trace arranged on an insulating substrate;a semiconductor device connected to the wiring trace;a plate-shaped bus bar having at least one end portion joined to the wiring trace or the semiconductor device; anda plastic housing having a frame body surrounding the wiring trace and the semiconductor device, the bus bar being integrated with the housing, wherein an upright portion that extends upright from the end portion in a thickness direction of the insulating substrate,', 'a bent portion that extends continuously with the upright portion and bends the bus bar in a direction crossing the thickness direction, and', 'an extension that extends continuously with the bent portion and has a section embedded in the housing, and, 'the bus bar includes'}the housing includes an opening for visual checking at a position corresponding to a joint portion between the end portion of the bus bar and the wiring trace or the semiconductor device.2. The semiconductor module according to claim 1 , wherein the bus bar projects from an end face of the housing that defines the opening to an inner side of the opening.3. The semiconductor module according to claim 1 , wherein the bus bar has a plurality of ends that is joined to the wiring trace or the semiconductor device.4. The semiconductor module ...

DELAMINATION-RESISTANT SEMICONDUCTOR DEVICE AND ASSOCIATED METHOD

A delamination-resistant semiconductor device includes a conductive layer, a semiconductor layer, and a spacer. The conductive layer has a first side opposite a second side. The semiconductor layer is on the first side and defines an aperture therethrough spanned by the conductive layer. The spacer is on the second side and has a top surface, proximate the conductive layer, that defines a blind hole spanned by the conductive layer. A method for preventing delamination of a multilayer structure, includes a step of disposing a first layer on a substrate such that the first layer spans an aperture of the substrate. The method also includes a step of disposing a second layer on the first layer. The second layer has a blind hole adjacent to the first layer such that the first layer spans the blind hole. 1. A delamination-resistant semiconductor device comprising:a conductive layer having a first side opposite a second side;a semiconductor layer on the first side and defining an aperture therethrough spanned by the conductive layer; anda spacer on the second side and having a top surface proximate the conductive layer that defines a blind hole spanned by the conductive layer.2. The delamination-resistant semiconductor device of claim 1 , further comprising a redistribution layer on a surface of the semiconductor layer within the aperture and electrically connected to the conductive layer.3. The delamination-resistant semiconductor device of claim 2 , further comprising a dielectric layer at least partially filling the aperture claim 2 , a region of the redistribution layer being between the semiconductor layer and the dielectric layer.4. The delamination-resistant semiconductor device of claim 1 , further comprising a dielectric layer at least partially filling the aperture.5. The delamination-resistant semiconductor device of claim 1 , the conductive layer including a stack of conductive layers interspersed with dielectric layers.6. The delamination-resistant ...

ELECTRONIC APPARATUS

An electronic apparatus includes: a first metal layer; an electronic component that is provided on the first metal layer; a second metal layer that is provided on the first metal layer and on the electronic component; and an insulating resin that fills a space between the first metal layer and the second metal layer so as to cover the electronic component. The second metal layer includes: a sheet-like electrode pad portion; and a connection portion that is disposed along a peripheral edge of the electrode pad portion, and that protrudes from the electrode pad portion toward the first metal layer so as to electrically connect the second metal layer to the first metal layer. 1. An electronic apparatus comprising:a first metal layer;an electronic component that is provided on the first metal layer;a second metal layer that is provided on the first metal layer and on the electronic component; andan insulating resin that fills a space between the first metal layer and the second metal layer so as to cover the electronic component,wherein the second metal layer comprises:a sheet-like electrode pad portion; anda connection portion that is disposed along a peripheral edge of the electrode pad portion, and that protrudes from the electrode pad portion toward the first metal layer so as to electrically connect the second metal layer to the first metal layer.2. The electronic apparatus according to claim 1 , whereinthe connection portion is higher in height than the electronic component.3. The electronic apparatus according to claim 1 , whereinthe electrode pad portion overlaps with the electronic component in plan view, and has a face exposed from the insulating resin.4. The electronic apparatus according to claim 1 , whereinthe electrode pad portion is formed into a rectangular shape, andthe connection portion is disposed along one side of the electrode pad portion.5. The electronic apparatus according to claim 1 , whereinthe first metal layer comprises:a placement portion ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

In one example, a semiconductor device comprises a substrate comprising a dielectric, a first conductor on a top side of the dielectric, and a second conductor on a bottom side of the dielectric, wherein the dielectric has an aperture, and the first conductor comprises a partial via contacting a pad of the second conductor through the aperture, an electronic device having an interconnect electrically coupled to the first conductor, and an encapsulant on a top side of the substrate contacting a side of the electronic device. Other examples and related methods are also disclosed herein. 1. A semiconductor device , comprising:a substrate comprising a dielectric, a first conductor on a top side of the dielectric, and a second conductor on a bottom side of the dielectric, wherein the dielectric has an aperture, and the first conductor comprises a partial via contacting a pad of the second conductor through the aperture;an electronic device having an interconnect electrically coupled to the first conductor; andan encapsulant on a top side of the substrate contacting a side of the electronic device.2. The semiconductor device of claim 1 , wherein the substrate comprises a third conductor on the top side of the dielectric claim 1 , and a fourth conductor on the bottom side of the dielectric claim 1 , wherein the dielectric has an additional aperture claim 1 , and the third conductor comprises a partial via contacting a pad of the fourth conductor through the additional aperture.3. The semiconductor device of claim 2 , further comprising a trace on the dielectric between the partial via of the first conductor and the partial via of the third conductor.4. The semiconductor device of claim 2 , wherein an end of the partial vial of the first conductor and an end of the partial via of the third conductor are spaced apart by 30 microns or less.5. The semiconductor device of claim 2 , wherein:the first conductor comprises a first trace on the top side of the dielectric and ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first substrate, a second substrate provided on the first substrate, a semiconductor chip provided between the first substrate and the second substrate, solder structures extending between the first substrate and the second substrate and spaced apart from the semiconductor chip, and bumps provided between the semiconductor chip and the second substrate. The solder structures electrically connect the first substrate and the second substrate. 1. A method for manufacturing a semiconductor package , comprising:mounting a semiconductor chip on a first substrate;forming lower solder balls on the first substrate, the lower solder balls spaced apart from the semiconductor chip and electrically connected to the first substrate;forming supporting structures on the first substrate, the supporting structures spaced apart from the semiconductor chip and the lower solder balls;providing a second substrate on the first substrate in such a way that a lower surface of the second substrate faces the semiconductor chip; anddownwardly moving the second substrate toward the first substrate,wherein the supporting structures support the second substrate when the second substrate is downwardly moved.2. The method of claim 1 , wherein the second substrate includes upper solder balls on the lower surface of the second substrate claim 1 , and the second substrate is provided on the first substrate in such a way that the upper solder balls are aligned to the lower solder balls claim 1 , respectively.3. The method of claim 2 , wherein the upper solder balls are electrically connected to the second substrate.4. The method of claim 2 , wherein the downwardly moving the second substrate includes bonding the second substrate to the first substrate by a thermal compression bonding method claim 2 , andwherein the bonding the second substrate to the first substrate includes forming solder structures by bonding the upper solder balls to the lower solder balls.5. The ...

Multi-metal package stiffener

A semiconductor package system includes a semiconductor package including at least one semiconductor device having a first side and a second side and a substrate having a first side and a second side. The second side of the at least one semiconductor device is positioned on the first side of the substrate. At least one stiffener element is provided on the semiconductor package. The at least one stiffener element includes at least two metal elements having different coefficients of thermal expansion joined together.

Electronic module and electronic device

An electronic module includes: a plurality of heat generating members provided over a first surface of a board; a frame joined to the first surface of the board and provided between the plurality of heat generating members that are arranged; and a lid configured to cover the first surface of the board and thermally coupled to each of the plurality of heat generating members, the frame being a grid-shaped frame or a mesh-shaped frame.

SEMICONDUCTOR DEVICE, POWER CONVERTER, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

An object is to provide a technique for reducing process steps, and a stress generated at the peripheral portion of the joint portion between an electrode of a semiconductor element and a lead frame. A semiconductor device includes the following: a semiconductor element disposed on a heat spreader; a lead frame joined to an emitter electrode of the semiconductor element via solder, which is a joining material; a metal film disposed on a surface of the emitter electrode; and an anti-oxidation film disposed on a surface of the metal film. The metal film has a peripheral portion that is entirely exposed from the anti-oxidation film. 1. A semiconductor device comprising:a semiconductor element disposed on a heat spreader;a lead frame joined to an electrode of the semiconductor element via a joining material;a metal film disposed on a surface of the electrode; andan anti-oxidation film disposed on a surface of the metal film,wherein the metal film comprises a peripheral portion that is entirely exposed from the anti-oxidation film.2. The semiconductor device according to claim 1 , wherein the entire peripheral portion of the metal film is oxidized.3. The semiconductor device according to claim 1 , wherein the anti-oxidation film comprises a corner portion whose radius is larger than a radius of a corner portion of the metal film.4. The semiconductor device according to claim 3 , wherein the anti-oxidation film is circular or elliptical in plan view.5. A semiconductor device comprising:a semiconductor element disposed on a heat spreader;a lead frame joined to an electrode of the semiconductor element via a joining material;a metal film disposed on a surface of the electrode;an anti-oxidation film disposed on a surface of the metal film; anda metal wire disposed throughout a peripheral portion of the anti-oxidation film.6. A semiconductor device comprising:a semiconductor element disposed on a heat spreader;a lead frame joined to an electrode of the semiconductor element ...

Supporting InFO Packages to Reduce Warpage

A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die. 1. A package comprising:a first device die;a second device die;a first encapsulating material encapsulating the first device die and the second device die therein;a plurality of redistribution lines over and electrically coupling to the first device die and the second device die;a bridge die over and bonded to the redistribution lines, wherein the bridge die electrically intercouples the first device die and the second device die; anda dummy support die underlying and attached to the first device die and the second device die.2. The package of claim 1 , wherein the bridge die comprises:a first portion overlapping the first device die; anda second portion overlapping the second device die.3. The package of claim 1 , wherein the bridge die comprises a substrate and an interconnect structure on the substrate claim 1 , and the bridge die is free from active devices and passive devices therein.4. The package of further comprising a first die-attach film and a second die-attach film attaching the first device die and the second device die claim 1 , respectively claim 1 , to the dummy support die.5. The package of further comprising a continuous adhesive film comprising:a first portion between and contacting the first die-attach film and the dummy support die; anda second portion between and contacting the second die-attach film and the dummy support die.6. The package of claim 4 , wherein the dummy support ...

FLEXIBLE ELECTRONIC ASSEMBLY FOR PLACEMENT ON A VEHICLE MOTOR ASSEMBLY

Embodiments of the disclosure relate to flexible electronic substrates for placement on an external surface of a vehicle motor assembly. In one embodiment, a motor assembly includes a motor comprising an external surface and one or more electronic assemblies positioned on the external surface of the motor. Each electronic assembly includes a metal substrate disposed on the external surface of the motor, a dielectric layer disposed on the metal substrate, a flexible metal base layer disposed on the dielectric layer, a bonding layer disposed on the flexible metal base layer, and one or more electronic devices disposed on the bonding layer. The bonding layer bonds the one or more electronic devices to the flexible metal base layer. 1. An electronic assembly comprising:a metal substrate directly disposed on a curved surface;a dielectric layer disposed on the metal substrate;a flexible metal base layer disposed on the dielectric layer;a bonding layer disposed on the flexible metal base layer; andone or more electronic devices disposed on the bonding layer, wherein the bonding layer bonds the one or more electronic devices to the flexible metal base layer.2. The electronic assembly of claim 1 , wherein the metal substrate comprises copper claim 1 , nickel claim 1 , aluminum or alloys thereof.3. The electronic assembly of claim 1 , wherein the dielectric layer comprises aluminum oxide claim 1 , aluminum nitride claim 1 , silicon nitride claim 1 , beryllium oxide or silicon carbide.4. The electronic assembly of claim 1 , wherein:the flexible metal base layer comprises a stress buffer layer disposed on the dielectric layer and an encapsulating layer encapsulating the stress buffer layer; anda melting temperature of the encapsulating layer is higher than a melting temperature of the stress buffer layer and a maximum operating temperature of the one or more electronic devices.5. The electronic assembly of claim 4 , wherein the stress buffer layer comprises indium claim 4 , tin ...

Electronic component package

An electronic component package includes: a core including a cavity, a first resin layer, a second resin layer and a reinforcing layer disposed between the first resin layer and the second resin layer; and an electronic component disposed in the cavity, wherein a thickness of the first resin layer is different from a thickness of the second resin layer.

STRUCTURE OF BACKSIDE COPPER METALLIZATION FOR SEMICONDUCTOR DEVICES AND A FABRICATION METHOD THEREOF

An improved structure of backside copper metallization for semiconductor devices and a fabrication method thereof, wherein the improved structure comprises sequentially from top to bottom an active layer, a substrate, a backside metal seed layer, a high-temperature sustaining buffer layer, a backside metal layer and at least one oxidation resistant layer, wherein the backside metal seed layer contains Pd and P, the high-temperature sustaining buffer layer is made of Ni, Ag or Ni alloys, and the backside metal layer is made of Cu. The semiconductor chip using the structure provided by the present invention can sustain high-temperature operations.

INTEGRATED CIRCUIT CHIP FABRICATION LEADFRAME

One example includes a conductive leadframe configured to couple to an integrated circuit (IC) chip die on a contact surface of the IC chip die. The conductive leadframe includes a plurality of chip-pin connections configured to facilitate conductive coupling to bond pads of the IC chip die via conductive lead wires. The conductive leadframe also includes a support beam that extends across the conductive leadframe along the contact surface of the IC chip die to enable support of the IC chip die to the conductive leadframe at a plurality of support locations during testing of the IC associated with the IC chip die. 1. A conductive leadframe configured to couple to an integrated circuit (IC) chip die on a contact surface of the IC chip die , the conductive leadframe comprising:a plurality of chip-pin connections configured to conductively couple to bond pads of the IC chip die via conductive lead wires; anda support beam that extends across the conductive leadframe along the contact surface of the IC chip die to enable support of the IC chip die with respect to the conductive leadframe at a plurality of support locations during testing of the IC associated with the IC chip die.2. The conductive leadframe of claim 1 , wherein the support beam is coupled to one of the plurality of chip-pin connections.3. The conductive leadframe of claim 2 , wherein the respective one of the plurality of chip-pin connections comprises one of the plurality of support locations during testing of the IC.4. The conductive leadframe of claim 1 , wherein the plurality of support locations comprises:a first support location proximal to a first edge of the IC chip die;a second support location proximal to a second edge of the IC chip die that is opposite the first edge; anda third support location proximal to a third edge that extends orthogonally between the first and second edges.5. The conductive leadframe of claim 4 , wherein the third support location is located along one of the plurality ...

SUPPORT FOR LONG CHANNEL LENGTH NANOWIRE TRANSISTORS

A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging. 1. A nanowire device , comprising:a first component formed on a substrate;a second component disposed apart from the first component on the substrate;at least one nanowire configured to connect the first component to the second component; anda plurality of anchor pads formed along a span of the at least one nanowire and configured to support the at least one nanowire along the span to prevent sagging, wherein the plurality of anchor pads are separated by a distance of between about 50 nm to about 300 nm.2. The device as recited in claim 1 , wherein the first component includes a transistor source and the second component include a transistor drain and the at least one nanowire forms a device channel.3. The device as recited in claim 2 , further comprising a gate dielectric and gate conductor formed around the at least one nanowire.4. The device as recited in claim 1 , wherein the at least one nanowire and the plurality of anchor pads include a semiconductor material.5. (canceled)6. (canceled)7. The device as recited in claim 1 , wherein the at least one nanowire is a plurality of parallel nanowires claim 1 , wherein each of the parallel nanowires is supported along the span by each of the plurality of anchor pads.8. The device as recited in claim 1 , wherein each of the anchor pads has a pad width of between about 20 nm and about 50 nm.9. The device as recited in claim 1 , wherein the at least one nanowire includes a plurality of nanowire segments connected by a plurality of anchor pads.10. The device as recited in claim 9 , wherein the plurality of nanowire segments and the plurality of anchor pads form a device ...

Electrical component with a dielectric passivation stack

An electrical component and method for manufacturing the electrical component with a substrate a conductor stack having multiple layers and including at least one electrically conductive path. The conductor stack mounted to the substrate with a dielectric passivation stack encasing at least a portion of the conductor stack.

STRETCHABLE SEMICONDUCTOR PACKAGES AND SEMICONDUCTOR DEVICES INCLUDING THE SAME

A semiconductor package includes an extendible molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member. First surfaces of the connectors are exposed at a surface of the molding member, and second surfaces of the connectors are coupled to the chip. 1. A semiconductor package comprising:a molding member comprised of an extendible material, wherein the molding member includes a first part having a warped shape, a second part extending from one end of the first part to be flat, and a third part extending from the other end of the first part to be flat;a chip embedded in the molding member to have a warped shape; andconnectors disposed in the molding member,wherein first surfaces of the connectors are exposed at a surface of the molding member and second surfaces of the connectors are coupled to the chip.2. The semiconductor package of claim 1 , wherein the molding member includes a polymer-based material.3. The semiconductor package of claim 2 , wherein the polymer-based material includes a polydimethylsiloxane (PDMS) material claim 2 , a poly-ethylene-terephthalate (PET) material claim 2 , a polyimide (PI) material claim 2 , or a silicone material.4. The semiconductor package of claim 1 , wherein the first part of the molding member warps so that a central portion of the first part of the molding member is located at a higher level than both ends of the first part of the molding member.5. The semiconductor package of claim 4 , wherein the chip is disposed in the first part of the molding member.6. The semiconductor package of claim 5 , wherein the chip includes contact pads disposed in a first surface of the chip.7. The semiconductor package of claim 6 , wherein the chip is disposed so that the first surface of the chip faces downward.8. The semiconductor package of claim 7 , wherein both ends of the chip bend in a downward direction to be located at a lower level than a central portion of the chip.9. ...