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13-01-2022 дата публикации

METHOD FOR FORMING CONDUCTIVE LAYER, AND CONDUCTIVE STRUCTURE AND FORMING METHOD THEREFOR

Номер: US20220013479A1

Автор: Hsieh Ming-Teng

Принадлежит: CHANGXIN MEMORY TECHNOLOGIES, INC.

A method for forming the conductive layer includes: providing a first conductive film and a solution with a conductive material; coating a surface of the first conductive film with the solution, before performing the coating, a temperature of the first conductive film being lower than an evaporation temperature or a sublimation temperature of the solution; and in a process step of performing the coating or after performing the coating, heating the first conductive film, such that the temperature of the first conductive film is higher than or equal to the evaporation temperature or the sublimation temperature of the solution, and forming a second conductive film covering the surface of the first conductive film, wherein the second conductive film including the conductive material. 1. A method for forming a conductive layer , comprising:providing a first conductive film and a solution with a conductive material;coating a surface of the first conductive film with the solution, and prior to said coating, a temperature of the first conductive film being lower than an evaporation temperature or a sublimation temperature of the solution; andin a process step of performing the coating or after performing the coating, heating the first conductive film, such that the temperature of the first conductive film is higher than or equal to the evaporation temperature or the sublimation temperature of the solution, and forming a second conductive film covering the surface of the first conductive film, the second conductive film comprising the conductive material.2. The method for forming a conductive layer of claim 1 , wherein the first conductive film has a damaged surface; the damaged surface is coated with the solution; and after said coating claim 1 , the second conductive film covering the damaged surface is formed.3. The method for forming a conductive layer of claim 1 , wherein in a process step of heating the first conductive film claim 1 , the temperature of the first ...

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Номер записи: 89

07-01-2016 дата публикации

INTEGRATED CIRCUIT ASSEMBLY AND INTEGRATED CIRCUIT PACKAGING STRUCTURE

Номер: US20160005674A1

Автор: WU Ya Tzu, Yang Yu Lin

Принадлежит:

An integrated circuit packaging structure includes a chip, an electrical bump, a heat dissipation bump, a lead frame, and a sealant. The chip includes an active surface and an electronic component that is formed by using a semiconductor process. The electrical bump is electrically connected to the electronic component through the active surface. The heat dissipation bump is connected to the active surface. The lead frame is electrically connected to the electrical bump. The sealant covers the chip, the lead frame, and the electrical bump, wherein the heat dissipation bump and a part of the lead frame are exposed without being covered. The height of the heat dissipation bump relative to the active surface is unequal to that of the electrical bump relative to the active surface. 1. An integrated circuit assembly , comprising:a chip, including an active surface and an electronic component that is formed by using a semiconductor process;a heat conductor, formed by using the semiconductor process, and protruding on the active surface;an electrical conductor, formed by using the semiconductor process, and protruding on the active surface;an electrical bump, electrically connected to the active surface via the electrical conductor, so as to be electrically connected to the electronic component through the active surface; anda heat dissipation bump, connected to the active surface via the heat conductor, so as to be connected to the active surface;wherein, through the height difference formed by the heat conductor and the electrical conductor, the height of the heat dissipation bump relative to the active surface is higher than that of the electrical bump relative to the active surface.2. (canceled)3. (canceled)4. (canceled)5. The integrated circuit assembly as claimed in claim 1 , wherein the volume of the heat dissipation bump is greater than that of the electrical bump.6. (canceled)7. The integrated circuit assembly as claimed in claim 1 , wherein materials of the heat ...

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Номер записи: 90

07-01-2016 дата публикации

Methods and Apparatus of Packaging Semiconductor Devices

Номер: US20160005704A1

Автор: Chen Hsien-Wei, Huang Ru-Ying, Kuo Yian-Liang, Sheu Ming-Song, TSAI Tsung-Fu, TU Chia-Wei

Принадлежит:

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface. 1. A semiconductor device comprising:a contact pad over a substrate;a redistribution layer in electrical connection with the contact pad;a passivation layer over the redistribution layer;an underbump metallization extending through the passivation layer to be in physical contact with a surface of the redistribution layer facing away from the substrate; anda solder ball in physical contact with the underbump metallization, wherein the solder ball is laterally separated from the redistribution layer in a direction parallel with a major surface of the substrate.2. The semiconductor device of claim 1 , wherein the underbump metallization comprises a reflowable material along a top surface of the underbump metallization.3. The semiconductor device of claim 1 , wherein the underbump metallization extends through the passivation layer at two or more locations.4. The semiconductor device of claim 1 , wherein the redistribution layer comprises a plurality of sub-layers.5. The semiconductor device of claim 1 , wherein the underbump metallization comprises a plurality of sub-layers.6. The semiconductor device of claim 1 , wherein the underbump metallization comprises a plurality of connection branches.7. The semiconductor device of claim 1 , wherein a sidewall of ...

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Номер записи: 91

07-01-2016 дата публикации

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Номер: US20160005707A1

Автор: Kwon Yong-hwan, Lee Chan-Ho, PARK MYEONG-SOON

Принадлежит:

A semiconductor package includes a package board that includes an circuit pattern and a plurality of contact pads electrically connected to the circuit pattern; a semiconductor chip having a plurality of chip pads; and a bump structure including a plurality of connecting bumps electrically connected with the semiconductor chip and the circuit pattern and a plurality of gap adjusting bumps bonded to the semiconductor chip and shaped into a slender bar between the semiconductor chip and the package board, the gap adjusting bumps spacing the semiconductor chip from the package board such that a gap space, S, is maintained between the package board and the semiconductor chip. A method of fabrication and a memory unit are disclosed. 1. A semiconductor package comprising:a package board comprising an circuit pattern and a plurality of contact pads electrically connected to the circuit pattern;a semiconductor chip having a plurality of chip pads; anda bump structure comprising a plurality of connecting bumps electrically connected with the semiconductor chip and the circuit pattern and a plurality of gap adjusting bumps bonded to the semiconductor chip and shaped into a slender bar between the semiconductor chip and the package board, the gap adjusting bumps spacing the semiconductor chip from the package board such that a gap space, S, is maintained between the package board and the semiconductor chip.2. The semiconductor package of claim 1 , wherein the semiconductor chip includes a passivation pattern covering an active face thereof and through which the chip pads are exposed and the plurality of gap adjusting bumps comprises at least one slender body connected to the passivation layer and a sidewall solder member arranged on a sidewall of the slender body.3. The semiconductor package of claim 2 , wherein the sidewall of the slender body is shaped into a concave face that is directed to a center of the slender body and is at least partially covered with the sidewall ...

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Номер записи: 92

04-01-2018 дата публикации

INTERFACE STRUCTURES FOR PACKAGED CIRCUITRY AND METHOD OF PROVIDING SAME

Номер: US20180005972A1

Автор: Hossain MD Altaf, LEE Cliff C.

Принадлежит:

Techniques and mechanisms for determining an accessibility of circuit functionality via interface structures of a microelectronic device. In an embodiment, a packaged microelectronic device includes a substrate having interconnect structures formed therein. The interconnect structures variously couple one or more integrated circuit (IC) dies of the packaged microelectronic device to respective conductors (or “contact lands”) at a side of the substrate. Access to some functionality of the one or more IC dies via certain ones the contact lands—the access during an operational mode of the packaged microelectronic device—may be selectively disabled based on testing which evaluates performance characteristics of the packaged microelectronic device. In another embodiment, some of the contact lands are covered with an insulator material to prevent deposition of solder on such contact lands. 1. A microelectronic device comprising:a substrate including a first side and a second side;contact lands disposed at the first side, the contact lands including first contact lands and second contact lands;one or more integrated circuit (IC) dies coupled to the substrate via the second side, wherein each of the contact lands is coupled to a respective interconnect structure extending at least partially through the substrate;a package mold disposed on the second side and the one or more IC dies; 'any solder ball of the device is disposed on a contact land other than the each contact land to prevent a respective functionality of a circuit component.', 'solder balls each disposed on a respective one of the second contact lands, wherein, for each contact land of the first contact lands2. The microelectronic device of claim 1 , wherein claim 1 , of the first contact lands and the second contact lands claim 1 , only the second contact lands have respective solder balls disposed thereon.3. The microelectronic device of claim 2 , wherein respective surfaces of one or more of the first contact ...

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Номер записи: 93

07-01-2021 дата публикации

SEMICONDUCTOR PACKAGE HAVING MAGNETIC INTERCONNECTS AND RELATED METHODS

Номер: US20210005566A1

Автор: GAMBINO Jeffrey Peter, LONG Thomas F.

Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Implementations of semiconductor packages may include a first die including a plurality of contact pads, a second die including a plurality of contact pads, a plurality of solder interconnects bonding the plurality of contact pads of the first die to the plurality of contact pads of the second die, and a plurality of magnetic particles each coated in an oxide included in each of the plurality of solder interconnects. 1. A semiconductor package comprising:a first die comprising a plurality of contact pads;a second die comprising a plurality of contact pads;a plurality of solder interconnects bonding the plurality of contact pads of the first die to the plurality of contact pads of the second die; anda plurality of magnetic particles each coated in an oxide comprised in each of the plurality of solder interconnects.2. The package of claim 1 , wherein the plurality of magnetic particles comprise Ni claim 1 , Co claim 1 , Fe claim 1 , FeO claim 1 , or any combination thereof.3. The package of claim 1 , wherein a pitch of the plurality of solder interconnects is less than 100 micrometers.4. The package of claim 1 , wherein the plurality of contact pads of the first die are bonded to the plurality of contact pads of the second die through an application of a magnetic field to the plurality of solder interconnects.5. The package of claim 1 , wherein the plurality of magnetic particles is more heavily concentrated near the second die than the first die.6. The package of claim 1 , wherein the oxide comprises silicon dioxide.7. A method of forming a semiconductor package comprising:forming a plurality of solder interconnects on a first die, wherein the plurality of solder interconnects comprise magnetic particles coated in an oxide;coupling a second die over the first die;reflowing the plurality of solder interconnects; andapplying a magnetic field to the plurality of solder interconnects to join the first die to the second die.8. The method of claim 7 , wherein the magnetic ...

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Номер записи: 94

02-01-2020 дата публикации

DEVICE CONTAINING AND METHOD OF PROVIDING CARBON COVERED COPPER LAYER

Номер: US20200006263A1

Автор: Seidemann Georg

Принадлежит:

A device and method of preventing corrosion of a copper layer in a PCB is disclosed. A first dielectric is disposed on a substrate. A copper layer is plated in an opening in the first dielectric and, after conditioning the copper layer, a redistribution layer is plated on the copper layer. A solder resist layer is disposed above the copper layer. A solder ball is disposed in an opening in the solder resist layer. The solder ball is in conductive contact with the copper layer and in physical contact with the redistribution layer. A non-conductive carbon layer is disposed on and in contact with the redistribution layer or tsi-diehe solder resist layer. The carbon layer is substantially thinner than the copper layer and acts as a diffusion barrier to moisture for the copper layer. 1. A device comprising:a substrate comprising at least one of a semiconductor or mold compound;a first dielectric disposed on substrate;a copper layer plated in an opening in the first dielectric;a solder resist layer above the copper layer;a solder ball in an opening in the solder resist layer, the solder ball in conductive contact with the copper layer; anda non-conductive carbon layer on the substrate, the non-conductive carbon layer formed from carbon rather than a carbon compound and configured to act as a diffusion barrier to moisture for the copper layer.2. The device of claim 1 , wherein the carbon layer is disposed on the substrate below the first dielectric.3. The device of claim 1 , wherein the carbon layer is disposed between the solder resist layer and the first dielectric.4. The device of claim 1 , wherein the carbon layer is disposed on the solder resist layer.5. The device of claim 4 , wherein the carbon layer is further disposed on at least one of the solder ball or an interconnect element.6. The device of claim 4 , wherein the carbon layer is adjacent to the solder ball and the solder ball is free from the carbon layer.7. The device of claim 1 , further comprising:a ...

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Номер записи: 95

03-01-2019 дата публикации

CHIP ENCAPSULATING METHOD AND CHIP ENCAPSULATING STRUCTURE

Номер: US20190006195A1

Автор: Qiu Yun, QU Lianjie, WANG DAN, ZHAO Hebin

Принадлежит:

A chip encapsulating method includes: fixing a plurality of wafers to a first panel level substrate, the wafer including a plurality of chips; forming a re-distribution layer on the wafer for each of the chips; forming each individual chip and the re-distribution layer connected to the chip by cutting; fixing the chip and the re-distribution layer connected thereto to a second panel level substrate; and encapsulating the chip to form an encapsulating layer. A chip encapsulating structure is prepared by the above described chip encapsulating method. 1. A chip encapsulating method , comprising:fixing a plurality of wafers to a first panel level substrate, the wafer comprising a plurality of chips;forming a re-distribution layer on the wafer for each of the chips;forming each individual chip and the re-distribution layer connected to the chip by cutting;fixing the chip and the re-distribution layer connected to the chip to a second panel level substrate; andencapsulating the chip to form an encapsulating layer.2. The chip encapsulating method of claim 1 , wherein when the chip and the re-distribution layer connected with the chip are fixed to the second panel level substrate claim 1 , the re-distribution layer is close to the second panel level substrate;after the chip is encapsulated, the chip encapsulating method further comprises:removing the second panel level substrate;fixing the encapsulating layer to a third panel level substrate, and forming a solder ball on one side of the re-distribution layer.3. The chip encapsulating method of claim 1 , wherein when the chip and the re-distribution layer connected with the chip are fixed to the second panel level substrate claim 1 , the re-distribution layer is close to the second panel level substrate;after the chip is encapsulated, the chip encapsulating method further comprises:cutting the encapsulating layer, to form each individual chip encapsulating body; andforming a solder ball for each of the chip encapsulating ...

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Номер записи: 96

02-01-2020 дата публикации

STRUCTURES FOR BONDING A GROUP III-V DEVICE TO A SUBSTRATE

Номер: US20200006271A1

Автор: Chen Eugene, Chen Jhih-Bin, Liu Ming Chyi, Tsai Chia-Shiung

Принадлежит:

Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer. 1. An integrated chip comprising:a substrate comprising a semiconductor substrate, complementary metal-oxide-semiconductor (CMOS) devices on the semiconductor substrate, and an interconnect structure covering the semiconductor substrate and the CMOS devices;a mesa structure on the substrate and comprising semiconductor material;a bump structure between the substrate and the mesa structure, wherein the bump structure comprises conductive material; anda diffusion layer recessed into the mesa structure, between the bump structure and the mesa structure;wherein the diffusion layer comprises semiconductor and conductive material respectively from the mesa structure and the bump structure, andsidewalls of the diffusion layer are spaced from sidewalls of the mesa structure.2. The integrated chip according to claim 1 , further comprising:an etch stop layer on the mesa structure, between the mesa structure and the substrate, wherein the bump structure protrudes through the etch stop layer to the diffusion layer.3. The integrated chip according to claim 2 , wherein the bump structure wraps around an adjoining corner of ...

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Номер записи: 97

03-01-2019 дата публикации

SEMICONDUCTOR DEVICE AND BUMP FORMATION PROCESS

Номер: US20190006303A1

Автор: Chen Ching-Hui, Chiu Chun-Mao, Huang Hon-Lin, KUO Chien-Hung, Lii Mirng-Ji, WANG CHAO-YI, WANG Zi-Zhong, WU KAI-DI, Wu Sheng-Yu

Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device includes a semiconductor substrate. A pad region is disposed on the semiconductor substrate. A micro bump is disposed on the pad region. The micro bump has a first portion on the pad region and a second portion on the first portion. The first portion and the second portion have different widths. The first portion has a first width and the second portion has a second width. The first width is larger or smaller than the second width. The micro bump includes nickel and gold. The semiconductor device also includes a passivation layer overlying a portion of the pad region. 115.-. (canceled)16. A method of fabricating a semiconductor device , the method comprising:forming a first sacrificial layer over a semiconductor substrate;forming a first opening in the first sacrificial layer to expose a conductive pad over the semiconductor substrate;forming a conductive bump in the first opening;forming a barrier layer on sidewalls of the first opening and on a top surface of the conductive bump;forming a conductive cap in the first opening with the barrier layer interposing in between the conductive bump and the conductive cap; andremoving the first sacrificial layer.17. The method of fabricating the semiconductor device of claim 16 , wherein the forming the barrier layer comprises:forming the barrier layer on a top surface of the first sacrificial layer and in the first opening; andremoving a portion of the barrier layer on the top surface of the first sacrificial layer.18. The method of fabricating the semiconductor device of claim 17 , wherein the portion of the barrier layer on the top surface of the first sacrificial layer is removed by chemical mechanical planarization.19. The method of fabricating the semiconductor device of claim 16 , further comprising:forming a second sacrificial layer over the first sacrificial layer after the forming the conductive cap in the first opening;forming a second opening in the second sacrificial layer exposing a top ...

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Номер записи: 98

03-01-2019 дата публикации

Metal pad modification

Номер: US20190006304A1

Автор: Ekta Misra, Krishna Tunga

Принадлежит: International Business Machines Corp

The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.

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Номер записи: 99

03-01-2019 дата публикации

SEMICONDUCTOR CHIP

Номер: US20190006306A1

Автор: KUROKAWA Atsushi, Shibata Masahiro, TOKUDA Daisuke, TOKUYA Hiroaki, UMEMOTO Yasunari

Принадлежит: MURATA MANUFACTURING CO., LTD.

A semiconductor chip includes a semiconductor substrate having a main surface, first and second electrodes, a first insulating layer, and first and second bumps. The first and second electrodes are formed above the main surface of the semiconductor substrate. The first insulating layer is formed above a first portion of the first electrode. The first bump is formed above a second portion of the first electrode and above the first insulating layer and is electrically connected to the first electrode. The second bump is formed above the second electrode. The area of the second bump is larger than that of the first bump in a plan view of the main surface of the semiconductor substrate. The first insulating layer adjusts the distance from the main surface of the semiconductor substrate to the top surface of the first bump in a direction normal to the main surface. 1. A semiconductor chip comprising:a semiconductor substrate having a main surface;a first electrode formed above the main surface of the semiconductor substrate;a second electrode formed above the main surface of the semiconductor substrate;a first insulating layer formed above a first portion of the first electrode;a first bump that is formed above a second portion of the first electrode and above the first insulating layer, and that is electrically connected to the first electrode; anda second bump formed above the second electrode, an area of the second bump being larger than an area of the first bump in a plan view of the main surface of the semiconductor substrate,wherein a level on which the first bump is formed is higher than a level on which the second bump is formed.2. The semiconductor chip according to claim 1 , wherein a longest distance from the main surface of the semiconductor substrate to a top surface of the first bump in a direction normal to the main surface of the semiconductor substrate is substantially equal to a longest distance from the main surface of the semiconductor substrate to a ...

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Номер записи: 100