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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 36526. Отображено 100.
05-01-2012 дата публикации

Semiconductor package having a stacked structure

Номер: US20120001347A1
Автор: Chan-Min Han, Jin-yang Lee, Kil-Soo Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

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Номер записи: 1
05-01-2012 дата публикации

Active energy ray-curable pressure-sensitive adhesive for re-release and dicing die-bonding film

Номер: US20120003470A1
Автор: Chie Kitano, Hironao OTAKE, Katsuhiko Kamiya, Masatsugu KOSO, Mika Okada, Shuhei Murata, Takeshi Matsumura, Tomokazu Takahashi
Принадлежит: Nitto Denko Corp

Provided is an active energy ray-curable pressure-sensitive adhesive for re-release, which has a small influence on an environment or a human body, can be easily handled, can largely change its pressure-sensitive adhesiveness before and after irradiation with an active energy ray, and can express high pressure-sensitive adhesiveness before the irradiation with the active energy ray and express high releasability after the irradiation with the active energy ray. The active energy ray-curable pressure-sensitive adhesive for re-release includes an active energy ray-curable polymer (P), in which the polymer (P) includes one of a polymer obtained by causing a carboxyl group-containing polymer (P3) and an oxazoline group-containing monomer (m3) to react with each other, and a polymer obtained by causing an oxazoline group-containing polymer (P4) and a carboxyl group-containing monomer (m2) to react with each other.

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Номер записи: 2
12-01-2012 дата публикации

Semiconductor device

Номер: US20120007224A1
Автор: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
Принадлежит: Hitachi Hokkai Semiconductor Ltd, Renesas Electronics Corp

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

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Номер записи: 3
12-01-2012 дата публикации

Power semiconductor module and fabrication method

Номер: US20120009733A1
Автор: Eladio Clemente Delgado, Ernest Wayne Balch, Kevin Matthew Durocher, Paul Alan McConnelee, Raymond Albert Fillion, Richard Alfred Beaupre, Stephen Daley Arthur
Принадлежит: General Electric Co

A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

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Номер записи: 4
19-01-2012 дата публикации

Semiconductor-encapsulating adhesive, semiconductor-encapsulating film-form adhesive, method for producing semiconductor device, and semiconductor device

Номер: US20120012999A1
Автор: Kazutaka Honda, Tetsuya Enomoto, Yuuki Nakamura
Принадлежит: Hitachi Chemical Co Ltd

The present invention relates to a semiconductor-encapsulating adhesive, a semiconductor-encapsulating film-form adhesive, a method for producing a semiconductor device, and a semiconductor device. The present invention provides a semiconductor-encapsulating adhesive comprising (a) an epoxy resin, and (b) a compound formed of an organic acid reactive with an epoxy resin and a curing accelerator.

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Номер записи: 5
19-01-2012 дата публикации

Stacked semiconductor package and method of fabricating the same

Номер: US20120013026A1
Автор: Won-Gil HAN
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A stacked semiconductor package and an electronic system, the stacked semiconductor package including a plurality of semiconductor chips, a set of the semiconductor chips being stacked such that an extension region of a top surface of each semiconductor chip of the set extends beyond an end of a semiconductor chip stacked thereon to form a plurality of extension regions; and a plurality of protection layers on the extension regions and on an uppermost semiconductor chip of the plurality of semiconductor chips.

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Номер записи: 6
26-01-2012 дата публикации

Substrate for semiconductor element, method for manufacturing substrate for semiconductor element, and semiconductor device

Номер: US20120018867A1
Автор: Junko Toda, Susumu Maniwa, Takehito Tsukamoto
Принадлежит: Toppan Printing Co Ltd

Provided is a manufacturing method of a semiconductor element substrate including: a step of forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; a step of forming a second photoresist pattern on the second surface of the metallic plate; a step of forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; a step of forming a plurality of concaved parts on the second surface of the metallic plate; a step of forming a resin layer by injecting a resin to the plurality of concaved parts; and a step of etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.

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Номер записи: 7
26-01-2012 дата публикации

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

Номер: US20120018904A1
Автор: Jianmin Fang, KANG Chen, Xia Feng, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

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Номер записи: 8
02-02-2012 дата публикации

Laminated semiconductor substrate, laminated chip package and method of manufacturing the same

Номер: US20120025354A1
Автор: Atsushi Iijima, Hiroyuki Ito, Yoshitaka Sasaki
Принадлежит: Headway Technologies Inc, SAE Magnetics HK Ltd

In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have an electromagnetic shielding layer formed using a ferromagnetic body. The electromagnetic shielding layer is formed in a shielding region except the extending zone. The extending zone is set a part which the wiring electrode crosses, in a peripheral edge part of the device region.

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Номер записи: 9
02-02-2012 дата публикации

Semiconductor device

Номер: US20120025367A1
Автор: Akio Katsumata, Goshi Kawazu, Isao Kudo, Yoichi Hiruta, Yukari Imaizumi
Принадлежит: J Devices Corp, Toshiba Corp

A semiconductor device which includes a substrate, a semiconductor element arranged on the substrate, a heat dissipation component arranged on the semiconductor element, and a mold component covering an upper part of the substrate, the semiconductor element and the heat dissipation component, wherein an area of a surface on the semiconductor element of the heat dissipation component is larger than an area of a surface on which the heat dissipation component of the semiconductor element is arranged.

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Номер записи: 10
02-02-2012 дата публикации

Chip package and fabricating method thereof

Номер: US20120025387A1
Автор: Kuo-Ching Chang, Tzu-Han Lin, Wu-Cheng Kuo
Принадлежит: Individual

A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.

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Номер записи: 11
02-02-2012 дата публикации

Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module

Номер: US20120025393A1
Автор: Andre Roehrig, Olaf Kirsch, Peter Kanschat, Thilo Stolze
Принадлежит: INFINEON TECHNOLOGIES AG

A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

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Номер записи: 12
02-02-2012 дата публикации

Method and electrostatic transfer stamp for transferring semiconductor dice using electrostatic transfer printing techniques

Номер: US20120027557A1
Автор: Ian Ashdown, Ingo Speier
Принадлежит: Cooledge Lighting Inc

A transfer stamp that can be charged with a spatial pattern of electrostatic charge for picking up selected semiconductor dice from a host substrate and transferring them to a target substrate. The stamp may be bulk charged and then selectively discharged using irradiation through a patterned mask. The technique may also be used to electrostatically transfer selected semiconductor dice from a host substrate to a target substrate.

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Номер записи: 13
09-02-2012 дата публикации

Semiconductor device and method for producing such a device

Номер: US20120032295A1
Автор: Carsten Von Koblinski, Francisco Javier Santos Rodriguez, Friedrich Kroener
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

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Номер записи: 14
09-02-2012 дата публикации

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

Номер: US20120032298A1
Автор: Hideki Fujii, Kenji Furuya, Yuichi Miyagawa
Принадлежит: Renesas Electronics Corp

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

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Номер записи: 15
16-02-2012 дата публикации

Method for molecular adhesion bonding at low pressure

Номер: US20120038027A1
Автор: Marcel Broekaart
Принадлежит: Soitec SA

The present invention relates to a method for molecular adhesion bonding between at least a first wafer and a second wafer involving aligning the first and second wafers, placing the first and second wafers in an environment having a first pressure (P 1 ) greater than a predetermined threshold pressure; bringing the first wafer and the second wafer into alignment and contact; and initiating the propagation of a bonding wave between the first and second wafer after the wafers are aligned and in contact by reducing the pressure within the environment to a second pressure (P 2 ) below the threshold pressure. The invention also relates to the three-dimensional composite structure that is obtained by the described method of adhesion bonding.

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Номер записи: 16
16-02-2012 дата публикации

Structure for Multi-Row Leadframe and Semiconductor Package Thereof and Manufacture Method Thereof

Номер: US20120038036A1
Автор: Hyuk Soo Lee, Hyun A. Chun, Jae Bong Choi, Sai Ran Eom, Sung Won Lee, Sung Wuk Ryu
Принадлежит: LG Innotek Co Ltd

The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

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Номер записи: 17
16-02-2012 дата публикации

Stitch bump stacking design for overall package size reduction for multiple stack

Номер: US20120038059A1
Автор: Foong Yue Ho, Kevin Guan, Koo Eng LUON, Lai Nguk Chin, Sally Foong, Wong Kwet Nam
Принадлежит: Individual

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

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Номер записи: 18
01-03-2012 дата публикации

Bumpless build-up layer package with pre-stacked microelectronic devices

Номер: US20120049382A1
Автор: Pramod Malatkar
Принадлежит: Intel Corp

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

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Номер записи: 19
08-03-2012 дата публикации

Semiconductor package

Номер: US20120056313A1
Автор: Jun Morimoto, Masashi AIZAWA, Masayuki Kato
Принадлежит: Individual

A semiconductor package includes a radiator plate including a stress alleviation section, a resin sheet arranged on the radiator plate, a pair of bus bars joined to the radiator plate through the resin sheet at positions at which the stress alleviation section is interposed between the bus bars, and a semiconductor device joined to the pair of bus bars by being sandwiched between the bus bars, and energized from outside through the pair of bus bars.

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Номер записи: 20
15-03-2012 дата публикации

Power Semiconductor Chip Package

Номер: US20120061812A1
Автор: Ralf Otremba
Принадлежит: INFINEON TECHNOLOGIES AG

A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad.

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Номер записи: 21
15-03-2012 дата публикации

Semiconductor device and manufacturing method of the same

Номер: US20120061817A1
Автор: Mamoru SHISHIDO, Noriyuki Takahashi
Принадлежит: Renesas Electronics Corp

A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

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Номер записи: 22
22-03-2012 дата публикации

Tsop with impedance control

Номер: US20120068317A1
Автор: Belgacem Haba, Brian Marcucci
Принадлежит: TESSERA RESEARCH LLC

A semiconductor device of an illustrative embodiment includes a die, a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die. Most preferably, the package includes at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the leads such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path, and an encapsulant which encapsulates the leads and the conductive element. The leads and, desirably, the conductive element have respective connection regions which are not covered by the encapsulant.

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Номер записи: 23
22-03-2012 дата публикации

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

Номер: US20120068319A1
Автор: Daesik Choi, Oh Han Kim, SangMi Park
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

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Номер записи: 24
22-03-2012 дата публикации

Substrate bonding with metal germanium silicon material

Номер: US20120068325A1
Автор: Alex P. Pamatat, Ruben B. Montez
Принадлежит: FREESCALE SEMICONDUCTOR INC

In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

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Номер записи: 25
22-03-2012 дата публикации

Anti-tamper microchip package based on thermal nanofluids or fluids

Номер: US20120068326A1
Автор: James J. McNamara, Jr., Mark D. Poliks, Rabindra N. Das, Voya R. Markovich
Принадлежит: Endicott Interconnect Technologies Inc

A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.

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Номер записи: 26
29-03-2012 дата публикации

Methods of fabricating package stack structure and method of mounting package stack structure on system board

Номер: US20120074586A1
Автор: Eun-Jin Choi, Sun-Kyoung SEO
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

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Номер записи: 27
29-03-2012 дата публикации

Integrated circuit packaging system with warpage control and method of manufacture thereof

Номер: US20120074588A1
Автор: Hin Hwa Goh, KANG Chen, Rui Huang, Xusheng Bao, Yung Kuan Hsiao
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.

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Номер записи: 28
12-04-2012 дата публикации

Package systems and manufacturing methods thereof

Номер: US20120086126A1
Автор: Chia-Pao SHU, Chun-Wen Cheng, Kuei-Sung CHANG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

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Номер записи: 29
12-04-2012 дата публикации

Package systems and manufacturing methods thereof

Номер: US20120086127A1
Автор: Chia-Pao SHU, Chun-Wen Cheng, Hsin-Ting HUANG, Jung-Huei Peng, Kuei-Sung CHANG, Shang-Ying Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

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Номер записи: 30
19-04-2012 дата публикации

Method of die bonding onto dispensed adhesives

Номер: US20120094440A1
Автор: Kui Kam Lam, Kwok Kee Chung, Kwok Kiu CHAN, Yen Hsi Tang
Принадлежит: ASM Assembly Automation Ltd

A method of bonding semiconductor dice onto a substrate first uses an optical assembly to perform pattern recognition of a die bonding section of the substrate in which multiple die pads are located so as to identify positions of the multiple die pads simultaneously during such pattern recognition step. After pattern recognition of the said die bonding section, an adhesive is dispensed with an adhesive dispenser onto at least one of the die pads located in the die bonding section. While the adhesive dispenser is dispensing the adhesive to further die pads located in the die bonding section, a pick-and-place arm concurrently bonds a die onto each die pad where the adhesive has already been dispensed.

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Номер записи: 31
03-05-2012 дата публикации

Semiconductor package device with a heat dissipation structure and the packaging method thereof

Номер: US20120104581A1
Автор: Chia-Feng Yeh, Chung-Hwa Wu, Shao-Kang Hung
Принадлежит: Global Unichip Corp

The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

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Номер записи: 32
03-05-2012 дата публикации

Chip-on-chip structure and manufacturing method therof

Номер: US20120104597A1
Автор: Junji Yoshikawa, Tatsuji Ishiduka, Tsutomu Kojima
Принадлежит: Toshiba Corp

According to an embodiment, a chip-on-chip structure includes a first chip, a second chip, the first chip and the second chip being opposite to each other, a first electrode terminal, a second electrode terminal, a bump and a protecting material. The first electrode terminal is provided on the surface of the first chip at the side of the second chip. The second electrode terminal is provided on the surface of the second chip at the side of the first chip. The bump electrically connects the first electrode terminal and the second electrode terminal. The protecting material is formed around the bump between the first chip and the second chip. The protecting material includes a layer made of a material having heat-sensitive adhesive property.

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Номер записи: 33
03-05-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120108013A1
Автор: Atsushi Fujisawa, Hiroshi Fujii
Принадлежит: Renesas Electronics Corp

In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads. This method includes a step of removing a sealing resin filled between the circumference of a mold cavity and the dam bar by using laser and then carrying out surface treatment, for example, solder plating.

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Номер записи: 34
10-05-2012 дата публикации

Electronic element unit and reinforcing adhesive agent

Номер: US20120111617A1
Автор: Koji Motomura, Seiichi Yoshinaga, Tadahiko Sakai
Принадлежит: Panasonic Corp

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

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Номер записи: 35
17-05-2012 дата публикации

Semiconductor Device And Method Of Manufacturing Semiconductor Device

Номер: US20120119338A1
Автор: Shintaro Yamamichi, Takahito Watanabe, Yoshitaka USHIYAMA
Принадлежит: Renesas Electronics Corp

A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

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Номер записи: 36
17-05-2012 дата публикации

Underfill method and chip package

Номер: US20120119353A1
Автор: Michael A. Gaynes, Rajneesh Kumar, Steve Ostrander, Thomas E. Lombardi
Принадлежит: International Business Machines Corp

A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.

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Номер записи: 37
24-05-2012 дата публикации

Connecting and Bonding Adjacent Layers with Nanostructures

Номер: US20120125537A1
Автор: Andrzej Brud, Mohammad Shafiqul Kabir
Принадлежит: Smoltek AB

An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.

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Номер записи: 38
24-05-2012 дата публикации

Copper conductor film and manufacturing method thereof, conductive substrate and manufacturing method thereof, copper conductor wiring and manufacturing method thereof, and treatment solution

Номер: US20120125659A1
Автор: Hideo Nakako, Katsuyuki Masuda, Kazunori Yamamoto, Shunya Yokozawa, Yasushi Kumashiro, Yoshinori Ejiri, Youichi Machii
Принадлежит: Hitachi Chemical Co Ltd

Provided are a copper conductor film and manufacturing method thereof, and patterned copper conductor wiring, which have superior conductivity and wiring pattern formation, and with which there is no decrease in insulation between circuits, even at narrow wiring widths and narrow inter-wiring spacing. Disclosed are a copper conductor film and manufacturing method thereof in which a copper-based particle-containing layer, which contains both a metal having catalytic activity toward a reducing agent and copper oxide, is treated using a treatment solution that contains a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complex to form metallic copper in a single solution, and patterned copper conductor wiring that is obtained by patterning a copper-based particle-containing layer using printing and by said patterned particle-containing layer being treated by a treatment method using a solution that contains both a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complexes to form metallic copper in a single solution.

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Номер записи: 39
14-06-2012 дата публикации

Integrated circuit mounting system with paddle interlock and method of manufacture thereof

Номер: US20120146192A1
Автор: Arnel Senosa Trasporto, Byung Joon Han, Byung Tai Do, Henry Descalzo Bathan
Принадлежит: Individual

A method of manufacture of an integrated circuit mounting system includes: providing a die paddle with a component side having a die mount area and a recess with more than one geometric shape; applying an adhesive on the die mount area and in a portion of the recess; and mounting an integrated circuit device with an inactive side directly on the adhesive.

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Номер записи: 40
14-06-2012 дата публикации

Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures

Номер: US20120146215A1
Автор: Chih-Hung Lu, Yu-Ju Yang
Принадлежит: ILI Techonology Corp

A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.

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Номер записи: 41
21-06-2012 дата публикации

Semiconductor component, semiconductor wafer component, manufacturing method of semiconductor component, and manufacturing method of joining structure

Номер: US20120153461A1
Автор: Akio Furusawa, Hidetoshi Kitaura, Shigeaki Sakatani, Taichi Nakamura, Takahiro Matsuo
Принадлежит: Panasonic Corp

A semiconductor component of the present invention includes a semiconductor element and a joining layer formed on one surface of the semiconductor element and consisting of a joining material containing Bi as an essential ingredient, and projecting sections are formed on a surface of the joining layer on a side opposite to a surface in contact with the semiconductor element. By joining the semiconductor component to an electrode arranged so as to face the joining layer, the generation of a void can be suppressed.

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Номер записи: 42
21-06-2012 дата публикации

Tsv for 3d packaging of semiconductor device and fabrication method thereof

Номер: US20120153496A1
Автор: Chang-woo Lee, Jae-hak Lee, Joon-Yub Song, Tae-Ho Ha
Принадлежит: Korea Institute of Machinery and Materials KIMM

The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electric conductivity, and minimizing electrical signal delay, without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.

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Номер записи: 43
21-06-2012 дата публикации

Microelectronic package and method of manufacturing same

Номер: US20120153504A1
Автор: Edward R. Prack, Leonel R. Arana, Robert M. Nickerson
Принадлежит: Intel Corp

A microelectronic package includes a substrate ( 110, 210 ), an interposer ( 120, 220 ) having a first surface ( 121 ) and an opposing second surface ( 122 ), a microelectronic die ( 130, 230 ) attached to the substrate, and a mold compound ( 140 ) over the substrate. The interposer is electrically connected to the substrate using a wirebond ( 150 ). The first surface of the interposer is physically connected to the substrate with an adhesive ( 160 ), and the second surface has an electrically conductive contact ( 126 ) formed therein. The mold compound completely encapsulates the wirebond and partially encapsulates the interposer such that the electrically conductive contact in the second surface of the interposer remains uncovered by the mold compound.

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Номер записи: 44
28-06-2012 дата публикации

Chip scale surface mounted semiconductor device package and process of manufacture

Номер: US20120161307A1
Автор: Tao Feng
Принадлежит: ALPHA AND OMEGA SEMICONDUCTOR INC

A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.

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Номер записи: 45
28-06-2012 дата публикации

Trap Rich Layer for Semiconductor Devices

Номер: US20120161310A1
Автор: Chris BRINDLE, Michael A. Stuber, Stuart B. Molin
Принадлежит: IO Semiconductor Inc

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

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Номер записи: 46
28-06-2012 дата публикации

Bond package and approach therefor

Номер: US20120162958A1
Автор: Michael Rother
Принадлежит: NXP BV

Lead-free or substantially lead-free structures and related methods are implemented for manufacturing electronic circuits. In accordance with various example embodiments, circuit components are joined using a copper-tin (Cu—Sn) alloy, which is melted and used to form a Cu—Sn compound having a higher melting point than the Cu—Sn alloy and both physically and electrically coupling circuit components together.

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Номер записи: 47
05-07-2012 дата публикации

Semiconductor device

Номер: US20120168927A1
Автор: Shingo Itoh
Принадлежит: Sumitomo Bakelite Co Ltd

A semiconductor device is configured that two or more semiconductor elements are stacked and mount on a lead frame, the aforementioned lead frame is electrically joined to the semiconductor element with a wire, and the semiconductor element, the wire and an electric junction are encapsulated with a cured product of an epoxy resin composition for encapsulating semiconductor device, and that the epoxy resin composition for encapsulating semiconductor device contains (A) an epoxy resin; (B) a curing agent; and (C) an inorganic filler, and that the (C) inorganic filler contains particles having particle diameter of equal to or smaller than two-thirds of a thinnest filled thickness at a rate of equal to or higher than 99.9% by mass.

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Номер записи: 48
05-07-2012 дата публикации

Substrate bonding method and semiconductor device

Номер: US20120168954A1
Автор: Toshihiro Seko
Принадлежит: Stanley Electric Co Ltd

A first Sn absorption layer is formed on a principal surface of a first substrate, the first Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A second Sn absorption layer is formed on a principal surface of a second substrate, the second Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A solder layer made of AuSn alloy is formed at least on one Sn absorption layer of the first and second Sn absorption layers. The first and second substrates are bonded together by melting the solder layer in a state that the first and second substrates are in contact with each other, with the principal surfaces of the first and second substrates facing each other.

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Номер записи: 49
12-07-2012 дата публикации

Methods And Materials Useful For Chip Stacking, Chip And Wafer Bonding

Номер: US20120175721A1
Автор: Andrew Bell, Chris Apanius, Hendra Ng, Phil Neal, Robert A. Shick, Wei Zhang
Принадлежит: PROMERUS LLC

Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.

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Номер записи: 50
12-07-2012 дата публикации

Alignment marks to enable 3d integration

Номер: US20120175789A1
Автор: Emily R. Kinser, Kevin R. Winstel, Kevin S. Patrarca, Mukta G. Farooq, Richard P. Volant, Robert Hannon, Troy L. Graves-Abe, William F. Landers
Принадлежит: International Business Machines Corp

Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

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Номер записи: 51
12-07-2012 дата публикации

Methods for vacuum assisted underfilling

Номер: US20120178219A1
Автор: Alec J. Babiarz, Horatio Quinones, Thomas L. Ratledge
Принадлежит: Nordson Corp

Methods for applying an underfill with vacuum assistance. The method may include dispensing the underfill onto a substrate proximate to at least one exterior edge of an electronic device attached to the substrate. A space between the electronic device and the substrate is evacuated through at least one gap in the underfill. The method further includes heating the underfill to cause the underfill to flow into the space. Because a vacuum condition is supplied in the open portion of the space before flow is initiated, the incidence of underfill voiding is lowered.

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Номер записи: 52
19-07-2012 дата публикации

Adhesive film for light emitting device and method of manufacturing led package using the same

Номер: US20120181571A1
Автор: II Woo Park, Kyu Jin Lee, Na Na Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided is an adhesive film for an LED chip, including: a double-sided adhesive layer having the LED chip adhered to an upper surface thereof and a lead frame adhered to a lower surface thereof; an ultraviolet (UV) cured layer adhered to one surface of the double-sided adhesive layer; and upper and lower cover layers respectively adhered to faces exposed to the exterior of the double-sided adhesive layer and the UV cured layer.

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Номер записи: 53
26-07-2012 дата публикации

Semiconductor chip module, semiconductor package having the same and package module

Номер: US20120187560A1
Автор: Hyeon Ji BAEK, Hyung Ju CHOI, Jong Hyun Kim, Mun Aun HYUN
Принадлежит: Hynix Semiconductor Inc

A semiconductor module comprising a plurality of semiconductor chips where at least one semiconductor chip is laterally offset with respect to a second semiconductor chip, and substantially aligned with a third semiconductor chip such that an electrical connection can be made between an electrical contact in the first semiconductor chip and an electrical contact in the third semiconductor chip.

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Номер записи: 54
26-07-2012 дата публикации

Direct Edge Connection for Multi-Chip Integrated Circuits

Номер: US20120187577A1
Автор: James L. Speidell, John U. Knickerbocker, Matthew J. Farinelli, Peter A. Gruber, Sherif A. Goma, Steven A. Cordes
Принадлежит: International Business Machines Corp

The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

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Номер записи: 55
02-08-2012 дата публикации

Ohmic connection using widened connection zones in a portable electronic object

Номер: US20120193804A1
Автор: Yannick Grasset
Принадлежит: RFIDEAL

The invention relates to portable electronic objects comprising an integrated circuit chip, and a mounting having two connection terminals for a circuit, as well as to a method for manufacturing such objects. The invention is characterized in that the chip is provided, on the active surface thereof, with two widened connection zones, in particular connection plates, said connection plates being positioned opposite said terminals and electrically connected, by ohmic contact, to the latter, and in that the surface defined by the connection plates, at the surface of the active integrated circuit having said plates, is greater than ½ of the surface of said surface. The invention can be used, in particular, for RFID objects.

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Номер записи: 56
02-08-2012 дата публикации

Semiconductor Package with Embedded Die

Номер: US20120196406A1
Автор: Rajendra D. Pendse
Принадлежит: Stats Chippac Pte Ltd

A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

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Номер записи: 57
09-08-2012 дата публикации

Semiconductor device and method of fabricating the semiconductor device

Номер: US20120199981A1
Автор: Ho-geon Song, Jae-hyun PHEE, Ju-Il Choi, Se-young Jeong
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

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Номер записи: 58
16-08-2012 дата публикации

Back side illuminated image sensor with reduced sidewall-induced leakage

Номер: US20120205769A1
Автор: Dun-Nian Yaung, Hsiao-Hui Tseng, Jen-Cheng Liu, Shuang-Ji Tsai, Wen-De Wang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Provided is an image sensor device. The image sensor device includes having a front side, a back side, and a sidewall connecting the front and back sides. The image sensor device includes a plurality of radiation-sensing regions disposed in the substrate. Each of the radiation-sensing regions is operable to sense radiation projected toward the radiation-sensing region through the back side. The image sensor device includes an interconnect structure that is coupled to the front side of the substrate. The interconnect structure includes a plurality of interconnect layers and extends beyond the sidewall of the substrate. The image sensor device includes a bonding pad that is spaced apart from the sidewall of the substrate. The bonding pad is electrically coupled to one of the interconnect layers of the interconnect structure.

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Номер записи: 59
16-08-2012 дата публикации

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

Номер: US20120208326A9
Автор: Rajendra D. Pendse
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

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Номер записи: 60
23-08-2012 дата публикации

Semiconductor device and method for manufacturing semiconductor device

Номер: US20120211764A1
Автор: Keiji Watanabe, Keishiro Okamoto, Nobuhiro Imaizumi, Tadahiro Imada
Принадлежит: Fujitsu Ltd

A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.

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Номер записи: 61
30-08-2012 дата публикации

Multi-chip module package

Номер: US20120217657A1
Автор: Chih-Feng Huang, Chiu-Chih Chiang, Lih-Ming Doong, You-Kuo Wu
Принадлежит: Individual

A multi-chip module package is provided, which includes a first chip mounted on via a first conductive adhesive and electrically connected to a first chip carrier, a second chip mounted on via a second conductive adhesive and electrically connected to a second chip carrier which is spaced apart from the first chip carrier, wherein the second conductive adhesive is made of an adhesive material the same as that of the first conductive material, a plurality of conductive elements to electrically connect the first chip to the second chip and an encapsulant encapsulating the first chip, the first chip carrier, the second chip, the second chip carrier and the plurality of conductive elements, allowing a portion of both chip carriers to be exposed to the encapsulant, so that the first chip and second chip are able to be insulated by the separation of the first and second chip carriers.

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Номер записи: 62
30-08-2012 дата публикации

Semiconductor apparatus, method for manufacturing the same and electric device

Номер: US20120217660A1
Автор: Keishiro Okamoto, Motoaki Tani
Принадлежит: Fujitsu Ltd

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

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Номер записи: 63
13-09-2012 дата публикации

Method of manufacturing film for semiconductor device

Номер: US20120231557A1
Автор: Koichi Inoue, Miki Morita, Yuichiro Shishido
Принадлежит: Nitto Denko Corp

The present invention aims to provides a method of manufacturing a film for a semiconductor device in which a dicing film, a die bond film, and a protecting film are laminated in this order, including the steps of: irradiating the die bond film with a light ray having a wavelength of 400 to 800 nm to detect the position of the die bond film based on the obtained light transmittance and punching the dicing film out based on the detected position of the die bond film, and in which T 2 /T 1 is 0.04 or more, wherein T 1 is the light transmittance of the portion where the dicing film and the protecting film are laminated and T 2 is the light transmittance of the portion where the dicing film, the die bond film, and the protecting film are laminated.

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Номер записи: 64
20-09-2012 дата публикации

Semiconductor apparatus and method for manufacturing the same

Номер: US20120235291A1
Автор: Kentaro Suga, Masayuki Uchida, Satoru Hara, Takashi Togasaki
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor apparatus includes a semiconductor device, a heat spreader, a regulating unit, a containing unit, and a holding unit. The heat spreader is bonded to the semiconductor device with an interposed solder layer. The regulating unit is configured to regulate a dimension between the semiconductor device and the heat spreader. The containing unit is configured to contain melted solder in an interior of the containing unit. The holding unit is configured to allow melted solder held in an interior of the holding unit. The holding unit is configured to replenish the melted solder in the case where an amount of the melted solder contained in the containing unit is insufficient. The holding unit is configured to recover the melted solder in the case where the amount of the melted solder contained in the containing unit is excessive.

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Номер записи: 65
27-09-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120241942A1
Автор: Takumi Ihara
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.

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Номер записи: 66
27-09-2012 дата публикации

Unpackaged and packaged IC stacked in a system-in-package module

Номер: US20120241954A1
Автор: Nic Rossi, Robert W. Warren
Принадлежит: Conexant Systems LLC

There is provided a system and method for unpackaged and packaged IC stacked in a system-in-package module. There is provided a system-in-package module comprising a substrate including a first contact pad and a second contact pad disposed thereon, a packaged device disposed on the substrate, and an unpackaged device stacked atop the packaged device, wherein a first electrode of the packaged device is electrically and mechanically coupled to the first contact pad, and wherein a second electrode of the unpackaged device is electrically coupled to the second contact pad. The structure of the disclosed system-in-package module provides several advantages over conventional designs including increased yields, facilitated die substitution, enhanced thermal and grounding performance through direct connect vias, stacking of wider devices without a spacer, and a simplified single package structure for reduced fabrication time and cost.

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Номер записи: 67
27-09-2012 дата публикации

Magnetic integration double-ended converter

Номер: US20120241959A1
Автор: Leif Bergstedt
Принадлежит: Huawei Technologies Co Ltd

The present invention relates to a method of bonding a chip to an external electric circuit. The conductors of the external electric circuit for connection to the chip are formed with physical extensions and the chip is directly bonded to these extensions. The invention also relates to an electric device comprising at least one chip and an external electric circuit. The chip is directly bonded to physical extensions of conductors of the external electric circuit.

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Номер записи: 68
27-09-2012 дата публикации

Integrated circuit packaging system with lead frame etching and method of manufacture thereof

Номер: US20120241962A1
Автор: Zigmund Ramirez Camacho
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing a pre-plated leadframe having a contact pad and a die paddle pad; forming an isolated contact from the pre-plated leadframe and the contact pad; mounting an integrated circuit die over the die paddle pad; and encapsulating with an encapsulation the integrated circuit die and the isolated contact, the encapsulation having a bottom surface which is planar and exposing in the bottom surface only the contact pad and the die paddle pad.

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Номер записи: 69
18-10-2012 дата публикации

Method for making circuit board

Номер: US20120260502A1
Автор: Lee-Sheng Yen
Принадлежит: Advance Materials Corp

A method for making the same is disclosed. First, a first substrate and a second substrate are provided. The first substrate includes a release film attached to a carrier. The second substrate includes a copper film covered with a solder mask. Second, the solder masked is patterned. Next, the release film and the patterned solder mask are pressed together so that the first substrate is attached to the second substrate. Then, the copper film is patterned to form a first pattern and a second pattern. The first pattern is in direct contact with the release film and the second pattern is in direct contact with the patterned solder mask. Later, a passivation is formed to cover the first pattern and the second pattern to form a circuit board structure. Afterwards, a package is formed on the carrier to form a packaging structure.

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Номер записи: 70
18-10-2012 дата публикации

Anisotropic conductive film, joined structure, and connecting method

Номер: US20120261171A1
Автор: Koichi Miyauchi, Yasunobu Yamada
Принадлежит: Sony Chemical and Information Device Corp

To provide an anisotropic conductive film, which contains: an electric conductive layer containing Ni particles, metal-coated resin particles, a binder, a polymerizable monomer, and a curing agent; and an insulating layer containing a binder, a monofunctional polymerizable monomer, and a curing agent, wherein the metal-coated resin particles are resin particles each containing a resin core coated at least with Ni.

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Номер записи: 71
18-10-2012 дата публикации

Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof

Номер: US20120261808A1
Автор: Dioscoro A. Merilo, Henry Descalzo Bathan, Lionel Chien Hui Tay, Zigmund Ramirez Camacho
Принадлежит: Individual

A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

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Номер записи: 72
18-10-2012 дата публикации

Chip package and manufacturing method thereof

Номер: US20120261809A1
Автор: Kuo-Hua LIU, Tsang-Yu Liu, Yen-Shih Ho, Yu-Lin Yen, Yu-Lung Huang
Принадлежит: XinTec Inc

An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.

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Номер записи: 73
18-10-2012 дата публикации

Bridging arrangement and method for manufacturing a bridging arrangement

Номер: US20120261819A1
Автор: Cyrill Kuemin, Heiko Wolf, Javier V. Goicochea, Thomas J. Brunschwiler, Walter H. Riess
Принадлежит: International Business Machines Corp

A bridging arrangement for coupling a first terminal to a second terminal includes a plurality of particles of a first type forming at least one path between the first terminal and the second terminal, wherein the particles of the first type are attached to each other; a plurality of particles of a second type arranged in a vicinity of a contact region between a first particle of the first type and a second particle of the first type, wherein at least a portion of the plurality of particles of the second type is attached to the first particle of the first type and the second particle of the first type.

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Номер записи: 74
25-10-2012 дата публикации

Semiconductor device

Номер: US20120267682A1
Автор: Takamitsu Kanazawa, Toshiyuki Hata
Принадлежит: Renesas Electronics Corp

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

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Номер записи: 75
25-10-2012 дата публикации

Sensor mounted in flip-chip technology on a substrate

Номер: US20120267731A1
Автор: Felix Mayer, Franziska Brem, Markus Graf, Werner Hunziker
Принадлежит: Individual

The sensor assembly comprises a substrate ( 1 ), such as a flexible printed circuit board, and a sensor chip ( 2 ) flip-chip mounted to the substrate ( 1 ), with a first side ( 3 ) of the sensor chip ( 2 ) facing the substrate ( 1 ). A sensing area ( 4 ) and contact pads ( 5 ) are integrated on the first side ( 3 ) of the sensor chip ( 2 ) and located in a chamber ( 17 ) between the substrate ( 1 ) and the sensor chip ( 2 ). Chamber ( 17 ) is bordered along at least two sides by a dam ( 16 ). Underfill ( 18 ) and/or solder flux is arranged between the sensor chip ( 2 ) and the substrate ( 1 ), and the dam ( 16 ) prevents the underfill from entering the chamber ( 17 ). An opening ( 19 ) extends from the chamber to the environment and is located between the substrate ( 1 ) and the sensor chip ( 2 ) or extends through the sensor chip ( 2 ).

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Номер записи: 76
25-10-2012 дата публикации

Die attach film

Номер: US20120270381A1
Автор: Hyo Sook Joo, Hyo Soon Park, Hyun Ju Cho, Jang Soon Kim, Jong Wan Hong, Suk Ky Chang, Yong Su Park
Принадлежит: LG Chem Ltd

Provided are a die attach film, a semiconductor wafer, and a semiconductor packaging method. The die attach film can prevent generation of burrs or scattering of chips in a dicing process, and exhibits excellent expandability and pick-up characteristics in a die pressure-sensitive adhesive process. Further, the die attach film can prevent release, shifting, or deflection of a chip in a wire pressure-sensitive adhesive or molding process. Thus, it is possible to improve embeddability, inhibit warpage of a wafer or wiring substrate, and enhance productivity in a semiconductor packaging process.

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Номер записи: 77
01-11-2012 дата публикации

Semiconductor device, process for producing same, and display device

Номер: US20120273831A1
Автор: Katsuyuki Suga
Принадлежит: Sharp Corp

A wire ( 24 ) and a pixel electrode ( 25 ) are formed on a surface of a flat supporting substrate ( 21 ) which surface is opposite to a surface on which a TFT ( 16 ) is formed. Accordingly, it is possible to provide an active matrix substrate ( 2 ) which makes it possible to suppress a decline in yield.

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Номер записи: 78
01-11-2012 дата публикации

Semiconductor Device and Method of Making a Semiconductor Device

Номер: US20120273935A1
Автор: Beng Keh See, Chin Wei Ronnie Tan, Horst Theuss, Kathleen Ong, Kian Pin Queck, Stefan Martens, Tze Yang Hin, Ulrich Krumbein
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device and a method of manufacturing a semiconductor device are disclosed. An embodiment comprises forming a bump on a die, the bump having a solder top, melting the solder top by pressing the solder top directly on a contact pad of a support substrate, and forming a contact between the die and the support substrate.

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Номер записи: 79
08-11-2012 дата публикации

Heating apparatus and implemented body manufacturing method

Номер: US20120279653A1
Автор: Takashi Matsumura
Принадлежит: Sony Chemical and Information Device Corp

To improve the tact time of a heating apparatus, provided is a heating apparatus comprising a first pressing member that heats a heating target; a second pressing member that includes an elastic body, and sandwiches the heating target between the first pressing member and the elastic body; and a floating jig that thermally separates the first pressing member from the heating target, holds the heating target between the first pressing member and the second pressing member, and when one of the first pressing member and the second pressing member presses the heating target toward the other of the first pressing member and the second pressing member, thermally connects the heating target and the first pressing member.

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Номер записи: 80
08-11-2012 дата публикации

Method of manufacturing chip-stacked semiconductor package

Номер: US20120282735A1
Автор: Chang-seong Jeon, Dong-Hyeon Jang, Ho-geon Song, Jung-seok Ahn, Sang-sick Park, Sung-Jun IM, Teak-Hoon LEE
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

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Номер записи: 81
08-11-2012 дата публикации

Manufacturing method of semiconductor device

Номер: US20120282737A1
Автор: Tetsuharu TANOUE
Принадлежит: Individual

Performing electrolysis plating to a wiring is made possible, aiming at the increasing of pin count of a semiconductor device. Package substrate 3 by which ring shape common wiring 3 p for electric supply was formed in the inner area of bonding lead 3 j in device region 3 v of main surface 3 a is used. Since a plurality of first plating lines 3 r and fourth plating lines 3 u for electric supply connected to common wiring 3 p can be arranged by this, the feeder for electrolysis plating can be arranged to all the land parts on the back. Hereby, it becomes possible to perform electrolysis plating to the wiring of main surface 3 a of package substrate 3 , and the back surface.

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Номер записи: 82
15-11-2012 дата публикации

Solar cell assembly ii

Номер: US20120285530A1
Автор: Martin Ziegler, Van Riesen Sascha
Принадлежит: SOITEC SOLAR GMBH

The present invention relates to a solar cell assembly that includes a solar cell attached to a bonding pad and a cooling substrate, wherein the bonding pad is attached to a surface of the cooling substrate by a thermally conductive adhesive and electrically contacted to the bonding pad and cooling substrate by a bonding wire. Alternatively, the bonding pad is attached to a surface of the cooling substrate by a thermally and electrically conductive adhesive.

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Номер записи: 83
15-11-2012 дата публикации

Semiconductor device

Номер: US20120286426A1
Автор: Ki Young Kim
Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a first structural body having first electrode pads; a second structural body disposed in a face-up type over the first structural body in such a way as to expose the first electrode pads, and having first connection members with at least two protrusions; and a third structural body disposed in a face-down type over the second structural body, and having second connection members with at least two protrusions, on a surface thereof facing the second structural body, wherein some of the protrusions of the second connection members are electrically connected with the exposed first electrode pads, and at least one of remaining protrusions of the second connection members is electrically connected with the first connection members.

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Номер записи: 84
15-11-2012 дата публикации

Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance

Номер: US20120289001A1
Автор: Anup Bhalla, Francois Hebert, Kai Liu, Ming Sun
Принадлежит: Alpha and Omega Semiconductor Ltd

A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

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Номер записи: 85
22-11-2012 дата публикации

Method for Producing a Metal Layer on a Substrate and Device

Номер: US20120292773A1
Автор: Hans-Joachim Schulze, Khalil Hosseini
Принадлежит: INFINEON TECHNOLOGIES AG

A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.

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Номер записи: 86
13-12-2012 дата публикации

Impedence controlled packages with metal sheet or 2-layer rdl

Номер: US20120313228A1
Автор: Belgacem Haba, Ellis Chau, Philip Damberg, Richard DeWitt Crisp, Wael Zohni
Принадлежит: Tessera LLC

A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces.

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Номер записи: 87
13-12-2012 дата публикации

Layered chip package and method of manufacturing same

Номер: US20120313260A1
Автор: Atsushi Iijima, Hiroshi Ikejima, Hiroyuki Ito, Yoshitaka Sasaki
Принадлежит: Headway Technologies Inc, SAE Magnetics HK Ltd

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

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Номер записи: 88
13-12-2012 дата публикации

Saw Type Package without Exposed Pad

Номер: US20120315728A1
Автор: Dana Liu, Elite Lee
Принадлежит: Shanghai Kaihong Electronic Co Ltd

In one embodiment, a method for manufacturing a saw type pad is provided. The method includes performing a first molding process to form a first molded layer beneath a pad of a lead frame. A semiconductor device is placed on the pad. A second molding process is performed to form a second molded layer. The first molded layer and the second molded layer form an encapsulation to enclose the semiconductor device and the pad. The lead frame is singulated to form an individualized semiconductor package. The pad is not exposed from a bottom surface of the semiconductor package.

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Номер записи: 89
20-12-2012 дата публикации

Method for manufacturing semiconductor device and semiconductor manufacturing apparatus

Номер: US20120318431A1
Автор: Atsushi Yoshimura, Fumihiro Iwami, Yasuo Tane, Yukio KATAMURA
Принадлежит: Toshiba Corp

In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include, upon attaching a bonding material containing a resin and a solvent to a second surface opposed to a first surface including a circuit pattern of a wafer, heating the bonding material to evaporate the solvent and decreasing vapor pressure of the solvent in an atmosphere faced with the bonding material and heating the attached bonding material to form a bonding layer.

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Номер записи: 90
20-12-2012 дата публикации

Semiconductor module manufacturing method, semiconductor module, and manufacturing device

Номер: US20120319253A1
Автор: HIROKI Mizuno
Принадлежит: Toyota Motor Corp

In the disclosed method for manufacturing a semiconductor module, a metal layer and a cooler, which have different coefficients of thermal expansion from each other, are joined into a single unit via an insulating resin sheet. A work, comprising a semiconductor element placed on the metal layer with solder interposed therebetween, is fed into a reflow furnace. The work, in that state, is heated in the reflow furnace, thereby mounting the semiconductor element to the metal layer. The heating is carried out such that the temperature of the cooler and the temperature of the metal layer differ by an amount that make the cooler and the metal layer undergo the same amount of thermal expansion as each other.

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Номер записи: 91
20-12-2012 дата публикации

Hermetically sealed wafer packages

Номер: US20120319261A1
Автор: Cody B. Moody
Принадлежит: Raytheon Co

Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.

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Номер записи: 92
27-12-2012 дата публикации

Heat dissipating structure and manufacture thereof

Номер: US20120325454A1
Автор: Daiyu Kondo, Masaki Norimatsu, Shinichi Hirose, Taisuke Iwai, Yohei Yagishita, Yoshitaka Yamaguchi, Yukie SAKITA
Принадлежит: Fujitsu Ltd

A heat dissipating structure includes a heat source; a heat dissipating part disposed to oppose to the heat source; a concave portion formed in at least one of opposing surfaces of the heat source and the heat dissipating part; and a heat conducting structure comprising a filler layer of thermoplastic material disposed between the heat source and the heat dissipating part and contacting with the opposing surfaces of the heat source and the heat dissipating part, and an assembly of carbon nanotubes that are distributed in the thermoplastic material, oriented perpendicularly to the surfaces of the filler layer, contacting, at both ends, with the opposing surfaces of the heat source and the heat dissipating part, and limited its distribution in the opposing surfaces by the concave portion.

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Номер записи: 93
27-12-2012 дата публикации

Fabrication method of semiconductor integrated circuit device

Номер: US20120329211A1
Автор: Hiroshi Maki, Yukio Tani
Принадлежит: Renesas Eastern Japan Semiconductor Inc, Renesas Electronics Corp

Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.

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Номер записи: 94
10-01-2013 дата публикации

Semiconductor device and method for manufacturing same

Номер: US20130009300A1
Автор: Hiroi Oka, Yuichi Yato
Принадлежит: Renesas Electronics Corp

A dug portion ( 50 ) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle ( 42 ) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion ( 50 ) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion ( 50 ) is smaller than a thickness of the chip. When the thickness of the chip is 100 μm or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle ( 42 ).

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Номер записи: 95
17-01-2013 дата публикации

Biaxial Drive Mechanism, Die Bonder and Die Bonder Operating Method

Номер: US20130014881A1
Автор: Koji Hosaka, shingo Fukasawa
Принадлежит: Hitachi High Tech Instruments Co Ltd

A highly reliable biaxial drive mechanism and a die bonder operating method capable of preventing fall of an elevation axis of a linear motor upon loss of power are disclosed. The biaxial drive mechanism includes a handling part; a biaxial drive axes provided with a first linear motor unit having a first movable part that moves up and down the handling part along a first linear guide and a first stationary part, and a second linear motor unit having a second movable part that moves the handling part in a horizontal direction vertical to a direction of up and down movement and a second stationary part; a main power source that supplies a power source to the biaxial drive axes; and an elevation axis fall prevention unit that prevents fall of a handling part upon loss of power at the main power source.

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Номер записи: 96
17-01-2013 дата публикации

Method of Forming a Package Substrate

Номер: US20130015234A1
Автор: Chin-Sung Lin, Li-Hua Lin, Yu-Yu Lin
Принадлежит: Global Unichip Corp, Taiwan Semiconductor Manufacturing Co TSMC Ltd

In accordance with an embodiment, a method comprises providing a substrate having a conductive material thereon, forming a ground plane, a first trace rail, and a first perpendicular trace from the conductive material, and forming an insulator material over the ground plane, the first trace rail, and the first perpendicular trace. The ground plane is between the first trace rail and an area of the substrate over which will be a die. The first trace rail extends along a first outer edge of the ground plane, and the first perpendicular trace is coupled to the first trace rail and extends perpendicularly from the first trace rail.

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Номер записи: 97
24-01-2013 дата публикации

Substrate For Integrated Modules

Номер: US20130023072A1
Автор: Hagit Avsian, Moshe Kriman
Принадлежит: DigitalOptics Corp East

A method of fabricating a plurality of components using wafer-level processing can include bonding first and second wafer-level substrates together to form a substrate assembly, such that first surfaces of the first and second substrates confront one another, the first substrate having first electrically conductive elements exposed at the first surface thereof, forming second electrically conductive elements contacting the first conductive elements, and processing the second substrate into individual substrate elements. The second conductive elements can extend through a thickness of the first substrate and can be exposed at a second surface thereof opposite the first surface. The processing can include trimming material to produce the substrate elements at least some of which have respective different controlled thicknesses between first surfaces adjacent the first substrate and second surfaces opposite therefrom.

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Номер записи: 98
31-01-2013 дата публикации

Semiconductor device, semiconductor module structure configured by vertically stacking semiconductor devices, and manufacturing method thereof

Номер: US20130026650A1
Автор: Akio Katsumata, Hiroshi Inoue, Osamu Yamagata, Satoru Itakura, Shigenori Sawachi, Yasuhiro Yamaji
Принадлежит: Individual

A semiconductor device is made up of an organic substrate; through vias which penetrate the organic substrate in its thickness direction; external electrodes and internal electrodes provided to the front and back faces of the organic substrate and electrically connected to the through vias; a semiconductor element mounted on one main surface of the organic substrate via a bonding layer, with an element circuit surface thereof facing upward; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part of this metal thin film wiring layer being exposed on an external surface; metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer; and external electrodes formed on the metal thin film wiring layer.

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Номер записи: 99
14-02-2013 дата публикации

Semiconductor assemblies with multi-level substrates and associated methods of manufacturing

Номер: US20130037949A1
Автор: Chin Hui Chong, Hong Wan Ng
Принадлежит: Micron Technology Inc

Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate.

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Номер записи: 100