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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 2500. Отображено 100.
02-02-2012 дата публикации

System with logic and embedded mim capacitor

Номер: US20120025285A1
Автор: Jeong Y. Choi
Принадлежит: Mosys Inc

An embedded memory system includes an array of random access memory (RAM) cells, on the same substrate as an array of logic transistors. Each RAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-insulator-metal capacitor in a dielectric layer. The embedded RAM system includes fewer metal layers in the logic region than in the memory region

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Номер записи: 1
09-02-2012 дата публикации

Methods of fabricating semiconductor devices having various isolation regions

Номер: US20120034757A1
Автор: Eunkee Hong, Gil-heyun Choi, Ha-Young YI, Hong-Gun Kim, Jun-Won Lee, Yong-Soon Choi
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of fabricating a semiconductor device includes forming a first trench and a second trench in a semiconductor substrate, forming a first insulator to completely fill the first trench, the first insulator covering a bottom surface and lower sidewalls of the second trench and exposing upper sidewalls of the second trench, and forming a second insulator on the first insulator in the second trench.

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Номер записи: 2
19-04-2012 дата публикации

Semiconductor device, method for forming the same, and data processing system

Номер: US20120091520A1
Автор: Nobuyuki Nakamura
Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate, a first interlayer insulating film over the semiconductor substrate, a first interconnect over the first interlayer insulating film, and a via plug penetrating the semiconductor substrate and the first interlayer insulating film. The via plug is coupled to the first interconnect.

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Номер записи: 3
26-04-2012 дата публикации

Method of forming a semiconductor device

Номер: US20120100702A1
Автор: Toshiya NAKAMORI
Принадлежит: Elpida Memory Inc

A method for forming a semiconductor device includes the following processes. A first well including a memory cell region of a semiconductor substrate is formed. A second well including a first peripheral circuit region of the semiconductor substrate is formed after forming the first well.

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Номер записи: 4
03-05-2012 дата публикации

Semiconductor device including a p-channel type mos transmitter

Номер: US20120108022A1
Автор: Kenichi Okabe, Toru Anezaki
Принадлежит: Fujitsu Semiconductor Ltd

A method of manufacturing a semiconductor device including a stacked gate type nonvolatile memory cell and a p-channel type first transistor, includes: forming a gate insulating film of the first transistor on a semiconductor substrate; forming a tunnel insulating film of the stacked gate type nonvolatile memory cell on the semiconductor substrate; forming a first conductive layer containing an n-type impurity on the tunnel insulating film and the gate insulating film; and implanting p-type impurity ions to a region of the first conductive layer for forming the first transistor to turn the region of the first conductive layer into a p-type region.

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Номер записи: 5
24-05-2012 дата публикации

Method for forming fine pattern of semiconductor device

Номер: US20120129316A1
Автор: Young-Kyun Jung
Принадлежит: Hynix Semiconductor Inc

A method for forming fine pattern includes sequentially forming a first thin film and a second thin film over a target layer for patterning, forming a partition over the second thin film, removing the partition after forming spacers on sidewalls of the partition, forming first pattern of the second thin film by etching the second thin film of a first region and the second thin film of a second region while exposing the spacers, forming second pattern of the second thin film by using the spacers as masks and etching the first pattern of the second thin film in the first region, forming first thin film pattern by using the first and second patterns of the second thin film as masks in the first and second regions and etching the first thin film, and etching the pattern target layer.

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Номер записи: 6
07-06-2012 дата публикации

Non-volatile memory device and method for fabricating the same

Номер: US20120142153A1
Автор: Yong-Sik Jeong
Принадлежит: MagnaChip Semiconductor Ltd

A method of fabricating a non-volatile memory device is provided. The method includes sequentially forming a tunnel insulation layer and a first polysilicon layer on a substrate, patterning the first polysilicon layer and the tunnel insulation layer, forming a dielectric layer to cover the patterned first polysilicon layer and the patterned tunnel insulation layer, forming a gate insulation layer on the substrate where the substrate is exposed, forming a second polysilicon layer to cover the dielectric layer, and forming a first floating gate and a second floating gate a fixed distance apart from each other, the forming of the first and second floating gates including etching middle portions of the second polysilicon layer, the dielectric layer, the patterned first polysilicon layer, and the patterned tunnel insulation layer, and separating the etched layers into two parts.

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Номер записи: 7
29-11-2012 дата публикации

Semiconductor memory device, method of manufacturing the same and method of forming contact structure

Номер: US20120299189A1
Автор: Shingo Nakajima
Принадлежит: Toshiba Corp

When a first wiring and/or a second wiring is formed, a connection portion is formed in the first wiring and/or the second wiring which covers a part of a lower electrode layer outside the memory cell array. An etching suppressing portion is formed above the connection portion. A contact hole is formed in which a portion under the etching suppressing portion reaches up to a connection potion, and the other portion reaches up to the lower electrode layer by performing etching to a laminated body in a range including the etching suppressing portion. The laminated body includes the insulating layer, the first wiring, a memory cell layer, the second wiring, and the etching suppressing portion. The contact layer is formed by burying a conductive material in the contact hole.

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Номер записи: 8
07-03-2013 дата публикации

Semiconductor memory devices including vertical transistor structures

Номер: US20130056812A1
Автор: Chulwoo PARK, Hongsun HWANG, Jin HO KIM, Sangbo Lee, Sua Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor memory device may include a common source region on a substrate, an active pattern between the substrate and the common source region, a gate pattern facing a sidewall of the active pattern, a gate dielectric pattern between the gate pattern and the active pattern, a variable resistance pattern between the common source region and the active pattern, and an interconnection line.

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Номер записи: 9
23-05-2013 дата публикации

NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130126961A1
Автор: Aochi Hideaki, FUKUZUMI Yoshiaki, ISHIDUKI Megumi, KATSUMATA Ryota, KIDOH Masaru, KITO Masaru, Komori Yosuke, Tanaka Hiroyasu
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells. 1. A non-volatile semiconductor storage device having a plurality of memory strings in each of which a plurality of electrically rewritable memory cells are connected in series , each of the memory strings comprising:first semiconductor layers each functioning as channels of the memory cells, the first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple lower ends of the pair of columnar portions;a charge storage layer formed to surround side surfaces of the columnar portions; andfirst conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer,the first conductive layers functioning as gate electrodes of the memory cells.2. The non-volatile semiconductor storage device according to claim 1 , further comprising second conductive layers formed to come into contact with the coupling portion claim 1 ,wherein the second conductive layers function as gate electrodes of transistors whose channels are formed at the coupling portion.3. The non-volatile semiconductor storage device according to claim 1 , whereinthe columnar portions are formed to be arranged in a first direction that is in parallel with the substrate, ...

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Номер записи: 10
06-06-2013 дата публикации

VERTICAL TRANSISTORS

Номер: US20130140618A1
Автор: Juengling Werner
Принадлежит: MICRON TECHNOLOGY, INC.

A semiconductor structure having U-shaped transistors includes source/drain regions at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. Methods of forming semiconductor structures are also disclosed. 1. A transistor comprising:a source region in a first pillar;a drain region in a second pillar, the first and second pillars aligned along a first axis; anda gate line elongated in a direction parallel to the first axis,wherein the source region, the drain region, and at least a portion of the gate line form a transistor.2. The transistor of claim 1 , further comprising a dielectric material filling a region between the first and second pillars.3. The transistor of claim 1 , wherein the first and second pillars comprise bulk semiconductor substrate material.4. The transistor of claim 1 , wherein the first and second pillars comprise epitaxial semiconductor material.5. The transistor of claim 1 , wherein the first pillar and the second pillar are connected by a base segment claim 1 , thereby forming a U-shaped structure claim 1 , wherein the gate line extends below the base segment.6. The transistor of claim 1 , wherein the gate line comprises a gate electrode layer and a metallic layer.7. The transistor of claim 1 , further comprising a digit line electrically connected to the source region and a memory storage device electrically ...

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Номер записи: 11
13-06-2013 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND RELATED METHOD

Номер: US20130146990A1
Автор: Park Hee-Sook
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region; forming a first interlayer insulating film; and patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions. The method further comprises forming a first ohmic film, a first barrier film, and a metal film; and removing portions of each of the metal film, the first barrier film, and the first ohmic film. 1. A semiconductor integrated circuit device comprising:a plurality of gate electrodes disposed on a cell array region and a peripheral circuit region of a semiconductor substrate;a plurality of gate capping films, wherein each of the gate capping films is disposed on one of the gate electrodes;first spacers formed on sidewalls of the gate electrodes;a first interlayer insulating film disposed on the semiconductor substrate, wherein groups of the gate electrodes are disposed in each of a plurality of first openings of the first interlayer insulating film;elevated source/drain regions, wherein each elevated source/drain region is disposed in one of a plurality of selective epitaxial films disposed on the semiconductor substrate in one of the first openings;a first ohmic film, wherein a plurality of portions of the first ohmic film are respectively disposed on at least some of the elevated source/drain regions;a first barrier film, wherein a plurality of portions of the first barrier film are respectively disposed on ...

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Номер записи: 12
20-06-2013 дата публикации

DATA STORAGE DEVICE AND METHODS OF MANUFACTURING THE SAME

Номер: US20130153998A1
Автор: Lee Jaekyu, Song Jungwoo
Принадлежит:

Provided are data storage devices and methods of manufacturing the same. The device may include a plurality of cell selection parts formed in a substrate, a plate conductive pattern covering the cell selection parts and electrically connected to first terminals of the cell selection parts, a plurality of through-pillars penetrating the plate conductive pattern and insulated from the plate conductive pattern, and a plurality of data storage parts directly connected to the plurality of through-pillars, respectively. The data storage parts may be electrically connected to second terminals of the cell selection parts, respectively. 1. A data storage device comprising:a plurality of cell selection parts formed in a substrate;a plate conductive pattern covering the cell selection parts, the plate conductive pattern electrically connected to first terminals of the cell selection parts;a plurality of through-pillars penetrating the plate conductive pattern, the plurality of through-pillars insulated from the plate conductive pattern; anda plurality of data storage parts directly connected to the plurality of through-pillars, respectively,wherein the data storage parts are electrically connected to second terminals of the cell selection parts, respectively.2. The data storage device of claim 1 , wherein each of the through-pillars is overlapped with the data storage part connected to the through-pillar in a plan view.3. The data storage device of claim 1 , wherein each of the data storage parts is directly connected to a top surface of a respective through-pillar;wherein each of the data storage parts is electrically connected to a second terminal of a cell selection part through a respective through-pillar; andwherein the data storage parts are disposed over the plate conductive pattern.4. The data storage device of claim 3 , further comprising:bit lines disposed on the data storage parts,wherein the data storage parts are arranged along rows and columns in a plan view; ...

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Номер записи: 13
01-08-2013 дата публикации

Memory Devices and Methods of Forming Memory Devices

Номер: US20130193505A1
Автор: ARITOME Seiichi, Larsen Chris, Li Di, Moradi Behnam, Prall Kirk D.
Принадлежит: MICRON TECHNOLOGY, INC.

Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. 1. A method of forming a memory device , comprising:forming a plurality of word line structures above a semiconducting substrate within a cell array area, the word line structures individually comprising gate insulation over the semiconducting substrate, a floating gate over the gate insulation, inter-gate insulation over the floating gate, and a control gate over the inter-gate insulation;performing an ion implant process to form doped implant regions in said semiconducting substrate between said word line structures within the cell array area;performing a halogen ion implantation process to implant atoms into said semiconducting substrate between said word line structures within the cell array area, the halogen ion implantation process and the ion implant process being conducted in separate ion implanting steps; andperforming at least one anneal process to cause at least some of said halogen atoms to diffuse from the semiconducting substrate into the gate insulation and the floating gate of adjacent word line structures.2. The method of claim 1 , wherein said memory device is a NAND flash memory device.3. The method of claim 1 , wherein said ion implant process is performed prior to performing said halogen ion implantation process.4. The ...

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Номер записи: 14
08-08-2013 дата публикации

SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Номер: US20130200363A1
Автор: INOUE Naoya, KANEKO Kishou, SUNAMURA Hiroshi
Принадлежит: RENESAS ELECTRONICS CORPORATION

There is provided a readily manufacturable semiconductor device including two transistors having mutually different characteristics. The semiconductor device includes a substrate, a multilayer wiring layer disposed over the substrate, a first transistor disposed in the multilayer wiring layer, and a second transistor disposed in a layer different from a layer including the first transistor disposed therein of the multilayer wiring layer, and having different characteristics from those of the first transistor. This can provide a readily manufacturable semiconductor device including two transistors having mutually different characteristics. 1. A semiconductor device , comprising:a substrate,a multilayer wiring layer disposed over the substrate,a first transistor disposed in the multilayer wiring layer, anda second transistor disposed in a different layer from a layer including the first transistor disposed therein of the multilayer wiring layer, and having a different characteristic from that of the first transistor.2. The semiconductor device according to claim 1 ,wherein the first transistor includes:a first semiconductor layer disposed in a first wiring layer of the multilayer wiring layer;first source/drain electrodes coupled with the first semiconductor layer;a first gate insulation film; anda first gate electrode coupled with the first semiconductor layer via the first gate insulation film.3. The semiconductor device according to claim 2 ,wherein the second transistor includes:a second semiconductor layer disposed in a second wiring layer different from the first wiring layer of the multilayer wiring layer;second source/drain electrodes coupled with the second semiconductor layer;a second gate insulation film; anda second gate electrode coupled with the second semiconductor layer via the second gate insulation film.4. The semiconductor device according to claim 1 ,wherein the first transistor is of a first conductivity type, andwherein the second transistor is ...

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Номер записи: 15
08-08-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130200369A1
Автор: Kato Kiyoshi, KOYAMA Jun, Yamazaki Shunpei
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

The semiconductor device includes a source line, a bit line, a first signal line, a second signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line, a second driver circuit electrically connected to the first signal line, a third driver circuit electrically connected to the second signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material. 1. A semiconductor device comprising:a first transistor comprising a gate electrode;a first insulating layer comprising an opening, wherein the gate electrode of the first transistor is positioned in the opening; an oxide semiconductor layer on the first insulating layer;', 'a first conductive layer and a second conductive layer over the oxide semiconductor layer;', 'a second insulating layer over the oxide semiconductor layer, the first conductive layer, and the second conductive layer; and', 'a gate electrode over the second insulating layer and overlapping with the oxide semiconductor layer,, 'a second transistor comprisingwherein the oxide semiconductor layer comprises indium and zinc,wherein the first conductive layer is in contact with the surface of the gate electrode of the first transistor and the first insulating layer.2. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer further comprises gallium.3. The semiconductor device according to claim 1 , wherein the first insulating layer is a silicon oxide film or a silicon oxynitride film.4. The semiconductor device according to claim 1 , wherein the surface of the first ...

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Номер записи: 16
15-08-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130207164A1
Автор: YAMAGUCHI Toshihide
Принадлежит: RENESAS ELECTRONICS CORPORATION

To suppress stress variation on a channel forming region, a semiconductor device includes an element isolating region on the semiconductor substrate principal surface, and an element forming region on the principal surface to be surrounded by the element isolating region. The principal surface has orthogonal first and second directions. A circumferential shape of the element forming region has a first side extending along the first direction. The element forming region has a first transistor region (TR), a second transistor region (TR) arranged between the first side and TR and a dummy region on the first direction side of TR TR has a first channel forming region facing the first side. TR has a second channel forming region facing the first side. The first channel forming region has a non-facing region that is not facing the second channel forming region. The dummy region faces the non-facing region in the second direction. 1. A semiconductor device comprising:a first transistor having a first gate electrode between first diffusion layers, said first gate electrode extending in a first direction which is a gate width direction;a second transistor arranged adjacent to said first transistor in said first direction, said second transistor having a second gate electrode between second diffusion layers, said second gate electrode extending in said first direction to be arranged in alignment with said first gate electrode;a first separation region arranged between said first transistor and said second transistor;a third transistor arranged adjacent to said first transistor in a second direction which is perpendicular to said first direction, and said third transistor having a third gate electrode between third diffusion layers, said third gate electrode extending in said first direction;a fourth transistor arranged adjacent to said third transistor in said first direction, and said fourth transistor having a fourth gate electrode between fourth diffusion layers, said ...

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Номер записи: 17
15-08-2013 дата публикации

PROGRAMMABLE LOGIC DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20130207170A1
Автор: KUROKAWA Yoshiyuki
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

To provide a programmable logic device in which the number of elements per bit in a memory array can be reduced and with which power consumption or operation frequency can be estimated accurately at a testing stage. Provided is a programmable logic device including a plurality of programmable logic elements and a memory array which stores configuration data that determines logic operation executed in the plurality of programmable logic elements. The memory array includes a plurality of memory elements. The memory element includes a node which establishes electrical connection between the programmable logic element and the memory array, a switch for supplying charge whose amount is determined by the configuration data to the node, holding the charge in the node, or releasing the charge from the node, and a plurality of wirings. Capacitance is formed between the node and the wiring. 1. A semiconductor device comprising:a programmable logic element; and an electrode electrically connected to the programmable logic element;', 'an insulating film over the electrode;', 'a first wiring over the electrode and the insulating film; and', 'a second wiring over the electrode and the insulating film., 'a memory element comprising2. The semiconductor device according to claim 1 ,wherein the memory element comprises a contact in the insulating film,wherein the electrode is electrically connected to one of the first wiring and the second wiring through the contact depending on configuration data,wherein the memory element is configured to supply a voltage corresponding to the configuration data from the electrode to the programmable logic element, andwherein the programmable logic element is configured to execute an operation determined by the voltage corresponding to the configuration data.3. The semiconductor device according to claim 2 ,wherein the first wiring is configured to supply a first voltage, andwherein the second wiring is configured to supply a second voltage.4. The ...

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Номер записи: 18
26-09-2013 дата публикации

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME

Номер: US20130248963A1
Автор: TAKEKIDA Hideto
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A memory cell array including a plurality of memory cell units arrayed in a matrix configuration along a first direction and a second direction which is perpendicular direction to the first direction, each memory cell unit including a plurality of memory cell transistors, a first select gate transistor and a second select gate transistor, word lines extending to the first direction, and a first insulating film formed on an upper surface of the memory cell array, a first embedded wiring layer embedded in the first embedded wiring layer, the first embedded wiring layer including a wiring portion commonly connected to a source region of each first select gate transistor, wherein the first embedded wiring layer has an inclined pattern which extends in a direction not parallel to either of the first and the second directions. 1. A nonvolatile semiconductor memory device , comprising:a memory cell array including a plurality of memory cell units arrayed in a matrix configuration along a first direction and a second direction which is perpendicular direction to the first direction, each memory cell unit including a plurality of memory cell transistors connected in series, a first select gate transistor connected to a first end of the memory cell unit, and a second select gate transistor connected to a second end of the memory cell unit word lines extending to the first direction, each of which is commonly connected to control gate electrodes of memory transistors disposed to the first direction, anda first insulating film formed on an upper surface of the memory cell array,a first embedded wiring layer embedded in the first embedded wiring layer, the first embedded wiring layer including a wiring portion commonly connected to a source region of each first select gate transistor,wherein the first embedded wiring layer has an inclined pattern in which extends in a direction not parallel to either the first and the second direction.2. The memory device of claim 1 , wherein ...

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Номер записи: 19
26-09-2013 дата публикации

NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130248970A1
Автор: KAI Naoki, Nagashima Satoshi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A method of manufacturing a nonvolatile semiconductor storage device includes filling an element isolation trench with a sacrificial film; etching a laminate of films to form a plurality of first and second gate electrodes such that the first gate electrodes are disposed in a first region, and the second gate electrodes are disposed in a second region adjacent to the first region; removing the sacrificial film; forming a resist having an opening in the first region; forming a barrier insulating film so as to at least cover an edge of the opening; etching back the barrier insulating film and thereafter removing the resist film; forming an insulating film to form an unfilled gap in the element isolation trench located below the second gate electrode, the second region, and the third region. 1. A method of manufacturing a nonvolatile semiconductor storage device , comprising:forming a gate insulating film and a first electrode film in the listed sequence above a semiconductor substrate;forming an element isolation trench along a first direction into the first electrode film, the gate insulating film, and the semiconductor substrate to define an element region isolated in a second direction;filling the element isolation trench with a sacrificial film;forming an interelectrode insulating film, and a second electrode film in the listed sequence above the element region and the sacrificial film;etching the second electrode film, the interelectrode insulating film, and the first electrode film along a second direction to form a plurality of first gate electrodes and a plurality of second gate electrodes such that the first gate electrodes are disposed in a first region, and the second gate electrodes are disposed in a second region adjacent to the first region,selectively removing the sacrificial film in the element isolation trench after the formation of the first and the second gate electrodes; andforming a resist, after the removal of the sacrificial film, and patterning ...

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Номер записи: 20
26-09-2013 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE DEVICE

Номер: US20130248971A1
Автор: Matsuno Koichi, Miyazaki Shoichi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

Method of manufacturing a semiconductor device includes forming, in a first region, a first trench through a second gate electrode film and an interelectrode insulating film, and a second trench partially extending into a sacrificial film in an isolation trench, filling the second trench with a first insulating film; forming a third gate electrode film above the second gate electrode film and into the first trench such that the third gate electrode film contacts the first gate electrode film; etching the third and the second gate electrode film, the interelectrode insulating film, and the first gate electrode film to form select gate electrodes in the first region and a group of memory-cell gate electrodes in the second region; removing the sacrificial film; and forming a second insulating film over the element regions and the isolation trench to define an unfilled gap in the isolation trench below the memory-cell gate electrodes. 1. A method of manufacturing a semiconductor storage device , comprising:forming a first gate insulating film and a first gate electrode film in the listed sequence above a first region and a second region of a semiconductor substrate;forming an element isolation trench along a first direction into the first gate electrode film, the first gate insulating film, and an upper portion of the semiconductor substrate to define a plurality of element regions extending in the first direction and being isolated from one another in a second direction intersecting with the first direction;filling the element isolation trench with a sacrificial film;forming an interelectrode insulating film along the first gate electrode film and the sacrificial film;forming a second gate electrode film above the interelectrode insulating film;forming, in the first region, a first trench extending through the second gate electrode film and the interelectrode insulating film, and a second trench extending through the second gate electrode film and the interelectrode ...

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Номер записи: 21
03-10-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Номер: US20130256769A1
Автор: JEONG Jin-Won, LEE WONCHUL
Принадлежит:

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include storage node pads disposed adjacent to each other between word lines but spaced apart from each other by an isolation pattern. Accordingly, it is possible to prevent a bridge problem from being caused by a mask misalignment. This enables to improve reliability of the semiconductor device. 1. A semiconductor device , comprising:a substrate having a recess partially defined by a sidewall, the substrate having a top surface;a device isolation layer provided in the recess, the device isolation layer having a top surface lower than the top surface of the substrate;a memory element disposed on the substrate; andone or more first contacts electrically connected to the memory element,wherein at least one of the first contacts is in contact with the top surface of the substrate and is formed adjacent to the sidewall of the recess.2. The device of claim 1 , further comprising an interlayer insulating layer claim 1 , wherein substantially an entire side surface of at least one of the first contacts is in contact with an insulation layer having an etch selectivity with respect to the interlayer insulating layer.3. The device of claim 2 , wherein the insulation layer comprises nitride.4. The device of claim 1 , wherein the device further comprises an isolation pattern provided between adjacent ones of the first contacts.5. The device of claim 4 , wherein at least one of the first contacts includes a contact pad claim 4 , and wherein a top surface of the isolation pattern is substantially coplanar with a top surface of the contact pad.6. The device of claim 4 , wherein a bottom surface of the isolation pattern is lower than the top surface of the substrate.7. The device of claim 1 , further comprising claim 1 ,a word line capping layer pattern adjacent to at least one of the first contacts; anda word line extending along a first direction below the word line capping ...

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Номер записи: 22
10-10-2013 дата публикации

HIGH-VOLTAGE TRANSISTOR HAVING SHIELDING GATE

Номер: US20130264627A1
Автор: KAMIGAICHI Takeshi, KUTSUKAKE Hiroyuki, SUGIMAE Kikuko
Принадлежит:

A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region. 14.-. (canceled)5. A semiconductor device comprising:first, second, third, and fourth high-voltage transistors arranged on a main surface of a semiconductor substrate, the first and second high-voltage transistors being adjacent each other in the gate-width direction, the third and fourth high-voltage transistors being adjacent each other in the gate-width direction, the first and third high-voltage transistors being adjacent each other in the gate-length direction, the second and fourth high-voltage transistors being adjacent each other in the gate-length direction, and each of the transistors having a gate electrode, and a gate electrode contact formed on the gate electrode;a first wiring formed on the gate electrode contact of the first high-voltage transistor;a second wiring formed on the gate electrode contact of the second high-voltage transistor;a third wiring formed on the gate electrode contact of the third high-voltage transistor;a fourth wiring formed on the gate electrode contact of the fourth high-voltage transistor; anda shielding gate provided on a portion of an element isolation region which lies between the first ...

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Номер записи: 23
17-10-2013 дата публикации

Three-dimensional semiconductor memory devices and methods of fabricating the same

Номер: US20130270643A1
Автор: Bumsu Kim, Dongchul Yoo, Hyun Park, Jae-Young Ahn, Jongsik Chun, Juyul Lee, Kihyun Hwang, Kwangmin Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A three-dimensional (3D) semiconductor memory device includes an electrode separation pattern, a stack structure, a data storage layer, and a channel structure. The electrode separation pattern is disposed on a substrate. A stack structure is disposed on a sidewall of the electrode separation pattern. The stack structure includes a corrugated sidewall opposite to the sidewall of the electrode separation pattern. The sidewall of the electrode separation pattern is vertical to the substrate. A data storage layer is disposed on the corrugated sidewall. A channel structure is disposed on the charge storage layer.

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Номер записи: 24
24-10-2013 дата публикации

Display panel

Номер: US20130277674A1
Автор: Bon-Yong Koo, Kyung-Wook Kim
Принадлежит: Samsung Display Co Ltd

A display panel includes an insulation substrate having a display area and a peripheral area, wires disposed on the insulation substrate in the display area, first and second testing lines disposed on the insulation substrate and aligned substantially parallel to each other, and a diode unit disposed between the wires and one of the first testing line and the second testing line. The wires extend from the display area into the peripheral area and through diodes included in the diode unit, and the wires are electrically connected to the one of the first testing line and the second testing line.

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Номер записи: 25
07-11-2013 дата публикации

Memory Cells, Memory Cell Arrays, Methods of Using and Methods of Making

Номер: US20130292635A1
Автор: Widjaja Yuniarto
Принадлежит:

A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region. 138-. (canceled)39. A semiconductor memory array comprising:a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include:a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell; anda nonvolatile memory comprising a resistance change element configured to store data stored in said floating body upon transfer thereto,wherein said transfer is performed to said at least two of said memory cells in parallel.40. The semiconductor memory array of claim 39 , wherein said resistance change element comprises a phase change material.41. The semiconductor memory array of claim 39 , wherein said resistance change element comprises a metal-oxide-metal system.42. The semiconductor memory array of claim 39 , ...

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Номер записи: 26
07-11-2013 дата публикации

ACTIVE MATRIX SUBSTRATE

Номер: US20130292681A1
Автор: Horiuchi Satoshi, Mitsumoto Kazuyori, YOSHIDA Masahiro
Принадлежит: SHARP KABUSHIKI KAISHA

The active matrix substrate is provided with: first and second scan lines () that extend in a first direction; first and second signal lines () that extend in a second direction; first and second pixels () that are arranged adjacent to each other along the second direction; an auxiliary capacitor line (); first and second pixel electrodes (); a first TFT (); a second TFT (); an auxiliary capacitor electrode () that is connected to the auxiliary capacitor line () and extends below the first and second pixel electrodes (); a first auxiliary capacitor counter electrode () that is connected to the first pixel electrode (); and a second auxiliary capacitor counter electrode () that is connected to the second pixel electrode (). 1. An active matrix substrate , comprising:a plurality of scan lines extending along a first direction, the plurality of scan lines including a first scan line and a second scan line that are adjacent to each other;a plurality of signal lines extending along a second direction, the plurality of signal lines including a first signal line and a second signal line that are adjacent to each other;a plurality of pixels arranged in a matrix, the plurality of pixels including a first pixel and a second pixel that are adjacent to each other along the second direction;an auxiliary capacitance line;a first pixel electrode for the first pixel and a second pixel electrode for the second pixel that are disposed in a region surrounded by the first scan line, the second scan line, the first signal line, and the second signal line;a first TFT for the first pixel, the first TFT being connected to the first signal line;a second TFT for the second pixel, the second TFT being connected to the second signal line;an auxiliary capacitance electrode connected to the auxiliary capacitance line, the auxiliary capacitance electrode extending under the first pixel electrode and the second pixel electrode;a first auxiliary capacitance opposite electrode for the first pixel, ...

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Номер записи: 27
28-11-2013 дата публикации

DISPLAY APPARATUS

Номер: US20130313557A1
Автор: Akamatsu Keiichi, Kato Yuichi, Masuda Kenta
Принадлежит: SONY CORPORATION

A display apparatus includes a scanning line to which a scanning signal is input, a signal line arranged perpendicular to the scanning line to which an image signal is input, a storage capacity line arranged in parallel with the signal line, an insulating film having a gate insulating portion that covers a gate electrode of a transistor, a pixel electrode connected to the transistor, a capacitor including a first electrode and a second electrode, the first electrode connected to the storage capacity line, the second electrode connected to the pixel electrode, and a protection film having a first insulating portion and a second insulating portion, the first insulating portion covering a source electrode and a drain electrode, the second insulating portion provided between the first electrode and the second electrode, the first electrode and the second electrode arranged to face each other with the second insulating portion disposed therebetween. 1. A display apparatus , comprising:a scanning line to which a scanning signal is input;a signal line to which an image signal is input and which is arranged perpendicular to the scanning line;a storage capacity line arranged in parallel with the signal line;an insulating film having a gate insulating portion that covers a gate electrode of a transistor;a pixel electrode connected to the transistor;a capacitor including a first electrode and a second electrode, the first electrode being connected to the storage capacity line, the second electrode being connected to the pixel electrode; anda protection film having a first insulating portion and a second insulating portion, the first insulating portion covering a source electrode and a drain electrode of the transistor, the second insulating portion being provided between the first electrode and the second electrode, the first electrode and the second electrode being arranged to face each other with the second insulating portion of the protection film disposed therebetween.2. ...

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Номер записи: 28
28-11-2013 дата публикации

MEMORY HAVING BURIED DIGIT LINES AND METHODS OF MAKING THE SAME

Номер: US20130314967A1
Автор: Huang Wen Kuei, Hwang David, Lin Ching Kai, PAREKH KUNAL, Wang Kuo Chen
Принадлежит: MICRON TECHNOLOGY, INC.

A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4Farchitecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device. 1. A memory cell comprising:a storage device;a vertical access device electrically coupled to the storage device;a word line electrically coupled to the vertical access device; anda buried digit line electrically coupled to the vertical access device and disposed below the storage device, the word line, and the vertical access device.2. The memory cell of claim 1 , wherein the word line and the buried digit line are orthogonal to each other.3. The memory cell of claim 1 , wherein the storage device is disposed above the vertical access device.4. The memory cell of claim 1 , wherein the storage device is disposed above the word line.5. The memory cell of claim 1 , wherein the storage device comprises a capacitor.6. The memory cell of claim 1 , wherein the vertical access device comprises a finFET.7. The memory cell of claim 6 , wherein the finFET comprises a fin claim 6 , and the vertical height of the word line is greater than two times the thickness of the fin.8. The memory cell of claim 1 , wherein the memory cell comprises at least two vertical access devices claim 1 , each of which is disposed above the buried digit line.9. The memory cell of claim 8 , wherein the memory cell comprises at least two word lines electrically coupled to the vertical access devices.10. A memory array comprising:a memory cell having two vertical access devices electrically coupled to and disposed below a storage device;a word line ...

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Номер записи: 29
19-12-2013 дата публикации

3D MEMORY HAVING VERTICAL SWITCHES WITH SURROUND GATES AND METHOD THEREOF

Номер: US20130336037A1
Автор: Cernea Raul Adrian, Chen Yung-Tin, Radigan Steven J., Scheuerlein Roy E.
Принадлежит: SanDisk 3D LLC

A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs. 1. A 3D memory having memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x , y and z-directions and with a plurality of parallel planes stacked in the z-direction , said memory having a multi-layer structure on top of a substrate , the multi-layer structure including a multi-plane memory layer , said 3D memory further comprising:a 2-D array in an x-y plane of conductive pillars as bit line pillars elongated in the z-direction through the plurality of planes, the 2-D array of bit line pillars being spaced apart in the x-direction and the y-direction by a spacing Lx and a spacing Ly respectively and a difference between the spacing Ly and the spacing Lx given by a spacing Ls;a 2D array of isolated TFT channels in the x-y plane, each TFT channel being in-line with and having a first end connected to one end of one of the bit line pillars along the z-direction;a layer of gate material surrounding each TFT channel but isolated from the TFT channel by an intermediate oxide layer, said layer of gate material having a thickness that fills a space between adjacent TFT channels in the x-direction to form a select gate line along the y-direction, thereby leaving a select ...

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Номер записи: 30
09-01-2014 дата публикации

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD OF THE SAME

Номер: US20140010016A1
Автор: HAZAMA Hiroaki, Higuchi Masaaki, KATSUMATA Ryota, Sekine Katsuyuki
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A nonvolatile semiconductor memory device includes a semiconductor substrate and memory transistors, each of which has a laminate formed by alternately laminating insulating films and conductive films on the semiconductor substrate, a silicon pillar going through the laminate, a tunnel insulating film arranged on the surface of the silicon pillar facing the laminate, a charge accumulating layer arranged on the surface of the tunnel insulating film facing the laminate, and a block insulating film arranged on the surface of the charge accumulating layer facing the laminate and in contact with the conductive film. During a data deletion operation, a voltage is applied on the conductive film so that the potential of the silicon pillar with respect to the conductive film decreases as the cross-sectional area of the silicon pillar decreases. 1. A nonvolatile semiconductor memory device comprising:a semiconductor substrate;a laminate including insulating films and conductive films alternately formed above the semiconductor substrate;a silicon pillar formed through the laminate to have a tapered cross-section;a tunnel insulating film disposed on a surface of the silicon pillar facing the laminate;a charge accumulating layer disposed on a surface of the tunnel insulating film facing the laminate; anda block insulating film disposed on a surface of the charge accumulating layer facing the laminate and in contact with the conductive film,wherein, when a voltage is applied on the conductive film during a data deletion operation for the nonvolatile semiconductor memory device, the potential of the silicon pillar with respect to the conductive film decreases as the cross-sectional area of the silicon pillar becomes smaller.2. The nonvolatile semiconductor memory device according to claim 1 , wherein a plurality of memory transistors are formed through layers of the laminate.3. The nonvolatile semiconductor memory device according to claim 2 , wherein the data deletion operation ...

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Номер записи: 31
16-01-2014 дата публикации

INTEGRATED CIRCUIT HAVING MEMORY CELL ARRAY INCLUDING BARRIERS, AND METHOD OF MANUFACTURING SAME

Номер: US20140017868A1
Автор: FAZAN Pierre C.
Принадлежит: MICRON TECHNOLOGY, INC.

An integrated circuit device having (i) a memory cell array which includes a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the body region of each transistor is electrically floating and (ii) the transistors of adjacent memory cells have a common first region and/or a common second region. Each common first region and/or second regions of transistors of adjacent memory cells includes a barrier disposed therein and/or therebetween, wherein each barrier provides a discontinuity in the common regions and/or includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common regions. 1. A method of manufacture of an integrated circuit device having a memory cell array including a plurality of memory cells , arranged in a matrix of rows and columns , wherein each memory cell includes at least one transistor having a gate , gate dielectric and first , second and body regions , the method comprising:forming the first regions of the transistors in a semiconductor, wherein the first regions of the transistors of adjacent memory cells are common regions;forming the second regions of the transistor in the semiconductor;etching a trench in each of the common first regions to remove a portion of the common first regions;depositing a barrier in each trench in each common first region, wherein each barrier includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common first regions; anddepositing an electrical contact on each of the common first region and associated barrier which is disposed therein and/or therebetween.2. The method of manufacture of wherein the barriers include one or more materials that are different from the material of the common first regions.3. The method ...

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Номер записи: 32
30-01-2014 дата публикации

Structures and operational methods of non-volatile dynamic random access memory devices

Номер: US20140029340A1
Автор: Lee Wang
Принадлежит: Individual

A Dynamic Random Access Memory (DRAM) cell and a semiconductor Non-Volatile Memory (NVM) cell are incorporated into a single Non-Volatile Dynamic Random Access Memory (NVDRAM) cell. The NVDRAM cell is operated as the conventional DRAM cell for read, write, and refreshment on dynamic memory applications. Meanwhile the datum in the NVM cells can be directly loaded into the correspondent DRAM cells in the NVDRAM cell array without applying intermediate data amplification and buffering leading to high speed non-volatile data access. The datum in DRAM cells can be also stored back to the correspondent semiconductor NVM cells in the NVDRAM cells for the datum required for non-volatile data storage. The NVDRAM of the invention can provide both fast read/write function for dynamic memory and non-volatile memory storage in one unit memory cell.

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Номер записи: 33
13-02-2014 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20140042512A1
Автор: Jeon Yoo Nam
Принадлежит: SK HYNIX INC.

A semiconductor device includes word lines stacked in a cell region of a substrate and each of the word lines includes a first conductive layer. At least one selection line is stacked on top of the word lines and includes a second conductive layer. At least one gate line is formed in a peripheral region of the substrate and includes the second conductive layer. 1. A semiconductor device , comprising:word lines stacked in a cell region of a substrate, wherein each of the word lines is a first conductive layer;at least one selection line, formed of a second conductive layer, stacked on top of the word lines; andat least one gate line, formed of the second conductive layer, formed in a peripheral region of the substrate.2. The semiconductor device of claim wherein the first conductive layer includes a metal layer , and the second conductive layer includes a polysilicon layer.3. The semiconductor device of claim 1 , further comprising a pipe gate formed between the substrate and the word lines.4. The semiconductor device of claim 1 , further comprising:first contact plugs connected to the word lines;at least one second contact plug connected to the at least one selection line; andat least one third contact plug connected to the at least one gate line.5. The semiconductor device of claim 1 , further comprising channel layers passing through the word lines and the at least one selection line.6. A semiconductor device claim 1 , comprising:metal layers stacked in a cell region of a substrate;at least one first polysilicon layer formed over the metal layers; andat least one second polysilicon layer formed in a peripheral region of the substrate.7. The semiconductor device of claim 6 , wherein the metal layers are word lines claim 6 , the at least one first polysilicon layer is a selection line claim 6 , and the at least one second polysilicon layer is a gate line.8. The semiconductor device of claim 6 , further comprising semiconductor pillars passing through the metal ...

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Номер записи: 34
06-03-2014 дата публикации

DISPLAY DEVICE

Номер: US20140061638A1
Автор: Umezaki Atsushi
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included. 1. (canceled)2. A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; and a seventh transistor ,wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,wherein one of a source and a drain of the third transistor is electrically connected to a fourth wiring,wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the sixth transistor,wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the sixth transistor,wherein one of a source ...

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Номер записи: 35
06-03-2014 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20140061750A1
Автор: KWON Oh Chul, Lee Ki Hong, Pyi Seung Ho
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes a first substrate on which a cell region is defined. In the cell region, memory cells are stacked. A second substrate is located above the first substrate, and a peripheral region is defined on the second substrate. One or more conductive lines are located in the peripheral region. The one or more lines extend through the second substrate and couple to the cell region. 1. A semiconductor memory device , comprising:a first substrate on which a cell region is defined, the cell region comprising memory cells that are stacked;a second substrate located above the first substrate, wherein a peripheral region is defined on the second substrate; andone or more conductive lines located in the peripheral region, wherein the one or more conductive lines extend through the second substrate and are coupled to the cell region.2. The semiconductor device of claim 1 , wherein the conductive lines comprise:first conductive lines coupled to the memory cells and located under the second substrate; andsecond conductive lines extending above the second substrate and, the second conductive lines being coupled to the first conductive lines through the second substrate.3. The semiconductor device of claim 1 , further comprising:at least one transistor formed on the second substrate; andat least one third conductive line coupled to transistors formed in the peripheral region, wherein the at least one third conductive line is located above the second substrate.4. The semiconductor device of claim 1 , further comprising:a stacked structure formed in the cell region over the first substrate and including a plurality of first material layers and a plurality of second material layers stacked alternately on top of one another; andan insulating layer covering the stacked structure and formed between the first substrate and the second substrate.5. The semiconductor device of claim 4 , wherein the plurality of first material layers comprises a conductive layer ...

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Номер записи: 36
06-03-2014 дата публикации

SEMICONDUCTOR DEVICE INCLUDING BURIED GATE, MODULE AND SYSTEM, AND METHOD FOR MANUFACTURING

Номер: US20140064004A1
Автор: JANG Tae Su
Принадлежит: SK HYNIX INC.

An embodiment of the semiconductor device includes a recess formed in an active region, a gate buried in a lower part of the recess, a first capping insulation film formed over the gate, a second capping insulation film formed over the first capping insulation film, and a third capping insulation film formed over the second capping insulation film. In the semiconductor device including the buried gate, mechanical stress caused by a nitride film can be reduced by reducing the volume of a nitride film in a capping insulation film formed over a buried gate, and the ratio of silicon to nitrogen of the nitride film is adjusted, so that mechanical stress is reduced, resulting in improvement of operation characteristics of the semiconductor device. 1. A semiconductor device comprising:a recess formed in an active region;a gate buried in a lower part of the recess;a first capping insulation film formed over the gate;a second capping insulation film formed over the first capping insulation film; anda third capping insulation film formed over the second capping insulation film so as to fill the recess.2. The semiconductor device according to claim 1 , wherein the first capping insulation film comprises a silicon nitride film having a higher nitrogen ratio than a SiNmaterial.3. The semiconductor device according to claim 1 , wherein the first capping insulation film is formed over a sidewall of the recess and over the gate.4. The semiconductor device according to claim 1 , wherein the second capping insulation film includes an oxide film in which the first capping insulation film is partially oxidized.5. The semiconductor device according to claim 1 , wherein the third capping insulation film comprises a silicon nitride film having a higher nitrogen ratio than a SiNmaterial.6. The semiconductor device according to claim 1 , wherein the third capping insulation film includes an oxide film.7. The semiconductor device according to claim 6 , wherein the third capping insulation ...

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Номер записи: 37
06-03-2014 дата публикации

METHOD OF MAKING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING

Номер: US20140065772A1
Автор: GROSS JOHN NICHOLAS, Liu David
Принадлежит: INVENSAS CORPORATION

A programmable non-volatile device is made with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. 1a. said MOTP memory cell has a drain region capacitively coupled to a floating gate;b. any and all regions and structures of said MOTP memory cell are formed in common with corresponding regions and structures used as components of the additional logic and/or non-MOTP memory devices; andc. an amount of capacitive coupling between said floating gate and said drain region can be varied during a program operation to store multiple bits of data within a single MOTP memory cell.. A method of forming a multi-level one-time programmable (MOTP) memory cell incorporated on a silicon substrate with one or more other additional logic and/or non-MOTP memory devices, characterized in that: The present application is a divisional of U.S. patent application Ser. No. 12/271,666, filed Nov. 14, 2008, which is a continuation-in-part of U.S. patent application Ser. No. 12/264,029, now U.S. Pat. No. 7,782,668; Ser. No. 12/264,060, now U.S. Pat. No. 7,787,304; and Ser. No. 12/264,076, now U.S. Pat. No. 7,787,309, all filed Nov. 3, 2008, which claim priority of U.S. Provisional Patent Application No. 60/987,869, filed Nov. 14, 2007, all of which are incorporated herein by reference.The present invention relates to making non-volatile memories with variable coupling which can be programmed one time, or multiple times in some instances. The invention has particular applicability to applications where is it desirable to customize ...

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Номер записи: 38
13-03-2014 дата публикации

SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20140070296A1
Автор: Matsuno Koichi, Yanai Yoshihiro
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A semiconductor storage device according to the present embodiment includes a semiconductor substrate. A memory cell array includes a plurality of memory cells provided on the semiconductor substrate in an array direction. A selection gate transistor is provided on an end of the memory cell array, and is used to select the memory cells from the memory cell arrays. A dummy cell is provided between a gate electrode of one of the memory cells on the end of the memory cell array and a gate electrode of the selection gate transistor. The width of a gate electrode of the dummy cell in the array direction of the memory cells and the dummy cell is twice or more as large as the width of the gate electrode of one of the memory cells. 1. A semiconductor storage device comprising:a semiconductor substrate;a memory cell array comprising a plurality of memory cells provided on the semiconductor substrate in an array direction;a selection gate transistor provided on an end of the memory cell array, and used to select the memory cells from the memory cell arrays; anda dummy cell provided between a gate electrode of one of the memory cells on the end of the memory cell array and a gate electrode of the selection gate transistor, whereina width of a gate electrode of the dummy cell in the array direction of the memory cells and the dummy cell is twice or more as large as a width of the gate electrode of one of the memory cells.2. The device of claim 1 , whereingate electrodes of the memory cells are arranged at a first pitch in the array direction, andan interval between the gate electrode of the dummy cell and the gate electrode of the selection gate transistor in the array direction is almost equal to the first pitch.3. The device of claim 1 , wherein a half pitch of a minimum processing size by a lithographic technique in a manufacturing process of the semiconductor storage device is equal to or smaller than 20 nm.4. The device of claim 2 , wherein a half pitch of a minimum ...

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Номер записи: 39
13-03-2014 дата публикации

SEMICONDUCTOR STORAGE DEVICE AND FABRICATION METHOD THEREOF

Номер: US20140070297A1
Автор: Meguro Hisataka, Yamasaki Hiroyuki
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, the semiconductor storage device includes a semiconductor substrate, a first pair of selection-gate electrodes including a first conductor layer and a second conductor layer, a second pair of selection-gate electrodes, a memory cell region formed in the area sandwiched by the first pair of selection-gate electrodes and the second pair of selection-gate electrodes, an interlayer-insulating film, a first contact provided between the first pair of selection gates and penetrates through the interlayer-insulating film and the first conductive film layer and is connected on the surface of the semiconductor substrate, and a second contact provided between the second pair of selection gates, in which first contact is connected to the first conductive film layer via an insulating film on the side surface thereof. 1. A semiconductor storage device , comprising:a semiconductor substrate;a first pair of selection-gate electrodes including a first conductive layer and a second conductive layer;a second pair of selection-gate electrodes;a memory cell region formed in a matrix pattern between the first pair of selection-gate electrodes and the second pair of selection-gate electrodes;an interlayer-insulating film covering the first pair of the selection-gate electrodes, the second pair of selection-gate electrodes, and the memory cell region,a first contact provided between the first pair of selection gates; anda second contact provided between the second pair of selection gates, whereinthe first contact penetrates through at least the interlayer-insulating film and the first conductive film layer and is connected on a surface of the semiconductor substrate;an insulating film is formed on the first contact, andthe first contact is at least connected to the first conductive film layer via the insulating film on a side surface of the first contact.2. The semiconductor storage device according to claim 1 , whereinthe second contact penetrates through at ...

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Номер записи: 40
13-03-2014 дата публикации

System and Method for Operation of Isfet Arrays Using pH Inert Reference Sensors

Номер: US20140073511A1
Автор: Bappal Arthika, Basuray Sagnik, Ferreri Gianni Calogero, Gomes Xavier Victor, Shenoy Suresh Gopalkrishna, WONG Chiu Tai Andrew
Принадлежит:

An embodiment of a method for sequencing a species of nucleic acid template using pH inert reference sensors is described that comprises the steps of: introducing a nucleotide species to an array of wells where a plurality of the wells comprise a species of nucleic acid template and a plurality of the wells comprise a plurality of functional groups with a high pH buffering characteristic, and in at least a first well a polymerase species incorporates the nucleotide species into a plurality of strands complementary to the species of nucleic acid template disposed in the first well and results in a release of a plurality of hydrogen ions; detecting a signal in the first well that is responsive to the hydrogen ions and one or more noise sources; detecting a signal in a second well comprising the functional groups with the high pH buffering characteristic that is responsive to the one or more noise sources; and subtracting the second well signal from the first well signal to generate a corrected signal associated with the detected hydrogen ions. 1. A method for sequencing a species of nucleic acid template using pH inert reference sensors , comprising the steps of:(a) introducing a nucleotide species to an array of wells wherein a plurality of the wells comprise a species of nucleic acid template and a plurality of the wells comprise a plurality of functional groups with a high pH buffering characteristic, and wherein in at least a first well a polymerase species incorporates the nucleotide species into a plurality of strands complementary to the species of nucleic acid template disposed in the first well and results in a release of a plurality of hydrogen ions;(b) detecting a signal in the first well, wherein the signal is responsive to the hydrogen ions and one or more noise sources;(c) detecting a signal in a second well comprising the functional groups with the high pH buffering characteristic, wherein the signal is responsive to the one or more noise sources; and(d ...

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Номер записи: 41
20-03-2014 дата публикации

SEMICONDUCTOR DEVICE INCLUDING FINFET DEVICE

Номер: US20140077146A1
Автор: Kakoschke Ronald, SCHRUEFER Klaus
Принадлежит:

A memory element includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element. 1. An apparatus , comprising , comprising:a memory element having two terminals;a source line, extending in a first direction above the surface of a substrate;a pair of fins, extending in parallel in a second direction above the surface of the substrate, each of the fins being partially wrapped around by the source line;a local interconnect extending in the first direction above the surface of the substrate, contacting one terminal of the memory element, and partially wrapping around the pair of fine;a gate line extending in the first direction above the surface of the substrate, arranged between the source line and the local interconnect, and partially wrapping around the pair of the fins; anda bit line coupled to another terminal of the memory element, and extending in the second direction above the substrate, but not in contact with the source line and the gate line.2. The apparatus of claim 1 , wherein the memory element is a NVM.3. The apparatus of claim 1 , wherein the memory element is selected from the group of elements consisting of PCRAM claim 1 , NRAM claim 1 , CMRAM claim 1 , and FeRAM.4. The apparatus of claim 1 , wherein the local interconnect is made of a conductive material.5. The apparatus of claim 1 , wherein the local interconnect is made of a conductive material selected from the one or more of copper claim 1 , silver claim 1 , gold claim 1 , aluminum claim 1 , and their alloys.6. A memory device claim 1 , comprising:a memory element;a pair of fins extending in parallel;a gate line coupled to each of the pair of fins; anda local interconnect coupled between the memory element and and the pair of fins, the local interconnect being in direct contact with a top surface of each of the pair of fins.7. The memory device of claim 6 , wherein the local interconnect ...

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Номер записи: 42
20-03-2014 дата публикации

VERTICAL-TYPE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

Номер: US20140080273A1
Автор: Kang Jong-Hyuk, Lee Jong-Wook, Son Yong-Hoon
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated. 1. A method of manufacturing a vertical-type non-volatile memory device , comprising:alternatively stacking two different layers on a substrate to form a multi-layered structure,forming a trench penetrating the different layers vertically with respect to the substrate;forming a tunnel oxide layer, a charge-trapping layer and a blocking dielectric layer in the trench;forming a semiconductor layer in the trench;forming a layer including metal on the semiconductor layer;thermally treating the layer including metal and the semiconductor layer; andremoving the layer including metal.2. The method of claim 1 , wherein forming the multi-layered structure comprises:partially etching the stacked layers of sacrificial layers and insulation interlayers to form an opening that has a linear shape extending in a first direction and exposes a surface of the substrate;forming an insulation layer pattern in the opening, the insulation layer pattern being spaced apart from a sidewall of the opening;forming a semiconductor pattern on both sidewalls of the opening to fill the opening, the semiconductor pattern having a pillar shape;3. The method of claim 2 , wherein forming the trench penetrating the different layers comprises:removing a portion of the multi-layered structure between the semiconductor patterns to form a first opening that extends in a first direction; andremoving the sacrificial layer exposed through the first ...

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Номер записи: 43
20-03-2014 дата публикации

SEMICONDUCTOR DEVICE HAVING A RESISTOR AND METHODS OF FORMING THE SAME

Номер: US20140080278A1
Автор: CHO SEONG SOON, Chol Seungwook, KIM Minchul, Shin Jinhyun
Принадлежит:

In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure. 1. A method of forming a semiconductor device including a first region and a second region comprising:providing a gate insulating layer on a substrate, the substrate having an upper surface;providing isolating structures in the substrate in the first region and in the second region;providing a first gate electrode layer on the gate insulating layer in the first region and in the second region;removing portions of the first gate electrode layer and the gate insulating layer in the second region to expose the isolating structures in the second region;removing upper portions of the exposed isolating structures to recess the isolating structures in the substrate so that top surfaces of the isolating structures are lower in height than the upper surface of the substrate;providing a second gate electrode layer in the first region on the first gate electrode layer and in the second region on the recessed isolating structures; andpatterning the second gate electrode layer, the first gate electrode layer, and the gate insulating layer in the first region to form first gate structures in the first region, and patterning the second gate electrode layer to form resistor patterns on the recessed isolating structures in the second region.2. The method of wherein the first region comprises a cell region of the device claim 1 , wherein the first gate structures comprise ...

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Номер записи: 44
27-03-2014 дата публикации

DISPLAY PANEL

Номер: US20140084294A1
Автор: KIM Kyung-Wook, Koo Bon-Yong
Принадлежит: Samsung Display Co., Ltd.

A display panel includes an insulation substrate having a display area and a peripheral area, wires disposed on the insulation substrate in the display area, first and second testing lines disposed on the insulation substrate and aligned substantially parallel to each other, and a diode unit disposed between the wires and one of the first testing line and the second testing line. The wires extend from the display area into the peripheral area and through diodes included in the diode unit, and the wires are electrically connected to the one of the first testing line and the second testing line. 1. A display panel comprising:an insulation substrate including a display area and a peripheral area;wires disposed in the display area; anda diode unit connected to portions of the wires which extend into the peripheral area from the display area,wherein the wires pass through diodes in the diode unit and extend such that one end of the wires corresponds to an edge of the insulation substrate.2. The display panel of claim 1 , whereinan input terminal and an output terminal of each of the diodes are formed with different wiring layers on the insulation substrate.3. The display panel of claim 1 , whereineach of the diodes is a diode connected thin film transistor, a gate electrode formed with a same layer as the gate line;', 'a source electrode formed with a same layer as a data line; and', 'a drain electrode formed with the same layer as the data line, and, 'the thin film transistor comprisesa gate insulating layer and a semiconductor layer are disposed between the gate electrode and the drain electrode of the thin film transistor.4. The display panel of claim 3 , whereina portion of the semiconductor layer is disposed under the drain electrode to have a same boundary as a boundary of the drain electrode on the insulation substrate.5. The display panel of claim 1 , whereina distance from a cutting line to the diodes is about 200 micrometers.6. The display panel of claim 1 , ...

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Номер записи: 45
01-01-2015 дата публикации

SEMICONDUCTOR DEVICES INCLUDING VERTICAL CHANNEL TRANSISTORS AND METHODS OF FABRICATING THE SAME

Номер: US20150001617A1
Автор: Hong HyeongSun, Hwang Yoosang, Kim Daeik, Oh Yongchul
Принадлежит:

Methods of fabricating semiconductor devices may include forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches extend in parallel. A gate dielectric layer is formed on upper inner sidewalls of the first trenches, and a gate conductive layer filling the first trenches is formed on the substrate including the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars. Semiconductor devices may also be provided. 110-. (canceled)11. A semiconductor device , comprising:an active pillar protruding from a substrate;a lower dopant region and an upper dopant region in the pillar, the lower dopant region vertically separated from the upper dopant region and separated from a first sidewall of the active pillar;a gate electrode on a second sidewall of the active pillar; anda gate dielectric layer between the second sidewall and the gate electrode.12. The semiconductor device as set forth in claim 11 , further comprising:a buried interconnection electrically connected to the lower dopant region,wherein a top surface of the buried interconnection is located at a lower level than a top surface of the lower dopant region.13. The semiconductor device as set forth in claim 12 , further comprising:a separation dopant region between the buried interconnection and a bulk of the substrate,wherein the separation dopant region includes at least one dopant of the same conductivity type as the lower dopant region, and the separation dopant region is connected to the lower dopant region.14. The semiconductor device as set forth in claim 11 , further comprising:a void in the gate electrode; anda void-filling dielectric pattern filling at least a portion of the void.15. The semiconductor device as set forth in claim 11 , further comprising:a buried ...

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Номер записи: 46
01-01-2015 дата публикации

METHODS OF FABRICATING AN F-RAM

Номер: US20150004718A1
Автор: Davenport Thomas, Patel Kedar, Ramkumar Krishnaswamy, Sun Shan
Принадлежит: CYPRESS SEMICONDUCTOR CORPORATION

Non-volatile memory cells including complimentary metal-oxide-semiconductor transistors and embedded ferroelectric capacitor and methods of forming the same are described. In one embodiment, the method includes forming on a surface of a substrate a gate level including a gate stack of a MOS transistor, a first dielectric layer overlying the MOS transistor and a first contact extending through the first dielectric layer from a top surface thereof to a diffusion region of the MOS transistor. A local interconnect (LI) layer is deposited over the top surface of the first dielectric layer and the first contact, a ferro stack including a bottom electrode, a top electrode and ferroelectric layer there between deposited over the LI layer, and the ferro stack and the LI layer patterned to form a ferroelectric capacitor and a LI through which the bottom electrode is electrically coupled to the diffusion region of the MOS transistor. 1. A method comprising:forming a gate level on a surface of a substrate, the gate level including a gate stack of a metal-oxide-semiconductor (MOS) transistor, a first dielectric layer overlying the MOS transistor and a first contact extending through the first dielectric layer from a top surface thereof to a diffusion region of the MOS transistor in the substrate;depositing a local interconnect (LI) layer over the top surface of the first dielectric layer and the first contact;depositing over the LI layer a ferroelectric layer and a top electrode;patterning the ferroelectric layer and top electrode to form a ferro stack;patterning the LI layer to concurrently form a ferroelectric capacitor comprising the ferro stack and a bottom electrode comprising a portion of the LI layer through which the bottom electrode is electrically coupled to the diffusion region of the MOS transistor, and a LI comprising an exposed portion of the LI layer not covered by the ferro stack; andconcurrently encapsulating the ferroelectric capacitor and the LI with an ...

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Номер записи: 47
07-01-2016 дата публикации

INTEGRATED CIRCUIT FABRICATION

Номер: US20160005601A1
Автор: Freeman Eric, Lee John, Liu Zengtao, Nielsen Russell, Tran Luan C.
Принадлежит:

A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width. 1. (canceled)2. A method for integrated circuit fabrication , comprising:forming a plurality of loops of masking material over a substrate;depositing a selectively definable material over the loops; andpatterning the selectively definable material to expose expanses of the loops between ends of the loops,wherein the ends remain covered by the selectively definable material after patterning, wherein an entire width of a portion of the masking material at the ends is covered by the selectively definable material,wherein patterning defines features in the selectively definable material, the features spaced apart from the loops and having a minimum width larger than a minimum width of the masking material forming the loops.3. The method of claim 2 , wherein forming the plurality of loops forms pairs of parallel runs of the masking material claim 2 , each pair of parallel runs joining at the ends of the loops.4. The method of claim 3 , wherein claim 3 , after patterning claim 3 , the selectively definable material extends completely over the ends of at least some of the loops claim 3 , the selectively definable material extending completely from a portion of one run of the masking material to a portion of another claim 3 , ...

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Номер записи: 48
07-01-2016 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20160005739A1
Автор: HAN SHINHEE, LEE KILHO
Принадлежит:

A semiconductor memory device includes a first insulating layer covering a substrate, a first contact plug and a second contact plug each penetrating the first insulating layer, a first data storage element disposed on the first contact plug, and a second data storage element disposed on the second contact plug. The first contact plug includes a vertically extending portion and a horizontally extending portion arranged between the vertically extending portion and the first data storage element, and the second contact plug extends substantially vertically from a top surface of the substrate. The first data storage element is laterally spaced apart from the vertically extending portion when viewed in plan view. The first data storage element is disposed on the horizontally extending portion. 1. A semiconductor memory device comprising:a first insulating layer covering a substrate;a first contact plug and a second contact plug, each penetrating the first insulating layer;a first data storage element disposed on the first contact plug and electrically connected to a portion of the substrate through the first contact plug; anda second data storage element disposed on and overlapping the second contact plug and electrically connected to a portion of the substrate through the second contact plug, a vertically extending portion; and', 'a horizontally extending portion arranged between the vertically extending portion and the first data storage element,, 'wherein the first contact plug compriseswherein the second contact plug vertically extends from a top surface of the substrate,wherein the first data storage element is laterally spaced apart from the vertically extending portion when viewed in plan view, andwherein the first data storage element is disposed on the horizontally extending portion.2. The semiconductor memory device of claim 1 , wherein the first insulating layer includes a recessed region that is disposed in an upper portion of the first insulating layer ...

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Номер записи: 49
27-01-2022 дата публикации

3D ARCHITECTURE OF TERNARY CONTENT-ADDRESSABLE MEMORY METHOD FOR THE SAME

Номер: US20220028858A1
Автор: CHEN Liang-Yu
Принадлежит:

Disclosed is a 3D architecture of ternary content-addressable memory (TCAM), comprising a first transistor layer, a second transistor layer, a third transistor layer and a fourth transistor layer. The first transistor layer and the second transistor layer are disposed on a first plane. The third transistor layer and the fourth transistor layer are respectively stacked on the first transistor layer and the second transistor layer in a second direction perpendicular to the first plane. Two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a first memory cell of the TCAM. The other two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a second memory cell of the TCAM. 1. A 3D architecture of ternary content-addressable memory (TCAM) , comprising:a first transistor layer, disposed on a first plane, and extending in a first direction parallel to the first plane;a second transistor layer, disposed on the first plane, parallel to the first transistor layer, and extending in the first direction;a third transistor layer, stacked on the first transistor layer in a second direction perpendicular to the first plane; anda fourth transistor layer, stacked on the second transistor layer in the second direction,wherein two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a first memory cell of the TCAM, and the other two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a second memory cell of the TCAM.2. The 3D architecture of TCAM according to claim 1 , wherein the first transistor layer is the first transistor ...

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Номер записи: 50
14-01-2016 дата публикации

Memory Cell

Номер: US20160013190A1
Автор: LIAW Jhon Jhy
Принадлежит:

Cell layouts for a memory cell, such as for ternary content addressable memory (TCAM), are disclosed. Some cell layouts include a well strap structure. A cell layout may include a p-doped well, an n-doped well, and a p-doped well sequentially along a layout. Another cell layout may include a p-doped well, an n-doped well, a p-doped well, and an n-doped well sequentially along a layout. A well strap structure may be in a p-doped well or an n-doped well. Various metallization layers having a mesh may be used with a memory cell layout. In some disclosed examples, a first metallization layer may have one, two, or four ground traces, and a second metallization layer may have two ground traces. These various ground traces may be electrically coupled together to form a mesh. 1. A cell structure comprising:a first data latch comprising a first group of transistors having active areas in a substrate;a second data latch comprising a second group of transistors having active areas in the substrate;a search port comprising a third group of transistors having an active area in the substrate;a well strap structure having an active area in the substrate;a first metallization layer over the substrate and comprising a first ground trace and a well strap trace each extending in a first direction, the active area of the well strap structure being electrically coupled to the well strap trace; anda second metallization layer over the substrate and comprising a second ground trace and a third ground trace each extending in a second direction, the first direction intersecting the second direction, the second ground trace and the third ground trace being electrically coupled to the first ground trace.2. The cell structure of claim 1 , wherein the well strap trace comprises a fourth ground trace claim 1 , the fourth ground trace being electrically coupled to the second ground trace claim 1 , and the fourth ground trace being electrically coupled to the third ground trace.3. The cell ...

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Номер записи: 51
15-01-2015 дата публикации

BIT LINE EQUALIZING CIRCUIT

Номер: US20150016199A1
Автор: KWON Hyuk-Joon, WON Bok-Yeon
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

There is provided a bit line equalizing circuit including: an active region; a first bit line disposed on the active region in a first direction; a second bit line disposed on the active region in the first direction; a gate pattern including a first pattern disposed on the active region in a second direction crossing the first direction, and a second pattern extended from one side of the first pattern to be disposed in the first direction, and formed in a stair shape; a first contact disposed at one side of the first pattern and one side of the second pattern, and configured to connect the active region and the first bit line; a second contact disposed at one side of the first pattern and the other side of the second pattern, and configured to connect the active region and the second bit line; and a third contact disposed at the other side of the first pattern, and configured to provide a predetermined voltage to the active region. 1. A bit line equalizing circuit comprising:an active region;a first bit line disposed on the active region in a first direction;a second bit line disposed on the active region in the first direction;a gate pattern including a first pattern disposed on the active region in a second direction crossing the first direction, and a second pattern extended from one side of the first pattern to be disposed in the first direction, and formed in a stair shape;a first contact disposed at one side of the first pattern and one side of the second pattern, and configured to connect the active region and the first bit line;a second contact disposed at one side of the first pattern and the other side of the second pattern, and configured to connect the active region and the second bit line; anda third contact disposed at the other side of the first pattern, and configured to provide a predetermined voltage to the active region.2. The bit line equalizing circuit of claim 1 , wherein the first contact and the second contact are disposed at a plurality of ...

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Номер записи: 52
21-01-2016 дата публикации

Method of Controlling Recess Depth and Bottom ECD in Over-Etching

Номер: US20160020119A1
Автор: Chang Sheng-Yuan, Wei An Chyi
Принадлежит:

A semiconductor stack includes a carbon doped/implanted stop layer that reacts with etching plasma to form polymers that maintain bottom etched critical dimension (ECD) and avoid excess recess depth when over-etching in high-aspect-ratio structures.

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Номер записи: 53
03-02-2022 дата публикации

Memory Array Staircase Structure

Номер: US20220036931A1
Автор: Chia Han-Jong, LIN Chung-Te, Lin Meng-Han, Lin Yu-Ming, Wang Sheng-Chen, Yang Feng-Cheng
Принадлежит:

Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length second edge of the memory array; a memory film contacting a first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line. 1. A memory array comprising:a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array, the second edge of the memory array being perpendicular to the first edge of the memory array;a second word line extending from a third edge of the memory array, the third edge of the memory array being opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length second edge of the memory array;a memory film contacting a first word line; andan oxide semiconductor (OS) layer contacting a first source line and a first bit line, wherein the memory film is disposed between the OS layer and the first word line.2. The memory array of claim 1 , wherein the memory film comprises a ferroelectric (FE) material.3. The memory array of claim 1 , further comprising:an inter-metal dielectric (IMD) over the first word line;a first contact extending through the IMD to the first word line, wherein the first contact is electrically coupled to the first word line;a dielectric material ...

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Номер записи: 54
21-01-2016 дата публикации

Composite Hard Mask Etching Profile for Preventing Pattern Collapse in High-Aspect-Ratio Trenches

Номер: US20160020211A1
Автор: Wei An Chyi, Yang Zusing
Принадлежит:

High-aspect ratio trenches in integrated circuits are fabricated of composite materials and with trench boundaries having pencil-like etching profiles. The fabrication methods reduce surface tension between trench boundaries and fluids applied during manufacture, thereby avoiding pattern bending, bowing, and collapse. The method, further, facilitates fill-in of trenches with suitable selected materials.

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Номер записи: 55
03-02-2022 дата публикации

Semiconductor Structure and its Fabricating Method

Номер: US20220037481A1
Автор: HSU Cheng Yeh, Zou Bing
Принадлежит: CHANGXIN MEMORY TECHNOLOGIES, INC.

Embodiments of the present application provide a semiconductor structure and its fabricating method, and a semiconductor memory. The method of fabricating a semiconductor structure comprises providing a substrate and performing ion implantation on the substrate to form an active area, forming a gate groove on surface of the substrate, measuring depth of the gate groove, and performing ion implantation compensation, if the depth of the gate groove meets a preset condition, on the substrate according to the depth of the gate groove, and forming an ion compensation region in the active area at one side of the gate groove. 1. A method of fabricating a semiconductor structure , comprising:providing a substrate and performing ion implantation on the substrate to form an active area;forming a gate groove on surface of the substrate;measuring depth of the gate groove; andperforming ion implantation compensation, if the depth of the gate groove meets a preset condition, on the substrate according to the depth of the gate groove, and forming an ion compensation region in the active area at one side of the gate groove.2. The method of fabricating a semiconductor structure according to claim 1 , wherein the step of forming an ion compensation region in the active area at one side of the gate groove comprises:forming a bitline contact hole in the active area at one side of the gate groove; andperforming ion implantation compensation on the substrate through the bitline contact hole, and forming the ion compensation region.3. The method of fabricating a semiconductor structure according to claim 1 , wherein the step of performing ion implantation compensation on the substrate according to the depth of the gate groove comprises:fixing implantation depth of compensation ions according to the depth of the gate groove;fixing implantation energy of the compensation ions according to the implantation depth of the compensation ions; andperforming ion implantation compensation on the ...

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Номер записи: 56
03-02-2022 дата публикации

MEMORY CELL

Номер: US20220037513A1
Автор: Galy Philippe
Принадлежит: STMICROELECTRONICS SA

A cell includes a Z-FET-type structure that is formed with two front gates extending over an intermediate region between an anode region and a cathode region. The individual front gates of the two front gates are spaced apart by a distance that is shorter than 40% of a width of each individual front gate. 1. A memory cell , comprising:{'sup': '2', 'claim-text': two front gates that extend over an intermediate region;', 'wherein said two front gates are spaced apart from each other by a distance that is shorter than 40% of a width of each front gate of the two front gates., 'a Z-FET-type structure comprising2. The memory cell according to claim 1 , wherein the distance is in the order of 30% of the width of each front gate of the two front gates.3. The memory cell according to claim 1 , wherein the two front gates are separated from each other by an insulating spacer having a thickness in a direction perpendicular to the width of each front gate that is at least greater than a thickness of an electrically conducting portion of each front gate.4. The memory cell according to claim 3 , further comprising insulating spacers on lateral side walls of each front gate of the two front gates at opposite ends of the intermediate region.5. The memory cell according to claim 1 , wherein each front gate of the two front gates has a 28-nm width.6. The memory cell according to claim 5 , wherein the distance between the two front gates is in the order of 9 nm.7. The memory cell according to claim 1 , wherein the Z-FET-type structure further comprises:an anode region;a cathode region; andwherein said intermediate region separates the anode region from the cathode region.8. The memory cell according to claim 7 , wherein one of the front gates is insulated from and positioned on top of a first portion of said intermediate region claim 7 , and another one of the front gates is insulated from and positioned on top of a second portion of said intermediate region.9. The memory cell of ...

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Номер записи: 57
18-01-2018 дата публикации

SELECTIVE DEVICE, MEMORY CELL, AND STORAGE UNIT

Номер: US20180019391A1
Автор: Ikarashi Minoru, Ohba Kazuhiro
Принадлежит:

A selective device includes a first electrode, a second electrode, a switch device, and a non-linear resistive device. The second electrode is disposed to face the first electrode. The switch device is provided between the first electrode and the second electrode. The non-linear resistive device contains one or more of boron (B), silicon (Si), and carbon (C). The non-linear resistive device is coupled to the switch device in series. 1. A selective device comprising:a first electrode,a second electrode disposed to face the first electrode;a switch device provided between the first electrode and the second electrode; anda non-linear resistive device that contains one or more of boron (B), silicon (Si), and carbon (C), the non-linear resistive device being coupled to the switch device in series.2. The selective device according to claim 1 , wherein the non-linear resistive device has a non-linear resistive layer including an alloy or a compound that contains one or more of boron (B) claim 1 , silicon (Si) claim 1 , and carbon (C).3. The selective device according to claim 1 , wherein the non-linear resistive device has a non-linear resistive layer that includes oxide claim 1 , nitride claim 1 , or oxynitride of any of boron (B) and silicon (Si).4. The selective device according to claim 1 , wherein the non-linear resistive device has a dielectric withstanding voltage of 1 MV/cm or higher claim 1 , and applies a current with a current density of 10 MA/cmor higher at a voltage of 2 V or lower that is applied to the non-linear resistive device.5. The selective device according to claim 1 , wherein the switch device includes a switch layer that is changed into a low-resistance state by increasing an applied voltage to a predetermined threshold voltage or higher claim 1 , the switch layer being changed into a high-resistance state by decreasing the applied voltage to the predetermined threshold voltage or lower claim 1 , or by removing the applied voltage.6. The selective ...

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Номер записи: 58
17-01-2019 дата публикации

MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20190019542A1
Автор: Chang Wei-Che, TANAKA Yoshinori
Принадлежит: WINBOND ELECTRONICS CORP.

Provided is a memory device including a substrate, isolation structures, conductive pillars, and bit-line structures. The substrate includes active areas. The active areas are arranged as a first array. The isolation structures are located in the substrate and extending along a Y direction. Each of the isolation structures is arranged between the active areas in adjacent two columns. The conductive pillars are located on the substrate and arranged as a second array. The conductive pillars in adjacent two rows are in contact with the active areas arranged as the same column, to form a first contact region and a second contact region. The bit-line structures are arranged on the substrate in parallel along a X direction. Each of the bit-line structures is in contact with the active areas arranged as the same column, to form a third contact region between the first and second regions. 1. A manufacturing method of a memory device , comprising:forming a plurality of first isolation structures in a substrate, wherein the first isolation structures separate the substrate into a plurality of strip patterns, and the strip patterns are bent or straight;forming a plurality of word line sets in the substrate, wherein the word line sets are extended along a Y direction and pass through the first isolation structures and the strip patterns to divide the substrate into a plurality of first regions and a plurality of second regions, and the first regions and the second regions are alternately arranged along an X direction and the word line sets are located in the first regions;forming a first dielectric pattern on the substrate, wherein the first dielectric pattern covers the word line sets and exposes a surface of the substrate of the second regions;forming a conductive layer on the substrate of the second regions, wherein a top surface of the conductive layer is lower than a top surface of the first dielectric pattern;forming a plurality of second isolation structures in the ...

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Номер записи: 59
17-01-2019 дата публикации

VERTICAL TRANSISTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20190019888A1
Автор: YEH Chih-Chieh, Yu Shao-Ming, YUN Wei-Sheng
Принадлежит:

A vertical transistor device and a method for fabricating the same are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and fin portions located on the bottom portion. Each of the fin portions includes an upper portion and a lower portion. The lower portion is located between the bottom portion of the semiconductor substrate and the upper portion, in which the lower portion includes recesses. The first sources/drains are disposed on terminals of the upper portions of the fin portions. The second sources/drains are disposed on the recesses of the lower portions of the fin portions, in which the sources/drains are not merged with each other. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the recesses on the lower portions of the fin portions. 1. A vertical transistor device , comprising:a semiconductor substrate comprising:a bottom portion; anda fin portion located on the bottom portion, wherein the fin portion comprises:an upper portion; anda lower portion located between the bottom portion of the semiconductor substrate and the upper portion of the fin portion, wherein the lower portion comprises a plurality of recesses; anda plurality of sources/drains disposed on the recesses of the lower portion of the fin portion, wherein the recesses are formed along a crystalline direction <111>.2. The vertical transistor device of claim 1 , further comprising a gate structure disposed on the upper portion of the fin portion to induce a cannel in the upper portion of the fin portion.3. (canceled)4. The vertical transistor device of claim 1 , further comprising a plurality of silicide layers disposed on the sources/drains.5. A vertical transistor device claim 1 , comprising:a semiconductor substrate comprising:a bottom portion; anda plurality of fin portions located on the ...

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Номер записи: 60
17-04-2014 дата публикации

NONVOLATILE MEMORY DEVICES

Номер: US20140106518A1
Автор: Choi Jung-Dal, Lee Chang-Hyun
Принадлежит:

A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers. 1. A method of making a nonvolatile memory device , the method comprising:forming a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor where each has a channel region and source/drain regions in a substrate;injecting first impurity ions into the substrate to form first impurity layers at boundaries of the channels and the source/drain regions of the string selection transistor, the memory cell transistors, and the ground selection transistor; andinjecting second impurity ions, which are same conductivity type as the first impurity ions, into the boundaries between the channel and drain regions of the string selection transistor and between the channel and source regions of the ground selection transistor,wherein the first impurity layers are doped with p conductivity type impurities.2. The method of claim 1 , wherein injecting second impurity ions comprises:forming an ion implantation mask on the substrate that exposes portions of the drain region of the string selection transistor and the source region of the ground ...

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Номер записи: 61
28-01-2021 дата публикации

CO-INTEGRATION OF NON-VOLATILE MEMORY ON GATE-ALL-AROUND FIELD EFFECT TRANSISTOR

Номер: US20210028175A1
Автор: Bi Zhenxing, Cheng Kangguo, Kong Dexin, Xu Zheng
Принадлежит:

A method of performing co-integrated fabrication of a non-volatile memory (NVM) and a gate-all-around (GAA) nanosheet field effect transistor (FET) includes recessing fins in a channel region of the NVM and the FET to form source and drain regions adjacent to recessed fins, and removing alternating portions of the recessed fins of the NVM and the FET to form gaps in the recessed fins. A stack of layers that make up an NVM structure are conformally deposited within the gaps of the recessed fins leaving second gaps, smaller than the gaps, and above the recessed fins of the NVM while protecting the FET with the organic planarization layer (OPL) and a block mask. The OPL and block mask are removed from the FET, and another OPL and another block mask protect the NVM while a gate of the FET is formed above the recessed fins and within the gaps. 1. An integrated device including a non-volatile memory (NVM) and a nanosheet field effect transistor (FET) , the device comprising:fins of a channel region of the NVM formed on a substrate;fins of a channel region of the nanosheet FET formed on the substrate;a stack of layers that make up an NVM structure conformally formed in alternating portions of the fins of the NVM;gate material formed in alternating portions of the fins of the nanosheet FET;source and drain regions between the fins of the NVM and the fins of the nanosheet FET; anda gate formed above the fins of the nanosheet FET.2. The device according to claim 1 , wherein the stack of layers that make up the NVM structure includes silicon oxide nitride.3. The device according to claim 2 , wherein the stack of layers that make up the NVM structure includes hafnium dioxide.4. The device according to claim 3 , wherein the stack of layers that make up the NVM structure includes silicon dioxide.5. The device according to claim 1 , wherein alternating portions of the fins of the NVM and of the nanosheet FET include silicon.6. The device according to claim 1 , wherein alternating ...

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Номер записи: 62
01-02-2018 дата публикации

Processor For Enhancing Computer Security

Номер: US20180032729A1
Автор: ZHANG Guobiao
Принадлежит: CHENGDU HAICUN IP TECHNOLOGY LLC

The present invention discloses a processor for enhancing computer security, i.e. a three-dimensional (-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (D-M) array for permanently storing virus patterns and a pattern-processing circuit for performing pattern processing on a scanned computer data against said virus patterns. The D-M array is stacked above the pattern-processing circuit. 1. A processor for enhancing computer security , comprising:an input for transferring at least a computer data;a semiconductor substrate having transistors thereon;a plurality of storage-processing units (SPU), each of said SPUs comprising a pattern-processing circuit and at least a three-dimensional memory (3D-M) array, whereinsaid 3D-M array is stacked above said pattern-processing circuit and stores at least a virus pattern;said pattern-processing circuit is formed on said semiconductor substrate and performs pattern matching or pattern recognition on said computer data against said virus pattern;said 3D-M array and said pattern-processing circuit are communicatively coupled by a plurality of contact vias.2. The processor according to claim 1 , further comprising first and second SPUs formed side-by-side.3. The processor according to claim 2 , wherein both of said first and second SPUs are communicatively coupled with said input.4. The processor according to claim 2 , further comprising an output for transferring at least a result of said pattern matching or pattern recognition.5. The processor according to claim 4 , wherein both of said first and second SPUs are communicatively coupled with said output.6. The processor according to claim 1 , wherein said 3D-M array is three-dimensional writable memory (3D-W) array.7. The processor according to claim 6 , wherein said 3D-W array is a three-dimensional one-time-programmable memory (3D-OTP) array.8. The ...

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Номер записи: 63
02-02-2017 дата публикации

MEMORY DEVICE AND FABRICATING METHOD THEREOF

Номер: US20170033100A1
Автор: Wu Tieh-Chiang
Принадлежит:

A memory device and a method for fabricating thereof are provided. The memory device includes a substrate, a first active region, a second active region, a gate structure, and a contact structure. The first active region and the second active region are alternately disposed in the substrate. The gate structure is disposed in the substrate and between the first active region and the second active region. The contact structure is over the substrate and electrically connected to one of the first active region and the second active region. The contact structure includes a metal portion directly in contact with one of the first active region and the second active region. 1. A memory device , comprising:a substrate;a first active region and a second active region alternately disposed in the substrate;a gate structure disposed in the substrate and between the first active region and the second active region; anda contact structure over the substrate and electrically connected to one of the first active region and the second active region, the contact structure comprising a metal portion directly in contact with one of the first active region and the second active region.2. The memory device of claim 1 , wherein the gate structure is a single-layer structure or a multi-layer structure.3. The memory device of claim 2 , wherein the gate structure is a multi-layer structure comprising:a first portion; anda second portion embedded in the first portion.4. The memory device of claim 1 , wherein the metal portion of the contact structure comprises one or more metal layers.5. The memory device of claim 4 , wherein the metal portion of the contact structure comprises:a first metal layer directly in contact with one of the first active region and the second active region; anda second metal layer embedded in the first metal layer.6. The memory device of claim 1 , wherein a bottom surface of the contact structure is lower than a top surface of the substrate.7. The memory device of ...

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Номер записи: 64
01-02-2018 дата публикации

Non-Volatile Memory With Reduced Program Speed Variation

Номер: US20180033794A1
Автор: Baraskar Ashish, Dong Yingda, Makala Raghuveer, Pang Liang, Zhang Yanli
Принадлежит: SanDisk Technologies LLC

A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness. 1. An apparatus , comprising:a substrate;a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over the substrate, the plurality of word line layers including a first word line layer formed below a second word line layer, the first word line layer having a first gate length that is smaller than a second gate length of the second word line layer; anda first memory hole extending vertically through at least a portion of the stack, the memory hole having a diameter that decreases from an upper region of the stack to a lower region of the stack.2. The apparatus of claim 1 , further comprising:a first word line formed in the first word line layer at a first level above a surface of the substrate;a second word line formed in the second word layer at a second level above the surface of the substrate; andthe first level is a smaller distance from the surface of the substrate than the second level.3. The apparatus of claim 1 , wherein:the plurality of word line layers are stacked vertically; ...

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Номер записи: 65
05-02-2015 дата публикации

METHOD FOR MANUFACTURING TESTED APPARATUS AND METHOD FOR MANUFACTURING SYSTEM INCLUDING TESTED APPARATUS

Номер: US20150037914A1
Автор: Ishikawa Toru, TAKAHASHI Tetsuji, TAKAKURA Kazuya
Принадлежит:

Disclosed herein is a method for manufacturing a tested apparatus that includes forming a stacked structure that includes a plurality of first semiconductor chips stacked over a semiconductor wafer. The semiconductor wafer comprises a plurality of second semiconductor chips that are arranged in matrix of a plurality of rows and columns. Each of the first semiconductor chips is stacked over and electrically connected to a different one of the second semiconductor chips. The method further includes contacting a probe card to at least one of the first semiconductor chips to perform a first test operation on a corresponding one of the second semiconductor chips with an intervention of the at least one of the first semiconductor chips so that a plurality of tested apparatus each comprising a pair of first and second semiconductor chips stacked with each other is derived. 1. A method for manufacturing a tested apparatus comprising:forming a stacked structure that includes a plurality of first semiconductor chips stacked over a semiconductor wafer, the semiconductor wafer comprising a plurality of second semiconductor chips that are arranged in matrix of a plurality of rows and columns, each of the first semiconductor chips being stacked over and electrically connected to a different one of the second semiconductor chips; andcontacting a probe card to at least one of the first semiconductor chips to perform a first test operation on a corresponding one of the second semiconductor chips with an intervention of the at least one of the first semiconductor chips so that a plurality of tested apparatus each comprising a pair of first and second semiconductor chips stacked with each other is derived.2. The method as claimed in claim 1 , wherein the contacting the probe card comprises contacting the probe card to the at least one of the first semiconductor chip to perform the first test operation on the at least one of the first semiconductor memory chips.3. The method as claimed ...

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Номер записи: 66
01-05-2014 дата публикации

STACKED BIT LINE DUAL WORD LINE NONVOLATILE MEMORY

Номер: US20140120665A1
Автор: LUNG HSIANG-LAN
Принадлежит:

An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics. 1. A manufacture method of a semiconductor device , comprising:providing a substrate;forming first and second conductive lines over the substrate;forming a first plug coupled to the first conductive line, and orthogonal to the first conductive line and the substrate;forming a second plug coupled to the second conductive line, and orthogonal to the second conductive line and the substrate;forming a first memory cell disposed on a first sidewall beside the first plug, the first sidewall being orthogonal to the substrate; andforming a second memory cell disposed on a second sidewall beside the second plug, the second sidewall being orthogonal to the substrate, wherein the first memory cell is over the second memory cell.2. The manufacture method of claim 1 , wherein the first and second conductive lines are arranged in respective first and second levels above the substrate.3. The manufacture method of claim 1 , wherein the first and second conductive lines comprise material having a conductivity type opposite a conductivity type of material of the first and second plugs.4. The manufacture method of claim 3 , wherein the first and second conductive lines comprise polysilicon having a first conductivity type claim 3 , and the first and second plugs comprise polysilicon having a second conductivity type opposite the first ...

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Номер записи: 67
12-02-2015 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20150041901A1
Автор: LEE Go Hyun, OH Sung Lae, SON Chang Man
Принадлежит: SK HYNIX INC.

A semiconductor memory device may include a string including at least one drain select transistor, a plurality of first memory cells, a first connection element, a plurality of second memory cells, a second connection element, a plurality of third memory cells, and at least one source select transistor, wherein the at least one drain select transistor, the plurality of first memory cells, the plurality of second memory cells, the plurality of third memory cells, and the at least one source select transistor connected serially via the first connection element and the second connection element. 1. A semiconductor memory device , comprising: at least one drain select transistor,', 'a plurality of first memory cells,', 'a first connection element,', 'a plurality of second memory cells,', 'a second connection element,', 'a plurality of third memory cells, and', 'at least one source select transistor,', 'wherein the at least one drain select transistor, the plurality of first memory cells, the plurality of second memory cells, the plurality of third memory cells, and the at least one source select transistor are connected serially via the first connection element and the second connection element., 'a string including2. The semiconductor memory device of claim 1 ,wherein the first connection element or the second connection element includes a transistor or a conductive pattern.3. The semiconductor memory device of claim 1 ,wherein the drain select transistor and the plurality of first memory cells are stacked on the first connection element,the plurality of second memory cells are stacked between the first connection element and the second connection element, andthe source select transistor and the plurality of third memory cells are stacked on a lower portion of the second connection element.4. The semiconductor memory device of claim 1 , further comprising:a common source line connected to a lower portion of the at least one source select transistor; anda bit line ...

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Номер записи: 68
12-02-2015 дата публикации

SEMICONDUCTOR APPARATUS

Номер: US20150041902A1
Автор: CHUN Duk Su
Принадлежит: SK HYNIX INC.

A semiconductor apparatus includes a first junction region formed over an active region; a gate region formed over the active region to substantially surround the first junction region; a second junction region formed over the active region outside the gate region on a first side of the first junction region; and a third junction region formed over the active region outside the gate region on a second side of the first junction region which is opposite to the first side, wherein the second junction region and the third junction region are disposed such that the gate region exists between the second junction region and the third junction region. 1. A semiconductor apparatus comprising:a first junction region formed over an active region;a gate region formed over the active region to substantially surround the first junction region;a second junction region formed over the active region outside the gate region on a first side of the first junction region; anda third junction region formed over the active region outside the gate region on a second side of the first junction region which is opposite to the first side,wherein the second junction region and the third junction region are disposed such that the gate region exists between the second junction region and the third junction region.2. The semiconductor apparatus according to claim 1 , wherein the gate region is configured in such a way as to be open on a third side of the first junction region which is other than the first side and the second side.3. The semiconductor apparatus according to claim 1 , wherein a transistor is formed at the first junction region claim 1 , the second junction region claim 1 , and the gate region which is formed between the first junction region and the second junction region.4. The semiconductor apparatus according to claim 1 , wherein a transistor is formed at the first junction region claim 1 , the third junction region claim 1 , and the gate region which is formed between the ...

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Номер записи: 69
12-02-2015 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20150041903A1
Автор: Kim Jin Ho, OH Sung Lae
Принадлежит: SK HYNIX INC.

A semiconductor device includes a plurality of transistors formed over a substrate, a support body including a horizontal portion and protrusions, wherein the horizontal portion covers at least one of the transistors, and the protrusions are formed over the horizontal portion and located between the transistors, and conductive layers and insulating layers alternately stacked over the support body and protruding upwardly along the sidewalls of the protrusions. 1. A semiconductor device , comprising:a plurality of transistors formed over a substrate;a support body including a horizontal portion and protrusions, wherein the horizontal portion covers at least one of the transistors, and the protrusions are formed over the horizontal portion and located between the transistors; andconductive layers and insulating layers alternately stacked over the support body and protruding upwardly along the sidewalls of the protrusions.2. The semiconductor device of claim 1 , wherein the protrusions are located between neighboring memory blocks.3. The semiconductor device of claim 1 , further comprising:first and second junctions of the transistors;a plurality of first lines coupled to the first junctions of the transistors, respectively; anda plurality of second lines coupling the conductive layers to the second junctions of the transistors, respectively.4. The semiconductor device of claim 3 , further comprising:a plurality of first contact plugs passing through the protrusions and coupling the first junctions to the first lines, respectively;a plurality of second contact plugs passing through the protrusions and coupling the second junctions to the second lines, respectively; anda plurality of third contact plugs coupling the conductive layers to the second lines, respectively.5. The semiconductor device of claim 3 , wherein the first and second lines are formed over the conductive layers and the insulating layers.6. The semiconductor device of claim 3 , wherein the protrusions ...

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Номер записи: 70
04-02-2021 дата публикации

MEMORY ARRAY DECODING AND INTERCONNECTS

Номер: US20210035612A1
Автор: Castro Hernan A., Russell Stephen W., Tang Stephen H.
Принадлежит:

Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques. 1. An apparatus , comprising:a conductive plug that extends through a plurality of decks of memory cells;a plurality of transistors that each has a source or a drain in contact with the conductive plug; anda driver coupled with the conductive plug and configured to be selectively coupled, by a transistor of the plurality of transistors, with an electrode included in a deck of the plurality of decks.2. The apparatus of claim 1 , further comprising:a second conductive plug, that extends through the plurality of decks; anda second plurality of transistors that each has a source or a drain in contact with the conductive plug; anda second driver coupled with the second conductive plug and configured to be selectively coupled, by a subset of transistors of the second plurality, with access lines of the first type included in a subset of decks of the plurality of decks.3. The apparatus of claim 2 , wherein the electrode comprises:a first portion that extends between the conductive plug and the second conductive plug in a first direction;a second portion coupled with an end of the first portion that extends in a second direction; ...

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Номер записи: 71
08-02-2018 дата публикации

DISPLAY APPARATUS

Номер: US20180040845A1
Автор: NONAKA Yoshihiro, TAKATORI Kenichi, YANASE Jiro
Принадлежит: TIANMA JAPAN, LTD.

Provided is a display apparatus that compensates a drive transistor threshold to attain a highly precise structure. The display apparatus comprises a light emitting element including a first electrode, a second electrode and an organic light emitting layer disposed between the first electrode and the second electrode, and a pixel circuit including a capacitor and a drive transistor letting current according to voltage of the capacitor flow in the light emitting element. The pixel circuit stops supply of current to the light emitting element while connecting the capacitor to the first electrode. 1. A display apparatus , comprising:a light emitting element including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode; anda pixel circuit including a capacitor and a drive transistor letting current according to voltage of the capacitor flow in the light emitting element,wherein the pixel circuit stops supply of current to the light emitting element while connecting the capacitor to the first electrode.2. The display apparatus according to claim 1 , whereinthe pixel circuit connects the capacitor to the first electrode, and thereafter stores threshold voltage of the drive transistor and data voltage corresponding to emission luminance of the light emitting element in the capacitor.3. The display apparatus according to claim 2 , whereinin a case of stopping the supply of current, the pixel circuit stops supplying current from a first power supply which supplies current to flow in the light emitting element to the drive transistor.4. The display apparatus according to claim 3 , whereinafter storing, in the capacitor, voltage subtracting the threshold voltage plus the data voltage from voltage of the first power supply, the pixel circuit disconnects the capacitor from the first electrode while starting to supply current from the first power supply to the drive transistor, and further ...

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Номер записи: 72
19-02-2015 дата публикации

SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND PERIPHERAL TRANSISTOR

Номер: US20150048444A1
Автор: Cho Kwan-Sik, Cho Sung-Il, Kim Bong-Soo, Kim Jin-Young, Kim Nam-Gun, Yoon Hyun-Chul
Принадлежит:

A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode. 1. A semiconductor device comprising:a substrate;a word line in the substrate;a bit line contact plug on the semiconductor substrate;a bit line barrier layer on the bit line contact plug;a bit line electrode on the bit line barrier layer;a peripheral transistor insulating layer on the substrate;a peripheral transistor lower electrode on the peripheral transistor insulating layer;a peripheral transistor upper electrode on the peripheral transistor lower layer; anda peripheral transistor capping layer on the peripheral transistor upper electrode,wherein the bit line electrode and the peripheral transistor upper electrode are at a same level.2. The semiconductor device according to claim 1 , wherein the substrate has a cell region and a peripheral region claim 1 , the word line claim 1 , the bit line contact plug claim 1 , the bit line barrier layer claim 1 , and the bit line electrode are disposed in the cell region claim 1 , and the peripheral transistor insulating layer claim 1 , the peripheral transistor lower electrode claim 1 , and the peripheral transistor upper ...

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Номер записи: 73
19-02-2015 дата публикации

MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME

Номер: US20150048506A1
Автор: CHEN SHIH-HUNG, Hsiao Yi-Hsuan, Lue Hang-Ting, Shih Yen-Hao
Принадлежит: MACRONIX INTERNATIONAL CO., LTD.

A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a 3D memory array, a periphery circuit, and a conductive connection structure. The 3D memory array and the periphery circuit are stacked on the substrate. The periphery circuit includes a patterned metal layer and a contact structure electrically connected to the patterned metal layer. The conductive connection structure is electrically connected to the patterned metal layer. The 3D memory array is electrically connected to the periphery circuit via the conductive connection structure. 1. A memory device , comprising:a substrate;a 3D memory array and a periphery circuit stacked on the substrate, the periphery circuit comprising:a patterned metal layer; anda contact structure electrically connected to the patterned metal layer; anda conductive connection structure electrically connected to the patterned metal layer, wherein the 3D memory array is electrically connected to the periphery circuit via the conductive connection structure.2. The memory device according to claim 1 , wherein the periphery circuit further comprises a plurality of transistors electrically connected to the patterned metal layer via the contact structure.3. The memory device according to claim 1 , wherein the 3D memory array comprises a metal layer electrically connected to the conductive connection structure.4. The memory device according to claim 1 , wherein the 3D memory array is stacked on the periphery circuit.5. The memory device according to claim 4 , further comprising:an insulating layer disposed between the 3D memory array and the periphery circuit and covering the patterned metal layer.6. The memory device according to claim 4 , wherein the patterned metal layer is disposed between the 3D memory array and the periphery circuit.7. The memory device according to claim 1 , wherein the periphery circuit is stacked on the 3D memory array.8. The memory device according to claim 7 , ...

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Номер записи: 74
06-02-2020 дата публикации

A CONTACT STRUCTURE HAVING A FIRST LINER AND A SECOND LINER FORMED BETWEEN A CONDUCTIVE ELEMENT AND A INSULATING LAYER

Номер: US20200043785A1
Автор: Chen Huang-Nan, IKEDA Noriaki
Принадлежит:

A contact structure and a method for forming the contact structure are provided. The contact structure includes an insulating layer formed on a substrate. The contact structure includes a conductive element formed on the substrate and in the insulating layer. The contact structure includes a first liner formed in the insulating layer and on sidewalls of an upper portion of the conductive element. The contact structure includes a second liner formed on the sidewalls of the conductive element. A conductive contact plug is formed by the second liner and the conductive element. At the upper portion of the conductive element, the second liner is interposed between the conductive element and the first liner. At the lower portion of the conductive element, the second liner is interposed between the conductive element and the insulating layer. 1. A contact structure , comprising:an insulating layer formed on a substrate;a conductive element formed on the substrate and in the insulating layer;a first liner formed in the insulating layer and on sidewalls of an upper portion of the conductive element; anda second liner formed on the sidewalls of the conductive element, wherein the second liner and the conductive element form a conductive contact plug, wherein the second liner is interposed between the conductive element and the first liner at the upper portion of the conductive element, and wherein the second liner is interposed between the conductive element and the insulating layer at a lower portion of the conductive element, and wherein a horizontal bottom portion of the second liner is interposed between the conductive element and the substrate.2. The contact structure as claimed in claim 1 , wherein a bottom surface of the conductive contact plug has a first width W1 claim 1 , wherein a top surface of the conductive contact plug has a second width W2 claim 1 , and wherein the first width W1 is greater than or equal to the second width W2.3. The contact structure as ...

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Номер записи: 75
15-02-2018 дата публикации

MEMORY CELL WITH INDEPENDENTLY-SIZED ELECTRODE

Номер: US20180047896A1
Автор: GOTTI ANDREA, Ravasio Marcello, Sciarrillo Samuele
Принадлежит:

Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode. 120.-. (canceled)21. An apparatus , comprising:a first electrode extending a first distance in a first lateral dimension;a second electrode coupled to the first electrode, the second electrode extending a second distance in the first lateral dimension; anda third electrode coupled to the second electrode, the third electrode extending the first distance in the first lateral dimension.22. The apparatus of claim 21 , wherein the second electrode is formed from a material that is different than a material used to form the first electrode or a material used to form the third electrode.23. The apparatus of claim 21 , wherein the second distance in the first lateral dimension is less than the first distance in the first lateral dimension.24. The apparatus of claim 21 , wherein:the first electrode extends a first distance in a second lateral dimension,the second electrode extends a second distance in the second lateral dimension, andthe third electrode extends the first distance in the second lateral dimension.25. The apparatus of claim 24 , wherein the second distance in the second lateral dimension is less than the first distance in the second lateral dimension.26. The apparatus of claim 21 , wherein the second electrode is formed of a material having a higher etch rate than a material of which at least one of the first electrode and the second electrode is formed.27. The apparatus of claim 21 , wherein the second electrode is self-aligned with a conductive line coupled to the first ...

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Номер записи: 76
26-02-2015 дата публикации

Single Spacer Process for Multiplying Pitch by a Factor Greater Than Two and Related Intermediate IC Structures

Номер: US20150054168A1
Автор: Abatchev Mirzafer K., Wells David H.
Принадлежит:

Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate. 1. (canceled)2. An integrated circuit , comprising:a first plurality of sets of interconnects, each set comprising 2n interconnects, wherein n is a whole number and is 2 or greater; anda second plurality of sets of interconnects, each set comprising 2n interconnects,wherein the sets of interconnects of the first and second plurality are interdigitated.3. The integrated circuit of claim 2 , wherein the integrated circuit comprises an array region disposed between opposing periphery regions claim 2 , wherein interconnects of the first and second pluralities extend into the array region from the opposing periphery regions.4. The integrated circuit of claim 3 , wherein interconnects of neighboring sets of interconnects turn towards each other and are aligned with corresponding interconnects of the neighboring set.5. The integrated circuit of claim 3 , wherein the interconnects comprise bond pads disposed in the periphery regions.6. The integrated circuit of claim 3 , wherein claim 3 , in the array region claim 3 , each set of interconnects is symmetric about a midpoint line claim 3 , wherein ends of the interconnects forming a set of interconnects are angled relative to a main expanse of the interconnects claim 3 , wherein the ends of the interconnects are angled to extend towards the midpoint line.7. The integrated circuit of ...

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Номер записи: 77
03-03-2022 дата публикации

TECHNIQUES AND DEVICE STRUCTURE BASED UPON DIRECTIONAL SEEDING AND SELECTIVE DEPOSITION

Номер: US20220068923A1
Автор: Chan Kelvin, Kallakuri Shantanu, Varghese Sony, Zeeshan M. Arif
Принадлежит: Applied Materials, Inc.

In one embodiment, a method of selectively forming a deposit may include

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Номер записи: 78
25-02-2016 дата публикации

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

Номер: US20160056158A1
Автор: CHO Taiheui, Jang Hyeon-Woo, KIM KEUNNAM, PARK Junghwan, RYU Ho-In, Yeom Kyehee
Принадлежит:

A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer. 116.-. (canceled)17. A method of manufacturing a semiconductor device , the method comprising:preparing a substrate including a cell region and a peripheral region;defining cell active portions in the cell region and a peripheral active portion in the peripheral region;forming cell gate electrodes respectively buried in grooves crossing the cell active portions;forming an insulating layer on the cell active portions and the peripheral active portion;forming a conductive layer on an entire surface of the substrate having the insulating layer;forming a hard mask layer on the conductive layer;forming cell line patterns by performing a cell patterning process on the hard mask layer and the conductive layer in the cell region; andforming a peripheral gate pattern by performing a peripheral patterning process on the hard mask layer and the conductive layer in the peripheral region,wherein, after one of the cell and peripheral patterning processes is performed, the other of the cell and peripheral patterning processes is performed.18. The method as claimed in claim 17 , wherein forming the conductive layer includes:forming a lower conductive layer ...

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Номер записи: 79
25-02-2016 дата публикации

Recessed Salicide Structure to Integrate a Flash Memory Device with a High K, Metal Gate Logic Device

Номер: US20160056250A1
Автор: Chuang Harry Hak-Lay, Kao Ya-Chen, Liu Shih-Chang, Wu Wei Cheng
Принадлежит:

Some embodiments of the present disclosure provide an integrated circuit (IC) for an embedded flash memory device. The IC includes a flash memory cell having a memory cell gate. A silicide contact pad is arranged in a recess of the memory cell gate. A top surface of the silicide contact pad is recessed relative to a top surface of the memory cell gate. Dielectric side-wall spacers extend along sidewalls of the recess from the top surface of the memory cell gate to the top surface of the silicide contact pad. 1. An integrated circuit (IC) for an embedded flash memory device , the integrated circuit comprising:a flash memory cell having a memory cell gate; anda silicide contact pad arranged in a recess of the memory cell gate, wherein a top surface of the silicide contact pad is recessed relative to a top surface of the memory cell gate; anddielectric sidewall spacers extending along sidewalls of the recess from the top surface of the memory cell gate to the top surface of the silicide contact pad.2. The IC of claim 1 , further comprising a vertical contact extending through the recess and coupled to the silicide contact pad.3. The IC of claim 1 , wherein the memory cell gate is a memory gate extending over a channel region of the flash memory cell.4. The IC of claim 3 , wherein the recess terminates at an upper surface of the memory gate and an upper surface of a dummy select gate adjacent to the memory gate claim 3 , wherein the upper surfaces of the memory gate and dummy select gate are co-planar.5. The IC of claim 4 , wherein the recess is asymmetric with regards to the memory gate and a dummy select gate adjacent to the memory gate.6. The IC of claim 1 , wherein the memory cell gate is a select gate extending over a channel region of the flash memory cell.7. The IC of claim 6 , wherein the recess terminates at an upper surface of the select gate and where the silicide contact pad extends continuously on the upper surface of the select gate between inner sidewalls ...

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Номер записи: 80
15-05-2014 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20140131783A1
Автор: Lee Ki Hong, Park In Su, Pyi Seung Ho
Принадлежит: SK HYNIX INC.

A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block. 1. A semiconductor device comprising:a first conductive layer;at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block;second conductive layers stacked on the first conductive layer; anda second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.2. The semiconductor device of claim 1 , wherein the first slit and the second slit do not overlap with each other.3. The semiconductor device of claim 1 , wherein the first conductive layer is a pipe gate claim 1 , at least one of an uppermost second conductive layer is a selection line claim 1 , and the other second conductive layers are word lines.4. The semiconductor device of claim 1 , wherein the first conductive layer is a source layer claim 1 , at least one of an uppermost second conductive layer is an upper selection line claim 1 , at least one of a lowermost second conductive layer is a lower selection line claim 1 , and the other second conductive layers are word lines.5. A semiconductor device comprising:a first source layer;at least one first slit through the first source layer, and configured to divide the first source layer in the unit of a memory block;conductive layers stacked on the first source layer; andat least one second slit through the conductive layers at different location from the first slit, and configured to divide the conductive layers in the unit of ...

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Номер записи: 81
15-05-2014 дата публикации

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

Номер: US20140131786A1
Автор: CHO Taiheui, Jang Hyeon-Woo, KIM KEUNNAM, PARK Junghwan, RYU Ho-In, Yeom Kyehee
Принадлежит:

A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer. 1. A semiconductor device , comprising:a substrate including a cell region and a peripheral region;a cell gate electrode buried in a groove crossing a cell active portion of the cell region;a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode;a peripheral gate pattern crossing over a peripheral active portion of the peripheral region;a planarized interlayer insulating layer on the substrate around the peripheral gate pattern; anda capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.2. The semiconductor device as claimed in claim 1 , further comprising:a capping line pattern on a top surface of the cell line pattern,wherein a width of a bottom surface of the capping line pattern is substantially equal to a width of the top surface of the cell line pattern, andwherein the capping line pattern ...

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Номер записи: 82
22-02-2018 дата публикации

VERTICAL ANTIFUSE STRUCTURES

Номер: US20180053767A1
Автор: Cheng Kangguo, Li Juntao, Wang Geng, Zhang Qintao
Принадлежит:

Semiconductor devices and methods are provided in which vertical antifuse devices are integrally formed with vertical FET devices, wherein the vertical antifuse devices are formed as part of a process flow for fabricating the vertical FET devices. For example, a semiconductor device comprises a lower source/drain region formed on a substrate, and first and second vertical semiconductor fins formed on the lower source/drain region. First and second metal gate electrodes are formed on sidewalls of the first and second vertical semiconductor fins, respectively. An upper source/drain region is formed on an upper surface of the first vertical semiconductor fin, and a vertical source/drain contact is formed in contact with the upper source/drain region formed on the first vertical semiconductor fin. An upper end of the second vertical semiconductor fin is encapsulated in an insulating material so that the upper end of the second vertical semiconductor fin is floating. 1. A method for fabricating a semiconductor device , comprising:forming a lower source/drain region on a semiconductor substrate;forming a plurality of vertical semiconductor fins on the lower source/drain region, the plurality of vertical semiconductor fins comprising a first vertical semiconductor fin and a second vertical semiconductor fin;forming a first metal gate electrode on a sidewall surface of the first vertical semiconductor fin, and a second metal gate electrode on a sidewall surface of the second vertical semiconductor fin;forming an insulating layer to insulate the first and second metal gate electrodes;forming an upper source/drain region on an upper surface of the first vertical semiconductor fin;forming a vertical source/drain contact to the upper source/drain region formed on the upper surface of the first vertical semiconductor fin; andencapsulating an upper end of the second vertical semiconductor fin in an insulating material so that the upper end of the second vertical semiconductor fin ...

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Номер записи: 83
22-02-2018 дата публикации

Vertical memory device and method of fabricating the same

Номер: US20180053768A1
Автор: Hong-Soo Kim, Kyoung-hoon Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A vertical memory device includes a substrate with a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes parallel to the substrate in the cell array and word line contact regions, the gate electrodes being stacked and spaced apart in a direction perpendicular to the substrate, a channel structure through the gate electrodes in the cell array region, the channel structure being electrically connected to the substrate, a dummy channel structure through the gate electrodes in the word line contact region, the dummy channel structure being spaced apart from the substrate, and a conductive line parallel to the substrate and electrically connected to a first gate electrode, the conductive line crossing at least a portion of an extension of the dummy channel structure in the perpendicular direction.

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Номер записи: 84
05-03-2015 дата публикации

MEMORY DEVICE

Номер: US20150061025A1
Автор: Nakazawa Takashi
Принадлежит:

A memory device according to embodiments includes a cell array region. The cell array region comprises a plurality of transistors sharing a word line, a plurality of memory elements, and a plurality of first contacts configured to connect the plurality of transistors with the plurality of memory elements, respectively, and aligned in a pith. The memory device further comprises a second contact positioned in the pith, along an extension of a row of the plurality of first contacts, outside the cell array region, and configured to be in contact with the word line. 1. A memory device comprising: a plurality of transistors sharing a word line,', 'a plurality of memory elements, and', 'a plurality of first contacts configured to connect the plurality of transistors with the plurality of memory elements, respectively, and aligned in a pith; and, 'a cell array region comprising'}a second contact positioned in the pith, along an extension of a row of the plurality of first contacts, outside the cell array region, and configured to be in contact with the word line.2. The device of claim 1 , whereinthe plurality of transistors comprise a plurality of source/drain regions,the memory device further comprises a first insulating film on the word line in the cell array region,the plurality of first contacts are in contact with the insulating film and the plurality of source/drain regions, andthe second contact is in contact with the word line.3. The device of claim 2 , whereinthe insulating film includes a opening at least in a part of the outside of the cell array region, andthe second contact is in contact with the word line at a portion of the opening.4. The device of claim 3 , further comprising a plurality of second insulating films to isolate the elements claim 3 ,wherein the plurality of second insulating films on at least the part of the outside of the cell array region is lower than the first insulating film.5. The device of claim 4 , further comprising a controller region ...

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Номер записи: 85
22-05-2014 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20140138687A1
Автор: Bin Jin Ho, Lee Ki Hong, Pyi Seung Ho
Принадлежит: SK HYNIX INC.

A semiconductor device includes first conductive layers and first interlayer insulating layers stacked alternately with each other, at least one second conductive layer and at least one second interlayer insulating layer formed on the first conductive layers and the first interlayer insulating layers and stacked alternately with each other, a first semiconductor layer passing through the first conductive layers and the first interlayer insulating layers and including polysilicon, and a second semiconductor layer coupled to the first semiconductor layer and passing through the at least one second conductive layer the at least one second interlayer insulating layer, wherein the second semiconductor layer includes silicon germanium. 1. A semiconductor device , comprising:first conductive layers alternately stacked with first interlayer insulating layers;at least one second conductive layer alternately stacked with at least one second interlayer insulating layer on the first conductive layers and the first interlayer insulating layers;a first semiconductor layer passing through the first conductive layers and the first interlayer insulating layers and including polysilicon; anda second semiconductor layer formed on the first semiconductor layer and passing through the at least one second conductive layer and the at least one second interlayer insulating layer, wherein the second semiconductor layer includes silicon germanium,wherein the first semiconductor layer is configured as a channel layer of a memory cell and the second semiconductor layer is configured as a channel layer of a selection transistor.2. The semiconductor device of claim 1 , wherein the first semiconductor layer or the second semiconductor layer has a tubular structure or a pillar structure.3. The semiconductor device of claim 2 , further comprising:an insulating layer formed in an opening defined in the first semiconductor layer or in the second semiconductor layer.4. The semiconductor device of ...

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Номер записи: 86
22-05-2014 дата публикации

CELL CIRCUITS AND LAYOUTS USED IN WRITE TRACKING CIRCUITS AND READ TRACKING CIRCUITS

Номер: US20140138776A1
Автор: CHANG Jacklyn, HSU Kuoyuan (Peter), TAO Derek C.
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A circuit includes a first transistor and a second transistor of a first type, a first transistor, a second transistor, a third transistor, and a fourth transistor of a second type. The first and second transistors of the first type, and the first transistor and the second transistor of the second type form a cross latch having a first node and a second node. A first terminal of the third transistor of the second type is coupled with the first node. A first terminal of the fourth transistor of the second type is coupled with the second node. At least one of a second terminal of the third transistor of the second type or a second terminal of the fourth transistor of the second type is configured to receive a signal sufficient to turn off the third transistor or the fourth transistor that is not directly from a power source. 1. A circuit comprising:a first transistor of a first type;a second transistor of the first type;a first transistor of a second type;a second transistor of the second type;a third transistor of the second type; anda fourth transistor of the second type; the first transistor of the first type, the second transistor of the first type, the first transistor of the second type, and the second transistor of the second type form a cross latch having a first node and a second node;', 'a first terminal of the third transistor of the second type is coupled with the first node;', 'a first terminal of the fourth transistor of the second type is coupled with the second node; and', 'at least one of a second terminal of the third transistor of the second type or a second terminal of the fourth transistor of the second type is configured to receive a signal that is not directly from a power source and is sufficient to turn off the third transistor or the fourth transistor., 'wherein'}2. The circuit of claim 1 , whereina third terminal of the fourth transistor of the second type is electrically coupled with the first terminal of the fourth transistor of the second ...

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Номер записи: 87
22-05-2014 дата публикации

Semiconductor Device

Номер: US20140138778A1
Автор: Kato Kiyoshi
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material. 1 the first memory cell comprising:', 'a first transistor having a first channel formation region electrically connected to a first bit line through a source or a drain of the first transistor; and', 'a second transistor having a second channel formation region electrically connected to a gate of the first transistor through a source or a drain of the second transistor, and', 'the second memory cell comprising:', 'a third transistor having a third channel formation region electrically connected to a second bit line through a source or a drain of the third transistor; and', 'a fourth transistor having a fourth channel formation region electrically connected to a gate of the third transistor through a source or a drain of the fourth transistor, and, 'a memory cell array comprising a first memory cell and a second memory cell;'}a driver circuit associated with the first memory cell and the second memory cell,wherein a first semiconductor material included in the first channel formation region is selected from the group consisting of silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide, andwherein the first memory cell and the second memory cell are ...

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Номер записи: 88
03-03-2016 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

Номер: US20160064041A1
Автор: Aochi Hideaki, FUKUZUMI Yoshiaki, Okada Takayuki
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a semiconductor memory device includes a substrate; a memory cell array including a plurality of memory cells stacked on the substrate; an inter-layer insulating layer provided on the memory cell array; and a first control circuit. The first control circuit includes a first transistor and first semiconductor layer, a number of a grain boundary of the first semiconductor layer is not less than a number of a grain boundary of the substrate, and the first control circuit is provided on the inter-layer insulating layer and electrically connected to the memory cells. 1. A semiconductor memory device , comprising:a substrate;a memory cell array including a plurality of memory cells stacked on the substrate;an inter-layer insulating layer provided on the memory cell array; anda first control circuit provided on the inter-layer insulating layer and electrically connected to the memory cells, the first control circuit including a first transistor and first semiconductor layer, a number of a grain boundary of the first semiconductor layer being not less than a number of a grain boundary of the substrate.2. The semiconductor memory device according to claim 1 , further comprising a second control circuit provided on the substrate and electrically connected to the memory cells claim 1 , the second control circuit including a second transistor.3. The semiconductor memory device according to claim 2 , wherein a first gate insulator film provided on the first semiconductor layer; and', 'a first gate electrode provided on the first gate insulator film, and, 'the first transistor includes a second semiconductor layer;', 'a second gate insulator film provided on the second semiconductor layer, the second gate insulator film being thicker than the first gate insulator film; and', 'a second gate electrode provided on the second gate insulator film., 'the second transistor includes4. The semiconductor memory device according to claim 1 , wherein a thickness ...

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Номер записи: 89
01-03-2018 дата публикации

SEMICONDUCTOR DIE PACKAGE AND METHOD OF PRODUCING THE PACKAGE

Номер: US20180061741A1
Автор: Beyne Eric
Принадлежит:

A package including a first die embedded in a reconstructed wafer obtainable by the known FO-WLP or eWLB technologies is disclosed. In one aspect and in addition to the first die, a Through Substrate Via insert is embedded in the wafer, the TSV insert being a separate element, possibly a silicon die with metal filled vias interconnecting contacts on the front and back sides of the insert. A second die is mounted on the back side of the substrate, with contacts on the second die in electrical connection with the TSV insert's contacts on the back side of the substrate. On the front side of the substrate, a lateral connecting device is mounted which interconnects the TSV insert's contacts on the front side of the substrate to contacts on the front side of the first die. The lateral connecting device and the TSV insert thereby effectively interconnect the contacts on the first and second dies. In another aspect, the lateral connecting device is mounted on a redistribution layer on the front side of the substrate, as it is known from FO-WLP technology. 1. A semiconductor die package comprising: the TSV insert comprises N contacts on the front side of the TSV insert, N contacts on the backside of the TSV insert, and N metal-filled vias individually interconnecting the contacts on the front and back sides of the TSV insert, N being an integer higher than or equal to 1,', 'the first semiconductor die comprises N contacts on the front side of the first semiconductor die,', 'the first semiconductor die further comprises one or more contact terminals on the front side of the first semiconductor die;, 'a substrate formed of a mold material, wherein embedded side by side in the mold material are a first semiconductor die and a Through Substrate Via (TSV) insert, the substrate, the TSV insert, and the first semiconductor die having a front side and a back side, and wherein'}a second semiconductor die mounted on the back side of the substrate, the second semiconductor die ...

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Номер записи: 90
04-03-2021 дата публикации

Dye-sensitized optoelectronic memory

Номер: US20210065788A1
Автор: Eng Huat Toh, Jianxun Sun, Juan Boon Tan, Tu Pei Chen
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

Structures for an optoelectronic memory and related fabrication methods. A metal oxide layer is located on an interlayer dielectric layer. A layer composed of a donor/acceptor dye is positioned on a portion of the first layer.

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Номер записи: 91
22-05-2014 дата публикации

Gcib-treated resistive device

Номер: US20140141590A1
Автор: Gurtej S. Sandhu, John A. Smythe, III
Принадлежит: Micron Technology Inc

The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.

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Номер записи: 92
04-03-2021 дата публикации

SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STORAGE DEVICE

Номер: US20210066297A1
Автор: Matsumoto Sota, NISHIMURA Takahito
Принадлежит: Kioxia Corporation

A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory portion in which a plurality of memory cells are disposed and a staircase portion in which end portions of the plurality of conductive layers form a staircase shape. The staircase portion has three or more first sub-staircase portions ascending in a direction opposite to a direction toward the memory portion, and at least one first sub-staircase portion among the three or more first sub-staircase portions is divided into at least an upper staircase and a lower staircase by a difference in level larger than a difference in level of each stair of the first sub-staircase portion. 1. A semiconductor storage device comprisinga stacked body in which a plurality of conductive layers are stacked via an insulating layer, the stacked body having a memory portion in which a plurality of memory cells are disposed and a staircase portion in which end portions of the plurality of conductive layers form a staircase shape,wherein the staircase portion has three or more first sub-staircase portions ascending in a direction opposite to a direction toward the memory portion, andat least one first sub-staircase portion among the three or more first sub-staircase portions is divided into at least an upper staircase and a lower staircase by a difference in level larger than a difference in level of each stair of the first sub-staircase portion.2. The semiconductor storage device according to claim 1 , whereineach stair of the first sub-staircase portion has a same number of a layer or layers of the conductive layers, andthe difference in level that divides the first sub-staircase portion includes more layers of the conductive layers than each stair of the first sub-staircase portion.3. The semiconductor storage device according to claim 1 , whereinsecond sub-staircase portions ascending in a direction ...

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Номер записи: 93
12-03-2015 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Номер: US20150070964A1
Автор: ASAO Yoshiaki, Yamada Yuki
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A semiconductor memory device according to an embodiment includes a semiconductor layer, a gate electrode, a ferroelectric film provided between the semiconductor layer and the gate electrode, a first impurity region of a first conductivity type provided on one side of the gate electrode in the semiconductor layer, a second impurity region of a second conductivity type provided on the other side of the gate electrode in the semiconductor layer, a third impurity region of the first conductivity type provided between the first impurity region and the second impurity region in the semiconductor layer facing the gate electrode and having a lower first-conductivity-type impurity concentration than the first impurity region, a first wiring connected to the first impurity region through a connection portion contacting with the first impurity region, and a second wiring connected to the second impurity region through a connection portion contacting with the second impurity region. 1. A semiconductor memory device comprising:a semiconductor layer;a gate electrode;a ferroelectric film provided between the semiconductor layer and the gate electrode;a first impurity region of a first conductivity type provided on one side of the gate electrode in the semiconductor layer;a second impurity region of a second conductivity type provided on the other side of the gate electrode in the semiconductor layer;a third impurity region of the first conductivity type provided between the first impurity region and the second impurity region in the semiconductor layer, the third impurity region facing the gate electrode and having a lower first-conductivity-type impurity concentration than the first impurity region;a first wiring connected to the first impurity region through a first connection portion, the first connection portion contacting with the first impurity region; anda second wiring connected to the second impurity region through a second connection portion, the second connection ...

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Номер записи: 94
28-02-2019 дата публикации

METHOD FOR FORMING THREE-DIMENSIONAL INTEGRATED WIRING STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF

Номер: US20190067105A1
Автор: CHEN Jun, Hu Si Ping, Lu Zhenyu, Zhu Jifeng
Принадлежит: Yangtze Memory Technologies Co., Ltd.

Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming a dielectric layer in a first substrate; forming a semiconductor structure having a first conductive contact over a front side of the first substrate; and forming a second conductive contact at a backside of the first substrate, wherein the second conductive contact extends through a backside of the dielectric layer and connects to a second end of the first conductive contact. The 3D integrated wiring structure can include a first substrate; a dielectric layer in the first substrate; a semiconductor structure over the front side of the first substrate, having a first conductive contact; and a second conductive contact at the backside of the first substrate, and the second conductive contact extends through a backside of the dielectric layer and connects to the second end of the first conductive contact. 1. A method for forming a 3D integrated wiring structure , comprising:forming a dielectric layer in a first substrate;forming a semiconductor structure over a front side of the first substrate, wherein the semiconductor structure comprises a first conductive layer above the dielectric layer and a first conductive contact, wherein a first end of the first conductive contact connects to the first conductive layer and a second end of the first conductive contact extends through a front side of the dielectric layer; andforming a second conductive contact at a backside of the first substrate, wherein the second conductive contact extends through a backside of the dielectric layer and connects to the second end of the first conductive contact.2. The method of claim 1 , wherein a backside of the dielectric layer is between the front side and the backside of the first substrate claim 1 , and a front side of the dielectric layer is at a same height as the front side of the first substrate with respect to the backside of the first substrate; or a ...

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Номер записи: 95
28-02-2019 дата публикации

METHOD FOR FORMING THREE-DIMENSIONAL INTEGRATED WIRING STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF

Номер: US20190067106A1
Автор: CHEN Jun, Hu Si Ping, Lu Zhenyu, Zhu Jifeng
Принадлежит: Yangtze Memory Technologies Co., Ltd.

Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming a dielectric layer in a contact hole region at a front side of a first substrate; forming a semiconductor structure at the front side of the first substrate and the semiconductor structure having a first conductive contact, forming a recess at a backside of the first substrate to expose at least a portion of the dielectric layer; and forming a second conductive layer above the exposed dielectric layer to connect the first conductive contact. The 3D integrated wiring structure can include a first substrate having a contact hole region; a dielectric layer disposed in the contact hole region; a semiconductor structure formed at the front side of the first substrate, having a first conductive contact; a recess formed at the backside of the first substrate to expose at least a portion of the dielectric layer; and a second conductive layer above the exposed dielectric layer. 1. A method for forming a 3D integrated wiring structure , comprising:forming a dielectric layer in a contact hole region at a front side of a first substrate;forming a semiconductor structure at the front side of the first substrate, comprising forming a semiconductor device layer, a first conductive layer at a front side of the semiconductor device layer, and a first conductive contact, wherein a first end of the first conductive contact connects to the first conductive layer and a second end of the first conductive contact extends vertically through at least a portion of the semiconductor device layer;forming a recess at a backside of the first substrate to expose at least a portion of the dielectric layer; andforming a second conductive layer above the exposed dielectric layer to connect the first conductive contact.2. The method of claim 1 , wherein a backside of the dielectric layer is between the front side and the backside of the first substrate claim 1 , and a front ...

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Номер записи: 96
08-03-2018 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20180069021A1
Автор: LEE Nam Jae
Принадлежит: SK HYNIX INC.

A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first cell structure and the second cell structure, and may be electrically coupled to the first and second cell structures. The pad structure may have a plurality of stepped structures. The circuit may be disposed under the pad structure. The one or more openings may pass through the pad structure, and may expose the circuit. The one or more openings may be disposed between the plurality of stepped structures. 1. A method of manufacturing a semiconductor device , comprising:forming a circuit on a pad region of a substrate comprising a first cell region, the pad region, and a second cell region, which are successively arranged in a first direction;{'sup': 'th', 'forming a stacked structure over the substrate on which the circuit is formed, the stacked structure including first to n(n is a natural number greater than or equal to three) groups stacked on top of one another;'}partially patterning the pad region of the stacked structure and forming a first cell structure disposed in the first cell region, a second cell structure disposed in the second cell region, and a pad structure disposed in the pad region, the pad structure comprising a plurality of stepped structures and being electrically coupled to the first and second cell structures; andforming one or more openings passing through the pad structure and exposing the circuit, the one or more openings being disposed between the plurality of stepped structures.2. The method of claim 1 , wherein forming the stacked structure comprises:forming the first group including first material layers and second material layers which are alternately stacked on top of one another;forming first slit insulating layers passing through the first group in the pad region and extending in the first direction; and{'sup': th', 'th, 'forming the second to ...

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Номер записи: 97
19-03-2015 дата публикации

SEMICONDUCTOR MEMORY DEVICE HAVING PADS

Номер: US20150076614A1
Автор: Choi Hae Rang, HAN Sung Woo, HWANG Tae Jin, Jang Jae Min, KIM Hyung Soo, Kim Yong Ju, LEE Ji Wang, Oh Ic Su, Park Chang Kun, SONG Hee Woong, SONG Seong Hwi
Принадлежит:

A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power. 1. A semiconductor memory device , comprising:a semiconductor circuit substrate; and a first differential signal data pad that is electrically connected to a first circuit unit that comprises a first pull up circuit unit and a first pull down circuit unit;', 'a second differential signal data pad electrically connected to a second circuit unit that comprises a second pull up circuit unit and a second pull down circuit unit; and', 'a power pad interposed between the first and second differential signal data pads and electrically connected to each of the first and second circuit units., 'a chip pad region included in the semiconductor circuit substrate, the chip pad region comprising a plurality of pads, wherein the pads include2. The semiconductor memory device of claim 1 , wherein the power pad is an external supply power pad claim 1 , and the external supply power pad is electrically connected to each of the first pull up circuit unit and the second pull up circuit unit.3. The semiconductor memory device of claim 2 , wherein the resistance between the first pull up circuit unit and the power pad is equal to the resistance between the second pull up circuit unit and the power pad.4. The semiconductor memory device of claim 1 , wherein the power pad is a ...

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Номер записи: 98
19-03-2015 дата публикации

SEMICONDUCTOR MEMORY DEVICE HAVING PADS

Номер: US20150076703A1
Автор: Choi Hae Rang, HAN Sung Woo, HWANG Tae Jin, Jang Jae Min, KIM Hyung Soo, Kim Yong Ju, LEE Ji Wang, Oh Ic Su, Park Chang Kun, SONG Hee Woong, SONG Seong Hwi
Принадлежит:

A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power. 1. A semiconductor memory device , comprising:a chip pad region comprising a first differential signal pad configured to receive a first differential data signal, a second differential signal pad configured to receive a second differential data signal having a level being opposite to a level of the first differential data signal, and a power pad configured to receive a voltage through a power signal line and interposed between the first and second differential signal pads,wherein a first distance between the first differential signal pad and the power pad is substantially same with a second distance between the second differential signal pad and the power pad, to be equalized an effective termination resistor between the first differential signal pad and the power pad, with an effective termination resistor between the second differential signal pad and the power pad.2. The semiconductor memory device of claim 1 , further comprising a first and a second data lines formed at a first side with reference to the chip pad region claim 1 ,wherein each of the first and the second data lines is arranged adjacent to each other and electrically connected to the first and the second differential signal pads respectively.3. The semiconductor memory device of claim 2 ...

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Номер записи: 99
19-03-2015 дата публикации

SEMICONDUCTOR DEVICE WITH BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME

Номер: US20150079744A1
Автор: HWANG Eui-Seong
Принадлежит:

A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer. 120-. (canceled)21. A method for fabricating a semiconductor device , comprising:defining trenches in a substrate;forming buried bit lines to partially fill the trenches;forming a first source/drain layer to fill remaining portions of the trenches on the buried bit lines;sequentially forming a second source/drain layer and a channel layer on an entire surface of a sacrificial substrate;bonding the substrate and the sacrificial substrate with each other for the first source/drain layer and the channel layer to face each other;removing the sacrificial substrate;forming stack patterns by selectively etching the second source/drain layer and the channel layer for the etched channel layer to contact with the first source/drain layer; andforming word lines to cross with the buried bit lines and be disposed adjacent to sidewalls of the channel layer.22. The method according to claim 21 , wherein the stack patterns include pillar type patterns disposed at intersections of the word lines with the buried bit lines.23. The semiconductor device according to claim 22 , wherein the word lines extend in one direction and surround the channel layer of the stack patterns.24. The method according to claim 22 , the forming of the first source/drain layer comprising:forming a semiconductor layer on the substrate including the buried bit lines;performing a planarization process until the substrate is exposed;selectively etching the semiconductor layer to form the first source/ ...

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Номер записи: 100