CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY

Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

NON-VOLATILE SPLIT GATE MEMORY CELLS WITH INTEGRATED HIGH K METAL CONTROL GATES AND METHOD OF MAKING

Integrated circuit and method for manufacturing thereof

A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. At least two semiconductor word lines, two memory cells in between the two semiconductor word lines, and a semiconductor gate in between the two memory cells are formed in the memory region. A transistor device including a dummy gate is formed in the core region, and a height of the dummy gate is larger than a height of the semiconductor word lines. A protecting layer is formed on the semiconductor word lines, the memory cells, the semiconductor gate and the transistor device. A portion of the protecting layer is removed to expose the dummy gate and followed be removing the dummy gate to form a gate trench in the transistor device. Then a metal gate is formed in the gate trench.

실리콘-온-인슐레이터 기판으로 임베디드 메모리 디바이스를 제조하는 방법

... 반도체 디바이스를 형성하는 방법은 실리콘 기판, 실리콘 상의 제1 절연 층, 및 제1 절연 층 상의 실리콘 층으로 시작한다. 실리콘 층 및 절연 층은 단지 제2 기판 영역으로부터 제거된다. 제2 절연 층은 기판 제1 영역의 실리콘 층 위에 그리고 제2 기판 영역의 실리콘 위에 형성된다. 제1 복수의 트렌치는 제1 기판 영역에 형성되고, 여기서 각각은 모든 층을 통과해서 연장되고 실리콘 내로 연장된다. 제2 복수의 트렌치는 제2 기판 영역에 형성되고, 여기서 각각은 제2 절연 층을 통과해서 연장되고 실리콘 내로 연장된다. 절연 재료가 제1 및 제2 트렌치들에 형성된다. 로직 디바이스는 제1 기판 영역에 형성되고, 메모리 셀은 제2 기판 영역에 형성된다.

Cell boundary structure for embedded memory

Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.

SEMICONDUCTOR STRUCTURE INCLUDING A PLURALITY OF PAIRS OF NONVOLATILE MEMORY CELLS AND AN EDGE CELL

A semiconductor structure includes a plurality of pairs of nonvolatile memory cells arranged in a row, an edge cell positioned adjacent to the pairs of nonvolatile memory cells, and first, second, third, and fourth gates. Each pair of nonvolatile memory cells includes first and second nonvolatile memory cells. The first and second gates extend across the first nonvolatile memory cells, the second gate partially overlapping the first gate, and the third and fourth gates extend across the second nonvolatile memory cells, the fourth gate partially overlapping the third gate. Each of the first, second, third, and fourth gates has an end portion that is positioned in the edge cell, and the edge cell includes a protection layer that is positioned over the end portions of the first, second, third, and fourth gates and covers an end face of the second and fourth gates.

Semiconductor device and method for manufacturing the same

According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type; a stacked body; a plurality of columnar portions; a plurality of first insulating portions having a wall configuration; and a plurality of second insulating portions having a columnar configuration. The columnar portions extend in a stacking direction of the stacked body. The columnar portions include a semiconductor body and a charge storage film. The first insulating portions extend in the stacking direction and in a first direction crossing the stacking direction. The second insulating portions extend in the stacking direction. A wide of the second insulating portions along a second direction crossing the first direction in a plane is wider than a wide of the first insulating portions along the second direction. The second insulating portions are disposed in a staggered lattice configuration.

For making silicon-on-insulator substrate of the embedded memory device method

With the single-layer polycrystal of EEPROM and its preparation method

Semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of isolation structures, a charge storage layer, and a conductive layer. The substrate has a memory region and a logic region. The substrate in the memory region has a plurality of semiconductor fins. The isolation structures are disposed in the substrate to isolate the semiconductor fins. The semiconductor fins are protruded beyond the isolation structures. The charge storage layer covers the semiconductor fins. The conductive layer is disposed across the semiconductor fins and the isolation structures such that the charge storage layer is disposed between the conductive layer and the semiconductor fins.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

In a method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a logic circuit formed in a peripheral area, a mask layer is formed over a substrate in the memory cell area and the peripheral area. A resist mask is formed over the peripheral area. The mask layer in the memory cell area is patterned by using the resist mask as an etching mask. The substrate is etched in the memory cell area. After etching the substrate, a memory cell structure in the memory cell area and a gate structure for the logic circuit are formed. A dielectric layer is formed to cover the memory cell structure and the gate structure. A planarization operation is performed on the dielectric layer. An upper portion of the memory cell structure is planarized during the planarization operation.

CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY

Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

Semiconductor device and method of manufacturing the same

A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

Si recess method in HKMG replacement gate technology

The present disclosure relates to an integrated circuit (IC). The IC includes a substrate, which includes a periphery region having a first substrate surface and a memory cell region having a second substrate surface. The second substrate surface is recessed within the substrate relative to the first substrate surface. A high k metal gate (HKMG) transistor is disposed on the first substrate surface and includes a HKMG gate. Two neighboring flash memory cells are disposed on the second substrate surface and include a pair of flash memory cell control gates. Top surfaces of the HKMG gate and flash memory cell control gates are co-planar.

Method of forming split gate memory cells with thinned tunnel oxide

A method of forming a memory device includes forming a floating gate on a memory cell area of a semiconductor substrate, having an upper surface terminating in an edge. An oxide layer is formed having first and second portions extending along the logic and memory cell regions of the substrate surface, respectively, and a third portion extending along the floating gate edge. A non-conformal layer is formed having a first, second and third portions covering the oxide layer first, second and third portions, respectively. An etch removes the non-conformal layer third portion, and thins but does not entirely remove the non-conformal layer first and second portions. An etch reduces the thickness of the oxide layer third portion. After removing the non-conformal layer first and second portions, a control gate is formed on the oxide layer second portion and a logic gate is formed on the oxide layer first portion.

Semiconductor device and manufacturing method thereof

Method of making embedded memory device with silicon-on-insulator substrate

A method of forming a semiconductor device with memory cells and logic devices on the same silicon-on-insulator substrate. The method includes providing a substrate that includes silicon, a first insulation layer directly over the silicon, and a silicon layer directly over the first insulation layer. Silicon is epitaxially grown on the silicon layer in a first (memory) area of the substrate and not in a second (logic device) area of the substrate such that the silicon layer is thicker in the first area of the substrate relative to the second area of the substrate. Memory cells are formed in the first area of the substrate, and logic devices are formed in the second area of the substrate.

실리콘-온-인슐레이터 기판으로 임베디드 메모리 디바이스를 제조하는 방법

... 반도체 디바이스를 형성하는 방법은 실리콘 기판, 실리콘 상의 제1 절연 층, 및 제1 절연 층 상의 실리콘 층으로 시작한다. 실리콘 층 및 절연 층은 단지 제2 기판 영역으로부터 제거된다. 제2 절연 층은 기판 제1 영역의 실리콘 층 위에 그리고 제2 기판 영역의 실리콘 위에 형성된다. 제1 복수의 트렌치는 제1 기판 영역에 형성되고, 여기서 각각은 모든 층을 통과해서 연장되고 실리콘 내로 연장된다. 제2 복수의 트렌치는 제2 기판 영역에 형성되고, 여기서 각각은 제2 절연 층을 통과해서 연장되고 실리콘 내로 연장된다. 절연 재료가 제1 및 제2 트렌치들에 형성된다. 로직 디바이스는 제1 기판 영역에 형성되고, 메모리 셀은 제2 기판 영역에 형성된다.

Integration of split gate flash memory array and logic devices

A memory device and method including a semiconductor substrate with memory and logic device areas. A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.

Method for fabricating semiconductor device

A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.

Verfahren zur Herstellung eines Halbleiterbauelements mit einem nichtflüchtigen Speicher und einer Logikschaltung

Verfahren zur Herstellung eines Halbleiter-Bauelements mit einem nichtflüchtigen Speicher, der in einem Speicherzellenbereich (CA) hergestellt ist, und einer Logikschaltung, die in einem Peripherie-Bereich (PA) hergestellt wird, mit den folgenden Schritten:Herstellen einer Maskenschicht über einem Substrat (10) in dem Speicherzellenbereich (CA) und dem Peripherie-Bereich (PA);Herstellen einer Resist-Maske (40) über dem Peripherie-Bereich (PA);Strukturieren der Maskenschicht in dem Speicherzellenbereich (CA) unter Verwendung der Resist-Maske (40) als eine Ätzmaske;Ätzen des Substrats (10) in dem Speicherzellenbereich (CA);nach dem Ätzen des Substrats (10) Herstellen einer Speicherzellenstruktur (MC) in dem Speicherzellenbereich (CA) und Herstellen einer Gate-Struktur (450) für die Logikschaltung;Herstellen einer dielektrischen Schicht (600) über der Speicherzellenstruktur (MC) und der Gate-Struktur (450); undDurchführen eines Planarisierungsprozess an der dielektrischen Schicht (600), wobei ...

Semiconductor device and method of manufacturing the same

In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.

실리콘-온-인슐레이터 기판으로 임베디드 메모리 디바이스를 제조하는 방법

... 동일한 실리콘-온-인슐레이터 기판 상에 메모리 셀들 및 로직 디바이스들을 갖는 반도체 디바이스를 형성하는 방법이 개시된다. 본 방법은, 실리콘, 실리콘 바로 위의 제1 절연 층, 및 제1 절연 층 바로 위의 실리콘 층을 포함하는 기판을 제공하는 단계를 포함한다. 실리콘은, 실리콘 층이 기판의 제2 (로직 디바이스) 영역에 대해 기판의 제1 (메모리) 영역에서 더 두껍도록 기판의 제1 영역에서는 실리콘 층 상에서 에피텍셜로 성장되지만 기판의 제2 영역에서는 성장되지 않는다. 메모리 셀들은 기판의 제1 영역에 형성되고, 로직 디바이스들은 기판의 제2 영역에 형성된다.

Techniques to avoid or limit implant punch through in split gate flash memory devices

Some embodiments of the present disclosure relate to a flash memory device. The flash memory device includes first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate. A common S/D region is arranged laterally between the first and second individual S/D regions, and is separated from the first individual S/D region by a first channel region and is separated from the second individual S/D region by a second channel region. An erase gate is arranged over the common S/D. A floating gate is disposed over the first channel region and is arranged to a first side of the erase gate. A control gate is disposed over the floating gate. A wordline is disposed over the first channel region and is spaced apart from the erase gate by the floating gate and the control gate. An upper surface of the wordline is a concave surface.

Array boundfary structure to reduce dishing

A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Robust nucleation layers for enhanced fluorine protection and stress reduction in 3D NAND word lines

A silicon-containing nucleation layer can be employed to provide a self-aligned template for selective deposition of tungsten within backside recesses during formation of a three-dimensional memory device. The silicon-containing nucleation layer may remain as a silicon layer, converted into a tungsten silicide layer, or replaced with a tungsten nucleation layer. Tungsten deposition can proceed only on the surface of the silicon-containing nucleation layer or a layer derived therefrom in a subsequent tungsten deposition process.

Patterning a gate stack of a non-volatile memory (nvm) with simultaneous etch in non-nvm area

Method for manufacturing semiconductor device and semiconductor device

According to one embodiment, a method for manufacturing a semiconductor device includes forming a first metal material inside the first holes; forming a plurality of metal layers on the first region, the metal layers being stacked with an insulator interposed, the metal layers including a plurality of terrace portions arranged in a staircase configuration with a level difference; forming a second insulating layer on the first insulating layer and on the terrace portions; simultaneously forming a second hole and a plurality of third holes piercing the second insulating layer, the second hole reaching the first metal material, the third holes reaching the terrace portions; and forming a second metal material inside the second hole and inside the third holes.

Anti-deciphering contacts

A method of making an integrated circuit that is resistant to an unauthorized duplication through reverse engineering includes forming a plurality of false contacts and/or false interconnection vias in the integrated circuit. These false contacts and/or false interconnection vias are connected as true contacts and true interconnection vias by lines patterned in a metallization layer deposited over an insulating dielectric layer or multilayer through which the true contacts and/or the true interconnection vias are formed. False contacts and false vias extend in the respective dielectric layers or multilayers to a depth insufficient to reach the active areas of a semiconductor substrate for false contacts, or to a depth insufficient to reach a layer of conductive material below the dielectric layers or multilayers for false interconnection vias.

Peripheral circuit, three-dimensional memory and preparation method thereof

SEMICONDUCTOR DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND LOGIC DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND LOGIC DEVICE

A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device. 1. A semiconductor device , comprising: a first well region formed in a substrate,', 'a tunneling gate insulator formed on the first well region,', 'a floating gate formed on the tunneling gate insulator,', 'a control gate insulator formed on the substrate,', 'a control gate formed on the control gate insulator, and', 'a first source region and a first drain region formed on opposite sides of the control gate, respectively; and, 'a nonvolatile memory device, comprising a first logic well region formed in the substrate,', 'a first logic gate insulator formed on the first logic well region,', 'a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device, and', 'a first logic source region and a first logic drain region formed on opposite sides of the first logic gate, respectively,', 'wherein the first logic well region has a depth shallower with respect to the first logic gate than a depth of the first logic well region with respect to the first logic source region and the first logic drain region., 'a first logic device, comprising2. The semiconductor ...

METHOD OF MAKING EMBEDDED MEMORY DEVICE WITH SILICON-ON-INSULATOR SUBSTRATE

Integration of split gate flash memory arrays and logic devices

THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICE

A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than ...

Method for integrating non-volatile memory cells with static random access memory cells and logic transistors

A method of making a semiconductor device is described. The method comprises depositing a first polysilicon layer in a non-volatile memory (NVM) region and a logic region of a substrate. A first coating layer is deposited over the first polysilicon layer. The first coating layer and the first polysilicon layer are patterned to form a first gate in the NVM region. A memory cell is formed including the first gate. The first coating layer and the first layer of polysilicon in the logic region are removed and a logic gate polysilicon layer is deposited. The logic gate polysilicon layer is patterned to form a second gate in the logic region while the logic gate polysilicon layer is removed from the NVM region. Source/drain regions of the memory cell and the second gate are implanted concurrently.

Is used for processing the carrier and method for making charge storage memory primitive method

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

Method of forming split gate memory cells with thinned side edge tunnel oxide

A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.

ARRAY BOUNDARY STRUCTURE TO REDUCE DISHING

A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Method of forming a semiconductor structure

The present invention provides a method of forming a semiconductor structure (10) comprising a substrate (12) having a patterned Oxide-Nitride-Oxide (ONO) insulating layer (22) provided over a portion of the substrate (12). The invention employs an Oxide-Nitride-Silicon structure (38, 40, 42) as the basis for the ONO layer, which has the advantage that the upper silicon sub-layer (42) of the structure is resistant to damage during the photoresist stripping step of a patterning process and is then available for re-oxidizing into an oxide layer forming the upper sub-layer of the required ONO structure.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on the substrate, a floating gate disposed on the first dielectric layer, a control gate, and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer comprises one of a silicon oxide layer, a silicon nitride layer and a multi-layer of them. The first dielectric layer includes a 1-1 dielectric layer formed on the substrate, and a 2-1 dielectric layer formed on the 1-1 dielectric layer. The 2-1 dielectric layer includes a dielectric material having a higher dielectric constant than silicon nitride. COPYRIGHT KIPO 2018 ...

Method for manufacturing semiconductor device

Nonvolatile split gate memory cell with integrated high K metal control gate and manufacturing method

Mask design for embedded memory

Various embodiments of the present application are directed to a method for forming an integrated circuit (IC), and the associated integrated circuit. In some embodiments, a substrate is provided including a logic region having a plurality of logic sub-regions including a low-voltage logic sub-region and a high-voltage logic sub-region. The method further comprises forming a stack of gate dielectric precursor layers on the plurality of logic sub-regions and removing the stack of gate dielectric precursor layers from the low-voltage logic sub-region and the high-voltage logic sub-region. The method further comprises forming a high-voltage gate dielectric precursor layer on the low-voltage logic sub-region and the high-voltage logic sub-region and removing the high-voltage gate dielectric precursor layer from the low-voltage logic sub-region. The low-voltage logic sub-region has a logic device configured to operate at a voltage smaller than that of another logic device of the high-voltage ...

Semiconductor device and manufacturing method thereof

In a method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a logic circuit formed in a peripheral area, a mask layer is formed over a substrate in the memory cell area and the peripheral area. A resist mask is formed over the peripheral area. The mask layer in the memory cell area is patterned by using the resist mask as an etching mask. The substrate is etched in the memory cell area. After etching the substrate, a memory cell structure in the memory cell area and a gate structure for the logic circuit are formed. A dielectric layer is formed to cover the memory cell structure and the gate structure. A planarization operation is performed on the dielectric layer. An upper portion of the memory cell structure is planarized during the planarization operation.

Molybdenum-containing conductive layers for control gate electrodes in a memory structure

A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A molybdenum-containing portion can be formed in each backside recess. Each backside recess can be filled with a molybdenum-containing portion alone, or can be filled with a combination of a molybdenum-containing portion and a metallic material portion including a material other than molybdenum.

Three-dimensional (3D) semiconductor memory device

A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than ...

Method Of Forming A Device With FINFET Split Gate Non-volatile Memory Cells And FINFET Logic Devices

A method of forming a device with a silicon substrate having upwardly extending first and second fins. A first implantation forms a first source region in the first silicon fin. A second implantation forms a first drain region in the first silicon fin, and second source and drain regions in the second silicon fin. A first channel region extends between the first source and drain regions. A second channel region extends between the second source and drain regions. A first polysilicon deposition is used to form a floating gate that wraps around a first portion of the first channel region. A second polysilicon deposition is used to form an erase gate wrapping around first source region, a word line gate wrapping around a second portion of the first channel region, and a dummy gate wrapping around the second channel region. The dummy gate is replaced with a metal gate.

Flash memory containing air gaps

A flash memory is provided and includes a substrate including a memory cell region; a memory transistor array including memory transistors and selecting transistors in the memory cell region; a functional layer covering outer surfaces of the memory transistors and selecting transistors, as well as surfaces of the substrate between adjacent memory transistors and selecting transistors; a dielectric layer covering top surfaces of the memory transistors and selecting transistors and fills gaps between each selecting transistor and a corresponding adjacent memory transistor; and air gaps formed between adjacent memory transistors. Each selecting transistor is used for selecting one column of memory transistors in the memory transistor array. The functional layer has a roughened surface capable of absorbing water. The air gaps in the flash memory are water vapor induced air gaps.

Method of manufacturing non-volatile memory

Semiconductor device and method of manufacturing the same

In a semiconductor substrate, a memory cell region in which a flash memory cell is formed is defined by an element isolation region. A floating gate electrode of the flash memory cell includes a protruding portion protruding toward an erase gate electrode so as to flare from a portion located immediately below a control gate electrode. Protruding portion includes an end face of a height corresponding to a thickness, and an inclined surface continuous with end face. Protruding portion faces erase gate electrode with a tunnel oxide film interposed therebetween.

Method of making embedded memory device with silicon-on-insulator substrate

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A semiconductor device includes: a substrate; a first semiconductor chip; a first adhesive layer; a second semiconductor chip; a second adhesive layer; and a spacer. The substrate has a first surface. The first semiconductor chip is provided above the first surface. The first adhesive layer is provided on a lower surface, which is opposed to the substrate, of the first semiconductor chip and contains a plurality of types of resins different in molecular weight. The second semiconductor chip is provided between the substrate and the first adhesive layer. The second adhesive layer covers surroundings of the second semiconductor chip in a view from a normal direction of a first surface, and contains at least one type of the resin lower in molecular weight than the other resins among the plurality of types of resins contained in the first adhesive layer. The spacer covers surroundings of the second adhesive layer in the view from the normal direction of the first surface.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A second gate dielectric film material and a memory gate electrode material are formed on a semiconductor substrate. The memory gate electrode material and the second gate dielectric film material formed in a peripheral circuit forming region are removed, and a part of each of the memory gate electrode material and the second gate dielectric film material is left in the memory cell forming region. Thereafter, in a state that the semiconductor substrate in the memory cell forming region is covered with a part of each of the memory gate electrode material and the second gate dielectric film material, heat treatment is performed to the semiconductor substrate to form a third gate dielectric film on the semiconductor substrate located in the peripheral circuit forming region. Thereafter, a memory gate electrode and a second gate dielectric film are formed.

Semiconductor device and method of manufacturing same

Method of manufacturing semiconductor device

A second gate dielectric film material and a memory gate electrode material are formed on a semiconductor substrate. The memory gate electrode material and the second gate dielectric film material formed in a peripheral circuit forming region are removed, and a part of each of the memory gate electrode material and the second gate dielectric film material is left in the memory cell forming region. Thereafter, in a state that the semiconductor substrate in the memory cell forming region is covered with a part of each of the memory gate electrode material and the second gate dielectric film material, heat treatment is performed to the semiconductor substrate to form a third gate dielectric film on the semiconductor substrate located in the peripheral circuit forming region. Thereafter, a memory gate electrode and a second gate dielectric film are formed.

Flash memory cell structure with step-shaped floating gate

The present disclosure relates to a flash memory cell that includes a substrate and a floating gate structure over the substrate. The floating gate structure includes a first portion having a first top surface and a first thickness. The floating gate structure also includes a second portion having a second top surface and a second thickness that is different from the first thickness. The floating gate structure further includes a sidewall surface connecting the first and second top surfaces, and an angle between the first top surface and the sidewall surface of the floating gate structure is an obtuse angle. The flash memory cell also includes a control gate structure over the first and second portions of the floating gate structure.

FLASH MEMORY CONTAINING AIR GAPS

A flash memory is provided and includes a substrate including a memory cell region; a memory transistor array including memory transistors and selecting transistors in the memory cell region; a functional layer covering outer surfaces of the memory transistors and selecting transistors, as well as surfaces of the substrate between adjacent memory transistors and selecting transistors; a dielectric layer covering top surfaces of the memory transistors and selecting transistors and fills gaps between each selecting transistor and a corresponding adjacent memory transistor; and air gaps formed between adjacent memory transistors. Each selecting transistor is used for selecting one column of memory transistors in the memory transistor array. The functional layer has a roughened surface capable of absorbing water. The air gaps in the flash memory are water vapor induced air gaps.

CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY

Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

Cell boundary structure for embedded memory

Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

INTEGRATION OF SPLIT GATE FLASH MEMORY ARRAY AND LOGIC DEVICES

Cell boundary structure for embedded memory

Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THEREOF

A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. At least two semiconductor word lines, two memory cells in between the two semiconductor word lines, and a semiconductor gate in between the two memory cells are formed in the memory region. A transistor device including a dummy gate is formed in the core region, and a height of the dummy gate is larger than a height of the semiconductor word lines. A protecting layer is formed on the semiconductor word lines, the memory cells, the semiconductor gate and the transistor device. A portion of the protecting layer is removed to expose the dummy gate and followed be removing the dummy gate to form a gate trench in the transistor device. Then a metal gate is formed in the gate trench.

Integration of split gate flash memory array and logic devices

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.

With silicon-on-insulator substrate is made of the method of the embedded memory device

Non-volatile split gate memory cells with integrated high K metal control gates and method of making same

A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE

A 3D semiconductor memory device includes a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure comprising stacked electrodes, and a vertical channel structure penetrating the electrode structure. The peripheral circuit structure includes a dummy interconnection structure under the second substrate. The dummy interconnection structure includes stacked interconnection lines, and a via connecting a top surface of an uppermost one of the interconnection lines to a bottom surface of the second substrate.

Semiconductor device and manufacturing method thereof

In a method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a logic circuit formed in a peripheral area, a mask layer is formed over a substrate in the memory cell area and the peripheral area. A resist mask is formed over the peripheral area. The mask layer in the memory cell area is patterned by using the resist mask as an etching mask. The substrate is etched in the memory cell area. After etching the substrate, a memory cell structure in the memory cell area and a gate structure for the logic circuit are formed. A dielectric layer is formed to cover the memory cell structure and the gate structure. A planarization operation is performed on the dielectric layer. An upper portion of the memory cell structure is planarized during the planarization operation.

Si RECESS METHOD IN HKMG REPLACEMENT GATE TECHNOLOGY

The present disclosure relates to an integrated circuit (IC). The IC includes a substrate, which includes a periphery region having a first substrate surface and a memory cell region having a second substrate surface. The second substrate surface is recessed within the substrate relative to the first substrate surface. A high k metal gate (HKMG) transistor is disposed on the first substrate surface and includes a HKMG gate. Two neighboring flash memory cells are disposed on the second substrate surface and include a pair of flash memory cell control gates. Top surfaces of the HKMG gate and flash memory cell control gates are co-planar.

Semiconductor device and method of manufacturing the same

A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

Semiconductor device including nonvolatile memory device and logic device and manufacturing method of semiconductor device including nonvolatile memory device and logic device

A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.

Cell boundary structure for embedded memory

Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

Semiconductor device

A semiconductor device includes a peripheral circuit region comprising a first substrate, circuit elements on the first substrate, a first insulating layer covering the circuit elements, and a contact plug passing through the first insulating layer and disposed to be connected to the first substrate; and a memory cell region comprising a second substrate, gate electrodes on the second substrate and stacked in a vertical direction, and channel structures passing through the gate electrodes, wherein the contact plug comprises a metal silicide layer disposed to contact the first substrate and having a first thickness, a first metal nitride layer on the metal silicide layer to contact the metal silicide layer and having a second thickness, greater than the first thickness, a second metal nitride layer on the first metal nitride layer, and a conductive layer on the second metal nitride layer.

Semiconductor device with embedded non-volatile memory and method of fabricating semiconductor device

The present invention provides a semiconductor device, including a substrate with a memory region and a logic region, the substrate having a recess disposed in the memory region, a logic gate stack disposed in the logic region, and a non-volatile memory disposed in the recess. The non-volatile memory includes at least two floating gates and at least two control gates disposed on the floating gates, where each floating gate has a step-shaped bottom, and the step-shaped bottom includes a first bottom surface and a second bottom surface lower than the first bottom surface.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE

A semiconductor device includes a first insulating layer, a first bonding pad in the first insulating layer, a second insulating layer in contact with the first insulating layer, and a second bonding pad in the second insulating layer. The first bonding pad includes a first conductive layer and a first barrier layer surrounding the first conductive layer, and the second bonding pad includes a second conductive layer and a second barrier layer surrounding the second conductive layer. The second barrier layer is in contact with the first conductive layer. The second conductive layer is spaced apart from the first conductive layer. The first conductive layer includes a metal material which is different from a metal material included in the second conductive layer. The first and second barrier layers each include at least one of titanium and tantalum.

Cell boundary structure for embedded memory

Various embodiments of the present application are directed to a method of forming an integrated circuit (IC). An isolation structure is formed between a logic region and a memory region of a substrate. A dummy structure is formed on the isolation structure and defines a dummy sidewall of the dummy structure facing the logic region. A boundary sidewall spacer is formed covering the dummy structure and at least partially defines a boundary sidewall of the boundary sidewall spacer facing the logic region. A protecting dielectric layer is formed on a top surface of the boundary sidewall spacer by converting an uppermost portion of the boundary sidewall spacer to the protecting dielectric layer. The protecting dielectric layer is removed, and a logic device structure is formed on the logic region.

THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICE

A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first and second row decoder regions, a first electrode structure and a second electrode structure on the peripheral circuit structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure on the peripheral circuit structure between the first and second electrode structures and including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than ...

Semiconductor device and method of manufacturing the same

In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.

FLASH MEMORY CONTAINING AIR GAPS

A flash memory is provided and includes a substrate including a memory cell region; a memory transistor array including memory transistors and selecting transistors in the memory cell region; a functional layer covering outer surfaces of the memory transistors and selecting transistors, as well as surfaces of the substrate between adjacent memory transistors and selecting transistors; a dielectric layer covering top surfaces of the memory transistors and selecting transistors and fills gaps between each selecting transistor and a corresponding adjacent memory transistor; and air gaps formed between adjacent memory transistors. Each selecting transistor is used for selecting one column of memory transistors in the memory transistor array. The functional layer has a roughened surface capable of absorbing water. The air gaps in the flash memory are water vapor induced air gaps.

FLASH MEMORY CELL STRUCTURE WITH STEP-SHAPED FLOATING GATE

The present disclosure relates to a flash memory cell that includes a substrate and a floating gate structure over the substrate. The floating gate structure includes a first portion having a first top surface and a first thickness. The floating gate structure also includes a second portion having a second top surface and a second thickness that is different from the first thickness. The floating gate structure further includes a sidewall surface connecting the first and second top surfaces, and an angle between the first top surface and the sidewall surface of the floating gate structure is an obtuse angle. The flash memory cell also includes a control gate structure over the first and second portions of the floating gate structure.

3 D NAND word line used in the enhanced [...] and stress reduction firm nucleating layer

SEMICONDUCTOR DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND LOGIC DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND LOGIC DEVICE

A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.

Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell

A semiconductor structure includes a plurality of pairs of nonvolatile memory cells arranged in a row, an edge cell positioned adjacent to the pairs of nonvolatile memory cells, and first, second, third, and fourth gates. Each pair of nonvolatile memory cells includes first and second nonvolatile memory cells. The first and second gates extend across the first nonvolatile memory cells, the second gate partially overlapping the first gate, and the third and fourth gates extend across the second nonvolatile memory cells, the fourth gate partially overlapping the third gate. Each of the first, second, third, and fourth gates has an end portion that is positioned in the edge cell, and the edge cell includes a protection layer that is positioned over the end portions of the first, second, third, and fourth gates and covers an end face of the second and fourth gates.

CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY

Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

Anti-deciphering contacts

A method of making an integrated circuit that is resistant to an unauthorized duplication through reverse engineering includes forming a plurality of false contacts and/or false interconnection vias in the integrated circuit. These false contacts and/or false interconnection vias are connected as true contacts and true interconnection vias by lines patterned in a metallization layer deposited over an insulating dielectric layer or multilayer through which the true contacts and/or the true interconnection vias are formed. False contacts and false vias extend in the respective dielectric layers or multilayers to a depth insufficient to reach the active areas of a semiconductor substrate for false contacts, or to a depth insufficient to reach a layer of conductive material below the dielectric layers or multilayers for interconnection vias.

Semiconductor device and method for fabricating the same

A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.

Flash memory cell structure with step-shaped floating gate

The present disclosure relates to a flash memory cell that includes a substrate and a floating gate structure over the substrate. The floating gate structure includes a first portion having a first top surface and a first thickness. The floating gate structure also includes a second portion having a second top surface and a second thickness that is different from the first thickness. The floating gate structure further includes a sidewall surface connecting the first and second top surfaces, and an angle between the first top surface and the sidewall surface of the floating gate structure is an obtuse angle. The flash memory cell also includes a control gate structure over the first and second portions of the floating gate structure.

Semiconductor memory device having composite dielectric film structure and methods of forming the same

A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.

Method of forming a device with FinFET split gate non-volatile memory cells and FinFET logic devices

A method of forming a device with a silicon substrate having upwardly extending first and second fins. A first implantation forms a first source region in the first silicon fin. A second implantation forms a first drain region in the first silicon fin, and second source and drain regions in the second silicon fin. A first channel region extends between the first source and drain regions. A second channel region extends between the second source and drain regions. A first polysilicon deposition is used to form a floating gate that wraps around a first portion of the first channel region. A second polysilicon deposition is used to form an erase gate wrapping around first source region, a word line gate wrapping around a second portion of the first channel region, and a dummy gate wrapping around the second channel region. The dummy gate is replaced with a metal gate.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film. 1. A semiconductor device including:a first ring structure disposed over a substrate; andan interlayer dielectric (ILD) layer disposed over the first ring structure, wherein: a first frame shaped poly silicon layer;', 'a first dielectric layer disposed between the first frame shaped poly silicon layer and the substrate; and', 'first sidewall spacers formed on sides of the first frame shaped poly silicon layer, and, 'the first ring structure includesthe first dielectric layer is physically separated from the ILD layer by the first sidewall spacers.2. The semiconductor device of claim 1 , further comprising a second ring structure surrounding the first ring structure claim 1 , wherein:the ILD layer is disposed over the second ring structure, a second frame shaped poly silicon layer surrounding the first frame shaped poly silicon layer;', 'a second dielectric layer disposed between the second frame shaped poly silicon layer and the substrate; and', 'second sidewall spacers formed on sides of the second frame shaped poly silicon layer, and, 'the second ring structure includesthe second dielectric layer is physically separated from the ILD layer by the second sidewall spacers.3. The semiconductor device of claim 2 , wherein the first dielectric layer and the ...

Flash memory having water vapor induced air gaps and fabricating method thereof

In some embodiments, a flash memory and a fabricating method thereof are provided. The method includes proving a substrate including multiple memory transistors and selecting transistors; forming a functional layer covering outer surfaces of the memory transistors and selecting transistors, and surfaces of the substrate between adjacent memory transistors and selecting transistors; performing a surface roughening treatment to the functional layer to provide a roughed surface of the functional layer that absorbs water; and forming a dielectric layer using a chemical vapor deposition (CVD) process, the absorbed water is evaporated from the functional layer during the CVD process to form an upward air flow that resists the deposition of the dielectric layer, such that air gaps are formed between adjacent memory transistors, and the dielectric layer covers top surfaces of the plurality of memory transistors and selecting transistors and fills gaps between each selecting transistor and corresponding ...

CELL BOUNDARY STRUCTURE FOR EMBEDDED MEMORY

Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

METHOD OF PREVENTING CHARGE LOSS FROM A FLOATING GATE

A method of preventing charge loss from a floating gate includes providing a substrate comprising a memory cell region and a logic region, wherein a floating gate is disposed in the memory cell region and a gate structure is disposed within the logic region, a first hard mask covers the floating gate and a second hard mask covers the first hard mask. A planarization process is performed to remove entirely the second hard mask and expose the first hard mask. Later, a third hard mask is formed to cover the first hard mask, the gate structure and the substrate, wherein the third hard mask prevents charges in the floating gate from flowing to the first hard mask. Finally, the third hard mask within the logic region is removed and the third hard mask remains within the memory region.

Three-dimensional memory device containing composite word lines including a metal silicide and an elemental metal and method of making thereof

Word lines for a three-dimensional memory device can be formed by forming a stack of alternating layers comprising insulating layers and sacrificial material layers and memory stack structures vertically extending therethrough. Backside recesses are formed by removing the sacrificial material layers through a backside via trench. A metal silicide layer and metal portion are formed in the backside recesses to form the word lines including a metal portion, a metal silicide layer, and optionally, a silicon-containing layer.

Semiconductor memory device having composite dielectric film structure and methods of forming the same

A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.

Semiconductor device and method of manufacturing semiconductor device

A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole.

Nonvolatile Semiconductor Memory Device Having Multi-Layered Oxide/(OXY) Nitride Film as Inter-Electrode Insulating Film and Manufacturing Method Thereof

A nonvolatile semiconductor memory device includes a first insulator, first conductor, element isolation insulator, second insulator and second conductor. The first insulator is formed on the main surface of a substrate and the first conductor is formed on the first insulator. The element isolation insulator is filled into at least part of both side surfaces of the first insulator in a gate width direction thereof and both side surfaces of the first conductor in a gate width direction thereof and is so formed that the upper surface thereof will be set with height between those of the upper and bottom surfaces of the first conductor. The second insulator includes a three-layered insulating film formed of a silicon oxide film, a silicon oxynitride film and a silicon oxide film formed on the first conductor and element isolation insulator. The second conductor is formed on the second insulator.

Patterning a gate stack of a non-volatile memory (nvm) with simultaneous etch in non-nvm area

Forming a gate stack of a non-volatile memory (NVM) over a substrate having an NVM region and non-NVM region which does not overlap the NVM region includes forming a select gate layer over the substrate in the NVM and non-NVM regions; simultaneously etching the select gate layer in the NVM and non-NVM regions; forming a charge storage layer over the substrate in the NVM and non-NVM regions; forming a control gate layer over the charge storage layer in the NVM and non-NVM regions; and simultaneously etching the charge storage layer in the NVM and the non-NVM regions. Etching the select gate layer in the NVM region results in a portion of the charge storage layer over a portion of the select gate layer and overlapping a sidewall of the select gate layer and results in a portion of the control gate layer over the portion of the charge storage layer.

EEPROM-based, data-oriented combo NVM design

A nonvolatile memory device has a combination of FLOTOX EEPROM nonvolatile memory arrays. Each FLOTOX-based nonvolatile memory array is formed of FLOTOX-based nonvolatile memory cells that include at least one floating gate tunneling oxide transistor such that a coupling ratio of the control gate to the floating gate of the floating gate tunneling oxide transistor is from approximately 60% to approximately 70% and a coupling ratio of the floating gate to the drain region of the floating gate tunneling oxide transistor is maintained as a constant of is from approximately 10% to approximately 20% and such that a channel length of the channel region is decreased such that during the programming procedure a negative programming voltage level is applied to the control gate and a moderate positive programming voltage level is applied to the drain region to prevent the moderate positive programming voltage level from exceeding a drain-to-source breakdown voltage.

Programmable Gate III-Nitride Power Transistor

A III-nitride semiconductor device which includes a charged floating gate electrode.

Methods of forming fine patterns and methods of fabricating semiconductor devices

Method of forming fine patterns and methods of fabricating semiconductor devices by which a photoresist (PR) pattern may be transferred to a medium material layer with a small thickness and a high etch selectivity with respect to a hard mask to form a medium pattern and the hard mask may be formed using the medium pattern. According to the methods, the PR pattern may have a low aspect ratio so that a pattern can be transferred using a PR layer with a small thickness without collapsing the PR pattern.

Non-volatile memory device and method of manufacturing the same

A non-volatile memory device includes a plurality of memory cells stacked along a channel protruded from a substrate, a first select transistor connected to one end of the plurality of memory cells, a first interlayer dielectric layer for being coupled between a source line and the first select transistor, and a second interlayer dielectric layer disposed between the first select transistor and the one end of the plurality of memory cells, and configured to include a first recess region.

Integrated non-volatile memory (nvm) and method therefor

A feature is formed in the NVM isolation region during the patterning and etching of an NVM device and a logic device such that the feature is of substantially equal height to the logic device and is well-defined so that it does not cause defect signals. A first conductive layer is formed over a substrate. The first conductive layer is patterned to expose at least a portion of the substrate in an NVM region and at least a portion of an isolation region. An NVM dielectric stack is formed over the first conductive layer, the exposed substrate, and the exposed isolation region, and a second conductive layer is formed over the NVM dielectric stack. The first and second conductive layers and the NVM dielectric stack are patterned to form a first gate and a second gate of an NVM cell in the NVM region and a feature over the isolation region. The feature comprises a portion of the first conductive layer, a portion of the NVM dielectric stack adjacent a first sidewall of the portion of the first conductive layer, and a portion of the second conductive layer adjacent the portion of the NVM dielectric stack.

Method of removing nanocrystals

A method for forming a semiconductor structure includes providing a semiconductor layer, forming nanocrystals over the semiconductor layer, and using a solution comprising pure water, hydrogen peroxide, and ammonium hydroxide to remove at least a portion of the nanocrystals. A ratio by volume of pure water to ammonium hydroxide of the solution may be equivalent to or less than a ratio by volume of 10:1 of pure water to ammonium hydroxide when ammonium hydroxide has a concentration of 29% ammonia by weight. The step of using the solution to remove the at least a portion of the nanocrystals may be performed at a temperature of 50 degrees Celsius or more.

Non-volatile storage system with shared bit lines connected to single selection device

A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line.

Vertical channel type non-volatile memory device and method for fabricating the same

A method for fabricating a vertical channel type non-volatile memory device including forming a source region, alternately forming a plurality of interlayer dielectric layers and a plurality of conductive layers for a gate electrode over a substrate with the source region formed therein, forming a trench exposing the source region by etching the plurality of interlayer dielectric layers and the plurality of conductive layers for a gate electrode, and siliciding the conductive layers for a gate electrode and the source region that are exposed through the trench.

Nonvolatile semiconductor memory device and method of manufacturing the same

According to one embodiment, a nonvolatile semiconductor memory device includes an element region, a gate insulating film, a first gate electrode, an intergate insulating film, a second gate electrode and an element isolation region. The gate insulating film is formed on the element region. The first gate electrode is formed on the gate insulating film. The intergate insulating film is formed on the first gate electrode and has an opening. The second gate electrode is formed on the intergate insulating film and in contact with the first gate electrode via the opening. The element isolation region encloses a laminated structure formed by the element region, the gate insulating film, and the first gate electrode. The air gap is formed between the element isolation region and side surfaces of the element region, the gate insulating film and the first gate electrode.

Semiconductor memory device including multi-layer gate structure

A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.

Floating gate flash cell device and method for partially etching silicon gate to form the same

A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques.

Flash cell with floating gate transistors formed using spacer technology

Methods for forming split gate flash cell structures provide for symmetrical cells that are immune to misalignment of the photoresist pattern when forming the control gates. Spacers are utilized to form the floating gates in the floating gate transistors used in the flash cells. The spacers may be oxide spacers used to mask a polysilicon layer that will form the floating gates or the spacers may be polysilicon spacers that will themselves form the floating gates. The inter-gate oxide of the floating gate transistors may be formed using HTO or may be deposited. Hard mask spacers are used in conjunction with the control gate photoresist patterning operation to control the size and configuration of the control gate and the channel length.

Split-gate non-volatile memory cells having improved overlap tolerance

Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer.

Non-volatile memory devices and methods of forming the same

A non-volatile may include a plurality of device isolation patterns disposed in a substrate to define an active region extending in a first direction, a gate pattern disposed on the substrate to extend in a second direction crossing the first direction, a charge storing pattern disposed between the active region and the gate pattern, a blocking dielectric layer disposed between the charge storing pattern and the gate pattern, and a tunnel dielectric layer disposed between the active region and the charge storing pattern. A center area of a top surface of the active region includes one of a rounded surface or a tip, and the center area of the top surface of the active region corresponds to an uppermost portion of the active region and the uppermost portion of the active region is disposed at a level lower than a lowermost portion of the gate pattern.

Structures and Methods of Improving Reliability of Non-Volatile Memory Devices

In one example, the memory device disclosed herein includes a gate insulation layer and a charge storage layer positioned above the gate insulation layer, wherein the charge storage layer has a first width. The device further includes a blocking insulation layer positioned above the charge storage layer and a gate electrode positioned above the blocking insulation layer, wherein the gate electrode has a second width that is greater than the first width. An illustrative method disclosed herein includes forming a gate stack for a memory device, wherein the gate stack includes a gate insulation layer, an initial charge storage layer, a blocking insulation layer and a gate electrode, and wherein the initial charge storage layer has a first width. The method further includes performing an etching process to selectively remove at least a portion of the initial charge storage layer so as to produce a charge storage layer having a second width that is less than the first width of the initial charge storage layer.

Floating gate device with oxygen scavenging element

A floating gate device is provided. A tunnel oxide layer is formed over the channel. A floating gate is formed over the tunnel oxide layer. A high-k dielectric layer is formed over the floating gate. A control gate is formed over the high-k dielectric layer. At least one of the control gate and/or the floating gate includes an oxygen scavenging element. The oxygen scavenging element is configured to decrease an oxygen density at least one of at a first interface between the control gate and the high-k dielectric layer, at a second interface between the high-k dielectric layer and the floating gate, at a third interface between the floating gate and the tunnel oxide layer, and at a fourth interface between the tunnel oxide layer and the channel responsive to annealing.

Semiconductor device and method of manufacturing semiconductor device

A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole.

Split-gate flash memory exhibiting reduced interference

A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.

Methods and apparatuses including memory cells with air gaps and other low dielectric constant materials

Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.

Semiconductor device and manufacturing method thereof

A semiconductor device has first and second conductive type transistors on a substrate. First conductive type transistor includes: a first lower gate electrode portion on the substrate, including silicon including first impurity ions; a first intervening layer on the first lower gate electrode portion, including silicon including oxygen and/or nitrogen; and a first upper gate electrode portion on the first intervening layer, the first upper gate electrode portion including silicon including the first impurity ions. Second conductive type transistor includes: a second lower gate electrode portion on the substrate, the second lower gate electrode portion including silicon including second impurity ions; a second intervening layer on the second lower gate electrode portion, the second intervening layer including silicon including oxygen and/or nitrogen; and a second upper gate electrode portion on the second intervening layer, the second upper gate electrode portion including silicon including the second impurity ions.

Non-volatile memory devices having vertical drain to gate capacitive coupling

Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate disposed vertically about a substrate, wherein the floating gate comprises a first side, a second side, and a bottom portion. A source region is coupled to a first terminal and formed adjacent to the first side of the floating gate. A drain region is coupled to a second terminal and formed adjacent to the second side of the floating gate. The non-volatile device includes a channel coupling the source region and drain region for programming and erasing operations. The drain region is capacitively coupled to the floating gate.

Method Of Programming A Split Gate Non-volatile Floating Gate Memory Cell Having A Separate Erase Gate

A non-volatile memory cell includes first and second regions and a channel region therebetween, a word line gate over a first portion of the channel region, a floating gate over another portion of the channel region and adjacent to the word line gate, a coupling gate over the floating gate, and an erase gate adjacent to the floating gate on an opposite side to the word line gate and over the second region. Programming the memory cell includes applying a first positive voltage to the word line gate, applying a voltage differential between the first and second regions, applying a second positive voltage to the coupling gate (where the voltages and the voltage differential are applied substantially at the same time), and applying a third positive voltage to the erase gate after a period of delay from the application of the first and second positive voltages and the voltage differential.

Logic and non-volatile memory (nvm) integration

A method includes forming a gate dielectric over a substrate in an NVM region and a logic region; forming a first conductive layer over the gate dielectric in the NVM region and the logic region; patterning the first conductive layer in the NVM region to form a select gate; forming a charge storage layer over the select gate in the NVM region and the first conductive layer in the logic region; forming a second conductive layer over the charge storage layer in the NVM region and the logic region; removing the second conductive layer and the charge storage layer from the logic region; patterning the first conductive layer in the logic region to form a first logic gate; and after forming the first logic gate, patterning the second conductive layer in the NVM region to form a control gate which overlaps a sidewall of the select gate.

Manufacturing method of flash memory structure with stress area

In a manufacturing method of a flash memory structure with a stress area, a better stress effect can be achieved by controlling the manufacturing process of a tunneling oxide layer formed in a gate structure and contacted with a silicon substrate, so that an L-shaped spacer (or a first stress area) and a contact etch stop layer (or a second stress area) of each L-shaped spacer are formed between two gate structures and aligned towards each other to enhance the carrier mobility of the gate structure, so as to achieve the effects of improving a read current, obtaining the required read current by using a lower read voltage, reducing the possibility of having a stress-induced leakage current, and enhancing the data preservation of the flash memory.

Method for Forming Self-Aligned Trench Contacts of Semiconductor Components and A Semiconductor Component

A method for producing a semiconductor component is described. The method includes providing a semiconductor body having a first surface and being comprised of a first semiconductor material extending to the first surface. At least one trench extends from the first surface into the semiconductor body and includes a gate electrode insulated from the semiconductor body and arranged below the first surface. The method further includes: forming a second insulation layer on the first surface with a recess that overlaps in projection onto the first surface with the conductive region; forming a mask region in the recess; etching the second insulation layer selectively to the mask region and the semiconductor body to expose the semiconductor body at the first surface; depositing a third insulation layer on the first surface; and etching the third insulation layer so that a semiconductor mesa of the semiconductor body arranged next to the a least one trench is exposed at the first surface.

Structure and method for healing tunnel dielectric of non-volatile memory cells

A semiconductor device comprises an array of memory cells. Each of the memory cells includes a tunnel dielectric, a well region including a first current electrode and a second current electrode, and a control gate. The first and second current electrodes are adjacent one side of the tunnel dielectric and the control gate is adjacent another side of the tunnel dielectric. A controller is coupled to the memory cells. The controller includes logic to determine when to perform a healing process in the tunnel dielectric of the memory cells, and to apply a first voltage to the first current electrode of the memory cells during the healing process to remove trapped electrons and holes from the tunnel dielectric.

Method of fabricating non-volatile memory device

A method of fabricating a non-volatile memory is provided. A tunneling dielectric layer and a first patterned conductive layer are sequentially formed on a substrate. A patterned inter-gate dielectric layer and a second patterned conductive layer are stacked on a first surface of the first patterned conductive layer, and a second surface of the first patterned conductive layer is exposed. The second surface is adjacent to the first surface. The substrate is covered by a passivation layer, and a first sidewall of the first patterned conductive layer is exposed. A recess is formed on the first sidewall of the first patterned conductive layer, such that the first sidewall has a sharp corner. A portion of the passivation layer on the second surface is removed, such that the sharp corner of the first patterned conductive layer is exposed.

Split-gate device and method of fabricating the same

A semiconductor device includes a substrate; a storage element disposed over the substrate in a first region; a control gate disposed over the storage element; a high-k dielectric layer disposed on the substrate in a second region adjacent the first region; and a metal select gate disposed over the high-k dielectric layer and adjacent to the storage element and the control gate.

Memory and method of operating the same

The disclosure discloses a memory and a method of operating the same. The memory includes an array of memory cells including a plurality of memory cells with a common source, wherein each of the plurality of memory cells with a common source includes two sub-memory cells, each of the sub-memory cells corresponds to a bit line, and the respective bits are electrically independent. Each of the sub-memory cells in the memory according to the disclosure corresponds to a bit line, and the respective bit lines are electrically independent, thereby effectively avoiding interference to other memory cells which will not be programmed during a program operation.

Methods of Fabricating Semiconductor Devices and Structures Thereof

Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the workpiece. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the workpiece comprising an NMOS FET of a CMOS device and a second transistor in the second region of the workpiece comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

Nonvolatile memory device and method of fabricating the same

A nonvolatile memory device includes a memory gate pattern on a substrate, and a non-memory gate pattern on the substrate, the non-memory gate pattern being spaced apart from the memory gate pattern, wherein the non-memory gate pattern includes an ohmic layer, and the memory gate pattern is provided without an ohmic layer.

Semiconductor device and method of manufacturing the same

In one embodiment, a semiconductor device includes a semiconductor substrate, isolation regions disposed in the semiconductor substrate, and device regions disposed between the isolation regions in the semiconductor substrate. The device further includes a first line disposed on the device regions and the isolation regions, a line width of the first line on the isolation regions being larger than a line width of the first line on the device regions.

Semiconductor storage device and manufacturing method for the same

According to one embodiment, a semiconductor storage device comprises a memory cell transistor including a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film and a control gate which are sequentially formed on a substrate, and a select transistor including a fourth insulating film, a first electrode layer, a fifth insulating film, a second electrode layer, a sixth insulating film and a third electrode layer which are sequentially formed on the substrate. Openings are provided in at least parts of the fifth insulating film and the sixth insulating film. The first electrode layer, the second electrode layer and the third electrode layer are electrically connected via the openings.

Floating gate flash cell device and method for partially etching silicon gate to form the same

A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques.

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device includes a semiconductor substrate, a tunnel insulating film on the semiconductor substrate, a first floating gate electrode on the tunnel insulating film, an inter-floating gate insulating film on the first floating gate electrode, a second floating gate electrode on the inter-floating gate insulating film, an inter-electrode insulating film on the second floating gate electrode, and a control gate electrode on the inter-electrode insulating film. The inter-floating gate insulating film includes a main insulating film, and a first fixed charge layer between the main insulating film and the second floating gate electrode and having negative fixed charges.

Semiconductor memory devices

A semiconductor memory device includes a substrate including a cell region and a peripheral region, word lines on the substrate of the cell region, each of the word lines including a charge storing part and a control gate electrode sequentially stacked, and a peripheral gate pattern on the substrate of the peripheral region. Each of the control gate electrode and the peripheral gate pattern includes a high-carbon semiconductor pattern and a low-carbon semiconductor pattern, the low-carbon semiconductor pattern being on the high-carbon semiconductor pattern.

Semiconductor chip and fabricating method thereof

The present disclosure provides a fabricating method of a semiconductor chip which includes the following steps. First, a substrate is provided. The substrate defines a memory unit region and a peripheral logic region. Then, a first spacer is formed around a stack structure of the memory unit region. The first space includes a first silicon oxide layer and the first silicon oxide layer directly contacts with the stack structure. After that, a silicon nitride layer is formed on both the first spacer and the peripheral logic region. Finally, the additional silicon nitride layer on the first spacer is removed but portions of the additional silicon nitride layer around gate structures in the peripheral logic region are remained.

Display device, array substrate, and thin film transistor

Embodiments of the present invention relate to a display device, an array substrate, and a thin film transistor. The thin film transistor comprises a gate, an active layer and a gate insulating layer disposed between the gate and the active layer, the active layer is an oxide semiconductor, and the gate insulating layer comprises at least one layer of inorganic insulating thin film. With the gate insulating layer of the thin film transistor, it is possible that an adverse effect on the oxide semiconductor given by hydrogen-containing groups is effectively avoided, stability of the whole TFT device is enhanced to the most extent, and yield of final products is increased.

Memory structure

A memory structure includes a substrate, a source region, a drain region, a gate insulating layer, a floating gate and a control gate. The substrate has a surface and a well extended from the surface to the interior of the substrate. The source region and the drain region are formed in the well and a channel region is formed between the source region and the drain region. The gate insulating layer is formed on the surface of the substrate between the source region and the drain region and covers the channel region. The floating gate disposed on the gate insulating layer to store a bit data. The control gate is disposed near lateral sides of the floating gate.

Semiconductor device and method of fabricating the same

A semiconductor device includes a semiconductor substrate and at least a first gate structure disposed on the semiconductor substrate. Furthermore, a spacer only disposed at a side of the first gate structure, and a material of the spacer does not comprise nitride.

Method of manufacturing semiconductor device

A semiconductor device fabrication method particularly suitable for the fabrication of a 90 nm embedded flash memory is disclosed. The method includes: forming a dielectric layer having a first thickness over a first device region and forming a dielectric layer having a second thickness different from the first thickness over a second device region, the dielectric layer having a first thickness serving as a tunnel oxide layer of a split-gate structure, the dielectric layer having a second thickness serving as a gate oxide layer of a MOS transistor. The method enables the fabrication of a MOS transistor including a gate oxide layer with a desired thickness.

Nonvolatile semiconductor memory device and method of manufacturing

According to one embodiment, a nonvolatile semiconductor memory device includes a first insulating layer on a semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The charge storage layer includes a floating gate layer on the first insulating layer, an interface insulating layer on the floating gate layer, and a charge trap layer on the interface insulating layer, and a lower end of a conduction band of the interface insulating layer is higher than a trap level of the charge trap layer and is lower than a lower end of a conduction band of the charge trap layer.

Trench shielding structure for semiconductor device and method

A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device, the method including forming a first gate electrode layer including a semiconductor material on a substrate; performing an annealing process on the first gate electrode layer; performing a dry cleaning process on a surface of the first gate electrode layer after the annealing process; and forming a second gate electrode layer on the first gate electrode layer after the dry cleaning process. 1. A method of manufacturing a semiconductor device , the method comprising:forming a first gate electrode layer including a semiconductor material on a substrate;performing an annealing process on the first gate electrode layer;performing a dry cleaning process on a surface of the first gate electrode layer after the annealing process; andforming a second gate electrode layer on the first gate electrode layer after the dry cleaning process.2. The method as claimed in claim 1 , wherein:impurities in the first gate electrode layer are segregated at a surface of the first gate electrode layer to form an impurity layer, andthe impurity layer is removed by the dry cleaning process.3. The method as claimed in claim 2 , wherein the impurities include oxygen or boron.4. The method as claimed in claim 1 , wherein the dry cleaning process is performed using a cleaning gas including a NFgas.5. The method as claimed in claim 4 , wherein:{'sub': '3', 'the cleaning gas further includes a NHgas, and'}{'sub': 3', '3, 'a volume ratio of the NFgas to the NHgas is about 8:1 to about 12:1.'}6. The method as claimed in claim 5 , wherein the dry cleaning process is performed under a pressure of about 2 Torr to about 5 Torr.7. The method as claimed in claim 5 , wherein the dry cleaning process is performed at a temperature of about 30 degrees Celsius or less.8. The method as claimed in claim 5 , wherein performing the dry cleaning process includes performing a remote plasma process.9. The method as claimed in claim 1 , further comprising performing a ...

Non-volatile programmable switch

According to one embodiment, a non-volatile programmable switch according to this embodiment includes first and second non-volatile memory transistors, and a common node that is connected to the output side terminals of the first and second non-volatile memory transistors, and a logic transistor unit that is connected to the common node. A length of a gate electrode of the first and second non-volatile memory transistors in a channel longitudinal direction is shorter than a length of the charge storage film in the channel longitudinal direction.

Method of manufacturing device having a blocking structure

A method of manufacturing a semiconductor device, and the method includes forming a stack of a work function layer, a blocking structure, and a metal cap layer sequentially on a substrate. The forming of the blocking structure includes sequentially depositing at least a metal diffusion prevention layer over the work function layer and an electrical performance enhancement layer over the metal diffusion prevention layer before forming the metal cap layer. The electrical performance enhancement layer includes a TiN layer having a Ti/N ratio greater than 1.

Flash Memory Utilizing a High-K Metal Gate

According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric o one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

Semiconductor device and method of manufacturing the same

A semiconductor device includes isolation layers formed in isolation regions defined between active regions of a semiconductor substrate, wherein each of the isolation layers includes a first air gap, word lines formed over the semiconductor substrate in a direction crossing the isolation layers, wherein each of the word lines includes a stacked structure of a tunnel insulating layer, a floating gate, a dielectric layer and a control gate, and including insulating layers between the word lines, wherein a width of the floating gate is greater than a width of each active region.

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device having patterns with different widths. The method includes etching a sacrificial pattern using a protective pattern that has a greater width and remains during an etch process of a spacer layer. Since the sacrificial pattern that has a greater width and remains under the protective pattern having a greater width is used as a pad mask pattern, a separate process of forming a pad mask pattern may not be necessary. Therefore, a method of manufacturing a semiconductor device may be simplified.

Method Of Forming A Memory Cell By Reducing Diffusion Of Dopants Under A Gate

A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.

Semiconductor device and manufacturing method of the same

According to one embodiment, a nonvolatile semiconductor storage device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge accumulation film formed on the first insulating film, a second insulating film formed on the charge accumulation film, and a control electrode formed on a second insulating film, and one of the first and the second insulating film includes a layer containing nitrogen, a layer that is formed on the layer containing nitrogen and that includes a first oxygen containing aluminum atoms and oxygen atoms, and a layer that is formed on the layer including the first oxygen and that includes a second oxygen containing silicon atoms and oxygen atoms; and a concentration of the aluminum atoms is from 1E12 atoms/cm 2 to 1E16 atoms/cm 2 .

Nonvolatile memory device

A non-volatile memory includes a channel layer to extend from a substrate in a vertical direction; a plurality of interlayer dielectric layers and a plurality of gate electrodes to be alternately stacked along the channel layer; and a memory layer to be interposed between the channel layer and each of the gate electrodes, wherein the memory layer comprises a tunnel dielectric layer to contact the channel layer, a first charge trap layer to contact the tunnel dielectric layer and formed of an insulating material, a charge storage layer to contact the first charge trap layer and formed of a semiconducting material or a conductive material, a second charge trap layer to contact the charge storage layer and formed of an insulating material, and a charge blocking layer to contact the second charge trap layer.

Semiconductor device having tungsten gate electrode and method for fabricating the same

The present invention provides a semiconductor device in which the threshold voltage of NMOS and the threshold voltage of PMOS are independently controllable, and a method for fabricating the same. The method includes: forming a gate insulating film over an NMOS region and a PMOS region of a semiconductor substrate; forming a carbon-containing tungsten over the gate insulating film formed over one of the NMOS region and the PMOS region; forming a carbon-containing tungsten nitride over the gate insulating film formed over the other one of the PMOS region or the NMOS region; forming a tungsten film over the carbon-containing tungsten and the carbon-containing tungsten nitride; post-annealing the carbon-containing tungsten and the carbon-containing tungsten nitride; and etching the tungsten film, the carbon-containing tungsten, and the carbon-containing tungsten nitride, to form a gate electrode in the NMOS region and the PMOS region

Processes for NAND Flash Memory Fabrication

Narrow word lines are formed in a NAND flash memory array using a double patterning process in which sidewall spacers define word lines. Sidewall spacers also define edges of select gates so that spacing between a select gate and the closest word line is equal to spacing between adjacent word lines.

NAND STRING CONTAINING SELF-ALIGNED CONTROL GATE SIDEWALL CLADDING

A method of making a NAND string includes forming a tunnel dielectric over a semiconductor channel, forming a charge storage layer over the tunnel dielectric, forming a blocking dielectric over the charge storage layer, and forming a control gate layer over the blocking dielectric. The method also includes patterning the control gate layer to form a plurality of control gates separated by trenches, and reacting a first material with exposed sidewalls of the plurality of control gates to form self aligned metal-first material compound sidewall spacers on the exposed sidewalls of the plurality of control gates. 15-. (canceled)6. A method of making a NAND string , comprising:forming a tunnel dielectric over a semiconductor channel;forming a charge storage layer over the tunnel dielectric,forming a blocking dielectric over the charge storage layer;forming a control gate layer over the blocking dielectric;patterning the control gate layer to form a plurality of control gates separated by trenches, wherein the step of patterning the control gate layer comprises a first etching step of etching the control gate layer and stopping the first etching step prior to reaching the semiconductor channel;reacting a first material with exposed sidewalls of the plurality of control gates to form self aligned metal-first material compound sidewall spacers on the exposed sidewalls of the plurality of control gates; anda second etching step of etching the charge storage layer after the step of forming the metal silicide sidewall spacers to extend the trenches to at least one of the tunnel dielectric and the semiconductor channel, wherein:the step of reacting the first material comprises depositing a first material layer into the trenches such that the first material layer contacts exposed metal or metal nitride sidewalls of the plurality of control gates, followed by annealing the first material layer to react the first material layer with the exposed metal or metal nitride sidewalls of ...

3-D NAND Control Gate Enhancement

Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. 1. A method of forming a NAND memory structure , the method comprising:depositing a plurality of alternating layers of a nitride material and an oxide material separated by a silicon layer;etching a memory hole through the plurality of alternating layers to form an exposed surface of the plurality of alternating layers;selectively etching laterally through the memory hole from the exposed surface a portion of the nitride material;depositing a blocking oxide layer in the memory hole to form a conformal oxide liner on the exposed surface of the plurality of alternating layers, the conformal oxide layer having a first side adjacent to the plurality of alternating layers of nitride material and oxide material, and second adjacent to the memory hole;depositing a floating gate metal into the memory hole to form a floating gate adjacent the conformal oxide liner, the floating gate material having a first side, a second side, a third side, and a fourth side, the conformal oxide layer surrounding the floating gate on the first side, the second, side, and the third side, and the fourth side facing the memory hole channel;depositing a gate oxide material into the memory hole to form a layer of gate oxide material adjacent the floating gate, the gate oxide material conformally extending along the fourth side of the floating gate material and conformally extending along the conformal blocking oxide liner adjacent the face of the first and second insulating layers facing the memory hole channel;depositing a silicon material in the memory hole to form a silicon channel ...

Semiconductor Structure and Method for Forming the Same

A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell. 1. A device comprising:a memory cell array, the memory cell array including at least one memory cell gate stack, the at least one memory cell gate stack including a first stack of first materials; anda dummy feature, the dummy feature including at least one dummy gate stack that at least partially surrounds the memory cell array, the at least one dummy gate stack including a second stack of the first materials.2. The device of claim 1 , further comprising:the first stack of first materials including a tunneling layer, a floating gate atop the tunneling layer, a blocking layer atop the floating gate, a control gate atop the blocking layer and a capping layer atop the control gate; anda sidewall spacer along a sidewall of the capping layer, the control gate and the blocking layer and wherein the floating gate extends under the sidewall spacer.3. The device of claim 1 , wherein the at least one memory cell gate stack has a first height and the at least one dummy gate stack has a second height claim 1 , the second height being equal to the first height.4. The device of claim 1 , further comprising a second dummy feature claim 1 , the second dummy feature including at least one second dummy gate stack that a least partially surrounds the dummy gate stack claim 1 , the at least one second dummy gate stack including a third stack of the first materials.5. The device of claim 1 , wherein the dummy feature encircles the memory cell array.6. The device of claim 1 , wherein the dummy feature has at least one opening communicating the memory cell array with a non-memory cell region outside of the memory cell ...

FIN-BASED NONVOLATILE MEMORY STRUCTURES, INTEGRATED CIRCUITS WITH SUCH STRUCTURES, AND METHODS FOR FABRICATING SAME

Integrated circuits, nonvolatile memory (NVM) structures, and methods for fabricating integrated circuits with NVM structures are provided. An exemplary integrated circuit includes a substrate and a dual-bit NVM structure overlying the substrate. The dual-bit NVM structure includes primary, first adjacent and second adjacent fin structures laterally extending in parallel over the substrate. The primary fin structure includes source, channel and drain regions. Each adjacent fin structure includes a program/erase gate. The dual-bit NVM structure further includes a first floating gate located between the channel region of the primary fin structure and the first adjacent fin structure and a second floating gate located between the channel region of the primary fin structure and the second adjacent fin structure. Also, the dual-bit NVM structure includes a control gate adjacent the primary fin structure. 1. An integrated circuit comprising:a substrate; and a primary fin structure, a first adjacent fin structure and a second adjacent fin structure laterally extending in parallel over the substrate, wherein the primary fin structure includes a source region, a channel region, and a drain region, wherein the first adjacent fin structure includes a first program/erase gate, and wherein the second adjacent fin structure includes a second program/erase gate;', 'a first floating gate located between the channel region of the primary fin structure and the first adjacent fin structure;', 'a second floating gate located between the channel region of the primary fin structure and the second adjacent fin structure; and', 'a control gate adjacent the primary fin structure., 'a dual-bit nonvolatile memory (NVM) structure overlying the substrate and including2. The integrated circuit of wherein the primary fin structure is located between the first adjacent fin structure and the second adjacent fin structure.3. The integrated circuit of wherein the control gate includes a first control ...

Method Of Forming Split-Gate Flash Memory Cell With Spacer Defined Floating Gate And Discretely Formed Polysilicon Gates

A method of forming a memory device that includes forming a first polysilicon layer using a first polysilicon deposition over a semiconductor substrate, forming an insulation spacer on the first polysilicon layer, and removing some of the first polysilicon layer to leave a first polysilicon block under the insulation spacer. A source region is formed in the substrate adjacent a first side surface of the first polysilicon block. A second polysilicon layer is formed using a second polysilicon deposition. The second polysilicon layer is partially removed to leave a second polysilicon block over the substrate and adjacent to a second side surface of the first polysilicon block. A third polysilicon layer is formed using a third polysilicon deposition. The third polysilicon layer is partially removed to leave a third polysilicon block over the source region. A drain region is formed in the substrate adjacent to the second polysilicon block. 1. A method of forming a memory device , comprising:forming a first polysilicon layer using a first polysilicon deposition over and insulated from a semiconductor substrate;forming an insulation spacer on the first polysilicon layer;removing some of the first polysilicon layer so as to leave a block of the first polysilicon layer under the insulation spacer, wherein the block of the first polysilicon layer has opposing first and second side surfaces;forming a source region in the substrate adjacent the first side surface;forming a second polysilicon layer using a second polysilicon deposition over the substrate;removing some of the second polysilicon layer so as to leave a block of the second polysilicon layer that is over and insulated from the substrate, and adjacent to and insulated from the second side surface;forming a third polysilicon layer using a third polysilicon deposition over the substrate;removing some of the third polysilicon layer so as to leave a block of the third polysilicon layer that is over and insulated from the ...

Method of Forming Split Gate Memory Cells

A method of forming a memory device includes forming a second insulation layer on a first conductive layer formed on a first insulation layer formed on semiconductor substrate. A trench is formed into the second insulation layer extending down and exposing a portion of the first conductive layer, which is etched or oxidized to have a concave upper surface. Two insulation spacers are formed along sidewalls of the trench, having inner surfaces facing each other and outer surfaces facing away from each other. A source region is formed in the substrate between the insulation spacers. The second insulation layer and portions of the first conductive layer are removed to form floating gates under the insulation spacers. A third insulation layer is formed on side surfaces of the floating gates. Two conductive spacers are formed along the outer surfaces. Drain regions are formed in the substrate adjacent the conductive spacers. 1. A method of forming a memory device , comprising:forming a first insulation layer on an upper surface of a semiconductor substrate;forming a first conductive layer on the first insulation layer;forming a second insulation layer on the first conductive layer;forming a trench into the second insulation layer that extends down to and exposes a portion of the first conductive layer;etching or oxidizing the exposed portion of the first conductive layer such that the exposed portion has a concave upper surface;forming first and second insulation spacers along sidewalls of the trench and over respective portions of the concave upper surface, wherein the first and second insulation spacers have inner surfaces that face each other and outer surfaces that face away from each other;forming a source region in a portion of the substrate below and between the first and second insulation spacers;removing the second insulation layer;removing portions of the first conductive layer to form a first block of the first conductive layer under the first insulation spacer ...

NON-VOLATILE MEMORY AND MANUFACTURING METHOD FOR THE SAME

The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner. 1. A non-volatile memory , comprising:a substrate;at least one shallow trench isolation structure, wherein a top surface of the shallow trench isolation structure is higher than a top surface of the substrate, and a lower portion of the shallow trench isolation structure is embedded in the substrate to define a plurality of active regions in the substrate;at least one floating gate structure, located on the substrate and comprising a first gate dielectric layer and a first conductive layer in sequence from bottom to top, wherein the first conductive layer has a first sharp portion and a second sharp portion, the first sharp portion and the second sharp portion are attached to two opposite sidewalls of the shallow trench isolation structure respectively, and tips of the first sharp portion and the second sharp portion are higher than the top surface of the shallow trench isolation structure;at least one control gate structure, located on the floating gate structure, covering a partial area of the floating gate structure, and comprising a second gate dielectric layer and a second conductive layer in sequence from bottom to top, wherein a corner formed by one side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by the control gate structure, the corner is connected between the first sharp portion and ...

PARTIALLY DISPOSED GATE LAYER INTO THE TRENCHES

In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches. 1. A system , comprising:a substrate layer having an outer surface;a plurality of trenches extending from the outer surface into the substrate layer;a plurality of active regions, each active region positioned between a different pair of consecutive trenches of the plurality of trenches;a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions; anda floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.2. The system of claim 1 , wherein the substrate layer claim 1 , in each of the plurality of active regions claim 1 , comprises at least one implant layer.3. The system of claim 1 , wherein the portions of the dielectric layer in the plurality of trenches form a plurality of shallow trench isolation regions.4. The system of claim 1 , wherein the substrate layer comprises silicon claim 1 , the floating gate layer comprises polysilicon claim 1 , and the dielectric layer comprises silicon dioxide.5. The system of claim 1 , wherein the substrate layer claim 1 , in each of the plurality of active regions claim 1 , comprises an anti-punch through layer.6. The system of claim 1 , wherein the substrate layer includes a plurality of bitcells.7. A device claim 1 , comprising:a substrate layer;first ...

SEAL METHOD TO INTEGRATE NON-VOLATILE MEMORY (NVM) INTO LOGIC OR BIPOLAR CMOS DMOS (BCD) TECHNOLOGY

Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region. 1. An integrated circuit comprising:a semiconductor substrate comprising a first device region and a second device region;an isolation structure extending into a top surface of the semiconductor substrate, wherein the isolation structure demarcates and separates the first and second device regions;a memory cell overlying the first device region;a metal-oxide-semiconductor (MOS) device overlying the second device region and comprising a gate dielectric layer; anda dummy structure overlying and directly contacting the isolation structure at a boundary of the first device region, wherein the dummy structure has a columnar profile and further has a bottom surface that is level with the gate dielectric layer of the MOS device, and wherein the dummy structure comprises a dummy seal element.2. The integrated circuit according to claim 1 , wherein the dummy seal element comprises silicon nitride claim 1 , silicon carbide claim 1 , silicon oxynitride claim 1 , or polysilicon.3. The integrated circuit according to claim 1 , ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section. 1. A semiconductor device including:a non-volatile memory cell formed in a memory cell area of a substrate;a first circuit formed in a first circuit area of the substrate; anda second circuit formed in a second circuit area of the substrate,wherein a first device forming surface of the substrate in the first circuit area is located at a lower level than a second device forming surface of the substrate in the second circuit area as viewed in cross section.2. The semiconductor device of claim 1 , wherein:the first circuit includes a first field effect transistor (FET) having a first gate dielectric layer,the second circuit includes a second FET having a second gate dielectric layer, anda thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer.3. The semiconductor device of claim 1 , wherein an operational voltage of the first circuit is higher than an operational voltage of the second circuit.4. The semiconductor device of claim 1 , wherein a memory cell forming surface of the substrate in the memory cell area is located at a lower level than the first device forming surface of the substrate in the first circuit area as viewed in cross section.5. The semiconductor device of claim 1 , further comprising ...

Semiconductor Constructions, Methods of Forming Vertical Memory Strings, and Methods of Forming Vertically-Stacked Structures

Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures. 1. A memory device , comprising:a stack of alternating electrically conductive levels and electrically insulative levels over a material comprising tungsten silicide;electrically insulative pillars that extends through the stack and contact an upper surface of the material comprising tungsten silicide;a channel material post between a first adjacent pair of the pillars, the channel material post extending through the material comprising tungsten silicide and having a first pair of opposing sides and a second pair of opposing sides; each side of the first pair of opposing sides being spaced from a respective one of a second adjacent pair of the pillars by a corresponding intervening region of the stack; none of the stack being present between each side of the second pair of opposing sides and a respective one of the first adjacent pair of the pillars;gate dielectric material and charge-storage material between edges of the electrically conductive levels and the channel material post.2. The memory device of claim 1 , further comprising charge blocking material ...

Split Gate Non-volatile Memory Cell Having A Floating Gate, Word Line, Erase Gate, And Method Of Manufacturing

A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate. A conductive word line gate is disposed over a second portion of the channel region. The word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. The thickness of insulation separating the word line gate from the second portion of the channel region is less than that of insulation separating the floating gate from the erase gate. 1. A memory device , comprising:a silicon semiconductor substrate;spaced apart source and drain regions formed in the silicon semiconductor substrate with a channel region there between;a conductive floating gate disposed over and insulated from a first portion of the channel region and a first portion of the source region; a first portion that is laterally adjacent to and insulated from the floating gate, and is over and insulated from the source region, and', 'a second portion that extends up and over, and is insulated from, the floating gate;, 'a conductive erase gate that includesa conductive word line gate disposed over and insulated from a second portion of the channel region, wherein the word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate;wherein a thickness of insulation separating the word line gate from the second portion of the channel region is less than a thickness of insulation separating the floating gate from the erase gate.2. The memory device of claim 1 , wherein the erase gate second portion is the only conductive gate or ...

METHOD TO IMPROVE MEMORY CELL ERASURE

A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate that includes a first source/drain region and a second source/drain region. The semiconductor structure further includes an erase gate located over the first source/drain region, and a word line and a floating gate located over the semiconductor substrate between the first and second source/drain regions. The floating gate is arranged between the word line and the erase gate. Further, the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate. A method of manufacturing the semiconductor structure using a high selectively etch recipe, such as an etch recipe comprised of primarily hydrogen bromide (HBr) and oxygen, is also provided. 1. A semiconductor structure of a split gate flash memory cell , said semiconductor structure comprising:a semiconductor substrate including a first source/drain region and a second source/drain region;an erase gate located over the first source/drain region; anda floating gate and a word line located over the semiconductor substrate between the first and second source/drain regions, wherein the floating gate is arranged between the word line and the erase gate, and wherein the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate.2. The semiconductor structure according to claim 1 , wherein the pair of protrusions extend vertically up about 20-180 Angstroms (A) from a planar interface between the protrusions and a base region of the floating gate.3. The semiconductor substrate according to claim 1 , wherein each protrusion extends between the word line and the erase gate.4. The semiconductor structure according to claim 1 , wherein the floating gate includes a base ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein each of the gate stack layers includes a top surface and two side surfaces. A conductive material layer is deposited to conformally cover the top surface and the two side surfaces of each of the gate stack layers. Then, a cap layer is deposited to conformally cover the conductive material layer. Finally, the cap layer and the conductive material layer above the top surface of each of the gate stack layers are removed to leave the cap layer adjacent to the two side surfaces of each of the gate stack layers and covering a portion of the conductive material layer. 1. A method for manufacturing a semiconductor device , comprising:forming two gate stack layers on a semiconductor substrate, wherein each of the gate stack layers comprises a top surface and two side surfaces;depositing a conductive material layer to conformally cover the top surface and the two side surfaces of each of the gate stack layers;depositing a cap layer to conformally cover the conductive material layer; andremoving the cap layer and the conductive material layer above the top surface of each of the gate stack layers to leave the cap layer adjacent to the two side surfaces of each of the gate stack layers and covering a portion of the conductive material layer.2. The method for manufacturing the semiconductor device according to claim 1 , wherein the two gate stack layers are mirror symmetric to each other.3. The method for manufacturing the semiconductor device according to claim 1 , wherein each of the gate stack layers comprises two gate layers and two dielectric layers.4. The method for manufacturing the semiconductor device according to claim 3 , wherein a material of the gate layers comprises polysilicon.5. The method for manufacturing the semiconductor device according to claim 1 , wherein each of the gate stack layers further ...

NVM MEMORY HKMG INTEGRATION TECHNOLOGY

The present disclosure relates to an integrated circuit (IC) that includes a HKMG hybrid non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a memory region having a NVM device with a pair of control gate electrodes separated from a substrate by corresponding floating gates. A pair of select gate electrodes are disposed at opposite sides of the pair of control gate electrodes. A logic region is disposed adjacent to the memory region and has a logic device with a metal gate electrode disposed over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer. The select gate electrodes or the control gate electrodes comprise metal and have bottom and sidewall surfaces covered by the high-k gate dielectric layer. 1. An integrated circuit (IC) , comprising:a memory region comprising a non-volatile memory (NVM) device having a pair of control gate electrodes separated from a substrate by corresponding floating gates, wherein a pair of select gate electrodes are disposed at opposite sides of the pair of control gate electrodes; anda logic region disposed adjacent to the memory region and comprising a logic device including a first metal gate electrode disposed over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer;wherein the select gate electrodes or the control gate electrodes comprise metal, and the metal select gate electrodes or the metal control gate electrodes have bottom and sidewall surfaces covered by the high-k gate dielectric layer;wherein the control gate electrodes and the select gate electrodes have upper surfaces coplanar with an upper surface of the first metal gate electrode.2. The IC of claim 1 , wherein the select gate electrodes are made of the same metal as the first metal gate electrode and are separated from the substrate by the high-k ...

SEMICONDUCTOR DEVICE

At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion. The transistor in a lower portion which is covered with an insulating layer is subjected to planarization treatment, whereby the gate electrode is exposed and connected to a layer functioning as source and drain electrodes of the transistor in an upper portion. 1. (canceled)2. A semiconductor device comprising a circuit , the circuit comprising: a first semiconductor layer;', 'a first gate insulating layer over the first semiconductor layer; and', 'a first gate electrode over the first gate insulating layer;, 'a first transistor comprisingan insulating layer over the first semiconductor layer; a second gate electrode;', 'a second gate insulating layer over the second gate electrode, the second gate insulating layer comprising part of the insulating layer;', 'a second semiconductor layer over the second gate insulating layer; and', 'a third gate electrode over the second semiconductor layer;, 'a second transistor comprising a first electrode; and', 'a second electrode over the first electrode,, 'a capacitor comprisingwherein the first semiconductor layer comprises silicon,wherein the second semiconductor layer comprises an oxide semiconductor,wherein the first electrode comprises silicon,wherein the second gate electrode is over and in contact with the first gate insulating layer,wherein the second electrode is electrically connected to the first ...

Split Gate Non-Volatile Memory Cells With Three-Dimensional FINFET Structure, And Method Of Making Same

A memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first of the fins, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second of the fins has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins. 1. A memory device , comprising:a semiconductor substrate having an upper surface with a plurality of upwardly extending fins, wherein each of the fins including first and second side surfaces that oppose each other and that terminate in a top surface; spaced apart source and drain regions in the first fin, with a channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the source and drain regions,', 'a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,', 'a select gate that extends along a second portion of the channel region, wherein the select gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,', 'a control gate that extends along and is insulated from the floating gate, and', 'an erase gate that extends along and is insulated from the source region;, 'a memory cell formed on a first fin of the plurality of fins, comprisinga second fin of the plurality of fins has a ...

Method Of Making Split Gate Non-Volatile Memory Cells With Three-Dimensional FINFET Structure, And Method Of Making Same

A method of forming a memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first fin, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second fin has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins. 1. A method of forming a memory device , comprising:forming a plurality of upwardly extending fins in an upper surface of a semiconductor substrate, wherein each of the fins including first and second side surfaces that oppose each other and that terminate in a top surface; forming spaced apart source and drain regions in the first fin, with a channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the source and drain regions,', 'forming a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,', 'forming a select gate that extends along a second portion of the channel region, wherein the select gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,', 'forming a control gate that extends along and is insulated from the floating gate, and', 'forming an erase gate that extends along and is insulated from the source region;, 'forming a memory cell on a first fin of the plurality ...

Split Gate Non-volatile Memory Cells And Logic Devices With FINFET Structure, And Method Of Making Same

A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region. 1. A memory device , comprising:a semiconductor substrate having an upper surface with a plurality of upwardly extending fins, wherein each of the fins includes first and second side surfaces that oppose each other and that terminate in a top surface; spaced apart source and drain regions in the first fin, with a channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the source and drain regions,', 'a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,', 'a select gate that extends along a second portion of the channel region, wherein the select gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,', 'a control gate that extends along and is insulated from the floating gate, and', 'an erase gate that extends along and is insulated from the source region;, 'a memory cell formed on a first fin of the plurality of fins, comprising spaced apart logic ...

METHOD TO IMPROVE FILL-IN WINDOW FOR EMBEDDED MEMORY

Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A sidewall spacer is disposed along a sidewall surface of the logic devices, but not disposed along a sidewall surface of the memory cell structures. Thus, the inter-layer dielectric (ILD) fill-in window between adjacent memory cell structures is enlarged, compared to the approaches where the sidewall spacer is concurrently formed in both memory region and the logic region. Thereby, voids formation would be reduced or eliminated, and device quality would be improved. 1. An integrated circuit (IC) comprising:a memory region and a logic region integrated in a substrate;a plurality of memory cell structures disposed on the memory region, wherein a memory cell structure of the plurality of memory cell structures comprises a pair of control gate electrodes respectively disposed over the substrate and a pair of select gate electrodes disposed on opposite sides of the pair of control gate electrodes;a plurality of logic devices disposed on the logic region, wherein a logic device of the plurality of logic devices comprises a logic gate electrode separated from the substrate by a logic gate dielectric;a sidewall spacer disposed along a sidewall surface of the logic gate electrode; anda contact etch stop layer (CESL) disposed along a top surface of the substrate, extending upwardly along sidewall surfaces of the pair of select gate electrodes within the memory region, and extending upwardly along a sidewall surface of the sidewall spacer with within the logic region;wherein the contact etch stop layer (CESL) is in direct contact with the sidewall surfaces of the pair of select gate electrodes and separated from the sidewall surface of the logic ...

3D SEMICONDUCTOR DEVICE AND STRUCTURE

A 3D memory device, the device including: a first vertical pillar; a second vertical pillar, where the first vertical pillar and the second vertical pillar function as a source or a drain for a plurality of overlaying horizontally-oriented memory transistors, where the plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following the same lithography step; and memory control circuits, where the memory control circuits are disposed at least partially directly underneath the plurality of overlaying horizontally-oriented memory transistors, or are disposed at least partially directly above the plurality of overlaying horizontally-oriented memory transistors. 121-. (canceled)22. A 3D memory device , the device comprising:a first vertical pillar; wherein said first vertical pillar and said second vertical pillar function as a source or a drain for a plurality of overlaying horizontally-oriented memory transistors,', 'wherein said plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following the same lithography step; and, 'a second vertical pillar,'} 'wherein said memory control circuits are disposed at least partially directly underneath said plurality of overlaying horizontally-oriented memory transistors, or are disposed at least partially directly above said plurality of overlaying horizontally-oriented memory transistors.', 'memory control circuits,'}23. The 3D memory device according to claim 22 ,wherein said plurality of overlaying horizontally-oriented memory transistors each comprise a tunneling oxide region and a charge trap region, andwherein said tunneling oxide region is thinner than 1 nm or does not exist.24. The 3D memory device according to claim 22 , further comprising: 'wherein said third vertical pillar and said second vertical pillar function as a source or a drain for a second plurality of overlaying horizontally-oriented memory transistors.', 'a third vertical ...

Method Of Making Split Gate Non-volatile Flash Memory Cell

A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region. 1. A method of forming a non-volatile memory cell comprising:providing a semiconductor substrate having a memory cell region and a logic circuit region;forming a pair of conductive floating gates disposed over and insulated from the memory cell region of the substrate;forming a first source region in the substrate between the pair of floating gates;forming a polysilicon layer over and insulated from the substrate in the memory cell region and the logic circuit region, wherein the polysilicon layer extends up and over, and is insulated from, the pair of conductive floating gates;performing a first polysilicon etch to remove portions of the polysilicon layer such that a first block of the polysilicon layer between the floating gates and over the first source region is separated from remaining portions of the polysilicon layer;forming an oxide layer over the substrate in the memory cell region and the logic circuit region;forming a first block of photoresist on the polysilicon layer in a first portion of the logic circuit region;performing an oxide etch to remove portions of the oxide layer except for at least spacers of ...

Method Of Making Split Gate Non-volatile Flash Memory Cell

A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region. 1. A method of forming a non-volatile memory cell comprising:providing a semiconductor substrate having a memory cell region and a logic circuit region;forming a pair of conductive floating gates disposed over and insulated from the memory cell region of the substrate;forming a first source region in the substrate between the pair of floating gates;forming a polysilicon layer over and insulated from the substrate in the memory cell region and the logic circuit region, wherein the polysilicon layer extends up and over, and is insulated from, the pair of conductive floating gates;performing a spin-on process to form a coating over the polysilicon layer in the memory cell and logic circuit regions; a first block of the polysilicon layer disposed over the substrate and between the pair of conductive floating gate,', 'a second block of the polysilicon layer disposed over the substrate with one of the pair of floating gates disposed between the first and second blocks of the polysilicon layer,', 'a third block of the polysilicon layer disposed over the substrate with the other of the pair of floating gates disposed between ...

METHOD FOR FABRICATING A FLASH MEMORY

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a dielectric stack is formed on the substrate, in which the dielectric stack includes a first silicon oxide layer and a first silicon nitride layer. Next, the dielectric stack is patterned, part of the first silicon nitride layer is removed to form two recesses under two ends of the first silicon nitride layer, second silicon oxide layers are formed in the two recesses, a spacer is formed on the second silicon oxide layers, and third silicon oxide layers are formed adjacent to the second silicon oxide layers. 1. A method for fabricating semiconductor device , comprising:providing a substrate;forming a dielectric stack on the substrate, wherein the dielectric stack comprises a first silicon oxide layer and a first silicon nitride layer;patterning the dielectric stack;removing part of the first silicon nitride layer for forming two recesses under two ends of the first silicon nitride layer;forming second silicon oxide layers in the two recesses;forming a spacer on the second silicon oxide layers; andforming third silicon oxide layers adjacent to the second silicon oxide layers.2. The method of claim 1 , further comprising:forming a patterned resist on the dielectric stack;using the patterned resist as mask to pattern the dielectric stack by removing part of the first silicon nitride layer;performing a dry etching process to remove the first silicon oxide layer not covered by the first silicon nitride layer;performing a wet etching process to remove part of the silicon oxide layer under the first silicon nitride layer for forming the two recesses under two ends of the first silicon nitride layer; andstripping the patterned resist.3. The method of claim 1 , further comprising performing an n-type implantation process after forming the second silicon oxide layers for forming a buried n+ region in the substrate.4. The method of claim 1 , further comprising:forming a second ...

COMPACT MEMORY CELL WITH A SHARED CONDUCTIVE WORD LINE AND METHODS OF MAKING SUCH A MEMORY CELL

An illustrative device disclosed herein includes a first memory cell comprising a first memory gate positioned above an upper surface of a semiconductor substrate and a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate. In this example, the device also includes a conductive word line structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive word line structure is shared by the first and second memory cells. 1. A device , comprising:a semiconductor substrate having an upper surface;a first memory cell comprising a first memory gate positioned above the upper surface of the semiconductor substrate and a first gate cap above the first memory gate;a first sidewall spacer positioned adjacent the first memory gate;a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate and a second gate cap above the second memory gate; anda second sidewall spacer positioned adjacent the second memory gate;a conductive word line structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive word line structure is shared by the first and second memory cells, wherein an upper surface of the conductive word line structure is above an upper surface of the first gate cap and an upper surface of the second gate cap,a first conductive select gate structure for the first memory cell, the first conductive select gate structure being positioned above the upper surface of the semiconductor substrate adjacent the first sidewall spacer; anda second conductive select gate structure for the second memory cell, the second conductive select gate structure being positioned above the upper surface of the semiconductor substrate adjacent the second sidewall spacer.2. The device of claim 1 , wherein:the first sidewall ...

MEMORY DEVICE AND METHOD FOR FORMING THE SAME

Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit. 1. A memory device , comprising:a first bottom-select-gate (BSG) structure, comprising cut slits extending vertically through the first BSG structure;a cell-layers structure on the first BSG structure; and the gate-line slits comprise a first gate-line slit between first and second regions of the plurality of regions, the first gate-line slit including gate-line sub-slits, and', 'the first BSG in the first portion of the second region is electrically connected to cell strings in the first region through an inter portion between the gate-line sub-slit and an adjacent gate-line sub-slit of the first gate-line slit.', 'the cut slits comprise a first cut-slit in the second region and connecting to a gate-line sub-slit of the first gate-line slit to define a first BSG in a first portion of the second region, wherein], 'gate-line slits extending vertically through the cell-layers structure and the first BSG structure and arranged along a lateral direction to distinguish a plurality of regions in a block of the memory device, wherein2. The memory device of ...

MEMORY DEVICE AND METHOD OF FORMING THE SAME

Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided. 1. A memory device , comprising:a plurality of word-line structures, disposed on a substrate;a plurality of cap structures, respectively disposed on the plurality of word-line structures, wherein a material of the plurality of cap structures includes a nitride, and the nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure; anda plurality of air gaps, respectively disposed between the plurality of word-line structures, wherein the plurality of air gaps are in direct contact with the plurality of word-line structures.2. The memory device according to claim 1 , wherein each word-line structure comprises:a tunneling dielectric layer;a floating gate, disposed on the tunneling dielectric layer;a control gate, disposed on the floating gate;an inter-gate dielectric layer, disposed between the floating gate and the control gate;a metal layer disposed on the control gate; anda hard mask layer, disposed on the metal layer.3. The memory device according to claim 2 , wherein one of the plurality of cap structures covers a top surface and a sidewall of the hard mask layer.4. The memory device according to claim 2 , further comprising a dielectric layer disposed on the plurality of ...

INTEGRATED CIRCUITS WITH PROGRAMMABLE MEMORY AND METHODS FOR PRODUCING THE SAME

Methods of producing integrated circuits and integrated circuits produced by those methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming first and second shallow trench isolations within a substrate, where the first and second shallow trench isolations have an initial shallow trench height. A base well is formed in the substrate, where the base well is positioned between the first and second shallow trench isolations. A gate dielectric is formed overlying the base well, and a floating gate is formed overlying the gate dielectric. An initial shallow trench height is reduced to a reduced shallow trench height shorter than the initial shallow trench height after the floating gate is formed. 1. A method of producing an integrated circuit comprising:forming a first shallow trench isolation and a second shallow trench isolation within a substrate, wherein the first shallow trench isolation comprises an initial shallow trench height;forming a base well in the substrate, wherein the base well is positioned between the first shallow trench isolation and the second shallow trench isolation;forming a gate dielectric overlying the base well;forming a floating gate overlying the gate dielectric, where the floating gate comprises a side surface, and where a portion of the side surface is covered by the first shallow trench isolation and an exposed portion of the side surface is exposed; andreducing the initial shallow trench height to a reduced shallow trench height shorter than the initial shallow trench height after forming the floating gate.2. The method of wherein reducing the initial shallow trench height comprises exposing the first shallow trench isolation to a wet etch.3. The method of wherein the exposed portion of the side surface of the floating gate is not covered by the first or second shallow trench isolation.4. The method of further comprising:forming a flash dielectric overlying the floating gate and the ...

SELECTIVE TUNGSTEN GROWTH FOR WORD LINES OF A THREE-DIMENSIONAL MEMORY DEVICE

Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced. 1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;memory stack structures extending through the alternating stack, each of the memory stack structures including a memory material layer, a tunneling dielectric, and a vertical semiconductor channel;a pair of backside trenches extending through the alternating stack and including respective backside contact via structures contacting a respective portion of the substrate;metallic liner layers laterally extending between the pair of backside trenches; andpolycrystalline aluminum oxide liners located between a respective metallic liner layer and a respective electrically conductive layer and laterally spaced from each of the pair of backside trenches by a respective lateral offset distance.2. The three-dimensional memory device of claim 1 , wherein each of the polycrystalline aluminum oxide liners is laterally spaced from each of the pair of backside trenches by a same lateral offset distance.3. The three-dimensional memory device of claim 1 , wherein the polycrystalline aluminum oxide liners are not in physical contact with any of the memory stack structures.4. The three-dimensional memory device of claim 1 , wherein each of the polycrystalline aluminum oxide ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

According to one embodiment, a nonvolatile semiconductor memory device includes a first memory cell on the first fin-type active area, and a second memory cell on the second fin-type active area. Each of widths of charge storage layers of the first and second memory cells becomes narrower upward from below. Each of inter-electrode insulating layers of the first and second memory cells has a contact portion through which both are in contact with each other. 1. (canceled)2. A nonvolatile semiconductor memory device comprising:a semiconductor substrate;first and second active areas adjacent to each other in a first direction on the semiconductor substrate;a first memory cell on the first active area, the first memory cell including a first gate insulating layer on the first active area, a first charge storage layer on the first gate insulating layer and in which a first width thereof in the first direction becomes narrower upward from below, a first insulating layer covering an upper portion of the first charge storage layer, and a control gate electrode on the first insulating layer and extending in the first direction, the first insulating layer having a first lowest edge and a first side edge; anda second memory cell on the second active area, the second memory cell including a second gate insulating layer on the second active area, a second charge storage layer on the second gate insulating layer and in which a second width thereof in the first direction becomes narrower upward from below, a second insulating layer covering an upper portion of the second charge storage layer, and the control gate electrode on the second insulating layer, the second insulating layer having a second lowest edge and a second side edge, the second insulating layer being isolated the first insulating layer,wherein a first interval between the first and second side edges in the first direction is smaller than a second interval between first and second lowest edges in the first direction. ...

Methods Of Forming A Channel Region Of A Transistor And Methods Used In Forming A Memory Array

A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

STRUCTURE AND METHOD FOR PREVENTING SILICIDE CONTAMINATION DURING THE MANUFACTURE OF MICRO-PROCESSORS WITH EMBEDDED FLASH MEMORY

A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps. 1. A method , comprising:defining a plurality of chips on a semiconductor material wafer;forming, on each of the chips defined on the semiconductor material wafer, a respective one of a plurality of microprocessor devices, each including an embedded memory;forming a monitor cell on the semiconductor material wafer, including:forming a floating gate, a control gate and corresponding dielectric layers;forming an aperture extending through the control gate of the monitor cell and exposing a portion of the floating gate of the monitor cell;forming a silicide protection layer over portions of the control gate of the monitor cell exposed by the forming an aperture; andfollowing the forming a silicide protection layer, forming a silicide contact terminal on the portion of the floating gate of the monitor cell exposed by the forming an aperture.2. The method of wherein the forming a silicide protection layer comprises forming a silicide protection layer simultaneously with performing processing steps associated with forming the plurality of microprocessor devices.3. The method of claim 1 , comprising claim 1 , following the forming a silicide contact terminal claim 1 , performing a chemical-mechanical polish of the ...

SUB-STOICHIOMETRIC METAL-OXIDE THIN FILMS

Embodiments of the present invention are directed to forming a sub-stoichiometric metal-oxide film using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor are selected. The first precursor can include a metal and a first ligand. The second precursor can include the same metal and a second ligand. A substrate can be exposed to the first precursor during a first pulse of an ALD cycle. The substrate can be exposed to the second precursor during a second pulse of the ALD cycle. The second pulse can occur directly after the first pulse without an intervening thermal oxidant. The substrate can be exposed to the thermal oxidant during a third pulse of the ALD cycle. 1. A method of depositing a sub-stoichiometric metal-oxide , the method comprising:selecting a first precursor comprising a metal and a first ligand;selecting a second precursor comprising the metal and a second ligand;exposing a substrate to the first precursor during a first pulse of an atomic layer deposition (ALD) cycle;exposing the substrate to the second precursor during a second pulse of the ALD cycle, the second pulse occurring directly after the first pulse; andexposing the substrate to an oxidant during a third pulse of the ALD cycle.2. The method of claim 1 , wherein the oxidant is a non-plasma based thermal oxidant.3. The method of claim 1 , wherein during the first pulse the metal of the first precursor chemisorbs onto a surface of the substrate.4. The method of claim 2 , wherein during the second pulse the metal of the second precursor chemisorbs onto a coated surface terminated by the first precursor ligands; and wherein the first ligand and the second ligand react during the second pulse to form one or more by-products.5. The method of further comprising off-gassing at least a portion of the one or more by-products.6. The method of claim 1 , wherein the second pulse occurs directly after the first pulse ...

Self-Aligned Source For Split-Gate Non-volatile Memory Cell

A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type. 1. A memory device , comprising:a pair of spaced apart conductive floating gates that include inner sidewalls that face each other, wherein the floating gates are disposed over and insulated from a substrate of first conductivity type;a pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, wherein each of the control gates includes opposing inner and outer sidewalls, and wherein the inner sidewalls of the control gates face each other;a pair of first spacers of insulation material extending along the inner sidewalls of the control gates and disposed over the floating gates, wherein the inner sidewalls of the floating gates are aligned with side surfaces of the pair of first spacers;a pair of second spacers of insulation material each extending along one of the first spacers and along the inner sidewall of one of the floating gates;a trench formed into the substrate having sidewalls that are aligned with side surfaces of the pair of second spacers;silicon carbon disposed in the trench; ...

Non-volatile Split Gate Memory Cells With Integrated High K Metal Gate Logic Device And Metal-Free Erase Gate, And Method Of Making Same

A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation. 1. A method of forming a memory device , comprising:providing a semiconductor substrate having a memory cell area, a core device area and an HV device area;forming spaced apart source and drain regions in the memory cell area of the substrate, with a channel region extending there between;forming a conductive floating gate disposed over and insulated from a first portion of the channel region and a portion of the source region;forming a conductive control gate disposed over and insulated from the floating gate;forming a first conductive layer in the memory cell area that at least extends over and is insulated from the source region and a second portion of the channel region;forming a first insulation layer that extends over the first conductive layer in the memory cell area, a surface portion of the substrate in the core device area and a surface portion of the substrate in the HV device area;removing the first insulation layer from the core device area; a layer of high K dielectric material, and', 'a layer of metal material on the layer of high K dielectric material;, 'forming an HKMG layer that extends over the first insulation layer in the memory cell area and the HV device area, and over the surface portion of the substrate in the core device area, wherein the HKMG layer includesforming a second conductive layer that extends over the HKMG layer in the memory cell area, the core device area and ...

SPLIT GATE MEMORY DEVICE, SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF

A split gate memory device, a semiconductor device and a manufacturing method thereof are provided. In the split gate memory device, an erasing gate is further disposed, wherein the easing gate and a control gate are respectively disposed on two sides of a floating gate. Thus, an erase operation is implemented by the erasing gate instead of the control gate. Accordingly, electric potential applied to the control gate is reduced. Therefore, hot-electron effect in channel region may be avoided, and performance degradation of the memory caused by the hot-electron effect may be avoided as well. Furthermore, as electric potential applied to the control gate is reduced, a gate oxide layer underneath the control gate may be thinner. Accordingly, manufacturing processes of the control gate and the gate oxide layer and that of the gate and the gate oxide layer of a logic transistor in a periphery circuit may be compatible. 1. A split gate memory device , comprising:a semiconductor substrate having a source region, a drain region, and a channel region located between the source region and the drain region;a first gate oxide layer located on a first portion of the source region and a first portion of the channel region;a floating gate located on the first gate oxide layer;a second gate oxide layer located on a second portion of the source region and a second portion of the channel region;a control gate located on the second gate oxide layer;an insulating layer isolating the first gate oxide layer and the floating gate away from the second gate oxide layer and the control gate;an insulating oxide layer located on the source region;an erasing gate located on the insulating oxide layer; anda tunnel insulating layer located between the erasing gate and the floating gate.2. The split gate memory device according to claim 1 , further connected with another split gate memory device which has the same structure claim 1 , components of the two split gate memory devices are in mirror ...

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode. 114-. (canceled)15. A method of manufacturing a semiconductor device having a memory cell of a non-volatile memory formed in a first region of a semiconductor substrate and a MISFET formed in a second region of the semiconductor substrate , in which the memory cell has a first gate electrode and a second gate electrode adjacent to each other formed over the semiconductor substrate , a first gate insulation film formed between the first gate electrode and the semiconductor substrate , and a second gate insulation film formed between the second gate electrode and the semiconductor substrate and having a charge accumulation portion in an interior , and the MISFET has a third gate electrode formed over the semiconductor substrate and a third gate insulation film formed between the third gate electrode and the semiconductor substrate , the method comprising the steps of:(a) providing the semiconductor substrate;(b) forming a first film for the first gate electrode and the third gate electrode over the main surface of the semiconductor substrate;(c) patterning the first film, thereby forming the first gate electrode in the first region, forming a first film pattern in the second region, and forming a first dummy gate electrode in a third region of the semiconductor substrate;(d) forming a first insulation film for the second gate insulation film over the main surface of the semiconductor substrate so as to cover the first gate electrode, the first film pattern, and the first dummy gate electrode;(e) forming a second film for the second ...

SEMICONDUCTOR DEVICE INCLUDING LINE-TYPE ACTIVE REGION AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device having a line-type active region and a method for manufacturing the same are disclosed. The semiconductor device includes an active region configured in a successive line type, at least one active gate having a first width and crossing the active region, and an isolation gate having a second width different from the first width and being formed between the active gates. The isolation gate's width and the active gate's width are different from each other to guarantee a large storage node contact region, resulting in increased device operation characteristics (write characteristics). 1. A semiconductor device comprising:an active region extending along a first direction;at least one active gate having a first width and crossing the active region; andfirst and second isolation gates having a second width different from the first width, the first and second isolation gates isolating the active region.2. The semiconductor device according to claim 1 , wherein the second width is smaller than the first width.3. The semiconductor device according to claim 1 , wherein the at least one active gate and the first and second isolation gates are buried gates.4. The semiconductor device according to claim 1 , wherein the active region is formed angled with respect to a word line or a bit line each running across the active region.515-. (canceled) The priority of Korean patent application No. 10-2010-0127224 filed on Dec. 13, 2010, the disclosure of which is hereby incorporated in its entirety by reference, is claimed.Embodiments of the present invention relate to a semiconductor device having a line-type active region, and more particularly, to a semiconductor device where the width of an isolation gate for device isolation in the line-type active region is different from the width of an active gate so as to guarantee a wide storage node contact region, thereby improving device operation characteristics (write characteristics).As is well known in the art, a ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a substrate comprising a storage region, forming stacked gates of storage transistors on the substrate; forming side walls on two sides of each stacked gate wherein the top surfaces of side walls are arranged to be lower than the top surfaces of the stacked gates; performing ion implantation in the storage region defined by the side walls; and performing an ashing process and a wet cleaning process using the side walls as protective layers of the stacked gates to remove a photoresist remaining after the ion implantation. The present disclosure further provides a semiconductor device formed according to the manufacturing method. According to the semiconductor device and the manufacturing method thereof, the problem of stacked gate collapse from the ion implantation process can be solved, thereby improving the yield. 1. A method for manufacturing a semiconductor device , comprising:providing a substrate comprising storage transistors in a storage region;forming a plurality of stacked gates for the storage transistors in the storage region on the substrate;forming side walls on two sides of each of the plurality of stacked gates, wherein a height of one of the side walls is lower than a top surface of said stacked gate;performing ion implantation in the storage region defined by the side walls; andperforming an ashing process followed by a wet cleaning process using the side walls as protective layers for the plurality of stacked gates to remove a photoresist remaining after the ion implantation.2. The manufacturing method according to claim 1 , wherein the plurality of stacked gates comprises:a floating gate film, an interlayer dielectric layer and a control gate film sequentially formed from bottom to top over the substrate, whereina top surface of one of the side walls is arranged to be higher than the interlayer dielectric layer.3 ...

SPLIT-GATE NON-VOLATILE MEMORY AND FABRICATION METHOD THEREOF

A split-gate non-volatile memory and a fabrication method thereof. The method comprises the following steps: 1) forming a plurality of shallow trench isolation structures in a semiconductor substrate; 2) forming word lines on the semiconductor substrate; 3) forming a source and a drain in the semiconductor substrate, and forming a floating gate on a sidewall of the word line on a side close to the source, a portion of the floating gate that contacts with the word lines presents as a sharp tip; 4) removing part of the word lines by adopting an etching process such that the sharp tip of the top portion of the floating gate is higher than the word lines; 5) forming a tunneling dielectric layer and an erasing gate at the top portion of the floating gate; and 6) forming a conductive plug on the drain and forming metal bit lines on the conductive plug. 1. A method for fabricating a split-gate non-volatile memory , characterized in that the method for fabricating the split-gate type non-volatile memory comprises the following steps:1) providing a semiconductor substrate and forming a plurality of shallow trench isolation structures in the semiconductor substrate, wherein the plurality of shallow trench isolation structures isolate a plurality of spaced active regions in the semiconductor substrate;2) forming a plurality of spaced word lines on the semiconductor substrate;3) forming at least one source and at least one drain in the semiconductor substrate, and forming a floating gate on a sidewall of the word lines on a side close to the source, wherein the source and the drain are respectively located on two opposite sides of the word lines, a width of the floating gate gradually decreases from a bottom portion to a top portion, such that a portion of the top portion of the floating gate that contacts with the word lines presents as a sharp tip;4) removing part of the word lines by adopting an etching process, such that the sharp tip of the top portion of the floating gate ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section. 1. A semiconductor device including:a non-volatile memory cell formed in a memory cell area of a substrate;a first circuit formed in a first circuit area of the substrate; anda second circuit formed in a second circuit area of the substrate,wherein a first device forming surface of the substrate in the first circuit area is located at a lower level than a second device forming surface of the substrate in the second circuit area as viewed in cross section.2. The semiconductor device of claim 1 , wherein:the first circuit includes a first field effect transistor (FET) having a first gate dielectric layer,the second circuit includes a second FET having a second gate dielectric layer, anda thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer.3. The semiconductor device of claim 1 , wherein an operational voltage of the first circuit is higher than an operational voltage of the second circuit.4. The semiconductor device of claim 1 , wherein a memory cell forming surface of the substrate in the memory cell area is located at a lower level than the first device forming surface of the substrate in the first circuit area as viewed in cross section.5. The semiconductor device of claim 1 , further comprising ...